WO2018182693A1

WO2018182693A1 - TEMPLATE GROWTH SURFACE FOR FIN FIELD EFFECT TRANSISTORS (FINFETs)

Info

Publication number: WO2018182693A1
Application number: PCT/US2017/025410
Authority: WO
Inventors: Willy Rachmady; Sanaz K. GARDNER; Matthew V. Metz; Gilbert Dewey; Cheng-Ying Huang; Sean T. MA; Nicholas G. MINUTILLO; Anand S. Murthy; Jack T. Kavalieros; Tahir Ghani
Original assignee: Intel Corporation
Priority date: 2017-03-31
Filing date: 2017-03-31
Publication date: 2018-10-04

Abstract

In various embodiments, the disclosure describes a fin field effect transistor (FinFET) device having a template growth surface for the growth of the channel and/or fin of the FinFET. In one embodiment, the template growth surface can include a predetermined facet or surface of a semiconductor material. For example, for the case of a semiconductor material comprising gallium arsenide, a facet having Miller indices of (111) can serve as the second template growth surface. In one embodiment, for the case of a semiconductor material comprising gallium arsenide, a second semiconductor material comprising the fin and/or channel of the FinFET can be an indium gallium arsenide (InGaAs) material.

Description

TEMPLATE GROWTH SURFACE FOR FIN FIELD EFFECT TRANSISTORS

(FINFETs)

TECHNICAL FIELD

[0001] This disclosure generally relates to transistors.

BACKGROUND

[0002] Planar transistors can be used in integrated circuits. In such circuits, the size of the individual transistors has steadily decreased over time. As the size decreases, planar transistors typically increasingly suffer from the undesirable short-channel effect, for example, "off-state" leakage current. Such currents can increase the idle power used by a device employing such planar transistors. The fin field effect transistor (FinFET) can refer to a transistor architecture that uses raised channels, called "fins," from source to drain. One characteristic of the FinFET is that the conducting channel is wrapped by a thin fin, which can form the body of the FinFET device. BRIEF DESCRIPTION OF THE FIGURES

[0003] Reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and wherein:

[0004] FIG. 1 shows a partial structure of a FinFET device, the device having a raised channel, alternatively or additionally referred to as a fin herein.

[0005] FIG. 2A shows a partial structure of a FinFET device further comprising a second template growth surface, in accordance with one or more example embodiments of the disclosure.

[0006] FIG. 2B shows a partial structure of a FinFET device further comprising a second template growth surface, in accordance with one or more example embodiments of the disclosure.

[0007] FIG. 2C shows a partial structure of a FinFET device further comprising a second template growth surface, in accordance with one or more example embodiments of the disclosure.

[0008] FIG. 3 shows a partial structure of a FinFET device in accordance with one or more example embodiments of the disclosure. [0009] FIG. 4 shows a partial structure of a FinFET device, in accordance with one or more example embodiments of the disclosure.

[0010] FIG. 5 shows a partial structure of a FinFET device in accordance with one or more example embodiments of the disclosure.

[0011] FIG. 6 shows a partial structure of a FinFET device in accordance with one or more example embodiments of the disclosure.

[0012] FIG. 7 shows a partial structure of a FinFET device in accordance with one or more example embodiments of the disclosure.

[0013] FIG. 8 shows a partial structure of a FinFET device in accordance with one or more example embodiments of the disclosure.

[0014] FIG. 9 shows an example process flow for the fabrication of a FinFET device, in accordance with example embodiments of the disclosure.

[0015] FIG. 10 shows a diagram of an example system diagram, in accordance with example embodiments of the disclosure.

DETAILED DESCRIPTION

[0016] Embodiments of the disclosure are described more fully hereinafter with reference to the accompanying drawings, in which example embodiments of the disclosure are shown. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like numbers refer to like, but not necessarily the same or identical, elements throughout.

[0017] The following embodiments are described in sufficient detail to enable at least those skilled in the art to understand and use the disclosure. It is to be understood that other embodiments would be evident based on the present disclosure and that process, mechanical, material, dimensional, process equipment, and parametric changes may be made without departing from the scope of the present disclosure.

[0018] In the following description, numerous specific details are given to provide a thorough understanding of various embodiments of the disclosure. However, it will be apparent that the disclosure may be practiced without these specific details. In order to avoid obscuring the present disclosure, some well-known system configurations and process steps may not be disclosed in full detail. Likewise, the drawings showing embodiments of the disclosure are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and may be exaggerated in the drawings. In addition, where multiple embodiments are disclosed and described as having some features in common, for clarity and ease of illustration, description, and comprehension thereof, similar and like features will ordinarily be described with like reference numerals even if the features are not identical.

[0019] The term "horizontal" as used herein may be defined as a direction parallel to a plane or surface (for example, surface of a substrate), regardless of its orientation. The term "vertical," as used herein, may refer to a direction orthogonal to the horizontal direction as just described. Terms, such as "on," "above," "below," "bottom," "top," "side" (as in "sidewall"), "higher," "lower," "upper," "over," and "under," may be referenced with respect to a horizontal plane, where the horizontal plane can include an x- y plane, a x-z plane, or a y-z plane, as the case may be. The term "processing" as used herein includes deposition of material or photoresist, patterning, exposure, development, etching, cleaning, ablating, polishing, and/or removal of the material or photoresist as required in formation of a described structure.

[0020] In various embodiments, a fin field effect transistor (FinFET) can refer to a transistor architecture that uses raised channels, referred to herein as fins, from source to drain. One characteristic of the FinFET can be that the conducting channel can be wrapped by a thin fin, which can form the body of the FinFET device. In one embodiment, the thickness of the fin (for example, measured in the direction from source to drain) can determine the effective channel length of the device. The wrap-around gate structure can provide electrical control over the channel and can reduce the leakage current other short- channel effects, such as drain-induced barrier lowering (DIBL). Such effects can otherwise make it harder for the voltage on a gate electrode to deplete the channel underneath and stop the flow of carriers through the channel, thereby turning the transistor off. By raising the channel above the surface of the wafer instead of creating the channel just below the surface, it can be possible to wrap the gate around all but one of its sides, providing greater electrostatic control over the carriers within the channel. Further, in one embodiment, nonplanar devices such as FinFETs can be more compact than planar transistors, thereby enabling higher transistor density that can translate to smaller overall sizes for microelectronic devices. [0021] In various embodiments, the disclosure describes a FinFET device having a template growth surface for the growth of the channel and/or fin of the FinFET. In one embodiment, the template growth surface can include a predetermined facet or surface of a semiconductor material. For example, for the case of a semiconductor material comprising gallium arsenide, a facet having Miller indices of (1 11) can serve as the second template growth surface. In one embodiment, for the case of a semiconductor material comprising gallium arsenide, a second semiconductor material comprising the fin and/or channel of the FinFET can be an indium gallium arsenide (InGaAs) material. Accordingly, the facet of the first semiconductor material comprising gallium arsenide having Miller indices of (1 11) can serve as a surface to minimize misfit dislocations during the formation of the second semiconductor material comprising indium gallium arsenide. Further the facet of the first semiconductor material comprising gallium arsenide having Miller indices of (1 11) can serve as a surface to increase the probability that defects, during the formation of the second semiconductor material can glide to the sidewalls of one or more trench sidewalls comprising a buffer layer (for example, buffer layer comprising a shallow trench isolation layer). As such, defects produced during the formation of the second semiconductor material comprising indium gallium arsenide can be contained substantially at the interface between the first semiconductor material comprising gallium arsenide and the second semiconductor material comprising indium gallium arsenide.

[0022] In one embodiment, the template growth surface can have a v-shape, for example, a v-shaped groove. In one embodiment, the template growth surface can have a convex shape. In another embodiment, the template growth surface can have a meniscus shape. In another embodiment, the template growth surface can have any other suitable shape which forms in the positive z-direction with respect to the plane vector pointing in the direction of the plane of the substrate. The shape (for example, v-shape) of the template growth surface can, in various embodiments, serve to change the kinetics of the semiconductor material comprising indium gallium arsenide, such that gallium atoms may no longer be pushed toward the center of the fin comprising the second semiconductor material comprising indium gallium arsenide during epitaxial growth of the second semiconductor material. In one embodiment, this change in growth kinetics of the second semiconductor material can reduce the InGaAs composition gradient across the width of the channel and/or fin comprising the second semiconductor material. [0023] FIG. 1 shows a partial structure 100 of a FinFET device, in accordance with one or more example embodiments of the disclosure. In one embodiment, the partial structure 100 of the FinFET can include a substrate 102. In one embodiment, the substrate 102 can refer to a solid (usually planar) substance onto which a layer of another substance is applied, and to which that second substance adheres. In another embodiment, the substrate 102 can include a silicon substrate. In one embodiment, the substrate 102 can include a p-doped silicon substrate. In one embodiment, the substrate 102 can include a thin slice of material such as silicon, silicon oxide, silicon dioxide, aluminum oxide, sapphire, an alloy of silicon and germanium, and/or indium phosphide (InP), and the like. In one embodiment, the substrate 102 can include a semiconductor material (for example, monocrystalline silicon, germanium, silicon germanium (SiGe), and/or a III-V materials based material (for example, gallium arsenide, GaAs), or any combination thereof.

[0024] In one embodiment, the partial structure 100 of the FinFET can include a buffer layer 104. In one embodiment, the buffer layer 104 can include any material suitable to insulate adjacent devices and prevent current leakage. In one embodiment, the buffer layer 104 can include a shallow trench isolation (STI) layer. In one embodiment, the STI layer can provide field isolation regions that isolate one fin from other fins (not shown), for example, other fins on adjacent devices. In one embodiment, the buffer layer 104 can include an oxide layer (for example, silicon dioxide), or any other electrically insulating layer. In one embodiment, the buffer layer 104 can include an interlay er dielectric (ILD), such as silicon dioxide. In one embodiment, the buffer layer 104 may include polyimide, epoxy, photodefinable materials (for example, benzocyclobutene, BCB), WPR-series materials, and/or spin-on-glass. In one embodiment, the buffer layer 104 can include a low permittivity (low-k) ILD layer. In one embodiment, low-k can refer to dielectrics having a dielectric constant (permittivity k) lower than the permittivity of silicon dioxide. In one embodiment, the thickness of the buffer layer 104 can be approximately 10 nm to approximately 300 nm, with an example thickness of approximately 30 nm to approximately 50 nm. In one embodiment, the buffer layer 104 can be deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), and/or atomic layer deposition (ALD), and the like.

[0025] In an embodiment, the buffer layer 104 can be patterned and etched to form trenches, such as trench 105, using one of the patterning and etching techniques known to one of ordinary skill in the art. In one embodiment, the trench 105 can have a depth D of approximately 50 nm to about 300 nm and a width W of approximately 5 nm to about 20 nm. In one embodiment, an aspect ratio of the trench 105 (DAV) can determine the thickness of the buffer layers deposited through that trench. In another embodiment, the higher the DAV ratio of the trench, the thicker the buffer layer 104 can be.

[0026] In one embodiment, the partial structure of the FinFET 100 can include a first semiconductor material 106. In another embodiment, the first semiconductor material 106 can include a gallium arsenide (GaAs) material. In one embodiment, the first semiconductor material 106 can be deposited through the trench 105 onto the exposed portion of substrate 102. In an embodiment, the first semiconductor material 106 can have as a lattice parameter between the lattice parameter of the substrate 102 and a second semiconductor material 108 (to be shown and described below) which will be formed thereon. Generally, a lattice constant can refer to a lattice parameter that can describe as a distance between unit cells in a crystal lattice. In one embodiment, the lattice parameter can be a measure of the structural compatibility between different materials. In another embodiment, the lattice constant of the first semiconductor material 106 can be substantially similar to the lattice constant of the fin comprising a second semiconductor material 108 later eventually formed thereon. In another embodiment, material for the first semiconductor material 106 can be selected such that the lattice constant of the first semiconductor material 106 is generally equal to the lattice constant of the second semiconductor material 108 comprising the fin in the FinFET 100.

[0027] In an embodiment, the substrate 102 can be a p-doped silicon substrate, and the first semiconductor material 106 can include a III-V material. In one embodiment, the III- V material can refer to a compound semiconductor material that comprises at least one group III element of the periodic table (for example, aluminum, gallium, and/or indium)) and at least one of group V element of the periodic table (for example, nitrogen, phosphorus, arsenic, and/or antimony). In an embodiment, the first semiconductor material 106 can include InP, GaAs, InAlAs, GaAsSb, another III-V material, or any combination thereof. In one embodiment, the first semiconductor material 106 can include black phosphorous, amorphous silicon, germanium, carbon nanotube, and the like. In one embodiment, the first semiconductor material 106 can include silicon, germanium, indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as zinc oxide (ZnO), indium gallium zinc oxide (IGZO), amorphous silicon (a-Si), amorphous germanium (a-Ge), polycrystalline germanium, polycrystalline silicon, and/or poly crystalline InGaAs, and the like. In one embodiment, the first semiconductor material 106 can have a length in the z-dimension and/or width in the x and/or y- dimensions that can depend on which technology is used to generate the transistor. In another embodiment, the first semiconductor material 106 can be approximately 20 nm to approximately 200 nm long (in the z-dimension), with example thicknesses of approximately 60 nm to approximately 80 nm (in the y- dimension). In one embodiment, the first semiconductor material 106 width can be approximately 90 nm down to approximately 5 nm (in the y- dimension). In one embodiment, the first semiconductor material 106 can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like.

[0028] In one embodiment, the partial structure 100 of the FinFET can include a first template growth surface 107. In one embodiment, the first semiconductor material 106 can be deposited through trench 105 onto the exposed portion of substrate 102, that is, onto the first template growth surface 107. In an embodiment, the first template growth surface 107 of the first semiconductor material 106 can include a predetermined facet or surface of the substrate 102. For example, a facet of the substrate 102 having Miller indices of (111) can serve as a surface to minimize misfit dislocations during the formation of the first semiconductor material 106. In one embodiment, the first template growth surface 107 can have a v-shape. In one embodiment, the template growth surface can have a convex shape. In another embodiment, the first template growth surface 107 can have a meniscus shape. In another embodiment, the first template growth surface 107 can have any other suitable shape which forms in the positive z-direction with respect to the plane vector pointing in the direction of the plane of the substrate 102.

[0029] In one embodiment, the partial structure 100 of the FinFET can include a second semiconductor material 108. In another embodiment, the second semiconductor material 108 can include an indium gallium arsenide material. In one embodiment, the second semiconductor material 108 can serve as a fin and/or a channel to the FinFET. In one embodiment, the second semiconductor material 108 can include black phosphorous, amorphous silicon, germanium, carbon nanotube, and the like. In one embodiment, the second semiconductor material 108 can include silicon, germanium, indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as zinc oxide (ZnO), indium gallium zinc oxide (IGZO), amorphous silicon (a-Si), amorphous germanium (a-Ge), polycrystalline germanium, polycrystalline silicon, and/or poly crystalline InGaAs, and the like. In one embodiment, the second semiconductor material 108 length in the z-dimension and/or width in the x and/or y- dimension can depend on which technology is used to generate the transistor. In another embodiment, the second semiconductor material 108 can be approximately 20 nm to approximately 200 nm long (in the z-dimension), with example thicknesses of approximately 60 nm to approximately 80 nm (in the y-dimension). In one embodiment, the channel width can be approximately 90 nm down to approximately 5 nm (in the y-dimension). In one embodiment, the second semiconductor material 108 can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like.

[0030] FIG. 2 A shows a partial structure 200 of a FinFET device further comprising a second template growth surface 210, in accordance with one or more example embodiments of the disclosure. In one embodiment, the second template growth surface 210 can include a predetermined facet or surface of the first semiconductor material 206. For example, for the case of a first semiconductor material 206 comprising gallium arsenide, a facet having Miller indices of (111) can serve as the second template growth surface 210. In one embodiment, for the case of a first semiconductor material 206 comprising gallium arsenide, the second semiconductor material 208 (to be discussed below) can be an indium gallium arsenide (InGaAs) material. Accordingly, the facet of the first semiconductor material 206 comprising gallium arsenide having Miller indices of (111) can serve as a surface to minimize misfit dislocations during the formation of the second semiconductor material 208 comprising indium gallium arsenide. Further the facet of the first semiconductor material 206 comprising gallium arsenide having Miller indices of (111) can serve as a surface to increase the probability that defects, during the formation of the second semiconductor material 208 comprising indium gallium arsenide, can glide to the sidewalls of the trench 205 sidewalls comprising a buffer layer 204 (for example, buffer layer 204 comprising an STI layer). As such, defects produced during the formation of the second semiconductor material 208 comprising indium gallium arsenide can be contained substantially at the interface between the first semiconductor material 206 comprising gallium arsenide and the second semiconductor material 208 comprising indium gallium arsenide.

[0031] In one embodiment, the second template growth surface 210 can have a v- shape, for example, a v-shaped groove. In one embodiment, the template growth surface can have a convex shape. In another embodiment, the second template growth surface 210 can have a meniscus shape. In another embodiment, the second template growth surface 210 can have any other suitable shape which forms in the positive z-direction with respect to the plane vector pointing in the direction of the plane of the substrate 202. The shape (for example, v-shape) of the second template growth surface 210 can, in various embodiments, serve to change the kinetics of the second semiconductor material 208 comprising indium gallium arsenide, such that gallium atoms may no longer be pushed toward the center of the fin comprising the second semiconductor material 208 comprising indium gallium arsenide during epitaxial growth of the second semiconductor material 208. In one embodiment, this change in growth kinetics of the second semiconductor material 208 can reduce the InGaAs composition gradient across the width of the channel and/or fin comprising the second semiconductor material 208.

[0032] In one embodiment, the partial structure 200 of the FinFET can include a substrate 202. In one embodiment, the substrate 202 can refer to a solid (usually planar) substance onto which a layer of another substance is applied, and to which that second substance adheres. In another embodiment, the substrate 202 can include a silicon substrate. In one embodiment, the substrate 202 can include a p-doped silicon substrate. In one embodiment, the substrate 202 can be a thin slice of material such as silicon, silicon oxide, silicon dioxide, aluminum oxide, sapphire, an alloy of silicon and germanium, and/or indium phosphide (InP), and the like. In one embodiment, the substrate 202 can include a semiconductor material (for example, monocrystalline silicon, germanium, silicon germanium, SiGe, and/or a III-V materials based material (for example, gallium arsenide, GaAs), or any combination thereof.

[0033] In one embodiment, the partial structure 200 of the FinFET can include a buffer layer 204. In one embodiment, the buffer layer 204 can include any material suitable to insulate adjacent devices and prevent current leakage. In one embodiment, the buffer layer 204 can be a STI layer. In one embodiment, the STI layer can provide field isolation regions that isolate one fin from other fins (not shown), for example, other fins on adjacent device. In one embodiment, the buffer layer 204 can include an oxide layer (for example, silicon dioxide), or any other electrically insulating layer. In one embodiment, the buffer layer 204 can include an interlayer dielectric (ILD), such as silicon dioxide. In one embodiment, the buffer layer 204 may include polyimide, epoxy, photodefinable materials (for example, benzocyclobutene, BCB), WPR-series materials, and/or spin-on-glass. In one embodiment, the buffer layer 204 can include a low permittivity (low-k) ILD layer. In one embodiment, low-k can refer to dielectrics having a dielectric constant (permittivity k) lower than the permittivity of silicon dioxide. In one embodiment, the thickness of the buffer layer 204 can be approximately 10 nm to approximately 300 nm, with an example thickness of approximately 30 nm to approximately 50 nm. In one embodiment, the buffer layer 204 can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like. In an embodiment, the buffer layer 204 can be pattemed and etched to form trenches, such as trench 205 using one of the patterning and etching techniques known to one of ordinary skill in the art. In one embodiment, the trench 205 can have a depth D of approximately about 50 nm to about 300 nm and a width W of approximately about 5 nm to about 20 nm. In one embodiment, an aspect ratio of the trench 205 (DAV) can determine the thickness of the buffer layers deposited through that trench. In another embodiment, the higher the DAV ratio of the trench, the thicker the buffer layer 204 can be.

[0034] In one embodiment, the partial structure of the FinFET 200 can include a first semiconductor material 206. In another embodiment, the first semiconductor material 206 can include a gallium arsenide material. In one embodiment, the first semiconductor material 206 can be deposited through the trench 205 onto the exposed portion of substrate 202. In an embodiment, the first semiconductor material 206 can have as a lattice parameter between the lattice parameter of the substrate 202 and a second semiconductor material 208 (to be shown and described below) which will be formed thereon. Generally, a lattice constant can refer to a lattice parameter that can describe as a distance between unit cells in a crystal lattice. In one embodiment, the lattice parameter can be a measure of the structural compatibility between different materials. In another embodiment the lattice constant of the first semiconductor material 206 can be substantially similar to the lattice constant of the fin comprising a second semiconductor material 208 later eventually formed thereon. In another embodiment, the material for the first semiconductor material 206 can be selected such that the lattice constant of the first semiconductor material 206 is generally equal to the lattice constant of the second semiconductor material 208 comprising the fin and/or channel in the FinFET 200.

[0035] In an embodiment, the substrate 202 can be a p-doped silicon substrate, and the first semiconductor material 206 can include a III-V material. In one embodiment, the III- V material can refer to a compound semiconductor material that comprises at least one group III element of the periodic table (for example, aluminum, gallium, and/or indium) and at least one of group V element of the periodic table (for example, nitrogen, phosphorus, arsenic, and/or antimony). In an embodiment, the first semiconductor material 206 can include InP, GaAs, InAlAs, GaAsSb, another III-V material, or any combination thereof. In one embodiment, the first semiconductor material 206 can include black phosphorous, amorphous silicon, germanium, carbon nanotube, and the like. In one embodiment, the first semiconductor material 206 can include silicon, germanium, indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as zinc oxide (ZnO), indium gallium zinc oxide (IGZO), amorphous silicon (a-Si), amorphous germanium (a-Ge), polycrystalline germanium, polycrystalline silicon, and/or polycrystalline InGaAs, and the like. In one embodiment, the first semiconductor material 206 can have a length in the z-dimension and/or width in the x and/or y-dimension that can depend on which technology is used to generate the transistor. In another embodiment, the first semiconductor material 206 can be approximately 20 nm to approximately 200 nm long (in the y-dimension), with example thicknesses of approximately 60 nm to approximately 80 nm long (in the y-dimension). In one embodiment, the first semiconductor material 206 can be approximately 90 nm down to approximately 5 nm (in the y-dimension). In one embodiment, the first semiconductor material 206 can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like.

[0036] In one embodiment, the partial structure 200 of the FinFET can include a first template growth surface 207. In one embodiment, the first semiconductor material 206 can be deposited through trench 205 onto the exposed portion of substrate 202, that is, onto the first template growth surface 207. In an embodiment, the first template growth surface 207 of the first semiconductor material 206 can have as a lattice parameter between the lattice parameter of the substrate 202 and a second semiconductor material 208 (described below) which will be formed thereon. In one embodiment, the lattice parameter can be a measure of the structural compatibility between different materials. In another embodiment, the lattice constant of the first semiconductor material 206 will be generally equal to the fin comprising the second semiconductor material 208 formed thereon. In another embodiment, material for the first semiconductor material 206 can be chosen such that the lattice constant of the first semiconductor material 206 is generally equal to the lattice constant of the fin comprising a second semiconductor material 208.

[0037] In one embodiment, the partial structure 200 of the FinFET can include a second semiconductor material 208. In another embodiment, the second semiconductor material 208 can include an indium gallium arsenide material. In one embodiment, the second semiconductor material 208 can include black phosphorous, amorphous silicon, germanium, carbon nanotube, and the like. In one embodiment, the second semiconductor material 208 can include silicon, germanium, indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as zinc oxide (ZnO), indium gallium zinc oxide (IGZO), amorphous silicon (a-Si), amorphous germanium (a-Ge), poly crystalline germanium, polycrystalline silicon, and/or poly crystalline InGaAs, and the like. In one embodiment, the second semiconductor material 208 length in the z-dimension and/or width in the x and/or y-dimension can depend on which technology is used to generate the transistor. In another embodiment, the second semiconductor material 208 can be approximately 20 nm to approximately 200 nm long (in the y-dimension), with example thicknesses of approximately 60 nm to approximately 80 nm long (in the y-dimension). In one embodiment, the channel width can be approximately 90 nm down to approximately 5 nm (in the y-dimension). In one embodiment, the second semiconductor material 208 can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like.

[0038] FIG. 2B shows a partial structure 201 of a FinFET device further comprising recesses 216 in the buffer layer 204 that can be generated, by removing a portion of the buffer layer 204 as shown and described in connection with FIG. 2A. In one embodiment, the recess 216 can thereby expose the portion of the second semiconductor material 208, and a portion of the first semiconductor material 206 including a second template growth surface 210. In one embodiment, the removal of the portion of the buffer layer 204 can be performed using an etching process. In one embodiment, the etching process can include, for example, a dry etch. In one embodiment, the dry etch can include, for example, a plasma-based and/or a mechanical-based etch. In one embodiment, the etching process can include, for example, a wet etch. The wet etching process can include, for example, any suitable chemicals for the removal of the portion of the buffer layer 204. For example, for a portion of the buffer layer 204 comprising an STI, an ammonium hydroxide based wet etch may be used.

[0039] In one embodiment, the partial structure 201 a second template growth surface 210, in accordance with one or more example embodiments of the disclosure. In one embodiment, the second template growth surface 210 can include a predetermined facet or surface of the first semiconductor material 206. For example, for the case of a first semiconductor material 206 comprising gallium arsenide, a facet having Miller indices of (1 11) can serve as the second template growth surface 210. In one embodiment, for the case of a first semiconductor material 206 comprising gallium arsenide, the second semiconductor material 208 (to be discussed below) can be an indium gallium arsenide (InGaAs) material. Accordingly, the facet of the first semiconductor material 206 comprising gallium arsenide having Miller indices of (1 1 1) can serve as a surface to minimize misfit dislocations during the formation of the second semiconductor material 208 comprising indium gallium arsenide. Further the facet of the first semiconductor material 206 comprising gallium arsenide having Miller indices of (11 1) can serve as a surface to increase the probability that defects, during the formation of the second semiconductor material 208 comprising indium gallium arsenide, can glide to the sidewalls of the trench 205 sidewalls comprising a buffer layer 204 (for example, buffer layer 204 comprising an STI layer). As such, defects produced during the formation of the second semiconductor material 208 comprising indium gallium arsenide can be contained substantially at the interface between the first semiconductor material 206 comprising gallium arsenide and the second semiconductor material 208 comprising indium gallium arsenide.

[0040] In one embodiment, the second template growth surface 210 can have a v- shape, for example, a v-shaped groove. In another embodiment, the second template growth surface 210 can have a meniscus shape. In another embodiment, the second template growth surface 210 can have any other suitable shape which forms in the positive z-direction with respect to the plane vector pointing in the direction of the plane of the substrate 202. The shape (for example, v-shape) of the second template growth surface 210 can, in various embodiments, serve to change the kinetics of the second semiconductor material 208 comprising indium gallium arsenide, such that gallium atoms may no longer be pushed toward the center of the fin comprising the second semiconductor material 208 comprising indium gallium arsenide during epitaxial growth of the second semiconductor material 208. In one embodiment, this change in growth kinetics of the second semiconductor material 208 can reduce the InGaAs composition gradient across the width of the channel and/or fin comprising the second semiconductor material 208.

[0041] In one embodiment, the partial structure 201 of the FinFET can include a substrate 202. In one embodiment, the substrate 202 can refer to a solid (usually planar) substance onto which a layer of another substance is applied, and to which that second substance adheres. In another embodiment, the substrate 202 can include a silicon substrate. In one embodiment, the substrate 202 can include a p-doped silicon substrate. In one embodiment, the substrate 202 can be a thin slice of material such as silicon, silicon oxide, silicon dioxide, aluminum oxide, sapphire, an alloy of silicon and germanium, and/or indium phosphide (InP), and the like. In one embodiment, the substrate 202 can include a semiconductor material (for example, monocrystalline silicon, germanium, silicon germanium, SiGe, and/or a III-V materials based material (for example, gallium arsenide, GaAs), or any combination thereof.

[0042] In one embodiment, the partial structure 201 of the FinFET can include a buffer layer 204. In one embodiment, the buffer layer 204 can include any material suitable to insulate adjacent devices and prevent current leakage. In one embodiment, the buffer layer 204 can be a STI layer. In one embodiment, the STI layer can provide field isolation regions that isolate one fin from other fins (not shown), for example, other fins on adjacent device. In one embodiment, the buffer layer 204 can include an oxide layer (for example, silicon dioxide), or any other electrically insulating layer. In one embodiment, the buffer layer 204 can include an interlay er dielectric (ILD), such as silicon dioxide. In one embodiment, the buffer layer 204 may include polyimide, epoxy, photodefinable materials (for example, benzocyclobutene, BCB), WPR-series materials, and/or spin-on-glass. In one embodiment, the buffer layer 204 can include a low permittivity (low-k) ILD layer. In one embodiment, low-k can refer to dielectrics having a dielectric constant (permittivity k) lower than the permittivity of silicon dioxide. In one embodiment, the thickness of the buffer layer 204 can be approximately 10 nm to approximately 300 nm, with an example thickness of approximately 30 nm to approximately 50 nm. In one embodiment, the buffer layer 204 can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like. In an embodiment, the buffer layer 204 can be patterned and etched to form trenches, such as trench 205 using one of the patterning and etching techniques known to one of ordinary skill in the art. In one embodiment, the trench 205 can have a depth D of approximately about 50 nm to about 300 nm and a width W of approximately about 5 nm to about 20 nm. In one embodiment, an aspect ratio of the trench 205 (DAV) can determine the thickness of the buffer layers deposited through that trench. In another embodiment, the higher the DAV ratio of the trench, the thicker the buffer layer 204 can be. [0043] In one embodiment, the partial structure of the FinFET 201 can include a first semiconductor material 206. In another embodiment, the first semiconductor material 206 can include a gallium arsenide material. In one embodiment, the first semiconductor material 206 can be deposited through the trench 205 onto the exposed portion of substrate 202. In an embodiment, the first semiconductor material 206 can have as a lattice parameter between the lattice parameter of the substrate 202 and a second semiconductor material 208 (to be shown and described below) which will be formed thereon. Generally, a lattice constant can refer to a lattice parameter that can describe as a distance between unit cells in a crystal lattice. In one embodiment, the lattice parameter can be a measure of the structural compatibility between different materials. In another embodiment the lattice constant of the first semiconductor material 206 can be substantially similar to the lattice constant of the fin comprising a second semiconductor material 208 later eventually formed thereon. In another embodiment, the material for the first semiconductor material 206 can be selected such that the lattice constant of the first semiconductor material 206 is generally equal to the lattice constant of the second semiconductor material 208 comprising the fin and/or channel in the FinFET 201.

[0044] In an embodiment, the substrate 202 can be a p-doped silicon substrate, and the first semiconductor material 206 can include a III-V material. In one embodiment, the III- V material can refer to a compound semiconductor material that comprises at least one group III element of the periodic table (for example, aluminum, gallium, and/or indium) and at least one of group V element of the periodic table (for example, nitrogen, phosphorus, arsenic, and/or antimony). In an embodiment, the first semiconductor material 206 can include InP, GaAs, InAlAs, GaAsSb, another III-V material, or any combination thereof. In one embodiment, the first semiconductor material 206 can include black phosphorous, amorphous silicon, germanium, carbon nanotube, and the like. In one embodiment, the first semiconductor material 206 can include silicon, germanium, indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as zinc oxide (ZnO), indium gallium zinc oxide (IGZO), amorphous silicon (a-Si), amorphous germanium (a-Ge), polycrystalline germanium, polycrystalline silicon, and/or polycrystalline InGaAs, and the like. In one embodiment, the first semiconductor material 206 can have a length in the z-dimension and/or width in the x and/or y-dimension that can depend on which technology is used to generate the transistor. In another embodiment, the first semiconductor material 206 can be approximately 20 nm to approximately 200 nm long (in the y-dimension), with example thicknesses of approximately 60 nm to approximately 80 nm long (in the y-dimension). In one embodiment, the first semiconductor material 206 can be approximately 90 nm down to approximately 5 nm (in the y-dimension). In one embodiment, the first semiconductor material 206 can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like.

[0045] In one embodiment, the partial structure 201 of the FinFET can include a first template growth surface 207. In one embodiment, the first semiconductor material 206 can be deposited through trench 205 onto the exposed portion of substrate 202, that is, onto the first template growth surface 207. In an embodiment, the first template growth surface 207 of the first semiconductor material 206 can have as a lattice parameter between the lattice parameter of the substrate 202 and a second semiconductor material 208 (described below) which will be formed thereon. In one embodiment, the lattice parameter can be a measure of the structural compatibility between different materials. In another embodiment, the lattice constant of the first semiconductor material 206 will be generally equal to the fin comprising the second semiconductor material 208 formed thereon. In another embodiment, material for the first semiconductor material 206 can be chosen such that the lattice constant of the first semiconductor material 206 is generally equal to the lattice constant of the fin comprising a second semiconductor material 208.

[0046] In one embodiment, the partial structure 201 of the FinFET can include a second semiconductor material 208. In another embodiment, the second semiconductor material 208 can include an indium gallium arsenide material. In one embodiment, the second semiconductor material 208 can include black phosphorous, amorphous silicon, germanium, carbon nanotube, and the like. In one embodiment, the second semiconductor material 208 can include silicon, germanium, indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as zinc oxide (ZnO), indium gallium zinc oxide (IGZO), amorphous silicon (a-Si), amorphous germanium (a-Ge), poly crystalline germanium, polycrystalline silicon, and/or poly crystalline InGaAs, and the like. In one embodiment, the second semiconductor material 208 length in the z-dimension and/or width in the x and/or y-dimension can depend on which technology is used to generate the transistor. In another embodiment, the second semiconductor material 208 can be approximately 20 nm to approximately 200 nm long (in the y-dimension), with example thicknesses of approximately 60 nm to approximately 80 nm long (in the y-dimension). In one embodiment, the channel width can be approximately 90 nm down to approximately 5 nm (in the y-dimension). In one embodiment, the second semiconductor material 208 can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like.

[0047] FIG. 2C shows a partial structure 203 of a FinFET device further comprising a gate 220 and a gate material 222 formed on the second semiconductor material 208, a portion of the first semiconductor material 206, and the buffer layer 204. In one embodiment, the gate material 222 can be deposited and/or grown on the second semiconductor material 208, a portion of the first semiconductor material 206, and the buffer layer 204. In one embodiment, the gate material 222 can include a high-K dielectric material. In another embodiment, the high-K material, for example, hafnium oxide, tantalum oxide, titanium oxide, aluminum oxide, silicon dioxide, silicon nitride and the like. In another embodiment, the gate material 222 can include silicon oxide, which may not be a high-K material. In one embodiment, an electroglass (EG) can be used as the gate material 222. In one embodiment, the gate material 222 can include hydrogenated boron nitride (HBN). In one embodiment, the gate material can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like. In one embodiment, a gate 220 can be deposited on the gate material 220. In another embodiment, the gate 220 can include a metal. In another embodiment, the gate 220 can include a transition metal. In one embodiment, the gate 220can be used to tune the threshold voltage of the device. In one embodiment, gate 220 can include titanium nitride, cobalt, tungsten and/or platinum. In one embodiment, the gate 220can be deposited using PVD, CVD, MOCVD, MBE and/or ALD, and the like.

[0048] In one embodiment, the partial structure 203 a second template growth surface 210, in accordance with one or more example embodiments of the disclosure. In one embodiment, the second template growth surface 210 can include a predetermined facet or surface of the first semiconductor material 206. For example, for the case of a first semiconductor material 206 comprising gallium arsenide, a facet having Miller indices of (111) can serve as the second template growth surface 210. In one embodiment, for the case of a first semiconductor material 206 comprising gallium arsenide, the second semiconductor material 208 (to be discussed below) can be an indium gallium arsenide (InGaAs) material. Accordingly, the facet of the first semiconductor material 206 comprising gallium arsenide having Miller indices of (111) can serve as a surface to minimize misfit dislocations during the formation of the second semiconductor material 208 comprising indium gallium arsenide. Further the facet of the first semiconductor material 206 comprising gallium arsenide having Miller indices of (11 1) can serve as a surface to increase the probability that defects, during the formation of the second semiconductor material 208 comprising indium gallium arsenide, can glide to the sidewalls of the trench 205 sidewalls comprising a buffer layer 204 (for example, buffer layer 204 comprising an STI layer). As such, defects produced during the formation of the second semiconductor material 208 comprising indium gallium arsenide can be contained substantially at the interface between the first semiconductor material 206 comprising gallium arsenide and the second semiconductor material 208 comprising indium gallium arsenide.

[0049] In one embodiment, the second template growth surface 210 can have a v- shape, for example, a v-shaped groove. In another embodiment, the second template growth surface 210 can have a meniscus shape. In another embodiment, the second template growth surface 210 can have any other suitable shape which forms in the positive z-direction with respect to the plane vector pointing in the direction of the plane of the substrate 202. The shape (for example, v-shape) of the second template growth surface 210 can, in various embodiments, serve to change the kinetics of the second semiconductor material 208 comprising indium gallium arsenide, such that gallium atoms may no longer be pushed toward the center of the fin comprising the second semiconductor material 208 comprising indium gallium arsenide during epitaxial growth of the second semiconductor material 208. In one embodiment, this change in growth kinetics of the second semiconductor material 208 can reduce the InGaAs composition gradient across the width of the channel and/or fin comprising the second semiconductor material 208.

[0050] In one embodiment, the partial structure 203 of the FinFET can include a substrate 202. In one embodiment, the substrate 202 can refer to a solid (usually planar) substance onto which a layer of another substance is applied, and to which that second substance adheres. In another embodiment, the substrate 202 can include a silicon substrate. In one embodiment, the substrate 202 can include a p-doped silicon substrate. In one embodiment, the substrate 202 can be a thin slice of material such as silicon, silicon oxide, silicon dioxide, aluminum oxide, sapphire, an alloy of silicon and germanium, and/or indium phosphide (InP), and the like. In one embodiment, the substrate 202 can include a semiconductor material (for example, monocrystalline silicon, germanium, silicon germanium, SiGe, and/or a III-V materials based material (for example, gallium arsenide, GaAs), or any combination thereof.

[0051] In one embodiment, the partial structure 203 of the FinFET can include a buffer layer 204. In one embodiment, the buffer layer 204 can include any material suitable to insulate adjacent devices and prevent current leakage. In one embodiment, the buffer layer 204 can be a STI layer. In one embodiment, the STI layer can provide field isolation regions that isolate one fin from other fins (not shown), for example, other fins on adjacent device. In one embodiment, the buffer layer 204 can include an oxide layer (for example, silicon dioxide), or any other electrically insulating layer. In one embodiment, the buffer layer 204 can include an interlay er dielectric (ILD), such as silicon dioxide. In one embodiment, the buffer layer 204 may include polyimide, epoxy, photodefinable materials (for example, benzocyclobutene, BCB), WPR-series materials, and/or spin-on-glass. In one embodiment, the buffer layer 204 can include a low permittivity (low-k) ILD layer. In one embodiment, low-k can refer to dielectrics having a dielectric constant (permittivity k) lower than the permittivity of silicon dioxide. In one embodiment, the thickness of the buffer layer 204 can be approximately 10 nm to approximately 300 nm, with an example thickness of approximately 30 nm to approximately 50 nm. In one embodiment, the buffer layer 204 can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like. In an embodiment, the buffer layer 204 can be patterned and etched to form trenches, such as trench 205 using one of the patterning and etching techniques known to one of ordinary skill in the art. In one embodiment, the trench 205 can have a depth D of approximately about 50 nm to about 300 nm and a width W of approximately about 5 nm to about 20 nm. In one embodiment, an aspect ratio of the trench 205 (DAV) can determine the thickness of the buffer layers deposited through that trench. In another embodiment, the higher the DAV ratio of the trench, the thicker the buffer layer 204 can be.

[0052] In one embodiment, the partial structure of the FinFET 203 can include a first semiconductor material 206. In another embodiment, the first semiconductor material 206 can include a gallium arsenide material. In one embodiment, the first semiconductor material 206 can be deposited through the trench 205 onto the exposed portion of substrate 202. In an embodiment, the first semiconductor material 206 can have as a lattice parameter between the lattice parameter of the substrate 202 and a second semiconductor material 208 (to be shown and described below) which will be formed thereon. Generally, a lattice constant can refer to a lattice parameter that can describe as a distance between unit cells in a crystal lattice. In one embodiment, the lattice parameter can be a measure of the structural compatibility between different materials. In another embodiment the lattice constant of the first semiconductor material 206 can be substantially similar to the lattice constant of the fin comprising a second semiconductor material 208 later eventually formed thereon. In another embodiment, the material for the first semiconductor material 206 can be selected such that the lattice constant of the first semiconductor material 206 is generally equal to the lattice constant of the second semiconductor material 208 comprising the fin and/or channel in the FinFET 203.

[0053] In an embodiment, the substrate 202 can be a p-doped silicon substrate, and the first semiconductor material 206 can include a III-V material. In one embodiment, the III- V material can refer to a compound semiconductor material that comprises at least one group III element of the periodic table (for example, aluminum, gallium, and/or indium) and at least one of group V element of the periodic table (for example, nitrogen, phosphorus, arsenic, and/or antimony). In an embodiment, the first semiconductor material 206 can include InP, GaAs, InAlAs, GaAsSb, another III-V material, or any combination thereof. In one embodiment, the first semiconductor material 206 can include black phosphorous, amorphous silicon, germanium, carbon nanotube, and the like. In one embodiment, the first semiconductor material 206 can include silicon, germanium, indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as zinc oxide (ZnO), indium gallium zinc oxide (IGZO), amorphous silicon (a-Si), amorphous germanium (a-Ge), polycrystalline germanium, polycrystalline silicon, and/or poly crystalline InGaAs, and the like. In one embodiment, the first semiconductor material 206 can have a length in the z-dimension and/or width in the x and/or y-dimension that can depend on which technology is used to generate the transistor. In another embodiment, the first semiconductor material 206 can be approximately 20 nm to approximately 200 nm long (in the y-dimension), with example thicknesses of approximately 60 nm to approximately 80 nm long (in the y-dimension). In one embodiment, the first semiconductor material 206 can be approximately 90 nm down to approximately 5 nm (in the y-dimension). In one embodiment, the first semiconductor material 206 can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like.

[0054] In one embodiment, the partial structure 203 of the FinFET can include a first template growth surface 207. In one embodiment, the first semiconductor material 206 can be deposited through trench 205 onto the exposed portion of substrate 202, that is, onto the first template growth surface 207. In an embodiment, the first template growth surface 207 of the first semiconductor material 206 can have as a lattice parameter between the lattice parameter of the substrate 202 and a second semiconductor material 208 (described below) which will be formed thereon. In one embodiment, the lattice parameter can be a measure of the structural compatibility between different materials. In another embodiment, the lattice constant of the first semiconductor material 206 will be generally equal to the fin comprising the second semiconductor material 208 formed thereon. In another embodiment, material for the first semiconductor material 206 can be chosen such that the lattice constant of the first semiconductor material 206 is generally equal to the lattice constant of the fin comprising a second semiconductor material 208.

[0055] In one embodiment, the partial structure 203 of the FinFET can include a second semiconductor material 208. In another embodiment, the second semiconductor material 208 can include an indium gallium arsenide material. In one embodiment, the second semiconductor material 208 can include black phosphorous, amorphous silicon, germanium, carbon nanotube, and the like. In one embodiment, the second semiconductor material 208 can include silicon, germanium, indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as zinc oxide (ZnO), indium gallium zinc oxide (IGZO), amorphous silicon (a-Si), amorphous germanium (a-Ge), poly crystalline germanium, polycrystalline silicon, and/or poly crystalline InGaAs, and the like. In one embodiment, the second semiconductor material 208 length in the z-dimension and/or width in the x and/or y-dimension can depend on which technology is used to generate the transistor. In another embodiment, the second semiconductor material 208 can be approximately 20 nm to approximately 200 nm long (in the y-dimension), with example thicknesses of approximately 60 nm to approximately 80 nm long (in the y-dimension). In one embodiment, the channel width can be approximately 90 nm down to approximately 5 nm (in the y-dimension). In one embodiment, the second semiconductor material 208 can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like.

[0056] FIG. 3 shows a partial structure 300 of a FinFET device in accordance with one or more example embodiments of the disclosure. In one embodiment, the partial structure 300 can include a substrate 302. In one embodiment, the substrate 302 can refer to a solid (usually planar) substance onto which a layer of another substance is applied, and to which that second substance adheres. In another embodiment, the substrate 302 can include a silicon substrate. In one embodiment, the substrate 302 can include a p-doped silicon substrate. In one embodiment, the substrate 302 can be a thin slice of material such as silicon, silicon oxide, silicon dioxide, aluminum oxide, sapphire, an alloy of silicon and germanium, and/or indium phosphide (InP), and the like. In one embodiment, the substrate 302 can include a semiconductor material (for example, monocrystalline silicon, germanium, silicon germanium, SiGe, and/or a III-V materials based material (for example, gallium arsenide, GaAs), or any combination thereof).

[0057] In one embodiment, the partial structure 300 can include a buffer layer 304. In one embodiment, the buffer layer 304 can include any material suitable to insulate adjacent devices and prevent current leakage. In one embodiment, the buffer layer 304 can be a STI layer. In one embodiment, the STI layer can provide field isolation regions that isolate one fin from other fins (not shown), for example, other fins on adjacent devices. In one embodiment, the buffer layer 304 can include an oxide layer (for example, silicon dioxide), or any other electrically insulating layer. In one embodiment, the buffer layer 304 can include an interlay er dielectric (ILD), such as silicon dioxide. In one embodiment, the buffer layer 304 may include polyimide, epoxy, photodefinable materials (for example, benzocyclobutene, BCB), WPR-series materials, and/or spin-on-glass. In one embodiment, the buffer layer 304 can include a low permittivity (low-k) ILD layer. In one embodiment, low-k can refer to dielectrics having a dielectric constant (permittivity k) lower than the permittivity of silicon dioxide. In one embodiment, the thickness of the buffer layer 304 can be approximately 10 nm to approximately 300 nm, with an example thickness of approximately 30 nm to approximately 50 nm. In one embodiment, the buffer layer 304 can be deposited using PVD, CVD, MOCVD, MBE and/or ALD, and the like. In an embodiment, the buffer layer 304 can be patterned and etched to form trenches, such as trench 305 using one of the patterning and etching techniques known to one of ordinary skill in the art. In one embodiment, the trench 305 has a depth D 50 nm to about 300 nm and a width W 5 nm to about 20 nm. In one embodiment, an aspect ratio of the trench 305 (DAV) can determine the thickness of the buffer layers deposited through that trench 305. In another embodiment, the higher the DAV ratio of the trench, the thicker the buffer layer 304 can be.

[0058] In one embodiment, the partial structure 300 can include a first semiconductor material 306. In another embodiment, the first semiconductor material 306 can include a gallium arsenide material. In another embodiment, the first semiconductor material 306 can have an overgrowth region 309 which can extend above the plane of the buffer layer 304.

[0059] In one embodiment, the first semiconductor material 306 can be deposited through the trench 305 onto the exposed portion of substrate 302. In an embodiment, the first semiconductor material 306 can have as a lattice parameter between the lattice parameter of the substrate 302 and a portion of a second semiconductor material 714 (to be shown and described in connection with FIG. 7) which will be formed thereon. Generally, a lattice constant can refer to a lattice parameter that can describe as a distance between unit cells in a crystal lattice. In one embodiment, the lattice parameter can be a measure of the structural compatibility between different materials. In another embodiment the lattice constant of the first semiconductor material 306 can be substantially similar to the lattice constant of the fin comprising a portion of a second semiconductor material 714 later eventually formed thereon. In another embodiment, material for the first semiconductor material 306 can be selected such that the lattice constant of the first semiconductor material 306 is generally equal to the lattice constant of the portion of a second semiconductor material 714 comprising the fin of the FinFET.

[0060] In an embodiment, the substrate 302 can be a p-doped silicon substrate, and the first semiconductor material 306 can include a III-V material. In one embodiment, the III- V material can refer to a compound semiconductor material that comprises at least one group III element of the periodic table (for example, aluminum, gallium, and/or indium) and at least one of group V element of the periodic table (for example, nitrogen, phosphorus, arsenic, and/or antimony). In an embodiment, the first semiconductor material 306 can include InP, GaAs, InAlAs, GaAsSb, another III-V material, or any combination thereof. In one embodiment, the first semiconductor material 306 can include black phosphorous, amorphous silicon, germanium, carbon nanotube, and the like. In one embodiment, the first semiconductor material 306 can include silicon, germanium, indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as zinc oxide (ZnO), indium gallium zinc oxide (IGZO), amorphous silicon (a-Si), amorphous germanium (a-Ge), polycrystalline germanium, polycrystalline silicon, and/or polycrystalline InGaAs, and the like. In one embodiment, the first semiconductor material 306 can have a length in the z-dimension and/or width in the x and/or y-dimensions that can depend on which technology is used to generate the transistor. In another embodiment, the first semiconductor material 306 can be approximately 20 nm to approximately 200 nm long (in the z-dimension), with example thicknesses of approximately 60 nm to approximately 80 nm (in the y-dimension). In one embodiment, the first semiconductor material 306 width can be approximately 90 nm down to approximately 5 nm (in the y- dimension). In one embodiment, the first semiconductor material 306 can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like.

[0061] In one embodiment, the partial structure 300 of the fin can include a first template growth surface 307. In one embodiment, the first semiconductor material 306 can be deposited through trench 305 onto the exposed portion of substrate 302, that is, onto the first template growth surface 307. In an embodiment, the first template growth surface 307 of the first semiconductor material 306 can include a predetermined facet or surface of the substrate 302. For example, a facet of the substrate 302 having Miller indices of (11 1) can serve as a surface to minimize misfit dislocations during the formation of the first semiconductor material 306. In one embodiment, the first template growth surface 307 can have a v-shape. For example, a v-shaped groove. In another embodiment, the first template growth surface 307 can have a meniscus shape. In another embodiment, the first template growth surface 307 can have any other suitable shape which forms in the positive z-direction with respect to the plane vector pointing in the direction of the plane of the substrate 302.

[0062] FIG. 4 shows a partial structure 400 of a FinFET device, in accordance with one or more example embodiments of the disclosure. In one embodiment, the partial structure 400 of the FinFET can include a first semiconductor material 406 after the portion of the first semiconductor material has been removed. In another embodiment, the partial structure 400 can include a recess 408 that can be generated by the removal of the portion of the first semiconductor material 406. In one embodiment, the removal of the portion of the first semiconductor material 406 can be performed using an etching process. In one embodiment, the etching process can include, for example, a dry etch. In one embodiment, the dry etch can include, for example, a plasma-based and/or a mechanical- based etch. In one embodiment, the etching process can include, for example, a wet etch. The wet etching process can include, for example, any suitable chemicals for the removal of a portion of the first semiconductor material 406. For example, for a first semiconductor material 406 comprising gallium arsenide, an ammonium hydroxide based wet etch may be used. [0063] In one embodiment, the partial structure 400 can include a substrate 402. In one embodiment, the substrate 402 can refer to a solid (usually planar) substance onto which a layer of another substance is applied, and to which that second substance adheres. In another embodiment, the substrate 402 can include a silicon substrate. In one embodiment, the substrate 402 can include a p-doped silicon substrate. In one embodiment, the substrate 402 can be a thin slice of material such as silicon, silicon oxide, silicon dioxide, aluminum oxide, sapphire, an alloy of silicon and germanium, and/or indium phosphide (InP), and the like. In one embodiment, the substrate 402 can include a semiconductor material (for example, monocrystalline silicon, germanium, silicon germanium, SiGe, and/or a III-V materials based material (for example, gallium arsenide, GaAs), or any combination thereof).

[0064] In one embodiment, the partial structure 400 can include a buffer layer 404. In one embodiment, the buffer layer 404 can include any material suitable to insulate adjacent devices and prevent current leakage. In one embodiment, the buffer layer 404 can be a STI layer. In one embodiment, the STI layer can provide field isolation regions that isolate one fin from other fins (not shown), for example, other fins on adjacent devices. In one embodiment, the buffer layer 404 can include an oxide layer (for example, silicon dioxide), or any other electrically insulating layer. In one embodiment, the buffer layer

404 can include an interlay er dielectric (ILD), such as silicon dioxide. In one embodiment, the buffer layer 404 may include polyimide, epoxy, photodefinable materials (for example, benzocyclobutene (BCB)), WPR-series materials, and/or spin-on-glass. In one embodiment, the buffer layer 404 can include a low permittivity (low-k) ILD layer. In one embodiment, low-k can refer to dielectrics having a dielectric constant (permittivity k) lower than the permittivity of silicon dioxide. In one embodiment, the thickness of the buffer layer 404 can be approximately 10 nm to approximately 300 nm, with an example thickness of approximately 30 nm to approximately 50 nm. In one embodiment, the buffer layer 404 can be deposited using PVD, CVD, MBE, MOCVD, and/or ALD, and the like. In an embodiment, the buffer layer 404 can be patterned and etched to form trenches, such as trench 405 using one of the patterning and etching techniques known to one of ordinary skill in the art. In one embodiment, the trench 405 has a depth D 50 nm to about 309 and a width W of about 5 nm to about 20 nm. In one embodiment, an aspect ratio of the trench

405 (DAV) can determine the thickness of the buffer layers deposited through that trench 405. In another embodiment, the higher the D/W ratio of the trench 405, the thicker the buffer layers can be.

[0065] In one embodiment, the partial structure 400 can include a first semiconductor material 406. In another embodiment, the first semiconductor material 406 can include a gallium arsenide material. In one embodiment, the first semiconductor material 406 can be deposited through the trench 405 onto the exposed portion of substrate 402. In an embodiment, the first semiconductor material 406 can have as a lattice parameter between the lattice parameter of the substrate 402 and a portion of a second semiconductor material 714 (to be shown and described in connection with FIG. 7) which will be formed thereon. Generally, a lattice constant can refer to a lattice parameter that can describe as a distance between unit cells in a crystal lattice. In one embodiment, the lattice parameter can be a measure of the structural compatibility between different materials. In another embodiment, the lattice constant of the first semiconductor material 406 can be substantially similar to the lattice constant of the fin comprising a portion of a second semiconductor material 714 later eventually formed thereon. In another embodiment, material for the first semiconductor material 406 can be selected such that the lattice constant of the first semiconductor material 406 is generally equal to the lattice constant of the portion of a second semiconductor material 714 comprising the fin of the FinFET.

[0066] In an embodiment, the substrate 402 can be a p-doped silicon substrate, and the first semiconductor material 406 can include a III-V material. In one embodiment, the III- V material can refer to a compound semiconductor material that comprises at least one group III element of the periodic table (for example, aluminum, gallium, and/or indium) and at least one of group V element of the periodic table (for example, nitrogen, phosphorus, arsenic, and/or antimony). In an embodiment, the first semiconductor material 406 can include InP, GaAs, InAlAs, GaAsSb, another III-V material, or any combination thereof. In one embodiment, the first semiconductor material 406 can include black phosphorous, amorphous silicon, germanium, carbon nanotube, and the like. In one embodiment, the first semiconductor material 406 can include silicon, germanium, indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as zinc oxide (ZnO), indium gallium zinc oxide (IGZO), amorphous silicon (a-Si), amorphous germanium (a-Ge), polycrystalline germanium, polycrystalline silicon, and/or poly crystalline InGaAs, and the like. In one embodiment, the first semiconductor material 406 can have a length in the z-dimension and/or width in the x and/or y- dimension that can depend on which technology is used to generate the transistor. In another embodiment, the first semiconductor material 406 can be approximately 20 nm to approximately 200 nm long (in the y-dimension), with example thicknesses of approximately 60 nm to approximately 80 nm long (in the y-dimension). In one embodiment, the first semiconductor material 406 width can be approximately 90 nm down to approximately 5 nm (in the y-dimension). In one embodiment, the first semiconductor material 406 can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like.

[0067] In one embodiment, the partial structure 400 of the fin can include a first template growth surface 407. In one embodiment, the first semiconductor material 406 can be deposited through trench 405 onto the exposed portion of substrate 402, that is, onto the first template growth surface 407. In an embodiment, the first template growth surface 407 of the first semiconductor material 406 can include a predetermined facet or surface of the substrate 402. For example, a facet of the substrate 402 having Miller indices of (11 1) can serve as a surface to minimize misfit dislocations during the formation of the first semiconductor material 406. In one embodiment, the first template growth surface 407 can have a v-shape. For example, a v-shaped groove. In another embodiment, the first template growth surface 407 can have a meniscus shape. In another embodiment, the first template growth surface 407 can have any other suitable shape which forms in the positive z-direction with respect to the plane vector pointing in the direction of the plane of the substrate 402.

[0068] FIG. 5 shows a partial structure 500 of a FinFET device in accordance with one or more example embodiments of the disclosure. In one embodiment, the partial structure 500 of the FinFET can include a second template growth surface 510. In one embodiment, the second template growth surface 510 can include a predetermined facet or surface of the first semiconductor material 506. For example, for the case of a first semiconductor material 506 comprising gallium arsenide, a facet having Miller indices of (1 11) can serve as the second template growth surface 510. In one embodiment, for the case of a first semiconductor material 506 comprising gallium arsenide, the portion of a second semiconductor material 714 (to be discussed below) can be an indium gallium arsenide (InGaAs) material. Accordingly, the facet of the first semiconductor material 506 comprising gallium arsenide having Miller indices of (1 11) can serve as a surface to minimize misfit dislocations during the formation of the portion of a second semiconductor material 714 comprising indium gallium arsenide. Further, the facet of the first semiconductor material 506 comprising gallium arsenide and having Miller indices of (1 11) can serve as a surface to increase the probability that defects, during the formation of the portion of a second semiconductor material 714 comprising indium gallium arsenide, can glide to the sidewalls of the trench 505 sidewalls comprising a buffer layer 504 (for example, buffer layer 504 comprising an STI layer). As such, the defects formed during the formation of the portion of the second semiconductor material 714 comprising indium gallium arsenide can be contained substantially at the interface between first semiconductor material 506 comprising gallium arsenide and the portion of the second semiconductor material 714.

[0069] In one embodiment, the second template growth surface 510 can have a v- shape, for example, a v-shaped groove. In another embodiment, the second template growth surface 510 can have a meniscus shape. In another embodiment, the second template growth surface 510 can have any other suitable shape which forms in the positive z-direction with respect to the plane vector pointing in the direction of the plane of the substrate 502. The shape (for example, v-shape) of the second template growth surface 510 can, in various embodiments, serve to change the kinetics of the portion of the second semiconductor material 714 comprising indium gallium arsenide, such that gallium atoms may no longer be pushed toward the center of the channel and/or fin comprising the portion of the second semiconductor material 714 comprising indium gallium arsenide during epitaxial growth of the portion of the second semiconductor material 714. In one embodiment, this can reduce the InGaAs composition gradient across the width of the fin comprising the second semiconductor material 714.

[0070] In another embodiment, the second template growth surface 510 can be generated by the removal of the portion of the first semiconductor material 506, thereby yielding a recess 508. In one embodiment, the removal of the portion of the first semiconductor material 506 can be performed using an etching process. In one embodiment, the etching process can include, for example, a dry etch. In one embodiment, the dry etch can include, for example, a plasma-based and/or a mechanical -based etch. In one embodiment, the etching process can include, for example, a wet etch. The wet etching process can include, for example, any suitable chemicals for the removal of first semiconductor material 506. For example, for a first semiconductor material 506 comprising gallium arsenide, a ammonium hydroxide based wet etch may be used. [0071] In one embodiment, the partial structure 500 can include a substrate 502. In one embodiment, the substrate 502 can refer to a solid (usually planar) substance onto which a layer of another substance is applied, and to which that second substance adheres. In another embodiment, the substrate 502 can include a silicon substrate. In one embodiment, the substrate 502 can include a p-doped silicon substrate. In one embodiment, the substrate 502 can be a thin slice of material such as silicon, silicon oxide, silicon dioxide, aluminum oxide, sapphire, an alloy of silicon and germanium, and/or indium phosphide (InP), and the like. In one embodiment, the substrate 502 can include a semiconductor material (for example, monocrystalline silicon, germanium, silicon germanium, SiGe, and/or a III-V materials based material (for example, gallium arsenide, GaAs), or any combination thereof.

[0072] In one embodiment, the partial structure 500 can include a buffer layer 504. In one embodiment, the buffer layer 504 can include any material suitable to insulate adjacent devices and prevent current leakage. In one embodiment, the buffer layer 504 can be a STI layer. In one embodiment, the STI layer can provide field isolation regions that isolate one fin from other fins (not shown), for example, other fins on adjacent devices. In one embodiment, the buffer layer 504 can include an oxide layer (for example, silicon dioxide), or any other electrically insulating layer. In one embodiment, the buffer layer 504 can include an interlay er dielectric (ILD), such as silicon dioxide. In one embodiment, the buffer layer 504 may include polyimide, epoxy, photodefinable materials (for example, benzocyclobutene, BCB), WPR-series materials, and/or spin-on-glass. In one embodiment, the buffer layer 504 can include a low permittivity (low-k) ILD layer. In one embodiment, low-k can refer to dielectrics having a dielectric constant (permittivity k) lower than the permittivity of silicon dioxide. In one embodiment, the thickness of the buffer layer 504 can be approximately 10 nm to approximately 300 nm, with an example thickness of approximately 30 nm to approximately 50 nm. In one embodiment, the buffer layer 504 can be deposited using PVD, CVD and/or ALD, and the like. In an embodiment, the buffer layer 504 can be patterned and etched to form trenches, such as trench 505 using one of the patterning and etching techniques known to one of ordinary skill in the art. In one embodiment, the trench 505 has a depth D of about 50 nm to about 300 nm and a width W of about 5 nm to about 20 nm. In one embodiment, an aspect ratio of the trench 505 (DAV) can determine the thickness of the buffer layers deposited through that trench 505. In another embodiment, the higher the D/W ratio of the trench 505, the thicker the buffer layers can be.

[0073] In one embodiment, the partial structure 500 can include a first semiconductor material 506. In another embodiment, the first semiconductor material 506 can include a gallium arsenide material. In one embodiment, the first semiconductor material 506 can be deposited through the trench 505 onto the exposed portion of substrate 502. In an embodiment, the first semiconductor material 506 can have as a lattice parameter between the lattice parameter of the substrate 502 and a second semiconductor material 714 (to be shown and described in connection with FIG. 7) which will be formed thereon. Generally, a lattice constant can refer to a lattice parameter that can describe as a distance between unit cells in a crystal lattice. In one embodiment, the lattice parameter can be a measure of the structural compatibility between different materials. In another embodiment, the lattice constant of the first semiconductor material 506 can be substantially similar to the lattice constant of the fin comprising a second semiconductor material 714 later eventually formed thereon. In another embodiment, material for the first semiconductor material 506 can be selected such that the lattice constant of the first semiconductor material 506 is generally equal to the lattice constant of the portion of the second semiconductor material 714 comprising the fin of the FinFET.

[0074] In an embodiment, the substrate 502 can be a p-doped silicon substrate, and the first semiconductor material 506 can include a III-V material. In one embodiment, the III- V material can refer to a compound semiconductor material that comprises at least one group III element of the periodic table (for example, aluminum, gallium, and/or indium)) and at least one of group V element of the periodic table (for example, nitrogen, phosphorus, arsenic, and/or antimony). In an embodiment, the first semiconductor material 506 can include InP, GaAs, InAlAs, GaAsSb, another III-V material, or any combination thereof. In one embodiment, the first semiconductor material 506 can include black phosphorous, amorphous silicon, germanium, carbon nanotube, and the like. In one embodiment, the first semiconductor material 506 can include silicon, germanium, indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as zinc oxide (ZnO), indium gallium zinc oxide (IGZO), amorphous silicon (a-Si), amorphous germanium (a-Ge), polycrystalline germanium, polycrystalline silicon, and/or poly crystalline InGaAs, and the like. In one embodiment, the first semiconductor material 506 can have a length in the z-dimension and/or width in the x and/or y- dimension that can depend on which technology is used to generate the transistor. In another embodiment, the first semiconductor material 506 can be approximately 20 nm to approximately 200 nm long (in the z-dimension), with example thicknesses of approximately 60 nm to approximately 80 nm (in the y-dimension). In one embodiment, the first semiconductor material 506 width can be approximately 90 nm down to approximately 5 nm (in the y- dimension). In one embodiment, the first semiconductor material 506 can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like.

[0075] In one embodiment, the partial structure 500 of the fin can include a first template growth surface 507. In one embodiment, the first semiconductor material 506 can be deposited through trench 505 onto the exposed portion of substrate 502, that is, onto the first template growth surface 507. In an embodiment, the first template growth surface 507 of the first semiconductor material 506 can include a predetermined facet or surface of the substrate 502. For example, a facet of the substrate 502 having Miller indices of (111) can serve as a surface to minimize misfit dislocations during the formation of the first semiconductor material 506. In one embodiment, the first template growth surface 507 can have a v-shape. For example, a v-shaped groove. In another embodiment, the first template growth surface 507 can have a meniscus shape. In another embodiment, the first template growth surface 507 can have any other suitable shape which forms in the positive z-direction with respect to the plane vector pointing in the direction of the plane of the substrate 502.

[0076] FIG. 6 shows a partial structure 600 of a FinFET device in accordance with one or more example embodiments of the disclosure. In an embodiment, the partial structure 600 of the FinFET can include a second semiconductor material 612 which can be formed in the previously shown recess 508 of FIG 5 (see relevant description above). In another embodiment, the second semiconductor material 612 can include an overgrowth region 613 of the second semiconductor material. In another embodiment, the second semiconductor material 612 can include an indium gallium arsenide material. In one embodiment, the second semiconductor material 612 can include black phosphorous, amorphous silicon, germanium, carbon nanotube, and the like. In one embodiment, the second semiconductor material 612 can include silicon, germanium, indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as zinc oxide (ZnO), indium gallium zinc oxide (IGZO), amorphous silicon (a-Si), amorphous germanium (a-Ge), polycrystalline germanium, poly crystalline silicon, and/or poly crystalline InGaAs, and the like. In one embodiment, the second semiconductor material 612 length in the z-dimension and/or width in the x and/or y-dimension can depend on which technology is used to generate the transistor. In another embodiment, the second semiconductor material 612 can be approximately 20 nm to approximately 200 nm long (in the y-dimension), with example thicknesses of approximately 60 nm to approximately 80 nm long (in the y-dimension). In one embodiment, the channel width can be approximately 90 nm down to approximately 5 nm (in the y-dimension). In one embodiment, the second semiconductor material 612 can be deposited using PVD, CVD, and/or ALD, and the like.

[0077] In one embodiment, the partial structure 600 of the FinFET can include a second template growth surface 610. In one embodiment, the second template growth surface 610 can include a predetermined facet or surface of the first semiconductor material 606. For example, for the case of a first semiconductor material 606 comprising gallium arsenide, a facet having Miller indices of (11 1) can serve as the second template growth surface 610. In one embodiment, for the case of a first semiconductor material 606 comprising gallium arsenide, the portion of the second semiconductor material 714 (to be discussed below) can be an indium gallium arsenide (InGaAs) material. Accordingly, the facet of the first semiconductor material 606 comprising gallium arsenide having Miller indices of (11 1) can serve as a surface to minimize misfit dislocations during the formation of the portion of the second semiconductor material 714 comprising indium gallium arsenide. Further, the facet of the first semiconductor material 606 comprising gallium arsenide having Miller indices of (11 1) can serve as a surface to increase the probability that defects, during the formation of the portion of the second semiconductor material 714 comprising indium gallium arsenide, can glide to the sidewalls of the trench 605 sidewalls comprising a buffer layer 604 (for example, buffer layer 604 comprising an STI layer). As such, the defects formed during the formation of the portion of the second semiconductor material 714 comprising indium gallium arsenide can be contained substantially at the interface between first semiconductor material 606 comprising gallium arsenide and the portion of the second semiconductor material 714 comprising indium gallium arsenide.

[0078] In one embodiment, the second template growth surface 610 can have a v- shape. For example, a v-shaped groove. In another embodiment, the second template growth surface 610 can have a meniscus shape. In another embodiment, the second template growth surface 610 can have any other suitable shape which forms in the positive z-direction with respect to the plane vector pointing in the direction of the plane of the substrate 602. The shape (for example, v-shape) of the second template growth surface 610 can, in various embodiments, serve to change the kinetics of the portion of the second semiconductor material 714 comprising indium gallium arsenide, such that the Ga atoms may no longer be pushed toward the center of the fin comprising the portion of the second semiconductor material 714 comprising indium gallium arsenide during epitaxial growth of the portion of the second semiconductor material 714 comprising indium gallium arsenide. In one embodiment, this can reduce the InGaAs composition gradient across the width of the fin comprising the second semiconductor material 714.

[0079] In one embodiment, the partial structure 600 can include a substrate 602. In one embodiment, the substrate 602 can refer to a solid (usually planar) substance onto which a layer of another substance is applied, and to which that second substance adheres. In another embodiment, the substrate 602 can include a silicon substrate. In one embodiment, the substrate 602 can include a p-doped silicon substrate. In one embodiment, the substrate 602 can be a thin slice of material such as silicon, silicon oxide, silicon dioxide, aluminum oxide, sapphire, an alloy of silicon and germanium, and/or indium phosphide (InP), and the like. In one embodiment, the substrate 602 can include a semiconductor material (for example, monocrystalline silicon, germanium, silicon germanium, SiGe, and/or a III-V materials based material (for example, gallium arsenide, GaAs), or any combination thereof.

[0080] In one embodiment, the partial structure 600 can include a buffer layer 604. In one embodiment, the buffer layer 604 can include any material suitable to insulate adjacent devices and prevent current leakage. In one embodiment, the buffer layer 604 can be a STI layer. In one embodiment, the STI layer can provide field isolation regions that isolate one fin from other fins (not shown), for example, other fins on adjacent devices. In one embodiment, the buffer layer 604 can include an oxide layer (for example, silicon dioxide), or any other electrically insulating layer. In one embodiment, the buffer layer 604 can include an interlay er dielectric (ILD), such as silicon dioxide. In one embodiment, the buffer layer 604 may include polyimide, epoxy, photodefinable materials (for example, benzocyclobutene, BCB), WPR-series materials, and/or spin-on-glass. In one embodiment, the buffer layer 604 can include a low permittivity (low-k) ILD layer. In one embodiment, low-k can refer to dielectrics having a dielectric constant (permittivity k) lower than the permittivity of silicon dioxide. In one embodiment, the thickness of the buffer layer 604 can be approximately 10 nm to approximately 300 nm, with an example thickness of approximately 30 nm to approximately 50 nm. In one embodiment, the buffer layer 604 can be deposited using PVD, CVD and/or ALD, and the like.

[0081] In an embodiment, the buffer layer 604 can be patterned and etched to form trenches, such as trench 605 using one of the patterning and etching techniques known to one of ordinary skill in the art. In one embodiment, the trench 605 has a depth D of about 50 nm to about 300 nm and a width W of about 5 nm to about 20 nm. In one embodiment, an aspect ratio of the trench 605 (DAV) can determine the thickness of the buffer layers deposited through that trench 605. In another embodiment, the higher the DAV ratio of the trench 605, the thicker the buffer layers can be.

[0082] In one embodiment, the partial structure 600 can include a first semiconductor material 606. In another embodiment, the first semi-conducting material 606 can include a gallium arsenide material. In another embodiment, the first semi-conducting material 606 can have an overgrowth region 613 which can extend above the plane of the buffer layer 604. In one embodiment, the first semiconductor material 606 can be deposited through the trench 605 onto the exposed portion of substrate 602. In an embodiment, the first semiconductor material 606 can have as a lattice parameter between the lattice parameter of the substrate 602 and a second semiconductor material 714 (to be shown and described in connection with FIG. 7) which will be formed thereon. Generally, a lattice constant can refer to a lattice parameter that can describe as a distance between unit cells in a crystal lattice. In one embodiment, the lattice parameter can be a measure of the structural compatibility between different materials. In another embodiment, the lattice constant of the first semiconductor material 606 can be substantially similar to the lattice constant of the fin comprising a second semiconductor material 714 later eventually formed thereon. In another embodiment, material for the first semiconductor material 606 can be selected such that the lattice constant of the first semiconductor material 606 is generally equal to the lattice constant of the portion of the second semiconductor material 714 comprising the fin and/or channel of the FinFET. In an embodiment, the substrate 602 can be a p-doped silicon substrate, and the first semiconductor material 606 can include a III-V material. In one embodiment, the III-V material can refer to a compound semiconductor material that comprises at least one group III element of the periodic table (for example, aluminum, gallium, and/or indium)) and at least one of group V element of the periodic table (for example, nitrogen, phosphorus, arsenic, and/or antimony). In an embodiment, the first semiconductor material 606 can include InP, GaAs, InAlAs, GaAsSb, another III-V material, or any combination thereof.

[0083] In one embodiment, the first semiconductor material 606 can include black phosphorous, amorphous silicon, germanium, carbon nanotube, and the like. In one embodiment, the first semiconductor material 606 can include silicon, germanium, indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as zinc oxide (ZnO), indium gallium zinc oxide (IGZO), amorphous silicon (a-Si), amorphous germanium (a-Ge), polycrystalline germanium, polycrystalline silicon, and/or polycrystalline InGaAs, and the like. In one embodiment, the first semiconductor material

606 can have a length in the z-dimension and/or width in the x and/or y- dimension that can depend on which technology is used to generate the transistor. In another embodiment, the first semiconductor material 606 can be approximately 20 nm to approximately 200 nm long (in the y-dimension), with example thicknesses of approximately 60 nm to approximately 80 nm long (in the y-dimension). In one embodiment, the first semiconductor material 606 width can be approximately 90 nm down to approximately 5 nm (in the y-dimension). In one embodiment, the first semiconductor material 606 can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like.

[0084] In one embodiment, the partial structure 600 of the FinFET can include a first template growth surface 607. In one embodiment, the first semiconductor material 606 can be deposited through trench 605 onto the exposed portion of substrate 602, that is, onto the first template growth surface 607. In an embodiment, the first template growth surface 607 of the first semiconductor material 606 can include a predetermined facet or surface of the substrate 602. For example, a facet of the substrate 602 having Miller indices of (111) can serve as a surface to minimize misfit dislocations during the formation of the first semiconductor material 606.

[0085] In one embodiment, the first template growth surface 607 can have a v-shape. For example, a v-shaped groove. In another embodiment, the first template growth surface

607 can have a meniscus shape. In another embodiment, the first template growth surface 607 can have any other suitable shape which forms in the positive z-direction with respect to the plane vector pointing in the direction of the plane of the substrate 602.

[0086] FIG. 7 shows a partial structure 700 of a FinFET device in accordance with one or more example embodiments of the disclosure. In one embodiment, the partial structure 700 of the FinFET can include a portion of a second semiconductor material 714. In one embodiment, the portion of the portion of the second semiconductor material 714 can be related to the previous FIG. 6, second semiconductor material 612, with the overgrowth region 613 of the second semiconductor material 612 removed. In another embodiment, the removal of the overgrowth region 613 of the second semiconductor material 612 can be performed using an etching process. In one embodiment, the etching process can include, for example, a dry etch. In one embodiment, the dry etch can include, for example, a plasma-based and/or a mechanical-based etch. In one embodiment, the etching process can include, for example, a wet etch. The wet etching process can include, for example, any suitable chemicals for the removal of the overgrowth region 613 of the second semiconductor material 612. For example, for a second semiconductor material 612 comprising gallium arsenide, a ammonium hydroxide based wet etch may be used.

[0087] In another embodiment, the portion of a second semiconductor material 714 can include an indium gallium arsenide material. In one embodiment, the portion of the second semiconductor material 714 can include black phosphorous, amorphous silicon, germanium, carbon nanotube, and the like. In one embodiment, the portion of the second semiconductor material 714 can include silicon, germanium, indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as zinc oxide (ZnO), indium gallium zinc oxide (IGZO), amorphous silicon (a-Si), amorphous germanium (a- Ge), polycrystalline germanium, poly crystalline silicon, and/or polycrystalline InGaAs, and the like. In one embodiment, the portion of the second semiconductor material 714 length in the z-dimension and/or width in the x and/or y- dimension can depend on which technology is used to generate the transistor. In another embodiment, the portion of the second semiconductor material 714 can be approximately 20 nm to approximately 200 nm long (in the y-dimension), with example thicknesses of approximately 60 nm to approximately 80 nm long (in the y-dimension). In one embodiment, the channel width can be approximately 90 nm down to approximately 5 nm (in the y-dimension). In one embodiment, the portion of the second semiconductor material 714 can be deposited using PVD, CVD, MOCVD, MBE and/or ALD, and the like.

[0088] In one embodiment, the partial structure 700 of the FinFET can include a second template growth surface 710. In one embodiment, the second template growth surface 710 can include a predetermined facet or surface of the first semiconductor material 706. For example, for the case of a first semiconductor material 706 comprising gallium arsenide, a facet having Miller indices of (1 11) can serve as the second template growth surface 710. In one embodiment, for the case of a first semiconductor material 706 comprising gallium arsenide, the portion of the second semiconductor material 714 can be an indium gallium arsenide (InGaAs) material. Accordingly, the facet of the first semiconductor material 706 comprising gallium arsenide having Miller indices of (1 11) can serve as a surface to minimize misfit dislocations during the formation of the portion of the second semiconductor material 714 comprising indium gallium arsenide. Further, the facet of the first semiconductor material 706 comprising gallium arsenide having Miller indices of (11 1) can serve as a surface to increase the probability that defects, during the formation of the portion of the second semiconductor material 714 comprising indium gallium arsenide, can glide to the sidewalls of the trench 705 sidewalls comprising a buffer layer 704 (for example, buffer layer 704 comprising an STI layer). As such, the defects formed during the formation of the portion of the second semiconductor material 714 comprising indium gallium arsenide can be contained substantially at the interface between first semiconductor material 706 comprising gallium arsenide and the portion of the second semiconductor material 714 comprising indium gallium arsenide.

[0089] In one embodiment, the second template growth surface 710 can have a v- shape, for example, a v-shaped groove. In another embodiment, the second template growth surface 710 can have a meniscus shape. In another embodiment, the second template growth surface 710 can have any other suitable shape which forms in the positive z-direction with respect to the plane vector pointing in the direction of the plane of the substrate 702. The shape (for example, v-shape) of the second template growth surface 710 can, in various embodiments, serve to change the kinetics of the portion of the second semiconductor material 714 comprising indium gallium arsenide, such that gallium atoms may no longer be pushed toward the center of the fin comprising the portion of the second semiconductor material 714 comprising indium gallium arsenide during epitaxial growth of the portion of the second semiconductor material 714 comprising indium gallium arsenide. In one embodiment, this can reduce the InGaAs composition gradient across the width of the fin comprising the second semiconductor material 714.

[0090] In one embodiment, the partial structure 700 can include a substrate 702. In one embodiment, the substrate 702 can refer to a solid (usually planar) substance onto which a layer of another substance is applied, and to which that second substance adheres. In another embodiment, the substrate 702 can include a silicon substrate. In one embodiment, the substrate 702 can include a p-doped silicon substrate. In one embodiment, the substrate 702 can be a thin slice of material such as silicon, silicon oxide, silicon dioxide, aluminum oxide, sapphire, an alloy of silicon and germanium, and/or indium phosphide (InP), and the like. In one embodiment, the substrate 702 can include a semiconductor material (for example, monocrystalline silicon, germanium, silicon germanium, SiGe, and/or a III-V materials based material (for example, gallium arsenide, GaAs), or any combination thereof. In one embodiment, the partial structure 700 can include a buffer layer 704. In one embodiment, the buffer layer 704 can include any material suitable to insulate adjacent devices and prevent current leakage. In one embodiment, the buffer layer 704 can be a STI layer. In one embodiment, the STI layer can provide field isolation regions that isolate one fin from other fins (not shown), for example, other fins on adjacent devices. In one embodiment, the buffer layer 704 can include an oxide layer (for example, silicon dioxide), or any other electrically insulating layer. In one embodiment, the buffer layer 704 can include an interlay er dielectric (ILD), such as silicon dioxide. In one embodiment, the buffer layer 704 may include polyimide, epoxy, photodefinable materials (for example, benzocyclobutene, BCB), WPR-series materials, and/or spin-on-glass. In one embodiment, the buffer layer 704 can include a low permittivity (low-k) ILD layer. In one embodiment, low-k can refer to dielectrics having a dielectric constant (permittivity k) lower than the permittivity of silicon dioxide. In one embodiment, the thickness of the buffer layer 704 can be approximately 10 nm to approximately 300 nm, with an example thickness of approximately 30 nm to approximately 50 nm. In one embodiment, the buffer layer 704 can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like.

[0091] In an embodiment, the buffer layer 704 can be patterned and etched to form trenches, such as trench 705 using one of the patterning and etching techniques known to one of ordinary skill in the art. In one embodiment, the trench 705 has a depth D of about 50 nm to about 300 nm and a width W of about 5 nm to about 20 nm. In one embodiment, an aspect ratio of the trench 705 (DAV) can determine the thickness of the buffer layers deposited through that trench 705. In another embodiment, the higher the DAV ratio of the trench 705, the thicker the buffer layers can be.

[0092] In one embodiment, the partial structure 700 can include a first semiconductor material 706. In another embodiment, the first semiconductor material 706 can include a gallium arsenide material. In one embodiment, the first semiconductor material 706 can be deposited through the trench 705 onto the exposed portion of substrate 702. In an embodiment, the first semiconductor material 706 can have as a lattice parameter between the lattice parameter of the substrate 702 and a second semiconductor material 714 which will be formed thereon. Generally, a lattice constant can refer to a lattice parameter that can describe as a distance between unit cells in a crystal lattice. In one embodiment, the lattice parameter can be a measure of the structural compatibility between different materials. In another embodiment the lattice constant of the first semiconductor material 706 can be substantially similar to the lattice constant of the fin comprising a second semiconductor material 714 later eventually formed thereon. In another embodiment, material for the first semiconductor material 706 can be selected such that the lattice constant of the first semiconductor material 706 is generally equal to the lattice constant of the portion of the second semiconductor material 714 comprising the fin and/or channel of the FinFET.

[0093] In an embodiment, the substrate 702 can be a p-doped silicon substrate, and the first semiconductor material 706 can include a III-V material. In one embodiment, the III- V material can refer to a compound semiconductor material that comprises at least one group III element of the periodic table (for example, aluminum, gallium, and/or indium)) and at least one of group V element of the periodic table (for example, nitrogen, phosphorus, arsenic, and/or antimony). In an embodiment, the first semiconductor material 706 can include InP, GaAs, InAlAs, GaAsSb, another III-V material, or any combination thereof.

[0094] In one embodiment, the first semiconductor material 706 can include black phosphorous, amorphous silicon, germanium, carbon nanotube, and the like. In one embodiment, the first semiconductor material 706 can include silicon, germanium, indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as zinc oxide (ZnO), indium gallium zinc oxide (IGZO), amorphous silicon (a-Si), amorphous germanium (a-Ge), polycrystalline germanium, polycrystalline silicon, and/or poly crystalline InGaAs, and the like. In one embodiment, the first semiconductor material 706 can have a length in the z-dimension and/or width in the x and/or y- dimension that can depend on which technology is used to generate the transistor. In another embodiment, the first semiconductor material 706 can be approximately 20 nm to approximately 200 nm long (in the z-dimension), with example thicknesses of approximately 60 nm to approximately 80 nm (in the y-dimension). In one embodiment, the first semiconductor material 706 width can be approximately 20 nm down to approximately 5 nm (in the y- dimension). In one embodiment, the first semiconductor material 706 can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like.

[0095] In one embodiment, the partial structure 700 can include a first template growth surface 707. In one embodiment, the first semiconductor material 706 can be deposited through trench 705 onto the exposed portion of substrate 702, that is, onto the first template growth surface 707. In an embodiment, the first template growth surface 707 of the first semiconductor material 706 can include a predetermined facet or surface of the substrate 702. For example, a facet of the substrate 702 having Miller indices of (1 11) can serve as a surface to minimize misfit dislocations during the formation of the first semiconductor material 706. In one embodiment, the first template growth surface 707 can have a v-shape. For example, a v-shaped groove. In another embodiment, the first template growth surface 707 can have a meniscus shape. In another embodiment, the first template growth surface 707 can have any other suitable shape which forms in the positive z-direction with respect to the plane vector pointing in the direction of the plane of the substrate 702.

[0096] FIG. 8 shows a partial structure 800 of a FinFET device in accordance with one or more example embodiments of the disclosure. In one embodiment, the partial structure 800 of the FinFET can include a recess 816 in the buffer layer 804 that can be generated, by removing a portion of the buffer layer 704 as shown and described in connection with FIG. 7. In one embodiment, the recess 816 can thereby expose the portion of the second semiconductor material 814 with the overgrowth (that is, the overgrown 613 shown and described in connection with FIG. 6) removed, and a portion of the first semiconductor material 806 including a second template growth surface 810. In one embodiment, the removal of the portion of the buffer layer 704 can be performed using an etching process. In one embodiment, the etching process can include, for example, a dry etch. In one embodiment, the dry etch can include, for example, a plasma-based and/or a mechanical- based etch. In one embodiment, the etching process can include, for example, a wet etch. The wet etching process can include, for example, any suitable chemicals for the removal of the portion of the buffer layer 704. For example, for a portion of the buffer layer 704 comprising an STI, an ammonium hydroxide based wet etch may be used.

[0097] In one embodiment, the partial structure 800 of the FinFET can include a portion of a second semiconductor material 814. In another embodiment, the portion of a second semiconductor material 814 can include an indium gallium arsenide material. In one embodiment, the portion of the second semiconductor material 814 can include black phosphorous, amorphous silicon, germanium, carbon nanotube, and the like. In one embodiment, the portion of the second semiconductor material 814 can include silicon, germanium, indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as zinc oxide (ZnO), indium gallium zinc oxide (IGZO), amorphous silicon (a-Si), amorphous germanium (a-Ge), poly crystalline germanium, polycrystalline silicon, and/or polycrystalline InGaAs, and the like. In one embodiment, the portion of the second semiconductor material 814 length in the z-dimension and/or width in the x and/or y- dimension can depend on which technology is used to generate the transistor. In another embodiment, the portion of the second semiconductor material 814 can be approximately 20 nm to approximately 200 nm long (in the z-dimension), with example thicknesses of approximately 60 nm to approximately 80 nm long (in the y-dimension). In one embodiment, the channel width can be approximately 90 nm down to approximately 5 nm (in the y-dimension). In one embodiment, the portion of the second semiconductor material 814 can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like.

[0098] In one embodiment, the partial structure 800 of the FinFET can include a second template growth surface 810. In one embodiment, the second template growth surface 810 can include a predetermined facet or surface of the first semiconductor material 806. For example, for the case of a first semiconductor material 806 comprising gallium arsenide, a facet having Miller indices of (111) can serve as the second template growth surface 810. In one embodiment, for the case of a first semiconductor material 806 comprising gallium arsenide, the portion of the second semiconductor material 814 can be an indium gallium arsenide (InGaAs) material. Accordingly, the facet of the first semiconductor material 806 comprising gallium arsenide having Miller indices of (111) can serve as a surface to minimize misfit dislocations during the formation of the portion of the second semiconductor material 814 comprising indium gallium arsenide. Further, the facet of the first semiconductor material 806 comprising gallium arsenide having Miller indices of (111) can serve as a surface to increase the probability that defects, during the formation of the portion of the second semiconductor material 814 comprising indium gallium arsenide, can glide to the sidewalls of the trench 805 sidewalls comprising a buffer layer 804 (for example, buffer layer 804 comprising an STI layer). As such, the defects formed during the formation of the portion of the second semiconductor material 814 comprising indium gallium arsenide can be contained substantially at the interface between first semiconductor material 806 comprising gallium arsenide and the portion of the second semiconductor material 814 comprising indium gallium arsenide.

[0099] In one embodiment, the second template growth surface 810 can have a v- shape, for example, a v-shaped groove. In another embodiment, the second template growth surface 810 can have a meniscus shape. In another embodiment, the second template growth surface 810 can have any other suitable shape which forms in the positive z-direction with respect to the plane vector pointing in the direction of the plane of the substrate 802. The shape (for example, v-shape) of the second template growth surface 810 can, in various embodiments, serve to change the kinetics of the portion of the second semiconductor material 814 comprising indium gallium arsenide, such that the Ga atoms may no longer be pushed toward the center of the fin comprising the portion of the second semiconductor material 814 comprising indium gallium arsenide during epitaxial growth of the portion of the second semiconductor material 814 comprising indium gallium arsenide. In one embodiment, this can reduce the InGaAs composition gradient across the width of the fin comprising the second semiconductor material 814.

[0100] In one embodiment, the partial structure 800 can include a substrate 802. In one embodiment, the substrate 802 can refer to a solid (usually planar) substance onto which a layer of another substance is applied, and to which that second substance adheres. In another embodiment, the substrate 802 can include a silicon substrate. In one embodiment, the substrate 802 can include a p-doped silicon substrate. In one embodiment, the substrate 802 can be a thin slice of material such as silicon, silicon oxide, silicon dioxide, aluminum oxide, sapphire, an alloy of silicon and germanium, and/or indium phosphide (InP), and the like. In one embodiment, the substrate 802 can include a semiconductor material (for example, monocrystalline silicon, germanium, silicon germanium, SiGe, and/or a III-V materials based material (for example, gallium arsenide, GaAs), or any combination thereof.

[0101] In one embodiment, the partial structure 800 can include a buffer layer 804. In one embodiment, the buffer layer 804 can include any material suitable to insulate adjacent devices and prevent current leakage. In one embodiment, the buffer layer 804 can be a STI layer. In one embodiment, the STI layer can provide field isolation regions that isolate one fin from other fins (not shown), for example, other fins on adjacent devices. In one embodiment, the buffer layer 804 can include an oxide layer (for example, silicon dioxide), or any other electrically insulating layer. In one embodiment, the buffer layer

804 can include an interlay er dielectric (ILD), such as silicon dioxide. In one embodiment, the buffer layer 804 may include polyimide, epoxy, photodefinable materials (for example, benzocyclobutene, BCB), WPR-series materials, and/or spin-on-glass. In one embodiment, the buffer layer 804 can include a low permittivity (low-k) ILD layer. In one embodiment, low-k can refer to dielectrics having a dielectric constant (permittivity k) lower than the permittivity of silicon dioxide. In one embodiment, the thickness of the buffer layer 804 after the removal of the portion of the buffer layer to generate the recess 816 can be 10 nm to approximately 300 nm, with an example thickness of approximately 30 nm to approximately 50 nm. In one embodiment, the buffer layer 804 can be deposited using PVD, CVD and/or ALD, and the like. In an embodiment, the buffer layer 804 can be patterned and etched to form trenches, such as trench 805 using one of the patterning and etching techniques known to one of ordinary skill in the art. In one embodiment, the trench

805 has a depth D of about 50 nm to about 300 nm and a width W of about 5 nm to about 20 nm. In one embodiment, an aspect ratio of the trench 805 (D/W) can determine the thickness of the buffer layers deposited through that trench 805. In another embodiment, the higher the D/W ratio of the trench 805, the thicker the buffer layers can be.

[0102] In one embodiment, the partial structure 800 can include a first semiconductor material 806. In another embodiment, the first semi-conducting material 806 can include a gallium arsenide material. In one embodiment, the first semiconductor material 806 can be deposited through the trench 805 onto the exposed portion of substrate 802. In an embodiment, the first semiconductor material 806 can have as a lattice parameter between the lattice parameter of the substrate 802 and a second semiconductor material 814 formed thereon. Generally, a lattice constant can refer to a lattice parameter that can describe as a distance between unit cells in a crystal lattice. In one embodiment, the lattice parameter can be a measure of the structural compatibility between different materials. In another embodiment the lattice constant of the first semiconductor material 806 can be substantially similar to the lattice constant of the fin comprising a second semiconductor material 814 later eventually formed thereon. In another embodiment, material for the first semiconductor material 806 can be selected such that the lattice constant of the first semiconductor material 806 is generally equal to the lattice constant of the portion of the second semiconductor material 814 comprising the fin of the FinFET. [0103] In an embodiment, the substrate 802 can be a p-doped silicon substrate, and the first semiconductor material 806 can include a III-V material. In one embodiment, the III- V material can refer to a compound semiconductor material that comprises at least one group III element of the periodic table (for example, aluminum, gallium, and/or indium)) and at least one of group V element of the periodic table (for example, nitrogen, phosphorus, arsenic, and/or antimony). In an embodiment, the first semiconductor material 806 can include InP, GaAs, InAlAs, GaAsSb, another III-V material, or any combination thereof. In one embodiment, the first semiconductor material 806 can include black phosphorous, amorphous silicon, germanium, carbon nanotube, and the like. In one embodiment, the first semiconductor material 806 can include silicon, germanium, indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as zinc oxide (ZnO), indium gallium zinc oxide (IGZO), amorphous silicon (a-Si), amorphous germanium (a-Ge), polycrystalline germanium, polycrystalline silicon, and/or poly crystalline InGaAs, and the like. In one embodiment, the first semiconductor material 806 can have a length in the z-dimension and/or width in the x and/or y-dimension that can depend on which technology is used to generate the transistor. In another embodiment, the first semiconductor material 806 can be approximately 20 nm to approximately 200 nm long (in the z-dimension), with example thicknesses of approximately 60 nm to approximately 80 nm (in the y-dimension). In one embodiment, the first semiconductor material 806 width can be approximately 20 nm down to approximately 5 nm (in the y- dimension). In one embodiment, the first semiconductor material 806 can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like.

[0104] In one embodiment, the partial structure 800 of the FinFET can include a first template growth surface 807. In one embodiment, the first semiconductor material 806 can be deposited through trench 805 onto the exposed portion of substrate 802, that is, onto the first template growth surface 807. In an embodiment, the first template growth surface 807 of the first semiconductor material 806 can have as a lattice parameter between the lattice parameter of the substrate 802 and a second semiconductor material 814 which will be formed thereon. In one embodiment, the lattice parameter can be a measure of the structural compatibility between different materials. In another embodiment, the lattice constant of the first semiconductor material 806 can be generally equal to the lattice constant of the fin and/or channel comprising the portion of the second semiconductor material 814 formed thereon. [0105] FIG. 9 shows a diagram of an example process flow for the fabrication of a FinFET device, in accordance with example embodiments of the disclosure. In block 902, a substrate can be provided. In one embodiment, the substrate can refer to a solid (usually planar) substance onto which a layer of another substance is applied, and to which that second substance adheres. In another embodiment, the substrate can include a silicon substrate. In one embodiment, the substrate can include a p-doped silicon substrate. In one embodiment, the substrate can be a thin slice of material such as silicon, silicon oxide, silicon dioxide, aluminum oxide, sapphire, an alloy of silicon and germanium, and/or indium phosphide (InP), and the like. In one embodiment, the substrate can include a semiconductor material (for example, monocrystalline silicon, germanium, silicon germanium, SiGe, and/or a III-V materials based material (for example, gallium arsenide, GaAs), or any combination thereof).

[0106] In block 904, a buffer layer that defines a trench exposing the substrate can be provided. In one embodiment, the buffer layer can include any material suitable to insulate adjacent devices and prevent current leakage. In one embodiment, the buffer layer can be a shallow trench isolation (STI) layer. In one embodiment, the STI layer can provide field isolation regions that isolate one fin from other fins, for example, other fins on adjacent devices. In one embodiment, the buffer layer can include an oxide layer (for example, silicon dioxide), or any other electrically insulating layer. In one embodiment, the buffer layer can include an interlayer dielectric (ILD), such as silicon dioxide. In one embodiment, the buffer layer may include polyimide, epoxy, photodefinable materials (for example, benzocyclobutene (BCB)), WPR-series materials, and/or spin-on-glass. In one embodiment, the buffer layer can include a low permittivity (low-k) ILD layer. In one embodiment, low-k can refer to dielectrics having a dielectric constant (permittivity k) lower than the permittivity of silicon dioxide. In one embodiment, the thickness of the buffer layer can be approximately 10 nm to approximately 300 nm, with an example thickness of approximately 30 nm to approximately 50 nm. In one embodiment, the buffer layer can be deposited using PVD, CVD and/or ALD, and the like. In an embodiment, the buffer layer can be patterned and etched to form trenches, using one of the patterning and etching techniques known to one of ordinary skill in the art. In one embodiment, the trench can have a depth D of approximately about 50 nm to about 300 nm and a width W of approximately about 50 nm to about 300 nm. In one embodiment, an aspect ratio of the trench (DAV) can determine the thickness of the buffer layers deposited through that trench. In another embodiment, the higher the D/W ratio of the trench, the thicker the buffer layer can be.

[0107] In block 906, a fin comprising a source and a drain can be formed, the formation of the fin including: forming a first semiconductor material in the trench on at least a portion of the exposed substrate. In another embodiment, the first semiconductor material can include a gallium arsenide (GaAs) material. In one embodiment, the first semiconductor material can be deposited through the trench onto the exposed portion of substrate. In an embodiment, the first semiconductor material can have as a lattice parameter between the lattice parameter of the substrate and a second semiconductor material which will be formed thereon. In another embodiment, the lattice constant of the first semiconductor material can be substantially similar to the lattice constant of the fin comprising a second semiconductor material formed thereon. In another embodiment, material for the first semiconductor material can be selected such that the lattice constant of the first semiconductor material is substantially equal to the lattice constant of the second semiconductor material. In an embodiment, the substrate can be a p-doped silicon substrate, and the first semiconductor material can include a III-V material. In one embodiment, the III-V material can refer to a compound semiconductor material that comprises at least one group III element of the periodic table (for example, aluminum, gallium, and/or indium) and at least one of group V element of the periodic table (for example, nitrogen, phosphorus, arsenic, and/or antimony). In an embodiment, the first semiconductor material can include InP, GaAs, InAlAs, GaAsSb, another III-V material, or any combination thereof.

[0108] In one embodiment, the first semiconductor material can include black phosphorous, amorphous silicon, germanium, carbon nanotube, and the like. In one embodiment, the first semiconductor material can include silicon, germanium, indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as zinc oxide (ZnO), indium gallium zinc oxide (IGZO), amorphous silicon (a-Si), amorphous germanium (a-Ge), polycrystalline germanium, polycrystalline silicon, and/or poly crystalline InGaAs, and the like. In one embodiment, the first semiconductor material can have a length in the z-dimension and/or width in the x and/or y- dimension that can depend on which technology is used to generate the transistor. In another embodiment, the first semiconductor material can be approximately 20 nm to approximately 200 nm long (in the z-dimension), with example thicknesses of approximately 60 nm to approximately 80 nm long (in the z-dimension). In one embodiment, the first semiconductor material can be approximately 90 nm down to approximately 5 nm (in the y-dimension). In one embodiment, the first semiconductor material can be deposited using PVD, CVD, MOCVD, MBE, and/or ALD, and the like.

[0109] In block 908, a portion of the first semiconductor material in the trench can be removed to form a template growth region on a first surface of the first semiconductor material. In one embodiment, the removal of the portion of the first semiconductor material can be performed using an etching process. In one embodiment, the etching process can include, for example, a dry etch. In one embodiment, the dry etch can include, for example, a plasma-based and/or a mechanical-based etch. In one embodiment, the etching process can include, for example, a wet etch. The wet etching process can include, for example, any suitable chemicals for the removal of first semiconductor material. For example, for a first semiconductor material comprising gallium arsenide, an ammonium hydroxide based wet etch may be used.

[0110] In block 910, a second semiconductor material can be formed in the trench on the template growth region of the first semiconductor material, wherein a first portion of the second semiconductor material extends out of the trench. In another embodiment, the second semiconductor material can include an indium gallium arsenide material. In one embodiment, the second semiconductor material can include black phosphorous, amorphous silicon, germanium, carbon nanotube, and the like. In one embodiment, the second semiconductor material can include silicon, germanium, indium gallium arsenide (InGaAs), gallium nitride (GaN), amorphous semiconductors such as zinc oxide (ZnO), indium gallium zinc oxide (IGZO), amorphous silicon (a-Si), amorphous germanium (a- Ge), polycrystalline germanium, poly crystalline silicon, and/or polycrystalline InGaAs, and the like. In one embodiment, the second semiconductor material length in the z- dimension and/or width in the x and/or y- dimension can depend on which technology is used to generate the transistor. In another embodiment, the second semiconductor material can be approximately 20 nm to approximately 200 nm long (in the z-dimension), with example thicknesses of approximately 60 nm to approximately 80 nm long (in the y- dimension). In one embodiment, the channel width can be approximately 20 nm down to approximately 5 nm (in the y-dimension). In one embodiment, the second semiconductor material can be deposited using PVD, CVD, and/or ALD, and the like. [0111] In block 912, the first portion of the second semiconductor material can be removed. In another embodiment, the removal of the first portion of the second semiconductor material can be performed using an etching process. In one embodiment, the etching process can include, for example, a dry etch. In one embodiment, the dry etch can include, for example, a plasma-based and/or a mechanical-based etch. In one embodiment, the etching process can include, for example, a wet etch. The wet etching process can include, for example, any suitable chemicals for the removal of the second portion of the second semiconductor material . For example, for a second semiconductor material comprising gallium arsenide, an ammonium hydroxide based wet etch may be used.

[0112] In block 914, a portion of the buffer layer proximate the fin can be removed to expose at least a portion of the second semiconductor material. In one embodiment, the removal of the portion of the buffer layer can generate a recess that can thereby expose the portion of the second semiconductor material, and a portion of the first semiconductor material including a second template growth surface. In one embodiment, the removal of the portion of the buffer layer can be performed using an etching process. In one embodiment, the etching process can include, for example, a dry etch. In one embodiment, the dry etch can include, for example, a plasma-based and/or a mechanical-based etch. In one embodiment, the etching process can include, for example, a wet etch. The wet etching process can include, for example, any suitable chemicals for the removal of the portion of the buffer layer. For example, for a portion of the buffer layer comprising an STI, an ammonium hydroxide based wet etch may be used.

[0113] In various embodiments, the devices, as described herein, may be used in connection with one or more processors. The one or more processors may include, without limitation, a central processing unit (CPU), a digital signal processor(s) (DSP), a reduced instruction set computer (RISC), a complex instruction set computer (CISC), a microprocessor, a microcontroller, a field programmable gate array (FPGA), or any combination thereof. The processors may also include one or more application specific integrated circuits (ASICs) or application specific standard products (ASSPs) for handling specific data processing functions or tasks. In certain embodiments, the processors may be based on an Intel® Architecture system and the one or more processors and any chipset included in an electronic device may be from a family of Intel® processors and chipsets, such as the Intel® Atom® processor(s) family or Intel-64 processors (for example, Sandy Bridge®, Ivy Bridge®, Haswell®, Broadwell®, Skylake®, etc.).

[0114] FIG. 10 depicts an example of a system 1000 according to one or more embodiments of the disclosure. In one embodiment, the transistors described herein can be used in connection with or formed as a part of any of the devices shown in system 1000. In one embodiment, system 1000 includes, but is not limited to, a desktop computer, a laptop computer, a netbook, a tablet, a notebook computer, a personal digital assistant (PDA), a server, a workstation, a cellular telephone, a mobile computing device, a smart phone, an Internet appliance or any other type of computing device. In some embodiments, system 1000 can include a system on a chip (SOC) system.

[0115] In one embodiment, system 1000 includes multiple processors including processor 1010 (in Fig. 10, processor 1010 is labeled as 610) and processor N 1005, where processor N 1005 has logic similar or identical to the logic of processor 1010. In one embodiment, processor 1010 has one or more processing cores (represented here by processing core 1 1012 and processing core N 1012N, where 1012N represents the Nth processor core inside processor 1010, where N is a positive integer). More processing cores can be present (but not depicted in the diagram of FIG. 10). In some embodiments, processing core 1012 includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions, a combination thereof, or the like. In some embodiments, processor 1010 has a cache memory 1016 to cache instructions and/or data for system 1000. Cache memory 1016 may be organized into a hierarchical structure including one or more levels of cache memory.

[0116] In some embodiments, processor 1010 includes a memory controller (MC) 1014, which is configured to perform functions that enable the processor 1010 to access and communicate with memory 1030 that includes a volatile memory 1032 and/or a nonvolatile memory 1034. In some embodiments, processor 1010 can be coupled with memory 1030 and chipset 1020. Processor 1010 may also be coupled to a wireless antenna 1078 to communicate with any device configured to transmit and/or receive wireless signals. In one embodiment, the wireless antenna 1078 operates in accordance with, but is not limited to, the IEEE 1002.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol. [0117] In some embodiments, volatile memory 1032 includes, but is not limited to, Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM), and/or any other type of random access memory device. Non-volatile memory 1034 includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device.

[0118] Memory device 1030 stores information and instructions to be executed by processor 1010. In one embodiment, memory 1030 may also store temporary variables or other intermediate information while processor 1010 is executing instructions. In the illustrated embodiment, chipset 1020 connects with processor 1010 via Point-to-Point (PtP or P-P) interface 1017 and P-P interface 1022. Chipset 1020 enables processor 1010 to connect to other elements in system 1000. In some embodiments of the disclosure, P-P interface 1017 and P-P interface 1022 can operate in accordance with a PtP communication protocol, such as the Intel® QuickPath Interconnect (QPI) or the like. In other embodiments, a different interconnect may be used.

[0119] In some embodiments, chipset 1020 can be configured to communicate with processor 1010, the processor N 1005, display device 1040, and other devices 1072, 1076, 1074, 1060, 1062, 1064, 1066, 1077, etc. Chipset 1020 may also be coupled to the wireless antenna 1078 to communicate with any device configured to transmit and/or receive wireless signals.

[0120] Chipset 1020 connects to display device 1040 via interface 1026. Display 1040 may be, for example, a liquid crystal display (LCD), a plasma display, cathode ray tube (CRT) display, or any other form of visual display device. In some embodiments of the disclosure, processor 1010 and chipset 1020 are integrated into a single SOC. In addition, chipset 1020 connects to bus 1050 and/or bus 1055 that interconnect various elements 1074, 1060, 1062, 1064, and 1066. Bus 1050 and bus 1055 may be interconnected via a bus bridge 1072. In one embodiment, chipset 1020 couples with a non-volatile memory 1060, a mass storage device(s) 1062, a keyboard/mouse 1064, and a network interface 1066 via interface 1024 and/or 1026, smart TV 1076, consumer electronics 1077, etc.

[0121] In one embodiment, mass storage device(s) 1062 can include, but not be limited to, a solid state drive, a hard disk drive, a universal serial bus flash memory drive, or any other form of computer data storage medium. In one embodiment, network interface 1066 is implemented by any type of well-known network interface standard including, but not limited to, an Ethernet interface, a universal serial bus (USB) interface, a Peripheral Component Interconnect (PCI) Express interface, a wireless interface and/or any other suitable type of interface. In one embodiment, the wireless interface operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

[0122] While the modules shown in FIG. 10 are depicted as separate blocks within the system 1000, the functions performed by some of these blocks may be integrated within a single semiconductor circuit or may be implemented using two or more separate integrated circuits. For example, although cache memory 1016 is depicted as a separate block within processor 1010, cache memory 1016 or selected elements thereof can be incorporated into processor core 1012.

[0123] It is noted that the system 1000 described herein may be any suitable type of microelectronics packaging and configurations thereof, including, for example, system in a package (SiP), system on a package (SOP), package on package (PoP), interposer package, 3D stacked package, etc. Further, any suitable type of microelectronic components may be provided in the semiconductor packages, as described herein. For example, microcontrollers, microprocessors, baseband processors, digital signal processors, memory dies, field gate arrays, logic gate dies, passive component dies, MEMSs, surface mount devices, application specific integrated circuits, baseband processors, amplifiers, filters, combinations thereof, or the like may be packaged in the semiconductor packages, as disclosed herein. The semiconductor packages (for example, the semiconductor packages described in connection with any of FIGS. 1-6), as disclosed herein, may be provided in any variety of electronic devices including consumer, industrial, military, communications, infrastructural, and/or other electronic devices.

[0124] Additionally or alternatively, the devices, as described herein, may be used in connection with one or more additional memory chips. The memory may include one or more volatile and/or non-volatile memory devices including, but not limited to, magnetic storage devices, read-only memory (ROM), random access memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), double data rate (DDR) SDRAM (DDR-SDRAM), RAM-BUS DRAM (RDRAM), flash memory devices, electrically erasable programmable read-only memory (EEPROM), non-volatile RAM (NVRAM), universal serial bus (USB) removable memory, or combinations thereof.

[0125] In example embodiments, the electronic device in which the disclosed devices are used and/or provided may be a computing device. Such a computing device may house one or more boards on which the devices may be disposed. The board may include a number of components including, but not limited to, a processor and/or at least one communication chip. The processor may be physically and electrically connected to the board through, for example, electrical connections of the devices. The computing device may further include a plurality of communication chips. For instance, a first communication chip may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, and others. In various example embodiments, the computing device may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra- mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, combinations thereof, or the like. In further example embodiments, the computing device may be any other electronic device that processes data.

[0126] Example 1 is a fin field effect transistor (FinFET) device, comprising: a substrate; a buffer layer defining a trench exposing the substrate; a fin comprising a source and a drain, the fin including: a first semiconductor material disposed in the trench on the substrate, wherein the first semiconductor material includes a template growth region on a first surface of the first semiconductor material; and a second semiconductor material disposed on the first semiconductor material; and a gate disposed on the buffer layer and a portion of the second semiconductor material. In example 2, the device of example 1 can optionally include the template growth region having a convex shape with respect to a direction normal to the plane of the substrate. In example 3, the device of any one of example 1-2 can optionally include the substrate comprising a p-doped silicon substrate. In example 4, the device of any one of examples 1-3 can optionally include the first semiconductor material comprising a GaAs semiconductor material. In example 5, the device of any one of examples 1-4 can optionally include the second semiconductor material comprising an InGaAs semiconductor material. In example 6, the device of any one of examples 1-5 can optionally include the InGaAs semiconductor material comprising an epitaxially grown InGaAs semiconductor material. In example 7, the device of any one of examples 1-6 can optionally include the template growth region on a first surface of the first semiconductor material comprising a template growth region having a facet having a Miller index of (111). In example 8, the device of any one of examples 1-7 can optionally include the buffer layer comprises a shallow trench isolation layer. In example 9, the device of any one of examples 1-8 can optionally include the template growth region being produced by a wet etch or a dry etch.

[0127] Example 10 is a method for fabrication a fin in a fin field effect transistor (FinFET) device, the method comprising: providing a substrate; providing a buffer layer defining a trench exposing the substrate; forming a fin comprising a source and a drain, the formation of the fin including: forming a first semiconductor material inside the trench, wherein a first portion of first semiconductor material extends above the level of the buffer layer in a direction normal to the plan of the buffer layer; removing a second portion of the first semiconductor material inside the trench to generate a first recess; removing a third portion of the first semiconductor material to produce a template growth region on a first surface of the first semiconductor material; forming a second semiconductor material inside the trench, wherein a first portion of the second semiconductor material extends above the level of the buffer layer in a direction normal to the plane of the buffer layer; removing a second portion of the second semiconductor material including the first portion of the second semiconductor material that extends above the level of the buffer layer; and remove a portion of the buffer layer to form a fin comprising a third portion of the second semiconductor material. In example 11, the method of example 10 can optionally include the template growth region having a convex shape with respect to a direction normal to the plane of the substrate. In example 12, the method of any one of examples 10-11 can optionally include providing the substrate comprising providing a p-doped silicon substrate. In example 13, the method of any one of examples 10-12 can optionally include removing a second portion of the first semiconductor material inside the trench to generate a first recess comprising removing a second portion of the first semiconductor material inside the trench to generate a first recess using an acid based etching process. In example 14, the method of any one of examples 10-13 can optionally include removing a third portion of the first semiconductor material to produce a template growth region on a first surface of the first semiconductor material comprising removing a third portion of the first semiconductor material to produce a template growth region on a first surface of the first semiconductor material using an ammonium hydroxide etching process. In example 15, the method of any one of examples 10-14 can optionally include forming a second semiconductor material inside the trench comprising forming a second semiconductor material inside the trench using an epitaxial growth process. In example 16, the method of any one of examples 10-15 can optionally include removing a second portion of the second semiconductor material including the first portion of the second semiconductor material that extends above the level of the buffer layer comprising removing a second portion of the second semiconductor material including the first portion of the second semiconductor material that extends above the level of the buffer layer using a mechanical polishing process. In example 17, the method of any one of examples 10-16 can optionally include removing a portion of the buffer layer to form a fin comprising a third portion of the second semiconductor material comprising removing a portion of the buffer layer to form a fin comprising a third portion of the second semiconductor material using an acid based etching process. In example 18, the method of any one of examples 10-17 can optionally include forming the first semiconductor material comprising forming a GaAs semiconductor material. In example 19, the method of any one of examples 10-18 can optionally include forming the second semiconductor material comprising forming an InGaAs semiconductor material. In example 20, the method of any one of examples 10-19 can optionally include producing a template growth region on a first surface of the first semiconductor material comprising producing a template growth region on a first surface of the first semiconductor material having a facet having a Miller index of (111).

[0128] Examples 21 is a system including: at least one processor and at least one a memory, wherein the at least one processor comprises a fin field effect transistor (FinFET) device, wherein the FinFET device further comprises: a substrate; a buffer layer defining a trench exposing the substrate; a fin comprising a source and a drain, the fin including: a first semiconductor material disposed in the trench on the substrate, wherein the first semiconductor material includes a template growth region on a first surface of the first semiconductor material; and a second semiconductor material disposed on the first semiconductor material; and a gate disposed on the buffer layer and a portion of the second semiconductor material. In example 22, the system of example 21 can optionally include template growth region having a convex shape with respect a direction normal to the plane of the substrate. In example 23, the system of any one of examples 21-22 can optionally include first semiconductor material comprising a GaAs semiconductor material. In example 24, the system of any one of examples 21-23 can optionally include the GaAs semiconductor material comprising an epitaxially grown GaAs semiconductor material. In example 25, the system of any one of examples 21-24 can optionally include the template growth region on a first surface of the first semiconductor material comprising a template growth region having a facet having a Miller index of (1 11). In example 26, the system of any one of examples 21-25 can optionally include the substrate comprising a p-doped silicon substrate. In example 27, the system of any one of examples 21-26 can optionally include the second semiconductor material comprising a GaAs semiconductor material. In example 28, the system of any one of examples 21 -27 can optionally include the buffer layer comprising a shallow trench isolation layer. In example 29, the system of any one of examples 21 -28 can optionally include the template growth region being produced by a wet etch or a dry etch.

[0129] Various features, aspects, and embodiments have been described herein. The features, aspects, and embodiments are susceptible to combination with one another as well as to variation and modification, as will be understood by those having skill in the art. The present disclosure should, therefore, be considered to encompass such combinations, variations, and modifications.

[0130] The terms and expressions which have been employed herein are used as terms of description and not of limitation, and there is no intention, in the use of such terms and expressions, of excluding any equivalents of the features shown and described (or portions thereof), and it is recognized that various modifications are possible within the scope of the claims. Other modifications, variations, and alternatives are also possible. Accordingly, the claims are intended to cover all such equivalents.

[0131] While the disclosure includes various embodiments, including at least a best mode, it is to be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the foregoing description. Accordingly, the disclosure is intended to embrace all such alternatives, modifications, and variations, which fall within the scope of the included claims. All matters disclosed herein or shown in the accompanying drawings are to be interpreted in an illustrative and non- limiting sense. [0132] This written description uses examples to disclose certain embodiments of the disclosure, including the best mode, and also to enable any person skilled in the art to practice certain embodiments of the disclosure, including making and using any apparatus, devices or systems and performing any incorporated methods and processes. The patentable scope of certain embodiments of the invention is defined in the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal language of the claims.

Claims

What is claimed is:

1. A fin field effect transistor (FinFET) device, comprising:

a substrate;

a buffer layer on the substrate, the buffer layer having a trench that extends to the substrate;

a source and a drain at least partially disposed in the trench;

a fin at least partially disposed in the trench and coupled with the source and the drain;

a first semiconductor material disposed in the trench, wherein the first

semiconductor material includes a template growth region on a surface of the first semiconductor material; and

a second semiconductor material disposed on the first semiconductor material and on the template growth region; and

a gate on the buffer layer and a portion of the second semiconductor material.

2. The device of claim 1, wherein the template growth region has a convex shape with respect to a direction normal to a plane of the substrate.

3. The device of claim 1, wherein the substrate comprises a p-doped silicon substrate.

4. The device of claim 1 , wherein the first semiconductor material comprises a GaAs semiconductor material.

5. The device of claim 4, wherein the buffer layer comprises a shallow trench isolation layer.

6. The device of claim 4, wherein the template growth region on a surface of the first semiconductor material comprises a template growth region having a facet having a Miller index of (1 1 1).

7. The device of claim 1, wherein the second semiconductor material comprises an InGaAs semiconductor material.

8. The device of claim 7, wherein the InGaAs semiconductor material comprises an epitaxially grown InGaAs semiconductor material.

9. A method for fabrication a fin in a fin field effect transistor (FinFET) device, the method comprising:

providing a substrate;

providing a buffer layer , the buffer layer having a trench that extends to the substrate;

forming a source and a drain at least partially disposed in the trench;

forming a fin at least partially disposed in the trench and coupled with the source and the drain, the formation of the fin including:

forming a first semiconductor material in the trench;

removing a portion of the first semiconductor material in the trench to form a template growth region on a surface of the first semiconductor material;

forming a second semiconductor material in the trench on the template growth region of the first semiconductor material, wherein a portion of the second semiconductor material extends out of the trench;

removing the portion of the second semiconductor material; and remove a portion of the buffer layer to expose at least a portion of the second semiconductor material. 10. The method of claim 9, wherein the template growth region has a convex shape with respect to a direction normal to a plane of the substrate.

11. The method of claim 9, wherein providing the substrate comprises providing a p-doped silicon substrate.

12. The method of claim 9, wherein removing a portion of the first semiconductor material comprises removing a portion of the first semiconductor material using an ammonium hydroxide etching process.

13. The method of claim 9, wherein forming a second semiconductor material in the trench comprises forming a second semiconductor material in the trench using an epitaxial growth process.

14. The method of claim 9, wherein removing the portion of the second semiconductor material comprises removing a second portion of the second semiconductor material including the portion of the second semiconductor material that extends above a level of the buffer layer using a mechanical polishing process.

15. The method of claim 9, wherein removing a portion of the buffer layer comprises removing a portion of the buffer layer using an acid based etching process.

16. The method of claim 9, wherein forming the first semiconductor material comprises forming a GaAs semiconductor material.

17. The method of claim 16, wherein the template growth region on a surface of the first semiconductor material comprises a facet having a Miller index of (111). 18. The method of claim 9, wherein forming the second semiconductor material comprises forming an InGaAs semiconductor material.

20. A system including:

at least one processor and at least one a memory, wherein the at least one processor comprises a fin field effect transistor (FinFET) device, wherein the FinFET device further comprises:

a substrate;

a source and a drain at least partially disposed in the trench;

a fin at least partially disposed in the trench and coupled with the source and the drain; a first semiconductor material disposed in the trench, wherein the first

a gate on the buffer layer and a portion of the second semiconductor material.

21. The system of claim 20, wherein the template growth region has a convex shape with respect a direction normal to a plane of the substrate.

22. The system of claim 20, wherein the first semiconductor material comprises a GaAs semiconductor material.

23. The system of claim 22, wherein the template growth region on a surface of the first semiconductor material comprises a facet having a Miller index of (1 11).

24. The system of claim 20, wherein the second semiconductor material comprises a GaAs semiconductor material. 25. The system of claim 24, wherein the GaAs semiconductor material comprises an epitaxially grown GaAs semiconductor material.