WO2018182645A1

WO2018182645A1 - Spintronic memory with perforated cap layer

Info

Publication number: WO2018182645A1
Application number: PCT/US2017/025172
Authority: WO
Inventors: Md Tofizur Rahman; Christopher J. WIEGAND; Daniel G. OUELLETTE; Angeline K. SMITH; Justin S. BROCKMAN; Mark L. Doczy; Kaan OGUZ; Kevin P. O'brien; Brian S. Doyle; Oleg Golonzka; Tahir Ghani
Original assignee: Intel Corporation
Priority date: 2017-03-30
Filing date: 2017-03-30
Publication date: 2018-10-04

Abstract

An embodiment includes an apparatus comprising: a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier layer between the free and fixed layers; and first, second, and third layers; wherein: (a)(i) the second layer is between the first and third layers and the first layer is between the MTJ and the second layer, (a)(ii) first layer includes an oxide, the second layer includes both cobalt and iron, and the third layer includes a metal, and (a)(iii) the first layer includes perforations. Other embodiments are described herein.

Description

Spintronic Memory with Perforated Cap Layer

Technical Field

[0001] Embodiments of the invention are in the field of semiconductor devices and, in particular, memory.

Background

[0002] Some magnetic memories, such as a spin transfer torque memory (STTM), utilize a magnetic tunnel junction (MTJ) for switching and detection of the memory's magnetic state. Figure 1 includes spin transfer torque random access memory (STTRAM), a form of STTM. Figure 1 includes a MTJ consisting of ferromagnetic (FM) layers 125, 127 and tunneling barrier 126 (e.g., magnesium oxide (MgO)). The MTJ couples bit line (BL) 105 to selection switch 120 (e.g., transistor), word line (WL) 110, and sense line (SL) 115. Memory 100 is "read" by assessing the change of resistance (e.g., tunneling magnetoresi stance (TMR)) for different relative magnetizations of FM layers 125, 127.

[0003] More specifically, MTJ resistance is determined by the relative magnetization directions of layers 125, 127. When the magnetization directions between the two layers are anti-parallel, the MTJ is in a high resistance state. When the magnetization directions between the two layers are parallel, the MTJ is in a low resistance state. Layer 127 is the "reference layer" or "fixed layer" because its magnetization direction is fixed. Layer 125 is the "free layer" because its magnetization direction is changed by passing a driving current polarized by the reference layer (e.g., positive voltage applied to layer 127 rotates the magnetization direction of layer 125 opposite to that of layer 127 and negative voltage applied to layer 127 rotates the magnetization direction of layer 125 to the same direction of layer 127).

Brief Description of the Drawings

[0004] Features and advantages of embodiments of the present invention will become apparent from the appended claims, the following detailed description of one or more example embodiments, and the corresponding figures, in which:

[0005] Figure 1 depicts a conventional magnetic memory cell.

[0006] Figures 2-3 depict conventional MTJs.

[0007] Figure 4 includes a memory stack in an embodiment. [0008] Figures 5A, 5B, 5C, 5D include embodiments of free layers.

[0009] Figure 6A shows an image of a magnesium oxide layer (which is in a memory stack, not shown, that does not include a tungsten cap layer) and Figure 6B shows an image of a magnesium oxide layer (which is in a memory stack, not shown, that does include a tungsten cap layer) in an embodiment.

[0010] Figure 7 depicts a method of forming a memory in an embodiment.

[0011] Figure 8 includes a memory cell in an embodiment.

[0012] Figures 9, 10, 11 depict systems for use with embodiments.

Detailed Description

[0013] Reference will now be made to the drawings wherein like structures may be provided with like suffix reference designations. In order to show the structures of various embodiments more clearly, the drawings included herein are diagrammatic representations of integrated circuit structures. Thus, the actual appearance of the fabricated integrated circuit structures, for example in a photomicrograph or atom probe image, may appear different while still incorporating the claimed structures of the illustrated embodiments. Moreover, the drawings may only show the structures useful to understand the illustrated embodiments. Additional structures known in the art may not have been included to maintain the clarity of the drawings. "An embodiment", "various embodiments" and the like indicate embodiment s) so described may include particular features, structures, or characteristics, but not every embodiment necessarily includes the particular features, structures, or characteristics. Some embodiments may have some, all, or none of the features described for other embodiments. "First", "second", "third" and the like describe a common object and indicate different instances of like objects are being referred to. Such adjectives do not imply objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner. "Connected" may indicate elements are in direct physical or electrical contact with each other and "coupled" may indicate elements co-operate or interact with each other, but they may or may not be in direct physical or electrical contact. Also, while similar or same numbers may be used to designate same or similar parts in different figures, doing so does not mean all figures including similar or same numbers constitute a single or same embodiment. [0014] STTRAM, described above, is just one example of "beyond CMOS" technology (or "non-CMOS based" technology), which relates to devices and processes not entirely implemented with complementary metal-oxide-semiconductor (CMOS) techniques. Beyond CMOS technology may rely on spin polarization (which concerns the degree to which the spin or intrinsic angular momentum of elementary particles is aligned with a given direction) and, more generally, spintronics (a branch of electronics concerning the intrinsic spin of an electron, its associated magnetic moment, and the electron's fundamental electronic charge). Spintronics devices may concern TMR, which uses quantum-mechanical tunneling of electrons through a thin insulator to separate ferromagnetic layers, and STT, where a current of spin polarized electrons may be used to control the magnetization direction of ferromagnetic electrodes.

[0015] Beyond CMOS devices include, for example, spintronics devices implemented in memory (e.g., 3 terminal STTRAM), spin logic devices (e.g., logic gates), tunnel field-effect transistors (TFETs), impact ionization MOS (EVIOS) devices, nano-electro-mechanical switches (NEMS), negative common gate FETs, resonant tunneling diodes (RTD), single electron transistors (SET), spin FETs, nanomagnet logic (NML), domain wall logic, domain wall memory, magnetic sensors, and the like.

[0016] Regarding STTM specifically, one form of STTM includes perpendicular STTM (pSTTM). Where a traditional MTJ or non-perpendicular MTJ generates a magnetization "in plane" (with which "high" and "low" memory states are set), a perpendicular MTJ (pMTJ) generates magnetization "out of plane". This reduces the switching current needed to switch between high and low memory states. This also allows for better scaling (e.g., smaller size memory cells). Traditional MTJs are converted to pMTJs by, for example, thinning the free layer, thereby making the tunnel barrier/free layer interface more dominant in magnetic field influence (and the interface promotes anisotropic out of plane magnetization). The interface is highlighted with bold dashed lines and Ki in Figure 2 (and other figures included herein) which addresses the anisotropic energy at the interface. Figure 2 includes such a system 200 with cobalt, iron, boron (CoFeB) free layer 225 interfacing magnesium oxide (MgO) tunnel barrier 226, which further couples to CoFeB fixed layer 227 and Tantalum (Ta) contacts 214 (which may couple to a selection switch such as transistor 120 of Figure 1), 216 (which may couple, by way of one or more vias, to a bit line such as bit line 105 of Figure 1). [0017] Figure 3 depicts a system 300 with a MTJ, where a second oxidized MgO interface 320 (sometimes referred to as a "cap layer") contacts CoFeB free layer 325 (which further couples to a tunnel barrier MgO 326, which is formed on CoFeB fixed layer 327). Adding cap layer 320 may increase stability for the memory, which is a problem for devices such as the device of Figure 2. Thus, Figure 3 includes MgO at both free layer interfaces (i.e., layers 320, 326). However, introducing MgO layer 320 on top of CoFeB free layer 325 increases the memory's total resistance significantly (as compared to having just one oxide layer interface at the free layer as in Figure 2), which makes the design impractical for scaled devices (e.g., 22 nm) because of degradation in resistance-area (RA) product and TMR. In other words, if MgO layer 326 is predominately responsible for resistance and voltage drop in conventional MTJs, adding yet another layer of MgO in series with layer 326 increases RA product, thereby driving up write voltage, decreasing battery life, decreasing TMR, and the like.

[0018] RA product refers to a measurement unequal to resistivity. Resistivity has units in ohm-cm, whereas RA product has units in ohm-um² (and is based on material resistivity (p), dot area (A), and MgO thickness (T_Mgo) such that increasing MgO thickness exponentially increases the RA of the device). While resistivity represents an "inherent resistance" and is independent of the thickness of a material layer, RA product is exponentially proportional to the thickness of the material (e.g., MgO thickness). (Regarding "thickness", layer 320 is disposed "horizontally" for purposes of discussion herein and has a "thickness" in the vertical orientation. The length and width for layer 320 are "in plane" and the height or thickness is "out of plane".)

[0019] Returning to Figure 3, a higher RA product increases STTM resistance. While this does not necessarily increase write current, a higher RA product does increase write voltage (write voltage = Jc * RA product)(Jc refers to a critical switching current density to write a bit), which may be problematic for switching devices (e.g., transistor 120 of Figure 1) which have voltage restrictions. Also, a larger STTM resistance degrades current provided by a select transistor (e.g., MOS transistor 120 of Figure 1) since the Gate-to- Source voltage is smaller due to the larger IR drop across the STTM resistance. Further, there is RA contribution from layers 320 and 326. While increasing the RA from layer 326 will not lower TMR, increasing the RA from layer 320 will lower TMR (and decreasing the RA from layer 320 will increase TMR). [0020] The addition of cap layer 320 provides additional issues. Applicant has determined the boron component of free layer 325 plays a critical role in TMR determination. Specifically, the storage layer of pSTTM 300 is composed of the CoFeB alloy of free layer 325. The boron is necessary to have an amorphous CoFeB film when the film is deposited. The amorphous film is then crystallized based on an oriented dielectric tunnel barrier (layer 326). This crystallization of CoFe in layer 325 helps increase TMR for memory 300 and decrease series resistance. For optimal crystallization of CoFe, however, boron needs to have an escape path from layer 325 (otherwise crystallization of CoFe is hindered and TMR decreases and perpendicular magnetic anisotropy (PMA) decreases). This escape path is obstructed in Figure 3. Specifically, the storage layer 325 is capped with MgO layer 320 (to increase PMA) but the MgO cap layer 320 also prevents the boron from escaping from the CoFeB of layer 325 (which hinders crystallization of free layer 325 thereby decreasing TMR).

[0021] However, an embodiment addresses this issue by providing an escape path for boron in the free layer, which promotes better crystallization of the free layer (which in turn increases TMR and PMA and decreases resistance). An embodiment includes a cap layer (such as MgO cap layer 320) with a boron escape path while still providing the cap layer at a thickness that maintains beneficial PMA associated with the cap layer.

[0022] In addition, providing the boron escape path increases thermal stability, which is a metric associated with the retention of stored data in pSTTM devices for certain period of time at certain environmental conditions. Thermal stability, as used herein, is determined as follows:

_{Δ =} _^ ₌ «effV

k_BT k_BT where K_eff is effective PMA of the storage layer, V is the volume of the layer, T is temperature, E denotes the energy barrier between two magnetization configurations of the MTJ, and k_B is Boltzmann constant. The thermal stability Δ is directly related to K_eff.

[0023] An embodiment provides the boron escape path by including a perforated cap layer to assist boron escape from the free layer and reduce the series resistance of the cap layer without compromising the PMA the MgO cap layer provides. In an embodiment a thin layer of tungsten (W) is inserted between the free layer and the upper contact/electrode layer. The presence of a tungsten layer causes tungsten to perforate the MgO cap. The perforated MgO cap causes a greater percentage of the resistance drop to occur across the spin filter (i.e., tunnel barrier), which increases TMR. For instance, in an embodiment the perforated MgO cap improves TMR by 50% and reduces the RA by 40%.

[0024] Figure 4 includes an embodiment. Memory 400 includes MTJ 411 including a free magnetic layer 405, a fixed magnetic layer 403, and a tunnel barrier layer 404. Memory 400 further includes first layer 406, second layer 407, and third layer 408. First layer 406 may include a cap layer similar to layer 320 of Figure 3. As explained above, the cap layer promotes PMA but also adds series resistance. However, the embodiment addresses the undesirable aspects of the cap layer (e.g., higher resistance) with the second and third layers.

[0025] Second layer 407 includes, in an embodiment, generally the same chemical composition as the free layer. Thus, for memory 400 layers 405 and 407 both include CoFe and an amount of boron that may vary depending on how much of the boron has migrated from the layer 405 and/or layer 407.

[0026] Third layer 408 includes a metal, such as tungsten. The metal of layer 408 is relatively heavy in terms of atomic number (Z) such that its deposition (e.g., sputtering via physical vapor deposition (PVD) in some embodiments but not so limited in other embodiments) carries enough energy (due to the large Z) that the tungsten atoms cause fracturing or perforations 412, 413 within the CoFeB layer 407 and/or the cap layer 406. These fractures lower the resistance of the cap layer 406 while not overly negating the contributions of PMA provided by the cap layer.

[0027] In an embodiment, the first layer 406 includes an oxide such as magnesium oxide and/or aluminum oxide. While the above example indicates layer 408 includes tungsten, in other embodiments the metal in layer 408 includes hafnium, tantalum, platinum, iridium, molybdenum, or combinations thereof. For example, layer 408 may include hafnium or an alloy thereof. As another example, layer 408 may include an alloy comprising two or more of hafnium, tantalum, tungsten, platinum, iridium, and molybdenum.

[0028] In an embodiment, due to perforations 412, 413 the free layer 405 may include both iron and cobalt and boron as well. However, some or all of the boron originally in layer 405 may have migrated into layers 406, 407, and/or 408 and/or layers above 408. Also, boron originally in layer 407 (or which has migrated into layer 407) may also migrate to other layers such as layers 406 and/or 408 and/or layers above layer 408.

[0029] As shown in Figure 4, in an embodiment at least some of the perforations 412, 413 extend from the third layer 408 into layer 407 and, in some embodiments, layer 406. The perforations may taper or narrow as they descend from layer 408 towards layers 407 and 406. This is due to the perforations (which may be similar to cracks) being wider closer to the area of impact for sputtered or otherwise deposited metal (e.g., tungsten) atoms. Thus, the width of a perforation, such as perforation 412, is wider in layer 407 than layer 406.

[0030] In an embodiment, a perforation may include the metal of layer 408 (e.g., tungsten) and/or boron that migrated from layer 405. In an embodiment each of the first 406 and second 407 layers includes the metal from layer 408, but layer 408 includes more of the metal than either of layers 406, 407. As a result the first layer 406 may include a metal (e.g., tungsten) from layer 408 and the third layer 408 may also include the metal but layer 408 includes more of the metal (in terms of atomic mass) than layer 406. In an embodiment the second layer 407 includes tungsten but the third layer 408 includes more tungsten than the second layer. However, the perforations may also include a void including no material or at least not including the metal of layer 408 or boron from layer 405. Thus, imaging the perforations may not show tungsten but instead may only show a perforation caused by tungsten (or some other heavy Z metal included in layer 408).

[0031] Figure 6 A shows an atom probe tomography (APT) reconstruction of magnesium atoms in an MgO cap layer similar to layer 406. Specifically, a layer similar to CoFeB layer 407 is directly on top of a cap layer similar to layer 406— but there is no layer similar to layer 408. For instance, there is no tungsten layer on the CoFeB and cap layers. As a result, in Figure 6A there is a large amount of MgO in the cap layer without perforations or discontinuities. The image in Figure 6A is largely homogenous and shows a largely continuous layer of magnesium. However, when an embodiment similar to memory 400 is used (i.e., a tungsten layer 408 on a CoFeB layer 407, the CoFeB layer 407 on an MgO cap layer 406, the MgO cap layer 406 on CoFeB free layer 405) there are many magnesium discontinuities/perforations 612 in the MgO cap layer. Figure 6B shows absences 612 of magnesium, which are indicative of perforations in this particular instance. Those perforations may be empty (e.g., have no material in them) or may have boron or tungsten within them. The image of Figure 6B (which directly shows morphology of a layer but does not directly show the material composition of a layer) does not show any boron or tungsten that may be present in the perforations 612 because the APT was not programmed to image those materials (i.e., Figure 6B was programmed to image the presence of magnesium, not boron or tungsten). Thus, in Figure 6B there are spaces 612 of zero or very low density for magnesium atoms (which are indicative of perforations in the magnesium oxide cap layer). Also, while not shown, current in-plane tunneling (CIPT) electrical data may be used to show a reduction in total stack resistance with a tungsten cap (e.g., a stack similar to stack 400) versus a stack with no such tungsten cap. Notably, Figure 6A includes an area 612' indicating a less dense area of magnesium, which may be expected with real world imaging. However, the amount of discontinuity in 612 (Figure 6B) is clearly larger than the amount of discontinuity in the image portion 612' (Figure 6A) thereby indicating the presence of perforations (Figure 6B) rather than a possible imaging anomaly (Figure 6A).

[0032] The perforation, such as either of perforations 412, 413, may be contiguous or noncontiguous. For example, when the perforation is imaged (e.g., with a technique such as APT) the resulting image may show individual pockets of magnesium discontinuities or chains. In other embodiments the image may show extended absences of magnesium that extend from a top of the cap layer to a bottom of the cap layer. Thus, a "perforation" as used herein is not to be construed in a literal sense entailing, for example, a regularly spaced group of weakened portions (like a line of perforations on a perforated sheet of paper) but instead entails absences of atoms (e.g., magnesium atoms in a cap layer). These absences of magnesium may have been created directly by tungsten atoms or may have been created indirectly by tungsten atoms. For example regarding indirect causation, an absence of magnesium in a lower portion of the cap layer near the free layer may be caused by the impact of tungsten near an upper portion of the cap layer 406 adjacent layer 407. For at least this reason, relatively heavy metals (e.g., metals with a Z greater than 42) are used in some embodiments due to their ability to cause an amount of damage (due to their Z value) to the oxide that reduces the resistance of the oxide while still retaining some or all of the PMA offered by the oxide cap layer.

[0033] Returning to Figure 4, in the embodiment of memory 400 at least one of the perforations (i.e., perforation 413) extends to a surface 406' of the free layer. Such an extension may more easily facilitate boron movement from free layer 405 than a perforation that does not extend all the way a bottom of the cap layer.

[0034] Regarding boron movement, due to the boron movement facilitated by perforations 412 and/or 413 free layer 405 is better able to convert from its deposited amorphous stage to a crystallized stage. Thus, in an embodiment a majority of the free layer is crystallized and non-amorphous. The high level of crystallization leads to higher TMR. For instance, the TMR for memory 400 may be less than 30% when layer 405 is amorphous but the TMR for memory 400 increases to over 100% when layer 405 is crystallized.

[0035] In an embodiment, layer 406 directly contacts both the free layer 405 and the second layer 407. In an embodiment, the second layer 407 directly contacts the third layer 408. In an embodiment, layer 406 directly contacts both the free layer 405 and the second layer 407 and second layer 407 directly contacts the third layer 408. In an embodiment electrode layer 410 directly contacts third layer 408.

[0036] In an embodiment contact layers 401, 410 each include a metal such as tantalum and/or ruthenium. An embodiment may include a pinning layer 402, otherwise known as a Synthetic Antiferromagnetic layer (SAF).

[0037] In an embodiment the first layer 406 includes a first thickness 416, the second layer 407 includes a second thickness 417 that is less than the first thickness 416; and the third layer 408 includes a third thickness 418 that is less than the first thickness 416. For example, in an embodiment thickness 418 may be 1-10 angstroms (however in other embodiments the thickness is less than 3, 5, 7, 9, or 11 angstroms), thickness 417 may be 1-10 angstroms (however in other embodiments the thickness is less than 3, 5, 7, 9 or 11 angstroms), and thickness 416 may be 10-20 angstroms (however in other embodiments the thickness is less than 12, 14, 16, 18, 22 or 24 angstroms). The above thicknesses address an advantage of embodiments regarding the critical nature of thicknesses for layers 406, 407, 408. The metal of layer 408 fractures the oxide of layer 406 (thereby decreasing resistance of layer 406), which allows for a thicker than normal cap layer 406 (thereby increasing PMA due to cap layer 406). Layer 406 is 2-5 angstroms thicker than many conventional cap layers. Also, limiting the thickness of layer 407 ensures the magnetic nature of layer 407 does not conflict or overwhelm the magnetic nature of free layer 405. For instance, keeping layer 407 less than 10 angstroms helps ensure layer 407 does not act as an active magnet in competition with free layer 405. However, the layer 407 must be thick enough to ensure there is not excessive perforation of the cap layer by metal from layer 408. More generally, the thicknesses of layers 406, 407, 408 are critical values in some embodiments in order to achieve a proper RA product and TMR levels.

[0038] Various embodiments may be used with various forms of free layers. For example, in Figure 5A the free layer is a single layer 501 (approximately 1.5 nm thick) including CoFeB. Figure 5B includes an embodiment where the free layer is a composite layer including a first layer 511 (approximately 1.55 nm thick) comprising boron and a second layer 512 (approximately 0.3 nm thick) comprising tungsten. Figure 5C includes an embodiment where the free layer is a composite layer including a first layer 521 (approximately 1.55 nm thick) comprising boron, a second layer 522 comprising tungsten (approximately 0.3 nm thick), and a third layer 523 (approximately 0.3 nm thick) comprising boron. Figure 5D includes an embodiment wherein (a) the free layer is a composite layer including first layer 531 (approximately 0.5 nm thick) and second layer 532 (approximately 0.4 nm thick), (b) the first layer is between the second layer and the tunnel barrier layer (not shown), and (c) the first layer includes a chemical composition with a higher percentage of boron (e.g., 30%) than a chemical composition of the second layer (e.g., 20%). Any of the exemplary free layers in any of Figures 5 A, 5B, 5C, 5D may be substituted for layer 405 of the embodiment of Figure 4.

[0039] In an embodiment the free layer is a composite layer including first and second layers, the first layer is between the second layer and the tunnel barrier layer, and the first layer is primarily located in a plane and has a thickness, orthogonal to the plane, that is thicker than the second layer. For instance, in Figure 5D layer 531 has a thickness 541 (e.g., 0.5 nm) that is thicker than thickness 542 (e.g., 0.4 nm) for layer 532.

[0040] Figure 4 is an example of an embodiment whereby a layer with a relatively high Z metal (e.g., tungsten) is formed in combination with a cap layer. The high Z metal perforates the cap layer. An intermediary layer (layer 407) may be included to help control the level of perforation. For example, some embodiments may not include layer 407 but others may use such a layer to ensure there is not excessive perforation of the cap layer. Such a combination of layers (e.g., layers 406, 407, 408) produces increased stability without unnecessarily increasing RA product and/or decreasing TMR (as is the case with the dual MgO layers found in Figure 3). In other words, this arrangement of layers induces greater stability without overly increasing RA product (which may adversely affect write/read voltages) or diminishing TMR (which may complicate accurate reads of memory states).

[0041] Figure 8 depicts an embodiment wherein memory 800 comprises a perpendicular STTM that includes MTJ 811. The MTJ has PMA. The memory cell includes a IT- IX (T = transistor, X = capacitor or resistor) at a small cell size. The MTJ comprises contacts 801, 810, pinning layer 802, fixed layer 803, tunnel barrier layer 804, free layer 805, cap layer 806, CoFeB layer 807, and a layer including a metal (e.g., tungsten) 808. The MTJ couples bit line 825 to selection switch 821 (e.g., transistor), word line 820, and sense line 815. The MTJ may be located on a substrate.

[0042] In an embodiment, the substrate is a bulk semiconductive material as part of a wafer. In an embodiment, the semiconductive substrate is a bulk semiconductive material as part of a chip that has been singulated from a wafer. In an embodiment, the semiconductive substrate is a semiconductive material that is formed above an insulator such as a semiconductor on insulator (SOI) substrate. There may be one or more layers between the MTJ and the substrate. There may be one or more layers above the MTJ.

[0043] Figure 7 includes a method 700 in an embodiment. Block 701 includes forming a MTJ including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier layer. Block 702 includes forming a first layer between the MTJ and a second layer, the first layer including an oxide and the second layer including both cobalt and iron. Block 703 includes forming a third layer on the second layer, the third layer including a metal selected from the group consisting of hafnium, tantalum, tungsten, platinum, iridium, molybdenum, or combinations thereof. Block 704 includes forming perforations in the first and second layers in response to forming the third layer.

[0044] Referring now to Figure 9, shown is a block diagram of an example system with which embodiments can be used. As seen, system 900 may be a smartphone or other wireless communicator or any Internet of Things (IoT) device. A baseband processor 905 is configured to perform various signal processing with regard to communication signals to be transmitted from or received by the system. In turn, baseband processor 905 is coupled to an application processor 910, which may be a main CPU of the system to execute an OS and other system software, in addition to user applications such as many well-known social media and multimedia apps. Application processor 910 may further be configured to perform a variety of other computing operations for the device.

[0045] In turn, application processor 910 can couple to a user interface/display 920 (e.g., touch screen display). In addition, application processor 910 may couple to a memory system including a non-volatile memory, namely a flash memory 930 (which may include memory cells such as those described in Figures 4 and/or 8) and a system memory, namely a DRAM 935 (which may include memory cells such as those described in Figures 4 and/or 8). In some embodiments, flash memory 930 may include a secure portion 932 (which may include memory cells such as those described in Figures 4 and/or 8) in which secrets and other sensitive information may be stored. As further seen, application processor 910 also couples to a capture device 945 such as one or more image capture devices that can record video and/or still images.

[0046] A universal integrated circuit card (UICC) 940 comprises a subscriber identity module, which in some embodiments includes a secure storage 942 (which may include memory cells such as those described in Figures 4 and/or 8) to store secure user information. System 900 may further include a security processor 950 (e.g., Trusted Platform Module (TPM)) that may couple to application processor 910. A plurality of sensors 925, including one or more multi-axis accelerometers may couple to application processor 910 to enable input of a variety of sensed information such as motion and other environmental information. In addition, one or more authentication devices 995 may be used to receive, for example, user biometric input for use in authentication operations.

[0047] As further illustrated, a near field communication (NFC) contactless interface 960 is provided that communicates in a NFC near field via an NFC antenna 965. While separate antennae are shown, understand that in some implementations one antenna or a different set of antennae may be provided to enable various wireless functionalities.

[0048] A power management integrated circuit (PMIC) 915 couples to application processor 910 to perform platform level power management. To this end, PMIC 915 may issue power management requests to application processor 910 to enter certain low power states as desired. Furthermore, based on platform constraints, PMIC 915 may also control the power level of other components of system 900.

[0049] To enable communications to be transmitted and received such as in one or more IoT networks, various circuitries may be coupled between baseband processor 905 and an antenna 990. Specifically, a radio frequency (RF) transceiver 970 and a wireless local area network (WLAN) transceiver 975 may be present. In general, RF transceiver 970 may be used to receive and transmit wireless data and calls according to a given wireless communication protocol such as 3G or 4G wireless communication protocol such as in accordance with a code division multiple access (CDMA), global system for mobile communication (GSM), long term evolution (LTE) or other protocol. In addition a GPS sensor 980 may be present, with location information being provided to security processor 950 for use as described herein when context information is to be used in a pairing process. Other wireless communications such as receipt or transmission of radio signals (e.g., AM/FM) and other signals may also be provided. In addition, via WLAN transceiver 975, local wireless communications, such as according to a Bluetooth™ or IEEE 802.11 standard can also be realized.

[0050] Referring now to Figure 10, shown is a block diagram of a system in accordance with another embodiment of the present invention. Multiprocessor system 1000 is a point-to- point interconnect system such as a server system, and includes a first processor 1070 and a second processor 1080 coupled via a point-to-point interconnect 1050. Each of processors 1070 and 1080 may be multicore processors such as SoCs, including first and second processor cores (i.e., processor cores 1074a and 1074b and processor cores 1084a and 1084b), although potentially many more cores may be present in the processors. In addition, processors 1070 and 1080 each may include a secure engine 1075 and 1085 to perform security operations such as attestations, IoT network onboarding or so forth.

[0051] First processor 1070 further includes a memory controller hub (MCH) 1072 and point-to-point (P-P) interfaces 1076 and 1078. Similarly, second processor 1080 includes a MCH 1082 and P-P interfaces 1086 and 1088. MCH's 1072 and 1082 couple the processors to respective memories, namely a memory 1032 and a memory 1034, which may be portions of main memory (e.g., a DRAM) locally attached to the respective processors. These memories may include memory cells such as those described in Figures 4 and/or 8. First processor 1070 and second processor 1080 may be coupled to a chipset 1090 via P-P interconnects 1052 and 1054, respectively. Chipset 1090 includes P-P interfaces 1094 and 1098.

[0052] Furthermore, chipset 1090 includes an interface 1092 to couple chipset 1090 with a high performance graphics engine 1038, by a P-P interconnect 1039. In turn, chipset 1090 may be coupled to a first bus 1016 via an interface 1096. Various input/output (I/O) devices 1014 may be coupled to first bus 1016, along with a bus bridge 1018 which couples first bus 1016 to a second bus 1020. Various devices may be coupled to second bus 1020 including, for example, a keyboard/mouse 1022, communication devices 1026 and a data storage unit 1028 such as a non-volatile storage or other mass storage device (which may include memory cells such as those described in Figures 4 and/or 8). As seen, data storage unit 1028 may include code 1030, in one embodiment. As further seen, data storage unit 1028 also includes a trusted storage 1029 (which may include memory cells such as those described in Figures 4 and/or 8) to store sensitive information to be protected. Further, an audio I/O 1024 may be coupled to second bus 1020.

[0053] Embodiments may be used in environments where IoT devices may include wearable devices or other small form factor IoT devices. Referring now to Figure 11, shown is a block diagram of a wearable module 1300 in accordance with another embodiment. In one particular implementation, module 1300 may be an Intel® Curie™ module that includes multiple components adapted within a single small module that can be implemented as all or part of a wearable device. As seen, module 1300 includes a core 1310 (of course in other embodiments more than one core may be present). Such core may be a relatively low complexity in-order core, such as based on an Intel Architecture® Quark™ design. In some embodiments, core 1310 may implement a TEE as described herein. Core 1310 couples to various components including a sensor hub 1320, which may be configured to interact with a plurality of sensors 1380, such as one or more biometric, motion environmental or other sensors. A power delivery circuit 1330 is present, along with a non-volatile storage 1340 (which may include memory cells such as those described in Figures 4 and/or 8). In an embodiment, this circuit may include a rechargeable battery and a recharging circuit, which may in one embodiment receive charging power wirelessly. One or more input/output (IO) interfaces 1350, such as one or more interfaces compatible with one or more of USB/SPI/I2C/GPIO protocols, may be present. In addition, a wireless transceiver 1390, which may be a Bluetooth™ low energy or other short-range wireless transceiver is present to enable wireless communications as described herein. Understand that in different implementations a wearable module can take many other forms. Wearable and/or IoT devices have, in comparison with a typical general purpose CPU or a GPU, a small form factor, low power requirements, limited instruction sets, relatively slow computation throughput, or any of the above.

[0054] While several embodiments herein describe perpendicular STTM, other embodiments are not so limited and may concern in plane (non-perpendicular) STTM, as well as embodiments that are neither fully in plane (non-perpendicular) nor fully out of plane (perpendicular) but are instead something in between in plane and out of plane.

[0055] At times herein an upper layer (e.g., layer 408) is said to "directly contact" a lower layer (e.g., layer 407). This includes situations where one considers, for example, the upper layer to be a sublayer of another layer. Further, for instance, the lower layer may include oxidation at its surface/interface to the upper layer. Such a situation would still comprise an upper layer directly contacting the lower layer despite the lower layer including surface oxidation.

[0056] While several embodiments include layers comprising CoFeB (e.g., layers 403, 405, 407) other embodiments may include some combination of the layers 403, 405, 407 including CoFe/CoFeB (e.g., two of the three layers include CoFe and the other includes CoFeB or one or more of the layers includes both CoFe and CoFeB); CoFeB/Ta/CoFeB; or CoFe/CoFeB/Ta/CoFeB/CoFe. Further, other embodiments may include tunnel barriers having something other than MgO, such as other oxides (e.g., aluminum oxide). In an embodiment layers 403, 405, 407 may include FeB (and may not include cobalt).

[0057] The following examples pertain to further embodiments.

[0058] Example 1 includes an apparatus comprising: a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier layer between the free and fixed layers; and first, second, and third layers; wherein: (a)(i) the second layer is between the first and third layers and the first layer is between the MTJ and the second layer, (a)(ii) first layer includes an oxide, the second layer includes both cobalt and iron, and the third layer includes a metal, and (a)(iii) the first layer includes perforations.

[0059] However, in other embodiments the second layer may not include cobalt.

[0060] Example 2 includes the apparatus of claim 1 wherein the metal is selected from the group consisting of hafnium, tantalum, tungsten, platinum, iridium, molybdenum, or combinations thereof.

[0061] Example 3 includes the apparatus of claim 2 wherein the metal includes tungsten.

[0062] Example 4 includes the apparatus of claim 3 wherein: the first layer includes at least one of magnesium oxide and aluminum oxide; the free layer includes both iron and cobalt; and the first layer includes boron.

[0063] However, in other versions of example 4 the free layer may not include cobalt.

[0064] Another version of example 4 includes the apparatus of claim 3 wherein the first layer includes boron and at least one of magnesium oxide and aluminum oxide; and the free layer includes both iron and cobalt. The boron may be included in an upper half of the first layer (wherein the upper half is adjacent the 2^nd layer and a lower half of the first layer is adjacent the free layer).

[0065] Example 5 includes the apparatus of claim 4 wherein the second layer includes at least one of the perforations.

[0066] Example 6 includes the apparatus of claim 5, wherein: the first layer is primarily located in a plane; the at least one of the perforations includes a width, parallel to the plane, that has a first width in the first layer and a second width in the second layer; the second width is wider than the first width.

[0067] Example 7 includes the apparatus of claim 4 wherein at least one of the perforations includes at least one of the metal and boron.

[0068] Example 8 includes the apparatus of claim 4 wherein at least one of the perforations includes a void that does not include the metal and does not include boron. [0069] Example 9 includes the apparatus of claim 3 wherein the first layer directly contacts both the free layer and the second layer.

[0070] Example 10 includes the apparatus of claim 9 wherein the second layer directly contacts the third layer.

[0071] Example 11 includes the apparatus of claim 3 wherein the first layer includes tungsten and the third layer includes more tungsten than the first layer.

[0072] Example 12 includes the apparatus of claim 3 wherein the second layer includes tungsten and the third layer includes more tungsten than the second layer.

[0073] Example 13 includes the apparatus of claim 3 wherein the third layer includes boron.

[0074] Example 14 includes the apparatus of claim 2 wherein each of the first and second layers includes the metal.

[0075] Example 15 includes the apparatus of claim 2, wherein: the first layer is primarily located in a plane and includes a first thickness measured orthogonal to the plane; the second layer includes a second thickness that is less than the first thickness; and the third layer includes a third thickness that is less than the first thickness.

[0076] Example 16 includes the apparatus of claim 2 wherein: (a) the free layer is a composite layer including additional first and second layers, (b) the additional first layer is between the additional second layer and the tunnel barrier layer, and (c) the additional first layer is primarily located in a plane and has a thickness, orthogonal to the plane, that is thicker than the additional second layer.

[0077] Example 17 includes the apparatus of claim 2 wherein the free layer is not a composite layer and includes a single layer.

[0078] Example 18 includes the apparatus of claim 2 wherein the free layer is a composite layer including an additional first layer comprising boron and an additional second layer comprising tungsten.

[0079] Example 19 includes the apparatus of claim 2 wherein (a) the free layer is a composite layer including additional first and second layers, (b) the additional first layer is between the additional second layer and the tunnel barrier layer, and (c) the additional first layer includes a material composition with a higher percentage of boron than a material composition of the additional second layer.

[0080] Example 20 includes the apparatus of claim 2 wherein a majority of the free layer is crystallized and non-amorphous.

[0081] Example 21 includes the apparatus of claim 2 wherein at least one of the perforations extends to a surface of the free layer.

[0082] For example, the perforation may extend from a top of the first layer to a bottom of the first layer (wherein the bottom directly contacts the surface of the free layer).

[0083] Example 22 includes the apparatus of claim 2 comprising an electrode layer directly contacting the third layer.

[0084] Example 23 includes the apparatus of claim 1 comprising a perpendicular spin torque transfer memory (STTM) that includes the MTJ, wherein the MTJ has perpendicular anisotropy.

[0085] Example 24 includes a method comprising: forming a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier layer between the free and fixed layers; and forming a first layer between the MTJ and a second layer, the first layer including an oxide and the second layer including both cobalt and iron; forming a third layer on the second layer, the third layer including a metal selected from the group consisting of hafnium, tantalum, tungsten, platinum, iridium, molybdenum, or combinations thereof; and forming perforations in the first and second layers in response to forming the third layer.

[0086] However, in other embodiments the second layer may not include cobalt.

[0087] Example 25 includes the method of example 24, wherein: the first layer is primarily located in a plane; the at least one of the perforations includes a width, parallel to the plane, that has a first width in the first layer and a second width in the second layer; the second width is wider than the first width. [0088] Example 26 includes a system comprising: a processor; and a memory, coupled to the processor, according to any one of examples 1 to 22; wherein the memory comprises a perpendicular spin torque transfer memory (STTM) that includes the MTJ.

[0089] Example 27 includes the apparatus according to any of examples 1 to 2 and 3 to 22 wherein the metal includes tungsten.

[0090] Example 28 includes the apparatus according to any of examples 1 to 3 and 5 to 22 wherein: the first layer includes boron and at least one of magnesium oxide and aluminum oxide; and the free layer includes both iron and cobalt.

[0091] Example 29 includes the apparatus according to any of examples 1 to 4 and 6 to 22 wherein the second layer includes at least one of the perforations.

[0092] Example 30 includes the apparatus according to any of examples 1 to 5 and 7 to 22, wherein: the first layer is primarily located in a plane; at least one of the perforations includes a width, parallel to the plane, that has a first width in the first layer and a second width in the second layer; the second width is wider than the first width.

[0093] Example 31 includes the apparatus according to any of examples 1 to 6 and 8 to 22 wherein at least one of the perforations includes at least one of the metal and boron.

[0094] Example 32 includes the apparatus according to any of examples 1 to 7 and 9 to 22 wherein at least one of the perforations includes a void that does not include the metal and does not include boron.

[0095] Example 33 includes the apparatus according to any of examples 1 to 8 and 10 to 22 wherein the first layer directly contacts both the free layer and the second layer.

[0096] Example 34 includes the apparatus according to any of examples 1 to 9 and 11 to 22 wherein the second layer directly contacts the third layer.

[0097] Example 35 includes the apparatus according to any of examples 1 to 3, 5 to 10, and 12 to 22 wherein the first layer includes tungsten and the third layer includes more tungsten than the first layer. [0098] Example 36 includes the apparatus according to any of examples 1 to 11 and 13 to 22 wherein the second layer includes tungsten and the third layer includes more tungsten than the second layer.

[0099] Example 37 includes the apparatus according to any of examples 1 to 12 and 14 to 22 wherein the third layer includes boron.

[0100] Example 38 includes the apparatus according to any of examples 1 to 13 and 15 to 22 wherein each of the first and second layers includes the metal.

[0101] Example 39 includes the apparatus according to any of examples 1 to 14 and 16 to 22, wherein: the first layer is primarily located in a plane and includes a first thickness measured orthogonal to the plane; the second layer includes a second thickness that is less than the first thickness; and the third layer includes a third thickness that is less than the first thickness.

[0102] Example 40 includes the apparatus according to any of examples 1 to 15 and 20 to 22 wherein: (a) the free layer is a composite layer including additional first and second layers, (b) the additional first layer is between the additional second layer and the tunnel barrier layer, and (c) the additional first layer is primarily located in a plane and has a thickness, orthogonal to the plane, that is thicker than the additional second layer.

[0103] Example 41 includes the apparatus according to any of examples 1 to 15 and 20 to 22 wherein the free layer is not a composite layer and includes a single layer.

[0104] Example 42 includes the apparatus according to any of examples 1 to 15 and 20 to 22 wherein the free layer is a composite layer including an additional first layer comprising boron and an additional second layer comprising tungsten.

[0105] Example 43 includes the apparatus according to any of examples 1 to 15 and 20 to 22 wherein (a) the free layer is a composite layer including additional first and second layers, (b) the additional first layer is between the additional second layer and the tunnel barrier layer, and (c) the additional first layer includes a material composition with a higher percentage of boron than a material composition of the additional second layer.

[0106] Example 44 includes the apparatus according to any of examples 1 to 19 and 21 to 22 wherein a majority of the free layer is crystallized and non-amorphous. [0107] Example 45 includes the apparatus according to any of examples 1 to 20 and 22 wherein at least one of the perforations extends to a surface of the first layer, the surface directly contacting the free layer.

[0108] Example 46 includes the apparatus according to any of examples 1 to 21 comprising an electrode layer directly contacting the third layer.

[0109] Example 47 includes a system comprising: a processor; and a memory, coupled to the processor, according to example 1; wherein the memory comprises a perpendicular spin torque transfer memory (STTM) that includes the MTJ.

[0110] The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. This description and the claims following include terms, such as left, right, top, bottom, over, under, upper, lower, first, second, etc. that are used for descriptive purposes only and are not to be construed as limiting. For example, terms designating relative vertical position refer to a situation where a device side (or active surface) of a substrate or integrated circuit is the "top" surface of that substrate; the substrate may actually be in any orientation so that a "top" side of a substrate may be lower than the "bottom" side in a standard terrestrial frame of reference and still fall within the meaning of the term "top." The term "on" as used herein (including in the claims) does not indicate that a first layer "on" a second layer is directly on and in immediate contact with the second layer unless such is specifically stated; there may be a third layer or other structure between the first layer and the second layer on the first layer. The embodiments of a device or article described herein can be manufactured, used, or shipped in a number of positions and orientations. Persons skilled in the relevant art can appreciate that many modifications and variations are possible in light of the above teaching. Persons skilled in the art will recognize various equivalent combinations and substitutions for various components shown in the Figures. It is therefore intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.

Claims

What is claimed is:

1. An apparatus comprising:

a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier layer between the free and fixed layers; and

first, second, and third layers;

wherein: (a)(i) the second layer is between the first and third layers and the first layer is between the MTJ and the second layer, (a)(ii) first layer includes an oxide, the second layer includes both cobalt and iron, and the third layer includes a metal, and (a)(iii) the first layer includes perforations.

2. The apparatus of claim 1 wherein the metal is selected from the group consisting of hafnium, tantalum, tungsten, platinum, iridium, molybdenum, or combinations thereof.

3. The apparatus of claim 2 wherein the metal includes tungsten.

4. The apparatus of claim 3 wherein:

the first layer includes boron and at least one of magnesium oxide and aluminum oxide; and

the free layer includes both iron and cobalt.

5. The apparatus of claim 4 wherein the second layer includes at least one of the perforations.

6. The apparatus of claim 5, wherein:

the first layer is primarily located in a plane;

at least one of the perforations includes a width, parallel to the plane, that has a first width in the first layer and a second width in the second layer;

the second width is wider than the first width.

7. The apparatus of claim 4 wherein at least one of the perforations includes at least one of the metal and boron.

8. The apparatus of claim 4 wherein at least one of the perforations includes a void that does not include the metal and does not include boron.

9. The apparatus of claim 3 wherein the first layer directly contacts both the free layer and the second layer.

10. The apparatus of claim 9 wherein the second layer directly contacts the third layer.

11. The apparatus of claim 3 wherein the first layer includes tungsten and the third layer includes more tungsten than the first layer.

12. The apparatus of claim 3 wherein the second layer includes tungsten and the third layer includes more tungsten than the second layer.

13. The apparatus of claim 3 wherein the third layer includes boron.

14. The apparatus of claim 2 wherein each of the first and second layers includes the metal.

15. The apparatus of claim 2, wherein:

the first layer is primarily located in a plane and includes a first thickness measured orthogonal to the plane;

the second layer includes a second thickness that is less than the first thickness; and the third layer includes a third thickness that is less than the first thickness.

16. The apparatus of claim 2 wherein: (a) the free layer is a composite layer including additional first and second layers, (b) the additional first layer is between the additional second layer and the tunnel barrier layer, and (c) the additional first layer is primarily located in a plane and has a thickness, orthogonal to the plane, that is thicker than the additional second layer.

17. The apparatus of claim 2 wherein the free layer is not a composite layer and includes a single layer.

18. The apparatus of claim 2 wherein the free layer is a composite layer including an additional first layer comprising boron and an additional second layer comprising tungsten.

19. The apparatus of claim 2 wherein (a) the free layer is a composite layer including additional first and second layers, (b) the additional first layer is between the additional second layer and the tunnel barrier layer, and (c) the additional first layer includes a material composition with a higher percentage of boron than a material composition of the additional second layer.

20. The apparatus of claim 2 wherein a majority of the free layer is crystallized and non- amorphous.

21. The apparatus of claim 2 wherein at least one of the perforations extends to a surface of the first layer, the surface directly contacting the free layer.

22. The apparatus of claim 2 comprising an electrode layer directly contacting the third layer.

23. A system comprising:

a processor; and

a memory, coupled to the processor, according to any one of claims 1 to 22;

wherein the memory comprises a perpendicular spin torque transfer memory (STTM) that includes the MTJ.

24. A method comprising:

forming a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier layer between the free and fixed layers; and

forming a first layer between the MTJ and a second layer, the first layer including an oxide and the second layer including both cobalt and iron; forming a third layer on the second layer, the third layer including a metal selected from the group consisting of hafnium, tantalum, tungsten, platinum, iridium, molybdenum, or combinations thereof; and

forming perforations in the first and second layers in response to forming the third layer.

25. The method of claim 24, wherein:

the first layer is primarily located in a plane;

the at least one of the perforations includes a width, parallel to the plane, that has a first width in the first layer and a second width in the second layer;

the second width is wider than the first width.