WO2018169519A1

WO2018169519A1 - METHODS AND APPARATUS FOR COPLANAR GaN ISLANDS INCLUDING CONFINED EPITAXIAL LAYER

Info

Publication number: WO2018169519A1
Application number: PCT/US2017/022303
Authority: WO
Inventors: Sansaptak DASGUPTA; Han Wui Then; Marko Radosavljevic; Paul B. Fischer
Original assignee: Intel Corporation
Priority date: 2017-03-14
Filing date: 2017-03-14
Publication date: 2018-09-20

Abstract

Methods and apparatus are disclosed for electronic devices including islands of III-V material having differing base width dimensions, but grown by confined epitaxy on island growth areas of an integrated silicon substrate so as to have top surfaces that are substantially coplanar with one another. Transistors of differing sizes can be formed that include the islands of III-V material having differing base width dimensions. The substantially coplanar top surfaces can facilitate electrical interconnection of the transistors of differing sizes formed to include the islands of III-V material. Moreover, a silicon CMOS transistor can be formed in close proximity on the same integrated silicon substrate. The coplanar top surfaces can facilitate interconnecting the silicon CMOS transistor with at least one of the transistors of differing sizes formed to include the islands of III-V material.

Description

METHODS AND APPARATUS FOR COPLANAR GaN ISLANDS INCLUDING CONFINED EPITAXIAL LAYER

FIELD OF THE DISCLOSURE

[0001] This disclosure relates generally to electronic systems manufacturing, and in particular, to methods and apparatus for coplanar GaN islands including a confined epitaxial layer.

BACKGROUND

[0002] Modemly, integrated circuits are fabricated on dies cut from fairly large silicon wafers. Historically, wafers had been much smaller. For example, in the 1970's silicon wafers in production were only one inch in diameter. Modernly, a common silicon wafer size is 300 millimeters, or 11.8 times larger than one inch. Someday, it is expected that silicon wafer size will continue to grow to 450 millimeters, or 1.5 times larger than 300 millimeter silicon wafers.

[0003] Increasing silicon wafer size is difficult and expensive. Over the years, an enormous amount of money has been spent to re-engineer manufacturing processes to accommodate increasing size of silicon wafers. However, larger silicon wafers provide a compelling case for this investment. Larger silicon wafers provide many more chips or dies per wafer. Accordingly, cost per die can be much lower for larger silicon wafers than for smaller silicon wafers.

[0004] Although there has been a compelling need to make the necessary investment to manufacture integrated circuits on dies cut from large 300 millimeter silicon wafers, there is likewise a compelling need to continue using large 300 millimeter silicon wafers, once the investment has been made on that manufacturing capability, to provide for continuing return on that investment.

[0005] In contrast to the large silicon wafers just discussed, wafers of other semiconductor materials, such as III-V semiconductor materials, in particular, wafers of Gallium Nitride (GaN) may relatively expensive and may be commercially available only in much smaller sizes. For example, wafers of device-quality native GaN may be relatively expensive in comparison to comparable silicon wafers. Further, wafers of device-quality native GaN may be commercially available only in much smaller wafer sizes, for example 50 millimeter size GaN wafers. For various reasons, 50 millimeter size GaN wafers may not be usable in fabrication facilities constructed for large 300 millimeter silicon wafers. [0006] GaN devices can be fabricated on dies cut from relatively smaller device- quality native GaN wafers, and such GaN dies can be packaged in various ways in packages with dies cut from relatively larger silicon wafers. However, cost of such packaging can be high. While such high cost may be justifiable for small volume military or aerospace applications, such packaging may not be affordable in large volumes for ordinary consumer application. In addition to packaging costs, other costs and other considerations are also adverse in this example, at least because the GaN and silicon devices are fabricated on separate integrated substrates. Further, packaging of GaN dies side by side with silicon dies takes up more space than packaging a single die. Moreover, differing coefficients of thermal expansion for silicon dies and GaN dies can create reliability problems in packaging, especially if attempts are made to stack GaN and silicon dies in packages, so as to save space. For example, differing coefficients of thermal expansion for silicon dies and GaN dies can cause stresses that may lead to fracture and failure of bonds.

[0007] Furthermore, packaging of silicon dies together with GaN dies may not provide a pathway for co-integration of both GaN transistors and silicon CMOS circuits in extremely close proximity to each other.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIG. 1 is a three-dimensional view of an example electronic device structure a cross-sectional portion of which is depicted in FIG. 2.

[0009] FIG. 2 is a cross-sectional view of the example electronic device structure shown in FIG. 1.

[0010] FIG. 3 shows a cross-sectional view of an example confined epitaxy template along with detailed views of trenches, nucleation layers and growth areas.

[0011] FIG. 4 shows a cross-sectional view of an electronic device structure according to an example of this disclosure.

[0012] FIG. 5 is a view very similar to FIG. 4, after depositing and patterning an example sacrificial layer.

[0013] FIG. 6 is a view very similar to FIG. 5, after an example deposition layer is deposited over the example patterned sacrificial layer.

[0014] FIG. 7 is a view very similar to FIG. 6, after example apertures are formed in the example deposition layer.

[0015] FIG. 8 is a view very similar to FIG. 7, after the example patterned sacrificial layer is etched away. [0016] FIG. 9 is a view very similar to FIG. 8, after example confined epitaxy.

[0017] FIG. 10 is a view very similar to FIG. 9, after a top portion of the example deposition layer is removed to expose respective coplanar top surfaces of example islands of epitaxial III-V material.

[0018] FIG. 11 is a cross-sectional view of example islands of epitaxial III-V material after device layers are deposited to form transistors.

[0019] FIG. 12 is a cross-sectional view very similar to FIG. 11, but including a block representing addition of an example electrical interconnection layer.

[0020] FIG. 13 is a cross-sectional view very similar to FIG. 11, but including addition of a block representing an example silicon CMOS field effect transistor and addition of a block representing an example electrical interconnection layer.

[0021] FIGS. 14 and 15 are views illustrating examples of integrated silicon substrate orientation on a silicon wafer according to one example.

[0022] FIG. 16 is a cross sectional view showing differing heights of example islands grown with differing base widths but without confined epitaxy.

[0023] FIG. 17 is a cross sectional view of an example confined epitaxy template for growing of islands with differing base widths but substantially coplanar top surfaces.

[0024] FIG. 18 is a cross sectional view showing example islands grown in the confined epitaxy template of FIG. 17 in which the islands are grown to have differing base widths but substantially coplanar top surfaces.

[0025] FIGS. 19-22 are an example flowchart of an example process of this disclosure.

[0026] FIG. 23 is a block diagram of an example processing platform capable of executing the example machine-readable instructions of FIGS. 19-22.

DETAILED DESCRIPTION

[0027] Methods and apparatus are disclosed for electronic devices including islands of III-V material having differing base width dimensions, but grown by confined epitaxy on island growth areas of an integrated silicon substrate so as to have top surfaces that are substantially coplanar with one another. Transistors of differing sizes can be formed that include the islands of III-V material having differing base width dimensions. The substantially coplanar top surfaces can facilitate electrical interconnection of the transistors of differing sizes formed to include the islands of III-V material. Moreover, a silicon CMOS transistor can be formed in close proximity on the same integrated silicon substrate. The coplanar top surfaces can facilitate interconnecting the silicon CMOS transistor with at least one of the transistors of differing sizes formed to include the islands of III-V material.

[0028] Generally, the III-V material refers to a compound semiconductor material that comprises at least one of group III elements of the periodic table, e.g., aluminum ("Al"), gallium ("Ga"), indium ("In"), and at least one of group V elements of the periodic table, e.g., nitrogen ("N"), phosphorus ("P"), arsenic ("As"), antimony ("Sb"). In at least some examples, the substrate includes silicon, and the III-V layer includes GaN.

[0029] In at least some examples, methods to co-integrate GaN devices (e.g., transistors, and other GaN based devices) for power management integrated circuits

("PMIC") and RF power amplifier ("PA") applications in close proximity to silicon (Si) Complementary Metal Oxide Semiconductor ("CMOS") circuits for system on chip ("SoC") products are described. In at least some embodiments, an electronic device, e.g., a transistor, or any other electronic device comprising an epitaxially grown Ill-Nitride ("N") material is formed within small islands embedded in a Si wafer having a (111) crystallographic orientation. Forming an electronic device in the islands embedded in a Si wafer having (111) crystallographical orientation allow the co-integration of the III-V material based transistors with both low defect density and low body leakage alongside Si CMOS circuits.

[0030] In an example, to integrate GaN on Si (111) for SoC high voltage and RF devices in close proximity of CMOS transistors, variously sized GaN transistors can be grown selectively inside respective variously sized predefined trenches of the Si CMOS wafer. In some examples, predefined trenches of various sizes can be predefined silicon trenches of various sizes etched into the Si CMOS wafer. Alternatively or additionally, in some examples predefined insulator trenches of various sizes can be etched within an insulator layer of the Si CMOS wafer. In some examples having square trench openings, respective square sides of the trench openings can be within a range from about 1 micron (".mu.m") to about 100 .mu.m. Further, various example combinations of insulator trenches and silicon trenches may be employed. For example, insulator trenches of various sizes having square top openings with respective square sides within a range from about 1 micron to about 100 microns can be disposed within a larger silicon trench.

[0031] For example, FIG. 1 is a three-dimensional view 100 of an electronic device structure a cross-sectional portion of which is depicted in FIG. 2. FIG. 2 is a cross-sectional view 200 of the electronic device structure shown in FIG. 1. The example of FIGS. 1 and 2 shows the substrate 111 of the silicon CMOS wafer, and the insulator layer 122 disposed on the substrate 111 of the silicon CMOS wafer. Insulator trenches 124a, 124b, 124c of various sizes having square top openings with respective square sides within a range from about 1 micron to about 100 microns are shown in examples in FIGS. 1 and 2. As shown in examples in FIGS. 1 and 2, top openings or windows of the insulator trenches 124a, 124b, 124c in the insulator layer 122 can be square shaped. For example: a first insulator trench 124a can have a square shaped top opening having square sides of equal width WTa and length LTa of about a micron; a second insulator trench 124b can have a square shaped top opening having square sides of equal width WTb and length LTb of about fifty microns; and a third insulator trench 124c can have a square shaped top opening having square sides of equal width WTc and length LTc of about one hundred microns. Although square shaped trench top openings are shown in examples FIGS. 1 and 2, in various examples trenches of various sizes can have top openings with a square shape, a rectangular shape, or a polygon shape. As another example, an insulator trench can have a rectangular shape top opening of one-hundred by three-hundred microns. Further, although FIGS. 1 and 2 do not explicitly show the insulator trenches of various sizes disposed within a larger silicon trench, as will be discussed in greater detail subsequently herein, FIG. 13 explicitly shows insulator trenches of various sizes disposed within a larger silicon trench.

[0032] Variously sized, but yet coplanar, GaN islands 126a, 126b, 126c for variously sized GaN transistors can be grown selectively inside respective variously sized predefined trenches 124a, 124b, 124c of the Si CMOS wafer, as shown in the example of FIGS. 1 and 2. To facilitate growth of the GaN islands 126a, 126b, 126c, nucleation layers 228a, 228b, 228c (e.g., aluminum nitride or A1N nucleation layers) can be disposed on island growth areas 230a, 230b, 230c of the substrate 111. In the example of FIG. 2, nucleation layers 228a, 228b, 228c are depicted using thickened black lines. In the example of FIG. 2, first island growth area 230a is disposed within first trench 124a on the substrate 111. Second island growth area 230b is disposed within second trench 124b on substrate 111. Third island growth area 230c is disposed within third trench 124c on the substrate 111. Respective first and second and third nucleation layers 228a, 228b, 228c, are disposed on the first and second and third island growth areas 230a, 230b, 230c. In the example of FIGS. 1 and 2, growth areas 230a, 230b, 230c have respective example square shapes. However, other shapes may be employed such as square shapes, rectangular shapes or polygon shapes. More generally, a member of the first and second and third island growth areas 230a, 230b, 230c, can have a square shape, rectangular shape, or a polygon shape.

[0033] First and second and third islands 126a, 126b, 126c, of III-V material have respective bottom surfaces disposed on respective ones of the first and second and third nucleation layers 228a, 228b, 228c. The first and second and third islands 126a, 126b, 126c, of III -V material include a III-V binary, ternary or quaternary semiconductor and the island growth areas 230a, 230b, 230c, include silicon.

[0034] The first and second and third islands 126a, 126b, 126c, of III-V material shown in the example of FIGS. 1 and 2 can include an epitaxial layer of III-V material. In particular, GaN islands 126a, 126b, 126c for variously sized GaN transistors can be grown selectively inside respective variously sized predefined trenches of the Si CMOS wafer using confined epitaxy. Accordingly, the first, second and third islands 126a, 126b, 126c, of III-V material include a confined epitaxial layer of III-V material. Moreover, since GaN islands 126a, 126b, 126c for variously sized GaN transistors can be grown in selective areas inside respective variously sized predefined trenches of the Si CMOS wafer, the first, second and third islands 126a, 126b, 126c, of III-V material layer can include Selective Area Growth (SAG) islands of III-V material.

[0035] Further, as shown in the example of FIG. 2, the first and second and third islands 126a, 126b, 126c, of III-V material have top surfaces 236a, 236b, 236c. The top surfaces 236a, 236b, 236c of the first and second and third islands 126a, 126b, 126c, of III-V material are substantially coplanar with one another. However, the first and second and third islands 126a, 126b, 126c, of III-V material have respective corresponding bottom width dimensions WGa, WGb, WGc, that are substantially different from one another. Similarly, the first and second and third trenches 124a, 124b, 124c, have respective corresponding bottom width dimensions WTa, WTb, WTc, that are substantially different from one another.

[0036] Further, as shown in the example of FIG. 2, the first and second and third islands 126a, 126b, 126c, of III-V material can have substantially equal layer thickness TG. Since the top surfaces 236a, 236b, 236c of the first and second and third islands 126a, 126b, 126c, of III-V material are substantially coplanar with one another, and since the layer thickness TG is substantially equal for the first and second and third islands 126a, 126b, 126c, of III-V material, the respective bottom surfaces of the first and second and third islands 126a, 126b, 126c, of III-V material are likewise substantially coplanar with one another.

[0037] The first and second and third islands 126a, 126b, 126c, of III-V material, for example GaN, can have a wurtzite crystal structure having a c-axis orientation or a {0001} crystal orientation. To facilitate the foregoing, the nucleation layers 228a, 228b, 228c can include, for example, aluminum nitride, A1N, likewise having a wurtzite crystal structure having a c-axis orientation or a {0001} crystal orientation. The layer thickness TG of the first and second and third islands 126a, 126b, 126c, of III-V material shown in the example of FIG. 2 is aligned along a {0001} crystal orientation (e.g., c-axis crystal orientation) of the III- V material. More generally, a thickness dimension TG of a member of the first and second and third islands 126a, 126b, 126c, of III-V material is aligned along a {0001} crystal orientation (e.g., c-axis orientation) of the III-V material.

[0038] The first and second and third island growth areas 230a, 230b, 230c have respective corresponding width dimensions WAa, WAb, WAc. The respective corresponding width dimensions of the first and second island growth areas WAa, WAb, WAc, are substantially different from one another, as shown for example in FIG. 2. Similarly, the respective nucleation layers 228a, 228b, 228c, on the first and second and third island growth areas 230a, 230b, 230c have respective corresponding width dimensions WNa,WNb,WNc. The respective corresponding width dimensions WNa, WNb, WNc, of the respective nucleation layers 228a, 228b, 228c, on the first and second and third island growth areas 230a, 230b, 230c, are substantially different from one another.

[0039] As shown in the example of FIG. 2, the first and second and third trenches 124a, 124b, 124c can include respective first and second and third bottom insulator layer features 138a, 138b, 138c filling respective peripheral spaces around the first and second and third island growth areas 230a, 230b, 230c. As shown in the example of FIG. 2, the first and second and third islands 126a, 126b, 126c, of III-V material can extend laterally over the respective first and second and third bottom insulator layer features 138a, 138b, 138c. The first and second and third features 138a, 138b, 138c of the bottom insulator layer can include silicon dioxide. In the example of FIG. 2, the laterally extended first and second and third islands 126a, 126b, 126c, of III-V material are formed in direct contact with the respective first and second and third bottom insulator layer features 138a, 138b, 138c.

[0040] The first and second and third islands 126a, 126b, 126c, of III-V material can include respective device layers (e.g., device layers of GaN transistors) on the first and second and third islands 126a, 126b, 126c, of III-V material. Although FIGS. 1 and 2 do not explicitly show the device layers of GaN transistors of the first and second and third islands 126a, 126b, 126c, as will be discussed in greater detail subsequently herein, FIG. 11 explicitly shows device layers of GaN transistors of differing sizes, including GaN islands of differing sizes, grown in predefined trenches of differing sizes. Referring now to the example of FIGS. 1 and 2, respective first and second and third transistors of differing sizes can be grown selectively inside respective variously sized predefined trenches 124a, 124b, 124c. For example, the first transistor can include the first island 126a of III-V material. The second transistor can include the second island 126b of III-V material. The third transistor can include the third island 126c of III-V material.

[0041] Since first and second and third islands 126a, 126b, 126c, of III-V material are variously sized, but yet coplanar as shown in the example of FIGS. 1 and 2, the first and second and third transistors can likewise have respective sizes that are substantially different from one another, but yet top surfaces of the first and second and third transistors are coplanar to facilitate interconnection. Since the first and second and third islands 126a, 126b, 126c, of III-V material have respective corresponding bottom width dimensions WGa, WGb, WGc, that are substantially different from one another, as shown for example in FIG. 2, the first and second and third transistors including the islands likewise have respective corresponding transistor bottom width dimensions that are substantially different from one another.

[0042] FIG. 3 shows a cross-sectional view of a confined epitaxy template 322 having first, second and third lumens 326a, 326b, 326c, along with detailed views of first and second trenches 124a, 124b, first and second nucleation layers 228a, 228b, and first and second growth areas 230a, 230b. In the example of FIG. 3, nucleation layers 228a, 228b are depicted in detailed view using stippling. As shown in detailed view in the example of FIG. 3, first and second trenches 124a, 124b have substantially different respective base widths WTa, WTb. As shown in detailed view in the example of FIG. 3, first and second nucleation layers 228a, 228b, have substantially different respective nucleation layer widths WNa, WNb, As shown in detailed view in the example of FIG. 3, first and second first and second growth areas 230a, 230b have substantially different respective growth area widths WAa, WAb, Despite having substantially different base widths, GaN islands for variously sized GaN transistors can be selectively grown inside trenches to have coplanar top surfaces, by confined epitaxy using the confined epitaxy template 322, shown in the example of FIG. 3.

[0043] FIG. 4 shows a cross-sectional view of an electronic device structure according to an example of this disclosure. First and second and third bottom insulator layer features 138a, 138b, 138c as well as first and second and third respective matching companion bottom insulator layer features 138aa, 138bb, 138cc can be formed on substrate 111 by patterning a first bottom insulator layer, for example to facilitate shallow trench isolation (STI). The first and second bottom insulator layer features 138a, 138b, can have respective width dimensions of, for example, 2 microns or for example within a range of about 500 nanometers to 2 microns. The bottom insulator layer can be masked and patterned using of techniques known to one of ordinary skill in the art of electronic device manufacturing. Initially, prior to any patteming, a bottom insulator layer can be deposited on the substrate. The bottom insulator layer can be any material suitable to insulate adjacent devices and prevent leakage. For example, the electrically bottom insulator layer can be an oxide layer, e.g., silicon dioxide, or any other electrical insulator layer determined by an electronic device design. For example, the bottom insulator layer can include an interlay er dielectric (ILD), e.g., silicon dioxide. In other examples, the bottom insulator layer can include polyimide, epoxy, photodefinable materials, such as benzocyclobutene (BCB), and WPR-series materials, or spin-on-glass. For example, bottom insulator layer can include a low permittivity (low-k) ILD layer. Typically, low-k is referred to the dielectrics having dielectric constant (permittivity k) lower than the permittivity of silicon dioxide. For example, as already mentioned the bottom insulator layer can facilitate shallow trench isolation (STI) layer to provide field isolation regions that isolate one island from other islands on substrate 111. For example, the thickness of the layer can in an approximate range of 20 nanometers ("nm") to 350 nanometers. The bottom insulator layer can be blanket deposited using any of techniques known to one of ordinary skill in the art of electronic device manufacturing, such as but not limited to a chemical vapor deposition (CVD), and a physical vapor deposition (PVD).

[0044] The bottom width dimension of the first island of epitaxial material can be determined by selecting the first bottom width WTa of the first trench 230a, shown in the example of FIG. 2. Similarly, the bottom width dimension of the second island of epitaxial material can be determined by selecting the second bottom width WTb of the second trench 230b, shown in the example of FIG. 4. Similarly, the bottom width dimension of the third island of epitaxial material can be determined by selecting the third bottom width WTc of the third trench 230c, shown in the example of FIG. 4. The first and second and third bottom width dimensions WTa, WTb, WTc are substantially different from one another as shown in the example of FIG. 4. The bottom insulator layer is patterned, for example by masking and etching, to form the first trench 230a having the first selected bottom width dimension WTA, and to form the second trench 230b having the second selected bottom width dimension WTb, and to form the third trench 230c having the third selected bottom width dimension WTc, in a patterned bottom insulator layer.

[0045] FIG. 5 is a view very similar to FIG. 4, after depositing and patterning a sacrificial layer. The sacrificial layer can include silicon nitride and can be deposited, for example using chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD). The silicon nitride of the sacrificial layer can be masked and patterned using techniques known to one of ordinary skill in the art of electronic device manufacturing, such as but not limited to lithography and dry etch. A thickness of the first and second and third islands of epitaxial material can be selected and determined by selecting a

corresponding thickness TS of the sacrificial layer. The sacrificial layer can be deposited on the first and second and third trenches formed in the patterned bottom insulator layer on the substrate to have the selected thickness TS. The sacrificial layer can be patterned to form a patterned sacrificial layer 500 including a first sacrificial island 526a, a second sacrificial island 526b and third sacrificial island 526c. As shown in the example of FIG. 5, the first sacrificial island 526a can be deposited over the first feature 138a of the bottom insulator layer. Further, the first sacrificial island 526a can be deposited in direct contact with the first feature 138a of the bottom insulator layer. Similarly, the second sacrificial island 526b can be deposited over the second feature 138b of the bottom insulator layer. The second sacrificial island 526b can be deposited in direct contact with the second feature 138b of the bottom insulator layer. Similarly, the third sacrificial island 526c can be deposited over the third feature 138c of the bottom insulator layer. The third sacrificial island 526c can be deposited in direct contact with the third feature 138c of the bottom insulator layer.

[0046] FIG. 6 is a view very similar to FIG. 5, after a deposition layer 622 is deposited over the patterned sacrificial layer. The deposition layer 622 can include silicon dioxide and can be deposited to have a layer thickness CLT, for example five microns or more. Deposition layer 622 can be blanket deposited using any of techniques known to one of ordinary skill in the art of electronic device manufacturing, such as but not limited to a chemical vapor deposition (CVD), and a physical vapor deposition (PVD).

[0047] The depositing the deposition layer 622 over the patterned sacrificial layer can include sandwiching the patterned sacrificial layer between the deposition layer and the substrate 111. The depositing the deposition layer 622 over the patterned sacrificial layer can include sandwiching the patterned sacrificial layer between the deposition layer and the patterned bottom insulator layer.

[0048] FIG. 7 is a view very similar to FIG. 6, after first, second and third apertures 738a, 738b, 738c, are formed in the deposition layer 622. The first, second and third apertures 738a, 738b, 738c, can be masked and etched into the silicon dioxide of the deposition layer 622 using of techniques known to one of ordinary skill in the art of electronic device manufacturing. First and second and third aperture widths APWa, APWb, APWc and locations can be selected based on matching respective widths and matching respective vertical alignment of locations of the first and second and third features 138a, 138b, 138c of the bottom insulator layer. The first aperture 738a in the deposition layer 622 can be formed over the first sacrificial island 526a and over the first feature 138a of the bottom insulator layer. Similarly, the second aperture 738b in the deposition layer 622 can be formed over the second sacrificial island 526b and over the second feature 138b of the bottom insulator layer. Similarly, the third aperture 738c in the deposition layer 622 can be formed over the third sacrificial island 526c and over the third feature 138c of the bottom insulator layer. Further, the foregoing can advantageously facilitate mask reuse between the masking and patterning of features of the bottom insulator layer and the masking and patterning of the apertures.

[0049] FIG. 8 is a view very similar to FIG. 7, after the patterned sacrificial layer is etched away to form first, second and third lumens 826a, 826b, 826c for confined epitaxy. For example silicon nitride of the patterned sacrificial layer can be etched away using hot phosphoric acid (H3P04), which advantageously does not affect the silicon dioxide of the deposition layer 622 that provides the template the confined epitaxy.

[0050] The example FIG. 8 is also very similar to FIG. 3. In the example of FIG. 8, nucleation layers 228a, 228b, 228c (e.g., Aluminum Nitride or A1N) are depicted using thickened black lines. As shown in the example of FIG. 8, the nucleation layers can be deposited through the first, second and third apertures in the deposition layer onto the respective island growth areas of the substrate 111. For example, the nucleation layers 228a, 228b, 228c can be deposited using one of epitaxial techniques, e.g., chemical vapor deposition ("CVD"), metalorganic chemical vapor deposition ("MOCVD"), atomic layer deposition ("ALD"), molecular beam epitaxy ("MBE"), or other epitaxial growth technique known to one of ordinary skill in the art of electronic device manufacturing.

[0051] The first, second and third nucleation layer widths WNa, WNb, WNc, shown in the example of FIG. 8 are all substantially different from one another. Similarly, first, second and third growth area widths WAa, WAb, WAc, are all substantially different from one another. As shown in the example of FIG. 8, first, second and third lumens 826a, 826b, 826c have matching respective height dimensions HLa, HLb, HLc, which are substantially equal. As shown in the example of FIG. 8, first, second and third lumens 826a, 826b, 826c have respective first, second and third bottom width dimensions WLa, WLb, WLc, that are substantially different than one another (e.g., WLa is substantially greater than WLb, e.g., WLb is substantially greater than WLc.) As shown in the example of FIG. 8, the first, second and third lumen bottom width dimensions WLa, WLb, WLc, can be respectively coextensive with the first, second and third trench bottom widths WTa, WTb, WTc, discussed previously herein, and shown again in FIG. 8.

[0052] Further as shown in FIG. 8, first and second and third aperture widths APWa, APWb, APWc (e.g. example aperture widths of 2 microns or within a range of about 500 nanometers to about 5 microns) and locations can be selected based on matching respective widths STIa, STIb, STIc (e.g. example matching aperture widths of 2 microns or within a range of about 500 nanometers to about 5 microns) and matching respective vertical alignment of locations of the first and second and third features 138a, 138b, 138c of the bottom insulator layer. The first aperture 738a can be formed over the first feature 138a of the bottom insulator layer and can be aligned with the first feature 138a of the bottom insulator layer. Similarly, the second aperture 738b in the deposition layer 622 can be formed over the second feature 138b of the bottom insulator layer and can be aligned with the second feature 138b of the bottom insulator layer. Similarly, the third aperture 738c in the deposition layer 622 can be formed over the third feature 138c of the bottom insulator layer and can be aligned with the third feature 138c of the bottom insulator layer. Further, the foregoing can advantageously facilitate mask reuse between the masking and patterning of features of the bottom insulator layer and the masking and patterning of the apertures.

[0053] FIG. 9 is a view very similar to FIG. 8, after confined epitaxy. Variously sized, but yet coplanar, first, second and third GaN islands 126a, 126b, 126c for variously sized GaN transistors can be grown selectively, by confined epitaxy through respective first, second and third apertures 728a, 728b, 728c, inside respective variously sized predefined insulator trenches 124a, 124b, 124c of the Si CMOS wafer, as shown in the example of FIG. 9. To facilitate growth of the first, second and third GaN islands 126a, 126b, 126c, respective first, second and third nucleation layers 228a, 228b, 228c are disposed on island growth areas of the substrate 111. In the example of FIG. 9, nucleation layers 228a, 228b, 228c are depicted using thickened black lines. The first, second and third GaN islands 126a, 126b, 126c can be grown, for example, using Metal Organic Chemical Vapor Deposition

("MOCVD") or Hydride Vapor Phase Epitaxial ("HVPE"). First and second and third islands 126a, 126b, 126c, of III-V material have respective bottom surfaces disposed on respective ones of the first and second and third nucleation layers 228a, 228b, 228c. As mentioned previously, the first and second and third islands 126a, 126b, 126c, of III-V material include a III-V binary, ternary or quaternary semiconductor and the island growth areas of the substrate 111 include silicon. The first and second and third islands 126a, 126b, 126c, of III-V material shown in the example of FIG. 9 can include an epitaxial layer of III-V material. In particular, GaN islands 126a, 126b, 126c for variously sized GaN transistors can be grown selectively inside respective variously sized predefined insulator trenches of the Si CMOS wafer using confined epitaxy. Accordingly, the first, second and third islands 126a, 126b, 126c, of III-V material include a confined epitaxial layer of III -V material. Moreover, since GaN islands 126a, 126b, 126c for variously sized GaN transistors can be grown in selective areas inside respective variously sized predefined insulator trenches of the Si CMOS wafer, the first, second and third islandsl26a, 126b, 126c, of III-V material layer can include Selective Area Growth (SAG) islands of III-V material.

[0054] Further, because top growth of the first and second and third islands 126a, 126b, 126c, of III-V material is limited under the confined epitaxy template 622, as shown in the example of FIG. 9, top surfaces of the first and second and third islands 126a, 126b, 126c, of III-V material are substantially coplanar with one another. However, the first and second and third islands 126a, 126b, 126c, of III-V material have respective corresponding bottom width dimensions WGa, WGb, WGc, that are substantially different from one another (e.g., WGa is substantially greater than WGb, e.g., WGb is substantially greater than WGc.) Similarly, the first and second and third trenches 124a, 124b, 124c, have respective corresponding bottom width dimensions WTa, WTb, WTc, that are substantially different from one another (e.g., WTa is substantially greater than WTb, e.g., WTb is substantially greater than WTc.) Similarly, respective widths of the first and second and third nucleation layers WNa, WNb, Wnc are substantially different from one another (e.g., WNa is substantially greater than WNb, e.g., WNb is substantial greater than WNc.) Similarly, respective widths of the first and second and third growth areas WAa, WAb, WAc are substantially different from one another (e.g., WAa is substantially greater than WAb, e.g., WAb is substantially greater than WAc.) For example, bottom width of the first GaN island WGa, bottom width of the first trench WTa, width of the first nucleation layer WNa and width of the first growth area WAa can be coextensive with one another and can be about 100 microns or more. For example, bottom width of the second GaN island WGb, bottom width of the second trench WTb, width of the second nucleation layer WNb and width of the second growth area WAb can about 10 microns or more. For example, bottom width of the third GaN island WGc, bottom width of the third trench WTc, width of the third nucleation layer WNc and width of the third growth area WAc can be about 1 micron or more. For example, 100 microns is substantially different than 10 microns, e.g., 100 microns is substantially greater than 10 microns. Moreover, since 50% of the smaller 10 microns is only 5 microns, and since the difference between the larger 100 microns and the smaller 10 microns is an increase of 90 microns, therefore the difference between 100 microns and 10 microns is more than 50% of the 10 microns, e.g., different by more than 50%. Furthermore, since the difference is an increase of 90 microns, and since 50% of the smaller 10 microns is only 5 microns, the 100 microns is greater than 10 microns by an increase of more than 50% of the 10 microns, e.g., an increase of fifty percent or more.

[0055] Further, as shown in the example of FIG. 9, the first and second and third islands 126a, 126b, 126c, of III-V material have respective matching and substantially equal layer thickness TGa, TGb, TGc (e.g. thickness can be within a range of 1 to 5 microns). Since the top surfaces 236a, 236b, 236c of the first and second and third islands 126a, 126b, 126c, of III-V material are substantially coplanar with one another, and since the layer thickness TGa, TGb, TGc, is substantially equal for the first and second and third islands 126a, 126b, 126c, of III-V material, the respective bottom surfaces of the first and second and third islands 126a, 126b, 126c, of III-V material are likewise substantially coplanar with one another.

[0056] The first and second and third islands 126a, 126b, 126c, of III-V material, for example GaN, shown in the example of FIG. 9 can have the wurtzite crystal structure having a c-axis orientation or a {0001} crystal orientation. To facilitate the foregoing, the nucleation layers 228a, 228b, 228c can include, for example, aluminum nitride, AIN, likewise having the wurtzite crystal structure having a c-axis orientation or a {0001} crystal orientation. The respective layer thickness TGa, TGb, TGc of the first and second and third islands 126a, 126b, 126c, of III-V material shown in the example of FIG. 9 is aligned along a {0001} crystal orientation (e.g., c-axis crystal orientation) of the III-V material. More generally, a thickness dimension of a member of the first and second and third islands 126a, 126b, 126c, of III-V material shown in the example of FIG. 9 is aligned along a {0001} crystal orientation (e.g., c-axis orientation) of the III-V material.

[0057] The first and second and third island growth areas have respective

corresponding width dimensions WAa, WAb, WAc. The respective corresponding width dimensions of the first and second island growth areas WAa, WAb, WAc, are substantially different from one another, as shown for example in FIG. 9. Similarly, the respective nucleation layers 228a, 228b, 228c, on the first and second and third island growth areas 230a, 230b, 230c have respective corresponding width dimensions WNa,WNb,WNc. The respective corresponding width dimensions WNa, WNb, WNc, of the respective nucleation layers 228a, 228b, 228c, on the first and second and third island growth areas 230a, 230b, 230c, are substantially different from one another. [0058] As shown in the example of FIG. 2, the first and second and third trenches 124a, 124b, 124c can include respective first and second and third bottom insulator layer features 138a, 138b, 138c filling respective peripheral spaces around the first and second and third island growth areas 230a, 230b, 230c. As shown in the example of FIG. 2, the first and second and third islands 126a, 126b, 126c, of III-V material can extend laterally over the respective first and second and third bottom insulator layer features 138a, 138b, 138c. The first and second and third features 138a, 138b, 138c of the bottom insulator layer can include silicon dioxide. In the example of FIG. 9, the laterally extended first and second and third islands 126a, 126b, 126c, of III-V material are formed in direct contact with the respective first and second and third bottom insulator layer features 138a, 138b, 138c.

[0059] FIG. 10 is a view very similar to FIG. 9, after a top portion of the deposition layer is removed, for example by polishing, to expose respective coplanar top surfaces 136a, 136b, 136c, of first, second, and third islands 126a, 126b, 126c, of epitaxial III-V material on the Si CMOS substrate 111. The example of FIG. 10 is very similar to the example of FIG. 2, already discussed in detail previously herein.

[0060] FIG. 11 is a cross-sectional view of islands of epitaxial III-V material after device layers are deposited to form first and second transistors 1126a, 1126b. In the example shown in FIG. 11, respective device layers 1118a, 1118b are deposited on respective device layers 1117a, 1117b on respective III-V material layers 1116a, 1116b. In the example shown in FIG. 11, device layers 1117a, 1117b are deposited to enhance mobility of respective two- dimensional electron gas ("2DEG") portions 1120a 1120b of the respective III-V material layers 1116a, 1116b. In the example shown in FIG. 11, respective device layers 1117a, 1117b are A1N layers. In the example shown in FIG. 11, the thicknesses of the device layers 1117a, 1117b are from about 1 nm to about 3 nm. In the example shown in FIG. 11, respective device layers 1118a, 1118b include III-V material, e.g., AlGaN, AlInN, A1N, any other III-V material, or any combination thereof. In the example shown in FIG. 11, respective device layers 1118a, 1118b are Al.sub.xGa.sub.N layers, where x is from about 15% to about 40%. In the example shown in FIG. I r respective device layers 1118a, 1118b are Al.sub.xln. sub.1- xN layers, where x is greater than about 85%. In the example shown in FIG. 11, respective device layers 1118a, 1118b are an A1N layer. The thickness of the foregoing various respective device layers are determined by device design. In the example shown in FIG. 11, the thickness of the foregoing various respective device layers is from about 2 nm to about 40 nm. In the example shown in FIG. 11, respective device layers 1118a, 1118b and 1117a, 1117b are deposited using one of epitaxial growth techniques, e.g., chemical vapor deposition ("CVD"), metal organic chemical vapor deposition ("MOCVD"), atomic layer deposition ("ALD"), MBE, or other epitaxial growth technique known to one of ordinary skill in the art of electronic device manufacturing. Contacts can be formed over respective portions of respective device layers 1118a, 1118b over respective portions of respective III-V material layers 1116a, 1116b to first and second III-V material based devices according to the example shown in FIG. 11. The III-V material based devices can be, for example, high voltage transistors (e.g., GaN transistors), RF -power amplifiers, power management integrated circuits, or other III-V material based electronic devices. As shown in the example of FIG. I r respective device contacts 1121a, 1121b, 1131a, 1131b, 1141a, 1141b are formed on respective portions of the respective device layer portions of the respective III-V material layers 1116a, 1116b. In the example shown in FIG. 11, respective device contacts 1121a, 1121b are respective gate electrodes over respective gate dielectrics 1151a, 1152b on respective device layers 1118a, 1118b over the respective portions 1813a, 1813b of respective III-V material layers 1116a, 1116b. Respective contacts 1141a, 1141b are respective source contacts on respective source regions 1161a, 116b, and respective contacts 1131a, 1113b are respective drain contacts on respective drain regions 1171a, 1171b of respective device layers 1118a, 1118b over respective portions of respective III-V material layers 118a, 1118b. The respective contacts 1121a, 1121b, 1131a, 1131b, 1121a, 1121b, respective gate dielectrics 151a, 151b, respective drain and source regions 1161a, 1161b, 1171a, 1171b can be formed on the III-V material device layer using techniques known to one of ordinary skill the art of electronic device manufacturing.

[0061] As shown in the example of FIG. 11, the first and second transistors 1126a, 1126b can have respective sizes that are substantially different from one another (e.g. sizes are different by fifty percent or more), but yet respective top surfaces of the first and second transistors 1126a, 1126b are coplanar to facilitate interconnection. Since the first and second islands 126a, 126b, of III-V material have respective corresponding bottom width dimensions WGa, WGb that are substantially different from one another (e.g. different by fifty percent or more), as shown for example in FIG. 11, the first and second transistors 1126a, 1126b including the islands 126a, 126b likewise have respective corresponding transistor bottom width dimensions WXa, WXb that are substantially different from one another (e.g. different by fifty percent or more). As shown in the example of FIG. 11, width WGa of the first island 126a of III-V material can be coextensive with width WXa of the first transistor 1126a, and width WGb of the second island 126b of III-V material can be coextensive with width WXb of the second transistor 1126b. Moreover, with the first transistor 1126a being substantial larger than the second transistor 1126b (e.g. larger by fifty percent or more), as shown in the example of FIG. 11, other transistor dimensions affecting transistor performance such as transistor channel length and/or transistor channel width of first transistor 1126a can be substantial larger than corresponding transistor channel length and/or transistor channel width of second transistor 1126b (e.g. larger by fifty percent or more). More broadly, channel width of the first transistor 1126a can be substantially different than channel width of the second transistor 1126b (e.g. different by fifty percent or more). Similarly, channel length of the first transistor 1126a and be substantially different than channel length of the second transistor 1126b (e.g. different by fifty percent or more).

[0062] FIG. 12 is a cross-sectional view very similar to FIG. 11, but including a block 1200 representing addition of an electrical interconnection layer. The electrical

interconnection layer 1200 can be formed using techniques known to one of ordinary skill. The electrical interconnection layer 1200 can electrically interconnect the first transistor 1126a and the second transistor 1126b. As shown in the example of FIG. 12, the first transistor 1126a and the second transistor 1126b are differently sized III-V transistors (e.g., differently sized GaN transistors) of respective differently sized islands of III-V material (e.g., differently sized GaN islands) disposed on the same Si CMOS substrate 111. The substantially coplanar top surfaces of the first transistor 1126a and the second transistor 1126b (and the corresponding substantially coplanar top surfaces for islands of III-V material) can facilitate the electrical interconnection of the first transistor 1126a and the second transistor 1126b using electrical interconnection layer 1200.

[0063] FIG. 13 is a cross-sectional view very similar to FIG. 11, but including addition of a block representing a silicon CMOS field effect transistor 1302 and addition of a block representing an electrical interconnection layer 1300. The electrical interconnection layer 1300 and the silicon CMOS field effect transistor 1302 can be formed using techniques known to one of ordinary skill. The example of FIG. 13 shows insulator trenches of various sizes disposed within a larger silicon trench etched into Si CMOS substrate 111. The larger silicon trench can have been previously patterned and etched into the Si CMOS substrate 111 using one or more etching techniques known to one of ordinary skill in the art of electronic device manufacturing. For example, an etching solution (e.g., tetramethylammonium hydroxide ("TMAH"), potassium hydroxide ("KOH"), ammonium hydroxide ("NH40H")) can be used to etch the Si CMOS substrate. For example, a dry etch using gases SF6, XeF2, BC13, C12, or any combination thereof is used to etch the Si CMOS substrate. As shown in the example of FIG. 13, the silicon CMOS field effect transistor 1302 can be arranged on the Si CMOS substrate 111 outside of the larger silicon trench in Si CMOS substrate 111, and can be arranged adjacent to an extremity of the larger silicon trench in Si CMOS substrate 111.

[0064] The electrical interconnection layer 1300 can electrically interconnect the silicon CMOS transistor 1302 with at least one of the first transistor 1126a and the second transistor 1126b. A top surface of the silicon CMOS transistor 1302 and top surfaces of the first transistor 1126a and the second transistor 1126b are substantially coplanar with one another to facilitate interconnecting the silicon CMOS transistor 1302 with at least one of the first transistor 1126a and the second transistor 1126b.

[0065] Further, the electrical interconnection layer 1300 can electrically interconnect the first transistor 1126a and the second transistor 1126b. As shown in the example of FIG. 13, the first transistor 1126a and the second transistor 1126b are differently sized III-V transistors (e.g., coplanar but differently sized GaN transistors) of respective differently sized islands of III-V material (e.g., coplanar but differently sized GaN islands) disposed on the same Si CMOS substrate 111 with silicon CMOS transistor 1302. The substantially coplanar top surfaces of the first transistor 1126a and the second transistor 1126b (and the

corresponding substantially coplanar top surfaces for islands of III-V material) can facilitate the electrical interconnection of the first transistor 1126a and the second transistor 1126b using electrical interconnection layer 1300.

[0066] The example of FIG. 13 shows thickness TG of the coplanar but differently sized III-V islands of the first transistor 1126a and the second transistor 1126b (e.g. coplanar but differently sized III-V transistors 1126a, 1126b or coplanar but differently sized GaN transistors 1126a, 1126b). The thickness TG of the coplanar but differently sized III-V islands of the first transistor 1126a and the second transistor 1126b (e.g. coplanar but differently sized III-V transistors 1126a, 1126b or coplanar but differently sized GaN transistors 1126a, 1126b) is larger (e.g. much larger or ten times larger) than parallel thickness TS of the silicon CMOS transistor 1302. For example, a few micron thickness TG of the coplanar but differently sized III-V islands of the first transistor 1126a and the second transistor 1126b) is larger (e.g. much larger or ten times larger) than twenty to thirty nanometer parallel thickness TS of the silicon CMOS transistor 1302. This much larger thickness of the coplanar but differently sized III-V islands of the first transistor 1126a and the second transistor 1126b) can be accommodated by the larger silicon trench, which can be etched into Si CMOS substrate 111 to facilitate the top surface of the silicon CMOS transistor 1302 and top surfaces of the first transistor 1126a and the second transistor 1126b being substantially coplanar with one another.

[0067] Moreover, the silicon CMOS transistor 1302 can be formed in close proximity to at least one of the transistors (e.g., close proximity distance DTT of a few microns between silicon CMOS transistor 1302 and transistor 1126b) and can be on the same integrated silicon substrate 111. The coplanar top surfaces can facilitate interconnecting the silicon CMOS transistor with at least one of the transistors of differing sizes formed to include the islands of III-V material. This can facilitate co-integration of GaN devices (e.g., transistor 1126b or other GaN based devices) for power management integrated circuits ("PMIC") and RF power amplifier ("PA") applications in close proximity to silicon (Si) Complementary Metal Oxide Semiconductor ("CMOS") circuits (e.g., silicon CMOS transistor 1302) for system on chip ("SoC") products.

[0068] FIGS. 14 and 15 are views illustrating examples of integrated silicon substrate orientation on a silicon (111) wafer 111 according to one example. As shown in FIGS. 14 and 15, there are different crystallographical directions on Si (111) wafer 111, such as directions 1401, 1402, and 1403. In an embodiment, direction 1401 is aligned along <l l-2> crystallographical direction. In an embodiment, direction 1402 is aligned along <1-10> crystallographical direction. In an embodiment, direction 1402 is aligned along <001> crystallographical direction.

[0069] FIG. 16 is a cross sectional view showing differing heights of islands 1626a, 1626b grown with respective differing base widths 16WGa, 16WGb on respective differing width growth areas 16WAa, 16WAb on substrate 1611, but without confined epitaxy. For example, without confined epitaxy, the larger width growth area (e.g., 16WAa) can result in a relatively thinner GaN film (e.g., thinner island 1626a) while the narrower width area (e.g., 16WAb) can result in a relatively thicker GaN films (e.g., thicker island 1626b). In the example shown in FIG. 16, without confined epitaxy, respective top surfaces of relatively thinner GaN island 1626a and relatively thicker GaN island 1626b are not coplanar, while relatively thinner GaN island 1626a and relatively thicker GaN island 1626b have differing respective base widths 16WGa, 16WGb. The foregoing can be explained by there being more "volume" to fill up adjacent to the larger width growth area (e.g., 16WAa), while there being less "volume" to fill up adjacent to the narrower width growth area (e.g., 16WAb). Thus, for the same growth time, the narrower width growth area (e.g., 16WAb) has a faster growth rate, and the larger width growth area (e.g., 16WAa) has a slower growth rate, given the fill factor or the pattern density around the larger width growth area (e.g., 16WAa) and the narrower width area (e.g., 16WAb) being uniform.

[0070] For the sake of contrast to FIG. 16, the example of FIG. 17 shows a cross sectional view of substrate 111a and a confined epitaxy template 322a for growing of islands with differing base widths but substantially coplanar top surfaces. FIG. 17 is similar to FIG. 3 already discussed in greater detail previously herein.

[0071] FIG. 18 is a cross sectional view showing islands 1726a, 1726b, 1726c grown on substrate 11 la in the confined epitaxy template 322a of FIG. 17 in which the islands 1726a, 1726b, 1726c are grown to have differing base widths but substantially coplanar top surfaces. FIG. 18 is similar to FIG. 9 already discussed in greater detail previously herein.

[0072] While example manners of implementing the example electronic device structure shown in three-dimensional view 100 in FIG land shown in cross-sectional view 200 in FIG 2 are illustrated in FIGS. 1-13, one or more of the elements, processes and/or devices illustrated in FIGS. 1-13 may be combined, divided, re-arranged, omitted, eliminated and/or implemented in any other way. For example, the example electronic device structure shown in three-dimensional view 100 in FIG 1 and shown in cross-sectional view 200 in FIG 2, example substrate 111, example insulator layer 122, example insulator trenches 124a, 124b, 124c, example GaN islands 126a, 126b, 126c and their example respective top surfaces 136a, 136b, 136c, example bottom insulator layer features 138a, 138aa, 138b, 138bb, 138c, 138cc example nucleation layers 228a, 228b, 228c, example island growth areas 230a, 230b, 230c, example lumens 326a, 326b, 326c, example sacrificial islands 526a, 526b, 526c, example deposition layer 622, example apertures 728a, 728b, 728c, example first and second GaN transistors 1126a, 1126b, example device layers 1118a, 1118b deposited on example respective device layers 1117a, 1117b on example respective III-V material layers 1116a, 1116b, example respective two-dimensional electron gas ("2DEG") portions 1120a 1120b of the example respective III-V material layers 1116a, 1116b, example respective device contacts 1121a, 1121b, 1131a, 1131b, 1141a, 1141b, example respective gate dielectrics 1151a, 1152b, example respective source contacts 1141a, 1141b, example respective source regions 1161a, 116b, example respective drain contacts 1131a, 1113b, example respective drain regions 1171a, 1171b, example electrical interconnection layer 1200, and example silicon CMOS field effect transistor 1302 may be combined, divided, re-arranged, omitted, eliminated and/or implemented in any other way.

[0073] Further the example electronic device structure shown in three-dimensional view 100 in FIG land shown in cross-sectional view 200 in FIG 2, example substrate 111, example insulator layer 122, example insulator trenches 124a, 124b, 124c, example GaN islands 126a, 126b, 126c and their example respective top surfaces 136a, 136b, 136c, example bottom insulator layer features 138a, 138aa, 138b, 138bb, 138c, 138cc example nucleation layers 228a, 228b, 228c, example island growth areas 230a, 230b, 230c, example lumens 326a, 326b, 326c, example sacrificial islands 526a, 526b, 526c, example deposition layer 622, example apertures 728a, 728b, 728c, example first and second GaN transistors 1126a, 1126b, example device layers 1118a, 1118b deposited on example respective device layers 1117a, 1117b on example respective III-V material layers 1116a, 1116b, example respective two-dimensional electron gas ("2DEG") portions 1120a 1120b of the example respective III-V material layers 1116a, 1116b, example respective device contacts 1121a, 1121b, 1131a, 1131b, 1141a, 1141b, example respective gate dielectrics 1151a, 1152b, example respective source contacts 1141a, 1141b, example respective source regions 1161a, 116b, example respective drain contacts 1131a, 1113b, example respective drain regions 1171a, 1171b, example electrical interconnection layer 1200, and example silicon CMOS field effect transistor 1302 may include more than one of any or all of the illustrated elements, processes and devices.

[0074] FIGS. 19-22 are an example flowchart of an example process 900 of this disclosure. Accordingly, the flowchart is representative of machine readable instructions that may be executed to implement example electronic device structure shown in three- dimensional view 100 in FIG land shown in cross-sectional view 200 in FIG 2, and the elements, processes and/or devices illustrated in FIGS. 1-13. In these examples, the machine readable instructions implement programs for execution by a processor such as the processor 2312 shown in the example processor platform 2300 discussed below in connection with FIG. 23. For example, the foregoing may be used in automation in a context of a semiconductor fabrication facility to carry out the example process 900. The programs may be embodied in software stored on a tangible computer readable storage medium such as a CD-ROM, a floppy disk, a hard drive, a digital versatile disk (DVD), a Blu-ray disk, or a memory associated with the processor 2312, but the entire program and/or parts thereof could alternatively be executed by a device other than the processor 2312 and/or embodied in firmware or dedicated hardware. Further, although the example programs are described with reference to the flowchart illustrated in FIGS. 19-22, other methods in accordance with the teachings of this disclosure may alternatively be used. For example, the order of execution of the blocks may be changed, and/or some of the blocks described may be changed, eliminated, or combined. [0075] As mentioned above, the example processes of FIGS. 19-22 may be implemented using coded instructions (e.g., computer and/or machine readable instructions) stored on a tangible computer readable storage medium such as a hard disk drive, a flash memory, a read-only memory (ROM), a compact disk (CD), a digital versatile disk (DVD), a cache, a random-access memory (RAM) and/or any other storage device or storage disk in which information is stored for any duration (e.g., for extended time periods, permanently, for brief instances, for temporarily buffering, and/or for caching of the information). As used herein, the term tangible computer readable storage medium is expressly defined to include any type of computer readable storage device and/or storage disk and to exclude propagating signals and to exclude transmission media. As used herein, "tangible computer readable storage medium" and "tangible machine readable storage medium" are used interchangeably. In some examples, the example processes of FIGS. 19-22 may be implemented using coded instructions (e.g., computer and/or machine readable instructions) stored on a non-transitory computer and/or machine readable medium such as a hard disk drive, a flash memory, a readonly memory, a compact disk, a digital versatile disk, a cache, a random-access memory and/or any other storage device or storage disk in which information is stored for any duration (e.g., for extended time periods, permanently, for brief instances, for temporarily buffering, and/or for caching of the information). As used herein, the term non-transitory computer readable medium is expressly defined to include any type of computer readable storage device and/or storage disk and to exclude propagating signals and to exclude transmission media.

[0076] The method 900 of FIGS. 19-22 begins at block 601. At block 901 of the example of FIG. 19, a bottom insulator layer can be deposited on the substrate. At block 902 first and second bottom width dimensions of respective first and second islands of epitaxial material can be selected and determined by selecting first and second bottom width dimensions of the first and second trenches. At block 904, the bottom insulator layer can be patterned to form the first trench having the first selected bottom width dimension and the second trench having the second selected bottom width dimension in a patterned bottom insulator layer. For example, as shown in FIG. 4, first and second and third bottom insulator layer features 138a, 138b, 138c as well as first and second and third companion bottom insulator layer features 138aa, 138bb, 138cc can be formed on substrate 1 11 by patterning a first bottom insulator layer. Initially, prior to any patterning, a bottom insulator layer can be deposited on the substrate. The bottom width dimension of the first island of epitaxial material can be determined by selecting the first bottom width WTa of the first trench 230a, shown in the example of FIG. 2. Similarly, the bottom width dimension of the second island of epitaxial material can be determined by selecting the second bottom width WTb of the second trench 230b, shown in the example of FIG. 4. Similarly, the bottom width dimension of the third island of epitaxial material can be determined by selecting the third bottom width WTc of the third trench 230c, shown in the example of FIG. 4. The first and second and third bottom width dimensions WTa, WTb, WTc are substantially different from one another as shown in the example of FIG. 4.

[0077] At block 906 shown in the example of FIG. 19, thickness of the first and second islands of epitaxial material can be selected and determined by selecting a thickness of a sacrificial layer. At block 908, the sacrificial layer can be deposited on the first and second trenches formed in the bottom insulator layer on the substrate to have the selected thickness. At block 910, the sacrificial layer deposited on the first and second trenches formed in the bottom insulator layer includes depositing the sacrificial layer laterally over first and second features of the bottom insulator layer. At block 912, the laterally deposited sacrificial layer over the bottom insulator layer is formed in direct contact with the bottom insulator layer. At block 914, the sacrificial layer can be patterned to form a patterned sacrificial layer. For example, FIG. 5, shows the sacrificial layer after depositing and patterning the sacrificial layer. The sacrificial layer can include silicon nitride. A thickness of the first and second and third islands of epitaxial material can be selected and determined by selecting a thickness TS of the sacrificial layer. The sacrificial layer can be deposited on the first and second and third trenches formed in the patterned bottom insulator layer on the substrate to have the selected thickness TS. The sacrificial layer can be patterned to form a patterned sacrificial layer 500 including a first sacrificial island 526a, a second sacrificial island 526b and third sacrificial island 526c. As shown in the example of FIG. 5, the first sacrificial island 526a can be deposited over the first feature 138a of the bottom insulator layer. Further, the first sacrificial island 526a can be deposited in direct contact with the first feature 138a of the bottom insulator layer. Similarly, the second sacrificial island 526b can be deposited over the second feature 138b of the bottom insulator layer. The second sacrificial island 526b can be deposited in direct contact with the second feature 138b of the bottom insulator layer. Similarly, the third sacrificial island 526c can be deposited over the third feature 138c of the bottom insulator layer. The third sacrificial island 526c can be deposited in direct contact with the third feature 138c of the bottom insulator layer.

[0078] At block 916 of the example of FIG. 20, a deposition layer can be deposited over the patterned sacrificial layer. At block 918, depositing the deposition layer over the patterned sacrificial layer can include sandwiching the patterned sacrificial layer between the deposition layer and the substrate. At block 920, the depositing the deposition layer over the patterned sacrificial layer includes sandwiching the patterned sacrificial layer between the deposition layer and the first patterned insulator layer. For example, FIG. 6 shows the deposition layer 622 after the deposition layer 622 is deposited over the patterned sacrificial layer. The depositing the deposition layer 622 over the patterned sacrificial layer can include sandwiching the patterned sacrificial layer between the deposition layer and the substrate 111. The depositing the deposition layer 622 over the patterned sacrificial layer can include sandwiching the patterned sacrificial layer between the deposition layer and the patterned bottom insulator layer.

[0079] At block 922 of the example of FIG. 20, first and second aperture widths and locations can be selected based on respective widths and locations of the first and second features of the bottom insulator layer. At blocks 924 and 926 patterning the deposition layer can be patterned to form the first aperture having the first aperture width in the deposition layer over a first sacrificial island of the patterned sacrificial layer and to form the second aperture having the second aperture width in the deposition layer over a second sacrificial island of the patterned sacrificial layer. At block 928 of the example of FIG. 21, the patterning the deposition layer is to form the first aperture in the deposition layer over the first sacrificial island and over the first feature of the bottom insulator layer. Further the patterning the deposition layer is to form the second aperture in the deposition layer over the second sacrificial island and over the second feature of the bottom insulator layer. For example, FIG. 7 shows deposition layer 622 after first, second and third apertures 738a, 738b, 738c, are formed in the deposition layer 622. First and second and third aperture widths APWa, APWb, APWc and locations can be selected based on matching respective widths and matching respective vertical alignment of locations of the first and second and third features 138a, 138b, 138c of the bottom insulator layer. The first aperture 738a in the deposition layer 622 can be formed over the first sacrificial island 526a and over the first feature 138a of the bottom insulator layer. Similarly, the second aperture 738b in the deposition layer 622 can be formed over the second sacrificial island 526b and over the second feature 138b of the bottom insulator layer. Similarly, the third aperture 738c in the deposition layer 622 can be formed over the third sacrificial island 526c and over the third feature 138c of the bottom insulator layer. Further, the foregoing can advantageously facilitate mask reuse between the masking and patterning of features of the bottom insulator layer and the masking and patterning of the apertures. [0080] At block 930 of the example of FIG. 21, the patterned sacrificial layer can be etched away. The patterned sacrificial layer can be etched away through the first aperture in the deposition layer to form a first lumen having a selected height dimension determined by the selected thickness of the first island epitaxial material, and having a selected bottom width dimension determined by the selected bottom width dimension of the first island of epitaxial material. The first lumen can be sandwiched between the deposition layer and the substrate. Similarly, the patterned sacrificial layer can be etched away through the second aperture in the deposition layer to form a second lumen having a selected height dimension determined by the selected thickness of the second island epitaxial material, and having a selected bottom width dimension determined by the selected bottom width dimension of the second island of epitaxial material. The second lumen can be sandwiched between the deposition layer and the substrate. At block 932, a first nucleation layer can be deposited on a first island growth area in a first trench on a substrate. The first and second island growth areas can have a square shape, rectangular shape, or a polygon shape. Further, second and third nucleation layers can be deposited on a respective second and third island growth areas in respective second and third trenches on the substrate. The first and second nucleation layers can include Aluminum Nitride. For example, FIG. 8 shows the patterned sacrificial layer etched away to form first, second and third lumens 826a, 826b, 826c for confined epitaxy. FIG. 8 is also very similar to FIG. 3. In the example of FIG. 8, nucleation layers 228a, 228b, 228c are depicted using thickened black lines. As shown in the example of FIG. 8, the nucleation layers can be deposited through the first, second and third apertures in the deposition layer onto the island growth areas of the substrate 111.

[0081] At block 934 of the example of FIG. 21, by confined epitaxy a first island of epitaxial material can be deposited on the first nucleation layer on the first island growth area in the first trench and a second island of epitaxial material can be deposited on the second nucleation layer on the second island growth area in the second trench on the substrate. The epitaxial material includes gallium nitride, and the substrate can include silicon. The first and second islands of epitaxial material have respective bottom surfaces on respective ones of the first and second nucleation layers, have top surfaces and have selected layer thickness between the top and bottom surfaces so that the selected layer thickness is substantially equal for the first and second islands. The depositing by confined epitaxy includes depositing the first island of epitaxial material though a first aperture in a deposition layer into a first lumen having a selected height extending between the deposition layer and the first nucleation layer on the first island growth area. Further, the depositing by confined epitaxy can include depositing second and third islands of epitaxial material though respective second and third apertures in the deposition layer into respective second and third lumens having the selected height extending between the deposition layer and the respective second and third nucleation layers on the respective second and third island growth areas. The selected height is substantially equal for the first and second and third lumens. At block 936, the selected layer thickness of the first and second islands of epitaxial material can be formed to be confined by the selected height of the first and second lumen. For example, FIG. 9 shows variously sized, but yet coplanar, first, second and third GaN islands 126a, 126b, 126c for variously sized GaN transistors that can be grown selectively, by confined epitaxy through respective first, second and third apertures 728a, 728b, 728c, inside respective variously sized predefined insulator trenches 124a, 124b, 124c of the Si CMOS wafer, shown in the example of FIG. 9.

[0082] As shown in the example of FIG. 22 at block 938, the depositing by confined epitaxy the first and second and third islands of epitaxial material can include forming respective selected bottom width dimensions of the first and second and third islands of epitaxial material to be substantially different from one another and confined by the respective selected bottom width dimensions of the first and second and third lumens that are substantially different from one another. For example, the first and second and third trenches can have respective opposing trench walls and respective selected bottom width dimensions extending between the respective opposing trench walls. For example, the respective selected bottom width dimensions of the first and second and third trenches can be substantially different from one another. For example, the depositing by confined epitaxy the first and second and third islands of epitaxial material can include forming respective bottom width dimensions of the first and second islands of III-V material epitaxial layer to be substantially different from one another and confined by the respective selected bottom width dimensions of the first and second and third trenches being substantially different from one another. Further, the depositing by confined epitaxy the first and second and third islands of epitaxial material includes laterally growing the first and second islands of epitaxial mater layer over respective first and second features of the bottom insulator layer. The bottom insulator layer can include silicon dioxide. Additionally, the laterally grown epitaxial material of the first and second and third islands is formed in direct contact with respective first and second and third features of the bottom insulator layer. For example, because top growth of the first and second and third islands 126a, 126b, 126c, of III-V material is limited under the confined epitaxy template 622, as shown in the example of FIG. 9, top surfaces of the first and second and third islands 126a, 126b, 126c, of III-V material are substantially coplanar with one another. However, the first and second and third islands 126a, 126b, 126c, of III-V material have respective corresponding bottom width dimensions WGa, WGb, WGc, that are substantially different from one another. Similarly, the first and second and third trenches 124a, 124b, 124c, have respective corresponding bottom width dimensions WTa, WTb, WTc, that are substantially different from one another. Further, as shown in the example of FIG. 9, the first and second and third islands 126a, 126b, 126c, of III-V material have respective matching and substantially equal layer thickness TGa, TGb, TGc. Since the top surfaces 236a, 236b, 236c of the first and second and third islands 126a, 126b, 126c, of III-V material are substantially coplanar with one another, and since the layer thickness TGa, TGb, TGc, is substantially equal for the first and second and third islands 126a, 126b, 126c, of III-V material, the respective bottom surfaces of the first and second and third islands 126a, 126b, 126c, of III-V material are likewise substantially coplanar with one another. The first and second and third island growth areas have respective corresponding width dimensions WAa, WAb, WAc. The respective corresponding width dimensions of the first and second island growth areas WAa, WAb, WAc, are substantially different from one another, as shown for example in FIG. 9. Similarly, the respective nucleation layers 228a, 228b, 228c, on the first and second and third island growth areas 230a, 230b, 230c have respective corresponding width dimensions WNa,WNb,WNc. The respective corresponding width dimensions WNa, WNb, WNc, of the respective nucleation layers 228a, 228b, 228c, on the first and second and third island growth areas 230a, 230b, 230c, are substantially different from one another. As shown in the example of FIG. 2, the first and second and third trenches 124a, 124b, 124c can include respective first and second and third bottom insulator layer features 138a, 138b, 138c filling respective peripheral spaces around the first and second and third island growth areas 230a, 230b, 230c. As shown in the example of FIG. 2, the first and second and third islands 126a, 126b, 126c, of III-V material can extend laterally over the respective first and second and third bottom insulator layer features 138a, 138b, 138c. The first and second and third features 138a, 138b, 138c of the bottom insulator layer can include silicon dioxide. In the example of FIG. 9, the laterally extended first and second and third islands 126a, 126b, 126c, of III-V material are formed in direct contact with the respective first and second and third bottom insulator layer features 138a, 138b, 138c.

[0083] As shown in the example of FIG. 22 at block 938, a top portion of deposition layer can be removed to expose respective coplanar top surfaces of first, second and third islands of epitaxial III-V material. For example, FIG. 10 is a view very similar to FIG. 9, after the top portion of the deposition layer is removed, for example by polishing, to expose respective coplanar top surfaces 136a, 136b, 136c, of first, second, and third islands 126a, 126b, 126c, of epitaxial III-V material on the Si CMOS substrate 111. The example of FIG. 10 is very similar to the example of FIG. 2, already discussed in detail previously herein.

[0084] As shown in the example of FIG. 22 at block 942, respective device layers can be deposited on the first and second islands of epitaxial material to form respective first and second transistors. For example, FIG. 11 is a cross-sectional view of islands of epitaxial III- V material after device layers are deposited to form first and second transistors 1126a, 1126b. In the example shown in FIG. 11 , respective device layers 1118a, 1118b are deposited on respective device layers 1117a, 1117b on respective III-V material layers 1116a, 1116b. In the example shown in FIG. 11, device layers 1117a, 1117b are deposited to enhance mobility of respective two-dimensional electron gas ("2DEG") portions 1120a 1120b of the respective III-V material layers 1116a, 1116b. In the example shown in FIG. 11, respective device layers 1117a, 1117b are A1N layers.

[0085] As shown in the example of FIG. 22 at block 944, the first and second III-V transistors can be electrically coupled (e.g. electrically interconnected). For example, FIG. 12 is a cross-sectional view very similar to FIG. 11, but including a block 1200 representing addition of an electrical interconnection layer. The electrical interconnection layer 1200 can electrically interconnect the first transistor 1126a and the second transistor 1126b. The substantially coplanar top surfaces of the first transistor 1126a and the second transistor 1126b (and the corresponding substantially coplanar top surfaces for islands of III-V material) can facilitate the electrical interconnection of the first transistor 1126a and the second transistor 1126b using electrical interconnection layer 1200.

[0086] As shown in the example of FIG. 22, at block 946, a silicon CMOS transistor can be fabricated on the same integrated substrate as the first and second transistors. At block 948, electrically interconnecting at least one of the first and second transistors with the silicon CMOS transistor fabricated on the same integrated substrate. For example, FIG. 13 is a cross-sectional view very similar to FIG. 11, but including addition of a block representing a silicon CMOS field effect transistor 1302 and addition of a block representing an electrical interconnection layer 1300. The example of FIG. 13 shows insulator trenches of various sizes disposed within a larger silicon trench etched into Si CMOS substrate 111. As shown in the example of FIG. 13, the silicon CMOS field effect transistor 1302 can be arranged on the Si CMOS substrate 111 outside of the larger silicon trench in Si CMOS substrate 111, and can be arranged adjacent to an extremity of the larger silicon trench in Si CMOS substrate 111. The electrical interconnection layer 1300 can electrically interconnect the silicon CMOS transistor 1302 with at least one of the first transistor 1126a and the second transistor 1126b. A top surface of the silicon CMOS transistor 1302 and top surfaces of the first transistor 1126a and the second transistor 1126b are substantially coplanar with one another to facilitate interconnecting the silicon CMOS transistor 1302 with at least one of the first transistor 1126a and the second transistor 1126b. Further, this can facilitate co-integration of GaN devices (e.g., transistor 1126b or other GaN based devices) for power management integrated circuits ("PMIC") and RF power amplifier ("PA") applications in close proximity to silicon (Si) Complementary Metal Oxide Semiconductor ("CMOS") circuits (e.g., silicon CMOS transistor 1302) for system on chip ("SoC") products. After block 948, the method 900 can end.

[0087] FIG. 23 is a block diagram of an example processing platform 2300 capable of executing the example machine-readable instructions of FIGS. 19-22 to implement example electronic device structure shown in three-dimensional view 100 in FIG land shown in cross- sectional view 200 in FIG 2, and the elements, processes and/or devices illustrated in FIGS. 1-13. The processor platform 2300 of the illustrated example includes a processor 2312. The processor 2312 of the illustrated example is hardware. For example, the processor 2312 can be implemented by one or more integrated circuits, logic circuits, microprocessors or controllers from any desired family or manufacturer.

[0088] The processor 2312 of the illustrated example includes a local memory 2313 (e.g., a cache), and executes instructions to implement the example operations of this disclosure. The processor 2312 of the illustrated example is in communication with a main memory including a volatile memory 2314 and a non-volatile memory 2316 via a bus 2318. The volatile memory 2314 may be implemented by Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM) and/or any other type of random access memory device. The non-volatile memory 2316 may be implemented by flash memory and/or any other desired type of memory device. Access to the main memory 2314, 2316 is controlled by a memory controller.

[0089] The processor platform 2300 of the illustrated example also includes an interface circuit 2320. The interface circuit 2320 may be implemented by any type of interface standard, such as an Ethernet interface, a universal serial bus (USB), and/or a PCI express interface. In the illustrated example, one or more input devices 2322 are connected to the interface circuit 2320. The input device(s) 2322 permit(s) a user to enter data and commands into the processor 2312. The input device(s) can be implemented by, for example, an audio sensor, a microphone, a keyboard, a button, a mouse, a touchscreen, a track-pad, a trackball, isopoint and/or a voice recognition system.

[0090] One or more output devices 2324 are also connected to the interface circuit 2320 of the illustrated example. The output devices 2324 can be implemented, for example, by display devices (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display, a cathode ray tube display (CRT), a touchscreen, a tactile output device, a printer and/or speakers). The interface circuit 2320 of the illustrated example, thus, typically includes a graphics driver card, a graphics driver chip or a graphics driver processor.

[0091] The interface circuit 2320 of the illustrated example also includes a communication device such as a transmitter, a receiver, a transceiver, a modem and/or network interface card to facilitate exchange of data with external machines (e.g., computing devices of any kind) via a network 2326 (e.g., an Ethernet connection, a digital subscriber line (DSL), a telephone line, coaxial cable, a cellular telephone system, etc.).

The processor platform 2300 of the illustrated example also includes one or more mass storage devices 2328 for storing software and/or data. Examples of such mass storage devices 2328 include flash devices, floppy disk drives, hard drive disks, optical compact disk (CD) drives, optical Blu-ray disk drives, RAID systems, and optical digital versatile disk (DVD) drives. Coded instructions 2332 representative of the example machine readable instructions of FIGS. 19-22 may be stored in the mass storage device 2328, in the volatile memory 2314, in the non-volatile memory 2316, and/or on a removable tangible computer readable storage medium such as a CD or DVD.

[0092] As used herein, when the phrase "at least" is used as the transition term in a preamble of a claim, it is open-ended in the same manner as the term "comprising" is open ended. As used herein, "substantially coplanar" is defined to mean less than 100 nanometers deviation from coplanar. As used herein, "substantially equal" is defined to mean less than 100 nanometers deviation from equal. As used herein, "substantially different" is defined to mean a difference of fifty percent or more. As used herein, "substantially greater" is defined to mean an increase of fifty percent or more.

[0093] Example 1 is a method to manufacture an electronic device, the method comprising, depositing a first nucleation layer on a first island growth area in a first trench on a substrate, depositing a second nucleation layer on a second island growth area in a second trench on the substrate, and depositing by confined epitaxy a first island of epitaxial material on the first nucleation layer on the first island growth area in the first trench and a second island of epitaxial material on the second nucleation layer on the second island growth area in the second trench on the substrate.

[0094] Example 2 includes the method as defined in example 1, in which the first and second islands of epitaxial material have respective bottom surfaces on respective ones of the first and second nucleation layers, have top surfaces and have selected layer thickness between the top and bottom surfaces so that the selected layer thickness is substantially equal for the first and second islands, and the depositing by confined epitaxy the first and second islands of epitaxial material includes, depositing the first island of epitaxial material though a first aperture in a deposition layer into a first lumen having a selected height extending between the deposition layer and the first nucleation layer on the first island growth area, depositing the second island of epitaxial material though a second aperture in the deposition layer into a second lumen having the selected height extending between the deposition layer and the second nucleation layer on the second island growth area, the selected height being substantially equal for the first and second lumens, and forming the selected layer thickness of the first and second islands of epitaxial material to be confined by the selected height of the first and second lumen.

[0095] Example 3 includes the method as defined in example 2, in which the first and second lumens have respective selected bottom width dimensions that are substantially different from one another, and the depositing by confined epitaxy the first and second islands of epitaxial material includes forming respective selected bottom width dimensions of the first and second islands of epitaxial material to be substantially different from one another and confined by the respective selected bottom width dimensions of the first and second lumens that are substantially different from one another.

[0096] Example 4 includes the method as defined in example 1, in which the first and second trenches have respective opposing trench walls and respective selected bottom width dimensions extending between the respective opposing trench walls, the respective selected bottom width dimensions of the first and second trenches being substantially different from one another, and the depositing by confined epitaxy the first and second islands of epitaxial material includes forming respective bottom width dimensions of the first and second islands of III-V material epitaxial layer to be substantially different from one another and confined by the respective selected bottom width dimensions of the first and second trenches being substantially different from one another.

[0097] Example 5 includes the method as defined in one of examples 1 -4, further including depositing respective device layers on the first and second islands of epitaxial material to form respective first and second transistors, electrically interconnecting the first and second III-V transistors, fabricating a silicon CMOS transistor on the same integrated substrate as the first and second transistors, and electrically interconnecting at least one of the first and second transistors with the silicon CMOS transistor fabricated on the same integrated substrate.

[0098] Example 6 includes the method as defined in one of examples 1-4, wherein the epitaxial material includes gallium nitride, and the substrate includes silicon.

[0099] Example 7 includes the method as defined in one of examples 1-4, wherein the nucleation layer includes Aluminum Nitride.

[00100] Example 8 includes the method as defined in one of examples 1-4, wherein a member of the first and second island growth areas has a square shape, rectangular shape, or a polygon shape.

[00101] Example 9 includes the method as defined in one of examples 1-4, including depositing a bottom insulator layer on the substrate, selecting a first bottom width dimension of the first island of epitaxial material to be determined by selecting a first bottom width of the first trench, selecting a second bottom width dimension of the second island of epitaxial material to be determined by selecting a second bottom width dimension of the second trench, the first and second bottom width dimensions being substantially different from one another, and patterning the bottom insulator layer to form the first trench having the first selected bottom width dimension and the second trench having the second selected bottom width dimension in a patterned bottom insulator layer.

[00102] Example 10 includes the method as defined in example 9, wherein the depositing by confined epitaxy the first and second islands of epitaxial material includes laterally growing the first and second islands of epitaxial mater layer over respective first and second features of the bottom insulator layer.

[00103] Example 11 includes the method as defined in example 9, wherein the bottom insulator layer includes silicon dioxide.

[00104] Example 12 includes the method as defined in example 10, wherein the laterally grown epitaxial material of the first and second islands is formed in direct contact with respective first and second features of the bottom insulator layer.

[00105] Example 13 includes the method as defined in example 9, including selecting a thickness of the first and second islands of epitaxial material to be determined by selecting a thickness of a sacrificial layer, depositing the sacrificial layer on the first and second trenches formed in the bottom insulator layer on the substrate to have the selected thickness, and patterning the sacrificial layer to form a patterned sacrificial layer.

[00106] Example 14 includes the method as defined in example 13, in which the depositing the sacrificial layer on the first and second trenches formed in the bottom insulator layer includes depositing the sacrificial layer laterally over first and second features of the bottom insulator layer.

[00107] Example 15 includes the method as defined in example 14, wherein the laterally deposited sacrificial layer over the bottom insulator layer is formed in direct contact with the bottom insulator layer.

[00108] Example 16 includes the method as defined in example 13, including depositing a deposition layer over the patterned sacrificial layer.

[00109] Example 17 includes the method as defined in example 16, wherein the depositing the deposition layer over the patterned sacrificial layer includes sandwiching the patterned sacrificial layer between the deposition layer and the substrate.

[00110] Example 18 includes the method as defined in example 17, wherein the depositing the deposition layer over the patterned sacrificial layer includes sandwiching the patterned sacrificial layer between the deposition layer and the first patterned insulator layer.

[00111] Example 19 includes the method as defined in example 17, further including, selecting first and second aperture widths and locations based on respective widths and locations of the first and second features of the bottom insulator layer, and patterning the deposition layer to form the first aperture having the first aperture width in the deposition layer over a first sacrificial island of the patterned sacrificial layer and to form the second aperture having the second aperture width in the deposition layer over a second sacrificial island of the patterned sacrificial layer.

[00112] Example 20 includes the method as defined in claim 19, in which depositing the sacrificial layer on the first and second trenches formed in the first patterned insulator layer includes depositing the sacrificial layer laterally over the first patterned insulator layer, the patterning the sacrificial layer to form the patterned sacrificial layer includes forming a first and second sacrificial islands deposited laterally over respective first and second features of the bottom insulator layer, the patterning the deposition layer is to form the first aperture in the deposition layer over the first sacrificial island and over the first feature of the bottom insulator layer, and the patterning the deposition layer is to form the second aperture in the deposition layer over the second sacrificial island and over the second feature of the bottom insulator layer. [00113] Example 21 includes the method as defined in claim 19, including etching away the patterned sacrificial layer, through the first aperture in the deposition layer to form a first lumen having a selected height dimension determined by the selected thickness of the first island epitaxial material, and having a selected bottom width dimension determined by the selected bottom width dimension of the first island of epitaxial material, the first lumen being sandwiched between the deposition layer and the substrate, and through the second aperture in the deposition layer to form a second lumen having a selected height dimension determined by the selected thickness of the second island epitaxial material, and having a selected bottom width dimension determined by the selected bottom width dimension of the second island of epitaxial material, the second lumen being sandwiched between the deposition layer and the substrate.

[00114] Example 22 is an electronic device as manufactured in any preceding example.

[00115] Example 23 is machine-readable storage including machine-readable instructions, when executed, to implement a method or realize an electronic device as in any preceding example.

[00116] Example 24 is an electronic device, including a first island growth area on a substrate, a second island growth area on the substrate, first and second islands of III-V material having respective bottom surfaces over respective ones of the first and second island growth areas, the first and second islands of III-V material having top surfaces, the top surfaces of the first and second islands of III-V material being substantially coplanar with one another, in which the first and second islands of III-V material have respective corresponding bottom width dimensions that are substantially different from one another.

[00117] Example 25 includes the electronic device as defined in example 24, in which the first and second islands of III-V material have substantially equal layer thickness.

[00118] Example 26 includes the electronic device as defined in example 24, in which the respective bottom surfaces of the first and second islands of III-V material are substantially coplanar with one another.

[00119] Example 27 includes the electronic device as defined in example 24, including respective device layers on the first and second islands of III-V material.

[00120] Example 28 includes the electronic device as defined in one of examples 24-27, in which the electronic device includes first and second transistors, the first transistor including the first island of III-V material, and the second transistor including the second island of III-V material. [00121] Example 29 includes the electronic device as defined in example 28, in which the first and second transistors have respective sizes that are substantially different from one another.

[00122] Example 30 includes the electronic device as defined in example 28, in which the first and second transistors have respective corresponding bottom width dimensions that are substantially different from one another.

[00123] Example 31 includes the electronic device as defined in example 28, including an electrical interconnection layer electrically interconnecting the first and second transistors, the substantially coplanar top surfaces to facilitate the electrical interconnection of the first and second transistors.

[00124] Example 32 includes the electronic device as defined in example 28, including a silicon CMOS transistor having a bottom surface on the substrate and an opposing top surface, and an electrical interconnection layer electrically interconnecting the silicon CMOS transistor with at least one of the transistors, wherein the top surface of the silicon CMOS transistor and the top surfaces of the first and second islands of III-V material are substantially coplanar with one another to facilitate interconnecting the silicon CMOS transistor with at least one of the transistors.

[00125] Example 33 includes the electronic device as defined in one of examples 24-27, including a silicon CMOS transistor having a bottom surface on the substrate, a top surface opposing the bottom surface, and a thickness extending between the bottom surface and the top surface, the first and second islands of III-V material having layer thicknesses substantially greater than the thicknesses of the silicon CMOS transistor.

[00126] Example 34 includes the electronic device as defined in one of examples 24-27, in which the first and second island growth areas have respective corresponding width dimensions, the respective corresponding width dimensions of the first and second island growth areas being substantially different from one another.

[00127] Example 35 includes the electronic device as defined in one of examples 24-27, in which the first and second islands of III-V material include a III-V binary, ternary or quaternary semiconductor and the island growth areas include silicon.

[00128] Example 36 includes the electronic device as defined in one of examples 24-27, in which a thickness dimension of a member of the first and second islands of III-V material is aligned along a {0001} crystal orientation of the III-V material. [00129] Example 37 includes the electronic device as defined in one of examples 24-27, in which a member of the first and second island growth areas has a square shape, rectangular shape, or a polygon shape.

[00130] Example 38 includes the electronic device as defined in one of examples 24-27, in which the first and second islands of III-V material include an epitaxial layer of III-V material.

[00131] Example 39 includes the electronic device as defined in one of examples 24-27, in which the first and second islands of III-V material include a confined epitaxial layer of III-V material.

[00132] Example 40 includes the electronic device as defined in one of examples 24-27, in which the first and second islands of III-V material include Selective Area Growth (SAG) islands of III-V material.

[00133] Example 41 is an electronic device, including a first island growth area within a first trench on a substrate, a second island growth area within a second trench on the substrate, respective first and second nucleation layers on the first and second island growth areas, and first and second islands of III-V material having respective bottom surfaces on respective ones of the first and second nucleation layers, the first and second islands of III-V material having top surfaces, the top surfaces of the first and second islands of III-V material being substantially coplanar with one another, in which the first and second islands of III-V material have respective corresponding bottom width dimensions that are substantially different from one another.

[00134] Example 42 includes the electronic device as defined in example 41, in which the first and second islands of III-V material have substantially equal layer thickness.

[00135] Example 43 includes the electronic device as defined in example 41, in which the respective bottom surfaces of the first and second islands of III-V material are substantially coplanar with one another.

[00136] Example 44 includes the electronic device as defined in one of examples 41-43, including respective device layers on the first and second islands of III-V material.

[00137] Example 45 includes the electronic device as defined in one of examples 41-43, in which the electronic device includes first and second transistors, the first transistor including the first island of III-V material, and the second transistor including the second island of III-V material. [00138] Example 46 includes the electronic device as defined in example 45, in which the first and second transistors have respective sizes that are substantially different from one another.

[00139] Example 47 includes the electronic device as defined in example 45, in which the first and second transistors have respective corresponding bottom width dimensions that are substantially different from one another.

[00140] Example 48 includes the electronic device as defined in example 45, including an electrical interconnection layer electrically interconnecting the first and second transistors, respective top surfaces the first and second transistors being substantially coplanar with one another to facilitate the electrical interconnection of the first and second transistors.

[00141] Example 49 includes the electronic device as defined in example 45, including a silicon CMOS transistor having a bottom surface on the substrate and an opposing top surface, and an electrical interconnection layer electrically interconnecting the silicon CMOS transistor with at least one of the transistors, wherein the top surface of the silicon CMOS transistor and the top surfaces of the first and second islands of III-V material are substantially coplanar with one another to facilitate interconnecting the silicon CMOS transistor to at least one of the transistors.

[00142] Example 50 includes the electronic device as defined in one of examples 41-43, including a silicon CMOS transistor having a bottom surface on the substrate, a top surface opposing the bottom surface, and a thickness extending between the bottom surface and the top surface, the first and second islands of III-V material having layer thicknesses substantially greater than the thicknesses of the silicon CMOS transistor.

[00143] Example 51 includes the electronic device as defined in one of examples 41-43, wherein the first and second trenches have respective corresponding bottom width dimensions that are substantially different from one another.

[00144] Example 52 includes the electronic device as defined in one of examples 41-43, wherein the first and second island growth areas have respective

corresponding width dimensions, the respective corresponding width dimensions of the first and second island growth areas being substantially different from one another.

[00145] Example 53 includes the electronic device as defined in one of examples 41-43, wherein the respective nucleation layers on the first and second island growth areas have respective corresponding width dimensions, the respective corresponding width dimensions of the respective nucleation layers on the first and second island growth areas being substantially different from one another. [00146] Example 54 includes the electronic device as defined in one of examples 41-43, wherein the first and second islands of III-V material include a III-V binary, ternary or quaternary semiconductor and the island growth areas include silicon.

[00147] Example 55 includes the electronic device as defined in one of examples 41-43, in which the first and second trenches including respective first and second bottom insulator layer features filling respective peripheral spaces around the first and second island growth areas, the first and second islands of III-V material extend laterally over the respective first and second bottom insulator layer features.

[00148] Example 56 includes the electronic device as defined in example 55, in which the bottom insulator layer includes silicon dioxide.

[00149] Example 57 includes the electronic device as defined in example 55, in which the laterally extended first and second islands of III-V material are formed in direct contact with the respective first and second bottom insulator layer features.

[00150] Example 58 includes the electronic device as defined in one of examples 41-43, in which the nucleation layer includes Aluminum Nitride.

[00151] Example 59 includes the electronic device as defined in one of examples 41-43, in which a thickness dimension of a member of the first and second islands of III-V material is aligned along a {0001} crystal orientation of the III-V material.

[00152] Example 60 includes the electronic device as defined in one of examples 41-43, in which a member of the first and second island growth areas has a square shape, rectangular shape, or a polygon shape.

[00153] Example 61 includes the electronic device as defined in one of examples 41-43, in which the first and second islands of III-V material include an epitaxial layer of III-V material.

[00154] Example 62 includes the electronic device as defined in one of examples 41-43, in which the first and second islands of III-V material include a confined epitaxial layer of III-V material.

[00155] Example 63 includes the electronic device as defined in one of examples 41-43, in which the first and second islands of III-V material layer include Selective Area Growth (SAG) islands of III-V material.

[00156] Although certain example methods, apparatus and articles of manufacture have been disclosed herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all methods, apparatus and articles of manufacture fairly falling within the scope of the claims of this patent.

Claims

What Is Claimed Is:

1. An electronic device, comprising:

a first island growth area within a first trench on a substrate;

a second island growth area within a second trench on the substrate;

respective first and second nucleation layers on the first and second island growth areas; and

first and second islands of III-V material having respective bottom surfaces on respective ones of the first and second nucleation layers, the first and second islands of III-V material having top surfaces, the top surfaces of the first and second islands of III-V material being substantially coplanar with one another, in which the first and second islands of III-V material have respective corresponding bottom width dimensions that are substantially different from one another.

2. The electronic device as defined in claim 1 , in which the first and second islands of III-V material have substantially equal layer thickness.

3. The electronic device as defined in claim 1 , in which the respective bottom surfaces of the first and second islands of III-V material are substantially coplanar with one another.

4. The electronic device as defined in claims 1 , including respective device layers on the first and second islands of III-V material.

5. The electronic device as defined in claim 1 , in which the electronic device includes first and second III-V transistors, the first III-V transistor including the first island of III-V material, and the second III-V transistor including the second island of III-V material.

6. The electronic device as defined in claim 5, in which the first and second III-V transistors have respective sizes that are substantially different from one another.

7. The electronic device as defined in claim 5, in which the first and second III-V transistors have respective corresponding bottom width dimensions that are substantially different from one another.

8. The electronic device as defined in claim 5, including an electrical interconnection layer electrically interconnecting the first and second III-V transistors, respective top surfaces the first and second III-V transistors being substantially coplanar with one another to facilitate the electrical interconnection of the first and second III-V transistors.

9. The electronic device as defined in claim 5, including:

a silicon CMOS transistor having a bottom surface on the substrate and an opposing top surface; and

an electrical interconnection layer electrically interconnecting the silicon CMOS transistor with at least one of the III-V transistors, wherein the top surface of the silicon CMOS transistor and the top surfaces of the first and second islands of III-V material are substantially coplanar with one another to facilitate interconnecting the silicon CMOS transistor to the at least one of the III-V transistors.

10. The electronic device as defined in claim 1, including a silicon CMOS transistor having a bottom surface on the substrate, a top surface opposing the bottom surface, and a thickness extending between the bottom surface and the top surface, the first and second islands of III-V material having layer thicknesses substantially greater than the thicknesses of the silicon CMOS transistor.

11. The electronic device as defined in claim 1, in which the first and second trenches have respective corresponding bottom width dimensions that are substantially different from one another.

12. The electronic device as defined in claim 1, in which the first and second island growth areas have respective corresponding width dimensions, the respective corresponding width dimensions of the first and second island growth areas being substantially different from one another.

13. The electronic device as defined in claim 1, in which the respective nucleation layers on the first and second island growth areas have respective corresponding width dimensions, the respective corresponding width dimensions of the respective nucleation layers on the first and second island growth areas being substantially different from one another.

14. The electronic device as defined in claim 1 , in which the first and second islands of III-V material include a III-V binary, ternary or quaternary semiconductor and the island growth areas include silicon.

15. The electronic device as defined in claims 1 , in which the first and second trenches including respective first and second bottom insulator layer features filling respective peripheral spaces around the first and second island growth areas, the first and second islands of III-V material extend laterally over the respective first and second bottom insulator layer features.

16. A method to manufacture an electronic device, comprising:

depositing a first nucleation layer on a first island growth area in a first trench on a substrate;

depositing a second nucleation layer on a second island growth area in a second trench on the substrate; and

depositing by confined epitaxy a first island of epitaxial material on the first nucleation layer on the first island growth area in the first trench and a second island of epitaxial material on the second nucleation layer on the second island growth area in the second trench on the substrate.

17. The method as defined in claim 16, in which:

the first and second islands of epitaxial material have respective bottom surfaces on respective ones of the first and second nucleation layers, have top surfaces and have selected layer thickness between the top and bottom surfaces so that the selected layer thickness is substantially equal for the first and second islands; and

the depositing by confined epitaxy the first and second islands of epitaxial material includes:

depositing the first island of epitaxial material though a first aperture in a deposition layer into a first lumen having a selected height extending between the deposition layer and the first nucleation layer on the first island growth area;

depositing the second island of epitaxial material though a second aperture in the deposition layer into a second lumen having the selected height extending between the deposition layer and the second nucleation layer on the second island growth area, the selected height being substantially equal for the first and second lumens; and forming the selected layer thickness of the first and second islands of epitaxial material to be confined by the selected height of the first and second lumen.

18. The method as defined in claim 16, further including:

depositing respective device layers on the first and second islands of epitaxial material to form respective first and second III-V transistors;

electrically interconnecting the first and second III-V transistors:

fabricating a silicon CMOS transistor on the same integrated substrate as the first and second III-V transistors; and

electrically interconnecting at least one of the first and second III-V transistors with the silicon CMOS transistor fabricated on the same integrated substrate.

19. An electronic device, comprising:

a first island growth area on a substrate;

a second island growth area on the substrate; and

first and second islands of III-V material having respective bottom surfaces over respective ones of the first and second island growth areas, the first and second islands of III- V material having top surfaces, the top surfaces of the first and second islands of III-V material being substantially coplanar with one another, in which the first and second islands of III-V material have respective corresponding bottom width dimensions that are substantially different from one another.

20. The electronic device as defined in claim 19, in which the electronic device includes first and second III-V transistors, the first III-V transistor including the first island of III-V material, and the second III-V transistor including the second island of III-V material.