WO2018142822A1 - 表示装置および投射型表示装置 - Google Patents

表示装置および投射型表示装置 Download PDF

Info

Publication number
WO2018142822A1
WO2018142822A1 PCT/JP2017/046963 JP2017046963W WO2018142822A1 WO 2018142822 A1 WO2018142822 A1 WO 2018142822A1 JP 2017046963 W JP2017046963 W JP 2017046963W WO 2018142822 A1 WO2018142822 A1 WO 2018142822A1
Authority
WO
WIPO (PCT)
Prior art keywords
light
substrate
light shielding
shielding film
film
Prior art date
Application number
PCT/JP2017/046963
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
津野　仁志
Original Assignee
ソニー株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ソニー株式会社 filed Critical ソニー株式会社
Priority to JP2018565994A priority Critical patent/JP7028192B2/ja
Priority to CN201780084744.8A priority patent/CN110226121B/zh
Publication of WO2018142822A1 publication Critical patent/WO2018142822A1/ja

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present disclosure relates to, for example, a display device used as a light modulation device and a projection display device including the same.
  • a projection-type liquid crystal display device (liquid crystal projector) generates image light by modulating light from a light source with a light valve, and displays the image light on a screen for display.
  • the light valve (light modulation device) is composed of a liquid crystal panel, and modulates light by, for example, each pixel being driven in an active matrix according to a video signal from the outside.
  • Liquid crystal panels are highly demanded for higher brightness and are required to improve the aperture ratio of pixels.
  • improving the aperture ratio reduces the light shielding area of the TFT.
  • LDD Lightly Doped Drain
  • Patent Documents 1 and 2 for example, a pair of grooves is provided on both sides of the semiconductor layer, and the light shielding layer is provided in the grooves to improve the light shielding property of the semiconductor layer and suppress the occurrence of leakage current.
  • An electro-optical device (display device) is disclosed.
  • Patent Document 3 discloses an electro-optical device in which an optical surface that guides light that is about to deviate from the opening region to the opening region is formed between the opening region and the non-opening region.
  • the aperture ratio and the light shielding property are basically in a trade-off relationship, but the liquid crystal panel is required to achieve both high luminance and improved image quality.
  • a display device includes a first substrate and a second substrate that are opposed to each other with a liquid crystal layer interposed therebetween.
  • the first substrate is provided on the support substrate and the plurality of substrates that intersect with each other. Scanning lines and a plurality of signal lines, TFT elements respectively provided at intersections of the plurality of scanning lines and the plurality of signal lines, and a conductive material, and in a plan view, the plurality of scanning lines And a light-shielding film provided along the line.
  • a projection display device includes a light modulation device that modulates light from a light source, and includes the display device according to the embodiment of the present disclosure as a light modulation device.
  • a light-shielding film containing is formed. Accordingly, it is possible to improve the light shielding property of the TFT element provided for each pixel without restricting the opening of the pixel.
  • the conductive light shielding film is formed along the plurality of scanning lines in a plan view.
  • the light shielding property of the TFT element is improved without restricting the aperture ratio. Therefore, it is possible to achieve both higher luminance and improved image quality.
  • FIG. 2 is a schematic plan view of a liquid crystal panel according to a first embodiment of the present disclosure.
  • FIG. 2 is a cross-sectional schematic diagram of the whole liquid crystal panel shown in FIG.
  • FIG. 2 is a schematic diagram illustrating a cross section of a drive substrate constituting the liquid crystal panel taken along the line II in FIG. 1.
  • FIG. 2 is a schematic diagram showing a cross section of a drive substrate constituting the liquid crystal panel taken along the line II-II shown in FIG.
  • FIG. 3 is a schematic diagram showing a cross section of a drive substrate constituting the liquid crystal panel taken along line III-III shown in FIG. It is sectional drawing for demonstrating the manufacturing method of the drive substrate which comprises the liquid crystal panel shown in FIG. It is sectional drawing showing the process of following FIG. 6A.
  • FIG. 6B It is sectional drawing showing the process of following FIG. 6B. It is sectional drawing showing the process of following FIG. 6C. It is sectional drawing showing the process of following FIG. 6D.
  • FIG. 6D It is a schematic diagram showing the positional relationship of a scanning line, a gate electrode, and a through-hole. It is a figure showing an example of the composition of the display provided with the liquid crystal panel of this indication. It is a figure showing an example of composition of a spatial light modulation part. It is a figure showing an example of the circuit structure of a pixel. It is a schematic diagram showing the cross section of the drive substrate which comprises the liquid crystal panel which concerns on 2nd Embodiment of this indication. It is sectional drawing for demonstrating the manufacturing method of the drive substrate shown in FIG.
  • FIG. 14 is a cross-sectional view for explaining a method for manufacturing the drive substrate shown in FIG. 13. It is sectional drawing showing the process of following FIG. 14A. It is a plane schematic diagram of the drive board which constitutes the liquid crystal panel concerning modification 1 of this indication.
  • FIG. 16 is a schematic diagram illustrating a cross section of the drive substrate taken along line IV-IV illustrated in FIG. 15. It is a plane schematic diagram of the drive board which constitutes the liquid crystal panel concerning modification 2 of this indication.
  • FIG. 17 is a schematic diagram illustrating a cross section of the drive substrate taken along the line VV illustrated in FIG. 16.
  • FIG. 20 is a schematic diagram showing a cross section of the drive substrate taken along the line VI-VI shown in FIG. 19.
  • FIG. 21 is a cross-sectional view for illustrating the method for manufacturing the drive substrate shown in FIG. 20. It is sectional drawing showing the process of following FIG. 21A.
  • FIG. 22C is a cross-sectional diagram illustrating a process following the process in FIG. 21B. It is a mimetic diagram showing the section of the drive substrate which constitutes the liquid crystal panel concerning modification 3 of this indication.
  • FIG. 24 is a schematic diagram showing a cross section of the drive substrate taken along the line VII-VII shown in FIG. 23.
  • First embodiment an example in which a light shielding film is formed along a scanning line in a plan view
  • Configuration of liquid crystal panel 1-2 Manufacturing method of driving substrate 1-3.
  • Action / Effect Second embodiment example in which a light shielding film is also formed above a transistor
  • Third embodiment example in which through holes are formed and scanning lines are separated in a lump
  • Modification 1 (example in which a scanning line and a gate electrode are directly connected) 5).
  • Modification 2 (Example in which a potential is supplied to the gate electrode outside the effective pixel region) 6).
  • Fourth Embodiment (Example in which a light shielding film and an opening are formed after the first wiring is formed) 7).
  • Modification 3 (example in which a light shielding film and an opening are formed after the third wiring is formed) 8).
  • Modification 4 (example of bottom-gate transistor)
  • FIG. 1 schematically shows a planar configuration of a display device (liquid crystal panel 1) according to the first embodiment of the present disclosure.
  • FIG. 2 schematically shows a cross-sectional configuration of the entire liquid crystal panel 1 shown in FIG.
  • the liquid crystal panel 1 has a pixel region 1A in which a plurality of pixels P are arranged in a matrix and a peripheral region 1B around the pixel region 1B (see FIG. 9), for example, a projection display device (projector 100, see FIG. 8). ) Is used as a light modulation device (spatial light modulation unit 130).
  • liquid crystal panel 1 a drive substrate 40A (first substrate) and a counter substrate 50 (second substrate) are disposed to face each other with a liquid crystal cell 60 (liquid crystal layer) interposed therebetween.
  • the liquid crystal panel 1 of the present embodiment has a configuration in which a light shielding film 15 having conductivity is provided along a plurality of scanning lines WSL provided on the drive substrate 40A in plan view.
  • “along the scanning line WSL” means a case where it is provided on the scanning line WSL or in contact with the end face of the scanning line WSL, and another layer (for example, between the scanning line WSL and the light shielding film 15). This includes the case where the insulating film 12) is interposed. In the present embodiment, an example in which the light shielding film 15 is provided over the scanning line WSL is shown.
  • the liquid crystal panel 1 includes the liquid crystal cell 60 between the drive substrate 40 ⁇ / b> A and the counter substrate 50 arranged to face each other.
  • the liquid crystal cell 60 is provided with alignment films 61 and 62 on the drive substrate 40 A side and the counter substrate 50 side, respectively, and the periphery of the liquid crystal cell 60 is sealed with a sealing material 63.
  • Polarizing plates 42 and 52 are provided on the surfaces of the drive substrate 40A and the counter substrate 50 opposite to the liquid crystal cell 60 (surface S2 side, surface S1 side), respectively.
  • FIG. 3 schematically shows a cross-sectional configuration of the drive substrate 40A in two adjacent pixels P including the pixel transistor 13 on the II line shown in FIG.
  • FIG. 4 schematically shows a cross-sectional configuration of the drive substrate 40A along the line II-II shown in FIG.
  • FIG. 5 schematically shows a cross-sectional configuration of the drive substrate 40A along the line III-III.
  • the drive substrate 40A is provided with, for example, a plurality of scanning lines WSL and a plurality of signal lines DTL that extend in the X-axis direction and the Y-axis direction, respectively, and intersect each other.
  • the drive substrate 40A has an opening region X that reflects or transmits incident light, and a non-opening region Y provided around the opening region X, and the non-opening region Y has a plurality of scans intersecting each other.
  • a line WSL, a plurality of signal lines DTL, and a pixel transistor 13 described later are provided.
  • the drive substrate 40A is provided with, for example, the TFT layer 10 provided with the pixel transistor 13 (TFT element) and the like and various wirings (wiring layers 21, 22, and 23) on the support substrate 41 (surface S1 side).
  • the multilayer wiring layer 20 and the pixel electrode 31 are stacked in this order.
  • a plurality of scanning lines WSL and a pixel transistor 13 are provided on each scanning line WSL via an insulating film 12 on the support substrate 41.
  • a membrane 14 is provided.
  • Each pixel transistor 13 is formed separately for each pixel P by a through hole H (see FIG. 6B).
  • the through hole H is formed, for example, along the formation region of the plurality of scanning lines WSL in plan view, and the bottom surface thereof reaches the support substrate 41.
  • the light shielding film 15 is formed on the side surface (surface S3) of the through hole H including the side surface of the pixel transistor 13 in the stacking direction (Z-axis direction). Irradiation of obliquely incident light onto the pixel transistor 13 is efficiently reduced.
  • a planarization layer 16 is provided between the pixel transistors 13, and the through hole H is buried by the planarization layer 16.
  • the multilayer wiring layer 20 is provided on the TFT layer 10 and includes, for example, wiring layers 21, 22 including wirings forming signal lines DTL and common connection lines COM (not shown) with the interlayer insulating layer 26 interposed therebetween. 23 are provided in this order.
  • the support substrate 41 is, for example, a quartz substrate, and has, for example, a rectangular surface shape (surface shape parallel to the display screen).
  • the scanning line WSL extends, for example, in the X-axis direction, and partly extends in the Y-axis direction. Specifically, the scanning line WSL extends immediately below (opposed region) and around the LDD region (LDD region 13c) of the pixel transistor 13.
  • the scanning line WSL is made of, for example, a metal film such as tungsten (W), titanium (Ti), molybdenum (Mo), chromium (Cr), tantalum (Ta), or an alloy film thereof.
  • the thickness of the scanning line WSL in the Z-axis direction (hereinafter simply referred to as thickness) is, for example, not less than 10 nm and not more than 500 nm.
  • the insulating films 12 and 14 are made of, for example, a silicon oxide (SiO 2 ) film, a silicon nitride (Si 3 N 4 ) film, or a laminated film thereof.
  • the insulating film 12 is provided on the scanning line WSL, and the pixel transistor 13 is provided on the insulating film 12.
  • the insulating film 14 is provided so as to cover the gate insulating film 13B and the gate electrode 13C of the pixel transistor 13.
  • the thickness of the insulating film 12 is, for example, not less than 50 nm and not more than 1 ⁇ m.
  • the thickness of the insulating film 14 is, for example, not less than 100 nm and not more than 1 ⁇ m.
  • the pixel transistor 13 has an LDD (Lightly Doped Drain) structure.
  • the pixel transistor 13 includes a semiconductor layer 13A, a gate electrode 13C that applies an electric field to the semiconductor layer 13A (particularly, the channel region 13a), and a gate insulating film 13B that isolates and isolates the semiconductor layer 13A and the gate electrode 13C from each other. is doing.
  • the semiconductor layer 13A has a channel region 13a at a position facing the gate electrode 13C, and further includes an LDD region 13c provided on both sides of the channel region 13a, and a source / drain region provided further outside the LDD region 13c. 13b.
  • the pixel transistor 13 has a gate electrode 13C electrically connected to the scanning line WSL via the light shielding film 15, one source / drain region 13b electrically connected to the signal line DTL, and the other. Source / drain regions 13b of the pixel electrode 31 are electrically connected.
  • the channel region 13a, the source / drain region 13b, and the LDD region 13c are all formed in the same layer (semiconductor layer 13A), for example, as described above.
  • semiconductor layer 13A semiconductor layer 13A
  • an amorphous silicon film or a polycrystalline silicon film is formed.
  • Etc. When the semiconductor layer 13A is formed of a polycrystalline silicon film, the source / drain region 13b is doped with an impurity such as an n-type impurity to reduce the resistance.
  • the LDD region 13c is doped with impurities so that the impurity concentration is lower than that of the source / drain region 13b.
  • the gate insulating film 13B is for electrically insulating the semiconductor layer 13A and the gate electrode 13C.
  • the gate insulating film 13B is made of, for example, a silicon oxide film or a silicon nitride film, and is formed by, for example, a thermal oxidation method or a CVD (Chemical Vapor Deposition) method.
  • the gate electrode 13C is provided so as to straddle the semiconductor layer 13A in the X-axis direction via the gate insulating film 13B.
  • a region facing the gate electrode 13C is a channel region 13a.
  • the gate electrode 13C is formed of a conductive material. Specifically, for example, it is constituted by an amorphous silicon film, a polycrystalline silicon film, a metal film such as W, Ti, Mo, Cr and Ta, and an alloy film thereof.
  • the gate electrode 13C includes a conductive film 13d formed of a conductive material such as polysilicon or amorphous silicon, and a metal film 13e (or alloy film) selected from the above.
  • a structure in which and are stacked may be employed.
  • the thickness of the gate electrode 13C is preferably 10 nm or more, for example. The upper limit is, for example, 1 ⁇ m or less.
  • the pixel transistor 13 of the present embodiment has been described with an example in which the semiconductor layer 13A extends in the Y-axis direction, but the present invention is not limited thereto, and the pixel transistor 13 can be configured to extend in the X-axis direction.
  • the layout efficiency is better when the semiconductor layer 13A extends in the Y-axis direction.
  • the light shielding film 15 is for reducing the irradiation of the obliquely incident light to the pixel transistor 13, and is formed on the side surface (surface S3) of the through hole H formed in the manufacturing process of the drive substrate 40A. .
  • the through hole H is formed along the formation region of the plurality of scanning lines WSL and the plurality of signal lines DTL in a plan view.
  • the peripheral end of the through hole H is formed so as to overlap the scanning line WSL.
  • the light shielding film 15 is formed so as to include the pixel transistor 13 in a plan view.
  • the light shielding film 15 is provided to extend between the semiconductor layer 13A and the gate electrode 13C and on both sides thereof.
  • the light shielding film 15 is continuously formed from the scanning line WSL to the upper end of the insulating film 14 in the stacking direction (Z-axis direction) of the pixel transistors 13.
  • the light shielding film 15 is made of, for example, a material having light shielding properties and conductivity. Specific examples of the material include W, Mo, Ti, aluminum (Al), and copper (Cu).
  • the gate electrode 13C and the scanning line WSL are electrically connected through the light shielding film 15 as shown in FIG.
  • the thickness of the light shielding film 15 is preferably 5 nm or more and 200 nm or less, for example.
  • FIG. 1 shows an example in which the light shielding film 15 is continuously formed on the peripheral portion of the scanning line WSL in a plan view
  • the light shielding film 15 may be formed at least at the PN junction portion of the pixel transistor 13, specifically, on both sides of the LDD region 13 c, and is desirably formed on the periphery including the pixel transistor 13. Therefore, for example, the light shielding film 15 may not be formed in a region corresponding to the scanning line WSL formed between adjacent pixel transistors 13. In other words, the light shielding film 15 may be formed intermittently along the scanning line WSL provided on the drive substrate 40A in plan view.
  • the planarizing layer 16 is composed of a SiO 2 film, a Si 3 N 4 film, or a laminated film thereof.
  • the flattening layer 16 is to bury the through hole H and flatten the surface of the TFT layer 10. For this reason, in FIG. 3 and the like, an example in which the through hole H is buried and the insulating film 14 is covered is shown, but it is not necessarily formed on the insulating film 14.
  • the thickness of the planarization layer 16 depends on the thickness of each part constituting the scanning line 11, the pixel transistor 13, etc., but is preferably 200 nm or more and 2 ⁇ m or less from the support substrate 41, for example.
  • the wiring layers 21, 22, and 23 constitute, for example, the signal line DTL and the common connection line COM (not shown) provided with the interlayer insulating layer 26 therebetween.
  • the wiring layers 21, 22, and 23 are made of, for example, metal films such as Al, Cu, W, Ti, Mo, Cr, and Ta, and alloy films thereof.
  • the wiring layers 21, 22, and 23 are appropriately electrically connected by, for example, contacts 24 and 25, for example.
  • the thickness of the wiring layers 21, 22, and 23 is preferably 100 nm or more and 1 ⁇ m or less, for example.
  • the signal line DTL extends, for example, in the Y-axis direction, and is provided, for example, immediately above the semiconductor layer 13A (opposing region, for example, the wiring 21A).
  • the signal line DTL is electrically connected to the semiconductor layer 13A through the contact 17 penetrating the planarizing layer 16, the insulating film 14, and the gate insulating film 13B in the source / drain region 13b of the semiconductor layer 13A.
  • the interlayer insulating layer 26 is composed of a SiO 2 film, a Si 3 N 4 film, or a laminated film thereof.
  • the interlayer insulating layer 26 insulates and isolates the wiring layers 21, 22, and 23 and is appropriately flattened.
  • the thickness of the interlayer insulating layer 26 varies depending on the number of wiring layers stacked, the film thickness between the wiring layers (between the wiring layer 21 and the wiring layer 22 and between the wiring layer 22 and the wiring layer 23) is as follows. For example, the thickness is preferably 200 nm or more and 1 ⁇ m.
  • the pixel electrode 31 is provided for each pixel P and is made of, for example, a transparent conductive film.
  • a transparent conductive film examples include oxide semiconductors called indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or IGZO (indium, gallium, zinc-containing oxide).
  • the counter substrate 50 has, for example, a configuration in which a support substrate 51 and a common electrode 53 provided on the surface (surface S2 side) facing the liquid crystal cell 60 of the support substrate 51 are stacked.
  • the support substrate 51 is made of, for example, a quartz substrate.
  • a color filter and a light shielding layer (black matrix layer) (not shown) are provided on the support substrate 51, and these are covered with, for example, an overcoat film (not shown).
  • the common electrode 53 is provided on this overcoat film.
  • the common electrode 53 is, for example, an electrode common to each pixel P, and supplies a voltage to the liquid crystal cell 60 together with the pixel electrode 31. Similar to the pixel electrode 31, the common electrode 53 is made of, for example, the above-described transparent conductive film.
  • the liquid crystal cell 60 has a function of controlling the transmittance of light passing therethrough according to the video voltage supplied through the pixel electrode 31 and the common electrode 53.
  • the liquid crystal cell 60 is a liquid crystal that is driven to display in, for example, a VA (Vertical Alignment) mode, a TN (Twisted Nematic) mode, an ECB (Electrically Controlled Birefringence) mode, an FFS (Fringe Field Switching) mode, or an IPS (In Plane Switching) mode. Is included.
  • VA Vertical Alignment
  • TN Transmission Nematic
  • ECB Electrical Controlled Birefringence
  • FFS Frringe Field Switching
  • IPS In Plane Switching
  • the alignment films 61 and 62 are for controlling the alignment of the liquid crystal cell 60, and are made of an inorganic material film such as a silicon oxide film.
  • the thickness of the alignment films 61 and 62 is, for example, about 50 nm to 360 nm.
  • the alignment films 61 and 62 are formed by vapor deposition, for example.
  • the alignment film 61 is formed so as to cover the pixel electrode 31, and the alignment film 62 is formed so as to cover the common electrode 53.
  • the sealing material 63 is for sealing the liquid crystal cell 60 between the drive substrate 40 ⁇ / b> A and the counter substrate 50.
  • the sealing material 63 is made of, for example, an insulating material such as a polymer material. Specifically, an epoxy resin or an acrylic resin can be used.
  • the polarizing plates 42 and 52 are, for example, arranged in crossed Nicols, and allow only light (polarized light) in a certain vibration direction to pass therethrough.
  • the drive substrate 40A constituting the liquid crystal panel 1 of the present embodiment can be manufactured as follows, for example.
  • FIG. 6A to 6E show the manufacturing method of the drive substrate 40A in the order of steps.
  • the scanning line 11 is formed through a patterning process.
  • the insulating film 12 is formed on the support substrate 41 and the scanning lines 11 by using, for example, a CVD method to form a silicon oxide film, for example.
  • the surface of the insulating film 12 is planarized using a CMP method or the like as necessary.
  • a polysilicon film is formed on the insulating film 12 by using, for example, a CVD method, and then a crystallization process is performed as necessary. Thereafter, a semiconductor layer 13A is formed through a patterning process. Subsequently, for example, a silicon oxide film is formed on the insulating film 12 and the semiconductor layer 13A by using a thermal oxidation method or a CVD method to form a gate insulating film 13B. Next, impurities are implanted into the semiconductor layer 13A as necessary to form a channel region 13a. Note that the impurity implantation may be performed before the gate insulating film 13B is formed.
  • a polysilicon film and a W film are formed on the gate insulating film 13B by using, for example, a CVD method, and then a gate electrode 13C made of a laminated film of the conductive film 13d and the metal film 13e is formed through a patterning process. Form. Thereafter, if necessary, thermal annealing for impurity implantation and impurity activation is performed on the semiconductor layer 13A to form the LDD region 13c and the source / drain region 13b. Next, an insulating film 14 is formed on the gate insulating film 13B and the gate electrode 13C by using, for example, a CVD method to form, for example, a silicon oxide film. At this time, the surface of the insulating film 14 is planarized using a CMP method or the like as necessary.
  • a resist film 81 is formed on the insulating film 14 so as to cover the non-opening region Y, and this resist film 81 is used as a mask by, for example, RIE (Reactive Ion Etching) or wet etching.
  • a through hole H is formed.
  • the end of the through hole H in the vicinity of the gate electrode 13C provided at the intersection of the plurality of scanning lines WSL (scanning line 11) and the plurality of signal lines DTL is as shown in FIG.
  • the distance between the end of the through hole H (through hole end) and the end of the gate electrode 13C is preferably about ⁇ 0.2 ⁇ m or more.
  • the case where the gate electrode 13C and the through-hole H overlap is defined as plus (+).
  • the scanning line 11 and the gate electrode 13C are connected via the light shielding film 15 at any one of the four corners of the rectangular gate electrode 13C. It can be electrically connected.
  • the W film 15a for example, the upper surface of the non-opening region Y, the through hole is formed as the light shielding film 15 by using, for example, CVD, sputtering, or ALD (Atomic Layer Deposition) method. It forms continuously on the side and bottom of H.
  • CVD chemical vapor deposition
  • sputtering sputtering
  • ALD atomic layer Deposition
  • the W film 15a is processed using, for example, RIE. Specifically, the W film 15a other than the side surface of the through hole H is selectively removed. Thereby, the light shielding film 15 is formed only on the side surface (surface S3) of the through hole H. 6D and the like show an example in which the thickness of the light shielding film 15 in the X-axis direction is constant from the lower end to the upper end, but the present invention is not limited to this. For example, when the W film is processed by RIE as described above, the thickness of the light shielding film 15 at the upper end portion gradually decreases toward the upper end by a manufacturing process such as RIE.
  • the through hole H is embedded using, for example, the CVD method, and a silicon oxide film covering the insulating film 14 is formed to form the planarizing layer 16.
  • the surface of the planarization layer 16 is planarized using a CMP method or the like as necessary.
  • a contact 17 is formed that penetrates the planarizing layer 16, the insulating film 14, and the gate insulating film 13B and is in contact with the semiconductor layer 13A.
  • an Al film is formed by using, for example, a CVD method
  • a wiring layer 21 including the wirings 21A and 21B is formed through a patterning process.
  • a silicon oxide film is formed on the planarizing layer 16 and the wiring layer 21 by using, for example, a CVD method.
  • the wiring layers 22 and 23, the silicon oxide film and the wiring layer 21 (wiring 21A) and the wiring layer 22, the wiring layer 22 and the wiring layer 23, and the wiring layer 23 and the pixel electrode 31 are electrically connected using the same method.
  • the contacts 24 and 25 connected to are formed.
  • a contact for electrically connecting the wiring layer 22 and the wiring layer 23 is not shown.
  • the multilayer wiring layer 20 is formed.
  • the pixel substrate 31 is formed on the interlayer insulating layer 26, thereby completing the drive substrate 40A shown in FIG.
  • FIG. 8 illustrates an example of the overall configuration of the projector 100 including the liquid crystal panel 1 of the present disclosure.
  • the projector 100 is, for example, a three-plate transmission projector, and includes, for example, a light emitting unit 110, an optical path branching unit 120, a spatial light modulation unit 130, a combining unit 140, and a projecting unit 150.
  • the light emitting unit 110 supplies a light beam that irradiates the irradiated surface of the spatial light modulation unit 130, and includes, for example, a white light source lamp and a reflecting mirror formed behind the lamp. Yes.
  • the light emitting unit 110 may have some optical element in a region (on the optical axis AX) through which the light 111 of the lamp passes as necessary.
  • a filter that attenuates light other than visible light among the light 111 from the lamp, and an optical integrator that makes the illuminance distribution on the irradiated surface of the spatial light modulator 130 uniform. It is possible to provide them in this order from the lamp side.
  • the optical path branching unit 120 separates the light 111 output from the light emitting unit 110 into a plurality of color lights having different wavelength bands, and guides each color light to the irradiated surface of the spatial light modulation unit 130.
  • the optical path branching unit 120 includes one cross mirror 121, two mirrors 122, and two mirrors 123.
  • the cross mirror 121 separates the light 111 output from the light emitting unit 110 into a plurality of color lights having different wavelength bands and branches the optical path of each color light.
  • the cross mirror 121 is disposed on the optical axis AX, and is configured by connecting two mirrors having different wavelength selectivity so as to cross each other.
  • the mirrors 122 and 123 reflect the color light (red light 111R and blue light 111B in FIG. 8) branched in the optical path by the cross mirror 121, and are disposed at a location different from the optical axis AX.
  • the mirror 122 guides light (red light 111R in FIG. 8) reflected in one direction intersecting the optical axis AX by one mirror included in the cross mirror 121 to the irradiated surface of the spatial light modulator 130R. Has been placed.
  • the mirror 123 guides light (blue light 111B in FIG. 8) reflected in another direction intersecting the optical axis AX by other mirrors included in the cross mirror 121 to the irradiated surface of the spatial light modulator 130B. Has been placed.
  • the light that passes through the cross mirror 121 and passes on the optical axis AX (green light 111G in FIG. 8) is transmitted from the spatial light modulation unit 130G disposed on the optical axis AX. It is incident on the surface to be irradiated.
  • the spatial light modulator 130 is configured using, for example, the liquid crystal panel 1 shown in FIG. 2 and the like, and modulates a plurality of color lights for each color light in accordance with a video signal Din input from an information processing device (not shown). Thus, modulated light is generated for each color light.
  • the spatial light modulator 130 includes, for example, a spatial light modulator 130R that modulates the red light 111R, a spatial light modulator 130G that modulates the green light 111G, and a spatial light modulator 130B that modulates the blue light 111B. .
  • the spatial light modulator 130R is disposed in a region facing one surface of the combining unit 140.
  • the spatial light modulation unit 130R modulates the incident red light 111R based on the video signal Din to generate red image light 112R, and the red image light 112R is output from the synthesis unit 140 behind the spatial light modulation unit 130R. It is designed to output on one side.
  • Spatial light modulation unit 130 ⁇ / b> G is arranged in a region facing the other surface of combining unit 140.
  • the spatial light modulator 130G modulates the incident green light 111G based on the video signal Din to generate a green image light 112G.
  • the green image light 112G is output from the combining unit 140 behind the spatial light modulator 130R. Output to other side.
  • Spatial light modulation unit 130 ⁇ / b> B is arranged in a region facing the other surface of combining unit 140.
  • the spatial light modulator 130B modulates the incident blue light 111B based on the video signal Din to generate blue image light 112B, and the blue image light 112B is output from the combining unit 140 behind the spatial light modulator 130R. Output to other aspects.
  • the combining unit 140 generates image light by combining a plurality of modulated lights.
  • the combining unit 140 is disposed on the optical axis AX, for example, and is, for example, a cross prism configured by joining four prisms. Two selective reflection surfaces having different wavelength selectivity are formed on the joint surfaces of these prisms by, for example, a multilayer interference film or the like.
  • the one selective reflection surface reflects the red image light 112 ⁇ / b> R output from the spatial light modulation unit 130 ⁇ / b> R in a direction parallel to the optical axis AX and guides it in the direction of the projection unit 150.
  • the other selective reflection surface for example, reflects the blue image light 112B output from the spatial light modulation unit 130B in a direction parallel to the optical axis AX and guides it in the direction of the projection unit 150.
  • the green image light 112G output from the spatial light modulation unit 130G passes through the two selective reflection surfaces and proceeds in the direction of the projection unit 150.
  • the combining unit 140 functions to generate image light 113 by combining the image light generated by the spatial light modulation units 130R, 130G, and 130B, and to output the generated image light 113 to the projection unit 150.
  • the projection unit 150 projects the image light 113 output from the synthesis unit 140 onto the screen 200 and displays an image.
  • the projection unit 150 is disposed on the optical axis AX, for example, and is configured by a projection lens, for example.
  • FIG. 9 illustrates an example of the overall configuration of the spatial light modulators 130R, 130G, and 130B.
  • the spatial light modulators 130R, 130G, and 130B include, for example, the above-described liquid crystal panel 1 and a drive circuit 70 that drives the liquid crystal panel 1.
  • the drive circuit 70 includes a display control unit 71, a data driver 72, and a gate driver 73.
  • the liquid crystal panel 1 has a pixel area 1A in which a plurality of pixels P are formed in a matrix and a peripheral area 1B.
  • the liquid crystal panel 1 displays an image based on the video signal Din input from the outside by actively driving each pixel P by the data driver 72 and the gate driver 73.
  • the liquid crystal panel 1 includes a plurality of scanning lines WSL extending in the row direction, a plurality of signal lines DTL extending in the column direction, and a plurality of common connection lines COM extending in the row direction or the column direction. ing. Pixels P are provided corresponding to the intersections between the signal lines DTL and the scanning lines WSL. Each signal line DTL is connected to an output end (not shown) of the data driver 72. Each scanning line WSL is connected to an output terminal (not shown) of the gate driver 73. Each common connection line COM is connected to, for example, an output terminal (not shown) of a circuit that outputs a fixed potential.
  • the display control unit 71 stores and holds the supplied video signal Din in a frame memory for each screen (for each display of one frame), for example.
  • the display control unit 71 has a function of controlling the data driver 72 and the gate driver 73 that drive the liquid crystal panel 1 to operate in conjunction with each other. Specifically, for example, the display control unit 71 supplies a scanning timing control signal to the data driver 72, and the image signal for one horizontal line based on the image signal held in the frame memory is supplied to the data driver 72. A display timing control signal is supplied.
  • the data driver 72 supplies, for example, a video signal Din for one horizontal line supplied from the display control unit 71 to each pixel P as a signal voltage. Specifically, the data driver 72 supplies, for example, a signal voltage corresponding to the video signal Din to each pixel P constituting one horizontal line selected by the gate driver 73 via the signal line DTL. It is.
  • the gate driver 73 has a function of selecting the pixel P to be driven in accordance with, for example, a scanning timing control signal supplied from the display control unit 71. Specifically, the gate driver 73 applies, for example, a selection pulse to the gate electrode 13C of the pixel transistor 13 of the pixel P via the scanning line WSL, thereby forming pixels formed in a matrix in the pixel region 1A. One row of P is selected as a driving target. In these pixels P, one horizontal line is displayed according to the signal voltage supplied from the data driver 72. In this way, the gate driver 73 sequentially scans, for example, one horizontal line at a time division, and performs display over the entire display area.
  • FIG. 10 illustrates an example of a circuit configuration of the pixel P.
  • the pixel P includes a liquid crystal element 2 and a pixel circuit 3 that drives the liquid crystal element 2.
  • the liquid crystal element 2 and the pixel circuit 3 are provided corresponding to the intersection of the scanning line WSL and the signal line DTL.
  • the liquid crystal element 2 includes a liquid crystal cell 60, a pixel electrode 31 and a common electrode 53 that sandwich the liquid crystal cell 60.
  • the pixel circuit 3 includes a transistor (pixel transistor 13) that writes a signal voltage to the liquid crystal element 2 and a storage capacitor 27 that holds the voltage written to the liquid crystal element 2.
  • the storage capacitor 27 is composed of a pair of capacitor electrodes facing each other with a predetermined gap. One capacitor electrode is connected to the source / drain region 13b of the semiconductor layer 13A, and the other capacitor electrode is connected in common. Connected to line COM.
  • the liquid crystal panel is highly demanded to increase the luminance, and in order to realize the higher luminance, it is necessary to improve the aperture ratio of the pixel.
  • improving the aperture ratio reduces the light shielding area of the TFT.
  • a liquid crystal panel is used as a light modulation device (light valve) of a projection display device, leakage due to strong light from the light source. An electric current is generated, which causes deterioration of image quality such as flicker.
  • the aperture ratio and the light shielding property are basically in a trade-off relationship, and development of a liquid crystal panel capable of supporting the light shielding property while improving the aperture ratio is underway.
  • an electro-optical device has been developed in which a gate electrode provided on a semiconductor layer is embedded on both sides of the semiconductor layer so as to serve as a contact with a scanning line, thereby preventing light from entering the semiconductor layer.
  • the contact by the gate electrode is formed in the non-opening region, it is difficult to improve the aperture ratio.
  • the buried gate electrode is formed on a part of each side of the semiconductor layer, the light shielding property of the portion where the gate electrode is not buried remains low.
  • an intermediate light-shielding layer is further provided between the light-shielding layer provided in the non-opening region and the TFT, and this intermediate light-shielding layer extends to the groove provided in the peripheral edge of the semiconductor layer, thereby shielding light.
  • a display device with improved performance has been developed.
  • this display device is disadvantageous for improving the aperture ratio because the groove for extending the intermediate light shielding layer is provided in the non-opening region.
  • an electro-optical device has been developed in which an optical surface is provided between the opening region and the non-opening region, thereby reflecting obliquely incident light to the opening region side to improve the light shielding performance and the light utilization efficiency. ing.
  • the optical surface is formed of a light-transmitting film such as SiN, it is difficult to obtain a great effect on the light shielding property.
  • the liquid crystal panel 1 of the present embodiment in a plan view, along the plurality of scanning lines WSL (scanning lines 11) including the semiconductor layer 13A and the gate electrode 13C constituting the pixel transistor 13 above,
  • the light shielding film 15 extending in the stacking direction (Z-axis direction) is formed so as to cover the side surface of the pixel transistor 13.
  • the light shielding film 15 is formed around the pixel transistor 13, and the entry path of light incident from an oblique direction into the pixel transistor 13 (particularly, the LDD region 13c of the semiconductor layer 13A) is significantly reduced. It becomes possible. That is, the light shielding property of the pixel transistor 13 can be improved.
  • the light shielding film 15 is formed using a conductive material, the scanning line 11 and the gate electrode 13C are electrically connected without separately providing a contact between the scanning line 11 and the gate electrode 13C. Can be connected to. Therefore, the aperture ratio can be improved.
  • the light shielding film 15 is formed along the plurality of scanning lines WSL in plan view, the light shielding film 15 is formed around the pixel transistor 13. Therefore, the light shielding property of the pixel transistor 13 is improved, and the image quality can be improved. Further, since the light shielding film 15 is formed using a conductive material, the scanning line 11 and the gate electrode 13C are electrically connected without separately providing a contact between the scanning line 11 and the gate electrode 13C. It will be possible to connect to. Therefore, the aperture ratio can be improved and high luminance can be realized. That is, it is possible to achieve both higher luminance and improved image quality.
  • FIG. 11 illustrates a cross-sectional configuration of the drive substrate 40B configuring the liquid crystal panel 1 according to the second embodiment of the present disclosure.
  • the light shielding film 15 is provided along the plurality of scanning lines WSL provided on the driving substrate 40A (light shielding film 15A) in plan view, and above the pixel transistor 13 (light shielding film 15B).
  • the drive substrate 40B shown in FIG. 11 schematically shows a cross-sectional configuration of two adjacent pixels P including the pixel transistor 13 on the II line shown in FIG.
  • FIG. 12 shows one process when manufacturing the drive substrate 40B shown in FIG.
  • the light shielding film 15 (light shielding) is formed on the side surface of the insulating film 14 (upper surface of the non-opening region Y) and the through hole H provided on the pixel transistor 13 by using the same method as that of the driving substrate 40A in the first embodiment.
  • a W film 15a to be the films 15A and 15B) is formed.
  • a resist film 82 having a desired pattern is formed to cover the side surface and the upper surface of the W film 15a.
  • the resist film 82 has an opening 82H at a position where the contact 17 that electrically connects the wiring layer 21 and the semiconductor layer 13A is formed.
  • the W film 15a is processed using, for example, RIE, and then the drive substrate 40B is manufactured using the same method as in the first embodiment. Thereby, the drive substrate 40B in which the light shielding film 15 covering the upper side of the pixel transistor 13 is formed together with the side surface of the through hole H.
  • the light shielding film 15 that covers the upper side is formed together with the side surface of the pixel transistor 13, so that stray light propagating in the drive substrate 40B is prevented from entering the pixel transistor 13. Is possible. Therefore, it is possible to further improve the light shielding property with respect to the pixel transistor 13.
  • the present invention is not limited to this.
  • the end surface (side surface) of the scanning line 11 may be covered from the upper surface of the support substrate 41.
  • FIG. 13 illustrates a cross-sectional configuration of a drive substrate 40C configuring the liquid crystal panel 1 according to the third embodiment of the present disclosure.
  • the scanning line 11, the insulating film 12, and the insulating film 14 have the same end surface, and the light shielding film 15 is formed on the end surface from the upper surface of the support substrate 41 to the upper end of the insulating film 14. It has the structure made.
  • the drive substrate 40C shown in FIG. 13 schematically shows a cross-sectional configuration of two adjacent pixels P including the pixel transistor 13 on the II line shown in FIG.
  • FIG. 14A and FIG. 14B show a part of the process when manufacturing the drive substrate 40C shown in FIG.
  • a W film 11a to be the scanning line 11 is formed on the support substrate 41 by using, for example, a CVD method or a sputtering method. Thereafter, a patterning step may be performed, but the W film 11a is not separated in the non-opening region.
  • the semiconductor layer 13A is formed as in the first embodiment, and then the gate insulating film 13B is formed.
  • a silicon oxide film 14a to be the silicon film 13x, the gate electrode 13C, and the insulating film 14 is sequentially formed.
  • a resist film 83 is formed on the insulating film 14 in a corresponding region so as to cover the non-opening region Y, and supported by, for example, RIE or wet etching using the resist film 81 as a mask.
  • a through hole H reaching the substrate 41 is formed.
  • the W film 11a to be the scanning line 11 in the non-opening region Y is also separated.
  • the drive substrate 40C is manufactured by using the same method as in the first embodiment. Thereby, the drive substrate 40C in which the scanning line 11, the insulating film 12, and the insulating film 14 have the same end surface is completed.
  • the scanning hole 11, the insulating film 12, and the insulating film 14 are collectively etched in the through-hole H to form the light shielding film 15 having conductivity on the side surface. .
  • the side surfaces of the scanning line 11, the insulating film 12, and the insulating film 14 of the light shielding film 15 form the same surface (surface S3). That is, the light shielding film 15 can electrically connect the scanning line 11 and the gate electrode 13C without alignment. Therefore, it is not necessary to consider misalignment between the through hole H and the scanning line 11, and the aperture ratio can be further improved.
  • FIG. 15 schematically illustrates a planar configuration of the drive substrate 40 ⁇ / b> D constituting the liquid crystal panel 1 according to the modified example of the present disclosure.
  • FIG. 16 shows a cross-sectional configuration taken along line IV-IV shown in FIG.
  • the gate electrode 13C is continuously formed between the adjacent pixels P extending in the X-axis direction.
  • the scanning line 11 is formed above the scanning line 11 so as to extend in the X-axis direction so as to face the scanning line 11 and through the through-hole 13H formed between the adjacent pixels P. Is different from the first embodiment in that it is electrically connected to the first embodiment.
  • the through hole 13H is formed by forming the scanning line 11, the insulating film 12, the semiconductor layer 13A, and the gate insulating film 13B on the support substrate 41, and then forming a resist on the gate insulating film 13B.
  • the film is patterned and formed by RIE or the like using this resist film as a mask.
  • a polysilicon film is formed on the gate insulating film 13B while burying the through hole 13H using the CVD method, for example, as in the first embodiment.
  • a gate electrode 13C is formed through a patterning process.
  • the drive substrate 40D is completed through steps similar to those of the first embodiment.
  • the connection between the scanning line 11 and the gate electrode 13C is performed at a position away from the semiconductor layer 13A without the light shielding film 15, so that the first implementation described above.
  • the scanning line 11 and the gate electrode 13C can be easily connected.
  • the degree of freedom in layout is improved and the aperture ratio can be further improved.
  • the potential of the gate electrode 13C since the potential of the gate electrode 13C is directly supplied from the scanning line 11, the potential of the light shielding film 15 may be arbitrary, for example, it may be electrically floating. Therefore, in plan view, the distance between the end of the through hole H that forms the light shielding film 15 on the side surface and the end of the gate electrode 13C (the amount of overlap with the through hole H) may be less than ⁇ 0.2 ⁇ m.
  • FIG. 17 schematically illustrates a planar configuration of the drive substrate 40 ⁇ / b> E that configures the liquid crystal panel 1 according to the modified example of the present disclosure.
  • FIG. 18 shows a cross-sectional configuration taken along the line VV shown in FIG. In this modification, the gate electrode 13C is electrically connected to the wiring layer 21 via the contact 18 in the peripheral region 1B, and a potential is supplied from the wiring layer 21.
  • the light shielding film 15 is at the same potential as the scanning line 11.
  • the distance between the end of the through hole H that forms the light shielding film 15 on the side surface and the end of the gate electrode 13C is less than ⁇ 0.2 ⁇ m. Yes.
  • the gate electrode 13C and the wiring layer 21 are connected via the contact 18, and the potential is supplied from the wiring layer 21 to the gate electrode 13C.
  • the connection process between the scanning line 11 and the gate electrode 13C can be reduced.
  • the scanning line WSL (scanning line 11) is a back light shielding film of the pixel transistor 13. Therefore, by setting the potential of the scanning line 11 to an optimal value for the holding characteristics of the pixel transistor 13, it is possible to reduce the leakage current of the pixel transistor 13 due to the electric field and further improve the image quality.
  • the scanning line 11 and the light shielding film 15 in this modification may have a floating potential, but by fixing to a certain potential, it is possible to reduce the influence of capacitive coupling. As a result, the image quality can be further improved.
  • FIG. 19 schematically shows a planar configuration of the drive substrate 40F constituting the liquid crystal panel 1 according to the fourth embodiment of the present disclosure
  • FIG. 20 shows a VI-VI line shown in FIG. 2 schematically shows a cross-sectional configuration of two adjacent pixels P including the pixel transistor 13 in FIG.
  • the light shielding film 15 is continuously provided from the upper surface of the support substrate 41 to the upper end of the wiring layer 21 (specifically, the wiring 21A), and the semiconductor layer 13A and the wiring 21A are provided.
  • the structure is electrically connected through the light shielding film 15. Further, the scanning line WSL is separated for each pixel P in the X-axis direction.
  • 21A to 21C show a part of the process for manufacturing the drive substrate 40F shown in FIG.
  • the insulating film 14 is formed using the same method as that for the drive substrate 40A in the first embodiment.
  • the semiconductor layer 13A is patterned so that one end face in the Y-axis direction is outside the end face of the scanning line 11.
  • a contact 17 penetrating the insulating film 14 and the gate insulating film 13B is formed.
  • an Al film is formed by using, for example, a CVD method, and then a wiring layer 21 (wirings 21A and 21B) is formed through a patterning process.
  • the end surface on the opening region X side of the wiring 21A is formed so as to be outside the end surface of the scanning line 11 provided below and to be the same as or inside the end surface of the semiconductor layer 13A.
  • a resist film 84 is formed on the insulating film 14 and the wiring layer 21.
  • the end face on the opening region X side of the wiring 21A is exposed.
  • the through hole H is formed by, for example, RIE or wet etching using the resist film 84 and the wiring 21A as a mask.
  • the end surface of the semiconductor layer 13A is exposed and a side surface (surface S3a) having the same surface as the end surface of the wiring layer 21 (wiring 21A) is formed.
  • the end surface of the semiconductor layer 13A is covered with the gate insulating film 13B.
  • the W film 15a is the light shielding film 15, the upper surface of the non-opening region Y, and the side surface of the through hole H. And continuously formed on the bottom surface.
  • the light-shielding film 15 is formed by removing the W film 15a other than the end face of the wiring layer 21 and the side face of the through hole H using, for example, RIE.
  • the semiconductor layer 13A and the wiring 21A are electrically connected via the light shielding film 15.
  • the wiring 21A is the signal line DTL, whereby the potential of the signal line DTL is supplied to the semiconductor layer 13A.
  • the through-hole H is buried by using, for example, a CVD method, and a silicon oxide film covering the insulating film 14 and the wiring layer 21 is formed to form the planarizing layer 16.
  • the surface of the planarization layer 16 is planarized using a CMP method or the like as necessary.
  • the wiring layers 22 and 23, the silicon oxide film, the wiring layer 21 and the wiring layer 22, the wiring layer 22 and the wiring layer 23, and the wiring layer 23 and the pixel electrode 31 are electrically connected.
  • the contacts 24 and 25 connected to the pixel electrode 31 and the pixel electrode 31 are formed.
  • the drive substrate 40F shown in FIG. 19 is completed.
  • a contact for electrically connecting the wiring layer 22 and the wiring layer 23 is not shown.
  • FIG. 19 shows an example in which the light shielding film 15 extending in the Y-axis direction is separated between adjacent pixels P, it may be continuous. This is because in the present embodiment, the scanning line 11 and the gate electrode 13C are arranged so as not to be electrically connected.
  • the wiring layer 21 (specifically, the wiring 21A) is used as a mask and the side surface (surface) including the end face of the wiring 21A and the end face of the semiconductor layer 13A.
  • a through hole H having S3a) is formed, and the light shielding film 15 is formed on the side surfaces (surface S3a and surface S3b) of the through hole H.
  • the semiconductor layer 13A and the wiring 21A as the signal line DTL are electrically connected via the light shielding film 15, and as shown in FIG. 3 in the first embodiment, the semiconductor layer 13A and the wiring layer are connected. Therefore, it is not necessary to form the contact 17 for connecting to the contact 21, and the non-opening region can be reduced by the area of the contact 17. That is, the aperture ratio can be further improved.
  • the light shielding film 15 is formed on the side surface of the through hole H including the end surface of the wiring layer 21. These are formed higher in the Z-axis direction than the light shielding film 15 in the first embodiment. Therefore, the light shielding property for the pixel transistor 13 is further improved, and the image quality can be further improved.
  • FIG. 22 illustrates a cross-sectional configuration of the drive substrate 40 ⁇ / b> G that configures the liquid crystal panel 1 according to the modified example of the present disclosure.
  • the drive substrate 40G of this modification is obtained by forming the light shielding film 15 after forming the wiring layer 23.
  • the through hole H is provided so that the end surface of the semiconductor layer 13A and the end surface of the wiring layer 23 form the same surface (surface S3d). Therefore, the light shielding film 15 is continuously formed from the upper surface of the support substrate 41 to the upper end of the wiring layer 23, and electrically connects the semiconductor layer 13A and the wiring layer 23.
  • the other end surface of the semiconductor layer 13A is covered with the gate insulating film 13B (surface S3c).
  • the wiring layer 23 is electrically connected to the pixel electrode 31 through the contact 25.
  • the scanning line WSL is separated for each pixel P in both the X-axis direction and the Y-axis direction, and the light shielding film 15 formed along the scanning line WSL is separated for each pixel P. Is formed.
  • the drive substrate 40F shown in FIG. 22 schematically represents a cross-sectional configuration of two adjacent pixels P including the pixel transistor 13 on the VI-VI line shown in FIG.
  • the drive substrate 40G of this modification can be manufactured using the same method as in the fourth embodiment except that the through hole H and the light shielding film 15 are provided after the wiring layer 23 is formed.
  • the through hole H having the side including the end surface of the wiring layer 23 and the end surface of the semiconductor layer 13A (surface S3d) is formed.
  • the light shielding film 15 is formed on the side surfaces (surface S3c and surface S3d).
  • the semiconductor layer 13 ⁇ / b> A and the wiring layer 23 are electrically connected via the light shielding film 15.
  • the semiconductor layer 13A is electrically connected to the pixel electrode 31 through the light shielding film 15, the wiring layer 23, and the contact 25. This eliminates the need to form the contact 17 for connecting the semiconductor layer 13A and the wiring layer 21 as in the fourth embodiment, and reduces the non-opening area by the area of the contact 17. Is possible.
  • the light shielding film 15 is formed on the side surface of the through hole H including the end surface of the wiring layer 23. Therefore, the light shielding film 15 in the fourth embodiment. Thus, the light shielding film 15 that is higher in the Z-axis direction is formed. Therefore, it is possible to further improve the light shielding property with respect to the pixel transistor 13. Furthermore, in this modification, since the light shielding film 15 is formed immediately below the pixel electrode 31, the effect as a waveguide can be obtained by forming the light shielding film 15 using a material having high light reflectance. Light utilization efficiency can be improved.
  • FIG. 23 schematically illustrates a planar configuration of the drive substrate 40H that configures the liquid crystal panel 1 according to the modification of the present disclosure.
  • FIG. 24 schematically shows a cross-sectional configuration of two adjacent pixels P including the pixel transistor 13 in the VII-VII line shown in FIG.
  • the top gate type transistor is shown as an example as the pixel transistor 13 provided for each pixel P.
  • the present invention is not limited to this, and as shown in FIG. Alternatively, a bottom gate type transistor may be used.
  • the driving substrate 40H of the present modification includes a TFT layer 90 having a bottom gate type pixel transistor 93 on a support substrate 41, a multilayer wiring layer 20 having a configuration similar to that of the first embodiment, a pixel The electrode 31 is stacked in this order.
  • the pixel transistor 93 has a configuration in which a gate electrode 93C also serving as the scanning line WSL, a gate insulating film 93B, and a semiconductor layer 93A are stacked in this order from the support substrate 41 side. An insulating film 92 and an insulating film 94 are stacked in this order on the semiconductor layer 93A.
  • the pixels P are separated by a through hole H, and a light shielding film 95 is formed along the end surfaces of the gate insulating film 93B and the insulating films 92 and 94 having the same surface.
  • the through hole H is buried by the planarizing layer 96, and the planarizing layer 96 is also formed on the insulating film 94, for example, and planarizes the surface of the TFT layer 90.
  • the TFT layer 90 and the multilayer wiring layer 20 penetrate the planarizing layer 96, the insulating film 94, and the insulating film 92, and are electrically connected by a contact 97 that connects the semiconductor layer 93A and the wiring layer 21.
  • the present disclosure is not limited to these embodiments and the like, and various modifications can be made.
  • the structure of the liquid crystal panel 1 of the present disclosure can be applied not only to a projection display device but also to all semiconductor devices that require light shielding.
  • an example using a liquid crystal element as a display element has been described.
  • the present invention is not limited to this.
  • an organic EL (Electro Luminescence) element or a CLED (Crystal Light Emitting Diode) may be used. Absent.
  • the display device and the projection display device of the present disclosure may have the following configurations.
  • the first substrate is A support substrate;
  • TFT elements respectively provided at intersections of the plurality of scanning lines and the plurality of signal lines;
  • a light-shielding film provided along the plurality of scanning lines in a plan view.
  • the TFT element includes a gate electrode provided at each of intersections of the plurality of scanning lines and the plurality of signal lines, and a semiconductor layer provided on each of the plurality of scanning lines,
  • the display device according to (1) or (2), wherein the light shielding film is continuously provided along the plurality of scanning lines in a plan view.
  • the TFT element is surrounded by the light shielding film in a plan view.
  • the gate electrode that also serves as the scanning line and the semiconductor layer are stacked in this order via an insulating film from the support substrate side,
  • the first substrate includes a plurality of pixels, an opening region provided for each of the plurality of pixels, and a non-opening region provided around the opening region,
  • a light modulation device for modulating light from the light source comprises: A first substrate and a second substrate disposed opposite to each other with a liquid crystal layer therebetween,
  • the first substrate is A support substrate;
  • a light-shielding film provided along the plurality of scanning lines in a plan view.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Liquid Crystal (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
PCT/JP2017/046963 2017-02-01 2017-12-27 表示装置および投射型表示装置 WO2018142822A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2018565994A JP7028192B2 (ja) 2017-02-01 2017-12-27 表示装置および投射型表示装置
CN201780084744.8A CN110226121B (zh) 2017-02-01 2017-12-27 显示装置和投影显示设备

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017-016621 2017-02-01
JP2017016621 2017-02-01

Publications (1)

Publication Number Publication Date
WO2018142822A1 true WO2018142822A1 (ja) 2018-08-09

Family

ID=63040194

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2017/046963 WO2018142822A1 (ja) 2017-02-01 2017-12-27 表示装置および投射型表示装置

Country Status (3)

Country Link
JP (1) JP7028192B2 (zh)
CN (1) CN110226121B (zh)
WO (1) WO2018142822A1 (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112289831A (zh) * 2019-07-24 2021-01-29 天马日本株式会社 显示装置
JP2021119373A (ja) * 2020-01-30 2021-08-12 セイコーエプソン株式会社 電気光学装置、および電子機器
JP7435087B2 (ja) 2020-03-17 2024-02-21 セイコーエプソン株式会社 電気光学装置、及び電子機器

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002196362A (ja) * 2000-12-25 2002-07-12 Sharp Corp 液晶表示装置およびその製造方法
JP3197990U (ja) * 2015-03-31 2015-06-11 セイコーエプソン株式会社 電気光学装置、及び電子機器
CN104950541A (zh) * 2015-07-20 2015-09-30 深圳市华星光电技术有限公司 Boa型液晶显示面板及其制作方法
JP2016009719A (ja) * 2014-06-23 2016-01-18 株式会社ジャパンディスプレイ 薄膜半導体装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1267781C (zh) * 1998-03-19 2006-08-02 精工爱普生株式会社 采用开关元件的衬底、液晶和投影型显示装置及电子仪器
JP4285158B2 (ja) * 2003-08-29 2009-06-24 セイコーエプソン株式会社 電気光学装置及び電子機器
JP2011071476A (ja) * 2009-08-25 2011-04-07 Canon Inc 薄膜トランジスタ、薄膜トランジスタを用いた表示装置及び薄膜トランジスタの製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002196362A (ja) * 2000-12-25 2002-07-12 Sharp Corp 液晶表示装置およびその製造方法
JP2016009719A (ja) * 2014-06-23 2016-01-18 株式会社ジャパンディスプレイ 薄膜半導体装置
JP3197990U (ja) * 2015-03-31 2015-06-11 セイコーエプソン株式会社 電気光学装置、及び電子機器
CN104950541A (zh) * 2015-07-20 2015-09-30 深圳市华星光电技术有限公司 Boa型液晶显示面板及其制作方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112289831A (zh) * 2019-07-24 2021-01-29 天马日本株式会社 显示装置
JP2021119373A (ja) * 2020-01-30 2021-08-12 セイコーエプソン株式会社 電気光学装置、および電子機器
JP7327184B2 (ja) 2020-01-30 2023-08-16 セイコーエプソン株式会社 電気光学装置、および電子機器
JP7435087B2 (ja) 2020-03-17 2024-02-21 セイコーエプソン株式会社 電気光学装置、及び電子機器

Also Published As

Publication number Publication date
JP7028192B2 (ja) 2022-03-02
CN110226121B (zh) 2022-09-30
JPWO2018142822A1 (ja) 2019-11-21
CN110226121A (zh) 2019-09-10

Similar Documents

Publication Publication Date Title
US8823071B2 (en) Electro-optical device and electronic apparatus
JP3197989U (ja) 電気光学装置、及び電子機器
JP3197990U (ja) 電気光学装置、及び電子機器
JP6044358B2 (ja) 電気光学装置用基板、電気光学装置、および電子機器
WO2011142265A1 (ja) 半導体装置、アクティブマトリクス基板、及び表示装置
JP2018040969A (ja) 電気光学装置、電子機器
JP5919636B2 (ja) 電気光学装置、電子機器、電気光学装置の製造方法
WO2018142822A1 (ja) 表示装置および投射型表示装置
US11081588B2 (en) Electro-optical device and electronic apparatus
JP6977561B2 (ja) 半導体装置および投射型表示装置
JP2018136477A (ja) 電気光学装置、電子機器
JP4475238B2 (ja) 電気光学装置及びその製造方法、並びに電子機器
TW201634995A (zh) 光電裝置及電子機器
JP2010096966A (ja) 電気光学装置及びその製造方法、並びに電子機器
JP5919890B2 (ja) 電気光学装置、及び電子機器
JP5609583B2 (ja) 電気光学装置、電気光学装置の製造方法、電子機器
JP2020034822A (ja) 電気光学装置、電子機器
JP2012181308A (ja) 電気光学装置および電子機器
JP7409236B2 (ja) 電気光学装置、及び電子機器
JP7434996B2 (ja) 電気光学装置、および電子機器
JP2012252033A (ja) 電気光学装置および電子機器
US9383633B2 (en) Electro-optical device and electronic apparatus
JP2022007339A (ja) 電気光学装置、及び電子機器
JP2012078680A (ja) 電気光学装置、電気光学装置の製造方法、電子機器
JP2019128518A (ja) 電気光学装置、電子機器

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17894968

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2018565994

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17894968

Country of ref document: EP

Kind code of ref document: A1