WO2018140842A2 - Insulate gate hybrid mode transistor - Google Patents

Insulate gate hybrid mode transistor Download PDF

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Publication number
WO2018140842A2
WO2018140842A2 PCT/US2018/015626 US2018015626W WO2018140842A2 WO 2018140842 A2 WO2018140842 A2 WO 2018140842A2 US 2018015626 W US2018015626 W US 2018015626W WO 2018140842 A2 WO2018140842 A2 WO 2018140842A2
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Prior art keywords
trench
ighmt
semiconductor
semiconductor layer
schottky junction
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PCT/US2018/015626
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French (fr)
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WO2018140842A3 (en
Inventor
Hongjian Wu
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Hongjian Wu
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Publication of WO2018140842A3 publication Critical patent/WO2018140842A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates

Definitions

  • This invention relates to power semiconductor devices.
  • Power semiconductor devices are widely used to control the flow of current to electronic devices such as motors and inductive heating ovens, typically VDMOS field effect transistors and insulate gate bipolar transistor (IGBT).
  • IGBT the gate voltage turns the device on by inducing a conducting MOS channel to flow the base current of the Bipolar Transistor.
  • a MOSFET that include three layers of alternating conductivity type semiconductors combines a Bipolar Transistor including three alternating layers, with two layers from each device sharing dual functions, i.e., Body and Drain layer of MOSFET become Collector and Base of the Bipolar Transistor.
  • an IGBT needs four layers of alternating conductivity type semiconductors to work.
  • a four-layer device is effectively a thyristor.
  • a thyristor acts exclusively as a bi-stable switch, conducting once the gate being triggered, and continuing to conduct as long as the voltage across the device is not removed or reversed.
  • Latch-up When an IGBT turns into Thyristor mode, called Latch-up, it lost the ability to switch off and becomes malfunction.
  • IGBT designers made years efforts to make an advanced design that is less prone to latch-up in the use, However, a total !atch ⁇ up free IGBT type of device is always in desire.
  • an Insulate Gate Hybrid Mode Transistor (IGHMT) power semiconductor device in accordance with this invention is formed in a
  • a heavy doping layer is formed to serve as Cathode layer.
  • the paired first and second trenches are provided along the surface of the Cathode layer and separated by mesas having parallel sides.
  • a MOS gate electrode is formed via an insulating film coating on the trench sidewall.
  • the Schottky junction is provided on the upper sidewall and connected to Cathode electrode via the metal trench filling that is electrically isolated from the substrate by an insulating film provided on the lower part of the sidewalls.
  • a metal Cathode electrode is connecting the Cathode layer and Schottky junction in the second trench.
  • a second conductivity type Anode layer is forming a PN junction. The metal Anode electrode is provided to electrically connect to the Anode layer.
  • the substrate is generally doped with N-type dopant uniformly except the Cathode layer at top surface of the substrate having a n+-type heavy doping level; the Anode layer is doped with P-type dopant.
  • the poly silicon which forms the gate electrode is doped with P-type dopant.
  • the depletion retreats and accumulation layer forms along the walls of the first trench.
  • the majority carrier current can flow from the Anode layer to the Cathode and minority carrier current can be collected by reverse biased Schottky junction by charge balancing principle.
  • the gate is biased zero or negative, the depletion come back and pinch off the majority carrier current path and cease minority carrier current flow altogether.
  • FIG. 1 is a schematic cross-sectional view of the main part of the semiconductor device IGHMT;
  • FIG. 2 is schematic cross-sectional views of main parts illustrating the first part of manufacturing process steps of the semiconductor device IGHMT;
  • FIG. 3 is schematic cross-sectional views of main parts illustrating the second part of manufacturing process steps of the semiconductor device IGHMT;
  • FIG. 4 is schematic cross-sectional views of main parts illustrating the third part of manufacturing process steps of the semiconductor device IGHMT;
  • FIG. 5 is schematic cross-sectional views of main parts illustrating the fourth part of manufacturing process steps of the semiconductor device IGHMT;
  • FIG. 6 is schematic cross-sectional views of main parts illustrating the fifth part of manufacturing process steps of the semiconductor device IGHMT.
  • FIG. 7 is schematic cross-sectional views of main parts illustrating the sixth part of manufacturing process steps of the semiconductor device IGHMT.
  • the Insulate Gate Hybrid Mode Transistor in accordance with this invention includes a first semiconductor layer of a first conductivity type as substrate, a second semiconductor layer of same conductivity type but having higher doping level provided on the first surface of the substrate, a third semiconductor layer of the second conductivity type on the second surface of the substrate, a first trench having MOS control electrode provided via an insulating film, an second trench having Schottky junction on upper portion sidewalls and insulating film on lower portion sidewalls, a Cathode electrode connecting to second semiconductor layer as well as Schottky junctions in the second trench, a Anode electrode connecting to the third semiconductor layer.
  • the first and second trenches are paired and separated by mesas having parallel sides and
  • FIG. 1 is a schematic cross-sectional view of a main part of the IGHMT according to the invention and illustrates as a device cell portion of the IGHMT.
  • Cathode layer 1 is a heavy dosed n+-type semiconductor layer
  • the substrate 3 is lightly dosed n-type semiconductor substrate or the epitaxial layer.
  • a plurality of trenches 10 is provided penetrating the surface of the Cathode layer 1 into the substrate or epitaxial layer 3 and periodically in a direction substantially parallel to the major surface of the substrate or the epitaxial layer.
  • the trenches 10 are built into two types: the first trench having MOS electrode 12 and the second trench having sidewall Schottky junction 15. These two trenches are paired and separated by mesas 20 in shapes having parallel sides such as rectangle, hexagon, stripe, etc.
  • the first trench is provided with gate insulting film 6 and gate electrode 12.
  • the second trench is provided with a sidewall Schottky barrier junction that is formed by a high work function barrier material 15 in contacting with the upper portion of the mesa sidewall.
  • An insulating film 6 is provided on the bottom portion of the second trench to prevent Cathode electrode metal 16 from contacting the substrate or the epitaxial layer 3.
  • the P-type Anode layer 18 is provided on the lower surface of the substrate by conventional doping technique, or as a top portion of the epitaxial substrate to the epitaxial layer.
  • the metal layer forms Cathode electrode 16 also fills the second trench to make the electrical connection to Schottky barrier junction.
  • a multi-layer metal Anode electrode 19 is formed on the surface of the Anode layer 18 by sputtering or CVD method.
  • a main component of the substrate 3 and the mesa 20 is n-type silicon (Si), for example.
  • a main component of the Anode layer 18 is p-type silicon (Si) from epitaxial substrate or conventional doping, for example.
  • a main component of the gate electrode 12 is P-type doped polysilicon (poly-Si), for example.
  • a main component of the Cathode electrode 16 is aluminum (Al), for example.
  • a main component of the Anode electrode 19 is multi-layer metal (Al-Ti-Ni-Ag), for example.
  • a main component of the insulating film 6 is silicon oxide (Si0 2 ), for example.
  • a main component of the Schottky barrier material 15 is Platinum (Pt), for example.
  • FIGs. 2 to 8 are schematic cross-sectional views of main parts for illustrating manufacturing processes of the semiconductor device.
  • the n-type substrate for example, semiconductor wafer-like
  • an n+-type Cathode layer 1 is formed on the upper surface of the substrate 3 by impurity diffusion (for example, ion implantation Arsenic followed by thermal anneal).
  • a plurality of trenches 10 is formed by using the anisotropic etching (for example, Reactive Ion Etching, RIE) or the like after a etching mask layer such as silicon oxide film, a resist and the like (not shown) is selectively formed on the surface of the Cathode layer 1 .
  • the insulating film 6 is formed in the trenchI O by using the thermal oxidation method, the chemical vapor deposition (CVD) method or the like.
  • a sacrificial film 30 (for example, Silicon Nitride or the like) is deposited in the trench 12 before a etch mask layer such as a resist and the like is selectively formed on the first type trenches.
  • the sacrificial film 30 is selectively etched away in second type trench, but leave insulating film 6 not etched.
  • polysilicon (poly-Si) is deposited and filled in the gate trench.
  • the formation method of polysilicon is, for example, the CVD method.
  • polysilicon is etched back.
  • the polisilicon gate electrode 12 is formed in the second type trench, as shown in FIG. 4.
  • the sacrificial film 30 is globally etched away including those filled in the first type trenches.
  • a silicon nitride film 14 is deposited by CVD method and thereafter an anisotropic nitride etch is performed to remove most of the film 14 except on the sidewalls of the first type trenches, as shown in FIG. 5.
  • a thermal oxidation is performed.
  • a silicon oxide layer 6 is thus formed over the surface exposed, including the bottom of first type trenches, except the sidewall surfaces covered by silicon nitride film 14.
  • an isotropic etching of Nitride such as phosphoric acid submerging method, is performed to strip off silicon nitride film 14 on the sidewall of first type trenches.
  • a Schottky junction is thus formed on the sidewall in first type trenches by Schottky film 15 contacting the semiconductor mesa sidewall.
  • the backside of the substrate is reduced by chemical-mechanical method to reach a pre-determined total thickness.
  • An ion implantation or other method is introducing the second conductivity type impurities into semiconductor layer 3 and followed by a heating anneal.
  • the Anode electrode 19 is then formed by sputter or CVD deposition method as shown in FIG.8.
  • the epitaxial technique can be used to grow n-type EPI layer on top of the P-type substrate initially as the substrate 3 then follow the same process steps described above to reach stage in FIG. 7.
  • the EPI substrate will be treated as Anode layer 18 and Anode electrode 19 is then formed by sputter or CVD deposition method as shown in FIG.8
  • the IGHMT shown in FIG. 1 includes a mesa (patterned area 20) having trench sidewall Schottky junction 15 on one side and trench MOS gate 12 on the opposite side.
  • the Schottky junction 15 and the MOS gate 12 are arranged face to face forming a mesa Schottky junction field effect transistor (mSJFET).
  • mSJFET mesa Schottky junction field effect transistor
  • the on-state of the SJFET can be achieved by applying a voltage to the MOS gate 12.
  • This gate voltage is to induce a majority carrier accumulation layer on the trench sidewall facing the gate electrode.
  • the gate voltage needs to be high enough to attract enough majority carriers out of the depletion region to reverse depletion into accumulation in surface layer.
  • This gate voltage is then the threshold voltage of the IGHMT. This represents the on-state of mSJFET.
  • a positive voltage applies to Anode electrode 19 with respect to Cathode providing a forward bias for the PN junction (Layer 18 and 3) but reverse biases for the Schottky junction.
  • the mesa With zero or negative gate voltage, the mesa is fully depleted and the mSJFET is off so that IGHMT is in its forward blocking status.
  • the accumulation layer With the applying of a gate voltage higher than the threshold voltage, the accumulation layer is established and provides the conducting path for the majority carrier current which is driven by the forward biased PN junction.
  • the forward biased PN junction also drives minority carriers into substrate 3. The minority carriers are subsequently drawn to the reverse biased Schottky junction for charge balance principle and collected by Cathode electrode 16. If the mSJFET is turned off, the majority carrier current in mSJFET will be cut off and the minority carrier current would also stop to flow due to the same principle.
  • IGHMT Similar to an enhance mode MOS transistor the forward conducting of IGHMT will enter the saturation zone at any given gate voltage which is higher than the threshold voltage of IGHMT, where the Anode current will be maintained at a steady level not affected by the changing the Anode-Cathode voltage. This is due to that increasing of Anode voltage will result in increasing PN junction forward current but at same time the Schottky junction reverse bias is enhanced and result in diminishing the current flowing through the accumulation layer. A stalemate will be reached as the field potential established by majority current flow through the resistance of the accumulation layer cancels depletion field potential.
  • a properly chosen Schottky barrier height (Schottky material's work function) is essential to make the IGHMT work. Ideally the mesa is fully depleted even with the Schottky junction is zero biased. This is accomplished by choosing the right mesa width, picking the right Schottky barrier material and MOS electrode material. For example, Platinum is used as Schottky barrier material, P-type polysilicon is used as MOS electrode material.

Abstract

Insulate Gate Hybrid Mode Transistor (IGHMT) includes a substrate of the first conductivity type having a high doping top layer of the same conductivity type on its first surface; a PN junction formed by a second conductivity type bottom layer provided on the second surface of the substrate; plurality of trenches that penetrate the surface of high doping top layer and extend a pre-determined depth into substrate separated by the mesas having parallel sides. In one side of the mesa the sidewall Schottky junction is formed on the upper portion of the first trench while in the opposite side of the mesa the MOS control electrode is formed in the second trench. The Cathode electrode electrically connect Schottky junction in the first trench and high doping top layer. The Anode electrode electrically connects the surface of the bottom layer.

Description

INSULATE GATE HYBRID MODE TRANSISTOR
Description
Field of the Invention
This invention relates to power semiconductor devices. Background of the Invenrion
Power semiconductor devices are widely used to control the flow of current to electronic devices such as motors and inductive heating ovens, typically VDMOS field effect transistors and insulate gate bipolar transistor (IGBT). In an IGBT, the gate voltage turns the device on by inducing a conducting MOS channel to flow the base current of the Bipolar Transistor. Inside of IGBT, a MOSFET that include three layers of alternating conductivity type semiconductors combines a Bipolar Transistor including three alternating layers, with two layers from each device sharing dual functions, i.e., Body and Drain layer of MOSFET become Collector and Base of the Bipolar Transistor. In its configuration, an IGBT needs four layers of alternating conductivity type semiconductors to work. However in
semiconductor device theory, a four-layer device is effectively a thyristor. A thyristor acts exclusively as a bi-stable switch, conducting once the gate being triggered, and continuing to conduct as long as the voltage across the device is not removed or reversed. When an IGBT turns into Thyristor mode, called Latch-up, it lost the ability to switch off and becomes malfunction. IGBT designers made years efforts to make an advanced design that is less prone to latch-up in the use, However, a total !atch~up free IGBT type of device is always in desire.
Summery of the Invention
As shown in FIG. 1. an Insulate Gate Hybrid Mode Transistor (IGHMT) power semiconductor device in accordance with this invention is formed in a
semiconductor substrate having first conductivity type. At upper surface of the substrate a heavy doping layer is formed to serve as Cathode layer. The paired first and second trenches are provided along the surface of the Cathode layer and separated by mesas having parallel sides. In first trench a MOS gate electrode is formed via an insulating film coating on the trench sidewall. In second trench the Schottky junction is provided on the upper sidewall and connected to Cathode electrode via the metal trench filling that is electrically isolated from the substrate by an insulating film provided on the lower part of the sidewalls. A metal Cathode electrode is connecting the Cathode layer and Schottky junction in the second trench. At lower surface of the substrate a second conductivity type Anode layer is forming a PN junction. The metal Anode electrode is provided to electrically connect to the Anode layer.
In one example, the substrate is generally doped with N-type dopant uniformly except the Cathode layer at top surface of the substrate having a n+-type heavy doping level; the Anode layer is doped with P-type dopant. The poly silicon which forms the gate electrode is doped with P-type dopant. With properly chosen Schottky material and the width of the mesa, when a positive voltage is applied to the Anode electrode with respect to the Cathode a depletion regions will extend from Schottky junction on one side of the mesa to the MOS gate on other side of mesa to pinch off current path between the Anode and the Cathode. When the gate electrode is biased positive, the depletion retreats and accumulation layer forms along the walls of the first trench. With the PN junction forward biased, the majority carrier current can flow from the Anode layer to the Cathode and minority carrier current can be collected by reverse biased Schottky junction by charge balancing principle. When the gate is biased zero or negative, the depletion come back and pinch off the majority carrier current path and cease minority carrier current flow altogether.
Brief Description of the Drawings
FIG. 1 is a schematic cross-sectional view of the main part of the semiconductor device IGHMT;
FIG. 2 is schematic cross-sectional views of main parts illustrating the first part of manufacturing process steps of the semiconductor device IGHMT;
FIG. 3 is schematic cross-sectional views of main parts illustrating the second part of manufacturing process steps of the semiconductor device IGHMT;
FIG. 4 is schematic cross-sectional views of main parts illustrating the third part of manufacturing process steps of the semiconductor device IGHMT;
FIG. 5 is schematic cross-sectional views of main parts illustrating the fourth part of manufacturing process steps of the semiconductor device IGHMT;
FIG. 6 is schematic cross-sectional views of main parts illustrating the fifth part of manufacturing process steps of the semiconductor device IGHMT.
FIG. 7 is schematic cross-sectional views of main parts illustrating the sixth part of manufacturing process steps of the semiconductor device IGHMT.
Description of the Invention In general, the Insulate Gate Hybrid Mode Transistor (IGHMT) in accordance with this invention includes a first semiconductor layer of a first conductivity type as substrate, a second semiconductor layer of same conductivity type but having higher doping level provided on the first surface of the substrate, a third semiconductor layer of the second conductivity type on the second surface of the substrate, a first trench having MOS control electrode provided via an insulating film, an second trench having Schottky junction on upper portion sidewalls and insulating film on lower portion sidewalls, a Cathode electrode connecting to second semiconductor layer as well as Schottky junctions in the second trench, a Anode electrode connecting to the third semiconductor layer. The first and second trenches are paired and separated by mesas having parallel sides and
penetrating through the second semiconductor layer into the substrate in pre-determined depth.
FIG. 1 is a schematic cross-sectional view of a main part of the IGHMT according to the invention and illustrates as a device cell portion of the IGHMT. For example, Cathode layer 1 is a heavy dosed n+-type semiconductor layer, the substrate 3 is lightly dosed n-type semiconductor substrate or the epitaxial layer. A plurality of trenches 10 is provided penetrating the surface of the Cathode layer 1 into the substrate or epitaxial layer 3 and periodically in a direction substantially parallel to the major surface of the substrate or the epitaxial layer. The trenches 10 are built into two types: the first trench having MOS electrode 12 and the second trench having sidewall Schottky junction 15. These two trenches are paired and separated by mesas 20 in shapes having parallel sides such as rectangle, hexagon, stripe, etc.
Further in FIG. 1 , on one side of the mesa, the first trench is provided with gate insulting film 6 and gate electrode 12. On the opposite side of the mesa, the second trench is provided with a sidewall Schottky barrier junction that is formed by a high work function barrier material 15 in contacting with the upper portion of the mesa sidewall. An insulating film 6 is provided on the bottom portion of the second trench to prevent Cathode electrode metal 16 from contacting the substrate or the epitaxial layer 3. The P-type Anode layer 18 is provided on the lower surface of the substrate by conventional doping technique, or as a top portion of the epitaxial substrate to the epitaxial layer. The metal layer forms Cathode electrode 16 also fills the second trench to make the electrical connection to Schottky barrier junction. A multi-layer metal Anode electrode 19 is formed on the surface of the Anode layer 18 by sputtering or CVD method.
A main component of the substrate 3 and the mesa 20 is n-type silicon (Si), for example. A main component of the Anode layer 18 is p-type silicon (Si) from epitaxial substrate or conventional doping, for example. A main component of the gate electrode 12 is P-type doped polysilicon (poly-Si), for example. A main component of the Cathode electrode 16 is aluminum (Al), for example. A main component of the Anode electrode 19 is multi-layer metal (Al-Ti-Ni-Ag), for example. A main component of the insulating film 6 is silicon oxide (Si02), for example. A main component of the Schottky barrier material 15 is Platinum (Pt), for example.
Next, manufacturing processes of the device will be described by way of one example.
FIGs. 2 to 8 are schematic cross-sectional views of main parts for illustrating manufacturing processes of the semiconductor device.
First, as shown in FIG. 2, the n-type substrate (for example, semiconductor wafer-like) is prepared. Next, an n+-type Cathode layer 1 is formed on the upper surface of the substrate 3 by impurity diffusion (for example, ion implantation Arsenic followed by thermal anneal). Next, a plurality of trenches 10 is formed by using the anisotropic etching (for example, Reactive Ion Etching, RIE) or the like after a etching mask layer such as silicon oxide film, a resist and the like (not shown) is selectively formed on the surface of the Cathode layer 1 . Next, the insulating film 6 is formed in the trenchI O by using the thermal oxidation method, the chemical vapor deposition (CVD) method or the like.
Thereafter, as shown in FIG. 3, a sacrificial film 30 (for example, Silicon Nitride or the like) is deposited in the trench 12 before a etch mask layer such as a resist and the like is selectively formed on the first type trenches.
Next, the sacrificial film 30 is selectively etched away in second type trench, but leave insulating film 6 not etched. Thereafter, polysilicon (poly-Si) is deposited and filled in the gate trench. The formation method of polysilicon is, for example, the CVD method. Thereafter, polysilicon is etched back. As a result, the polisilicon gate electrode 12 is formed in the second type trench, as shown in FIG. 4.
Next, the sacrificial film 30 is globally etched away including those filled in the first type trenches. A silicon nitride film 14 is deposited by CVD method and thereafter an anisotropic nitride etch is performed to remove most of the film 14 except on the sidewalls of the first type trenches, as shown in FIG. 5.
Next, as shown in FIG. 6, a thermal oxidation is performed. A silicon oxide layer 6 is thus formed over the surface exposed, including the bottom of first type trenches, except the sidewall surfaces covered by silicon nitride film 14.
Next, not shown in FIGs, an isotropic etching of Nitride, such as phosphoric acid submerging method, is performed to strip off silicon nitride film 14 on the sidewall of first type trenches. A high work function material (metal or metal alloy) film 15, such as Platinum, is then deposited followed by an anisotropic etch to only conserve the metallic film 15 on the sidewalls in first type trenches, as shown in FIG. 7. A Schottky junction is thus formed on the sidewall in first type trenches by Schottky film 15 contacting the semiconductor mesa sidewall.
Thereafter, the backside of the substrate is reduced by chemical-mechanical method to reach a pre-determined total thickness. An ion implantation or other method is introducing the second conductivity type impurities into semiconductor layer 3 and followed by a heating anneal. The Anode electrode 19 is then formed by sputter or CVD deposition method as shown in FIG.8.
Alternatively the epitaxial technique can be used to grow n-type EPI layer on top of the P-type substrate initially as the substrate 3 then follow the same process steps described above to reach stage in FIG. 7. The EPI substrate will be treated as Anode layer 18 and Anode electrode 19 is then formed by sputter or CVD deposition method as shown in FIG.8
Next, the functional effect of the IGHMT will be described.
The IGHMT shown in FIG. 1 includes a mesa (patterned area 20) having trench sidewall Schottky junction 15 on one side and trench MOS gate 12 on the opposite side. The Schottky junction 15 and the MOS gate 12 are arranged face to face forming a mesa Schottky junction field effect transistor (mSJFET). When the Schottky junction 15 is negatively biased its depletion region extends from the Schottky barrier towards the MOS gate 12 on opposite side of the mesa. The conducting path from Anode electrode 19 to Cathode electrode 14 is cut off once the mesa is fully depleted laterally. This represents the off-state of the mSJFET. The on-state of the SJFET can be achieved by applying a voltage to the MOS gate 12. This gate voltage is to induce a majority carrier accumulation layer on the trench sidewall facing the gate electrode. The gate voltage needs to be high enough to attract enough majority carriers out of the depletion region to reverse depletion into accumulation in surface layer. This gate voltage is then the threshold voltage of the IGHMT. This represents the on-state of mSJFET.
A positive voltage applies to Anode electrode 19 with respect to Cathode providing a forward bias for the PN junction (Layer 18 and 3) but reverse biases for the Schottky junction. With zero or negative gate voltage, the mesa is fully depleted and the mSJFET is off so that IGHMT is in its forward blocking status. With the applying of a gate voltage higher than the threshold voltage, the accumulation layer is established and provides the conducting path for the majority carrier current which is driven by the forward biased PN junction. On the other direction, the forward biased PN junction also drives minority carriers into substrate 3. The minority carriers are subsequently drawn to the reverse biased Schottky junction for charge balance principle and collected by Cathode electrode 16. If the mSJFET is turned off, the majority carrier current in mSJFET will be cut off and the minority carrier current would also stop to flow due to the same principle.
Similar to an enhance mode MOS transistor the forward conducting of IGHMT will enter the saturation zone at any given gate voltage which is higher than the threshold voltage of IGHMT, where the Anode current will be maintained at a steady level not affected by the changing the Anode-Cathode voltage. This is due to that increasing of Anode voltage will result in increasing PN junction forward current but at same time the Schottky junction reverse bias is enhanced and result in diminishing the current flowing through the accumulation layer. A stalemate will be reached as the field potential established by majority current flow through the resistance of the accumulation layer cancels depletion field potential.
A properly chosen Schottky barrier height (Schottky material's work function) is essential to make the IGHMT work. Ideally the mesa is fully depleted even with the Schottky junction is zero biased. This is accomplished by choosing the right mesa width, picking the right Schottky barrier material and MOS electrode material. For example, Platinum is used as Schottky barrier material, P-type polysilicon is used as MOS electrode material.

Claims

Ciaims What is claimed is:
1. An Insulate Gate Hybrid Mode Transistor (IGHMT) comprising:
a first semiconductor layer of a first conductivity type;
a second semiconductor layer of a first conductivity type provided on the first surface of the first semiconductor layer;
a third semiconductor layer of the second conductivity type provided on the second surface of the first semiconductor layer;
a semiconductor mesa formed by peripheral trenches which penetrate the second semiconductor layer into the first semiconductor layer;
a control electrode provided via insulating film forms a MOS gate in the first trench on one side of the semiconductor mesa;
a Schottky junction formed on upper sidewalls of the second trench on the opposite side of the semiconductor mesa;
a first main electrode provided in the second trench and electrically connected to Schottky junction and the surface of the second semiconductor layer;
a second main electrode electrically connected to surface of the third
semiconductor layer.
2. The IGHMT according to claim 1, wherein the second semiconductor layer has higher doping concentration than that of the first semiconductor iayer.
3. The IGHMT according to claim 1, wherein the semiconductor mesa could has various shapes, most commonly rectangle, hexagon and stripe.
4. The IGHMT according to claim 1, wherein the first and second trenches are provided alternatively in plurality along the surface of the second semiconductor Iayer and separated by the semiconductor mesas.
5. The IGHMT according to claim 1, wherein the Schottky junction is formed by Schottky barrier material contacting semiconductor in upper portion sidewalls of the second trench.
6. The IGHMT according to claim 1, wherein the second trench is filled with metal electrode material so that the first main electrode can make contact to the
Schottky junction.
7. The IGHMT according to claim 5, wherein an insulating film is provided on the second trench sidewalls where the Schottky junction does not form.
PCT/US2018/015626 2017-01-30 2018-01-28 Insulate gate hybrid mode transistor WO2018140842A2 (en)

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JP3216743B2 (en) * 1993-04-22 2001-10-09 富士電機株式会社 Protection diode for transistor
JP3618517B2 (en) * 1997-06-18 2005-02-09 三菱電機株式会社 Semiconductor device and manufacturing method thereof
US7157785B2 (en) * 2003-08-29 2007-01-02 Fuji Electric Device Technology Co., Ltd. Semiconductor device, the method of manufacturing the same, and two-way switching device using the semiconductor devices
US7285822B2 (en) * 2005-02-11 2007-10-23 Alpha & Omega Semiconductor, Inc. Power MOS device
US7737522B2 (en) * 2005-02-11 2010-06-15 Alpha & Omega Semiconductor, Ltd. Trench junction barrier controlled Schottky device with top and bottom doped regions for enhancing forward current in a vertical direction
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