WO2018125244A1

WO2018125244A1 - Perpendicular magnetic tunnel junction (pmtj) devices having thermally resistive layers

Info

Publication number: WO2018125244A1
Application number: PCT/US2016/069627
Authority: WO
Inventors: Charles C. Kuo; Abhishek A. Sharma
Original assignee: Intel Corporation
Priority date: 2016-12-30
Filing date: 2016-12-30
Publication date: 2018-07-05

Abstract

In various embodiments, disclosed herein are systems, methods, and apparatus directed to one or more thermally resistive layers that may be proximate to the bottom electrode or the top electrode in a perpendicular magnetic tunnel junction (pMTJ) device. In one embodiment, the thermally resistive layers can act to sandwich an active layer of the device and thereby at least partially contain and/or confine heat generated from the active layer during operation of the device. In one embodiment the thermally resistive layers can include any suitable material, including conductive metal oxides such as, for example, indium tin oxide (ITO), indium zinc oxide (IZO), amorphous carbon, indium gallium zinc oxide (IGZO), amorphous carbon, tin oxide (SnO), tungsten (W), cobalt (Co), tantalum nitride (TaN), titanium nitride (TiN), and the like.

Description

PERPENDICULAR MAGNETIC TUNNEL JUNCTION (PMTJ) DEVICES HAVING

THERMALLY RESISTIVE LAYERS

TECHNICAL FIELD

[0001] This disclosure generally relates perpendicular magnetic tunnel junction (pMTJ) devices.

BACKGROUND

[0002] Magnetic tunnel junctions (MTJs) can represent electronic components comprising two ferromagnets separated by a thin insulator. The insulating layer can be thin (typically a few nanometers), permitting electrons to tunnel from one ferromagnet into the other. MTJs can be manufactured using thin film technology. The film deposition can be performed, for example, by magnetron sputter deposition, molecular beam epitaxy, pulsed laser deposition, and/or electron beam physical vapor deposition. A magnetic tunnel junction with a perpendicular magnetic axis (referred herein as a perpendicular magnetic tunnel junction, pMTJ) is a type of MTJ that can be used for spintronic nonvolatile magnetoresistive random access memory (MRAM).

BRIEF DESCRIPTION OF THE FIGURES

[0003] Reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and wherein:

[0004] FIG. 1 shows a diagram of an example cross-sectional view of a perpendicular magnetic tunnel junction (pMTJ) device in accordance with one or more example embodiments of the disclosure;

[0005] FIG. 2 shows an example cross-sectional view of a pMTJ device, in accordance with one or more example embodiments of the disclosure;

[0006] FIG. 3 shows another example cross-sectional view of a pMTJ device, in accordance with example embodiments of the disclosure; [0007] FIG. 4 shows a diagram of an example cross-sectional view of a pMTJ device, in accordance with one or more example embodiments of the disclosure;

[0008] FIG. 5 shows a diagram of an example cross-sectional view of a portion of a pMTJ device, in accordance with one or more example embodiments of the disclosure; [0009] FIG. 6 shows a diagram that represents a cross-sectional view of a first device with one reference layer, a second device with one reference layer and a thermally resistive layer and a plot of the temperature in the various layers of the devices and (temperature on the x axis versus the position in the device on the y axis), in accordance with one or more example embodiments of the disclosure; [0010] FIG. 7 shows an example processing flow diagram that can be used to fabricate an example pMTJ device, in accordance with one or more example embodiments of the disclosure; and

[0011] FIG. 8 illustrates an example of a system, in accordance with one or more embodiments of the disclosure. DETAILED DESCRIPTION

[0012] Embodiments of the disclosure are described more fully hereinafter with reference to the accompanying drawings, in which example embodiments of the disclosure are shown. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like numbers refer to like, but not necessarily the same or identical, elements throughout.

[0013] The following embodiments are described in sufficient detail to enable at least those skilled in the art to understand and use the disclosure. It is to be understood that other embodiments would be evident based on the present disclosure and that process, mechanical, material, dimensional, process equipment, and parametric changes may be made without departing from the scope of the present disclosure. [0014] In the following description, numerous specific details are given to provide a thorough understanding of various embodiments of the disclosure. However, it will be apparent that the disclosure may be practiced without these specific details. In order to avoid obscuring the present disclosure, some well-known system configurations and process steps may not be disclosed in full detail. Likewise, the drawings showing embodiments of the disclosure are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and may be exaggerated in the drawings. In addition, where multiple embodiments are disclosed and described as having some features in common, for clarity and ease of illustration, description, and comprehension thereof, similar and like features will ordinarily be described with like reference numerals even if the features are not identical.

[0015] The term "horizontal" as used herein may be defined as a direction parallel to a plane or surface (for example, surface of a substrate), regardless of its orientation. The term "vertical," as used herein, may refer to a direction orthogonal to the horizontal direction as just described. Terms, such as "on," "above," "below," "bottom," "top," "side" (as in "sidewall"), "higher," "lower," "upper," "over," and "under," may be referenced with respect to a horizontal plane, where the horizontal plane can include an x- y plane, a x-z plane, or a y-z plane, as the case may be. The term "processing" as used herein includes deposition of material or photoresist, patterning, exposure, development, etching, cleaning, ablating, polishing, and/or removal of the material or photoresist as required in formation a described structure.

[0016] In various embodiments, disclosed herein may be one or more thermally resistive layers that may be proximate to the bottom electrode or the top electrode in a perpendicular magnetic tunnel junction (pMTJ) device. In one embodiment, the thermally resistive layers can act to sandwich the active layer of the device, and thereby at least partially contain and/or confine heat generated from the active layer during operation of the device. In one embodiment the thermally resistive layers can include any suitable material, including conductive metal oxides such as, for example, indium tin oxide (ITO), indium zinc oxide (IZO), amorphous carbon, indium gallium zinc oxide (IGZO), amorphous carbon, tin oxide (SnO), tungsten (W), cobalt (Co), tantalum nitride (TaN), titanium nitride (TiN), and the like. [0017] In one embodiment, the thermally resistive layers can further comprise a multilayer. The thermally resistive multilayer can include a first conductive metal oxide layer, followed by a metal layer, then followed by again another conductive metal oxide layer, and another metal layer and so on. In one embodiment, the thermally resistive multilayer can have a high difference in Debye temperature between individual layers comprising the thermally resistive multilayer. For example, the metal layer can include a material that has Debye temperature that is less than or approximately equal to ambient temperature. For example, tantalum (Ta) may have a Debye temperature at approximately 240K; further, Ta is electrically conductive. Continuing with the example, the non-metal layer can include a material having a higher Debye temperature and a low electrical resistance below a predetermined threshold vale. For example, the non-metal layer can include: amorphous carbon, ITO, and/or IGZO. In one embodiment, the temperature within one of the layers of the pMTJ (for example, the free layer of the pMTJ) can rise with a larger Debye temperature mismatch (that it, different in Debye temperature between layers) in the multi-layer, and/or with a larger Debye temperature mismatch between the thermally resistive layer and neighboring layers to the thermally resistive layer, for example, the free layer of the pMTJ. In one embodiment, a larger Debye temperature mismatch can result in a larger difference in available phonon modes for heat to travel through in the free layer, which results in a higher thermal interface resistance, for example, between the thermally resistive layer and a free layer. Further, with additional layers in the thermally resistive multilayer, the thermal resistance of the thermally resistive multilayer can increase, at least partially due to the presence of more interfaces in the thermally resistive multilayer.

[0018] In one embodiment, the thermally resistive layer and/or multilayer can have a total thickness of approximately 0.5 nm to approximately 20 nm, with example thicknesses of approximately 1 nm to approximately 3 nm. In one example embodiment the conductive metal oxide can include a zinc oxide and indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), amorphous carbon, tin oxide (SnO), tungsten (W), cobalt (Co), tantalum nitride (TaN), titanium nitride (TiN), and the like. In one embodiment, the metal can include aluminum, silver, copper, gold, zinc, tin, tungsten, and the like. In one embodiment the confinement of the heat generated by the active layer by the one or more thermally resistive layers and can assist the switching mechanism of the active layer. This process can thereby reduce the read and/or write power consumption during operation of the device. For example, the read and/or write power consumption can be reduced in the context of a memory array employing several devices in an array. In various embodiments the active layer, the thermally resistive layers, and the top and bottom electrodes can be deposited using any suitable mechanism, including, but not limited to, physical vapor deposition (PVD) chemical vapor deposition (CVD) and/or atomic layer deposition (ALD).

[0019] In one embodiment, the switching mechanism of the device can be due to both the magnitude of the current passing through the active layer and the operational temperature of the device. As such, the thermally resistive layer (for example, the thermally resistive layer) can assist the switching process of the device. In one embodiment, the thermally resistive layer can thereby act to reduce the temperature at which the active layer and thereby, the device, can switch from a low resistance to a high resistance and/or vice versa. In one embodiment, the thermally resistive layer can be positioned below the top electrode and above the active layer. In another embodiment thermally resistive layer can be, additionally or alternatively, placed above the top electrode.

[0020] In one embodiment, the thermally resistive layer and a second thermally resistive layer can further be included in the device. In an embodiment the first thermally resistive layer can be positioned between the bottom electrode and the active layer. In another embodiment the second thermally resistive layer can be positioned between the top electrode and the active layer.

[0021] Further the first thermally resistive layer can be positioned between the bottom electrode and the substrate. Additionally or alternatively, the thermally resistive layer could be positioned above the first buffer layer and/or between the first buffer layer and the active layer. Additionally or alternatively, the second thermally resistive layer can be positioned above the top electrode and/or between the second buffer layer and the active layer.

[0022] In all of these embodiments and other similar variations, the thermally resistive layer can serve to confine the heat in the active layer. Therefore the presence of thermally resistive layers (for example thermally resistive layers and/or thermally resistive layer) throughout the device in proximity to both the bottom electrode and/or the top electrode can serve to further confine the heat in the active layer, and thereby serve to reduce the switching power of the device.

[0023] FIG. 1 shows a diagram of an example cross-sectional view of a perpendicular magnetic tunnel junction (pMTJ) device in accordance with one or more example embodiments of the disclosure. In one embodiment, the pMTJ device 100 can be fabricated on a substrate 101. In another embodiment, the substrate 101 can refer to a solid (usually planar) substance onto which a layer of another substance is applied, and to which that second substance adheres. The substrate 101 can be a thin slice of material such as silicon, silicon dioxide, aluminum oxide, sapphire, germanium, gallium arsenide(GaAs), an alloy of silicon and germanium, or indium phosphide (InP), and/or glass. In one or more embodiments, the substrate 101 can serve as a heat sink for the device 100 allowing for the dissipation of heat generated by the various layers (to be discussed) in the device 100.

[0024] The device 100 can further include a bottom electrode 102 and a top electrode 110 that may, together, sandwich an active layer. For example, the bottom electrode 102 can be disposed substantially on the substrate 101. In one embodiment the bottom electrode 102 can include any suitable metal; for example, copper, tungsten, titanium nitride, platinum, and/or any other suitable material. Similarly, the top electrode 110 can include any suitable metal; for example, a copper, tungsten, titanium nitride, platinum, and/or any other suitable material.

[0025] Further, as shown in FIG. 1 the device 100 can include an active layer 106. The active layer 106 may include one or more layers; for example, the active layer 106 a three- layer structure (not shown) including a metal or a metal alloy, a metal oxide and another metal alloy. In various embodiments, the active layer 106 can act as a switching layer giving rise to the memory storage capability of the device 100.

[0026] In another embodiment, one or more thermally resistive layers 104 and 108 may be provided proximate to the bottom electrode 102 or the top electrode 110, respectfully. In one embodiment, the thermally resistive layers 104 and 108 can act to sandwich the active layer 106 and thereby at least partially contain and/or confine heat generated from the active layer 106 during operation of the device 100. In one embodiment the thermally resistive layers 104 and 108 can include any suitable material, including conductive metal oxides such as, for example, indium tin oxide (ITO), indium zinc oxide (IZO), amorphous carbon, indium gallium zinc oxide (IGZO), and the like.

[0027] In one embodiment the one or both of the thermally resistive layers 104 and/or 108 can further comprise a multilayer 111. The multilayer 111 can include a first conductive metal oxide layer 112, followed by a metal layer 114, then followed by again another conductive metal oxide layer 113, and another metal layer 114 and so on. In one embodiment, the thermally resistive layer can have a total thickness of approximately 0.5 nm to approximately 20 nm, with example thicknesses of approximately 1 nm to approximately 3 nm. In one example embodiment the conductive metal oxide layer 112 can include a zinc oxide and indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), amorphous carbon, tin oxide (SnO), tungsten (W), cobalt (Co), tantalum nitride (TaN), titanium nitride (TiN), and the like. In one embodiment, the metal 114 can include aluminum, silver, copper, gold, zinc, tin, tungsten, and the like. In one embodiment the confinement of the heat generated by the active layer 106 by the one or more thermally resistive layers 104 and 108 can assist the switching mechanism of the active layer. This process can thereby reduce the read and/or write power consumption during operation of the device 100. For example, the read and/or write power consumption can be reduced in the context of a memory array employing several devices (each device similar to the device 100) in an array. In various embodiments the active layer 106, the thermally resistive layers 104 and/or 108, and the top and bottom electrodes 102 and/or 110 can be deposited using any suitable mechanism, including, but not limited to, physical vapor deposition (PVD) chemical vapor deposition (CVD) and/or atomic layer deposition (ALD).

[0028] In one embodiment, the multilayer 111 can have a high difference in Debye temperature between individual layers (for example, between metal oxide layer 112 and the metal layer 114) comprising the multilayer 111. For example, the metal layer 114 can include a material that has Debye temperature that is less than or approximately equal to ambient temperature. For example, tantalum (Ta) may have a Debye temperature at approximately 240K; further, Ta can be electrically conductive. Continuing with the example, the metal-oxide layer 112 can include a material having a higher Debye temperature and a low electrical resistance below a predetermined threshold vale. For example, the metal-oxide layer 112 can include: amorphous carbon, ITO, and/or IGZO. In one embodiment, the temperature within one of the layers of the pMTJ (for example, the active layer 106 of the pMTJ) can rise with a larger Debye temperature mismatch (that it, different in Debye temperature between layers) in the multilayer 1 11 , and/or a larger Debye temperature mismatch between the multilayer 11 1 and neighboring layers to the multilayer 11 1, for example, the active layer 106 of the pMTJ. In one embodiment, a larger Debye temperature mismatch can result in a larger difference in available phonon modes for heat to travel through in the active layer 106, which results in a higher thermal interface resistance, for example, between the multilayer 11 1 and the active layer 106. Further, with additional layers in the multilayer 1 11 , the thermal resistance of the multilayer 1 11 can increase, at least partially due to the presence of more interfaces in the multilayer 111.

[0029] FIG. 2 shows a cross-sectional view of a pMTJ device 200, in accordance with one or more example embodiments of the disclosure. In an embodiment, the device 200 can include a substrate 201. The substrate 101 can be a thin layer of material such as silicon, silicon dioxide, aluminum oxide, sapphire, germanium, gallium arsenide(GaAs), an alloy of silicon and germanium, or indium phosphide (InP), and/or glass. In one or more embodiments, the substrate 201 can serve as a heat sink for the device 200 allowing for the dissipation of heat generated by the various layers (to be discussed) in the device 200.

[0030] In an embodiment, the device 200 can further include a bottom electrode 202. The bottom electrode can be deposited onto the substrate 201 using physical vapor deposition (PVD), chemical vapor deposition (CVD), and/or atomic layer deposition (ALD), or any other suitable method. In one embodiment, the bottom electrode 202 can include copper, tungsten, titanium nitride,platinum, and/or any other suitable material. In one embodiment, the bottom electrode 202 can have a thickness of approximately 0.4 nm to approximately 1 mm with example thicknesses of approximately 0.4 nm to approximately 20 nm.

[0031] In various embodiments of the disclosure the device 200 can further optionally include a first buffer layer 204. In one embodiment, the first buffer layer 204 may be deposited on to the bottom electrode 202. In another embodiment, the first buffer layer 204 can include a synthetic antiferromagnetic layer (SAF) layer 204. Alternatively or additionally, the first buffer layer can include cobalt, nickel, platinum, boron, and/or iron, and the like. The first buffer layer 204 can have a thickness of approximately 0.4 nm to approximately 20 nm. In one embodiment, the buffer layer can comprise a multilayer of various materials. The first buffer layer can be deposited using PVD, CVD, and/or ALD.

[0032] In one embodiment, the device 200 can further include a first magnetic layer 206 (which can also be referred to as a reference layer), and a tunneling layer 208 (which can also be referred to as a metal oxide layer, for example, a magnesium oxide layer, MgO). In another embodiment, the device 200 can further include a second magnetic layer 210 (which can also be referred to as a free layer). In one embodiment, a combination of the first magnetic layer 206, the tunneling layer 208, and the second magnetic layer 210 can be referred to as the active layer 211 of the device 200. [0033] In one embodiment the first magnetic layer 206 can have a perpendicular anisotropy. In another embodiment, the second magnetic layer 210 can have a perpendicular anisotropy. In one embodiment the first magnetic layer 206 can include a metal or a metal alloy material. For example, the first magnetic layer 206 can include a cobalt iron, boron based metal, and/or metal alloy material. In another embodiment, the tunneling layer 208 can include a metal oxide layer, for example, a magnesium oxide (MgO) material. In one embodiment the second magnetic layer 210 can also include a metal and/or a metal alloy material, for example, including, but not limited to a cobalt iron, boron based metal, and/or metal alloy material.

[0034] In one embodiment, the first magnetic layer 206 can have a thickness of approximately 0.4 nm to approximately 20 nm. In another embodiment the first magnetic layer 206 can be deposited using PVD, CVD, and/or ALD.

[0035] In one embodiment the tunneling layer 208 can have a thickness of approximately 0.4 nm to approximately 20 nm. In another embodiment, the tunneling layer 208 can be deposited using PVD, CVD, and/or ALD. [0036] In one embodiment the second magnetic layer 210 can have a thickness of approximately 0.4 nm to approximately 20 nm. In another embodiment the second magnetic layer 210 can be deposited using PVD, CVD, and/or ALD.

[0037] In one embodiment the device 200 can further include a second buffer layer 212 which may alternatively or additionally be referred to as a cap layer 212. The second buffer layer can have a thickness of approximately 0.4 nm to approximately 20 nm. In one embodiment, the second buffer layer 212 can be deposited using PVD, CVD, and/or ALD. In an embodiment the second buffer layer 212 can serve to space the active layer 21 1 from the top electrode 216 (to be discussed). [0038] In one embodiment the device 200 can further optionally include a thermally resistive layer 214 that may be deposited on the second buffer layer 212. Alternatively or additionally, if the second buffer layer 212 is not present in the device 200, the thermally resistive layer 214 can be deposited on the second magnetic layer 210. In one embodiment, the thermally resistive layer 214 can comprise a multi-layer structure similar to the multi-layer structure 1 11 shown and described in connection with FIG. 1. For example, the thermally resistive layer 214 can include a structure comprising a conductive metal oxide layer, a metal layer and then another conductive metal oxide layer, another metal layer in series (not shown).

[0039] In an embodiment the thickness of the thermally resistive layer 214 can be approximately 0.4 nm to approximately 20 nm. In one embodiment the thermally resistive layer 214 can be deposited using PVD, CVD, and/or ALD.

[0040] In an embodiment the thermally resistive layer 214 can include a conductive metal oxide layer; for example, a zinc oxide layer, an aluminum oxide layer, a tin oxide layer, and/or an indium tin oxide (ITO) layer. In another embodiment the thermally resistive layer 214 can further include a metal layer including an aluminum, silver, copper, gold, zinc, tin and/or tungsten layer.

[0041] In one embodiment the top electrode 216 can be deposited onto the thermally resistive layer 214. In one embodiment the device 200 can further include a top electrode 216. In another embodiment the top electrode 216 can include copper, tungsten, titanium nitrate, platinum or any suitable layer.

[0042] In one embodiment the active layer 21 1(which can include a first magnetic layer 206, a tunneling layer 208, and a second magnetic layer 210) can include a switching mechanism that can serve to permit the memory functionality of the device 200. For example, the switching mechanism can operate as follows: the first magnetic layer 206 can have a perpendicular anisotropy vector that points substantially in the positive z direction with respect to the z-axis of the device. Similarly, the second magnetic layer 210 can also have a perpendicular anisotropy vector pointing in the positive z direction with respect to the z-axis of the device. Under forward bias, current can pass through the active layer. In one embodiment, forward bias can refer to the application of a positive voltage to both the bottom electrode and/or the top electrode, while grounding one of the electrodes, for example, the bottom electrode 202. In particular, the tunneling layer 208 which can be a relatively thin layer can pass current. This passage of current by the active layer 211 can be considered synonymous to a low resistant state in the device.

[0043] At higher current levels and/or higher temperatures in the device 200, the first magnetic layer 206 (also referred to as the reference layer 206) can continue to maintain its perpendicular anisotropy magnetic vector in the positive z direction with respect to the z-axis of the device. However, at the higher current levels and/or higher temperatures in the device 200, the second magnetic layer 210 (also referred to as the free layer 210) can flip its magnetic anisotropy vector to the negative z direction with respect to the z-axis of the device. This can then cause the device 200 to pass into a high resistant state leading to the cut-off of further current passage through the active layer 211 of the device 200.

[0044] As such, the switching mechanism of the device 200 can be due to both the magnitude of the current passing through the active layer and the operational temperature of the device 200. As such, the thermally resistive layer (for example, the thermally resistive layer 214) can assist the switching process of the device 200. In one embodiment, the thermally resistive layer 214 can thereby act to reduce the temperature at which the active layer can switch from a low resistance to a high resistance and/or vice versa. As shown in FIG. 200, in one embodiment, the thermally resistive layer 214 can be positioned below the top electrode 216 and above the active layer 211. In another embodiment thermally resistive layer 214 can be, additionally or alternatively, placed above the top electrode 216.

[0045] FIG. 3 shows another example cross-sectional view of a pMTJ device 300 in accordance with example embodiments of the disclosure. In particular, the structure of device 300 is substantially the same as that described in connection with FIG. 2, that is, for example, the device 300 includes a bottom electrode 302, and a first buffer layer 306 (also referred to as a SAF layer). The device 300 further includes an active layer 31 1 that comprises a first magnetic layer 308 (also referred to as a reference layer). The device 300 also includes a tunneling layer 310 (which can further comprise a magnesium oxide layer) and a second magnetic layer 312 (which can further comprise a free layer). The device 300 can further include a second buffer layer 314 that can also be referred to as a cap layer 314.

[0046] However as can be seen in FIG. 3 the thermally resistive layer 304 and a second thermally resistive layer 316 can further be included in the device. In an embodiment, the first thermally resistive layer 304 can be positioned between the bottom electrode 302 and the active layer 311. In another embodiment the second thermally resistive layer 316 can be positioned between the top electrode 318 and the active lay er 311.

[0047] Further, although not shown in FIG. 3, the first thermally resistive layer 304 can be positioned between the bottom electrode 302 and the substrate 301. Additionally or alternatively, the thermally resistive layer 304 could be positioned above the first buffer layer 306 and/or between the first buffer layer 306 and the active layer 31 1. Additionally or alternatively, the second thermally resistive layer 316 can be positioned above the top electrode 318 and/or between the second buffer layer 314 and the active layer 311.

[0048] In all of these embodiments and other similar variations, the thermally resistive layer can serve to confine the heat in the active layer. Therefore the presence of thermally resistive layers (for example thermally resistive layers 304 and/or thermally resistive layer 316) throughout the device in proximity to both the bottom electrode and/or the top electrode can serve to further confine the heat in the active layer 311 , and thereby serve to reduce the switching power of the device 300.

[0049] FIG. 4 shows a diagram of an example cross-sectional view of a pMTJ device 400 in accordance with one or more example embodiments of the disclosure. In one embodiment, FIG. 4 also shows a device that is substantially similar to FIG. 2 and FIG. 3 and associated description. In particular FIG. 4 shows a device that includes a substrate 401, a bottom electrode 402, a first buffer layer 406 (also referred to as a SAF layer), an active layer 411 that includes a first magnetic layer 408 (also referred to as a reference layer), a tunneling layer 410 that can include a magnesium oxide material, and a second magnetic layer 412 (also referred to as a free layer). Optionally, the device 400 can further include a second buffer layer, also known as a capping layer 414. The device 400 further shows a top electrode 416.

[0050] In one embodiment, as shown in diagram 400, the thermally resistive layer 404 is shown to be positioned between the bottom electrode 402 and the first buffer layer 406. Additionally or alternatively, a thermally resistive layer 404 could be positioned below the bottom electrode that is in between the bottom electrode 402 and the substrate 401. Additionally or alternatively the thermally resistive layer 404 could be positioned between the first buffer layer 406 and the active layer 411.

[0051] FIG. 5 shows an example cross-sectional view of a portion of a pMTJ device 500 in accordance with one or more example embodiments of the disclosure. In particular FIG. 5 shows the device 500, which may be representative of a composite electrode for use in connection with a pMTJ device; for example, the pMTJ devices shown and described in connection with FIGs. 1-4. In one embodiment, the portion of the pMTJ device 500 can include a top electrode material 502 and/or a bottom electrode material 502. The portion of the pMTJ device 500 can further include a thermally resistive layer 504 that can be deposited on the top electrode material 502 and/or a bottom electrode material 502. Similarly, a top electrode material 506 and/or a bottom electrode material 506 can be deposited on the thermally resistive layer 504. Further, a thermally resistive layer 508 can be deposited on the top electrode material 506 and/or the bottom electrode material 506 and so on. In this way, the multi-layer structure represented by the portion of the device 500 can include a succession of electrode material followed by thermally resistive material in a multi-layer stack. In another embodiment, in such a configuration, the thermally resistive material can be effectively integrated into the electrodes of the device. As such, the composite electrodes can better serve to confine the heat generated by an active layer of a device; for example, the active layers shown and described in connection with FIGs. 1-4.

[0052] FIG. 6 shows a diagram that represents a cross-sectional view of a first device 603 with one reference layer, a second device 605 with one reference layer and a thermally resistive layer 616, and a plot 607 of the temperature in the various layers of the devices 603 and 605 (temperature 622 on the x axis versus the position 624 in the device on the y axis) in accordance with one or more example embodiments of the disclosure. In particular, the first device 603 does not include a thermally resistive layer, but can have a structure as follows: a substrate 601, a bottom electrode 602, a first buffer layer 604, an active layer 611 (the active layer comprising a first magnetic layer 606, a tunneling layer 608, a second magnetic layer 610), a second buffer layer 612, and a top electrode 614. The details of the respective layers shown in this device 603 can be found variously described in connection with FIGs. 1 -4 of this disclosure.

[0053] Further shown in FIG. 6 is a second device 605 having one thermally resistive layer 616. In particular, the device 605 includes a substrate 601, a bottom electrode 602, a first buffer layer 604, an active layer 61 1 (the active layer comprising a first magnetic layer 606, a tunneling layer 608, a second magnetic layer 610), a second buffer layer 612, and a top electrode 614. As mentioned, the device 605 further includes a thermally resistive layer 616. In various embodiments the thermally resistive layer 616 can comprise a multi-layer structure made of interlayers of metals and non-metal layers (for example, metal oxide layers and/or insulator layers), as shown and described, for example, in connection with the multilayer 11 1 of FIG. 1.

[0054] In one embodiment the curve 630 in plot 607 represents the temperature 622 versus position 624 (with reference to the z-axis) in a first device (not shown), where the first device is similar to device 603, where the device has no thermally resistive layers. As shown in curve 630, the maximum temperature achieved in the active layer 61 1 of the device not having any thermally resistive layer is approximately 420 degrees centigrade.

[0055] In another embodiment, the second curve 632 represents a device 605 having one thermally resistive layer 616, though otherwise being similar to device 603. In another embodiment, the curve 632 has a maximum internal temperature achieved in the active layer of approximately 525 to approximately 530 degrees centigrade. [0056] In one embodiment, the curve 634 shows that the temperature achieved in a device similar to device 605 but having a material choice for the thermally resistive layer 616 that has a greater difference in the Debye temperature between the thermally resistive layer 616 and the neighboring first magnetic layer 606 and/or first buffer layer 604. In one embodiment, the device represented by curve 634 can achieve a maximum temperature of approximately 580 degrees Centigrade. Accordingly, plot 607 shows that the incorporation of thermally resistive layers in a pMTJ device can permit a higher internal temperature to be achieved in the active layer of the pMTJ device.

[0057] FIG. 7 shows an example processing flow diagram 700 that can be used to fabricate an example pMTJ device, in accordance with one or more example embodiments of the disclosure. In particular, the processing flow diagram 700 can be used to fabricate a device similar, but not necessarily identical to, the device shown and described in connection with FIG. 3 of the disclosure.

[0058] In block 702, a substrate can be provided. In one embodiment, the substrate can include silicon, semiconductor, glass, or other suitable material. In an embodiment the substrate can serve as a heat sink for removing the heat generated in the device during operation.

[0059] In block 704, a bottom electrode can be deposited on the substrate. In an embodiment, the bottom electrode can include copper, tungsten, titanium nitride, and/or platinum material. In another embodiment the bottom electrode can have a thickness of approximately 0.4 nm to approximately 1 mm, with example thicknesses of approximately 0.4 nm to approximately 20 nm. In another embodiment the bottom electrode can be deposited using PVD, CVD, and/or ALD.

[0060] In block 706, a first thermally resistive layer can be optionally deposited on the bottom electrode. In one embodiment, the deposition of the first thermally resistive layer is optional in that it can be deposited in a layer step (for example, step 718) of the processing sequence (or not at all), depending on the desired application and/or use case.

[0061] In one embodiment, the first thermally resistive layer can comprise a metal oxide material. For example, the first thermally resistive layer can comprise an indium tin oxide (ITO), an indium zinc oxide (IZO), a zinc oxide (ZnO), and/or any other suitable material. In one embodiment the first thermally resistive layer can comprise a multi-layer structure that includes a first conductive metal oxide layer followed by a metal layer, followed by another conductive metal oxide layer and another metal layer and so on. In various embodiments the thickness of the first thermally resistive layer can be approximately 0.4 nm to approximately 20 nm. In an embodiment the first thermally resistive layer can be deposited using PVD, CVD, and/or ALD. [0062] In block 708, a first buffer layer can optionally be deposited on the first thermally resistive layer in the case where a first thermally resistive layer exists in the structure formed at this point in the process. Alternatively or additionally, a first buffer layer can optionally be deposited on the bottom electrode, in the case where the first thermally resistive layer does not exist at this point in the process. In an embodiment, the first buffer layer can alternatively be referred to as a synthetic antiferromagnetic (SAF) layer. In another embodiment the first buffer layer can have a thickness of approximately 0.4 nm to approximately 20 nm. In an embodiment the first buffer layer can be deposited using PVD, CVD, and/or ALD. [0063] In block 710, a first magnetic layer can be deposited on the first buffer layer in the case in the case where the first buffer layer exists at this point in the process. Alternatively or additionally, a first magnetic layer can be deposited on the first thermally resistive layer in the case that the first thermally resistive layer exists at this point in the process. Alternatively or additionally, a first magnetic layer can be deposited on a bottom electrode in case a first buffer layer and the first thermally resistive layer do not exist at this point in the process.

[0064] In an embodiment the first magnetic layer can additionally or alternatively be referred to as a reference layer. In an embodiment the first magnetic layer can include a metal or metal alloy; for example, a cobalt iron and/or boron based metal or metal alloy material. In an embodiment the first magnetic layer can have a thickness of approximately 0.4 nm to approximately 20 nm. In an embodiment the first magnetic layer can be deposited using PVD, CVD, and/or ALD.

[0065] In block 712, a tunneling layer can be deposited on the first magnetic layer. In an embodiment the tunneling layer can include a metal oxide layer; for example, a magnesium oxide layer. In another embodiment the tunneling layer can have a thickness of approximately 0.4 nm to approximately 20 nm. In an embodiment the tunneling layer can be deposited using PVD, CVD, and/or ALD.

[0066] In block 714, a second magnetic layer can be deposited on the tunneling layer. In one embodiment, the second magnetic layer can include a metal or metal alloy; for example, a cobalt iron and/or boron based metal or metal alloy material. In an embodiment the second magnetic layer can have a thickness of approximately 0.4 nm to approximately 20 nm. In an embodiment the second magnetic layer can be deposited using PVD, CVD, and/or ALD.

[0067] In block 716, a second buffer layer can optionally be deposited onto the second magnetic layer. In an embodiment, the second buffer layer can alternatively be referred to as a synthetic antiferromagnetic (SAF) layer. In another embodiment the second buffer layer can have a thickness of approximately 0.4 nm to approximately 20 nm. In an embodiment the second buffer layer can be deposited using PVD, CVD, and/or ALD.

[0068] In block 718, a second thermally resistive layer can optionally be deposited in the device; for example, a second thermally resistive layer can optionally be deposited on the second buffer layer in case the second buffer layer exists at this point in the process. Alternatively or additionally, a second thermally resistive layer can optionally be deposited on a second magnetic layer in case the second buffer layer does not exist at this point in the process.

[0069] In one embodiment, the second thermally resistive layer can comprise a metal oxide material. For example, the thermally resistive layer can comprise an indium tin oxide (ITO), an indium zinc oxide (IZO), a zinc oxide (ZnO), and/or any other suitable material. In one embodiment the second thermally resistive layer can comprise a multilayer structure that includes a first conductive metal oxide layer followed by a metal layer, followed by another conductive metal oxide layer and another metal layer and so on. In various embodiments the total thickness of the second thermally resistive layer can be approximately 0.4 nm to approximately 20 nm. In an embodiment the second thermally resistive layer can be deposited using PVD, CVD, and/or ALD.

[0070] In block 720 a top electrode can be deposited on the second buffer layer 716 and/or on the second thermally resistive layer in case that they exist and/or on the second magnetic layer in case the second buffer layer and/or the thermally resistive layer do not exist in the device. In an embodiment, the top electrode can include copper, tungsten, titanium nitride, and/or platinum material. In another embodiment the top electrode can have a thickness of approximately 0.4 nm to approximately 1 mm. In another embodiment the bottom electrode can be deposited using PVD, CVD, and/or ALD. [0071] FIG. 8 depicts an example of a system 800 according to one or more embodiments of the disclosure. In one embodiment, the systems, methods, and apparatus disclosed herein, including for example, the pMTJ devices described herein can be used in connection with system 800. For example, the pMTJ devices described herein can be used in connection with system 800 to improve the performance of system 800 or to provide memory capabilities to one or more devices of system 800. In one embodiment, system 800 includes, but is not limited to, a desktop computer, a laptop computer, a netbook, a tablet, a notebook computer, a personal digital assistant (PDA), a server, a workstation, a cellular telephone, a mobile computing device, a smart phone, an Internet appliance or any other type of computing device. In some embodiments, system 800 can include a system on a chip (SOC) system.

[0072] In one embodiment, system 800 includes multiple processors including processor 810 and processor N 805, where processor N 805 has logic similar or identical to the logic of processor 810. In one embodiment, processor 810 has one or more processing cores (represented here by processing core 1 812 and processing core N 812N, where 812N represents the Nth processor core inside processor 810, where N is a positive integer). More processing cores can be present (but not depicted in the diagram of FIG. 8). In some embodiments, processing core 812 includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions, a combination thereof, or the like. In some embodiments, processor 810 has a cache memory 816 to cache instructions and/or data for system 800. Cache memory 816 may be organized into a hierarchical structure including one or more levels of cache memory.

[0073] In some embodiments, processor 810 includes a memory controller (MC) 814, which is configured to perform functions that enable the processor 810 to access and communicate with memory 830 that includes a volatile memory 832 and/or a non-volatile memory 834. In some embodiments, processor 810 can be coupled with memory 830 and chipset 820. Processor 810 may also be coupled to a wireless antenna 878 to communicate with any device configured to transmit and/or receive wireless signals. In one embodiment, the wireless antenna 878 operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol. [0074] In some embodiments, volatile memory 832 includes, but is not limited to, Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM), and/or any other type of random access memory device. Non-volatile memory 834 includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device.

[0075] Memory device 830 stores information and instructions to be executed by processor 810. In one embodiment, memory 830 may also store temporary variables or other intermediate information while processor 810 is executing instructions. In the illustrated embodiment, chipset 820 connects with processor 810 via Point-to-Point (PtP or P-P) interface 817 and P-P interface 822. Chipset 820 enables processor 810 to connect to other elements in system 800. In some embodiments of the disclosure, P-P interface 817 and P-P interface 822 can operate in accordance with a PtP communication protocol, such as the Intel® QuickPath Interconnect (QPI) or the like. In other embodiments, a different interconnect may be used.

[0076] In some embodiments, chipset 820 can be configured to communicate with processor 810, the processor N 805, display device 840, and other devices 872, 876, 874, 860, 862, 864, 866, 877, etc. Chipset 820 may also be coupled to the wireless antenna 878 to communicate with any device configured to transmit and/or receive wireless signals.

[0077] Chipset 820 connects to display device 840 via interface 826. Display 840 may be, for example, a liquid crystal display (LCD), a plasma display, cathode ray tube (CRT) display, or any other form of visual display device. In some embodiments of the disclosure, processor 810 and chipset 820 are integrated into a single SOC. In addition, chipset 820 connects to bus 850 and/or bus 855 that interconnect various elements 874, 860, 862, 864, and 866. Bus 850 and bus 855 may be interconnected via a bus bridge 872. In one embodiment, chipset 820 couples with a non-volatile memory 860, a mass storage device(s) 862, a keyboard/mouse 864, and a network interface 866 via interface 824 and/or 804, smart TV 876, consumer electronics 877, etc. [0078] In one embodiment, mass storage device(s) 862 can include, but not be limited to, a solid state drive, a hard disk drive, a universal serial bus flash memory drive, or any other form of computer data storage medium. In one embodiment, network interface 866 is implemented by any type of well-known network interface standard including, but not limited to, an Ethernet interface, a universal serial bus (USB) interface, a Peripheral Component Interconnect (PCI) Express interface, a wireless interface and/or any other suitable type of interface. In one embodiment, the wireless interface operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

[0079] While the modules shown in FIG. 8 are depicted as separate blocks within the system 800, the functions performed by some of these blocks may be integrated within a single semiconductor circuit or may be implemented using two or more separate integrated circuits. For example, although cache memory 816 is depicted as a separate block within processor 810, cache memory 816 or selected elements thereof can be incorporated into processor core 812. [0080] It is noted that the system 800 described herein may be any suitable type of microelectronics packaging and configurations thereof, including, for example, system in a package (SiP), system on a package (SOP), package on package (PoP), interposer package, 3D stacked package, etc. Further, any suitable type of microelectronic components may be provided in the semiconductor packages, as described herein. For example, microcontrollers, microprocessors, baseband processors, digital signal processors, memory dies, field gate arrays, logic gate dies, passive component dies, MEMSs, surface mount devices, application specific integrated circuits, baseband processors, amplifiers, filters, combinations thereof, or the like may be packaged in the semiconductor packages, as disclosed herein. The semiconductor packages (for example, the semiconductor packages described in connection with any of FIGS. 1-7), as disclosed herein, may be provided in any variety of electronic device including consumer, industrial, military, communications, infrastructural, and/or other electronic devices.

[0081] In various embodiments, the devices, as described herein, may be used in connection with one or more processors. The one or more processors may include, without limitation, a central processing unit (CPU), a digital signal processor(s) (DSP), a reduced instruction set computer (RISC), a complex instruction set computer (CISC), a microprocessor, a microcontroller, a field programmable gate array (FPGA), or any combination thereof. The processors may also include one or more application specific integrated circuits (ASICs) or application specific standard products (ASSPs) for handling specific data processing functions or tasks. In certain embodiments, the processors may be based on an Intel® Architecture system and the one or more processors and any chipset included in an electronic device may be from a family of Intel® processors and chipsets, such as the Intel® Atom® processor(s) family or Intel-64 processors (for example, Sandy Bridge®, Ivy Bridge®, Haswell®, Broadwell®, Skylake®, etc.).

[0082] Additionally or alternatively, the devices, as described herein, may be used in connection with one or more additional memory chips. The memory may include one or more volatile and/or non-volatile memory devices including, but not limited to, magnetic storage devices, read-only memory (ROM), random access memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), double data rate (DDR) SDRAM (DDR-SDRAM), RAM-BUS DRAM (RDRAM), flash memory devices, electrically erasable programmable read-only memory (EEPROM), non-volatile RAM (NVRAM), universal serial bus (USB) removable memory, or combinations thereof.

[0083] In example embodiments, the electronic device in which the disclosed devices are used and/or provided may be a computing device. Such a computing device may house one or more boards on which the devices may be disposed. The board may include a number of components including, but not limited to, a processor and/or at least one communication chip. The processor may be physically and electrically connected to the board through, for example, electrical connections of the devices. The computing device may further include a plurality of communication chips. For instance, a first communication chip may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, and others. In various example embodiments, the computing device may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, combinations thereof, or the like. In further example embodiments, the computing device may be any other electronic device that processes data.

[0084] According to example embodiments of the disclosure, there may be a perpendicular magnetic tunnel junction (pMTJ) device. The device may comprise: a substrate; a first magnetic layer having a first magnetic moment; a second magnetic layer having a second magnetic moment oriented parallel to the first magnetic moment of the first magnetic layer; a first electrode configured to inject charge carriers into the first magnetic layer; a tunneling layer through which the charge carriers are transported from the first magnetic layer to the second magnetic layer; a second electrode that collects the charge carriers from the second magnetic layer; and a thermally resistive layer between an active layer comprising the first magnetic layer, the second magnetic layer, and the tunneling layer, and either the first electrode or the second electrode, wherein the thermally resistive layer confines heat generated by the active layer during the transport of the charge carriers.

[0085] Implementation may include one or more of the following features. The device may have a thermally resistive layer positioned between the first electrode and the active layer. A second thermally resistive layer may be positioned between the substrate and first electrode. A third thermally resistive layer may be deposited on the second electrode and a fourth thermally resistive layer may be positioned between the active layer and second electrode. The thermally resistive layer may include a conductive metal oxide where the conductive metal oxide may further include indium tin oxide (ITO), indium zinc oxide (IZO), amorphous carbon, or indium gallium zinc oxide (IGZO). The thermally resistive layer may comprise a multilayer, which may comprise a first metal oxide layer and a first metal layer. The device may further comprise a first buffer layer positioned between the first electrode and the active layer, which may be comprised of a synthetic antiferromagnetic (SAF) layer. A second buffer layer may be positioned between the active layer and the second electrode.

[0086] According to example embodiments of the disclosure, there may be a method for fabricating a perpendicular magnetic tunnel junction (pMTJ) device. The method may comprise: providing a substrate; depositing, on the substrate, a first electrode configured to inject charge carriers into a first magnetic layer of an active layer; depositing the first magnetic layer, the first magnetic layer having a first magnetic moment; depositing, on the first magnetic layer, a tunneling layer of the active layer configured to transport the charge carriers from the first magnetic layer to a second magnetic layer; depositing the second magnetic layer of the active layer on the tunneling layer, the second magnetic layer having a second magnetic moment oriented parallel or antiparallel to the first magnetic moment of the first magnetic layer; depositing a second electrode configured to collect the charge carriers from the second magnetic layer; and depositing a thermally resistive layer between an active layer and either the first electrode or the second electrode, wherein the thermally resistive layer confines heat generated by the active layer during the transport of the charge carriers. [0087] Implementation may include one or more of the following features. The method of depositing the thermally resistive layer may further comprise depositing a first thermally resistive layer between the first electrode and the active layer. A second thermally resistive layer may be deposited between the substrate and the first electrode. A third thermally resistive layer may be deposited on the second electrode and a fourth thermally resistive layer may be deposited between the active layer and the second electrode. Depositing the thermally resistive layer may further comprise depositing a conductive metal oxide, the metal oxide may further include indium tin oxide (ITO), indium zinc oxide (IZO), amorphous carbon, or indium gallium zinc oxide (IGZO). A first buffer layer may be deposited between the first electrode and the active layer. The first buffer layer may further comprise a synthetic antiferromagnetic (SAF) layer. Depositing the thermally resistive layer may further comprise depositing a thermally resistive layer comprising a multilayer, the multilayer further comprising a first metal oxide layer and a first metal layer. The method of depositing the thermally resistive layer may further comprise a physical vapor deposition technique, a chemical vapor deposition technique, or a plasma- enhanced chemical vapor deposition technique. The method of depositing the tunnel layer may further comprise a physical vapor deposition technique, a chemical vapor deposition technique, or a plasma-enhanced chemical vapor deposition technique.

[0088] According to example embodiments of the disclosure, there may be an electronic device. The electronic device may comprise a perpendicular magnetic tunnel junction (pMTJ) device, which may further comprise: a substrate; a first magnetic layer having a first magnetic moment; a second magnetic layer having a second magnetic moment oriented parallel to the first magnetic moment of the first magnetic layer; a first electrode configured to inject charge carriers into the first magnetic layer; a tunneling layer through which the charge carriers are transported from the first magnetic layer to the second magnetic layer; a second electrode that collects the charge carriers from the second magnetic layer; and a thermally resistive layer between an active layer comprising the first magnetic layer, the second magnetic layer, and the tunneling layer, and either the first electrode or the second electrode, wherein the thermally resistive layer confines heat generated by the active layer during the transport of the charge carriers.

[0089] Implementation may include one or more of the following features. The pMTJ of the electronic device may have a thermally resistive layer positioned between the first electrode and the active layer. A second thermally resistive layer may be positioned between the substrate and first electrode. A third thermally resistive layer may be deposited on the second electrode and a fourth thermally resistive layer may be positioned between the active layer and second electrode. The thermally resistive layer may include a conductive metal oxide where the conductive metal oxide may further include indium tin oxide (ITO), indium zinc oxide (IZO), amorphous carbon, or indium gallium zinc oxide (IGZO). The thermally resistive layer may comprise a multilayer, which may comprise a first metal oxide layer and a first metal layer. The pMTJ of the electronic device may further comprise a first buffer layer positioned between the first electrode and the active layer, which may be comprised of a synthetic antiferromagnetic (SAF) layer. A second buffer layer may be positioned between the active layer and the second electrode.

[0090] Various features, aspects, and embodiments have been described herein. The features, aspects, and embodiments are susceptible to combination with one another as well as to variation and modification, as will be understood by those having skill in the art. The present disclosure should, therefore, be considered to encompass such combinations, variations, and modifications.

[0091] The terms and expressions which have been employed herein are used as terms of description and not of limitation, and there is no intention, in the use of such terms and expressions, of excluding any equivalents of the features shown and described (or portions thereof), and it is recognized that various modifications are possible within the scope of the claims. Other modifications, variations, and alternatives are also possible. Accordingly, the claims are intended to cover all such equivalents. [0092] While the disclosure includes various embodiments, including at least a best mode, it is to be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the foregoing description. Accordingly, the disclosure is intended to embrace all such alternatives, modifications, and variations, which fall within the scope of the included claims. All matters disclosed herein or shown in the accompanying drawings are to be interpreted in an illustrative and non-limiting sense.

[0093] This written description uses examples to disclose certain embodiments of the disclosure, including the best mode, and also to enable any person skilled in the art to practice certain embodiments of the disclosure, including making and using any apparatus, devices or systems and performing any incorporated methods and processes. The patentable scope of certain embodiments of the invention is defined in the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal language of the claims.

Claims

CLAIMS The claimed invention is:

1. A perpendicular magnetic tunnel junction (pMTJ) device, the device comprising: a substrate;

an active layer, the active layer comprising:

a first magnetic layer having a first magnetic moment,

a second magnetic layer having a second magnetic moment oriented parallel to the first magnetic moment of the first magnetic layer, and

a tunneling layer through which the charge carriers are transported from the first magnetic layer to the second magnetic layer;

a first electrode configured to inject charge carriers into the first magnetic layer; a second electrode configured to collect the charge carriers from the second magnetic layer; and

a thermally resistive layer between the active layer and one of the first electrode or the second electrode, wherein the thermally resistive layer is configured to confine heat generated by the active layer during the transport of the charge carriers.

2. The device of claim 1, wherein the thermally resistive layer is positioned between the first electrode and the active layer.

3. The device of claim 1 , further comprising a second thermally resistive layer positioned between the substrate and the first electrode.

4. The device of claim 1 , further comprising a third thermally resistive layer deposited on the second electrode.

5. The device of claim 1 , further comprising a fourth thermally resistive layer positioned between the active layer and the second electrode.

6. The device of claim 1, wherein the thermally resistive layer include a conductive metal oxide.

7. The device of claim 6, wherein the conductive metal oxide includes indium tin oxide (ITO), indium zinc oxide (IZO), amorphous carbon, or indium gallium zinc oxide (IGZO).

8. The device of claim 1, wherein the thermally resistive layer comprises a multilayer.

9. The device of claim 8, wherein the multilayer comprises a first metal oxide layer and a first metal layer.

10. The device of claim 1, further comprising a first buffer layer positioned between the first electrode and the active layer.

11. The device of claim 10, wherein the first buffer layer comprises a synthetic antiferromagnetic (SAF) layer.

12. The device of claim 1, further comprising a second buffer layer positioned between the active layer and the second electrode.

13. A method for fabricating a perpendicular magnetic tunnel junction (pMTJ) device, the method comprising:

providing a substrate;

depositing, on the substrate, a first electrode configured to inject charge carriers into a first magnetic layer of an active layer;

depositing the first magnetic layer, the first magnetic layer having a first magnetic moment;

depositing, on the first magnetic layer, a tunneling layer of the active layer configured to transport the charge carriers from the first magnetic layer to a second magnetic layer;

depositing the second magnetic layer of the active layer on the tunneling layer, the second magnetic layer; depositing a second electrode configured to collect the charge carriers from the second magnetic layer; and

depositing a thermally resistive layer between an active layer and either the first electrode or the second electrode, wherein the thermally resistive layer is configured to confine heat generated by the active layer during the transport of the charge carriers.

14. The method of claim 13, wherein depositing the thermally resistive layer further comprises depositing a first thermally resistive layer between the first electrode and the active layer.

15. The method of claim 13, wherein depositing the thermally resistive layer further comprises depositing a second thermally resistive layer between the substrate and the first electrode.

16. The method of claim 13, wherein depositing the thermally resistive layer further comprises depositing a third thermally resistive layer on the second electrode.

17. The method of claim 13, wherein depositing the thermally resistive layer further comprises depositing a fourth thermally resistive layer between the active layer and the second electrode.

18. The method of claim 13, wherein depositing the thermally resistive layer further comprises depositing a conductive metal oxide.

19. The method of claim 18, wherein the conductive metal oxide includes indium tin oxide (ITO), indium zinc oxide (IZO), amorphous carbon, or indium gallium zinc oxide (IGZO).

20. The method of claim 13, further comprising depositing a first buffer layer positioned between the first electrode and the active layer.

21. The method of claim 20, wherein the first buffer layer comprises a synthetic antiferromagnetic (SAF) layer.

22. The method of claim 13, wherein depositing the thermally resistive layer further comprises depositing a thermally resistive layer comprising a multilayer, the multilayer further comprising a first metal oxide layer and a first metal layer.

23. The method of claim 13, wherein depositing the thermally resistive layer further comprises a physical vapor deposition technique, a chemical vapor deposition technique, or a plasma-enhanced chemical vapor deposition technique.

24. The method of claim 13, wherein depositing the first magnetic layer or the second magnetic layer further comprises a physical vapor deposition technique, a chemical vapor deposition technique, or a plasma-enhanced chemical vapor deposition technique.

25. The method of claim 13, wherein depositing the tunneling layer further comprises a physical vapor deposition technique, a chemical vapor deposition technique, or a plasma- enhanced chemical vapor deposition technique.