WO2018120555A1 - 一种相位插值器电路及其提升线性度的方法 - Google Patents

一种相位插值器电路及其提升线性度的方法 Download PDF

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WO2018120555A1
WO2018120555A1 PCT/CN2017/082609 CN2017082609W WO2018120555A1 WO 2018120555 A1 WO2018120555 A1 WO 2018120555A1 CN 2017082609 W CN2017082609 W CN 2017082609W WO 2018120555 A1 WO2018120555 A1 WO 2018120555A1
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port
circuit
switch tube
phase interpolator
signal input
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PCT/CN2017/082609
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English (en)
French (fr)
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易生涛
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深圳市中兴微电子技术有限公司
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Publication of WO2018120555A1 publication Critical patent/WO2018120555A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals

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  • the present invention relates to a phase interpolator circuit, and more particularly to a phase interpolator circuit and a method thereof for improving linearity.
  • phase interpolator (PI) circuit is widely used in high-speed digital-analog hybrid circuits (such as phase-locked loop (PLL) circuits, clock data recovery (CDR) circuits, and the like.
  • PLL phase-locked loop
  • CDR clock data recovery
  • Integral nonlinearity (INL, Integral Nonlinearity) and differential nonlinearity (DNL) of the output phase of the ordinary phase interpolator circuit tend to be greater than 1 LSB (Least Significant Bit), affecting the phase interpolator circuit The normal operation of the latter circuit. How to reduce the INL and DNL of the output phase of the phase interpolator circuit is an urgent problem to be solved.
  • an embodiment of the present invention provides a phase interpolator circuit and a method for improving linearity thereof.
  • a phase interpolator circuit provided by an embodiment of the present invention includes N phase interpolator units, N ⁇ 2; the phase interpolator unit includes: a differential switching transistor circuit, a current control circuit, and a bias current circuit, wherein
  • the differential switch tube circuit includes a first switch tube and a second switch tube; the first switch tube is connected to the clock signal input end through its first port, and is connected to the negative signal output end through its second port. And connected to the current control circuit through its own third port; the second switch tube is connected to the clock signal input end through its first port, and is connected to the positive signal output end through its second port, and Connected to the current control circuit through its third port;
  • the current control circuit is connected to the control signal input end through its first port, connected to the differential switch tube circuit through its second port, and connected to the bias current circuit through its third port;
  • the bias current circuit is connected to the reference signal input terminal through its first port, connected to the current control circuit through its second port, and connected to the ground through its own third port.
  • the phase interpolator unit includes four sets of differential switch tube circuits
  • a first port of the first switch tube of the first group of differential switch transistors is connected to the first clock signal input end, and a first port of the second switch tube is connected to the second clock signal input end;
  • the first port of the first switch tube of the second group of differential switch transistors is connected to the third clock signal input end, and the first port of the second switch tube is connected to the fourth clock signal input end;
  • the first port of the first switch tube of the third group of differential switch transistors is connected to the second clock signal input end, and the first port of the second switch tube is connected to the first clock signal input end;
  • the first port of the first switch tube of the fourth group of differential switch transistors is connected to the fourth clock signal input end, and the first port of the second switch tube is connected to the third clock signal input end.
  • the phase interpolator unit includes four sets of current control circuits
  • a first port of the first set of current control circuits is coupled to the first control signal input
  • a first port of the second group of current control circuits is coupled to the second control signal input terminal
  • the first port of the third group of current control circuits is connected to the third control signal input end;
  • the first port of the fourth group of current control circuits is coupled to the fourth control signal input.
  • the negative signal output ends respectively connected to the four sets of differential switch tube circuits are connected together, and the positive signal output ends respectively connected to the four sets of differential switch tube circuits are connected together.
  • the current control circuit is connected to the differential switch tube circuit through its second port, specifically:
  • the current control circuit is respectively connected to the third port of the first switch tube and the third port of the second switch tube in the differential switch tube circuit through its second port.
  • the first switch tube, the second switch tube, the current control circuit, and the bias current circuit are all N-type metal-oxide-semiconductor field effects (NMOS, N-Metal) -Oxide-Semiconductor) tube.
  • NMOS N-type metal-oxide-semiconductor field effects
  • the phase interpolator circuit further includes: a first resistor and a second resistor, wherein
  • the first end of the first resistor is connected to the power source, and the second end is connected to the negative signal output end;
  • the first end of the second resistor is connected to the power source, and the second end is connected to the positive signal output end.
  • phase interpolator circuit When the phase adjustment is performed by the phase interpolator circuit, the weights of the different quadrants are adjusted, wherein the phase interpolator circuit comprises N phase interpolator units, N ⁇ 2;
  • the phase is adjusted by N phase interpolator units in the phase interpolator circuit.
  • the phase interpolator unit includes: a differential switch transistor circuit, a current control circuit, and a bias current circuit, wherein
  • the differential switch tube circuit includes a first switch tube and a second switch tube; the first switch tube Connected to the clock signal input terminal through its first port, connected to the negative signal output terminal through its second port, and connected to the current control circuit through its own third port; the second switch tube passes The first port of the self is connected to the clock signal input end, is connected to the positive signal output end through its second port, and is connected to the current control circuit through its third port;
  • the current control circuit is connected to the control signal input end through its first port, connected to the differential switch tube circuit through its second port, and connected to the bias current circuit through its third port;
  • the bias current circuit is connected to the reference signal input terminal through its first port, connected to the current control circuit through its second port, and connected to the ground through its own third port.
  • the phase interpolator circuit includes N phase interpolator units, N ⁇ 2; the phase interpolator unit includes: a differential switch transistor circuit, a current control circuit, and a bias current circuit, wherein
  • the differential switching transistor circuit includes a first switching transistor and a second switching transistor; the first switching transistor is connected to the clock signal input terminal through its first port, and is connected to the negative signal output terminal through its second port, and Connected to the current control circuit through its own third port;
  • the second switch tube is connected to the clock signal input terminal through its first port, and is connected to the positive signal output terminal through its second port, and passes through The third port of the self is connected to the current control circuit;
  • the current control circuit is connected to the control signal input terminal through its first port, and is connected to the differential switch transistor circuit through its second port, and passes through itself a third port is coupled to the bias current circuit;
  • the bias current circuit passes through its first port and the reference signal input Then, by its second port to the current control circuit, and is connected through its own third port and
  • the independent phase interpolator unit has small parasitics, the current can be quickly stabilized. Increase each time or By reducing an independent phase interpolator unit, the change in current is linear and the phase change is linear.
  • the number of independent phase interpolator units connected in parallel is increased or decreased. In fact, there is no difference between the phase jumps in the quadrant. In this way, the linearity of the phase interpolator is greatly improved, and a smooth change in the phase of the output signal is ensured.
  • Figure 1 is a circuit diagram of a conventional phase interpolator
  • FIG. 2 is a schematic structural diagram of a phase interpolator circuit according to an embodiment of the present invention.
  • FIG. 3 is a circuit diagram of a PI CELL according to an embodiment of the present invention.
  • FIG. 4 is a general diagram of a PI circuit according to an embodiment of the present invention.
  • FIG. 5 is a schematic flow chart of a method for improving linearity of a phase interpolator circuit according to an embodiment of the present invention.
  • the ordinary phase interpolator circuit is affected by the nonlinearity of the current source.
  • the phase of the output clock is nonlinear, and the phase INL and DNL are often greater than 1LSB.
  • the embodiment of the present invention provides a phase interpolator circuit and a method for improving linearity thereof, which greatly reduces the INL and DNL of the phase phase of the phase interpolator, thereby improving the performance of the phase interpolator.
  • a conventional phase interpolator circuit includes a metal-oxide-semiconductor (MOS) tube 101. Up to 108, digital to analog converter (IDAC) 111, resistors 114, 115.
  • the IDAC output current varies linearly with the PIctrl signal, adjusting the current levels of the four sets of differential switching transistors 101 and 102, 103 and 104, 105 and 106, 107 and 108, and controlling CLK0, CLK90, CLK180, and CLK270 in the output clocks OUTP, OUTN. Weight, the function of phase adjustment.
  • the phase of the output clock is primarily determined by the weight of the four pairs of differential switch currents flowing through.
  • Phase interpolators with a speed exceeding GHz have a relatively large current consumption, so the tail current will be relatively large, and the size of the four pairs of differential switching tubes will increase accordingly. This will cause the parasitic capacitance of nodes A, B, C, and D to be large.
  • phase adjustment especially quadrant hopping, it is expected that the potentials of the four points A, B, C, and D can quickly jump from a very low voltage to several hundred mV, or from several hundred mV to a low voltage. Due to the influence of parasitic, the voltage change requires a certain response time, and the adjustment current will cause a deviation, which will cause the phase to be changed in time, which seriously affects the linearity of the phase interpolator.
  • the differential switch tubes 101 to 108 and IDAC 111 of the conventional phase interpolator circuit of FIG. 1 are split into N independent units.
  • the size of the tube of each individual unit is 1/N of the total size.
  • the phase of the phase interpolator is determined by the current weight of each quadrant, which is the number of cells.
  • phase interpolator circuit includes N phase interpolator units 21, N ⁇ 2; the phase interpolator unit 21 includes a differential switch transistor circuit 211, a current control circuit 212, and a bias current circuit 213, wherein
  • the differential switch transistor circuit 211 includes a first switch tube and a second switch tube; the first switch tube is connected to the clock signal input terminal through its first port, and is connected to the negative signal output terminal through its second port. And connected to the current control circuit 212 through its own third port; the second switch tube is connected to the clock signal input terminal through its first port, and is connected to the positive signal output terminal through its second port And through its third port with the electricity
  • the flow control circuit 212 is connected;
  • the current control circuit 212 is connected to the control signal input terminal through its first port, and is connected to the differential switch transistor circuit 211 through its second port, and passes through its own third port and the bias current circuit 213. connection;
  • the bias current circuit 213 is connected to the reference signal input terminal through its own first port, connected to the current control circuit 212 through its second port, and connected to the ground through its own third port.
  • the phase interpolator unit 21 includes four sets of differential switch tube circuits 211;
  • the first port of the first switch of the first set of differential switch circuit 211 is connected to the first clock signal input end, and the first port of the second switch tube is connected to the second clock signal input end;
  • the first port of the first switch tube of the second group of differential switch tube circuits 211 is connected to the third clock signal input end, and the first port of the second switch tube is connected to the fourth clock signal input end;
  • the first port of the first switch tube of the third group of differential switch tube circuits 211 is connected to the second clock signal input end, and the first port of the second switch tube is connected to the first clock signal input end;
  • the first port of the first switch tube of the fourth group of differential switch transistors 211 is connected to the fourth clock signal input end, and the first port of the second switch tube is connected to the third clock signal input end.
  • the phase interpolator unit 21 includes four sets of current control circuits 212;
  • the first port of the first set of current control circuit 212 is coupled to the first control signal input;
  • the first port of the second group of current control circuits 212 is coupled to the second control signal input terminal
  • the first port of the third group of current control circuits 212 is coupled to the third control signal input terminal;
  • the first port of the fourth set of current control circuits 212 is coupled to the fourth control signal input.
  • the negative signal output ends respectively connected to the four sets of differential switch tube circuits 211 are connected together, and the positive signal output ends respectively connected to the four sets of differential switch tube circuits 211 are respectively connected. connected.
  • the current control circuit 212 is connected to the differential switch transistor circuit 211 through its second port, specifically:
  • the current control circuit 212 is respectively connected to the third port of the first switch tube and the third port of the second switch tube in the differential switch tube circuit 211 through its second port.
  • the first switch tube, the second switch tube, the current control circuit 212, and the bias current circuit 213 are all N-type NMOS tubes.
  • the phase interpolator circuit further includes: a first resistor 22 and a second resistor 23, wherein
  • the first end of the first resistor 22 is connected to the power source, and the second end is connected to the negative signal output end;
  • the first end of the second resistor 23 is connected to the power source, and the second end is connected to the positive signal output end.
  • FIG. 3 is a circuit diagram of a PI CELL according to an embodiment of the present invention, wherein substrates of all NMOS transistors are connected to ground.
  • the drain of the NMOS transistor 101 is connected to the positive output terminal OUTN of the phase interpolator, the gate is connected to the phase interpolator input signal CLK0, and the source is connected to A.
  • the drain of the NMOS transistor 102 is connected to the negative output terminal OUTP of the phase interpolator, and the gate and phase interpolator input signal CLK180 Connected, the source is connected to A.
  • the drain of the NMOS transistor 103 is connected to the positive output terminal OUTN of the phase interpolator, the gate is connected to the phase interpolator input signal CLK90, and the source is connected to B.
  • the drain of the NMOS transistor 104 is connected to the negative output terminal OUTP of the phase interpolator, the gate is connected to the phase interpolator input signal CLK270, and the source is connected to B.
  • the drain of the NMOS transistor 105 is connected to the positive output terminal OUTN of the phase interpolator, the gate is connected to the phase interpolator input signal CLK180, and the source is connected to C.
  • the drain of the NMOS transistor 106 is connected to the negative output terminal OUTP of the phase interpolator, the gate is connected to the phase interpolator input signal CLK0, and the source is connected to C.
  • the drain of the NMOS transistor 107 is connected to the positive output terminal OUTN of the phase interpolator, the gate is connected to the phase interpolator input signal CLK270, and the source is connected to D.
  • the drain of the NMOS transistor 108 is connected to the negative output terminal OUTP of the phase interpolator, the gate is connected to the phase interpolator input signal CLK0, and the source is connected to D.
  • the gate of the NMOS transistor 109 is connected to ctrl0, the drain is connected to A, and the source is E.
  • the gate of the NMOS transistor 110 is connected to ctrl90, the drain is connected to B, and the source is connected to E.
  • the gate of the NMOS transistor 111 is connected to ctrl180, the drain is connected to C, and the source is connected to E.
  • the gate of the NMOS transistor 112 is connected to ctrl270, the drain is connected to D, and the source is connected to E.
  • the gate of the NMOS transistor 113 is connected to vref, the drain is connected to E, and the source is grounded.
  • FIG. 4 is a general diagram of a PI circuit according to an embodiment of the present invention.
  • the PI circuit is composed of a resistor and N PI CELLs. All PI CELL's OUTP and OUTN are connected together. PI ctrl is controlled by the digital circuit output.
  • One end of the resistor 114 is connected to the power supply, and the other end is connected to the output terminal OUTN of the phase interpolator.
  • One end of the resistor 115 is connected to the power supply, and the other end is connected to the output terminal OUTP of the phase interpolator.
  • FIG. 5 is a schematic flowchart of a method for improving linearity of a phase interpolator circuit according to an embodiment of the present invention. As shown in FIG. 5, the method includes:
  • Step 501 Adjust the weights of different quadrants when the phase adjustment is performed by the phase interpolator circuit, wherein the phase interpolator circuit includes N phase interpolator units, N ⁇ 2.
  • Step 502 Adjust the phase by the N phase interpolator units 21 in the phase interpolator circuit.
  • the phase interpolator unit 21 includes: a differential switch transistor circuit 211, a current control circuit 212, and a bias current circuit 213, where
  • the differential switch transistor circuit 211 includes a first switch tube and a second switch tube; the first switch tube is connected to the clock signal input terminal through its first port, and is connected to the negative signal output terminal through its second port. And connected to the current control circuit 212 through its own third port; the second switch tube is connected to the clock signal input terminal through its first port, and is connected to the positive signal output terminal through its second port And connected to the current control circuit 212 through its third port;
  • the current control circuit 212 is connected to the control signal input terminal through its first port, and is connected to the differential switch transistor circuit 211 through its second port, and passes through its own third port and the bias current circuit 213. connection;
  • the bias current circuit 213 is connected to the reference signal input terminal through its own first port, connected to the current control circuit 212 through its second port, and connected to the ground through its own third port.
  • phase interpolator circuit in this embodiment can be understood with reference to the phase interpolator circuit shown in FIGS. 1-3.

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Abstract

本发明公开了一种相位插值器电路及其提升线性度的方法，相位插值器电路包括N个相位插值器单元，N≥2；相位插值器单元包括：差分开关管电路、电流控制电路、偏置电流电路，差分开关管电路包括第一开关管和第二开关管；第一开关管与时钟信号输入端、负信号输出端、电流控制电路相连接；第二开关管与时钟信号输入端、正信号输出端、电流控制电路相连接；电流控制电路与控制信号输入端、差分开关管电路、偏置电流电路连接；偏置电流电路与参考信号输入端、电流控制电路、地连接。

Description

一种相位插值器电路及其提升线性度的方法
相关申请的交叉引用
本申请基于申请号为201611239678.0、申请日为2016年12月28日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本发明涉及一种相位插值器电路，尤其涉及一种相位插值器电路及其提升线性度的方法。
背景技术
相位插值器(PI，Phase Interpolator)电路在高速数模混合电路(如锁相环(PLL，Phase Locked Loop)电路、时钟数据恢复(CDR，Clock Data Recovery)电路等)中被广泛应。随着工作速度的不断提高，对相位插值器电路的精度要求也不断提高。普通相位插值器电路输出时钟的相位的积分非线性(INL，Integral Nonlinearity)、差分非线性(DNL，Differential Nonlinearity)往往会大于1最低有效位(LSB，Least Significant Bit)，影响相位插值器电路的后级电路的正常工作。如何减小相位插值器电路输出相位的INL和DNL是亟需解决的问题。
发明内容
为解决上述技术问题，本发明实施例提供了一种相位插值器电路及其提升线性度的方法。
本发明实施例提供的相位插值器电路，包括N个相位插值器单元，N ≥2；所述相位插值器单元包括：差分开关管电路、电流控制电路、偏置电流电路，其中，
所述差分开关管电路包括第一开关管和第二开关管；所述第一开关管通过自身的第一端口与时钟信号输入端连接，通过自身的第二端口与负信号输出端相连接，并通过自身的第三端口与所述电流控制电路相连接；所述第二开关管通过自身的第一端口与时钟信号输入端连接，通过自身的第二端口与正信号输出端相连接，并通过自身的第三端口与所述电流控制电路相连接；
所述电流控制电路通过自身的第一端口与控制信号输入端连接，通过自身的第二端口与所述差分开关管电路连接，并通过自身的第三端口与所述偏置电流电路连接；
所述偏置电流电路通过自身的第一端口与所述参考信号输入端连接，通过自身的第二端口与所述电流控制电路连接，并通过自身的第三端口与地连接。
本发明实施例中，所述相位插值器单元包括四组差分开关管电路；其中，
第一组差分开关管电路中的第一开关管的第一端口与第一时钟信号输入端连接，第二开关管的第一端口与第二时钟信号输入端连接；
第二组差分开关管电路中的第一开关管的第一端口与第三时钟信号输入端连接，第二开关管的第一端口与第四时钟信号输入端连接；
第三组差分开关管电路中的第一开关管的第一端口与第二时钟信号输入端连接，第二开关管的第一端口与第一时钟信号输入端连接；
第四组差分开关管电路中的第一开关管的第一端口与第四时钟信号输入端连接，第二开关管的第一端口与第三时钟信号输入端连接。
本发明实施例中，所述相位插值器单元包括四组电流控制电路；其中，
第一组电流控制电路的第一端口与第一控制信号输入端连接；
第二组电流控制电路的第一端口与第二控制信号输入端连接；
第三组电流控制电路的第一端口与第三控制信号输入端连接；
第四组电流控制电路的第一端口与第四控制信号输入端连接。
本发明实施例中，所述四组差分开关管电路分别连接的负信号输出端连接在一起，所述四组差分开关管电路分别连接的正信号输出端连接在一起。
本发明实施例中，所述电流控制电路通过自身的第二端口与所述差分开关管电路连接，具体为：
所述电流控制电路通过自身的第二端口分别与所述差分开关管电路中的第一开关管的第三端口和第二开关管的第三端口连接。
本发明实施例中，所述第一开关管、所述第二开关管、所述电流控制电路、所述偏置电流电路均为N型金属-氧化物-半导体场效应(NMOS，N-Metal-Oxide-Semiconductor)管。
本发明实施例中，所述相位插值器电路还包括：第一电阻、第二电阻，其中，
所述第一电阻的第一端与电源连接，第二端与所述负信号输出端连接；
所述第二电阻的第一端与电源连接，第二端与所述正信号输出端连接。
本发明实施例提供的相位插值器电路提升线性度的方法，包括：
当通过相位插值器电路进行相位调整时，调整不同象限所占的权重，其中，所述相位插值器电路包括N个相位插值器单元，N≥2；
通过所述相位插值器电路中的N个相位插值器单元对相位进行调整。
本发明实施例中，所述相位插值器单元包括：差分开关管电路、电流控制电路、偏置电流电路，其中，
所述差分开关管电路包括第一开关管和第二开关管；所述第一开关管 通过自身的第一端口与时钟信号输入端连接，通过自身的第二端口与负信号输出端相连接，并通过自身的第三端口与所述电流控制电路相连接；所述第二开关管通过自身的第一端口与时钟信号输入端连接，通过自身的第二端口与正信号输出端相连接，并通过自身的第三端口与所述电流控制电路相连接；
所述电流控制电路通过自身的第一端口与控制信号输入端连接，通过自身的第二端口与所述差分开关管电路连接，并通过自身的第三端口与所述偏置电流电路连接；
所述偏置电流电路通过自身的第一端口与所述参考信号输入端连接，通过自身的第二端口与所述电流控制电路连接，并通过自身的第三端口与地连接。
本发明实施例的技术方案中，相位插值器电路包括N个相位插值器单元，N≥2；所述相位插值器单元包括：差分开关管电路、电流控制电路、偏置电流电路，其中，所述差分开关管电路包括第一开关管和第二开关管；所述第一开关管通过自身的第一端口与时钟信号输入端连接，通过自身的第二端口与负信号输出端相连接，并通过自身的第三端口与所述电流控制电路相连接；所述第二开关管通过自身的第一端口与时钟信号输入端连接，通过自身的第二端口与正信号输出端相连接，并通过自身的第三端口与所述电流控制电路相连接；所述电流控制电路通过自身的第一端口与控制信号输入端连接，通过自身的第二端口与所述差分开关管电路连接，并通过自身的第三端口与所述偏置电流电路连接；所述偏置电流电路通过自身的第一端口与所述参考信号输入端连接，通过自身的第二端口与所述电流控制电路连接，并通过自身的第三端口与地连接。采用本发明实施例的技术方案，在每次相位跳变的时候，只需要改变并联的独立相位插值器单元的个数。由于独立相位插值器单元寄生小，电流可以快速稳定。每次增加或 者减少一个独立相位插值器单元，电流的变化是线性的，对相位的改变是线性的。特别是在发生象限跳变的时候，只是增加或减少并联的独立相位插值器单元的个数，其实和象限内的相位跳变是没有区别的。通过这种方式，大大提高了相位插值器的线性度，保证了输出信号相位的平滑变化。
附图说明
附图以示例而非限制的方式大体示出了本文中所讨论的各个实施例。
图1为传统的相位插值器电路图；
图2为本发明实施例的相位插值器电路的结构组成示意图；
图3为本发明实施例的PI CELL电路图；
图4为本发明实施例的PI电路总图；
图5为本发明实施例的相位插值器电路提升线性度的方法的流程示意图。
具体实施方式
为了能够更加详尽地了解本发明实施例的特点与技术内容，下面结合附图对本发明实施例的实现进行详细阐述，所附附图仅供参考说明之用，并非用来限定本发明实施例。
普通的相位插值器电路受到电流源的非线性的影响，输出时钟的相位是非线性变化的，相位的INL、DNL往往会大于1LSB。另外，由于受到大的寄生电容的影响，输出信号相位在改变时，电流的变化无法及时响应，导致相位很难平滑变化。这些都会降低相位插值器的性能。为此，本发明实施例提出一种相位插值器电路及其提升线性度的方法，极大的减小相位插值器输出相位的INL和DNL，进而提升相位插值器的性能。
图1为传统的相位插值器电路图，如图1所示，传统的相位插值器电路包括：金属-氧化物-半导体(MOS，Metal-Oxide-Semiconductor)管101 至108、数模转换装置(IDAC)111、电阻114、115。IDAC输出电流随PIctrl信号线性变化，调整四组差分开关管101与102、103与104、105与106、107与108的电流大小，控制CLK0、CLK90、CLK180、CLK270在输出时钟OUTP、OUTN中的权重，实现相位调整的功能。输出时钟的相位主要由流过的四对差分开关管电流的权重决定。通过调整四相时钟的比重，可以输出0°到360°之间任意相位的时钟。速率超过GHz的相位插值器，电流消耗比较大，因此尾管电流会比较大，四对差分开关管的尺寸也要相应增加。这样会导致节点A、B、C、D的寄生电容较大。在进行相位调整特别是象限跳变的时候，期望A、B、C、D四点的电位可以迅速从很低的电压跳变到几百mV，或者从几百mV跳变到低电压。由于寄生的影响，电压的改变需要一定的响应时间，调整电流会产生偏差，这样会导致相位不能及时改变，严重的影响了相位插值器的线性度。
本发明实施例的技术方案中，将图1中传统的相位插值器电路的差分开关管101至108、IDAC111，拆分成N个独立的单元。每一个独立单元的管子的尺寸是总尺寸的1/N。相位插值器的相位，由每个象限的电流权重决定，也就是单元的个数决定。
图2为本发明实施例的相位插值器电路的结构组成示意图，如图2所示，所述相位插值器电路包括N个相位插值器单元21，N≥2；所述相位插值器单元21包括：差分开关管电路211、电流控制电路212、偏置电流电路213，其中，
所述差分开关管电路211包括第一开关管和第二开关管；所述第一开关管通过自身的第一端口与时钟信号输入端连接，通过自身的第二端口与负信号输出端相连接，并通过自身的第三端口与所述电流控制电路212相连接；所述第二开关管通过自身的第一端口与时钟信号输入端连接，通过自身的第二端口与正信号输出端相连接，并通过自身的第三端口与所述电 流控制电路212相连接；
所述电流控制电路212通过自身的第一端口与控制信号输入端连接，通过自身的第二端口与所述差分开关管电路211连接，并通过自身的第三端口与所述偏置电流电路213连接；
所述偏置电流电路213通过自身的第一端口与所述参考信号输入端连接，通过自身的第二端口与所述电流控制电路212连接，并通过自身的第三端口与地连接。
本发明实施例中，所述相位插值器单元21包括四组差分开关管电路211；其中，
第一组差分开关管电路211中的第一开关管的第一端口与第一时钟信号输入端连接，第二开关管的第一端口与第二时钟信号输入端连接；
第二组差分开关管电路211中的第一开关管的第一端口与第三时钟信号输入端连接，第二开关管的第一端口与第四时钟信号输入端连接；
第三组差分开关管电路211中的第一开关管的第一端口与第二时钟信号输入端连接，第二开关管的第一端口与第一时钟信号输入端连接；
第四组差分开关管电路211中的第一开关管的第一端口与第四时钟信号输入端连接，第二开关管的第一端口与第三时钟信号输入端连接。
本发明实施例中，所述相位插值器单元21包括四组电流控制电路212；其中，
第一组电流控制电路212的第一端口与第一控制信号输入端连接；
第二组电流控制电路212的第一端口与第二控制信号输入端连接；
第三组电流控制电路212的第一端口与第三控制信号输入端连接；
第四组电流控制电路212的第一端口与第四控制信号输入端连接。
本发明实施例中，所述四组差分开关管电路211分别连接的负信号输出端连接在一起，所述四组差分开关管电路211分别连接的正信号输出端 连接在一起。
本发明实施例中，所述电流控制电路212通过自身的第二端口与所述差分开关管电路211连接，具体为：
所述电流控制电路212通过自身的第二端口分别与所述差分开关管电路211中的第一开关管的第三端口和第二开关管的第三端口连接。
本发明实施例中，所述第一开关管、所述第二开关管、所述电流控制电路212、所述偏置电流电路213均为N型NMOS管。
本发明实施例中，所述相位插值器电路还包括：第一电阻22、第二电阻23，其中，
所述第一电阻22的第一端与电源连接，第二端与所述负信号输出端连接；
所述第二电阻23的第一端与电源连接，第二端与所述正信号输出端连接。
本发明实施例，在每次相位跳变的时候，只需要改变并联的独立相位插值器单元21的个数。由于独立相位插值器单元21寄生小，电流可以快速稳定。每次增加或者减少一个独立相位插值器单元21，电流的变化是线性的，对相位的改变是线性的。特别是在发生象限跳变的时候，只是增加或减少并联的独立相位插值器单元21的个数，其实和象限内的相位跳变是没有区别的。通过这种方式，大大提高了相位插值器的线性度，保证了输出信号相位的平滑变化。
下面结合图3和图4对本发明实施例的技术方案进一步的详细描述。
图3为本发明实施例的PI CELL电路图，所有NMOS管的衬底都与地相连。NMOS管101的漏极与相位插值器的正输出端OUTN相连，栅极与相位插值器输入信号CLK0相连，源极与A相连。NMOS管102的漏极与相位插值器的负输出端OUTP相连，栅极与相位插值器输入信号CLK180 相连，源极与A相连。NMOS管103的漏极与相位插值器的正输出端OUTN相连，栅极与相位插值器输入信号CLK90相连，源极与B相连。NMOS管104的漏极与相位插值器的负输出端OUTP相连，栅极与相位插值器输入信号CLK270相连，源极与B相连。NMOS管105的漏极与相位插值器的正输出端OUTN相连，栅极与相位插值器输入信号CLK180相连，源极与C相连。NMOS管106的漏极与相位插值器的负输出端OUTP相连，栅极与相位插值器输入信号CLK0相连，源极与C相连。NMOS管107的漏极与相位插值器的正输出端OUTN相连，栅极与相位插值器输入信号CLK270相连，源极与D相连。NMOS管108的漏极与相位插值器的负输出端OUTP相连，栅极与相位插值器输入信号CLK0相连，源极与D相连。NMOS管109的栅极接ctrl0，漏极接A，源极E。NMOS管110的栅极接ctrl90，漏极接B，源极接E。NMOS管111的栅极接ctrl180，漏极接C，源极接E。NMOS管112的栅极接ctrl270，漏极接D，源极接E。NMOS管113的栅极接vref，漏极接E，源极接地。
图4为本发明实施例的PI电路总图，如图4所示，PI电路由电阻和N个PI CELL组成。所有的PI CELL的OUTP、OUTN分别接在一起。PI ctrl由数字电路输出控制。电阻114一端连接至电源，另外一端连接至相位插值器的输出端OUTN。电阻115一端连接至电源，另外一端连接至相位插值器的输出端OUTP。
图5为本发明实施例的相位插值器电路提升线性度的方法的流程示意图，如图5所示，所述方法包括：
步骤501：当通过相位插值器电路进行相位调整时，调整不同象限所占的权重，其中，所述相位插值器电路包括N个相位插值器单元，N≥2。
步骤502：通过所述相位插值器电路中的N个相位插值器单元21对相位进行调整。
本发明实施例中，所述相位插值器单元21包括：差分开关管电路211、电流控制电路212、偏置电流电路213，其中，
所述差分开关管电路211包括第一开关管和第二开关管；所述第一开关管通过自身的第一端口与时钟信号输入端连接，通过自身的第二端口与负信号输出端相连接，并通过自身的第三端口与所述电流控制电路212相连接；所述第二开关管通过自身的第一端口与时钟信号输入端连接，通过自身的第二端口与正信号输出端相连接，并通过自身的第三端口与所述电流控制电路212相连接；
所述电流控制电路212通过自身的第一端口与控制信号输入端连接，通过自身的第二端口与所述差分开关管电路211连接，并通过自身的第三端口与所述偏置电流电路213连接；
所述偏置电流电路213通过自身的第一端口与所述参考信号输入端连接，通过自身的第二端口与所述电流控制电路212连接，并通过自身的第三端口与地连接。
本发明实施例，在每次相位跳变的时候，只需要改变并联的独立相位插值器单元21的个数。由于独立相位插值器单元21寄生小，电流可以快速稳定。每次增加或者减少一个独立相位插值器单元21，电流的变化是线性的，对相位的改变是线性的。特别是在发生象限跳变的时候，只是增加或减少并联的独立相位插值器单元21的个数，其实和象限内的相位跳变是没有区别的。通过这种方式，大大提高了相位插值器的线性度，保证了输出信号相位的平滑变化。
本领域技术人员应当理解，本实施例中的相位插值器电路可参照图1-图3所示的相位插值器电路进行理解。
以上所述，仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围。
工业实用性
本发明实施例的技术方案，在每次相位跳变的时候，只需要改变并联的独立相位插值器单元的个数。由于独立相位插值器单元寄生小，电流可以快速稳定。每次增加或者减少一个独立相位插值器单元，电流的变化是线性的，对相位的改变是线性的。特别是在发生象限跳变的时候，只是增加或减少并联的独立相位插值器单元的个数，其实和象限内的相位跳变是没有区别的。通过这种方式，大大提高了相位插值器的线性度，保证了输出信号相位的平滑变化。

Claims (9)

  1. 一种相位插值器电路，所述相位插值器电路包括N个相位插值器单元，N≥2；所述相位插值器单元包括：差分开关管电路、电流控制电路、偏置电流电路，其中，
    所述差分开关管电路包括第一开关管和第二开关管；所述第一开关管通过自身的第一端口与时钟信号输入端连接，通过自身的第二端口与负信号输出端相连接，并通过自身的第三端口与所述电流控制电路相连接；所述第二开关管通过自身的第一端口与时钟信号输入端连接，通过自身的第二端口与正信号输出端相连接，并通过自身的第三端口与所述电流控制电路相连接；
    所述电流控制电路通过自身的第一端口与控制信号输入端连接，通过自身的第二端口与所述差分开关管电路连接，并通过自身的第三端口与所述偏置电流电路连接；
    所述偏置电流电路通过自身的第一端口与所述参考信号输入端连接，通过自身的第二端口与所述电流控制电路连接，并通过自身的第三端口与地连接。
  2. 根据权利要求1所述的相位插值器电路，其中，所述相位插值器单元包括四组差分开关管电路；其中，
    第一组差分开关管电路中的第一开关管的第一端口与第一时钟信号输入端连接，第二开关管的第一端口与第二时钟信号输入端连接；
    第二组差分开关管电路中的第一开关管的第一端口与第三时钟信号输入端连接，第二开关管的第一端口与第四时钟信号输入端连接；
    第三组差分开关管电路中的第一开关管的第一端口与第二时钟信号输入端连接，第二开关管的第一端口与第一时钟信号输入端连接；
    第四组差分开关管电路中的第一开关管的第一端口与第四时钟信号 输入端连接，第二开关管的第一端口与第三时钟信号输入端连接。
  3. 根据权利要求2所述的相位插值器电路，其中，所述相位插值器单元包括四组电流控制电路；其中，
    第一组电流控制电路的第一端口与第一控制信号输入端连接；
    第二组电流控制电路的第一端口与第二控制信号输入端连接；
    第三组电流控制电路的第一端口与第三控制信号输入端连接；
    第四组电流控制电路的第一端口与第四控制信号输入端连接。
  4. 根据权利要求2或3所述的相位插值器电路，其中，所述四组差分开关管电路分别连接的负信号输出端连接在一起，所述四组差分开关管电路分别连接的正信号输出端连接在一起。
  5. 根据权利要求1所述的相位插值器电路，其中，所述电流控制电路通过自身的第二端口与所述差分开关管电路连接，具体为：
    所述电流控制电路通过自身的第二端口分别与所述差分开关管电路中的第一开关管的第三端口和第二开关管的第三端口连接。
  6. 根据权利要求1所述的相位插值器电路，其中，所述第一开关管、所述第二开关管、所述电流控制电路、所述偏置电流电路均为N型金属-氧化物-半导体场效应NMOS管。
  7. 根据权利要求1至6任一项所述的相位插值器电路，其中，所述相位插值器电路还包括：第一电阻、第二电阻，其中，
    所述第一电阻的第一端与电源连接，第二端与所述负信号输出端连接；
    所述第二电阻的第一端与电源连接，第二端与所述正信号输出端连接。
  8. 一种相位插值器电路提升线性度的方法，所述方法包括：
    当通过相位插值器电路进行相位调整时，调整不同象限所占的权重， 其中，所述相位插值器电路包括N个相位插值器单元，N≥2；
    通过所述相位插值器电路中的N个相位插值器单元对相位进行调整。
  9. 根据权利要求8所述的相位插值器电路提升线性度的方法，其中，所述相位插值器单元包括：差分开关管电路、电流控制电路、偏置电流电路，其中，
    所述差分开关管电路包括第一开关管和第二开关管；所述第一开关管通过自身的第一端口与时钟信号输入端连接，通过自身的第二端口与负信号输出端相连接，并通过自身的第三端口与所述电流控制电路相连接；所述第二开关管通过自身的第一端口与时钟信号输入端连接，通过自身的第二端口与正信号输出端相连接，并通过自身的第三端口与所述电流控制电路相连接；
    所述电流控制电路通过自身的第一端口与控制信号输入端连接，通过自身的第二端口与所述差分开关管电路连接，并通过自身的第三端口与所述偏置电流电路连接；
    所述偏置电流电路通过自身的第一端口与所述参考信号输入端连接，通过自身的第二端口与所述电流控制电路连接，并通过自身的第三端口与地连接。
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