WO2018119993A1 - 栅极驱动电路及显示装置 - Google Patents
栅极驱动电路及显示装置 Download PDFInfo
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- WO2018119993A1 WO2018119993A1 PCT/CN2016/113410 CN2016113410W WO2018119993A1 WO 2018119993 A1 WO2018119993 A1 WO 2018119993A1 CN 2016113410 W CN2016113410 W CN 2016113410W WO 2018119993 A1 WO2018119993 A1 WO 2018119993A1
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- reference point
- signal line
- unit circuit
- gate
- sustain
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/12—Picture reproducers
- H04N9/30—Picture reproducers using solid-state colour display devices
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13454—Drivers integrated on the active matrix substrate
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
Definitions
- the present invention relates to the field of display technologies, and in particular to a gate driving circuit and a display device.
- LCD screens are widely used in information communication tools such as TVs, mobile phones, and tablets, because of their high space utilization, low power consumption, no radiation, and low electromagnetic interference.
- Gate Driver On Array technology has been increasingly used in liquid crystal displays, that is, the gate drive circuit of the scan line is fabricated on the array substrate by using the existing thin film transistor process to realize the scan line.
- Progressive scan driver At present, Gate Driver On Array (GOA) technology has been increasingly used in liquid crystal displays, that is, the gate drive circuit of the scan line is fabricated on the array substrate by using the existing thin film transistor process to realize the scan line. Progressive scan driver.
- the existing GOA gate driving circuit introduces two reference points Q and P in order to ensure the stability of the scanning line output point Gn, and the two points between Q and P are mutually restrained. Relationship.
- Gn outputs a high-level scan signal
- Gn needs to be in a low-level stable phase.
- the clock signal CKV3 is at a high level
- the high level signal line VGH charges the P point to a high level, and maintains a high level of the P point through the capacitor C2.
- P is high, both T4 and T5 are in the on state to ensure the stability of the low level of Gn and Q.
- T4 and T5 are always in an open state.
- TFTs thin film transistors
- the present invention provides a gate driving circuit including a precharge unit circuit, an output unit circuit, and a sustain unit circuit;
- the output unit circuit includes a first reference point and a clock signal line
- the sustain unit circuit includes a second reference point and a sustain signal line, and a sustain capacitor is connected between the second reference point and the sustain signal line;
- the pre-charging unit circuit inputs a high level to the first reference point before an output period
- the first reference point maintains a high level, and the clock signal line outputs a high level, causing the output unit circuit to output a scan signal to the scan line;
- the sustain signal line After the output period, the sustain signal line outputs a periodic high level to the second reference point through the sustain capacitor, so that the first reference point is maintained at a low level.
- the pre-charging unit circuit includes a first switching tube and a high-level signal line;
- the gate of the first switch tube is connected to the previous scan line, the source is connected to the high level signal line, and the drain is connected to the first reference point.
- the pre-charging unit circuit further includes a second switching tube
- the gate of the second switch tube is connected to the first scan line, the source is connected to the high level signal line, and the drain is connected to the first reference point.
- the output unit circuit further includes a third switch tube and a first capacitor
- a gate of the third switch tube is connected to the first reference point, a source is connected to the clock signal line, and a drain is connected to the scan line;
- the first capacitor is connected between a gate and a drain of the third switching transistor.
- the maintaining unit circuit further includes a low level signal line, a fourth switching tube and a second capacitor;
- a gate of the fourth switching transistor is connected to the second reference point, a source is connected to the low-level signal line, and a drain is connected to the scan line;
- the second capacitor is connected between the second reference point and the low level signal line.
- the maintaining unit circuit further includes a fifth switching tube
- the gate of the fifth switch tube is connected to the second reference point, the source is connected to the first reference point, and the drain is connected to the low level signal line.
- the maintaining unit circuit further includes a sixth switching tube
- the gate of the sixth switch tube is connected to the first reference point, the source is connected to the second reference point, and the drain is connected to the low-level signal line.
- the duty ratio of the periodic high level of the sustain signal line output is 25% or 50%.
- the present invention also provides a display device comprising a plurality of cascaded gate drive circuits as described above.
- the display device comprises an array substrate, and the gate driving circuit is formed on the array substrate.
- the gate driving circuit provided by the present invention comprises a pre-charging unit circuit, an output unit circuit and a sustaining unit circuit.
- the pre-charging unit circuit Before the output period, the pre-charging unit circuit inputs a high level to the first reference point in the output unit circuit; within the output period, the first reference point maintains a high level, and the clock signal line output in the output unit circuit is high. Level, the output unit circuit outputs a scan signal to the scan line; after the output period, the sustain signal line in the sustain unit circuit outputs a periodic high level to the second reference point through the sustain capacitor, so that the first reference point is kept low. level.
- the second reference point When the sustain signal line is high, the second reference point is bootstrapped to a high level to maintain the stability of the first reference point and the scan line; when the sustain signal line is low, the second reference point is bootstrapped It is low level to prevent potential shift of the thin film transistor in the sustain unit circuit due to maintaining the ON state for a long time, thereby solving the technical problem that the prior art is liable to cause abnormality of the gate drive signal output.
- 1 is a schematic view of a conventional gate driving circuit
- FIG. 2 is a timing diagram of a conventional gate driving circuit
- FIG. 3 is a schematic diagram of a gate driving circuit according to Embodiment 1 of the present invention.
- FIG. 4 is a timing diagram of a gate driving circuit according to Embodiment 1 of the present invention.
- FIG. 5 is a schematic diagram of a gate driving circuit according to Embodiment 2 of the present invention.
- FIG. 6 is a timing diagram of a gate driving circuit according to a second embodiment of the present invention.
- the embodiment of the invention provides a splicing unit reticle for forming a color resist layer and a black matrix, so as to solve the technical problem that the splicing exposure technology is easy to generate splicing marks.
- Embodiment 1 is a diagrammatic representation of Embodiment 1:
- an embodiment of the present invention provides a gate driving circuit including a pre-charging unit circuit, an output unit circuit, and a sustaining unit circuit.
- the output unit circuit includes a first reference point Q and a clock signal line CKV1.
- the sustain unit circuit includes a second reference point P and a sustain signal line CKV3, and a sustain capacitor C3 is connected between the second reference point P and the sustain signal line CKV3.
- the precharge unit circuit inputs a high level to the first reference point Q before the output period.
- the first reference point Q maintains a high level
- the clock signal line CKV1 outputs a high level, causing the output unit circuit to output a scan signal to the scan line Gn.
- the sustain signal line CKV3 outputs a periodic high level to the second reference point P through the sustain capacitor C3, so that the first reference point Q is maintained at a low level.
- the output period is also a scan period in which the scan line Gn controlled by the gate drive circuit of the stage outputs a scan signal.
- the pre-charging unit circuit may specifically include a first switching tube T1 and a high-level signal line VGH.
- the gate of the first switching transistor T1 is connected to the previous-stage scanning line Gn-1, the source is connected to the high-level signal line VGH, and the drain is connected to the first reference point Q.
- the first switch tube T1 can be turned on, thereby pre-charging the output unit circuit from the high-level signal line VGH through the first switch tube T1.
- the pre-charging unit circuit may further include a second switching transistor T2.
- the gate of the second switching transistor T2 is connected to the first-level scanning Gn+1, the source is connected to the high-level signal line VGH, and the drain is connected to the first reference point Q.
- the output unit circuit can be precharged through the second switching tube T2, thereby realizing bidirectional scanning.
- the output unit circuit further includes a third switch tube T3 and a first capacitor C1.
- the gate of the third switching transistor T3 is connected to the first reference point Q, the source is connected to the clock signal line CKV1, and the drain is connected to the scanning line Gn.
- the first capacitor C1 is connected between the gate and the drain of the third switching transistor T3.
- the sustain unit circuit further includes a low level signal line VGL, a fourth switching transistor T4, and a second capacitor C2.
- the gate of the fourth switching transistor T4 is connected to the second reference point P, the source is connected to the low-level signal line VGL, and the drain is connected to the scanning line Gn.
- the second capacitor C2 is connected between the second reference point P and the low level signal line VGL.
- the sustain unit circuit further includes a fifth switch tube T5.
- the gate of the fifth switch tube T5 is connected to the second reference point P, the source is connected to the first reference point Q, and the drain is connected to the low level signal line VGL.
- the sustain unit circuit further includes a sixth switch tube T6.
- the gate of the sixth switch tube T6 is connected to the first reference point Q, the source is connected to the second reference point P, and the drain is connected to the low level signal line VGL.
- the duty ratio of the periodic high level outputted by the sustain signal line CKV3 is 25%
- the sustain signal line CKV3 is similar to the clock signal line CKV1
- the output is also a duty ratio of 25%. Clock signal, but the phase of the two is different by half a cycle.
- the operation of the gate driving circuit provided by the embodiment of the present invention includes the following stages:
- Phase 1 pre-charging: This embodiment takes a forward scanning as an example for description. Gn-1 outputs a high-level scanning signal, T1 is turned on, and Q is precharged to a high level.
- phase 2 Gn outputs a high level: in phase 1, Q is precharged to a high level, and C1 can maintain a high level at point Q, causing T3 to be in a conducting state. At the same time, the high level of CKV1 is output to Gn through T3, so that Gn outputs a scan signal. In addition, at this time, T6 is turned on to maintain the P point at a low level.
- Gn outputs a low level: Gn+1 outputs a high level, T2 is turned on, and Q is maintained at a high level. At this time, the low level of CKV1 is output to Gn through T3, so that Gn outputs a low level.
- phase 4 Q is pulled low to low: CKV3 outputs a high level, and P is pulled high to high level by C3's bootstrap action.
- T5 is turned on, Q is pulled low, and T3 is turned off; at the same time, T4 is turned on, and Gn is not pulled low.
- phase 5 the Q point and the Gn point are maintained at a low level: when the Q point becomes a low level, the T6 is in an off state.
- CKV3 When CKV3 is high, P point is bootstrapped to a high level through C3, maintaining the low level of Q and Gn points; when CKV3 is low, P point is bootstrapped to low level through C3.
- the potential offset caused by T4 and T5 being maintained in the on state for a long time is prevented, thereby solving the technical problem that the prior art is prone to cause abnormality of the gate drive signal output.
- Embodiment 2 is a diagrammatic representation of Embodiment 1:
- an embodiment of the present invention provides a gate driving circuit including a pre-charging unit circuit, an output unit circuit, and a sustaining unit circuit.
- the structure in each unit circuit in this embodiment is basically the same as that in the first embodiment, and the difference is that the duty ratio of the periodic high level of the output of the signal line Reset is 50% in this embodiment.
- Phase 1 pre-charging:
- reverse scanning is taken as an example for description.
- Gn+1 outputs a high-level scanning signal
- T2 is turned on, and Q point is precharged to a high level.
- phase 2 Gn outputs a high level: in phase 1, Q is precharged to a high level, and C1 can maintain a high level at point Q, causing T3 to be in a conducting state. At the same time, the high level of CKV1 is output to Gn through T3, so that Gn outputs a scan signal. In addition, at this time, T6 is turned on to maintain the P point at a low level.
- Gn outputs a low level: Gn-1 outputs a high level, T1 is turned on, and Q is maintained at a high level. At this time, the low level of CKV1 is output to Gn through T3, so that Gn outputs a low level.
- phase 4 the Q point is pulled low to the low level: Reset outputs a high level, and P is pulled high to the high level by the bootstrap action of C3.
- T5 is turned on, Q is pulled low, and T3 is turned off; at the same time, T4 is turned on, and Gn is not pulled low.
- phase 5 the Q point and the Gn point are maintained at a low level: when the Q point becomes a low level, the T6 is in an off state.
- Reset high, P point is bootstrapped to a high level by C3, maintaining a low level of Q and Gn points; when Reset is low, P point is bootstrapped to a low level by C3.
- the potential offset caused by T4 and T5 being maintained in the on state for a long time is prevented, thereby solving the technical problem that the prior art is prone to cause abnormality of the gate drive signal output.
- Embodiment 3 is a diagrammatic representation of Embodiment 3
- the present invention provides a display device including a plurality of cascaded gate drive circuits provided by the above two embodiments.
- the display device provided by the embodiment of the invention includes an array substrate, and the gate driving circuit is formed on the array substrate, that is, the gate driving circuit is formed on the half area of the array substrate by using GOA technology.
- the display device provided by the embodiment of the present invention has the same technical features as the gate driving circuit provided in the first embodiment and the second embodiment, so that the same technical problem can be solved and the same technical effect can be achieved.
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Abstract
一种栅极驱动电路及显示装置,解决了现有技术容易造成栅极驱动信号输出异常的技术问题。该栅极驱动电路包括预充电单元电路、输出单元电路和维持单元电路;输出单元电路中包括第一参考点(Q)和时钟信号线(CKV1);维持单元电路中包括第二参考点(P)和维持信号线(CKV3、Reset),第二参考点(P)与维持信号线(CKV3、Reset)之间连接有维持电容(C3)。
Description
本申请要求享有2016年12月27日提交的名称为“栅极驱动电路及显示装置”的中国专利申请CN201611228518.6的优先权,其全部内容通过引用并入本文中。
本发明涉及显示技术领域,具体的说,涉及一种栅极驱动电路及显示装置。
随着显示技术的发展,液晶显示屏已经成为最为常见的显示装置。液晶显示屏具有高空间利用率、低功耗、无辐射以及低电磁干扰等优越特性,因此在电视、手机、平板电脑等信息沟通工具中得到广泛使用。
目前,Gate Driver On Array(GOA)技术已被越来越多的应用在液晶显示器中,也就是利用现有薄膜晶体管的制程将扫描线的栅极驱动电路制作在阵列基板上,实现对扫描线逐行扫描的驱动。
如图1和图2所示,现有的GOA栅极驱动电路,为了保证扫描线输出点Gn的稳定,会引入Q、P两个参考点,而Q、P两点之间多为相互牵制的关系。当Gn输出高电平的扫描信号之后,Gn需处于低电平稳定阶段。当时钟信号CKV3为高电平时,高电平信号线VGH将P点充电到高电平,并通过电容C2来维持P点的高电平。当P点为高电平时,T4和T5均处于导通状态,以保证Gn和Q点低电平的稳定。可以看出,当Q点变为低电平之后,P点在一帧时间内均处于高电平,也就是T4、T5一直处于打开的状态。但是,那么长时间的工作,会造成T4、T5这两个关键的薄膜晶体管(Thin Film Transistor,简称TFT)发生电位偏移,使电路的稳定能力下降,导致栅极驱动信号输出异常。
发明内容
本发明的目的在于提供一种栅极驱动电路及显示装置,以解决现有技术容易造成栅极驱动信号输出异常的技术问题。
本发明提供一种栅极驱动电路,包括预充电单元电路、输出单元电路和维持单元电路;
所述输出单元电路中包括第一参考点和时钟信号线;
所述维持单元电路中包括第二参考点和维持信号线,所述第二参考点与所述维持信号线之间连接有维持电容;
在输出周期之前,所述预充电单元电路向所述第一参考点输入高电平;
在输出周期之内,所述第一参考点维持高电平,同时所述时钟信号线输出高电平,使所述输出单元电路向扫描线输出扫描信号;
在输出周期之后,所述维持信号线通过所述维持电容向所述第二参考点输出周期性高电平,使所述第一参考点维持低电平。
优选的是,所述预充电单元电路包括第一开关管和高电平信号线;
所述第一开关管的栅极连接前一级扫描线,源极连接所述高电平信号线,漏极连接所述第一参考点。
进一步的是,所述预充电单元电路还包括第二开关管;
所述第二开关管的栅极连接后一级扫描线,源极连接所述高电平信号线,漏极连接所述第一参考点。
进一步的是,所述输出单元电路还包括第三开关管和第一电容;
所述第三开关管的栅极连接所述第一参考点,源极连接所述时钟信号线,漏极连接所述扫描线;
所述第一电容连接在所述第三开关管的栅极与漏极之间。
优选的是,所述维持单元电路还包括低电平信号线、第四开关管和第二电容;
所述第四开关管的栅极连接所述第二参考点,源极连接所述低电平信号线,漏极连接所述扫描线;
所述第二电容连接在所述第二参考点与所述低电平信号线之间。
进一步的是,所述维持单元电路还包括第五开关管;
所述第五开关管的栅极连接所述第二参考点,源极连接所述第一参考点,漏极连接所述低电平信号线。
进一步的是,所述维持单元电路还包括第六开关管;
所述第六开关管的栅极连接所述第一参考点,源极连接所述第二参考点,漏极连接所述低电平信号线。
优选的是,所述维持信号线输出的周期性高电平的占空比为25%或50%。
本发明还提供一种显示装置,包括多个级联的上述的栅极驱动电路。
优选的是,所述显示装置包括阵列基板,且所述栅极驱动电路形成于所述阵列基板上。
本发明带来了以下有益效果:本发明提供的栅极驱动电路,包括预充电单元电路、输出单元电路和维持单元电路。在输出周期之前,预充电单元电路向输出单元电路中的第一参考点输入高电平;在输出周期之内,第一参考点维持高电平,同时输出单元电路中的时钟信号线输出高电平,使输出单元电路向扫描线输出扫描信号;在输出周期之后,维持单元电路中的维持信号线通过维持电容向第二参考点输出周期性高电平,使第一参考点维持低电平。当维持信号线为高电平时,第二参考点被自举为高电平,以维持第一参考点及扫描线的稳定;当维持信号线为低电平时,第二参考点会被自举为低电平,以防止维持单元电路中的薄膜晶体管由于长时间维持在开启状态而造成的电位偏移,从而解决了现有技术容易造成栅极驱动信号输出异常的技术问题。
本发明的其它特征和优点将在随后的说明书中阐述,并且,部分的从说明书中变得显而易见,或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
为了更清楚的说明本发明实施例中的技术方案,下面将对实施例描述中所需要的附图做简单的介绍:
图1是现有的栅极驱动电路的示意图;
图2是现有的栅极驱动电路的时序图;
图3是本发明实施例一提供的栅极驱动电路的示意图;
图4是本发明实施例一提供的栅极驱动电路的时序图;
图5是本发明实施例二提供的栅极驱动电路的示意图;
图6是本发明实施例二提供的栅极驱动电路的时序图。
以下将结合附图及实施例来详细说明本发明的实施方式,借此对本发明如何应用技术手段来解决技术问题,并达成技术效果的实现过程能充分理解并据以实施。需要说明的是,
只要不构成冲突,本发明中的各个实施例以及各实施例中的各个特征可以相互结合,所形成的技术方案均在本发明的保护范围之内。
本发明实施例提供一种用于形成色阻层、黑矩阵的拼接单元光罩,以解决现有的拼接曝光技术存在易产生拼接斑纹的技术问题。
实施例一:
如图3所示,本发明实施例提供一种栅极驱动电路,包括预充电单元电路、输出单元电路和维持单元电路。输出单元电路中包括第一参考点Q和时钟信号线CKV1。维持单元电路中包括第二参考点P和维持信号线CKV3,第二参考点P与维持信号线CKV3之间连接有维持电容C3。
在输出周期之前,预充电单元电路向第一参考点Q输入高电平。在输出周期之内,第一参考点Q维持高电平,同时时钟信号线CKV1输出高电平,使输出单元电路向扫描线Gn输出扫描信号。在输出周期之后,维持信号线CKV3通过维持电容C3向第二参考点P输出周期性高电平,使第一参考点Q维持低电平。其中,输出周期也就是指,本级栅极驱动电路所控制的扫描线Gn输出扫描信号的一个扫描周期。
本实施例中,预充电单元电路具体可包括第一开关管T1和高电平信号线VGH。第一开关管T1的栅极连接前一级扫描线Gn-1,源极连接高电平信号线VGH,漏极连接第一参考点Q。当前一级扫描线Gn-1输出扫描信号时,即可使第一开关管T1导通,从而通过第一开关管T1由高电平信号线VGH向输出单元电路进行预充电。
预充电单元电路还可以进一步包括第二开关管T2,第二开关管T2的栅极连接后一级扫描Gn+1,源极连接高电平信号线VGH,漏极连接第一参考点Q。当后一级扫描线Gn+1输出扫描信号时,可以通过第二开关管T2向输出单元电路进行预充电,从而实现双向扫描。
进一步的是,输出单元电路中还包括第三开关管T3和第一电容C1。第三开关管T3的栅极连接第一参考点Q,源极连接时钟信号线CKV1,漏极连接扫描线Gn。第一电容C1连接在第三开关管T3的栅极与漏极之间。
作为一个优选方案,维持单元电路还包括低电平信号线VGL、第四开关管T4和第二电容C2。第四开关管T4的栅极连接第二参考点P,源极连接低电平信号线VGL,漏极连接扫描线Gn。第二电容C2连接在第二参考点P与低电平信号线VGL之间。
本实施例中,维持单元电路还包括第五开关管T5,第五开关管T5的栅极连接第二参考点P,源极连接第一参考点Q,漏极连接低电平信号线VGL。
进一步的是,维持单元电路还包括第六开关管T6,第六开关管T6的栅极连接第一参考点Q,源极连接第二参考点P,漏极连接低电平信号线VGL。
如图4所示,本实施例中维持信号线CKV3输出的周期性高电平的占空比为25%,维持信号线CKV3与时钟信号线CKV1相似,输出的也是占空比为25%的时钟信号,但二者的相位相差半个周期。
如图3和图4所示,本发明实施例提供的栅极驱动电路的工作包括如下几个阶段:
阶段1,预充电:本实施例以正向扫描为例进行说明,Gn-1输出高电平的扫描信号,T1导通,Q点被预充电为高电平。
阶段2,Gn输出高电平:在阶段1中,Q点被预充电为高电平,而C1能够保持Q点的高电平,使T3处于导通状态。同时,CKV1的高电平通过T3输出到Gn,使Gn输出扫描信号。另外,此时T6导通,使P点维持在低电平。
阶段3,Gn输出低电平:Gn+1输出高电平,T2导通,Q点维持高电平,此时CKV1的低电平通过T3输出到Gn,使Gn输出低电平。
阶段4,Q点被拉低到低电平:CKV3输出高电平,通过C3的自举作用,P点被拉高为高电平。此时T5导通,Q点被拉低,使T3断开;同时T4导通,Gn也没拉低。
阶段5,Q点及Gn点维持低电平:当Q点变为低电平后,T6处于截止状态。当CKV3为高电平时,P点通过C3被自举为高电平,维持Q及Gn点的低电平;当CKV3为低电平时,P点又会通过C3被自举为低电平,防止T4、T5由于长时间维持在开启状态而造成的电位偏移,从而解决了现有技术容易造成栅极驱动信号输出异常的技术问题。
实施例二:
如图5和图6所示,本发明实施例提供一种栅极驱动电路,包括预充电单元电路、输出单元电路和维持单元电路。本实施例中各个单元电路中的结构与实施例一基本相同,其不同点在于,本实施例中维持信号线Reset输出的周期性高电平的占空比为50%。
本发明实施例提供的栅极驱动电路的工作包括如下几个阶段:
阶段1,预充电:本实施例以反向扫描为例进行说明,Gn+1输出高电平的扫描信号,T2导通,Q点被预充电为高电平。
阶段2,Gn输出高电平:在阶段1中,Q点被预充电为高电平,而C1能够保持Q点的高电平,使T3处于导通状态。同时,CKV1的高电平通过T3输出到Gn,使Gn输出扫描信号。另外,此时T6导通,使P点维持在低电平。
阶段3,Gn输出低电平:Gn-1输出高电平,T1导通,Q点维持高电平,此时CKV1的低电平通过T3输出到Gn,使Gn输出低电平。
阶段4,Q点被拉低到低电平:Reset输出高电平,通过C3的自举作用,P点被拉高为高电平。此时T5导通,Q点被拉低,使T3断开;同时T4导通,Gn也没拉低。
阶段5,Q点及Gn点维持低电平:当Q点变为低电平后,T6处于截止状态。当Reset为高电平时,P点通过C3被自举为高电平,维持Q及Gn点的低电平;当Reset为低电平时,P点又会通过C3被自举为低电平,防止T4、T5由于长时间维持在开启状态而造成的电位偏移,从而解决了现有技术容易造成栅极驱动信号输出异常的技术问题。
实施例三:
本发明提供一种显示装置,其中包括多个级联的上述两实施例提供的栅极驱动电路。
本发明实施例提供的显示装置包括阵列基板,且栅极驱动电路形成于阵列基板上,即采用GOA技术将栅极驱动电路制作在阵列基板的半边区域。
本发明实施例提供的显示装置,与上述实施例一、实施例二提供的栅极驱动电路具有相同的技术特征,所以也能解决相同的技术问题,达到相同的技术效果。
虽然本发明所公开的实施方式如上,但所述的内容只是为了便于理解本发明而采用的实施方式,并非用以限定本发明。任何本发明所属技术领域内的技术人员,在不脱离本发明所公开的精神和范围的前提下,可以在实施的形式上及细节上作任何的修改与变化,但本发明的专利保护范围,仍须以所附的权利要求书所界定的范围为准。
Claims (17)
- 一种栅极驱动电路,包括预充电单元电路、输出单元电路和维持单元电路;所述输出单元电路中包括第一参考点和时钟信号线;所述维持单元电路中包括第二参考点和维持信号线,所述第二参考点与所述维持信号线之间连接有维持电容;在输出周期之前,所述预充电单元电路向所述第一参考点输入高电平;在输出周期之内,所述第一参考点维持高电平,同时所述时钟信号线输出高电平,使所述输出单元电路向扫描线输出扫描信号;在输出周期之后,所述维持信号线通过所述维持电容向所述第二参考点输出周期性高电平,使所述第一参考点维持低电平。
- 根据权利要求1所述的栅极驱动电路,其中,所述预充电单元电路包括第一开关管和高电平信号线;所述第一开关管的栅极连接前一级扫描线,源极连接所述高电平信号线,漏极连接所述第一参考点。
- 根据权利要求2所述的栅极驱动电路,其中,所述预充电单元电路还包括第二开关管;所述第二开关管的栅极连接后一级扫描线,源极连接所述高电平信号线,漏极连接所述第一参考点。
- 根据权利要求1所述的栅极驱动电路,其中,所述输出单元电路还包括第三开关管和第一电容;所述第三开关管的栅极连接所述第一参考点,源极连接所述时钟信号线,漏极连接所述本级扫描线;所述第一电容连接在所述第三开关管的栅极与漏极之间。
- 根据权利要求1所述的栅极驱动电路,其中,所述维持单元电路还包括低电平信号线、第四开关管和第二电容;所述第四开关管的栅极连接所述第二参考点,源极连接所述低电平信号线,漏极连接所述扫描线;所述第二电容连接在所述第二参考点与所述低电平信号线之间。
- 根据权利要求5所述的栅极驱动电路,其中,所述维持单元电路还包括第五开关管;所述第五开关管的栅极连接所述第二参考点,源极连接所述第一参考点,漏极连接所述低电平信号线。
- 根据权利要求6所述的栅极驱动电路,其中,所述维持单元电路还包括第六开关管;所述第六开关管的栅极连接所述第一参考点,源极连接所述第二参考点,漏极连接所述低电平信号线。
- 根据权利要求1所述的栅极驱动电路,其中,所述维持信号线输出的周期性高电平的占空比为25%或50%。
- 一种显示装置,包括多个级联的栅极驱动电路,所述栅极驱动电路包括预充电单元电路、输出单元电路和维持单元电路;所述输出单元电路中包括第一参考点和时钟信号线;所述维持单元电路中包括第二参考点和维持信号线,所述第二参考点与所述维持信号线之间连接有维持电容;在输出周期之前,所述预充电单元电路向所述第一参考点输入高电平;在输出周期之内,所述第一参考点维持高电平,同时所述时钟信号线输出高电平,使所述输出单元电路向扫描线输出扫描信号;在输出周期之后,所述维持信号线通过所述维持电容向所述第二参考点输出周期性高电平,使所述第一参考点维持低电平。
- 根据权利要求9所述的显示装置,其中,所述预充电单元电路包括第一开关管和高电平信号线;所述第一开关管的栅极连接前一级扫描线,源极连接所述高电平信号线,漏极连接所述第一参考点。
- 根据权利要求10所述的显示装置,其中,所述预充电单元电路还包括第二开关管;所述第二开关管的栅极连接后一级扫描线,源极连接所述高电平信号线,漏极连接所述第一参考点。
- 根据权利要求9所述的显示装置,其中,所述输出单元电路还包括第三开关管和第一电容;所述第三开关管的栅极连接所述第一参考点,源极连接所述时钟信号线,漏极连接所述本级扫描线;所述第一电容连接在所述第三开关管的栅极与漏极之间。
- 根据权利要求9所述的显示装置,其中,所述维持单元电路还包括低电平信号线、第四开关管和第二电容;所述第四开关管的栅极连接所述第二参考点,源极连接所述低电平信号线,漏极连接所述扫描线;所述第二电容连接在所述第二参考点与所述低电平信号线之间。
- 根据权利要求13所述的显示装置,其中,所述维持单元电路还包括第五开关管;所述第五开关管的栅极连接所述第二参考点,源极连接所述第一参考点,漏极连接所述低电平信号线。
- 根据权利要求14所述的显示装置,其中,所述维持单元电路还包括第六开关管;所述第六开关管的栅极连接所述第一参考点,源极连接所述第二参考点,漏极连接所述低电平信号线。
- 根据权利要求9所述的显示装置,其中,所述维持信号线输出的周期性高电平的占空比为25%或50%。
- 根据权利要求9所述的显示装置,其中,所述显示装置包括阵列基板,且所述栅极驱动电路形成于所述阵列基板上。
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