WO2018061077A1 - Power conversion device - Google Patents
Power conversion device Download PDFInfo
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- WO2018061077A1 WO2018061077A1 PCT/JP2016/078395 JP2016078395W WO2018061077A1 WO 2018061077 A1 WO2018061077 A1 WO 2018061077A1 JP 2016078395 W JP2016078395 W JP 2016078395W WO 2018061077 A1 WO2018061077 A1 WO 2018061077A1
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- WIPO (PCT)
- Prior art keywords
- voltage
- voltage dividing
- power
- circuit
- power supply
- Prior art date
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0067—Converter structures employing plural converter units, other than for parallel operation of the units on a single load
- H02M1/0074—Plural converter units whose inputs are connected in series
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0006—Arrangements for supplying an adequate voltage to the control circuit of converters
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33561—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having more than one ouput with independent control
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
- H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
- H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0067—Converter structures employing plural converter units, other than for parallel operation of the units on a single load
- H02M1/007—Plural converter units in cascade
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
Definitions
- the present invention relates to a power conversion device that performs power conversion.
- Patent Document 1 describes that a difference in leakage current between a plurality of capacitors connected in series is compensated by a transistor and a resistor to equalize the voltage balance of each capacitor.
- Patent Document 2 describes that a plurality of capacitors connected in series are charged by a power supply device, and the voltage between terminals of each capacitor is equalized.
- an object of the present invention is to provide a low-cost power conversion device with low energy loss.
- a power conversion device includes a power conversion circuit that performs power conversion, and a plurality of DC converters that are connected to a DC side of the power conversion circuit and that divide a DC voltage applied from the DC side. And a power supply circuit that is connected to both ends of each of the plurality of voltage dividing capacitors, and inputs a larger current to itself from a voltage dividing capacitor having a higher voltage among the plurality of voltage dividing capacitors, It is characterized by providing.
- FIG. 1 is a configuration diagram including a power conversion device 100 according to the first embodiment.
- the power conversion device 100 is a device that converts the DC power input from the solar cell E into predetermined AC power and outputs the AC power to the power system F.
- the power conversion apparatus 100 includes a DC-DC converter 10 (power conversion circuit, DC-DC converter), voltage dividing capacitors Cdc1, Cdc2, and an inverter 20 (power conversion circuit).
- the power conversion device 100 includes an auxiliary power supply circuit 30 (power supply circuit), a control circuit 40 (power supply target), and a fan 50 (power supply target) in addition to the configuration described above. .
- the DC-DC converter 10 is a power converter that boosts or lowers a DC voltage. That is, the DC-DC converter 10 has a function of converting the voltage applied from the solar cell E into a predetermined DC voltage Vdc.
- the inverter 20 is a power converter that converts a DC voltage into an AC voltage. That is, the inverter 20 has a function of converting a DC voltage smoothed by voltage dividing capacitors Cdc1 and Cdc2 described later into an AC voltage and outputting the AC voltage to the power system F. As shown in FIG. 1, the inverter 20 is connected to the DC-DC converter 10 via a positive-side wiring kp and a negative-side wiring kn.
- the voltage dividing capacitors Cdc1 and Cdc2 are capacitors that divide the DC voltage Vdc applied from the DC-DC converter 10, and are connected in series with each other.
- the voltage dividing capacitors Cdc1 and Cdc2 also have a function of smoothing the DC voltage Vdc.
- the voltage dividing capacitors Cdc1 and Cdc2 are connected to the output side of the DC-DC converter 10 and to the input side (DC side) of the inverter 20.
- the positive electrode of one voltage dividing capacitor Cdc1 is connected to the wiring kp, and the negative electrode of the other voltage dividing capacitor Cdc2 is connected to the wiring kn.
- the rated voltages of the voltage dividing capacitors Cdc1 and Cdc2 are substantially equal.
- the auxiliary power supply circuit 30 is a circuit that supplies power to the control circuit 40 using DC power input from the voltage dividing capacitors Cdc1 and Cdc2.
- the auxiliary power supply circuit 30 also has a function of supplying power to the fan 50 via the control circuit 40.
- the auxiliary power supply circuit 30 is connected to the positive electrode of the voltage dividing capacitor Cdc1 through the wiring kp1, and is connected to the negative electrode of the voltage dividing capacitor Cdc1 through the wiring kn1.
- the auxiliary power supply circuit 30 is connected to the positive electrode of the voltage dividing capacitor Cdc2 through the wiring kp2 and is connected to the negative electrode of the voltage dividing capacitor Cdc2 through the wiring kn2.
- the auxiliary power circuit 30 is connected to both ends of the voltage dividing capacitors Cdc1 and Cdc2.
- the voltage across the voltage dividing capacitor Cdc1 is V1
- the voltage across the voltage dividing capacitor Cdc2 is V2.
- a current flowing through the voltage dividing capacitor Cdc1, the wiring kp (part), the wiring kp1, the auxiliary power supply circuit 30, and the wiring kn1 in this order is denoted by I1.
- the current flowing through the voltage dividing capacitor Cdc2, the wiring kp2, the auxiliary power supply circuit 30, and the wiring kn2 in this order is defined as I2.
- the wirings kn1 and kp2 are illustrated as separate wirings for easy understanding, but these wirings kn1 and kp2 may be a single wiring.
- control circuit 40 includes electronic circuits such as a CPU (Central Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), and various interfaces. Then, the program stored in the ROM is read out and expanded in the RAM, and the CPU executes various processes.
- CPU Central Processing Unit
- ROM Read Only Memory
- RAM Random Access Memory
- the control circuit 40 is driven by the power input from the auxiliary power supply circuit 30 and has a function of controlling the DC-DC converter 10 and the inverter 20. That is, on / off of a switching device (not shown) included in the DC-DC converter 10 and the inverter 20 is switched by the control circuit 40.
- the control circuit 40 has a function of controlling the fan 50 described below.
- the fan 50 is driven by power supplied via the control circuit 40 and has a function of cooling the DC-DC converter 10 and the inverter 20. That is, a switching device (not shown) included in the DC-DC converter 10 and the inverter 20 is cooled by the fan 50.
- FIG. 2 is a configuration diagram of the auxiliary power supply circuit 30 included in the power conversion apparatus 100.
- the auxiliary power circuit 30 includes DC-DC converters 31 and 32 (DC-DC converters), voltage sensors 33 and 34, and a control unit 35.
- the DC-DC converter 31 is a power converter that adjusts the current input from the voltage dividing capacitor Cdc1 according to a command from the control unit 35.
- the input side of the DC-DC converter 31 is connected to the positive electrode of the voltage dividing capacitor Cdc1 (see FIG. 1) through the wiring kp1, and is connected to the negative electrode of the voltage dividing capacitor Cdc1 through the wiring kn1.
- the DC-DC converter 31 has a one-to-one correspondence with the voltage dividing capacitor Cdc1, and its input side is connected to both ends of the voltage dividing capacitor Cdc1.
- the output side of the DC-DC converter 31 is connected to the control circuit 40.
- the DC-DC converter 32 is a power converter that adjusts the current input from the voltage dividing capacitor Cdc2 according to a command from the control unit 35.
- the input side of the DC-DC converter 32 is connected to the positive electrode of the voltage dividing capacitor Cdc2 (see FIG. 1) through the wiring kp2, and is connected to the negative electrode of the voltage dividing capacitor Cdc2 through the wiring kn2.
- the DC-DC converter 32 has a one-to-one correspondence with the voltage dividing capacitor Cdc2 and its input side is connected to both ends of the voltage dividing capacitor Cdc2.
- the output side of the DC-DC converter 32 is connected to the control circuit 40.
- the DC-DC converters 31 and 32 may be well-known flyback converters, or may be other types of circuits.
- the voltage sensor 33 is a sensor that detects the voltage V1 across the voltage dividing capacitor Cdc1.
- the voltage sensor 34 is a sensor that detects the voltage V2 across the voltage dividing capacitor Cdc2. The detection values of the voltage sensors 33 and 34 are output to the control unit 35 described below.
- control unit 35 includes electronic circuits such as a CPU, a ROM, a RAM, and various interfaces.
- the control unit 35 reads out a program stored in the ROM, expands the program in the RAM, and the CPU executes various processes. It has become.
- the control unit 35 has a function of controlling the DC-DC converters 31 and 32. That is, the control unit 35 controls on / off of a switching device (not shown) included in the DC-DC converters 31 and 32 based on the detection values of the voltage sensors 33 and 34.
- FIG. 3 is an explanatory diagram relating to the operation of the auxiliary power supply circuit 30.
- the horizontal axis in FIG. 3 is the voltage V1 across the voltage dividing capacitor Cdc1.
- the vertical axis in FIG. 3 is the voltage V2 across the voltage dividing capacitor Cdc2.
- the auxiliary power supply circuit 30 performs a predetermined operation according to the magnitude relationship between the voltage V1 of the voltage dividing capacitor Cdc1 and the voltage V2 of the voltage dividing capacitor Cdc2.
- the operation of the auxiliary power supply circuit 30 will be described with reference to FIG. 3 and the flowchart of FIG.
- FIG. 4 is a flowchart of processing executed by the control unit 35 of the auxiliary power circuit 30.
- the control unit 35 reads the detection values of the voltages V1 and V2. That is, the control unit 35 reads the detected values of the voltage V1 of the voltage dividing capacitor Cdc1 and the voltage V2 of the voltage dividing capacitor Cdc2.
- step S102 the control unit 35 determines whether or not the voltage V1 of the voltage dividing capacitor Cdc1 is higher than the voltage V2 of the other voltage dividing capacitor Cdc2.
- the process of the control unit 35 proceeds to step S103.
- step S103 the control unit 35 controls the DC-DC converters 31 and 32 so that the current I1 is larger than the current I2 (see the region “I1> I2” shown in FIG. 3).
- the control unit 35 makes the on-duty of the switching device (not shown) of the DC-DC converter 31 larger than the on-duty of the switching device (not shown) of the DC-DC converter 32.
- step S104 the control unit 35 determines whether or not the voltage V2 of the voltage dividing capacitor Cdc2 is higher than the voltage V1 of the other voltage dividing capacitor Cdc1.
- the process of the control unit 35 proceeds to step S105.
- step S105 the control unit 35 controls the DC-DC converters 31 and 32 so that the current I2 is larger than the current I1 (refer to the region “I2> I1” shown in FIG. 3). As a result, the voltages of the voltage dividing capacitors Cdc1 and Cdc2 are equalized.
- control unit 35 adjusts the current I1 flowing from the voltage dividing capacitor Cdc1 to the DC-DC converter 31 based on the detection values of the voltage sensors 33 and 34, and from the voltage dividing capacitor Cdc2 to the DC-DC converter 32.
- the current I2 flowing through is adjusted.
- the auxiliary power supply circuit 30 operates to input a larger current to itself from the voltage dividing capacitor having a higher voltage among the voltage dividing capacitors Cdc1 and Cdc2.
- step S104 the process of the control unit 35 proceeds to step S106. That is, when the voltages V1 and V2 are substantially equal, the process of the control unit 35 proceeds to step S106.
- step S107 the control unit 35 determines whether or not a stop command for the power conversion apparatus 100 is input from a host controller or the like (not shown).
- command of the power converter device 100 is input (S107: Yes)
- the process of the control part 35 progresses to step S108.
- step S108 the control unit 35 stops power supply to the control circuit 40 and the like, and ends a series of processing (END).
- step S107 when the stop instruction
- the auxiliary power supply circuit 30 has both a function of a power supply for supplying power to the control circuit 40 and a function of equalizing the voltages of the voltage dividing capacitors Cdc1 and Cdc2. Therefore, the cost can be reduced compared to a configuration in which a circuit for equalizing the voltages of the voltage dividing capacitors Cdc1 and Cdc2 is provided separately.
- auxiliary power supply circuit 30 is connected to both ends of the series-connected voltage dividing capacitors Cdc1 and Cdc2, it is necessary to use a high breakdown voltage switching device (not shown) for the auxiliary power supply circuit 30.
- both ends of the voltage dividing capacitors Cdc1 and Cdc2 are connected to the auxiliary power circuit 30. Therefore, a device having a relatively low withstand voltage can be used as the switching device of the auxiliary power supply circuit 30, and as a result, the cost of the power conversion device 100 can be reduced.
- the second embodiment is different from the first embodiment in that the power conversion device 100A (see FIG. 5) is applied to the uninterruptible power supply system S (see FIG. 5).
- the configuration and the like are the same as those in the first embodiment. Therefore, a different part from 1st Embodiment is demonstrated and description is abbreviate
- FIG. 5 is a configuration diagram of an uninterruptible power supply system S to which the power conversion device 100A according to the second embodiment is applied.
- the uninterruptible power supply system S normally converts AC power from the AC power supply G into AC power having a predetermined amplitude and frequency, and also converts DC power from the battery B into predetermined AC power when the AC power supply G fails.
- the uninterruptible power supply system S includes a power conversion device 100A and a battery B.
- the power conversion device 100A includes a converter 60 (power conversion circuit, AC / DC converter), an inverter 70, and a DC-DC converter 80 (power conversion circuit, DC-DC converter).
- the power conversion device 100A includes voltage dividing capacitors Cdc1 and Cdc2, an auxiliary power supply circuit 30, a control circuit 40, and a fan 50.
- Converter 60 is a power converter that converts a three-phase AC voltage input from AC power supply G into DC voltage Vdc.
- the inverter 70 is a power converter that converts the DC voltage Vdc applied from the converter 60 into an AC voltage and outputs the AC voltage to the AC load H. As shown in FIG. 5, the inverter 70 is connected to the converter 60 via a positive-side wiring kp and a negative-side wiring kn.
- the DC-DC converter 80 is a chopper circuit that converts the DC voltage of the battery B into a predetermined DC voltage Vdc when the AC power supply G fails. As shown in FIG. 5, the DC-DC converter 80 has an input side connected to the battery B and an output side connected to the wirings kp and kn.
- the voltage dividing capacitors Cdc1 and Cdc2 are capacitors that divide the DC voltage Vdc applied from the converter 60 (the DC-DC converter 80 in the event of a power failure), and are connected in series with each other. As shown in FIG. 5, the voltage dividing capacitors Cdc1 and Cdc2 are connected to the output side (DC side) of the converter 60 and the DC-DC converter 80 and to the input side (DC side) of the inverter 70. .
- the auxiliary power circuit 30 has the same configuration as that of the first embodiment, and is connected to both ends of the voltage dividing capacitor Cdc1 and is connected to both ends of the voltage dividing capacitor Cdc2.
- the operation of the auxiliary power supply circuit 30 is also the same as that of the first embodiment (see FIG. 4), and thus the description thereof is omitted. Further, since the control circuit 40 and the fan 50 have the same configuration as that of the first embodiment, description thereof is omitted.
- the battery B functions as a power source when the AC power source G fails, and is connected to the input side of the DC-DC converter 80.
- the auxiliary power supply circuit 30 can supply power to the control circuit 40 while equalizing the voltages of the voltage dividing capacitors Cdc1 and Cdc2. Therefore, energy loss in the auxiliary power supply circuit 30 can be reduced, and the cost of the power conversion device 100A can be reduced. In addition, even if the AC power supply G fails, the power supply to the AC load H can be continued by operating each circuit using the power of the battery B.
- the third embodiment differs from the first embodiment in the configuration of the auxiliary power supply circuit 30B (see FIG. 6), but the other (the overall configuration of the power conversion device 100: see FIG. 1) is the same as that in the first embodiment. It is the same. Therefore, a different part from 1st Embodiment is demonstrated and description is abbreviate
- FIG. 6 is a configuration diagram of an auxiliary power circuit 30B included in the power conversion device.
- the auxiliary power supply circuit 30B is a flyback type comprising an iron core T that is a magnetic circuit, primary side circuits J11 and J12, secondary side circuits J20 to J24, and a control unit M. It is a power supply circuit.
- the primary windings N1 and N2 are wound on the primary side of the iron core T, and the secondary windings N20 to N24 are wound on the secondary side.
- the iron core T, the primary windings N1 and N2, and the secondary windings N20 to N24 constitute a transformer (transformer).
- the primary side circuit J11 is a circuit to which the voltage V1 of the voltage dividing capacitor Cdc1 (see FIG. 1) is applied. As shown in FIG. 6, the primary circuit J11 includes a primary capacitor C1, a primary winding N1, a primary diode Db1, a switching element Q1, a freewheeling diode D1, and a snubber circuit Sn1. ing.
- the primary capacitor C1 is a capacitor for suppressing voltage fluctuation when the switching element Q1 is turned off.
- the primary capacitor C1 is a capacitor different from the smoothing voltage dividing capacitor Cdc1 (see FIG. 1).
- the positive electrode of the primary capacitor C1 is connected to the positive electrode of the voltage dividing capacitor Cdc1 through the wiring kp1.
- the negative electrode of the primary capacitor C1 is connected to the negative electrode of the voltage dividing capacitor Cdc1 through the wiring kn1.
- a “series connection body” in which the primary winding N1, the primary diode Db1, and the switching element Q1 are sequentially connected in series is connected in parallel to the primary capacitor C1. That is, the above-described “series connection body” has a one-to-one correspondence with the voltage dividing capacitor Cdc1 (see FIG. 1), and both ends thereof are connected to both ends of the voltage dividing capacitor Cdc1.
- the primary winding N1 has one end connected to the positive electrode of the primary capacitor C1 and the other end connected to the anode of the primary diode Db1.
- the switching element Q1 has a drain connected to the cathode of the primary diode Db1, and a source connected to the negative electrode of the primary capacitor C1.
- a free-wheeling diode D1 is connected in antiparallel to the switching element Q1.
- a MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
- another type of switching element may be used.
- the primary diode Db1 is connected so as to allow a current from the positive electrode of the voltage dividing capacitor Cdc1 (see FIG. 1) to the self through the wiring kp1 and the like, and prevent a reverse current.
- the provision of the primary diode Db1 (and the other primary diode Db2) is one of the main features of the third embodiment.
- the snubber circuit Sn1 is a circuit that suppresses a surge voltage generated between the drain and source of the switching element Q1.
- the snubber circuit Sn1 has a one-to-one correspondence with the primary winding N1 and is connected in parallel to the primary winding N1.
- the snubber circuit Sn1 includes a diode Ds1, a capacitor Cs1, and a resistor Rs1.
- a diode Ds1 is connected in series to a “parallel connection body” in which a capacitor Cs1 and a resistor Rs1 are connected in parallel.
- the anode of the diode Ds1 is connected to the anode of the primary diode Db1, and the cathode is connected to the “parallel connection body” described above.
- the primary side circuit J12 is a circuit to which the voltage V2 of the voltage dividing capacitor Cdc2 (see FIG. 1) is applied.
- the primary side circuit J12 has the same configuration as the primary side circuit J11 described above.
- a “series connection body” in which a primary winding N2, a primary diode Db2, and a switching element Q2 are sequentially connected in series is connected in parallel to the primary capacitor C2. That is, the above-described “series connection body” has a one-to-one correspondence with the voltage dividing capacitor Cdc2 (see FIG. 1), and both ends thereof are connected to both ends of the voltage dividing capacitor Cdc2.
- the primary diode Db2 is connected so as to allow a current from the positive electrode of the voltage dividing capacitor Cdc2 toward itself through the wiring kp2 and the like and to block a reverse current.
- the secondary side circuit J21 includes a secondary winding N21, a secondary diode D21, and a secondary capacitor C21. As shown in FIG. 6, the secondary winding N21 and the secondary diode D21 are connected in series. A secondary capacitor C21 is connected in parallel to the secondary winding N21 and the secondary diode D21.
- the secondary diode D21 has an anode connected to the secondary winding N21 and a cathode connected to the positive electrode of the secondary capacitor C21. That is, the secondary diode D21 is connected so as to allow a current from the secondary winding N21 toward the positive electrode of the secondary capacitor C21 through itself and prevent a reverse current. Electric power is output from both ends of the secondary capacitor C21.
- the secondary side circuits J20, J22 to J24 have the same configuration as the secondary side circuit J21 described above, description thereof is omitted. Note that power is supplied to the control circuit 40 (see FIG. 1) from one or more of the secondary side circuits J21 to J24. Note that power may be supplied from one or more of the secondary side circuits J21 to J24 to other devices such as the fan 50 (see FIG. 1).
- the control unit M is configured to include an electronic circuit such as an IC (not shown), reads a program stored in the ROM, develops it in the RAM, and the CPU executes various processes. As shown in FIG. 6, the control unit M is connected to both ends of the secondary capacitor C20. The controller M controls the on / off of the switching elements Q1, Q2 so that the voltage V20 of the secondary capacitor C20 becomes a predetermined value.
- FIG. 7A is an explanatory diagram when the switching elements Q1 and Q2 are turned on when the voltage V1 is higher than the voltage V2.
- the broken-line arrow shown to Fig.7 (a), (b) represents the flow of an electric current.
- FIG. 7A when the control unit M turns on the switching elements Q1 and Q2, a voltage substantially equal to the voltage V1 is applied to the primary winding N1.
- the primary diode Db1 becomes forward biased, and the current flowing through the primary winding N1 increases.
- predetermined energy is accumulated in the exciting inductance of the transformer constituted by the iron core T, the primary windings N1, N2, the secondary winding N21, and the like.
- the primary windings N1 and N2 have substantially the same number of turns and are wound around a common iron core T. Accordingly, a voltage V1 of the same level as that of the primary winding N1 is generated in the primary winding N2. Since the voltage V1 is higher than the voltage V2 applied to the primary capacitor C2, the primary diode Db2 is reverse-biased. Therefore, as shown in FIG. 7A, no current flows through the primary winding N2.
- the control unit M turns off the switching elements Q1 and Q2 (that is, switches to the off state).
- FIG. 7B is an explanatory diagram showing a state immediately after the switching elements Q1 and Q2 are turned off when the voltage V1 is higher than the voltage V2.
- switching elements Q1, Q2 are turned off, a voltage is generated in secondary windings N20-N24, and secondary diodes D20-D24 become forward biased and become conductive.
- the energy accumulated in the magnetizing inductance of the transformer is released, and power is supplied to the control circuit 40 (see FIG. 1) via the secondary capacitors C20 to C24.
- FIG. 7C is an explanatory diagram showing a state after energy is released from the transformer when the voltage V1 is higher than the voltage V2. If the OFF state continues for a predetermined time after the switching elements Q1 and Q2 are turned off, all the energy stored in the exciting inductance of the transformer is released. As a result, no current flows through the secondary windings N20 to N24. At this time, no current flows through the primary windings N1 and N2.
- the state returns to the state of FIG.
- the control unit M repeats the process of turning on the switching elements Q1, Q2 at the same timing and then turning off at the same timing. That is, the switching elements Q1 and Q2 included in the auxiliary power supply circuit 30B operate so as to have a period in which the auxiliary power supply circuit 30B is simultaneously in an on state and a period in which the auxiliary power supply circuit 30B is in an off state.
- the switching element Q1 is also in the on state when the other switching element Q2 is in the on state, and is also in the off state when the other switching element Q2 is in the off state.
- FIG. 8A is an explanatory diagram when the switching elements Q1 and Q2 are turned on when the voltage V2 is higher than the voltage V1.
- the control unit M turns on the switching elements Q1 and Q2
- a voltage substantially equal to the voltage V2 is applied to the primary winding N2.
- the primary diode Db2 becomes forward biased, and the current flowing through the primary winding N2 increases.
- predetermined energy is accumulated in the exciting inductance of the transformer constituted by the iron core T, the primary windings N1, N2, the secondary winding N21, and the like.
- the primary windings N1 and N2 have substantially the same number of turns and are wound around a common iron core T. Accordingly, a voltage V2 of the same level as that of the primary winding N2 is generated in the primary winding N1. Since this voltage V2 is higher than the voltage V1 applied to the primary capacitor C1, the primary diode Db1 is reverse-biased. Therefore, as shown in FIG. 8A, no current flows through the primary winding N1.
- FIG. 8B is an explanatory diagram showing a state immediately after the switching elements Q1 and Q2 are turned off when the voltage V2 is higher than the voltage V1.
- switching elements Q1 and Q2 are turned off, secondary diodes D20 to D24 conduct, and current flows through secondary capacitors C20 to C24.
- FIG. 8C is an explanatory diagram showing a state after energy is released from the transformer when the voltage V2 is higher than the voltage V1. If the OFF state continues for a predetermined time after the switching elements Q1 and Q2 are turned off, all the energy stored in the exciting inductance of the transformer is released. As a result, no current flows through the secondary windings N20 to N24.
- the state returns to the state of FIG. In this way, the control unit M repeats the process of turning on the switching elements Q1, Q2 at the same timing and then turning off at the same timing.
- a current flows through the primary winding N2, but no current flows through the primary winding N1. That is, current flows from the voltage dividing capacitor Cdc2 (see FIG. 1), but no current flows from the voltage dividing capacitor Cdc1 (see FIG. 1). As a result, the voltage V2 of the voltage dividing capacitor Cdc2 is reduced and the voltages V1 and V2 are equalized.
- FIG. 9A is an explanatory diagram when the switching elements Q1 and Q2 are turned on when the voltages V1 and V2 are substantially equal. As shown in FIG. 9A, when the control unit M turns on the switching elements Q1 and Q2, the voltages V1 and V2 are substantially equal. Therefore, both the primary diodes Db1 and Db2 become forward biased, and the primary Current flows through both windings N1 and N2.
- FIG. 9B is an explanatory diagram showing a state immediately after the switching elements Q1 and Q2 are turned off when the voltages V1 and V2 are substantially equal.
- switching elements Q1, Q2 are turned off, secondary diodes D20-D24 are turned on, and current is supplied to secondary capacitors C20-C24.
- FIG. 9C is an explanatory diagram showing a state after energy is released from the transformer when the voltages V1 and V2 are substantially equal. If the OFF state continues for a predetermined time after the switching elements Q1 and Q2 are turned off, all the energy stored in the exciting inductance of the transformer is released. As a result, no current flows through the secondary windings N20 to N24.
- the state returns to the state of FIG. In this way, the control unit M repeats the process of turning on the switching elements Q1, Q2 at the same timing and then turning off at the same timing. Thereby, the state where the voltages V1 and V2 are substantially equal is maintained.
- FIGS. 7C, 8C, and 9C may be omitted. In this case, even if the switching elements Q1 and Q2 are maintained in the OFF state, the current continues to flow to the secondary side due to the exciting inductance of the transformer.
- the auxiliary power supply circuit 30B performs the same operation. That is, switching the switching elements Q1, Q2 on and off at the same timing results in equalization of the voltages V1, V2 regardless of the magnitude relationship between the voltages V1, V2. That is, a current flows from the higher voltage of the voltage dividing capacitors Cdc1 and Cdc2 to the primary side. This is due to the characteristic that approximately the same voltage is generated in the primary windings N1 and N2, and the characteristic of the primary diodes Db1 and Db2.
- control unit M operates the switching elements Q1 and Q2 with the same gate pattern so that any one of the voltages V20 to V24 output from the secondary side is a predetermined value. Therefore, the voltages of the voltage dividing capacitors Cdc1 and Cdc2 can be equalized by a simple control method similar to that of a conventional flyback converter having no primary diodes Db1 and Db2.
- the fourth embodiment differs from the first embodiment in the configuration of the auxiliary power supply circuit 30C (see FIG. 10), but the other embodiments (the overall configuration of the power conversion device 100: see FIG. 1) are the first embodiment. It is the same. Therefore, a different part from 1st Embodiment is demonstrated and description is abbreviate
- FIG. 10 is a configuration diagram of an auxiliary power circuit 30C included in the power conversion device according to the fourth embodiment.
- the auxiliary power supply circuit 30C includes a forward power supply including an iron core T, which is a magnetic circuit, primary circuits P11 and P12, secondary circuits P20 to P24, and a control unit M. Circuit.
- a transformer is constituted by the iron core T, the primary windings N1 and N2, and the secondary windings N20 to N24.
- the primary side circuit P11 is a circuit to which the voltage V1 of the voltage dividing capacitor Cdc1 (see FIG. 1) is applied. As shown in FIG. 10, the primary circuit P11 includes a primary capacitor C1, a primary winding N1, a primary diode Db1, a switching element Q1, a freewheeling diode D1, and a snubber circuit Sn4. Yes.
- the elements other than the snubber circuit Sn4 are the same as the primary side circuit J11 (see FIG. 6) described in the third embodiment, and thus the description thereof is omitted.
- a snubber circuit Sn4 shown in FIG. 10 is an active clamp type circuit that suppresses a surge voltage generated between the drain and source of the switching element Q1, and corresponds to the primary winding N1 in a one-to-one correspondence.
- the line N1 is connected in parallel.
- the snubber circuit Sn4 includes a capacitor Cs4, a switching element Q4, and a free wheeling diode D4.
- a capacitor Cs4 and a switching element Q4 are connected in series.
- the switching element Q4 has a drain connected to the negative electrode of the capacitor Cs4 and a source connected to the anode of the primary diode Db1.
- the switching element Q4 is connected with a freewheeling diode D4 in antiparallel.
- the primary side circuit P12 is a circuit to which the voltage V2 of the voltage dividing capacitor Cdc2 (see FIG. 1) is applied. Since the configuration of the primary side circuit P12 is the same as the primary side circuit P11 described above, the description thereof is omitted.
- the secondary side circuit P21 includes a secondary winding N21, secondary diodes D21 and D25, a secondary capacitor C21, and an inductor L21. As shown in FIG. 10, a secondary winding N21 and a secondary diode D21 are connected in series, and a secondary diode D25 is connected in parallel to the secondary winding N21 and the secondary diode D21.
- the secondary diode D21 has an anode connected to the secondary winding N21 and a cathode connected to the cathode of another secondary diode D25.
- a secondary capacitor C21 is connected in parallel to the secondary diode D25 via an inductor L21 connected to the cathodes of the secondary diodes D21 and D25. Both ends of the secondary capacitor C21 are secondary output terminals. Since the secondary side circuits P20, P22 to P24 have the same configuration as the secondary side circuit J21 described above, description thereof is omitted.
- the switching elements Q1 and Q4 are alternately switched on and off by the control unit M. That is, when one of the switching elements Q1 and Q4 is on, the control unit M turns off the other. Further, the control unit M provides a predetermined dead time (period in which both the switching elements Q1 and Q4 are in the off state) when the switching elements Q1 and Q4 are switched on and off.
- the switching elements Q2 and Q5 are similarly switched on and off in the same manner.
- control unit M repeats the process of turning off the switching elements Q1 and Q2 at the same timing and then turning off at the same timing. That is, the switching elements Q1 and Q2 included in the auxiliary power supply circuit 30C operate so as to have a period in which the auxiliary power supply circuit 30C is in the on state and a period in which the auxiliary power supply circuit 30C is in the off state at the same time.
- the switching element Q1 is also in the on state when the other switching element Q2 is in the on state, and is also in the off state when the other switching element Q2 is in the off state.
- the secondary diode D21 is forward biased and another secondary diode D25 is reverse biased.
- a current flows through the inductor L21, and power is supplied to the control circuit 40 and the like (see FIG. 1) via the secondary capacitors C20 to C24.
- auxiliary power supply circuit 30C is a forward type, higher efficiency can be achieved and a large output power can be obtained compared to the third embodiment using the flyback type auxiliary power supply circuit 30B (see FIG. 6). be able to.
- FIG. 11 is a configuration diagram of an auxiliary power circuit 30D included in a power conversion device according to a modification.
- the auxiliary power circuit 30D includes primary circuits J11, J12, and J13.
- the primary side circuits J11, J12, and J13 are connected to three voltage dividing capacitors on a one-to-one basis.
- the control unit M repeats the process of turning on the switching elements Q1, Q2, and Q3 at the same timing and then turning off at the same timing.
- the voltages V1, V2, and V3 of the three voltage dividing capacitors (not shown) are equalized.
- the number of voltage dividing capacitors (not shown) and the primary side circuit J11 may be three as described above, or may be four or more. The same can be said for the first, second, and fourth embodiments.
- the present invention is not limited to this.
- a voltage sensor (not shown) for detecting the voltages V1 and V2
- the control unit M repeatedly turns on and off the switching element Q1, thereby switching the switching element Q2 may be maintained in the off state.
- the configuration in which the freewheeling diodes D1 and D2 are provided has been described.
- the freewheeling diodes D1 and D2 may be omitted. This is because almost no current flows through the freewheeling diodes D1 and D2 in the normal control (see FIGS. 7 to 9).
- the fourth embodiment when using the element which has the reverse blocking capability which primary diode Db1 and Db2 were carrying out as switching element Q1 and Q2 (refer FIG. 6), you may abbreviate
- the case where the numbers of turns of the primary windings N1 and N2 are substantially equal has been described.
- the target voltage division ratio between the voltage V1 and the voltage V2 that is, the voltage dividing capacitors Cdc1 and Cdc2
- the primary windings N1, N2 may have different numbers of turns.
- the voltage division ratio between the voltages V1 and V2 is substantially equal to the turn ratio of the primary windings N1 and N2.
- flyback circuit described in the third embodiment and the forward circuit described in the fourth embodiment (see FIG. 10) are examples, and other known flyback circuits or A forward type circuit may be used.
- the configuration in which the primary winding N1, the primary diode Db1, and the switching element Q1 are sequentially connected in series has been described.
- the present invention is not limited to this.
- the primary winding N1, the switching element Q1, and the primary diode Db1 may be sequentially connected in series. The same applies to the fourth embodiment.
- each embodiment can be applied to a multi-level inverter or the like in addition to a PCS (Power Conditioning System) for photovoltaic power generation and an uninterruptible power system (UPS).
- PCS Power Conditioning System
- UPS uninterruptible power system
- the uninterruptible power supply system S may be configured to include the auxiliary power supply circuit 30B illustrated in FIG. 6 by combining the second embodiment and the third embodiment. Further, for example, the uninterruptible power supply system S may include the auxiliary power supply circuit 30C illustrated in FIG. 10 by combining the second embodiment and the fourth embodiment.
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Abstract
Provided is a low cost power conversion device having little energy loss. A power conversion device (100) is provided with: an inverter (20), etc., that performs power conversion; voltage dividing capacitors (Cdc1, Cdc2) connected to a direct current side of the inverter (20), etc., that perform voltage division of DC voltage applied from the direct current side; and an auxiliary power supply circuit (30) connected to both ends respectively of the voltage dividing capacitors (Cdc1, Cdc2), that inputs to itself a larger current from the voltage dividing capacitor with the higher voltage among the voltage dividing capacitors (Cdc1, Cdc2).
Description
本発明は、電力変換を行う電力変換装置に関する。
The present invention relates to a power conversion device that performs power conversion.
太陽電池で発電された直流電力を交流電力に変換する太陽光発電システムや、モータを駆動するインバータ装置の他、停電時にも負荷への電力供給を継続する無停電電源システム等が知られている。前記した各システムには、通常、直流電圧を平滑化するコンデンサが設置されている。この直流電圧がコンデンサの定格電圧よりも高い場合や、直流電圧を分圧した電圧を得る場合には、直列接続された複数のコンデンサを設けるようにしている。
Known are photovoltaic power generation systems that convert DC power generated by solar cells into AC power, inverter devices that drive motors, and uninterruptible power supply systems that continue to supply power to loads even during power outages. . Each of the above systems is usually provided with a capacitor that smoothes the DC voltage. When this DC voltage is higher than the rated voltage of the capacitor or when a voltage obtained by dividing the DC voltage is obtained, a plurality of capacitors connected in series are provided.
しかしながら、複数のコンデンサが直列接続された構成において、各コンデンサの漏れ電流に差がある場合には、各コンデンサの電圧がアンバランスになる。その結果、コンデンサの電圧が、そのコンデンサの定格電圧を超える可能性がある。
However, in a configuration in which a plurality of capacitors are connected in series, when there is a difference in the leakage current of each capacitor, the voltage of each capacitor becomes unbalanced. As a result, the voltage of the capacitor may exceed the rated voltage of the capacitor.
このような問題に関して特許文献1には、直列接続された複数のコンデンサの漏れ電流の差をトランジスタ及び抵抗によって補償し、各コンデンサの電圧バランスを均等化することが記載されている。
Regarding such a problem, Patent Document 1 describes that a difference in leakage current between a plurality of capacitors connected in series is compensated by a transistor and a resistor to equalize the voltage balance of each capacitor.
また、特許文献2には、直列接続された複数のコンデンサを電源装置によって充電し、各コンデンサの端子間電圧を均等化することが記載されている。
Also, Patent Document 2 describes that a plurality of capacitors connected in series are charged by a power supply device, and the voltage between terminals of each capacitor is equalized.
しかしながら、特許文献1に記載の技術では、コンデンサの電圧の均等化に伴う電流をトランジスタ及び抵抗に流すことで電力が消費されるため、エネルギの損失が大きくなりやすいという事情がある。
また、特許文献2に記載の技術では、コンデンサの電圧を均等化するための電源装置が必要となるため、コストの増加を招いてしまう。 However, in the technique described inPatent Document 1, since power is consumed by causing a current accompanying equalization of the capacitor voltage to flow through the transistor and the resistor, energy loss tends to increase.
Further, the technique described in Patent Document 2 requires a power supply device for equalizing the capacitor voltage, which increases costs.
また、特許文献2に記載の技術では、コンデンサの電圧を均等化するための電源装置が必要となるため、コストの増加を招いてしまう。 However, in the technique described in
Further, the technique described in Patent Document 2 requires a power supply device for equalizing the capacitor voltage, which increases costs.
そこで、本発明は、エネルギの損失が小さく、低コストな電力変換装置を提供することを課題とする。
Therefore, an object of the present invention is to provide a low-cost power conversion device with low energy loss.
前記課題を解決するために、本発明に係る電力変換装置は、電力変換を行う電力変換回路と、前記電力変換回路の直流側に接続され、前記直流側から印加される直流電圧を分圧する複数の分圧コンデンサと、複数の前記分圧コンデンサのそれぞれの両端に接続され、複数の前記分圧コンデンサのうち、電圧のより高い分圧コンデンサから、より大きな電流を自身に入力する電源回路と、を備えることを特徴とする。
In order to solve the above problems, a power conversion device according to the present invention includes a power conversion circuit that performs power conversion, and a plurality of DC converters that are connected to a DC side of the power conversion circuit and that divide a DC voltage applied from the DC side. And a power supply circuit that is connected to both ends of each of the plurality of voltage dividing capacitors, and inputs a larger current to itself from a voltage dividing capacitor having a higher voltage among the plurality of voltage dividing capacitors, It is characterized by providing.
本発明によれば、エネルギの損失が小さく、低コストな電力変換装置を提供できる。
According to the present invention, it is possible to provide a low-cost power conversion device with low energy loss.
≪第1実施形態≫
<電力変換装置の構成>
図1は、第1実施形態に係る電力変換装置100を含む構成図である。
電力変換装置100は、太陽電池Eから入力される直流電力を所定の交流電力に変換し、この交流電力を電力系統Fに出力する装置である。
図1に示すように、電力変換装置100は、DC-DCコンバータ10(電力変換回路、直流-直流変換器)と、分圧コンデンサCdc1,Cdc2と、インバータ20(電力変換回路)と、を備えている。また、電力変換装置100は、前記した構成の他に、補助電源回路30(電源回路)と、制御回路40(電力の供給対象)と、ファン50(電力の供給対象)と、を備えている。 << First Embodiment >>
<Configuration of power converter>
FIG. 1 is a configuration diagram including apower conversion device 100 according to the first embodiment.
Thepower conversion device 100 is a device that converts the DC power input from the solar cell E into predetermined AC power and outputs the AC power to the power system F.
As shown in FIG. 1, thepower conversion apparatus 100 includes a DC-DC converter 10 (power conversion circuit, DC-DC converter), voltage dividing capacitors Cdc1, Cdc2, and an inverter 20 (power conversion circuit). ing. The power conversion device 100 includes an auxiliary power supply circuit 30 (power supply circuit), a control circuit 40 (power supply target), and a fan 50 (power supply target) in addition to the configuration described above. .
<電力変換装置の構成>
図1は、第1実施形態に係る電力変換装置100を含む構成図である。
電力変換装置100は、太陽電池Eから入力される直流電力を所定の交流電力に変換し、この交流電力を電力系統Fに出力する装置である。
図1に示すように、電力変換装置100は、DC-DCコンバータ10(電力変換回路、直流-直流変換器)と、分圧コンデンサCdc1,Cdc2と、インバータ20(電力変換回路)と、を備えている。また、電力変換装置100は、前記した構成の他に、補助電源回路30(電源回路)と、制御回路40(電力の供給対象)と、ファン50(電力の供給対象)と、を備えている。 << First Embodiment >>
<Configuration of power converter>
FIG. 1 is a configuration diagram including a
The
As shown in FIG. 1, the
DC-DCコンバータ10は、直流電圧を昇圧又は降圧する電力変換器である。すなわち、DC-DCコンバータ10は、太陽電池Eから印加される電圧を所定の直流電圧Vdcに変換する機能を有している。
The DC-DC converter 10 is a power converter that boosts or lowers a DC voltage. That is, the DC-DC converter 10 has a function of converting the voltage applied from the solar cell E into a predetermined DC voltage Vdc.
インバータ20は、直流電圧を交流電圧に変換する電力変換器である。すなわち、インバータ20は、後記する分圧コンデンサCdc1,Cdc2によって平滑化された直流電圧を交流電圧に変換し、この交流電圧を電力系統Fに出力する機能を有している。図1に示すように、インバータ20は、正側の配線kp及び負側の配線knを介して、DC-DCコンバータ10に接続されている。
The inverter 20 is a power converter that converts a DC voltage into an AC voltage. That is, the inverter 20 has a function of converting a DC voltage smoothed by voltage dividing capacitors Cdc1 and Cdc2 described later into an AC voltage and outputting the AC voltage to the power system F. As shown in FIG. 1, the inverter 20 is connected to the DC-DC converter 10 via a positive-side wiring kp and a negative-side wiring kn.
分圧コンデンサCdc1,Cdc2は、DC-DCコンバータ10から印加される直流電圧Vdcを分圧するコンデンサであり、互いに直列接続されている。また、分圧コンデンサCdc1,Cdc2は、前記した直流電圧Vdcを平滑化する機能も有している。
The voltage dividing capacitors Cdc1 and Cdc2 are capacitors that divide the DC voltage Vdc applied from the DC-DC converter 10, and are connected in series with each other. The voltage dividing capacitors Cdc1 and Cdc2 also have a function of smoothing the DC voltage Vdc.
図1に示すように、分圧コンデンサCdc1,Cdc2は、DC-DCコンバータ10の出力側に接続されるとともに、インバータ20の入力側(直流側)に接続されている。また、一方の分圧コンデンサCdc1の正極は配線kpに接続され、他方の分圧コンデンサCdc2の負極は配線knに接続されている。本実施形態では、一例として、分圧コンデンサCdc1,Cdc2の定格電圧が略等しいものとして説明する。
As shown in FIG. 1, the voltage dividing capacitors Cdc1 and Cdc2 are connected to the output side of the DC-DC converter 10 and to the input side (DC side) of the inverter 20. The positive electrode of one voltage dividing capacitor Cdc1 is connected to the wiring kp, and the negative electrode of the other voltage dividing capacitor Cdc2 is connected to the wiring kn. In the present embodiment, as an example, it is assumed that the rated voltages of the voltage dividing capacitors Cdc1 and Cdc2 are substantially equal.
補助電源回路30は、分圧コンデンサCdc1,Cdc2から入力される直流電力を用いて、制御回路40に電力を供給する回路である。また、補助電源回路30は、制御回路40を介してファン50に電力を供給する機能も有している。
The auxiliary power supply circuit 30 is a circuit that supplies power to the control circuit 40 using DC power input from the voltage dividing capacitors Cdc1 and Cdc2. The auxiliary power supply circuit 30 also has a function of supplying power to the fan 50 via the control circuit 40.
図1に示すように、補助電源回路30は、配線kp1を介して分圧コンデンサCdc1の正極に接続されるとともに、配線kn1を介して分圧コンデンサCdc1の負極に接続されている。
また、補助電源回路30は、配線kp2を介して分圧コンデンサCdc2の正極に接続されるとともに、配線kn2を介して分圧コンデンサCdc2の負極に接続されている。このように、補助電源回路30は、分圧コンデンサCdc1,Cdc2のそれぞれの両端に接続されている。 As shown in FIG. 1, the auxiliarypower supply circuit 30 is connected to the positive electrode of the voltage dividing capacitor Cdc1 through the wiring kp1, and is connected to the negative electrode of the voltage dividing capacitor Cdc1 through the wiring kn1.
The auxiliarypower supply circuit 30 is connected to the positive electrode of the voltage dividing capacitor Cdc2 through the wiring kp2 and is connected to the negative electrode of the voltage dividing capacitor Cdc2 through the wiring kn2. As described above, the auxiliary power circuit 30 is connected to both ends of the voltage dividing capacitors Cdc1 and Cdc2.
また、補助電源回路30は、配線kp2を介して分圧コンデンサCdc2の正極に接続されるとともに、配線kn2を介して分圧コンデンサCdc2の負極に接続されている。このように、補助電源回路30は、分圧コンデンサCdc1,Cdc2のそれぞれの両端に接続されている。 As shown in FIG. 1, the auxiliary
The auxiliary
図1に示すように、分圧コンデンサCdc1の両端の電圧をV1とし、分圧コンデンサCdc2の両端の電圧をV2とする。また、分圧コンデンサCdc1、配線kp(一部)、配線kp1、補助電源回路30、及び配線kn1を順次に介して流れる電流をI1とする。また、分圧コンデンサCdc2、配線kp2、補助電源回路30、及び配線kn2を順次に介して流れる電流をI2とする。
As shown in FIG. 1, the voltage across the voltage dividing capacitor Cdc1 is V1, and the voltage across the voltage dividing capacitor Cdc2 is V2. Further, a current flowing through the voltage dividing capacitor Cdc1, the wiring kp (part), the wiring kp1, the auxiliary power supply circuit 30, and the wiring kn1 in this order is denoted by I1. Further, the current flowing through the voltage dividing capacitor Cdc2, the wiring kp2, the auxiliary power supply circuit 30, and the wiring kn2 in this order is defined as I2.
なお、図1では、説明を分かりやすくするために配線kn1,kp2を別々の配線として図示しているが、これらの配線kn1,kp2を1本の配線としてもよい。
Note that in FIG. 1, the wirings kn1 and kp2 are illustrated as separate wirings for easy understanding, but these wirings kn1 and kp2 may be a single wiring.
制御回路40は、図示はしないが、CPU(Central Processing Unit)、ROM(Read Only Memory)、RAM(Random Access Memory)、各種インタフェース等の電子回路を含んで構成されている。そして、ROMに記憶されたプログラムを読み出してRAMに展開し、CPUが各種処理を実行するようになっている。
Although not shown, the control circuit 40 includes electronic circuits such as a CPU (Central Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), and various interfaces. Then, the program stored in the ROM is read out and expanded in the RAM, and the CPU executes various processes.
制御回路40は、補助電源回路30から入力される電力によって駆動し、DC-DCコンバータ10やインバータ20を制御する機能を有している。つまり、DC-DCコンバータ10やインバータ20が備えるスイッチングデバイス(図示せず)のオン・オフが、制御回路40によって切り替えられる。その他、制御回路40は、次に説明するファン50を制御する機能も有している。
The control circuit 40 is driven by the power input from the auxiliary power supply circuit 30 and has a function of controlling the DC-DC converter 10 and the inverter 20. That is, on / off of a switching device (not shown) included in the DC-DC converter 10 and the inverter 20 is switched by the control circuit 40. In addition, the control circuit 40 has a function of controlling the fan 50 described below.
ファン50は、制御回路40を介して供給される電力によって駆動し、DC-DCコンバータ10やインバータ20を冷却する機能を有している。つまり、DC-DCコンバータ10やインバータ20が備えるスイッチングデバイス(図示せず)が、ファン50によって冷却される。
The fan 50 is driven by power supplied via the control circuit 40 and has a function of cooling the DC-DC converter 10 and the inverter 20. That is, a switching device (not shown) included in the DC-DC converter 10 and the inverter 20 is cooled by the fan 50.
<補助電源回路の構成>
図2は、電力変換装置100が備える補助電源回路30の構成図である。
図2に示すように、補助電源回路30は、DC-DCコンバータ31,32(直流‐直流変換器)と、電圧センサ33,34と、制御部35と、を備えている。 <Configuration of auxiliary power circuit>
FIG. 2 is a configuration diagram of the auxiliarypower supply circuit 30 included in the power conversion apparatus 100.
As shown in FIG. 2, theauxiliary power circuit 30 includes DC-DC converters 31 and 32 (DC-DC converters), voltage sensors 33 and 34, and a control unit 35.
図2は、電力変換装置100が備える補助電源回路30の構成図である。
図2に示すように、補助電源回路30は、DC-DCコンバータ31,32(直流‐直流変換器)と、電圧センサ33,34と、制御部35と、を備えている。 <Configuration of auxiliary power circuit>
FIG. 2 is a configuration diagram of the auxiliary
As shown in FIG. 2, the
DC-DCコンバータ31は、制御部35からの指令によって、分圧コンデンサCdc1から自身に入力される電流を調整する電力変換器である。DC-DCコンバータ31の入力側は、配線kp1を介して分圧コンデンサCdc1(図1参照)の正極に接続されるとともに、配線kn1を介して分圧コンデンサCdc1の負極に接続されている。このように、DC-DCコンバータ31は、分圧コンデンサCdc1と一対一で対応して、その入力側が分圧コンデンサCdc1の両端に接続されている。また、DC-DCコンバータ31の出力側は、制御回路40に接続されている。
The DC-DC converter 31 is a power converter that adjusts the current input from the voltage dividing capacitor Cdc1 according to a command from the control unit 35. The input side of the DC-DC converter 31 is connected to the positive electrode of the voltage dividing capacitor Cdc1 (see FIG. 1) through the wiring kp1, and is connected to the negative electrode of the voltage dividing capacitor Cdc1 through the wiring kn1. In this manner, the DC-DC converter 31 has a one-to-one correspondence with the voltage dividing capacitor Cdc1, and its input side is connected to both ends of the voltage dividing capacitor Cdc1. The output side of the DC-DC converter 31 is connected to the control circuit 40.
DC-DCコンバータ32は、制御部35からの指令によって、分圧コンデンサCdc2から自身に入力される電流を調整する電力変換器である。DC-DCコンバータ32の入力側は、配線kp2を介して分圧コンデンサCdc2(図1参照)の正極に接続されるとともに、配線kn2を介して分圧コンデンサCdc2の負極に接続されている。このように、DC-DCコンバータ32は、分圧コンデンサCdc2と一対一で対応して、その入力側が分圧コンデンサCdc2の両端に接続されている。また、DC-DCコンバータ32の出力側は、制御回路40に接続されている。
The DC-DC converter 32 is a power converter that adjusts the current input from the voltage dividing capacitor Cdc2 according to a command from the control unit 35. The input side of the DC-DC converter 32 is connected to the positive electrode of the voltage dividing capacitor Cdc2 (see FIG. 1) through the wiring kp2, and is connected to the negative electrode of the voltage dividing capacitor Cdc2 through the wiring kn2. As described above, the DC-DC converter 32 has a one-to-one correspondence with the voltage dividing capacitor Cdc2 and its input side is connected to both ends of the voltage dividing capacitor Cdc2. The output side of the DC-DC converter 32 is connected to the control circuit 40.
なお、DC-DCコンバータ31,32は、周知のフライバック形コンバータであってもよいし、また、他の種類の回路であってもよい。
The DC- DC converters 31 and 32 may be well-known flyback converters, or may be other types of circuits.
電圧センサ33は、分圧コンデンサCdc1の両端の電圧V1を検出するセンサである。電圧センサ34は、分圧コンデンサCdc2の両端の電圧V2を検出するセンサである。電圧センサ33,34の検出値は、次に説明する制御部35に出力される。
The voltage sensor 33 is a sensor that detects the voltage V1 across the voltage dividing capacitor Cdc1. The voltage sensor 34 is a sensor that detects the voltage V2 across the voltage dividing capacitor Cdc2. The detection values of the voltage sensors 33 and 34 are output to the control unit 35 described below.
制御部35は、図示はしないが、CPU、ROM、RAM、各種インタフェース等の電子回路を含んで構成され、ROMに記憶されたプログラムを読み出してRAMに展開し、CPUが各種処理を実行するようになっている。この制御部35は、DC-DCコンバータ31,32を制御する機能を有している。すなわち、制御部35は、電圧センサ33,34の検出値に基づいて、DC-DCコンバータ31,32が備えるスイッチングデバイス(図示せず)のオン・オフを制御する。
Although not shown, the control unit 35 includes electronic circuits such as a CPU, a ROM, a RAM, and various interfaces. The control unit 35 reads out a program stored in the ROM, expands the program in the RAM, and the CPU executes various processes. It has become. The control unit 35 has a function of controlling the DC- DC converters 31 and 32. That is, the control unit 35 controls on / off of a switching device (not shown) included in the DC- DC converters 31 and 32 based on the detection values of the voltage sensors 33 and 34.
<補助電源回路の動作>
図3は、補助電源回路30の動作に関する説明図である。
図3の横軸は、分圧コンデンサCdc1の両端の電圧V1である。図3の縦軸は、分圧コンデンサCdc2の両端の電圧V2である。また、図3に示す破線は、V1=V2の状態を表す直線である。
補助電源回路30は、分圧コンデンサCdc1の電圧V1と、分圧コンデンサCdc2の電圧V2と、の大小関係に応じて所定の動作をする。以下では、図3を参照しつつ、図4のフローチャートを用いて、補助電源回路30の動作を説明する。 <Operation of auxiliary power circuit>
FIG. 3 is an explanatory diagram relating to the operation of the auxiliarypower supply circuit 30.
The horizontal axis in FIG. 3 is the voltage V1 across the voltage dividing capacitor Cdc1. The vertical axis in FIG. 3 is the voltage V2 across the voltage dividing capacitor Cdc2. Moreover, the broken line shown in FIG. 3 is a straight line representing the state of V1 = V2.
The auxiliarypower supply circuit 30 performs a predetermined operation according to the magnitude relationship between the voltage V1 of the voltage dividing capacitor Cdc1 and the voltage V2 of the voltage dividing capacitor Cdc2. Hereinafter, the operation of the auxiliary power supply circuit 30 will be described with reference to FIG. 3 and the flowchart of FIG.
図3は、補助電源回路30の動作に関する説明図である。
図3の横軸は、分圧コンデンサCdc1の両端の電圧V1である。図3の縦軸は、分圧コンデンサCdc2の両端の電圧V2である。また、図3に示す破線は、V1=V2の状態を表す直線である。
補助電源回路30は、分圧コンデンサCdc1の電圧V1と、分圧コンデンサCdc2の電圧V2と、の大小関係に応じて所定の動作をする。以下では、図3を参照しつつ、図4のフローチャートを用いて、補助電源回路30の動作を説明する。 <Operation of auxiliary power circuit>
FIG. 3 is an explanatory diagram relating to the operation of the auxiliary
The horizontal axis in FIG. 3 is the voltage V1 across the voltage dividing capacitor Cdc1. The vertical axis in FIG. 3 is the voltage V2 across the voltage dividing capacitor Cdc2. Moreover, the broken line shown in FIG. 3 is a straight line representing the state of V1 = V2.
The auxiliary
図4は、補助電源回路30の制御部35が実行する処理のフローチャートである。
ステップS101において制御部35は、電圧V1,V2の検出値を読み込む。つまり、制御部35は、分圧コンデンサCdc1の電圧V1、及び分圧コンデンサCdc2の電圧V2の検出値を読み込む。 FIG. 4 is a flowchart of processing executed by thecontrol unit 35 of the auxiliary power circuit 30.
In step S101, thecontrol unit 35 reads the detection values of the voltages V1 and V2. That is, the control unit 35 reads the detected values of the voltage V1 of the voltage dividing capacitor Cdc1 and the voltage V2 of the voltage dividing capacitor Cdc2.
ステップS101において制御部35は、電圧V1,V2の検出値を読み込む。つまり、制御部35は、分圧コンデンサCdc1の電圧V1、及び分圧コンデンサCdc2の電圧V2の検出値を読み込む。 FIG. 4 is a flowchart of processing executed by the
In step S101, the
ステップS102において制御部35は、分圧コンデンサCdc1の電圧V1が、他方の分圧コンデンサCdc2の電圧V2よりも高いか否かを判定する。電圧V1が電圧V2よりも高い場合(S102:Yes)、制御部35の処理はステップS103に進む。
In step S102, the control unit 35 determines whether or not the voltage V1 of the voltage dividing capacitor Cdc1 is higher than the voltage V2 of the other voltage dividing capacitor Cdc2. When the voltage V1 is higher than the voltage V2 (S102: Yes), the process of the control unit 35 proceeds to step S103.
ステップS103において制御部35は、電流I2よりも電流I1の方が大きくなるようにDC-DCコンバータ31,32を制御する(図3に示す「I1>I2」の領域を参照)。例えば、制御部35は、DC-DCコンバータ31のスイッチングデバイス(図示せず)のオンデューティを、DC-DCコンバータ32のスイッチングデバイス(図示せず)のオンデューティよりも大きくする。これによって、分圧コンデンサCdc2から流れる電流I2よりも、分圧コンデンサCdc1から流れる電流I1の方が大きくなり、分圧コンデンサCdc1,Cdc2の電圧が均等化される(つまり、V1=V2の状態に近づく)。
In step S103, the control unit 35 controls the DC- DC converters 31 and 32 so that the current I1 is larger than the current I2 (see the region “I1> I2” shown in FIG. 3). For example, the control unit 35 makes the on-duty of the switching device (not shown) of the DC-DC converter 31 larger than the on-duty of the switching device (not shown) of the DC-DC converter 32. As a result, the current I1 flowing from the voltage dividing capacitor Cdc1 becomes larger than the current I2 flowing from the voltage dividing capacitor Cdc2, and the voltages of the voltage dividing capacitors Cdc1 and Cdc2 are equalized (that is, V1 = V2). Approach).
一方、ステップS102において電圧V1が電圧V2よりも高くない場合(S102:No)、制御部35の処理はステップS104に進む。
ステップS104において制御部35は、分圧コンデンサCdc2の電圧V2が、他方の分圧コンデンサCdc1の電圧V1よりも高いか否かを判定する。電圧V2が電圧V1よりも高い場合(S104:Yes)、制御部35の処理はステップS105に進む。 On the other hand, when the voltage V1 is not higher than the voltage V2 in step S102 (S102: No), the process of thecontrol unit 35 proceeds to step S104.
In step S104, thecontrol unit 35 determines whether or not the voltage V2 of the voltage dividing capacitor Cdc2 is higher than the voltage V1 of the other voltage dividing capacitor Cdc1. When the voltage V2 is higher than the voltage V1 (S104: Yes), the process of the control unit 35 proceeds to step S105.
ステップS104において制御部35は、分圧コンデンサCdc2の電圧V2が、他方の分圧コンデンサCdc1の電圧V1よりも高いか否かを判定する。電圧V2が電圧V1よりも高い場合(S104:Yes)、制御部35の処理はステップS105に進む。 On the other hand, when the voltage V1 is not higher than the voltage V2 in step S102 (S102: No), the process of the
In step S104, the
ステップS105において制御部35は、電流I1よりも電流I2の方が大きくなるようにDC-DCコンバータ31,32を制御する(図3に示す「I2>I1」の領域を参照)。これによって、分圧コンデンサCdc1,Cdc2の電圧が均等化される。
In step S105, the control unit 35 controls the DC- DC converters 31 and 32 so that the current I2 is larger than the current I1 (refer to the region “I2> I1” shown in FIG. 3). As a result, the voltages of the voltage dividing capacitors Cdc1 and Cdc2 are equalized.
このように、制御部35は、電圧センサ33,34の検出値に基づいて、分圧コンデンサCdc1からDC-DCコンバータ31に流れる電流I1を調整するとともに、分圧コンデンサCdc2からDC-DCコンバータ32に流れる電流I2を調整する。そして、前記したように、補助電源回路30は、分圧コンデンサCdc1,Cdc2のうち電圧のより高い分圧コンデンサから、より大きな電流を自身に入力するように動作する。
As described above, the control unit 35 adjusts the current I1 flowing from the voltage dividing capacitor Cdc1 to the DC-DC converter 31 based on the detection values of the voltage sensors 33 and 34, and from the voltage dividing capacitor Cdc2 to the DC-DC converter 32. The current I2 flowing through is adjusted. As described above, the auxiliary power supply circuit 30 operates to input a larger current to itself from the voltage dividing capacitor having a higher voltage among the voltage dividing capacitors Cdc1 and Cdc2.
また、ステップS104において電圧V2が電圧V1よりも高くない場合(S104:No)、制御部35の処理はステップS106に進む。つまり、電圧V1,V2が略等しい場合、制御部35の処理はステップS106に進む。
ステップS106において制御部35は、電流I1,I2が略等しい状態を維持するように、DC-DCコンバータ31,32を制御する(図3に示す破線「V1=V2」を参照)。 If the voltage V2 is not higher than the voltage V1 in step S104 (S104: No), the process of thecontrol unit 35 proceeds to step S106. That is, when the voltages V1 and V2 are substantially equal, the process of the control unit 35 proceeds to step S106.
In step S106, thecontrol unit 35 controls the DC- DC converters 31 and 32 so that the currents I1 and I2 are maintained substantially equal (see the broken line “V1 = V2” shown in FIG. 3).
ステップS106において制御部35は、電流I1,I2が略等しい状態を維持するように、DC-DCコンバータ31,32を制御する(図3に示す破線「V1=V2」を参照)。 If the voltage V2 is not higher than the voltage V1 in step S104 (S104: No), the process of the
In step S106, the
ステップS103,S105,又はS106の処理を行った後、制御部35の処理はステップS107に進む。
ステップS107において制御部35は、電力変換装置100の停止指令が上位コントローラ等(図示せず)から入力されたか否かを判定する。電力変換装置100の停止指令が入力された場合(S107:Yes)、制御部35の処理はステップS108に進む。
ステップS108において制御部35は、制御回路40等への給電を停止し、一連の処理を終了する(END)。 After performing the process of step S103, S105, or S106, the process of thecontrol unit 35 proceeds to step S107.
In step S107, thecontrol unit 35 determines whether or not a stop command for the power conversion apparatus 100 is input from a host controller or the like (not shown). When the stop instruction | command of the power converter device 100 is input (S107: Yes), the process of the control part 35 progresses to step S108.
In step S108, thecontrol unit 35 stops power supply to the control circuit 40 and the like, and ends a series of processing (END).
ステップS107において制御部35は、電力変換装置100の停止指令が上位コントローラ等(図示せず)から入力されたか否かを判定する。電力変換装置100の停止指令が入力された場合(S107:Yes)、制御部35の処理はステップS108に進む。
ステップS108において制御部35は、制御回路40等への給電を停止し、一連の処理を終了する(END)。 After performing the process of step S103, S105, or S106, the process of the
In step S107, the
In step S108, the
一方、ステップS107において電力変換装置100の停止指令が入力されていない場合(S107:No)、制御部35の処理はステップS101に戻る。そして、制御部35は、前記したように、分圧コンデンサCdc1,Cdc2の電圧を均等化するようにDC-DCコンバータ31,32を制御する。
On the other hand, when the stop instruction | command of the power converter device 100 is not input in step S107 (S107: No), the process of the control part 35 returns to step S101. Then, as described above, the control unit 35 controls the DC- DC converters 31 and 32 so as to equalize the voltages of the voltage dividing capacitors Cdc1 and Cdc2.
<効果>
第1実施形態によれば、分圧コンデンサCdc1の電圧V1と、分圧コンデンサCdc2の電圧V2と、が漏れ電流の差に起因して一時的にアンバランスになったとしても、電流I1,I2を調整することで電圧V1,V2を均等化できる。したがって、分圧コンデンサCdc1,Cdc2の電圧を定格電圧未満に抑えることができる。 <Effect>
According to the first embodiment, even if the voltage V1 of the voltage dividing capacitor Cdc1 and the voltage V2 of the voltage dividing capacitor Cdc2 are temporarily imbalanced due to the difference in leakage current, the currents I1, I2 By adjusting the voltage V1, the voltages V1 and V2 can be equalized. Therefore, the voltage of the voltage dividing capacitors Cdc1 and Cdc2 can be suppressed below the rated voltage.
第1実施形態によれば、分圧コンデンサCdc1の電圧V1と、分圧コンデンサCdc2の電圧V2と、が漏れ電流の差に起因して一時的にアンバランスになったとしても、電流I1,I2を調整することで電圧V1,V2を均等化できる。したがって、分圧コンデンサCdc1,Cdc2の電圧を定格電圧未満に抑えることができる。 <Effect>
According to the first embodiment, even if the voltage V1 of the voltage dividing capacitor Cdc1 and the voltage V2 of the voltage dividing capacitor Cdc2 are temporarily imbalanced due to the difference in leakage current, the currents I1, I2 By adjusting the voltage V1, the voltages V1 and V2 can be equalized. Therefore, the voltage of the voltage dividing capacitors Cdc1 and Cdc2 can be suppressed below the rated voltage.
また、分圧コンデンサCdc1、Cdc2の電圧を均等化するための電力を用いて、制御回路40等に電力が供給される。したがって、均等化に伴うエネルギの損失がほとんどないため、電力変換装置100の高効率化を図ることができる。また、補助電源回路30は、制御回路40に電力を供給する電源の機能と、分圧コンデンサCdc1,Cdc2の電圧の均等化を行う機能と、の両方を兼ねている。したがって、分圧コンデンサCdc1,Cdc2の電圧の均等化を行う回路を別に設ける構成と比較して、低コスト化を図ることができる。
Further, power is supplied to the control circuit 40 and the like using power for equalizing the voltages of the voltage dividing capacitors Cdc1 and Cdc2. Therefore, since there is almost no energy loss accompanying equalization, the power converter 100 can be highly efficient. The auxiliary power supply circuit 30 has both a function of a power supply for supplying power to the control circuit 40 and a function of equalizing the voltages of the voltage dividing capacitors Cdc1 and Cdc2. Therefore, the cost can be reduced compared to a configuration in which a circuit for equalizing the voltages of the voltage dividing capacitors Cdc1 and Cdc2 is provided separately.
また、仮に、直列接続された分圧コンデンサCdc1,Cdc2の両端に補助電源回路30を接続すると、補助電源回路30のスイッチングデバイス(図示せず)として高耐圧のものを用いる必要がある。これに対して本実施形態では、分圧コンデンサCdc1,Cdc2のそれぞれの両端が補助電源回路30に接続されている。したがって、補助電源回路30のスイッチングデバイスとして、耐圧が比較的低いものを用いることができ、ひいては、電力変換装置100の低コスト化を図ることができる。
If the auxiliary power supply circuit 30 is connected to both ends of the series-connected voltage dividing capacitors Cdc1 and Cdc2, it is necessary to use a high breakdown voltage switching device (not shown) for the auxiliary power supply circuit 30. In contrast, in the present embodiment, both ends of the voltage dividing capacitors Cdc1 and Cdc2 are connected to the auxiliary power circuit 30. Therefore, a device having a relatively low withstand voltage can be used as the switching device of the auxiliary power supply circuit 30, and as a result, the cost of the power conversion device 100 can be reduced.
≪第2実施形態≫
第2実施形態は、電力変換装置100A(図5参照)が無停電電源システムS(図5参照)に適用される点が第1実施形態とは異なっているが、その他(補助電源回路30の構成等:図2参照)については第1実施形態と同様である。したがって、第1実施形態と異なる部分について説明し、重複する部分については説明を省略する。 << Second Embodiment >>
The second embodiment is different from the first embodiment in that thepower conversion device 100A (see FIG. 5) is applied to the uninterruptible power supply system S (see FIG. 5). The configuration and the like (see FIG. 2) are the same as those in the first embodiment. Therefore, a different part from 1st Embodiment is demonstrated and description is abbreviate | omitted about the overlapping part.
第2実施形態は、電力変換装置100A(図5参照)が無停電電源システムS(図5参照)に適用される点が第1実施形態とは異なっているが、その他(補助電源回路30の構成等:図2参照)については第1実施形態と同様である。したがって、第1実施形態と異なる部分について説明し、重複する部分については説明を省略する。 << Second Embodiment >>
The second embodiment is different from the first embodiment in that the
図5は、第2実施形態に係る電力変換装置100Aが適用される無停電電源システムSの構成図である。
無停電電源システムSは、通常時には交流電源Gからの交流電力を所定の振幅・周波数の交流電力に変換し、また、交流電源Gの停電時にはバッテリBからの直流電力を所定の交流電力に変換するシステムである。
図5に示すように、無停電電源システムSは、電力変換装置100Aと、バッテリBと、を備えている。 FIG. 5 is a configuration diagram of an uninterruptible power supply system S to which thepower conversion device 100A according to the second embodiment is applied.
The uninterruptible power supply system S normally converts AC power from the AC power supply G into AC power having a predetermined amplitude and frequency, and also converts DC power from the battery B into predetermined AC power when the AC power supply G fails. System.
As shown in FIG. 5, the uninterruptible power supply system S includes apower conversion device 100A and a battery B.
無停電電源システムSは、通常時には交流電源Gからの交流電力を所定の振幅・周波数の交流電力に変換し、また、交流電源Gの停電時にはバッテリBからの直流電力を所定の交流電力に変換するシステムである。
図5に示すように、無停電電源システムSは、電力変換装置100Aと、バッテリBと、を備えている。 FIG. 5 is a configuration diagram of an uninterruptible power supply system S to which the
The uninterruptible power supply system S normally converts AC power from the AC power supply G into AC power having a predetermined amplitude and frequency, and also converts DC power from the battery B into predetermined AC power when the AC power supply G fails. System.
As shown in FIG. 5, the uninterruptible power supply system S includes a
電力変換装置100Aは、コンバータ60(電力変換回路、交直変換器)と,インバータ70と,DC-DCコンバータ80(電力変換回路、直流-直流変換器)と,を備えている。また、電力変換装置100Aは、前記した構成の他に、分圧コンデンサCdc1,Cdc2と、補助電源回路30と、制御回路40と、ファン50と、を備えている。
The power conversion device 100A includes a converter 60 (power conversion circuit, AC / DC converter), an inverter 70, and a DC-DC converter 80 (power conversion circuit, DC-DC converter). In addition to the above-described configuration, the power conversion device 100A includes voltage dividing capacitors Cdc1 and Cdc2, an auxiliary power supply circuit 30, a control circuit 40, and a fan 50.
コンバータ60は、交流電源Gから入力される三相交流電圧を直流電圧Vdcに変換する電力変換器である。
インバータ70は、コンバータ60から印加される直流電圧Vdcを交流電圧に変換し、この交流電圧を交流負荷Hに出力する電力変換器である。図5に示すように、インバータ70は、正側の配線kp及び負側の配線knを介して、コンバータ60に接続されている。Converter 60 is a power converter that converts a three-phase AC voltage input from AC power supply G into DC voltage Vdc.
Theinverter 70 is a power converter that converts the DC voltage Vdc applied from the converter 60 into an AC voltage and outputs the AC voltage to the AC load H. As shown in FIG. 5, the inverter 70 is connected to the converter 60 via a positive-side wiring kp and a negative-side wiring kn.
インバータ70は、コンバータ60から印加される直流電圧Vdcを交流電圧に変換し、この交流電圧を交流負荷Hに出力する電力変換器である。図5に示すように、インバータ70は、正側の配線kp及び負側の配線knを介して、コンバータ60に接続されている。
The
DC-DCコンバータ80は、交流電源Gが停電した場合にバッテリBの直流電圧を所定の直流電圧Vdcに変換するチョッパ回路である。図5に示すように、DC-DCコンバータ80は、入力側がバッテリBに接続され、出力側が配線kp,knに接続されている。
The DC-DC converter 80 is a chopper circuit that converts the DC voltage of the battery B into a predetermined DC voltage Vdc when the AC power supply G fails. As shown in FIG. 5, the DC-DC converter 80 has an input side connected to the battery B and an output side connected to the wirings kp and kn.
分圧コンデンサCdc1,Cdc2は、コンバータ60(停電時にはDC-DCコンバータ80)から印加される直流電圧Vdcを分圧するコンデンサであり、互いに直列接続されている。図5に示すように、分圧コンデンサCdc1,Cdc2は、コンバータ60やDC-DCコンバータ80の出力側(直流側)に接続されるとともに、インバータ70の入力側(直流側)に接続されている。
The voltage dividing capacitors Cdc1 and Cdc2 are capacitors that divide the DC voltage Vdc applied from the converter 60 (the DC-DC converter 80 in the event of a power failure), and are connected in series with each other. As shown in FIG. 5, the voltage dividing capacitors Cdc1 and Cdc2 are connected to the output side (DC side) of the converter 60 and the DC-DC converter 80 and to the input side (DC side) of the inverter 70. .
補助電源回路30は、第1実施形態と同様の構成を備え、分圧コンデンサCdc1の両端に接続されるとともに、分圧コンデンサCdc2の両端に接続されている。なお、補助電源回路30の動作についても第1実施形態(図4参照)と同様であるから、説明を省略する。
また、制御回路40及びファン50も第1実施形態と同様の構成であるから、説明を省略する。 Theauxiliary power circuit 30 has the same configuration as that of the first embodiment, and is connected to both ends of the voltage dividing capacitor Cdc1 and is connected to both ends of the voltage dividing capacitor Cdc2. The operation of the auxiliary power supply circuit 30 is also the same as that of the first embodiment (see FIG. 4), and thus the description thereof is omitted.
Further, since thecontrol circuit 40 and the fan 50 have the same configuration as that of the first embodiment, description thereof is omitted.
また、制御回路40及びファン50も第1実施形態と同様の構成であるから、説明を省略する。 The
Further, since the
バッテリBは、交流電源Gが停電した場合の電源として機能するものであり、DC-DCコンバータ80の入力側に接続されている。
The battery B functions as a power source when the AC power source G fails, and is connected to the input side of the DC-DC converter 80.
<効果>
第2実施形態によれば、補助電源回路30によって分圧コンデンサCdc1,Cdc2の電圧を均等化しつつ、制御回路40への給電を行うことができる。したがって、補助電源回路30におけるエネルギの損失を低減し、また、電力変換装置100Aの低コスト化を図ることができる。また、交流電源Gが停電しても、バッテリBの電力を用いて各回路を動作させることで、交流負荷Hへの給電を継続できる。 <Effect>
According to the second embodiment, the auxiliarypower supply circuit 30 can supply power to the control circuit 40 while equalizing the voltages of the voltage dividing capacitors Cdc1 and Cdc2. Therefore, energy loss in the auxiliary power supply circuit 30 can be reduced, and the cost of the power conversion device 100A can be reduced. In addition, even if the AC power supply G fails, the power supply to the AC load H can be continued by operating each circuit using the power of the battery B.
第2実施形態によれば、補助電源回路30によって分圧コンデンサCdc1,Cdc2の電圧を均等化しつつ、制御回路40への給電を行うことができる。したがって、補助電源回路30におけるエネルギの損失を低減し、また、電力変換装置100Aの低コスト化を図ることができる。また、交流電源Gが停電しても、バッテリBの電力を用いて各回路を動作させることで、交流負荷Hへの給電を継続できる。 <Effect>
According to the second embodiment, the auxiliary
≪第3実施形態≫
第3実施形態は、第1実施形態と比較して、補助電源回路30B(図6参照)の構成が異なるが、その他(電力変換装置100の全体構成:図1参照)は第1実施形態と同様である。したがって、第1実施形態とは異なる部分について説明し、重複する部分については説明を省略する。 «Third embodiment»
The third embodiment differs from the first embodiment in the configuration of the auxiliarypower supply circuit 30B (see FIG. 6), but the other (the overall configuration of the power conversion device 100: see FIG. 1) is the same as that in the first embodiment. It is the same. Therefore, a different part from 1st Embodiment is demonstrated and description is abbreviate | omitted about the overlapping part.
第3実施形態は、第1実施形態と比較して、補助電源回路30B(図6参照)の構成が異なるが、その他(電力変換装置100の全体構成:図1参照)は第1実施形態と同様である。したがって、第1実施形態とは異なる部分について説明し、重複する部分については説明を省略する。 «Third embodiment»
The third embodiment differs from the first embodiment in the configuration of the auxiliary
<補助電源回路の構成>
図6は、電力変換装置が備える補助電源回路30Bの構成図である。
図6に示すように、補助電源回路30Bは、磁気回路である鉄心Tと、1次側回路J11,J12と、2次側回路J20~J24と、制御部Mと、を備えるフライバック形の電源回路である。 <Configuration of auxiliary power circuit>
FIG. 6 is a configuration diagram of anauxiliary power circuit 30B included in the power conversion device.
As shown in FIG. 6, the auxiliarypower supply circuit 30B is a flyback type comprising an iron core T that is a magnetic circuit, primary side circuits J11 and J12, secondary side circuits J20 to J24, and a control unit M. It is a power supply circuit.
図6は、電力変換装置が備える補助電源回路30Bの構成図である。
図6に示すように、補助電源回路30Bは、磁気回路である鉄心Tと、1次側回路J11,J12と、2次側回路J20~J24と、制御部Mと、を備えるフライバック形の電源回路である。 <Configuration of auxiliary power circuit>
FIG. 6 is a configuration diagram of an
As shown in FIG. 6, the auxiliary
鉄心Tの1次側には1次巻線N1,N2が巻回され、2次側には2次巻線N20~N24が巻回されている。そして、鉄心Tと、1次巻線N1,N2と、2次巻線N20~N24と、によってトランス(変圧器)が構成されている。
The primary windings N1 and N2 are wound on the primary side of the iron core T, and the secondary windings N20 to N24 are wound on the secondary side. The iron core T, the primary windings N1 and N2, and the secondary windings N20 to N24 constitute a transformer (transformer).
1次側回路J11は、分圧コンデンサCdc1(図1参照)の電圧V1が印加される回路である。図6に示すように、1次側回路J11は、1次コンデンサC1と、1次巻線N1と、1次ダイオードDb1と、スイッチング素子Q1と、還流ダイオードD1と、スナバ回路Sn1と、を備えている。
The primary side circuit J11 is a circuit to which the voltage V1 of the voltage dividing capacitor Cdc1 (see FIG. 1) is applied. As shown in FIG. 6, the primary circuit J11 includes a primary capacitor C1, a primary winding N1, a primary diode Db1, a switching element Q1, a freewheeling diode D1, and a snubber circuit Sn1. ing.
1次コンデンサC1は、スイッチング素子Q1のターンオフ時の電圧変動を抑制するためのコンデンサである。なお、1次コンデンサC1は、平滑用の分圧コンデンサCdc1(図1参照)とは別のコンデンサである。1次コンデンサC1の正極は、配線kp1を介して分圧コンデンサCdc1の正極に接続されている。また、1次コンデンサC1の負極は、配線kn1を介して分圧コンデンサCdc1の負極に接続されている。
The primary capacitor C1 is a capacitor for suppressing voltage fluctuation when the switching element Q1 is turned off. The primary capacitor C1 is a capacitor different from the smoothing voltage dividing capacitor Cdc1 (see FIG. 1). The positive electrode of the primary capacitor C1 is connected to the positive electrode of the voltage dividing capacitor Cdc1 through the wiring kp1. The negative electrode of the primary capacitor C1 is connected to the negative electrode of the voltage dividing capacitor Cdc1 through the wiring kn1.
また、1次巻線N1、1次ダイオードDb1、及びスイッチング素子Q1が順次に直列接続されてなる「直列接続体」が、1次コンデンサC1に並列接続されている。つまり、前記した「直列接続体」は、分圧コンデンサCdc1(図1参照)と一対一で対応して、その両端が分圧コンデンサCdc1の両端に接続されている。
Further, a “series connection body” in which the primary winding N1, the primary diode Db1, and the switching element Q1 are sequentially connected in series is connected in parallel to the primary capacitor C1. That is, the above-described “series connection body” has a one-to-one correspondence with the voltage dividing capacitor Cdc1 (see FIG. 1), and both ends thereof are connected to both ends of the voltage dividing capacitor Cdc1.
図6に示すように、1次巻線N1は、その一端が1次コンデンサC1の正極に接続され、他端が1次ダイオードDb1のアノードに接続されている。また、スイッチング素子Q1は、ドレインが1次ダイオードDb1のカソードに接続され、ソースが1次コンデンサC1の負極に接続されている。また、スイッチング素子Q1には、還流ダイオードD1が逆並列に接続されている。
なお、図6に示す例では、スイッチング素子Q1としてMOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor)を用いているが、別の種類のスイッチング素子を用いてもよい。 As shown in FIG. 6, the primary winding N1 has one end connected to the positive electrode of the primary capacitor C1 and the other end connected to the anode of the primary diode Db1. The switching element Q1 has a drain connected to the cathode of the primary diode Db1, and a source connected to the negative electrode of the primary capacitor C1. In addition, a free-wheeling diode D1 is connected in antiparallel to the switching element Q1.
In the example shown in FIG. 6, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is used as the switching element Q1, but another type of switching element may be used.
なお、図6に示す例では、スイッチング素子Q1としてMOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor)を用いているが、別の種類のスイッチング素子を用いてもよい。 As shown in FIG. 6, the primary winding N1 has one end connected to the positive electrode of the primary capacitor C1 and the other end connected to the anode of the primary diode Db1. The switching element Q1 has a drain connected to the cathode of the primary diode Db1, and a source connected to the negative electrode of the primary capacitor C1. In addition, a free-wheeling diode D1 is connected in antiparallel to the switching element Q1.
In the example shown in FIG. 6, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is used as the switching element Q1, but another type of switching element may be used.
1次ダイオードDb1は、分圧コンデンサCdc1(図1参照)の正極から配線kp1等を介して自身に向かう電流を許容し、逆向きの電流を阻止するように接続されている。この1次ダイオードDb1(及び、他方の1次ダイオードDb2)を設けている点が、第3実施形態の主な特徴の一つである。
The primary diode Db1 is connected so as to allow a current from the positive electrode of the voltage dividing capacitor Cdc1 (see FIG. 1) to the self through the wiring kp1 and the like, and prevent a reverse current. The provision of the primary diode Db1 (and the other primary diode Db2) is one of the main features of the third embodiment.
スナバ回路Sn1は、スイッチング素子Q1のドレイン-ソース間に発生するサージ電圧を抑制する回路である。スナバ回路Sn1は、1次巻線N1と一対一で対応して、この1次巻線N1に並列接続されている。スナバ回路Sn1は、ダイオードDs1と、コンデンサCs1と、抵抗Rs1と、を備えている。
The snubber circuit Sn1 is a circuit that suppresses a surge voltage generated between the drain and source of the switching element Q1. The snubber circuit Sn1 has a one-to-one correspondence with the primary winding N1 and is connected in parallel to the primary winding N1. The snubber circuit Sn1 includes a diode Ds1, a capacitor Cs1, and a resistor Rs1.
図6に示すように、コンデンサCs1と抵抗Rs1とが並列接続されてなる「並列接続体」にダイオードDs1が直列接続されている。ダイオードDs1のアノードは、1次ダイオードDb1のアノードに接続され、カソードは、前記した「並列接続体」に接続されている。そして、スイッチング素子Q1のドレイン-ソース間にサージ電圧が発生した場合には、コンデンサCs1によってサージ電圧が抑制され、また、サージ電圧に伴うエネルギが抵抗Rs1で消費されるようになっている。
As shown in FIG. 6, a diode Ds1 is connected in series to a “parallel connection body” in which a capacitor Cs1 and a resistor Rs1 are connected in parallel. The anode of the diode Ds1 is connected to the anode of the primary diode Db1, and the cathode is connected to the “parallel connection body” described above. When a surge voltage is generated between the drain and source of the switching element Q1, the surge voltage is suppressed by the capacitor Cs1, and energy associated with the surge voltage is consumed by the resistor Rs1.
1次側回路J12は、分圧コンデンサCdc2(図1参照)の電圧V2が印加される回路である。この1次側回路J12は、前記した1次側回路J11と同様の構成を備えている。
図6に示すように、1次巻線N2、1次ダイオードDb2、及びスイッチング素子Q2が順次に直列接続されてなる「直列接続体」が、1次コンデンサC2に並列接続されている。つまり、前記した「直列接続体」は、分圧コンデンサCdc2(図1参照)と一対一で対応して、その両端が分圧コンデンサCdc2の両端に接続されている。
1次ダイオードDb2は、分圧コンデンサCdc2の正極から配線kp2等を介して自身に向かう電流を許容し、逆向きの電流を阻止するように接続されている。 The primary side circuit J12 is a circuit to which the voltage V2 of the voltage dividing capacitor Cdc2 (see FIG. 1) is applied. The primary side circuit J12 has the same configuration as the primary side circuit J11 described above.
As shown in FIG. 6, a “series connection body” in which a primary winding N2, a primary diode Db2, and a switching element Q2 are sequentially connected in series is connected in parallel to the primary capacitor C2. That is, the above-described “series connection body” has a one-to-one correspondence with the voltage dividing capacitor Cdc2 (see FIG. 1), and both ends thereof are connected to both ends of the voltage dividing capacitor Cdc2.
The primary diode Db2 is connected so as to allow a current from the positive electrode of the voltage dividing capacitor Cdc2 toward itself through the wiring kp2 and the like and to block a reverse current.
図6に示すように、1次巻線N2、1次ダイオードDb2、及びスイッチング素子Q2が順次に直列接続されてなる「直列接続体」が、1次コンデンサC2に並列接続されている。つまり、前記した「直列接続体」は、分圧コンデンサCdc2(図1参照)と一対一で対応して、その両端が分圧コンデンサCdc2の両端に接続されている。
1次ダイオードDb2は、分圧コンデンサCdc2の正極から配線kp2等を介して自身に向かう電流を許容し、逆向きの電流を阻止するように接続されている。 The primary side circuit J12 is a circuit to which the voltage V2 of the voltage dividing capacitor Cdc2 (see FIG. 1) is applied. The primary side circuit J12 has the same configuration as the primary side circuit J11 described above.
As shown in FIG. 6, a “series connection body” in which a primary winding N2, a primary diode Db2, and a switching element Q2 are sequentially connected in series is connected in parallel to the primary capacitor C2. That is, the above-described “series connection body” has a one-to-one correspondence with the voltage dividing capacitor Cdc2 (see FIG. 1), and both ends thereof are connected to both ends of the voltage dividing capacitor Cdc2.
The primary diode Db2 is connected so as to allow a current from the positive electrode of the voltage dividing capacitor Cdc2 toward itself through the wiring kp2 and the like and to block a reverse current.
2次側回路J21は、2次巻線N21と、2次ダイオードD21と、2次コンデンサC21と、を備えている。図6に示すように、2次巻線N21と2次ダイオードD21とが直列接続されている。また、2次巻線N21及び2次ダイオードD21に2次コンデンサC21が並列接続されている。
The secondary side circuit J21 includes a secondary winding N21, a secondary diode D21, and a secondary capacitor C21. As shown in FIG. 6, the secondary winding N21 and the secondary diode D21 are connected in series. A secondary capacitor C21 is connected in parallel to the secondary winding N21 and the secondary diode D21.
2次ダイオードD21は、アノードが2次巻線N21に接続され、カソードが2次コンデンサC21の正極に接続されている。つまり、2次ダイオードD21は、自身を介して2次巻線N21から2次コンデンサC21の正極に向かう電流を許容し、逆向きの電流を阻止するように接続されている。そして、2次コンデンサC21の両端から電力が出力されるようになっている。
The secondary diode D21 has an anode connected to the secondary winding N21 and a cathode connected to the positive electrode of the secondary capacitor C21. That is, the secondary diode D21 is connected so as to allow a current from the secondary winding N21 toward the positive electrode of the secondary capacitor C21 through itself and prevent a reverse current. Electric power is output from both ends of the secondary capacitor C21.
2次側回路J20,J22~J24については、前記した2次側回路J21と同様の構成であるから、説明を省略する。
なお、2次側回路J21~J24のうち、一つ又は複数から制御回路40(図1参照)に電力が供給されるようになっている。なお、2次側回路J21~J24のうち、一つ又は複数からら、ファン50等(図1参照)の他の機器に電力を供給してもよい。 Since the secondary side circuits J20, J22 to J24 have the same configuration as the secondary side circuit J21 described above, description thereof is omitted.
Note that power is supplied to the control circuit 40 (see FIG. 1) from one or more of the secondary side circuits J21 to J24. Note that power may be supplied from one or more of the secondary side circuits J21 to J24 to other devices such as the fan 50 (see FIG. 1).
なお、2次側回路J21~J24のうち、一つ又は複数から制御回路40(図1参照)に電力が供給されるようになっている。なお、2次側回路J21~J24のうち、一つ又は複数からら、ファン50等(図1参照)の他の機器に電力を供給してもよい。 Since the secondary side circuits J20, J22 to J24 have the same configuration as the secondary side circuit J21 described above, description thereof is omitted.
Note that power is supplied to the control circuit 40 (see FIG. 1) from one or more of the secondary side circuits J21 to J24. Note that power may be supplied from one or more of the secondary side circuits J21 to J24 to other devices such as the fan 50 (see FIG. 1).
制御部Mは、図示はしないが、IC等の電子回路を含んで構成され、ROMに記憶されたプログラムを読み出してRAMに展開し、CPUが各種処理を実行するようになっている。図6に示すように、制御部Mは、2次コンデンサC20の両端に接続されている。制御部Mは、2次コンデンサC20の電圧V20が所定値になるように、スイッチング素子Q1,Q2のオン・オフを制御するようになっている。
The control unit M is configured to include an electronic circuit such as an IC (not shown), reads a program stored in the ROM, develops it in the RAM, and the CPU executes various processes. As shown in FIG. 6, the control unit M is connected to both ends of the secondary capacitor C20. The controller M controls the on / off of the switching elements Q1, Q2 so that the voltage V20 of the secondary capacitor C20 becomes a predetermined value.
<補助電源回路の動作>
次に、補助電源回路30Bの動作について、図7(V1>V2の場合)、図8(V1<V2の場合)、及び図9(V1=V2の場合)を順次に参照して説明する。なお、図7~図9では、スナバ回路Sn1,Sn2(図6参照)の図示を省略している。また、以下では、1次巻線N1の巻数と、1次巻線N2の巻数と、が略等しいものとして説明する。 <Operation of auxiliary power circuit>
Next, the operation of the auxiliarypower supply circuit 30B will be described with reference to FIG. 7 (when V1> V2), FIG. 8 (when V1 <V2), and FIG. 9 (when V1 = V2) sequentially. 7 to 9, illustration of the snubber circuits Sn1 and Sn2 (see FIG. 6) is omitted. In the following description, it is assumed that the number of turns of the primary winding N1 is substantially equal to the number of turns of the primary winding N2.
次に、補助電源回路30Bの動作について、図7(V1>V2の場合)、図8(V1<V2の場合)、及び図9(V1=V2の場合)を順次に参照して説明する。なお、図7~図9では、スナバ回路Sn1,Sn2(図6参照)の図示を省略している。また、以下では、1次巻線N1の巻数と、1次巻線N2の巻数と、が略等しいものとして説明する。 <Operation of auxiliary power circuit>
Next, the operation of the auxiliary
(1.V1>V2の場合)
図7(a)は、電圧V2よりも電圧V1の方が高い場合において、スイッチング素子Q1,Q2をオン状態にしたときの説明図である。
なお、図7(a)、(b)に示す破線矢印は、電流の流れを表している。図7(a)に示すように、制御部Mがスイッチング素子Q1、Q2をオン状態にすると、電圧V1に略等しい電圧が1次巻線N1に印加される。これによって、1次ダイオードDb1が順バイアスになり、1次巻線N1に流れる電流が増加する。その結果、鉄心T・1次巻線N1,N2・2次巻線N21等によって構成されるトランスの励磁インダクタンスに所定のエネルギが蓄積される。 (1. When V1> V2)
FIG. 7A is an explanatory diagram when the switching elements Q1 and Q2 are turned on when the voltage V1 is higher than the voltage V2.
In addition, the broken-line arrow shown to Fig.7 (a), (b) represents the flow of an electric current. As shown in FIG. 7A, when the control unit M turns on the switching elements Q1 and Q2, a voltage substantially equal to the voltage V1 is applied to the primary winding N1. As a result, the primary diode Db1 becomes forward biased, and the current flowing through the primary winding N1 increases. As a result, predetermined energy is accumulated in the exciting inductance of the transformer constituted by the iron core T, the primary windings N1, N2, the secondary winding N21, and the like.
図7(a)は、電圧V2よりも電圧V1の方が高い場合において、スイッチング素子Q1,Q2をオン状態にしたときの説明図である。
なお、図7(a)、(b)に示す破線矢印は、電流の流れを表している。図7(a)に示すように、制御部Mがスイッチング素子Q1、Q2をオン状態にすると、電圧V1に略等しい電圧が1次巻線N1に印加される。これによって、1次ダイオードDb1が順バイアスになり、1次巻線N1に流れる電流が増加する。その結果、鉄心T・1次巻線N1,N2・2次巻線N21等によって構成されるトランスの励磁インダクタンスに所定のエネルギが蓄積される。 (1. When V1> V2)
FIG. 7A is an explanatory diagram when the switching elements Q1 and Q2 are turned on when the voltage V1 is higher than the voltage V2.
In addition, the broken-line arrow shown to Fig.7 (a), (b) represents the flow of an electric current. As shown in FIG. 7A, when the control unit M turns on the switching elements Q1 and Q2, a voltage substantially equal to the voltage V1 is applied to the primary winding N1. As a result, the primary diode Db1 becomes forward biased, and the current flowing through the primary winding N1 increases. As a result, predetermined energy is accumulated in the exciting inductance of the transformer constituted by the iron core T, the primary windings N1, N2, the secondary winding N21, and the like.
前記したように、1次巻線N1,N2は巻数が略等しく、また、共通の鉄心Tに巻回されている。したがって、1次巻線N2にも1次巻線N1と同程度の電圧V1が生じる。この電圧V1は、1次コンデンサC2に印加されている電圧V2よりも高いため、1次ダイオードDb2が逆バイアスになる。したがって、図7(a)に示すように、1次巻線N2には電流が流れない。
As described above, the primary windings N1 and N2 have substantially the same number of turns and are wound around a common iron core T. Accordingly, a voltage V1 of the same level as that of the primary winding N1 is generated in the primary winding N2. Since the voltage V1 is higher than the voltage V2 applied to the primary capacitor C2, the primary diode Db2 is reverse-biased. Therefore, as shown in FIG. 7A, no current flows through the primary winding N2.
また、2次巻線N20~N24にも電圧が生じるが、2次ダイオードD20~D24がそれぞれ逆バイアスになる。したがって、図7(a)に示すように、2次巻線N20~N24にも電流は流れない。
次に制御部Mは、図7(b)に示すように、スイッチング素子Q1,Q2をターンオフする(つまり、オフ状態に切り替える)。 Although voltages are also generated in the secondary windings N20 to N24, the secondary diodes D20 to D24 are reversely biased, respectively. Accordingly, as shown in FIG. 7A, no current flows through the secondary windings N20 to N24.
Next, as shown in FIG. 7B, the control unit M turns off the switching elements Q1 and Q2 (that is, switches to the off state).
次に制御部Mは、図7(b)に示すように、スイッチング素子Q1,Q2をターンオフする(つまり、オフ状態に切り替える)。 Although voltages are also generated in the secondary windings N20 to N24, the secondary diodes D20 to D24 are reversely biased, respectively. Accordingly, as shown in FIG. 7A, no current flows through the secondary windings N20 to N24.
Next, as shown in FIG. 7B, the control unit M turns off the switching elements Q1 and Q2 (that is, switches to the off state).
図7(b)は、電圧V2よりも電圧V1の方が高い場合において、スイッチング素子Q1,Q2がターンオフされた直後の状態を示す説明図である。
スイッチング素子Q1,Q2がターンオフされると、2次巻線N20~N24に電圧が生じ、2次ダイオードD20~D24が順バイアスになって導通する。その結果、前記したトランスの励磁インダクタンスに蓄積されたエネルギが放出され、2次コンデンサC20~C24を介して制御回路40等(図1参照)に電力が供給される。 FIG. 7B is an explanatory diagram showing a state immediately after the switching elements Q1 and Q2 are turned off when the voltage V1 is higher than the voltage V2.
When switching elements Q1, Q2 are turned off, a voltage is generated in secondary windings N20-N24, and secondary diodes D20-D24 become forward biased and become conductive. As a result, the energy accumulated in the magnetizing inductance of the transformer is released, and power is supplied to the control circuit 40 (see FIG. 1) via the secondary capacitors C20 to C24.
スイッチング素子Q1,Q2がターンオフされると、2次巻線N20~N24に電圧が生じ、2次ダイオードD20~D24が順バイアスになって導通する。その結果、前記したトランスの励磁インダクタンスに蓄積されたエネルギが放出され、2次コンデンサC20~C24を介して制御回路40等(図1参照)に電力が供給される。 FIG. 7B is an explanatory diagram showing a state immediately after the switching elements Q1 and Q2 are turned off when the voltage V1 is higher than the voltage V2.
When switching elements Q1, Q2 are turned off, a voltage is generated in secondary windings N20-N24, and secondary diodes D20-D24 become forward biased and become conductive. As a result, the energy accumulated in the magnetizing inductance of the transformer is released, and power is supplied to the control circuit 40 (see FIG. 1) via the secondary capacitors C20 to C24.
図7(c)は、電圧V2よりも電圧V1の方が高い場合において、トランスからエネルギが放出された後の状態を示す説明図である。
スイッチング素子Q1,Q2のターンオフ後、そのオフ状態が所定時間続くと、前記したトランスの励磁インダクタンスに蓄積されたエネルギが、全て放出される。その結果、2次巻線N20~N24には電流が流れなくなる。このとき、1次巻線N1,N2にも電流は流れていない。 FIG. 7C is an explanatory diagram showing a state after energy is released from the transformer when the voltage V1 is higher than the voltage V2.
If the OFF state continues for a predetermined time after the switching elements Q1 and Q2 are turned off, all the energy stored in the exciting inductance of the transformer is released. As a result, no current flows through the secondary windings N20 to N24. At this time, no current flows through the primary windings N1 and N2.
スイッチング素子Q1,Q2のターンオフ後、そのオフ状態が所定時間続くと、前記したトランスの励磁インダクタンスに蓄積されたエネルギが、全て放出される。その結果、2次巻線N20~N24には電流が流れなくなる。このとき、1次巻線N1,N2にも電流は流れていない。 FIG. 7C is an explanatory diagram showing a state after energy is released from the transformer when the voltage V1 is higher than the voltage V2.
If the OFF state continues for a predetermined time after the switching elements Q1 and Q2 are turned off, all the energy stored in the exciting inductance of the transformer is released. As a result, no current flows through the secondary windings N20 to N24. At this time, no current flows through the primary windings N1 and N2.
その後、制御部Mによってスイッチング素子Q1,Q2がターンオンされると、図7(a)の状態に戻る。このようにして、制御部Mは、スイッチング素子Q1,Q2を同じタイミングでターンオンした後、同じタイミングでターンオフするという処理を繰り返す。つまり、補助電源回路30Bが備えるスイッチング素子Q1,Q2が、同時にオン状態である期間と、同時にオフ状態である期間と、を有するように動作する。言い換えると、スイッチング素子Q1は、他のスイッチング素子Q2がオン状態であるときには自身もオン状態であり、他のスイッチング素子Q2がオフ状態であるときには自身もオフ状態になっている。
Thereafter, when the switching elements Q1 and Q2 are turned on by the control unit M, the state returns to the state of FIG. In this way, the control unit M repeats the process of turning on the switching elements Q1, Q2 at the same timing and then turning off at the same timing. That is, the switching elements Q1 and Q2 included in the auxiliary power supply circuit 30B operate so as to have a period in which the auxiliary power supply circuit 30B is simultaneously in an on state and a period in which the auxiliary power supply circuit 30B is in an off state. In other words, the switching element Q1 is also in the on state when the other switching element Q2 is in the on state, and is also in the off state when the other switching element Q2 is in the off state.
また、電圧V2よりも電圧V1の方が高い場合には、図7(a)に示すように、1次巻線N1には電流が流れるが、他方の1次巻線N2には電流が流れない。つまり、分圧コンデンサCdc1(図1参照)からは電流が流れるが、他方の分圧コンデンサCdc2(図1参照)からは電流が流れない。その結果、分圧コンデンサCdc1の電圧V1が低下し、電圧V1,V2が均等化される。
When the voltage V1 is higher than the voltage V2, as shown in FIG. 7A, a current flows through the primary winding N1, but a current flows through the other primary winding N2. Absent. That is, current flows from the voltage dividing capacitor Cdc1 (see FIG. 1), but no current flows from the other voltage dividing capacitor Cdc2 (see FIG. 1). As a result, the voltage V1 of the voltage dividing capacitor Cdc1 decreases and the voltages V1 and V2 are equalized.
(2.V1<V2の場合)
図8(a)は、電圧V1よりも電圧V2の方が高い場合において、スイッチング素子Q1,Q2をオン状態にしたときの説明図である。
制御部Mがスイッチング素子Q1、Q2をオン状態にすると、電圧V2に略等しい電圧が1次巻線N2に印加される。これによって、1次ダイオードDb2が順バイアスになり、1次巻線N2に流れる電流が増加する。その結果、鉄心T・1次巻線N1,N2・2次巻線N21等によって構成されるトランスの励磁インダクタンスに所定のエネルギが蓄積される。 (2. When V1 <V2)
FIG. 8A is an explanatory diagram when the switching elements Q1 and Q2 are turned on when the voltage V2 is higher than the voltage V1.
When the control unit M turns on the switching elements Q1 and Q2, a voltage substantially equal to the voltage V2 is applied to the primary winding N2. As a result, the primary diode Db2 becomes forward biased, and the current flowing through the primary winding N2 increases. As a result, predetermined energy is accumulated in the exciting inductance of the transformer constituted by the iron core T, the primary windings N1, N2, the secondary winding N21, and the like.
図8(a)は、電圧V1よりも電圧V2の方が高い場合において、スイッチング素子Q1,Q2をオン状態にしたときの説明図である。
制御部Mがスイッチング素子Q1、Q2をオン状態にすると、電圧V2に略等しい電圧が1次巻線N2に印加される。これによって、1次ダイオードDb2が順バイアスになり、1次巻線N2に流れる電流が増加する。その結果、鉄心T・1次巻線N1,N2・2次巻線N21等によって構成されるトランスの励磁インダクタンスに所定のエネルギが蓄積される。 (2. When V1 <V2)
FIG. 8A is an explanatory diagram when the switching elements Q1 and Q2 are turned on when the voltage V2 is higher than the voltage V1.
When the control unit M turns on the switching elements Q1 and Q2, a voltage substantially equal to the voltage V2 is applied to the primary winding N2. As a result, the primary diode Db2 becomes forward biased, and the current flowing through the primary winding N2 increases. As a result, predetermined energy is accumulated in the exciting inductance of the transformer constituted by the iron core T, the primary windings N1, N2, the secondary winding N21, and the like.
また、1次巻線N1,N2は巻数が略等しく、共通の鉄心Tに巻回されている。したがって、1次巻線N1にも1次巻線N2と同程度の電圧V2が生じる。この電圧V2は、1次コンデンサC1に印加されている電圧V1よりも高いため、1次ダイオードDb1が逆バイアスになる。したがって、図8(a)に示すように、1次巻線N1には電流は流れない。
The primary windings N1 and N2 have substantially the same number of turns and are wound around a common iron core T. Accordingly, a voltage V2 of the same level as that of the primary winding N2 is generated in the primary winding N1. Since this voltage V2 is higher than the voltage V1 applied to the primary capacitor C1, the primary diode Db1 is reverse-biased. Therefore, as shown in FIG. 8A, no current flows through the primary winding N1.
また、2次巻線N20~N24にも電圧が生じるが、2次ダイオードD20~D24がそれぞれ逆バイアスになる。したがって、図8(a)に示すように、2次巻線N20~N24にも電流は流れない。
次に制御部Mは、図8(b)に示すように、スイッチング素子Q1,Q2をターンオフする。 Although voltages are also generated in the secondary windings N20 to N24, the secondary diodes D20 to D24 are reversely biased, respectively. Therefore, as shown in FIG. 8A, no current flows through the secondary windings N20 to N24.
Next, as shown in FIG. 8B, the control unit M turns off the switching elements Q1 and Q2.
次に制御部Mは、図8(b)に示すように、スイッチング素子Q1,Q2をターンオフする。 Although voltages are also generated in the secondary windings N20 to N24, the secondary diodes D20 to D24 are reversely biased, respectively. Therefore, as shown in FIG. 8A, no current flows through the secondary windings N20 to N24.
Next, as shown in FIG. 8B, the control unit M turns off the switching elements Q1 and Q2.
図8(b)は、電圧V1よりも電圧V2の方が高い場合において、スイッチング素子Q1,Q2をターンオフした直後の状態を示す説明図である。
スイッチング素子Q1,Q2がターンオフされると、2次ダイオードD20~D24が導通し、2次コンデンサC20~C24に電流が流れる。 FIG. 8B is an explanatory diagram showing a state immediately after the switching elements Q1 and Q2 are turned off when the voltage V2 is higher than the voltage V1.
When switching elements Q1 and Q2 are turned off, secondary diodes D20 to D24 conduct, and current flows through secondary capacitors C20 to C24.
スイッチング素子Q1,Q2がターンオフされると、2次ダイオードD20~D24が導通し、2次コンデンサC20~C24に電流が流れる。 FIG. 8B is an explanatory diagram showing a state immediately after the switching elements Q1 and Q2 are turned off when the voltage V2 is higher than the voltage V1.
When switching elements Q1 and Q2 are turned off, secondary diodes D20 to D24 conduct, and current flows through secondary capacitors C20 to C24.
図8(c)は、電圧V1よりも電圧V2の方が高い場合において、トランスからエネルギが放出された後の状態を示す説明図である。
スイッチング素子Q1,Q2のターンオフ後、そのオフ状態が所定時間続くと、前記したトランスの励磁インダクタンスに蓄積されたエネルギが、全て放出される。その結果、2次巻線N20~N24には電流が流れなくなる。 FIG. 8C is an explanatory diagram showing a state after energy is released from the transformer when the voltage V2 is higher than the voltage V1.
If the OFF state continues for a predetermined time after the switching elements Q1 and Q2 are turned off, all the energy stored in the exciting inductance of the transformer is released. As a result, no current flows through the secondary windings N20 to N24.
スイッチング素子Q1,Q2のターンオフ後、そのオフ状態が所定時間続くと、前記したトランスの励磁インダクタンスに蓄積されたエネルギが、全て放出される。その結果、2次巻線N20~N24には電流が流れなくなる。 FIG. 8C is an explanatory diagram showing a state after energy is released from the transformer when the voltage V2 is higher than the voltage V1.
If the OFF state continues for a predetermined time after the switching elements Q1 and Q2 are turned off, all the energy stored in the exciting inductance of the transformer is released. As a result, no current flows through the secondary windings N20 to N24.
その後、制御部Mによってスイッチング素子Q1,Q2がターンオンされると、図8(a)の状態に戻る。このようにして、制御部Mは、スイッチング素子Q1,Q2を同じタイミングでターンオンした後、同じタイミングでターンオフするという処理を繰り返す。
Thereafter, when the switching elements Q1 and Q2 are turned on by the control unit M, the state returns to the state of FIG. In this way, the control unit M repeats the process of turning on the switching elements Q1, Q2 at the same timing and then turning off at the same timing.
また、図8(a)に示すように、1次巻線N2には電流が流れるが、1次巻線N1には電流が流れない。つまり、分圧コンデンサCdc2(図1参照)からは電流が流れるが、分圧コンデンサCdc1(図1参照)からは電流が流れない。その結果、分圧コンデンサCdc2の電圧V2が低下し、電圧V1,V2が均等化される。
Further, as shown in FIG. 8A, a current flows through the primary winding N2, but no current flows through the primary winding N1. That is, current flows from the voltage dividing capacitor Cdc2 (see FIG. 1), but no current flows from the voltage dividing capacitor Cdc1 (see FIG. 1). As a result, the voltage V2 of the voltage dividing capacitor Cdc2 is reduced and the voltages V1 and V2 are equalized.
(3.V1=V2の場合)
図9(a)は、電圧V1,V2が略等しい場合において、スイッチング素子Q1,Q2をオン状態にしたときの説明図である。
図9(a)に示すように、制御部Mがスイッチング素子Q1、Q2をオン状態にすると、電圧V1,V2が略等しいため、1次ダイオードDb1,Db2の両方が順バイアスになり、1次巻線N1,N2の両方に電流が流れる。 (3. When V1 = V2)
FIG. 9A is an explanatory diagram when the switching elements Q1 and Q2 are turned on when the voltages V1 and V2 are substantially equal.
As shown in FIG. 9A, when the control unit M turns on the switching elements Q1 and Q2, the voltages V1 and V2 are substantially equal. Therefore, both the primary diodes Db1 and Db2 become forward biased, and the primary Current flows through both windings N1 and N2.
図9(a)は、電圧V1,V2が略等しい場合において、スイッチング素子Q1,Q2をオン状態にしたときの説明図である。
図9(a)に示すように、制御部Mがスイッチング素子Q1、Q2をオン状態にすると、電圧V1,V2が略等しいため、1次ダイオードDb1,Db2の両方が順バイアスになり、1次巻線N1,N2の両方に電流が流れる。 (3. When V1 = V2)
FIG. 9A is an explanatory diagram when the switching elements Q1 and Q2 are turned on when the voltages V1 and V2 are substantially equal.
As shown in FIG. 9A, when the control unit M turns on the switching elements Q1 and Q2, the voltages V1 and V2 are substantially equal. Therefore, both the primary diodes Db1 and Db2 become forward biased, and the primary Current flows through both windings N1 and N2.
図9(b)は、電圧V1,V2が略等しい場合において、スイッチング素子Q1,Q2をターンオフした直後の状態を示す説明図である。
スイッチング素子Q1,Q2がターンオフされると、2次ダイオードD20~D24が導通し、2次コンデンサC20~C24に電流が供給される。 FIG. 9B is an explanatory diagram showing a state immediately after the switching elements Q1 and Q2 are turned off when the voltages V1 and V2 are substantially equal.
When switching elements Q1, Q2 are turned off, secondary diodes D20-D24 are turned on, and current is supplied to secondary capacitors C20-C24.
スイッチング素子Q1,Q2がターンオフされると、2次ダイオードD20~D24が導通し、2次コンデンサC20~C24に電流が供給される。 FIG. 9B is an explanatory diagram showing a state immediately after the switching elements Q1 and Q2 are turned off when the voltages V1 and V2 are substantially equal.
When switching elements Q1, Q2 are turned off, secondary diodes D20-D24 are turned on, and current is supplied to secondary capacitors C20-C24.
図9(c)は、電圧V1,V2が略等しい場合において、トランスからエネルギが放出された後の状態を示す説明図である。
スイッチング素子Q1,Q2のターンオフ後、そのオフ状態が所定時間続くと、前記したトランスの励磁インダクタンスに蓄積されたエネルギが、全て放出される。その結果、2次巻線N20~N24には電流が流れなくなる。 FIG. 9C is an explanatory diagram showing a state after energy is released from the transformer when the voltages V1 and V2 are substantially equal.
If the OFF state continues for a predetermined time after the switching elements Q1 and Q2 are turned off, all the energy stored in the exciting inductance of the transformer is released. As a result, no current flows through the secondary windings N20 to N24.
スイッチング素子Q1,Q2のターンオフ後、そのオフ状態が所定時間続くと、前記したトランスの励磁インダクタンスに蓄積されたエネルギが、全て放出される。その結果、2次巻線N20~N24には電流が流れなくなる。 FIG. 9C is an explanatory diagram showing a state after energy is released from the transformer when the voltages V1 and V2 are substantially equal.
If the OFF state continues for a predetermined time after the switching elements Q1 and Q2 are turned off, all the energy stored in the exciting inductance of the transformer is released. As a result, no current flows through the secondary windings N20 to N24.
その後、制御部Mによってスイッチング素子Q1,Q2がターンオンされると、図9(a)の状態に戻る。このようにして、制御部Mは、スイッチング素子Q1,Q2を同じタイミングでターンオンした後、同じタイミングでターンオフするという処理を繰り返す。これによって、電圧V1,V2が略等しい状態が維持される。
Then, when the switching elements Q1 and Q2 are turned on by the control unit M, the state returns to the state of FIG. In this way, the control unit M repeats the process of turning on the switching elements Q1, Q2 at the same timing and then turning off at the same timing. Thereby, the state where the voltages V1 and V2 are substantially equal is maintained.
なお、前記したトランスの励磁インダクタンスが比較的大きい場合には、図7(c)、図8(c)、及び図9(c)の動作を省略してもよい。この場合には、仮にスイッチング素子Q1,Q2をオフ状態で維持しても、トランスの励磁インダクタンスによって2次側に電流が流れ続けるからである。
If the above-described transformer has a relatively large excitation inductance, the operations of FIGS. 7C, 8C, and 9C may be omitted. In this case, even if the switching elements Q1 and Q2 are maintained in the OFF state, the current continues to flow to the secondary side due to the exciting inductance of the transformer.
<効果>
第3実施形態によれば、電圧V1が電圧V2よりも高い場合(図7参照)、電圧V2が電圧V1よりも高い場合(図8参照)、及び、電圧V1,V2が略等しい場合(図9参照)のいずれにおいても、補助電源回路30Bは同じ動作をする。つまり、スイッチング素子Q1,Q2のオン・オフを同じタイミングで切り替えることによって、電圧V1,V2の大小関係に関わらず、結果的に電圧V1,V2が均等化される。つまり、分圧コンデンサCdc1,Cdc2のうち、電圧の高い方から1次側に電流が流れる。これは、1次巻線N1、N2に同程度の電圧が生じるという特性、及び1次ダイオードDb1,Db2の特性によるものである。 <Effect>
According to the third embodiment, when the voltage V1 is higher than the voltage V2 (see FIG. 7), when the voltage V2 is higher than the voltage V1 (see FIG. 8), and when the voltages V1 and V2 are substantially equal (see FIG. 9), the auxiliarypower supply circuit 30B performs the same operation. That is, switching the switching elements Q1, Q2 on and off at the same timing results in equalization of the voltages V1, V2 regardless of the magnitude relationship between the voltages V1, V2. That is, a current flows from the higher voltage of the voltage dividing capacitors Cdc1 and Cdc2 to the primary side. This is due to the characteristic that approximately the same voltage is generated in the primary windings N1 and N2, and the characteristic of the primary diodes Db1 and Db2.
第3実施形態によれば、電圧V1が電圧V2よりも高い場合(図7参照)、電圧V2が電圧V1よりも高い場合(図8参照)、及び、電圧V1,V2が略等しい場合(図9参照)のいずれにおいても、補助電源回路30Bは同じ動作をする。つまり、スイッチング素子Q1,Q2のオン・オフを同じタイミングで切り替えることによって、電圧V1,V2の大小関係に関わらず、結果的に電圧V1,V2が均等化される。つまり、分圧コンデンサCdc1,Cdc2のうち、電圧の高い方から1次側に電流が流れる。これは、1次巻線N1、N2に同程度の電圧が生じるという特性、及び1次ダイオードDb1,Db2の特性によるものである。 <Effect>
According to the third embodiment, when the voltage V1 is higher than the voltage V2 (see FIG. 7), when the voltage V2 is higher than the voltage V1 (see FIG. 8), and when the voltages V1 and V2 are substantially equal (see FIG. 9), the auxiliary
また、制御部Mは、2次側から出力される電圧V20~V24のいずれかを所定値とするように、スイッチング素子Q1、Q2を同じゲートパターンで動作させる。したがって、1次ダイオードDb1,Db2を有しない従来のフライバック形コンバータと同様の簡素な制御方法で、分圧コンデンサCdc1,Cdc2の電圧を均等化できる。
Also, the control unit M operates the switching elements Q1 and Q2 with the same gate pattern so that any one of the voltages V20 to V24 output from the secondary side is a predetermined value. Therefore, the voltages of the voltage dividing capacitors Cdc1 and Cdc2 can be equalized by a simple control method similar to that of a conventional flyback converter having no primary diodes Db1 and Db2.
≪第4実施形態≫
第4実施形態は、第1実施形態と比較して、補助電源回路30C(図10参照)の構成が異なるが、その他(電力変換装置100の全体構成:図1参照)については第1実施形態と同様である。したがって、第1実施形態とは異なる部分について説明し、重複する部分については説明を省略する。 << Fourth Embodiment >>
The fourth embodiment differs from the first embodiment in the configuration of the auxiliarypower supply circuit 30C (see FIG. 10), but the other embodiments (the overall configuration of the power conversion device 100: see FIG. 1) are the first embodiment. It is the same. Therefore, a different part from 1st Embodiment is demonstrated and description is abbreviate | omitted about the overlapping part.
第4実施形態は、第1実施形態と比較して、補助電源回路30C(図10参照)の構成が異なるが、その他(電力変換装置100の全体構成:図1参照)については第1実施形態と同様である。したがって、第1実施形態とは異なる部分について説明し、重複する部分については説明を省略する。 << Fourth Embodiment >>
The fourth embodiment differs from the first embodiment in the configuration of the auxiliary
図10は、第4実施形態に係る電力変換装置が備える補助電源回路30Cの構成図である。なお、図10では、スイッチング素子Q1,Q2,Q4,Q5のゲートと、制御部Mと、を接続する配線の図示を省略している。
図10に示すように、補助電源回路30Cは、磁気回路である鉄心Tと、1次側回路P11,P12と、2次側回路P20~P24と、制御部Mと、を備えるフォワード形の電源回路である。 FIG. 10 is a configuration diagram of anauxiliary power circuit 30C included in the power conversion device according to the fourth embodiment. In FIG. 10, illustration of wirings that connect the gates of the switching elements Q1, Q2, Q4, and Q5 and the control unit M is omitted.
As shown in FIG. 10, the auxiliarypower supply circuit 30C includes a forward power supply including an iron core T, which is a magnetic circuit, primary circuits P11 and P12, secondary circuits P20 to P24, and a control unit M. Circuit.
図10に示すように、補助電源回路30Cは、磁気回路である鉄心Tと、1次側回路P11,P12と、2次側回路P20~P24と、制御部Mと、を備えるフォワード形の電源回路である。 FIG. 10 is a configuration diagram of an
As shown in FIG. 10, the auxiliary
そして、鉄心T、1次巻線N1,N2、及び2次巻線N20~N24によってトランスが構成されている。
A transformer is constituted by the iron core T, the primary windings N1 and N2, and the secondary windings N20 to N24.
1次側回路P11は、分圧コンデンサCdc1(図1参照)の電圧V1が印加される回路である。図10に示すように1次側回路P11は、1次コンデンサC1と、1次巻線N1と、1次ダイオードDb1と、スイッチング素子Q1と、還流ダイオードD1と、スナバ回路Sn4と、を備えている。なお、スナバ回路Sn4以外の各素子については、第3実施形態で説明した1次側回路J11(図6参照)と同様であるから、説明を省略する。
The primary side circuit P11 is a circuit to which the voltage V1 of the voltage dividing capacitor Cdc1 (see FIG. 1) is applied. As shown in FIG. 10, the primary circuit P11 includes a primary capacitor C1, a primary winding N1, a primary diode Db1, a switching element Q1, a freewheeling diode D1, and a snubber circuit Sn4. Yes. The elements other than the snubber circuit Sn4 are the same as the primary side circuit J11 (see FIG. 6) described in the third embodiment, and thus the description thereof is omitted.
図10に示すスナバ回路Sn4は、スイッチング素子Q1のドレイン-ソース間に発生するサージ電圧を抑制するアクティブクランプ形の回路であり、1次巻線N1と一対一で対応して、この1次巻線N1に並列接続されている。スナバ回路Sn4は、コンデンサCs4と、スイッチング素子Q4と、還流ダイオードD4と、を備えている。
A snubber circuit Sn4 shown in FIG. 10 is an active clamp type circuit that suppresses a surge voltage generated between the drain and source of the switching element Q1, and corresponds to the primary winding N1 in a one-to-one correspondence. The line N1 is connected in parallel. The snubber circuit Sn4 includes a capacitor Cs4, a switching element Q4, and a free wheeling diode D4.
図10に示すように、コンデンサCs4と、スイッチング素子Q4と、が直列接続されている。また、スイッチング素子Q4は、ドレインがコンデンサCs4の負極に接続され、ソースが1次ダイオードDb1のアノードに接続されている。また、スイッチング素子Q4には、還流ダイオードD4が逆並列に接続されている。
As shown in FIG. 10, a capacitor Cs4 and a switching element Q4 are connected in series. The switching element Q4 has a drain connected to the negative electrode of the capacitor Cs4 and a source connected to the anode of the primary diode Db1. The switching element Q4 is connected with a freewheeling diode D4 in antiparallel.
1次側回路P12は、分圧コンデンサCdc2(図1参照)の電圧V2が印加される回路である。1次側回路P12の構成は、前記した1次側回路P11と同様であるから、その説明を省略する。
The primary side circuit P12 is a circuit to which the voltage V2 of the voltage dividing capacitor Cdc2 (see FIG. 1) is applied. Since the configuration of the primary side circuit P12 is the same as the primary side circuit P11 described above, the description thereof is omitted.
2次側回路P21は、2次巻線N21と、2次ダイオードD21,D25と、2次コンデンサC21と、インダクタL21と、を備えている。図10に示すように、2次巻線N21と2次ダイオードD21とが直列接続され、これらの2次巻線N21及び2次ダイオードD21に、2次ダイオードD25が並列接続されている。2次ダイオードD21は、アノードが2次巻線N21に接続され、カソードが別の2次ダイオードD25のカソードに接続されている。
The secondary side circuit P21 includes a secondary winding N21, secondary diodes D21 and D25, a secondary capacitor C21, and an inductor L21. As shown in FIG. 10, a secondary winding N21 and a secondary diode D21 are connected in series, and a secondary diode D25 is connected in parallel to the secondary winding N21 and the secondary diode D21. The secondary diode D21 has an anode connected to the secondary winding N21 and a cathode connected to the cathode of another secondary diode D25.
また、2次ダイオードD21,D25のカソードに接続されたインダクタL21を介して、2次コンデンサC21が2次ダイオードD25に並列接続されている。この2次コンデンサC21の両端が、2次側の出力端子になっている。
なお、2次側回路P20,P22~P24については、前記した2次側回路J21と同様の構成であるから、説明を省略する。 A secondary capacitor C21 is connected in parallel to the secondary diode D25 via an inductor L21 connected to the cathodes of the secondary diodes D21 and D25. Both ends of the secondary capacitor C21 are secondary output terminals.
Since the secondary side circuits P20, P22 to P24 have the same configuration as the secondary side circuit J21 described above, description thereof is omitted.
なお、2次側回路P20,P22~P24については、前記した2次側回路J21と同様の構成であるから、説明を省略する。 A secondary capacitor C21 is connected in parallel to the secondary diode D25 via an inductor L21 connected to the cathodes of the secondary diodes D21 and D25. Both ends of the secondary capacitor C21 are secondary output terminals.
Since the secondary side circuits P20, P22 to P24 have the same configuration as the secondary side circuit J21 described above, description thereof is omitted.
また、スイッチング素子Q1,Q4は、そのオン・オフが制御部Mによって交互に切り替えられる。つまり、制御部Mは、スイッチング素子Q1,Q4の一方がオン状態のときには、他方をオフ状態にする。また、制御部Mは、スイッチング素子Q1,Q4のオン・オフの切替時に、所定のデッドタイム(スイッチング素子Q1,Q4の両方がオフ状態の期間)を設ける。なお、スイッチング素子Q2,Q5も同様にして、オン・オフが交互に切り替えられる。
Further, the switching elements Q1 and Q4 are alternately switched on and off by the control unit M. That is, when one of the switching elements Q1 and Q4 is on, the control unit M turns off the other. Further, the control unit M provides a predetermined dead time (period in which both the switching elements Q1 and Q4 are in the off state) when the switching elements Q1 and Q4 are switched on and off. The switching elements Q2 and Q5 are similarly switched on and off in the same manner.
また、制御部Mは、スイッチング素子Q1,Q2を同じタイミングでターンオンした後、同じタイミングでターンオフするという処理を繰り返す。つまり、補助電源回路30Cが備えるスイッチング素子Q1,Q2が、同時にオン状態である期間と、同時にオフ状態である期間と、を有するように動作する。言い換えると、スイッチング素子Q1は、他のスイッチング素子Q2がオン状態であるときには自身もオン状態であり、他のスイッチング素子Q2がオフ状態であるときには自身もオフ状態になっている。
Also, the control unit M repeats the process of turning off the switching elements Q1 and Q2 at the same timing and then turning off at the same timing. That is, the switching elements Q1 and Q2 included in the auxiliary power supply circuit 30C operate so as to have a period in which the auxiliary power supply circuit 30C is in the on state and a period in which the auxiliary power supply circuit 30C is in the off state at the same time. In other words, the switching element Q1 is also in the on state when the other switching element Q2 is in the on state, and is also in the off state when the other switching element Q2 is in the off state.
例えば、電圧V1が電圧V2よりも高い場合において、スイッチング素子Q1,Q2がオン状態、スイッチング素子Q4,Q5がオフ状態のときには、次のように電流が流れる。すなわち、第3実施形態(図7(a))と同様に、1次ダイオードDb1が順バイアスになり、他方の1次ダイオードDb2は逆バイアスになる。したがって、分圧コンデンサCdc1(図1参照)から1次巻線N1に電流が流れるが、その一方で、分圧コンデンサCdc2(図1参照)から1次巻線N2には電流が流れない。その結果、分圧コンデンサCdc1の電圧V1と、分圧コンデンサCdc2の電圧V2と、が均等化される。
For example, when the voltage V1 is higher than the voltage V2, when the switching elements Q1 and Q2 are on and the switching elements Q4 and Q5 are off, current flows as follows. That is, as in the third embodiment (FIG. 7A), the primary diode Db1 is forward biased and the other primary diode Db2 is reverse biased. Therefore, a current flows from the voltage dividing capacitor Cdc1 (see FIG. 1) to the primary winding N1, but no current flows from the voltage dividing capacitor Cdc2 (see FIG. 1) to the primary winding N2. As a result, the voltage V1 of the voltage dividing capacitor Cdc1 and the voltage V2 of the voltage dividing capacitor Cdc2 are equalized.
また、前記したスイッチングの処理において2次側回路P21では、2次ダイオードD21が順バイアスになり、別の2次ダイオードD25が逆バイアスになる。その結果、インダクタL21に電流が流れ、2次コンデンサC20~C24を介して制御回路40等(図1参照)に電力が供給される。
In the switching process described above, in the secondary circuit P21, the secondary diode D21 is forward biased and another secondary diode D25 is reverse biased. As a result, a current flows through the inductor L21, and power is supplied to the control circuit 40 and the like (see FIG. 1) via the secondary capacitors C20 to C24.
その後、スイッチング素子Q1,Q2がオフ状態、スイッチング素子Q4,Q5がオン状態に切り替えられると、前記したトランスの漏れインダクタンスに蓄積されたエネルギが還流ダイオードD4を介してコンデンサCs4に充電され、サージ電圧が吸収される。
Thereafter, when the switching elements Q1 and Q2 are turned off and the switching elements Q4 and Q5 are turned on, the energy accumulated in the leakage inductance of the transformer is charged to the capacitor Cs4 via the freewheeling diode D4, and the surge voltage Is absorbed.
なお、電圧V2が電圧V1よりも高い場合や、電圧V1,V2が略等しい場合も、前記と同様の制御を行うことで、電圧V1,V2が均等化される。
Even when the voltage V2 is higher than the voltage V1 or when the voltages V1 and V2 are substantially equal, the voltages V1 and V2 are equalized by performing the same control as described above.
<効果>
第4実施形態によれば、スイッチング素子Q1,Q2のオン・オフを同じタイミングで切り替えることによって、電圧V1,V2の大小関係に関わらず、結果的に電圧V1,V2が均等化される。
また、補助電源回路30Cがフォワード形であるため、フライバック形の補助電源回路30B(図6参照)を用いる第3実施形態に比べて、高効率化を図ることができ、大きな出力電力を得ることができる。 <Effect>
According to the fourth embodiment, switching the switching elements Q1, Q2 on and off at the same timing results in equalization of the voltages V1, V2 regardless of the magnitude relationship between the voltages V1, V2.
Further, since the auxiliarypower supply circuit 30C is a forward type, higher efficiency can be achieved and a large output power can be obtained compared to the third embodiment using the flyback type auxiliary power supply circuit 30B (see FIG. 6). be able to.
第4実施形態によれば、スイッチング素子Q1,Q2のオン・オフを同じタイミングで切り替えることによって、電圧V1,V2の大小関係に関わらず、結果的に電圧V1,V2が均等化される。
また、補助電源回路30Cがフォワード形であるため、フライバック形の補助電源回路30B(図6参照)を用いる第3実施形態に比べて、高効率化を図ることができ、大きな出力電力を得ることができる。 <Effect>
According to the fourth embodiment, switching the switching elements Q1, Q2 on and off at the same timing results in equalization of the voltages V1, V2 regardless of the magnitude relationship between the voltages V1, V2.
Further, since the auxiliary
≪変形例≫
以上、本発明に係る電力変換装置100等について各実施形態により説明したが、本発明はこれらの記載に限定されるものではなく、種々の変更を行うことができる。
例えば、第3実施形態(図6参照)では、補助電源回路30Bが、2つの1次側回路J11,J12を備える構成について説明したが、これに限らない。例えば、次に説明するように、3つの1次側回路J11,J12,J13を備える構成にしてもよい。 ≪Modification≫
As mentioned above, although each embodiment demonstrated thepower converter device 100 grade | etc., Which concerns on this invention, this invention is not limited to these description, A various change can be performed.
For example, in the third embodiment (see FIG. 6), the configuration in which the auxiliarypower supply circuit 30B includes the two primary side circuits J11 and J12 has been described, but the configuration is not limited thereto. For example, as described below, a configuration including three primary side circuits J11, J12, and J13 may be adopted.
以上、本発明に係る電力変換装置100等について各実施形態により説明したが、本発明はこれらの記載に限定されるものではなく、種々の変更を行うことができる。
例えば、第3実施形態(図6参照)では、補助電源回路30Bが、2つの1次側回路J11,J12を備える構成について説明したが、これに限らない。例えば、次に説明するように、3つの1次側回路J11,J12,J13を備える構成にしてもよい。 ≪Modification≫
As mentioned above, although each embodiment demonstrated the
For example, in the third embodiment (see FIG. 6), the configuration in which the auxiliary
図11は、変形例に係る電力変換装置が備える補助電源回路30Dの構成図である。
図11に示すように、補助電源回路30Dは、1次側回路J11,J12,J13を備えている。1次側回路J11,J12,J13は、図示はしないが、3つの分圧コンデンサと一対一で接続されている。制御部Mは、第3実施形態と同様に、スイッチング素子Q1,Q2,Q3を同じタイミングでターンオンした後、同じタイミングでターンオフするという処理を繰り返す。これによって、3つの分圧コンデンサ(図示せず)の電圧V1,V2,V3が均等化される。
なお、分圧コンデンサ(図示せず)及び1次側回路J11等の個数は、前記したように、3つであってもよいし、また、4つ以上であってもよい。第1、第2、第4実施形態についても同様のことがいえる。 FIG. 11 is a configuration diagram of anauxiliary power circuit 30D included in a power conversion device according to a modification.
As shown in FIG. 11, theauxiliary power circuit 30D includes primary circuits J11, J12, and J13. Although not shown, the primary side circuits J11, J12, and J13 are connected to three voltage dividing capacitors on a one-to-one basis. As in the third embodiment, the control unit M repeats the process of turning on the switching elements Q1, Q2, and Q3 at the same timing and then turning off at the same timing. As a result, the voltages V1, V2, and V3 of the three voltage dividing capacitors (not shown) are equalized.
The number of voltage dividing capacitors (not shown) and the primary side circuit J11 may be three as described above, or may be four or more. The same can be said for the first, second, and fourth embodiments.
図11に示すように、補助電源回路30Dは、1次側回路J11,J12,J13を備えている。1次側回路J11,J12,J13は、図示はしないが、3つの分圧コンデンサと一対一で接続されている。制御部Mは、第3実施形態と同様に、スイッチング素子Q1,Q2,Q3を同じタイミングでターンオンした後、同じタイミングでターンオフするという処理を繰り返す。これによって、3つの分圧コンデンサ(図示せず)の電圧V1,V2,V3が均等化される。
なお、分圧コンデンサ(図示せず)及び1次側回路J11等の個数は、前記したように、3つであってもよいし、また、4つ以上であってもよい。第1、第2、第4実施形態についても同様のことがいえる。 FIG. 11 is a configuration diagram of an
As shown in FIG. 11, the
The number of voltage dividing capacitors (not shown) and the primary side circuit J11 may be three as described above, or may be four or more. The same can be said for the first, second, and fourth embodiments.
また、第3実施形態では、スイッチング素子Q1,Q2のオン・オフを同じタイミングで切り替える処理について説明したが、これに限らない。例えば、電圧V1,V2を検出する電圧センサ(図示せず)を設け、電圧V2よりも電圧V1の方が高い場合には、制御部Mが、スイッチング素子Q1のオン・オフを繰り返し、スイッチング素子Q2をオフ状態で維持するようにしてもよい。このようにしても、第3実施形態(図7(a)を参照)と同様に、スイッチング素子Q1がオン状態のときに分圧コンデンサCdc1から1次巻線N1に電流が流れる。これは、電圧V2よりも電圧V1の方が高い場合には、スイッチング素子Q2のオン・オフの状態に関わらず、分圧コンデンサCdc2から1次巻線N2には電流が流れないからである(図7参照)。また、電圧V1よりも電圧V2の方が高い場合には、制御部Mが、スイッチング素子Q2のオン・オフを繰り返し、スイッチング素子Q1をオフ状態で維持する。これによって、分圧コンデンサCdc1の電圧V1と、分圧コンデンサCdc2の電圧V2と、が均等化される。なお、第4実施形態についても同様のことがいえる。
In the third embodiment, the process of switching on / off of the switching elements Q1, Q2 at the same timing has been described. However, the present invention is not limited to this. For example, when a voltage sensor (not shown) for detecting the voltages V1 and V2 is provided, and the voltage V1 is higher than the voltage V2, the control unit M repeatedly turns on and off the switching element Q1, thereby switching the switching element Q2 may be maintained in the off state. Even in this case, as in the third embodiment (see FIG. 7A), current flows from the voltage dividing capacitor Cdc1 to the primary winding N1 when the switching element Q1 is in the ON state. This is because when the voltage V1 is higher than the voltage V2, no current flows from the voltage dividing capacitor Cdc2 to the primary winding N2 regardless of the ON / OFF state of the switching element Q2. (See FIG. 7). Further, when the voltage V2 is higher than the voltage V1, the control unit M repeats on / off of the switching element Q2, and maintains the switching element Q1 in the off state. As a result, the voltage V1 of the voltage dividing capacitor Cdc1 and the voltage V2 of the voltage dividing capacitor Cdc2 are equalized. The same applies to the fourth embodiment.
また、第3実施形態(図6参照)では、還流ダイオードD1,D2を設ける構成について説明したが、これらの還流ダイオードD1,D2を省略してもよい。通常の制御において還流ダイオードD1,D2に電流が流れることは、ほとんどないからである(図7~図9を参照)。なお、第4実施形態についても同様のことがいえる。
また、スイッチング素子Q1、Q2(図6参照)として、1次ダイオードDb1、Db2が担っていた逆阻止能力を有する素子を用いる場合には、これらの1次ダイオードDb1,Db2を省略してもよい。つまり、補助電源回路が、「1次ダイオードとして、スイッチング素子の逆阻止能力」を用いる構成であってもよい。これによって、さらなる低コスト化を図ることができる。 In the third embodiment (see FIG. 6), the configuration in which the freewheeling diodes D1 and D2 are provided has been described. However, the freewheeling diodes D1 and D2 may be omitted. This is because almost no current flows through the freewheeling diodes D1 and D2 in the normal control (see FIGS. 7 to 9). The same applies to the fourth embodiment.
Moreover, when using the element which has the reverse blocking capability which primary diode Db1 and Db2 were carrying out as switching element Q1 and Q2 (refer FIG. 6), you may abbreviate | omit these primary diodes Db1 and Db2. . That is, the auxiliary power supply circuit may be configured to use “the reverse blocking ability of the switching element as the primary diode”. Thereby, further cost reduction can be achieved.
また、スイッチング素子Q1、Q2(図6参照)として、1次ダイオードDb1、Db2が担っていた逆阻止能力を有する素子を用いる場合には、これらの1次ダイオードDb1,Db2を省略してもよい。つまり、補助電源回路が、「1次ダイオードとして、スイッチング素子の逆阻止能力」を用いる構成であってもよい。これによって、さらなる低コスト化を図ることができる。 In the third embodiment (see FIG. 6), the configuration in which the freewheeling diodes D1 and D2 are provided has been described. However, the freewheeling diodes D1 and D2 may be omitted. This is because almost no current flows through the freewheeling diodes D1 and D2 in the normal control (see FIGS. 7 to 9). The same applies to the fourth embodiment.
Moreover, when using the element which has the reverse blocking capability which primary diode Db1 and Db2 were carrying out as switching element Q1 and Q2 (refer FIG. 6), you may abbreviate | omit these primary diodes Db1 and Db2. . That is, the auxiliary power supply circuit may be configured to use “the reverse blocking ability of the switching element as the primary diode”. Thereby, further cost reduction can be achieved.
また、第3実施形態では、1次巻線N1,N2の巻数が略等しい場合について説明したが、目標とする電圧V1と電圧V2の分圧比に応じて(つまり、分圧コンデンサCdc1,Cdc2の特性に応じて)、1次巻線N1,N2を異なる巻数にしてもよい。この場合において電圧V1,V2の分圧比は、1次巻線N1,N2の巻数比と略等しい値になる。なお、第4実施形態についても同様のことがいえる。
In the third embodiment, the case where the numbers of turns of the primary windings N1 and N2 are substantially equal has been described. However, according to the target voltage division ratio between the voltage V1 and the voltage V2 (that is, the voltage dividing capacitors Cdc1 and Cdc2 Depending on the characteristics, the primary windings N1, N2 may have different numbers of turns. In this case, the voltage division ratio between the voltages V1 and V2 is substantially equal to the turn ratio of the primary windings N1 and N2. The same applies to the fourth embodiment.
また、第3実施形態で説明したフライバック形の回路(図6参照)や、第4実施形態で説明したフォワード形の回路(図10参照)は一例であり、他の周知のフライバック形又はフォワード形の回路を用いてもよい。
Further, the flyback circuit described in the third embodiment (see FIG. 6) and the forward circuit described in the fourth embodiment (see FIG. 10) are examples, and other known flyback circuits or A forward type circuit may be used.
また、第3実施形態(図6参照)では、1次巻線N1、1次ダイオードDb1、及びスイッチング素子Q1が順次に直列接続される構成について説明したが、これに限らない。例えば、1次巻線N1、スイッチング素子Q1、及び1次ダイオードDb1が順次に直列接続される構成にしてもよい。なお、第4実施形態についても同様のことがいえる。
In the third embodiment (see FIG. 6), the configuration in which the primary winding N1, the primary diode Db1, and the switching element Q1 are sequentially connected in series has been described. However, the present invention is not limited to this. For example, the primary winding N1, the switching element Q1, and the primary diode Db1 may be sequentially connected in series. The same applies to the fourth embodiment.
また、各実施形態は、太陽光発電用PCS(Power Conditioning System)や無停電電源システム(UPS:Uninterruptible Power Supply)の他、マルチレベルインバータ等にも適用できる。
Further, each embodiment can be applied to a multi-level inverter or the like in addition to a PCS (Power Conditioning System) for photovoltaic power generation and an uninterruptible power system (UPS).
また、各実施形態は、適宜組み合わせることができる。例えば、第2実施形態と第3実施形態とを組み合わせ、無停電電源システムSが、図6に示す補助電源回路30Bを備える構成にしてもよい。また、例えば、第2実施形態と第4実施形態とを組み合わせ、無停電電源システムSが、図10に示す補助電源回路30Cを備える構成にしてもよい。
Further, the embodiments can be combined as appropriate. For example, the uninterruptible power supply system S may be configured to include the auxiliary power supply circuit 30B illustrated in FIG. 6 by combining the second embodiment and the third embodiment. Further, for example, the uninterruptible power supply system S may include the auxiliary power supply circuit 30C illustrated in FIG. 10 by combining the second embodiment and the fourth embodiment.
また、各実施形態は本発明を分かりやすく説明するために詳細に記載したものであり、必ずしも説明した全ての構成を備えるものに限定されない。また、実施形態の構成の一部について、他の構成の追加・削除・置換をすることが可能である。また、前記した機構や構成は説明上必要と考えられるものを示しており、製品上必ずしも全ての機構や構成を示しているとは限らない。
Each embodiment is described in detail for easy understanding of the present invention, and is not necessarily limited to one having all the configurations described. Further, it is possible to add, delete, and replace other configurations for a part of the configuration of the embodiment. In addition, the above-described mechanisms and configurations are those that are considered necessary for the description, and do not necessarily indicate all the mechanisms and configurations on the product.
100,100A,100B,100C,100D 電力変換装置
10 DC-DCコンバータ(電力変換回路)
20 インバータ(電力変換回路)
30,30A,30B,30C,30D 補助電源回路(電源回路)
31,32 DC-DCコンバータ(電力変換回路、直流‐直流変換器)
33,34 電圧センサ
35 制御部
40 制御回路(電力の供給対象)
50 ファン(電力の供給対象)
60 コンバータ(電力変換回路、交直変換器)
70 インバータ(電力変換回路)
80 DC-DCコンバータ(電力変換回路、直流‐直流変換器)
Cdc1,Cdc2 分圧コンデンサ
C20,C21,C22,C23,C24 2次コンデンサ
D20,D21,D22,D23,D24 2次ダイオード
Db1,Db2,Db3 1次ダイオード
M 制御部
N1,N2,N3 1次巻線
N20,N21,N22,N23,N24 2次巻線
Q1,Q2,Q3 スイッチング素子
Sn1,Sn2,Sn4,Sn5 スナバ回路
T 鉄心 100, 100A, 100B, 100C, 100DPower conversion device 10 DC-DC converter (power conversion circuit)
20 Inverter (Power conversion circuit)
30, 30A, 30B, 30C, 30D Auxiliary power circuit (power circuit)
31, 32 DC-DC converter (Power conversion circuit, DC-DC converter)
33, 34Voltage sensor 35 Control unit 40 Control circuit (power supply target)
50 fans (subject of power supply)
60 Converter (power conversion circuit, AC / DC converter)
70 Inverter (Power conversion circuit)
80 DC-DC converter (Power conversion circuit, DC-DC converter)
Cdc1, Cdc2 Voltage dividing capacitor C20, C21, C22, C23, C24 Secondary capacitor D20, D21, D22, D23, D24 Secondary diode Db1, Db2, Db3 Primary diode M Control unit N1, N2, N3 Primary winding N20, N21, N22, N23, N24 Secondary winding Q1, Q2, Q3 Switching element Sn1, Sn2, Sn4, Sn5 Snubber circuit T Iron core
10 DC-DCコンバータ(電力変換回路)
20 インバータ(電力変換回路)
30,30A,30B,30C,30D 補助電源回路(電源回路)
31,32 DC-DCコンバータ(電力変換回路、直流‐直流変換器)
33,34 電圧センサ
35 制御部
40 制御回路(電力の供給対象)
50 ファン(電力の供給対象)
60 コンバータ(電力変換回路、交直変換器)
70 インバータ(電力変換回路)
80 DC-DCコンバータ(電力変換回路、直流‐直流変換器)
Cdc1,Cdc2 分圧コンデンサ
C20,C21,C22,C23,C24 2次コンデンサ
D20,D21,D22,D23,D24 2次ダイオード
Db1,Db2,Db3 1次ダイオード
M 制御部
N1,N2,N3 1次巻線
N20,N21,N22,N23,N24 2次巻線
Q1,Q2,Q3 スイッチング素子
Sn1,Sn2,Sn4,Sn5 スナバ回路
T 鉄心 100, 100A, 100B, 100C, 100D
20 Inverter (Power conversion circuit)
30, 30A, 30B, 30C, 30D Auxiliary power circuit (power circuit)
31, 32 DC-DC converter (Power conversion circuit, DC-DC converter)
33, 34
50 fans (subject of power supply)
60 Converter (power conversion circuit, AC / DC converter)
70 Inverter (Power conversion circuit)
80 DC-DC converter (Power conversion circuit, DC-DC converter)
Cdc1, Cdc2 Voltage dividing capacitor C20, C21, C22, C23, C24 Secondary capacitor D20, D21, D22, D23, D24 Secondary diode Db1, Db2, Db3 Primary diode M Control unit N1, N2, N3 Primary winding N20, N21, N22, N23, N24 Secondary winding Q1, Q2, Q3 Switching element Sn1, Sn2, Sn4, Sn5 Snubber circuit T Iron core
Claims (12)
- 電力変換を行う電力変換回路と、
前記電力変換回路の直流側に接続され、前記直流側から印加される直流電圧を分圧する複数の分圧コンデンサと、
複数の前記分圧コンデンサのそれぞれの両端に接続され、複数の前記分圧コンデンサのうち、電圧のより高い分圧コンデンサから、より大きな電流を自身に入力する電源回路と、を備えること
を特徴とする電力変換装置。 A power conversion circuit for performing power conversion;
A plurality of voltage dividing capacitors connected to the DC side of the power conversion circuit and dividing a DC voltage applied from the DC side;
A power supply circuit that is connected to both ends of each of the plurality of voltage dividing capacitors and inputs a larger current to itself from a voltage dividing capacitor having a higher voltage among the plurality of voltage dividing capacitors. Power converter. - 前記電源回路は、
複数の直流‐直流変換器と、
複数の前記直流‐直流変換器を制御する制御部と、を備え、
前記直流‐直流変換器は、前記分圧コンデンサと一対一で対応して、その入力側が前記分圧コンデンサの両端に接続され、出力側が電力の供給対象に接続され、
前記制御部は、前記分圧コンデンサから前記直流‐直流変換器に入力される電流を調整すること
を特徴とする請求項1に記載の電力変換装置。 The power supply circuit is
A plurality of DC-DC converters,
A controller that controls the plurality of DC-DC converters,
The DC-DC converter has a one-to-one correspondence with the voltage dividing capacitor, its input side is connected to both ends of the voltage dividing capacitor, and its output side is connected to a power supply target,
The power converter according to claim 1, wherein the control unit adjusts a current input from the voltage dividing capacitor to the DC-DC converter. - 前記電源回路は、
磁気回路である鉄心の1次側に巻回される1次巻線と、1次ダイオードと、スイッチング素子と、が直列接続されてなる直列接続体を複数備えるとともに、
前記鉄心の2次側に巻回される2次巻線と、
前記スイッチング素子のオン・オフを制御する制御部と、を備え、
前記直列接続体は、前記分圧コンデンサと一対一で対応して、その両端が前記分圧コンデンサの両端に接続され、
前記1次ダイオードは、前記分圧コンデンサの正極から自身に向かう電流を許容し、逆向きの電流を阻止するように接続されること
を特徴とする請求項1に記載の電力変換装置。 The power supply circuit is
A plurality of serially connected bodies in which a primary winding wound around a primary side of an iron core that is a magnetic circuit, a primary diode, and a switching element are connected in series,
A secondary winding wound around the secondary side of the iron core;
A control unit for controlling on / off of the switching element,
The series connection body has a one-to-one correspondence with the voltage dividing capacitor, and both ends thereof are connected to both ends of the voltage dividing capacitor,
2. The power converter according to claim 1, wherein the primary diode is connected so as to allow a current from the positive electrode of the voltage dividing capacitor toward the self and to block a reverse current. - 前記電源回路が備える複数の前記スイッチング素子が、同時にオン状態である期間と、同時にオフ状態である期間と、を有するように動作すること
を特徴とする請求項3に記載の電力変換装置。 The power conversion device according to claim 3, wherein the plurality of switching elements included in the power supply circuit operate so as to have a period in which the switching elements are simultaneously on and a period in which the switching elements are simultaneously off. - 前記電源回路は、前記1次ダイオードとして、前記スイッチング素子の逆阻止能力を用いること
を特徴とする請求項3に記載の電力変換装置。 The power converter according to claim 3, wherein the power supply circuit uses a reverse blocking capability of the switching element as the primary diode. - 前記電源回路は、前記スイッチング素子に生じるサージ電圧を抑制するスナバ回路を複数備え、
前記スナバ回路は、前記1次巻線と一対一で対応して、前記1次巻線に並列接続されること
を特徴とする請求項3に記載の電力変換装置。 The power supply circuit includes a plurality of snubber circuits that suppress a surge voltage generated in the switching element,
The power converter according to claim 3, wherein the snubber circuit is connected in parallel to the primary winding in a one-to-one correspondence with the primary winding. - 前記電源回路は、
磁気回路である鉄心の1次側に巻回される1次巻線を備えるとともに、
前記鉄心の2次側に巻回される2次巻線と、前記2次巻線に直列接続される2次ダイオードと、前記2次巻線及び前記2次ダイオードに並列接続される2次コンデンサと、を備え、
前記2次ダイオードは、自身を介して前記2次巻線から前記2次コンデンサの正極に向かう電流を許容し、逆向きの電流を阻止するように接続され、
前記2次コンデンサの両端から電力が出力されること
を特徴とする請求項1に記載の電力変換装置。 The power supply circuit is
With a primary winding wound around the primary side of the iron core, which is a magnetic circuit,
A secondary winding wound around the secondary side of the iron core, a secondary diode connected in series to the secondary winding, and a secondary capacitor connected in parallel to the secondary winding and the secondary diode And comprising
The secondary diode is connected so as to allow a current from the secondary winding to the positive electrode of the secondary capacitor through itself and prevent a reverse current;
The power converter according to claim 1, wherein power is output from both ends of the secondary capacitor. - 前記電源回路は、前記電力変換回路を制御する制御回路に電力を供給すること
を特徴とする請求項1から請求項7のいずれか一項に記載の電力変換装置。 The power converter according to any one of claims 1 to 7, wherein the power supply circuit supplies power to a control circuit that controls the power converter circuit. - 前記電源回路は、前記電力変換回路を冷却するファンに電力を供給すること
を特徴とする請求項1から請求項7のいずれか一項に記載の電力変換装置。 The power converter according to any one of claims 1 to 7, wherein the power supply circuit supplies power to a fan that cools the power converter circuit. - 前記電力変換回路は、直流電圧を交流電圧に変換するインバータを含み、
複数の前記分圧コンデンサは、前記インバータの直流側に接続されること
を特徴とする請求項1から請求項7のいずれか一項に記載の電力変換装置。 The power conversion circuit includes an inverter that converts a DC voltage into an AC voltage;
The power converter according to any one of claims 1 to 7, wherein the plurality of voltage dividing capacitors are connected to a direct current side of the inverter. - 前記電力変換回路は、交流電圧を直流電圧に変換する交直変換器を含み、
複数の前記分圧コンデンサは、前記交直変換器の直流側に接続されること
を特徴とする請求項1から請求項7のいずれか一項に記載の電力変換装置。 The power conversion circuit includes an AC / DC converter that converts an AC voltage into a DC voltage,
The power converter according to any one of claims 1 to 7, wherein the plurality of voltage dividing capacitors are connected to a DC side of the AC / DC converter. - 前記電力変換回路は、直流電圧を昇圧又は降圧する直流-直流変換器を含み、
複数の前記分圧コンデンサは、前記直流-直流変換器の出力側に接続されること
を特徴とする請求項1から請求項7のいずれか一項に記載の電力変換装置。 The power conversion circuit includes a DC-DC converter that boosts or reduces a DC voltage,
The power converter according to any one of claims 1 to 7, wherein the plurality of voltage dividing capacitors are connected to an output side of the DC-DC converter.
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