WO2018036088A1 - Amoled扫描驱动电路及方法、液晶显示面板及装置 - Google Patents

Amoled扫描驱动电路及方法、液晶显示面板及装置 Download PDF

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Publication number
WO2018036088A1
WO2018036088A1 PCT/CN2017/070643 CN2017070643W WO2018036088A1 WO 2018036088 A1 WO2018036088 A1 WO 2018036088A1 CN 2017070643 W CN2017070643 W CN 2017070643W WO 2018036088 A1 WO2018036088 A1 WO 2018036088A1
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Prior art keywords
signal
logic
shift register
unit
start pulse
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PCT/CN2017/070643
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English (en)
French (fr)
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王振岭
黄泰钧
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深圳市华星光电技术有限公司
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Priority to US15/328,514 priority Critical patent/US10522086B2/en
Publication of WO2018036088A1 publication Critical patent/WO2018036088A1/zh

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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0224—Details of interlacing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
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    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
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    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention belongs to the field of liquid crystal display technology, and in particular, to an AMOLED scan driving circuit and method, a liquid crystal display panel and a device.
  • FIG. 1 The architecture of the existing AMOLED scan driver circuit is shown in FIG. 1.
  • the corresponding basic function module is shown in FIG. 2, which can only be used for the AMOLED scan driver circuit that requires a single gate control signal.
  • the existing scan driving compensation circuit cannot satisfy the requirement of outputting multiple gate control signals.
  • the present invention provides an AMOLED scan driving circuit and method, a liquid crystal display panel and a device for providing a plurality of scan driving signals.
  • an AMOLED scan driving circuit comprising:
  • a selector is disposed between adjacent shift register units and between adjacent logic units, and a portion of the shift register units and a portion of the logic units are connected by a selector, and a control signal is selected to control the selector and the clock.
  • the signal and the start pulse signal control the shift register unit and the logic signal control logic unit to output different scan drive signals.
  • the shift register units and the logic unit are connected by a selector interlace, wherein an odd row shift register unit and an odd row logic unit pass between The odd row selectors should be connected, and the even row shift register cells and the even row logic cells are connected by corresponding even row selectors.
  • the output of the logic unit is further connected with a level shifting unit and a digital buffer unit.
  • the shift register units and the logic unit are connected by a selector interlace, wherein
  • odd row shift register cells and the odd row logic cells are connected by corresponding odd row selectors, and the even row shift register cells and the even row logic cells are connected by corresponding even row selectors;
  • Each shift register unit is connected by two rows of selectors corresponding to the row of the shift register unit in the preceding layout, and each logic unit is connected by two rows of selectors corresponding to the corresponding row of the logical unit in the preceding layout.
  • the output of the logic unit is further connected with a level shifting unit and a digital buffer unit.
  • an AMOLED scan driving method including:
  • the logic signal controls the logic unit to output different scan drive signals
  • the clock signal includes a first clock signal and a second clock signal
  • the start pulse signal includes a first start pulse signal and a second start pulse signal
  • the logic signal includes a first logic signal and a second logic signal
  • the selection control signal When the selection control signal is in the first state, the first clock signal, the second clock signal, the first start pulse signal and the first logic signal are valid, and the scan signals are sequentially output according to the output line number;
  • the output line number is a set of sequential outputs, wherein a set of internal scan signal outputs are N, N+2, N+1, and N+3, where N is the first output line number in the group.
  • the clock signal includes a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, and a fifth clock signal
  • the start signal includes a first start pulse signal, a second start pulse signal, and a third start a pulse signal
  • the logic signal including a first logic signal, a second logic signal, and a third logic Signal
  • the selection control signal When the selection control signal is in the first state, the first clock signal, the second clock signal, the first start pulse signal and the first logic signal are valid, and the scan signals are sequentially output according to the output line number;
  • the line number is a set of sequential outputs, wherein a set of internal scan signal outputs are N, N+2, N+1, and N+3, where N is the first output line number in the group;
  • the scan signal is sequentially outputted by the adjacent six output line numbers, wherein the output of one set of internal scan signals is N, N+3, N+1, N+4, N+ 2 and N+5, N is the first output line number in the group.
  • liquid crystal display panel comprising the AMOLED scan driving circuit described above and the AMOLED scan driving method using the above.
  • liquid crystal display device comprising the liquid crystal display panel described above.
  • the scan drive signals outputting different waveforms can be correspondingly selected, so that the output waveform of the scan drive circuit can be selected through an external control signal, which is convenient to do. Double drive design.
  • FIG. 1 is a schematic diagram of an AMOLED scan driving circuit in the prior art
  • FIG. 2 is a schematic diagram of an internal basic function module corresponding to FIG. 1;
  • FIG. 3 is a schematic diagram of an internal basic function module according to an embodiment of the present invention.
  • 4 is a schematic diagram of a 4T1C internal compensation circuit in the prior art
  • Figure 5 is a timing diagram corresponding to Figure 4.
  • Figure 6 is a timing diagram corresponding to each signal of Figure 3;
  • FIG. 7 is a schematic diagram of an internal basic functional module in accordance with another embodiment of the present invention.
  • the present invention provides an AMOLED scan driving circuit, as shown in FIG. 3 and FIG. A schematic diagram of internal basic functional modules of an AMOLED scan driving circuit according to an embodiment of the present invention. The present invention will be described in detail below with reference to FIGS. 3 and 7.
  • the AMOLED scan driving circuit includes a shift register unit and a logic unit, wherein a selector is disposed between adjacent shift register units and between adjacent logic units, between the partial shift register units and between the partial logic units Through the selector communication, different scan driving signals are output in the case of selecting the control signal control selector, the clock signal, and the start pulse signal to control the shift register unit and the logic signal control logic unit.
  • the scan drive signals outputting different waveforms can be correspondingly selected, so that the output waveform of the scan drive circuit can be selected through an external control signal, which is convenient to do. Double drive design.
  • FIG. 3 is a block diagram of an AMOLED scan driving circuit according to an embodiment of the present invention. As shown in FIG. 3, a plurality of shift register units S/R are arranged in parallel, and the logic unit Log is connected in one-to-one correspondence with the shift register unit S/R, between adjacent shift register units and between adjacent logic units. A selector is provided, and the selector is controlled by the selection control signal Sel.
  • a level converting unit L/S and a digital buffer unit D/B are sequentially connected to the output end of each logic unit.
  • the level conversion unit performs level conversion under the control of the turn-on voltage Vg ,on , and stops level conversion under the control of the off voltage Vg ,off ;
  • the digital buffer unit buffers and outputs the scan drive signal under the control of the turn-on voltage Vg ,on Stop the buffer and output the scan drive signal under the control of the off voltage V g, off .
  • the shift register units and the logic cells are connected by a selector interleave, wherein the odd row shift register unit and the odd row logic unit are connected by corresponding odd row selectors, and the even row shift register is connected.
  • the cells and even row logic cells are connected by corresponding even row selectors.
  • the clock signal herein includes a first clock signal CPV1 and a second clock signal CPV2
  • the start pulse signal includes a first start pulse signal STV1 and a second start pulse signal STV2
  • the logic signal includes a first logic signal ENA and a second logic Signal ENB.
  • Different scan driving signals of different waveforms may be output by different combinations of the first clock signal and the second clock signal, the first start pulse signal and the second start pulse signal, the first logic signal, and the second logic signal.
  • the AMOLED scan driving circuit shown in FIG. 3 can output scan signals of two waveforms. Specifically, in the first case: when the control signal Sel is selected as the first state, the first clock signal, the second clock signal, and the first start pulse When the signal and the first logic signal are valid, the scan signals are sequentially outputted according to the output line number, that is, the scan drive circuit can be controlled to output the scan signals in the order of G1, G2, G3, G4, G5, G6.
  • each shift register unit controls the scan drive circuit to be G1, G2, G3, G4, G5, G6 under the action of the first clock signal, the second clock signal and the first start pulse signal. The order of ... outputs the scan signal.
  • the signal is sequentially outputted in groups of four adjacent output line numbers, wherein a set of internal scan signal outputs are N, N+2, N+1, and N+3, and N is the first output line in the group.
  • the scan drive circuit can be controlled to output scan signals in the order of G1, G3, G2, G4, G5, G7, G6, G8.
  • the odd row shift register cells are connected by the odd row selectors
  • the even row shift register cells are connected by the corresponding even row selectors
  • the adjacent odd row shift register cells and the even rows are shifted.
  • the registration unit is not connected.
  • the odd row shift register unit is operated by the first clock signal and the first start pulse signal
  • the even row shift register unit acts on the first logic signal under the action of the second clock signal and the second start pulse signal
  • the even-numbered row logic unit can control the scan driving circuit to output the scan signals in the order of G1, G3, G2, G4, G5, G7, G6, G8... under the action of the second logic signal.
  • the selection control signal Sel when the selection control signal Sel is in the second state, the first clock signal and the first start pulse signal are turned on, S ⁇ R1 turns on the output scan signal G1, and S ⁇ R1 outputs a similar start signal and is output through the selector.
  • S ⁇ R3, S ⁇ R3 turns on the output scan signal G3.
  • the selection control signal Sel is kept in the second state, and S ⁇ R2 turns on the output scan signal.
  • the S ⁇ R2 output similar start signal is output to S ⁇ R4 through the selector, and S ⁇ R4 turns on the output scan signal G4.
  • the first clock signal and the first start pulse signal are turned on, and when the selection control signal Sel is kept in the second state, the scan signals G5, G7 are output, and so on.
  • the scan signal can be output in an arbitrary order under the condition that the shift register unit and the logic unit are connected through the selector, and the corresponding clock signal, start pulse signal, and logic signal are adjusted.
  • the waveforms of the first clock signal and the second clock signal, the first start pulse signal and the second start pulse signal, the first logic signal, and the second logic signal may be controlled by the timing control circuit TCON to satisfy The scan control signal required by the compensation circuit.
  • FIG. 4 is a schematic diagram of a conventional 4T1C internal compensation circuit.
  • the scan driving signal shown in FIG. 3 is input through the DATA terminal of FIG. 4, and is output to the control signals SEL1 and SEL2, and the input signal IN and the driving signal Vdd.
  • Organic light emitting diode OLED Organic light emitting diode OLED.
  • the timings of the input signals of the control signals SEL1, SEL2 and DATA are as shown in FIG. 5, and the timings of the respective control signals and output signals of FIG. 3 corresponding to the input data of the DATA terminal are as shown in FIG. 6.
  • FIG. 7 is a schematic diagram of a basic functional block of an AMOLED scan driving circuit according to another embodiment of the present invention.
  • a plurality of shift register units S/R are arranged in parallel, and the logic unit is connected in one-to-one correspondence with the shift register unit, and a selection is made between adjacent shift register units and adjacent logic units.
  • the selector, the partial shift register unit and the partial logic unit are connected by a selector, and the selector is controlled by the selection control signal Sel.
  • each logic unit is also sequentially connected with a level converting unit L/S and a digital buffer unit D/B, and the two units output scanning under the control of the opening voltage V g,on
  • the drive signal stops outputting the scan drive signal under the control of the off voltage V g,off .
  • the shift register units and the logic cells are connected by a selector interlace, wherein the odd row shift register cells and the odd row logic cells are connected by corresponding odd row selectors, even numbers.
  • the row shift register units and the even row logic cells are connected by corresponding even row selectors.
  • each shift register unit is connected by two rows of selectors corresponding to the row of the shift register unit arranged on the upper side, and each logic unit is separated by two rows by a selector of the corresponding row of the logical unit arranged on the upper row. connection. That is, the first row shift register unit S/R1 is connected to the fourth row shift register unit S/R4 through the selector corresponding to the first row, and the second row logic unit passes the selector corresponding to the second row and the fifth row logic unit. connection.
  • the clock signal includes a first clock signal CPV1, a second clock signal CPV2, a third clock signal CPV3, a fourth clock signal CPV4, and a fifth clock signal CPV5, and a total of five clock signals;
  • the start signal includes a first start The pulse signal STV1, the second start pulse signal STV2, and the third start pulse signal STV3;
  • the logic signal includes a first logic signal ENA, a second logic signal ENB, and a third logic signal ENC.
  • the selector between the adjacent shift register units is connected to the adjacent shift register unit, and the selector between the adjacent logic units is connected to the adjacent logic unit.
  • Each shift register unit controls the scan drive circuit to be G1, G2, G3, G4, G5, G6 under the action of the first clock signal, the second clock signal and the first start pulse signal. The order of ... outputs the scan signal.
  • the logic signals are all valid, and the scan signals are sequentially outputted in groups of four adjacent output line numbers, wherein the output of one set of internal scan signals is N, N+2, N+1, and N+3, and N is the group.
  • the first output line number in the inside can control the scan drive circuit to output the scan signals in the order of G1, G3, G2, G4, G5, G7.
  • the odd row shift register unit is connected by the odd row selector
  • the even row shift register unit is connected by the corresponding even row selector
  • the adjacent odd row shift register unit and the even number The row shift register unit is not connected.
  • the odd row shift register unit is operated by the first clock signal and the first start pulse signal
  • the even row shift register unit acts on the first logic signal under the action of the second clock signal and the second start pulse signal
  • the even-numbered row logic unit can control the scan driving circuit to output the scan signals in the order of G1, G3, G2, G4, G5, G7... under the action of the second logic signal, and the specific signal matching process is the same as that of FIG. No longer detailed.
  • the scan signal is sequentially outputted in groups of six adjacent output line numbers, wherein the output of one set of internal scan signals is N, N+3, N+1, N+4, N+2, and N+5.
  • N is the first output line number in the group, that is, the scan driving circuit can be controlled to output the scanning signals in the order of G1, G4, G2, G5, G3, G6.
  • the selection control signal Sel when the selection control signal Sel is in the third state, when the third clock signal, the first start pulse signal and the first logic signal cooperate, the G1, G4 output signals; the fourth clock signal, the second start pulse signal, and the When the two logic signals work together, the G2 and G5 output signals; when the fifth clock signal, the third start pulse signal and the third logic signal work together, the G3, G6 output signals, and so on.
  • the scanning signals can be output in the order of G1, G4, G2, G5, G3, G6...
  • the scan signal can be output in an arbitrary order under the condition that the shift register unit and the logic unit are connected through the selector, and the corresponding clock signal, start pulse signal, and logic signal are adjusted.
  • each signal can be controlled by the timing control circuit TCON to satisfy the scan control signal required by the compensation circuit.
  • an AMOLED scan driving method comprising: controlling a partial shift register unit disposed between adjacent shift register units and between adjacent logic units by selecting a control signal a selector between the inter- and partial logic units, in combination with the clock signal and the start pulse signal, controls the shift register unit and the logic signal control logic unit to output different scan drive signals
  • the clock signal includes a first clock signal and a second clock signal
  • the start pulse signal includes a first start pulse signal and a second start pulse signal
  • the logic signal includes the first logic signal and the Two logic signals
  • the scan driving circuit can be controlled G1, G2, G3, G4, G5, G6, G7, G8... sequentially output scan signals;
  • the first clock signal, the second clock signal, the first start pulse signal, the second start pulse signal, the first logic signal, and the second logic signal are all valid, and the scan signal is adjacent to four
  • the output line number is divided into a set of sequential outputs, wherein a set of internal scan signal outputs are N, N+2, N+1, and N+3, and N is the first output line number in the group, that is, G1 , G3, G2, G4, G5, G7, G6, G8... sequentially output scan signals.
  • the clock signal includes a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, and a fifth clock signal
  • the start signal includes a first start pulse signal and a second start pulse.
  • a third start pulse signal the logic signal comprising a first logic signal, a second logic signal, and a third logic signal.
  • the selection control signal When the selection control signal is in the first state, the first clock signal, the second clock signal, the first start pulse signal and the first logic signal are valid, and the scan signal is sequentially outputted according to the output line number, that is, G1, G2, G3 , G4, G5, G6... output the scan signal in sequence.
  • the first clock signal, the second clock signal, the first start pulse signal, the second start pulse signal, the first logic signal, and the second logic signal are all valid, and the scan signal is adjacent to four
  • the output line number is divided into a set of sequential outputs, wherein a set of internal scan signal outputs are N, N+2, N+1, and N+3, and N is the first output line number in the group, that is, G1 , G3, G2, G4, G5, G7... sequentially output the scan signal.
  • the third clock signal, the fourth clock signal and the fifth clock signal When the control signal is selected as the third state, the third clock signal, the fourth clock signal and the fifth clock signal, the first start pulse signal, the second start pulse signal, the third start pulse signal, the first logic signal, the second logic
  • the signal and the third logic signal are both valid, and the scan signal is sequentially outputted in groups of six adjacent output line numbers, wherein the output of one set of internal scan signals is N, N+3, N+1, N+4, N+2 and N+5, N is the first output line number in the group, and N is the first output line number in the group, that is, in the order of G1, G4, G2, G5, G3, G6...
  • the scan signal is output.
  • liquid crystal display panel comprising the above-described AMOLED scan driving circuit and the AMOLED scan driving method using the above.
  • liquid crystal display device comprising the liquid crystal display panel described above.

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Abstract

一种AMOLED扫描驱动电路及方法、液晶显示面板及装置，该电路包括：移位寄存单元（S/R）；逻辑单元（Log），在相邻移位寄存单元（S/R）之间和相邻逻辑单元（Log）之间设置有选择器，在选择控制信号（Sel）控制选择器、时钟信号（CPV）及启动脉冲信号（STV）控制移位寄存单元（S/R）、逻辑信号（EN）控制逻辑单元（Log）情况下输出不同的扫描驱动信号（G）。

Description

AMOLED扫描驱动电路及方法、液晶显示面板及装置
相关申请的交叉引用
本申请要求享有2016年08月24日提交的名称为“AMOLED扫描驱动电路及方法、液晶显示面板及装置”的中国专利申请CN201610714844.1的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本发明属于液晶显示技术领域，具体地说，尤其涉及一种AMOLED扫描驱动电路及方法、液晶显示面板及装置。
背景技术
现有AMOLED扫描驱动电路的架构如图1所示，其内部对应的基本功能模块如图2所示，其只能用于需要单个栅极控制信号的AMOLED扫描驱动电路。
当AMOLED扫描驱动电路需要大于或等于2个的栅极控制信号时，现有的扫描驱动补偿电路无法满足输出多个栅极控制信号的要求。
发明内容
为解决以上问题，本发明提供了一种AMOLED扫描驱动电路及方法、液晶显示面板及装置，用以提供多种扫描驱动信号。
根据本发明的一个方面，提供了一种AMOLED扫描驱动电路，包括：
移位寄存单元；
逻辑单元，
其中，在相邻移位寄存单元之间和相邻逻辑单元之间设置有选择器，部分移位寄存单元之间和部分逻辑单元之间通过选择器连通，在选择控制信号控制选择器、时钟信号及启动脉冲信号控制移位寄存单元、逻辑信号控制逻辑单元情况下输出不同的扫描驱动信号。
根据本发明的一个实施例，所述移位寄存单元之间和所述逻辑单元之间通过选择器隔行连接，其中，奇数行移位寄存单元之间和奇数行逻辑单元之间通过对 应的奇数行选择器连接，偶数行移位寄存单元之间和偶数行逻辑单元之间通过对应的偶数行选择器连接。
根据本发明的一个实施例，所述逻辑单元的输出端还依次连接有电平转换单元和数字缓存单元。
根据本发明的一个实施例，所述移位寄存单元之间和所述逻辑单元之间通过选择器隔行连接，其中，
奇数行移位寄存单元之间和奇数行逻辑单元之间通过对应的奇数行选择器连接，偶数行移位寄存单元之间和偶数行逻辑单元之间通过对应的偶数行选择器连接；
各移位寄存单元通过布局在前的移位寄存单元对应行的选择器间隔两行连接，各逻辑单元通过布局在前的逻辑单元对应行的选择器间隔两行连接。
根据本发明的一个实施例，所述逻辑单元的输出端还依次连接有电平转换单元和数字缓存单元。
根据本发明的另一个方面，还提供了一种AMOLED扫描驱动方法，包括：
通过选择控制信号控制相邻移位寄存单元之间和相邻逻辑单元之间设置的、连通部分移位寄存单元和部分逻辑单元的选择器，结合时钟信号及启动脉冲信号控制移位寄存单元、逻辑信号控制逻辑单元，从而输出不同的扫描驱动信号
根据本发明的一个实施例，
所述时钟信号包括第一时钟信号和第二时钟信号，所述启动脉冲信号包括第一启动脉冲信号和第二启动脉冲信号，所述逻辑信号包括第一逻辑信号和第二逻辑信号，
当选择控制信号为第一状态，第一时钟信号、第二时钟信号、第一启动脉冲信号和第一逻辑信号有效，扫描信号按输出行号依序输出；
当选择控制信号为第二状态，第一时钟信号、第二时钟信号、第一启动脉冲信号、第二启动脉冲信号、第一逻辑信号和第二逻辑信号均有效，扫描信号以相邻4个输出行号为一组顺序输出，其中，一组内扫描信号输出顺为N、N+2、N+1和N+3，N为该组内的第一个输出行号。
根据本发明的一个实施例，
所述时钟信号包括第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号和第五时钟信号，所述启动信号包括第一启动脉冲信号、第二启动脉冲信号和第三启动脉冲信号，所述逻辑信号包括第一逻辑信号、第二逻辑信号和第三逻 辑信号，
当选择控制信号为第一状态，第一时钟信号、第二时钟信号、第一启动脉冲信号和第一逻辑信号有效，扫描信号按输出行号依序输出；
选择控制信号为第二状态，第一时钟信号、第二时钟信号、第一启动脉冲信号、第二启动脉冲信号、第一逻辑信号和第二逻辑信号均有效，扫描信号以相邻4个输出行号为一组顺序输出，其中，一组内扫描信号输出顺为N、N+2、N+1和N+3，N为该组内的第一个输出行号；
选择控制信号为第三状态，第三时钟信号、第四时钟信号和第五时钟信号、第一启动脉冲信号、第二启动脉冲信号、第三启动脉冲信号、第一逻辑信号、第二逻辑信号和第三逻辑信号均有效，扫描信号以相邻6个输出行号为一组顺序输出，其中，一组内扫描信号输出顺为N、N+3、N+1、N+4、N+2和N+5，N为该组内的第一个输出行号。
根据本发明的再一个方面，还提供了一种液晶显示面板，包括以上所述的AMOLED扫描驱动电路和采用以上所述的AMOLED扫描驱动方法。
根据本发明的又一个方面，还提供了一种液晶显示装置，包括以上所述的液晶显示面板。
本发明的有益效果：
在本发明中，通过选择控制信号、时钟信号及启动脉冲信号、逻辑信号的不同组合，可以对应选择输出不同波形的扫描驱动信号，使得扫描驱动电路的输出波形可以通过外部控制信号选择，方便做双驱设计。
本发明的其他优点、目标，和特征在某种程度上将在随后的说明书中进行阐述，并且在某种程度上，基于对下文的考察研究对本领域技术人员而言将是显而易见的，或者可以从本发明的实践中得到教导。本发明的目标和其他优点可以通过下面的说明书，权利要求书，以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本申请的技术方案或现有技术的进一步理解，并且构成说明书的一部分。其中，表达本申请实施例的附图与本申请的实施例一起用于解释本申请的技术方案，但并不构成对本申请技术方案的限制。
图1是现有技术中一种AMOLED扫描驱动电路架构图；
图2是对应图1的内部基本功能模块示意图；
图3是根据本发明的一个实施例的内部基本功能模块示意图；
图4是现有技术中一种4T1C内部补偿电路示意图；
图5是对应图4的时序图；
图6是对应图3的各信号时序图；
图7是根据本发明的另一个实施例的内部基本功能模块示意图。
具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成相应技术效果的实现过程能充分理解并据以实施。本申请实施例以及实施例中的各个特征，在不相冲突前提下可以相互结合，所形成的技术方案均在本发明的保护范围之内。
为解决AMOLED扫描驱动电路需要大于或等于2个栅极控制信号，而现有扫描驱动电路无法满足要求的问题，本发明提供了一种AMOLED扫描驱动电路，如图3和图7所示为根据本发明的实施例的AMOLED扫描驱动电路内部基本功能模块示意图，以下参考图3和图7来对本发明进行详细说明。
该AMOLED扫描驱动电路包括移位寄存单元和逻辑单元，其中，在相邻移位寄存单元之间和相邻逻辑单元之间设置有选择器，部分移位寄存单元之间和部分逻辑单元之间通过选择器连通，在选择控制信号控制选择器、时钟信号及启动脉冲信号控制移位寄存单元、逻辑信号控制逻辑单元情况下输出不同的扫描驱动信号。
在本发明中，通过选择控制信号、时钟信号及启动脉冲信号、逻辑信号的不同组合，可以对应选择输出不同波形的扫描驱动信号，使得扫描驱动电路的输出波形可以通过外部控制信号选择，方便做双驱设计。
如图3所示为根据本发明的一个实施例的一种AMOLED扫描驱动电路架构图。如图3所示，多个移位寄存单元S/R并行排列，逻辑单元Log与移位寄存单元S/R一一对应连接，在相邻移位寄存单元之间和相邻逻辑单元之间设置有选择器，选择器由选择控制信号Sel控制。
为实现扫描驱动信号的输出，在每个逻辑单元的输出端还依次连接有电平转换单元L/S和数字缓存单元D/B。电平转换单元在开启电压Vg,on控制下进行电平转换，在关闭电压Vg,off控制下停止电平转换；数字缓存单元在开启电压Vg,on 控制下缓存并输出扫描驱动信号，在关闭电压Vg,off控制下停止缓存和输出扫描驱动信号。
如图3所示，移位寄存单元之间和逻辑单元之间通过选择器隔行连接，其中，奇数行移位寄存单元和奇数行逻辑单元通过对应的奇数行选择器连接，偶数行移位寄存单元和偶数行逻辑单元通过对应的偶数行选择器连接。其中，此处的时钟信号包括第一时钟信号CPV1和第二时钟信号CPV2，启动脉冲信号包括第一启动脉冲信号STV1和第二启动脉冲信号STV2，逻辑信号包括第一逻辑信号ENA和第二逻辑信号ENB。由第一时钟信号和第二时钟信号、第一启动脉冲信号和第二启动脉冲信号、第一逻辑信号和第二逻辑信号的不同组合，可以输出不同波形的扫描驱动信号。
图3所示的AMOLED扫描驱动电路可以输出两种波形的扫描信号，具体的，第一种情况：当选择控制信号Sel为第一状态，第一时钟信号、第二时钟信号、第一启动脉冲信号和第一逻辑信号有效时，扫描信号按输出行号依序输出，即可以控制该扫描驱动电路以G1,G2,G3,G4,G5,G6…的顺序输出扫描信号。
此时，相邻移位寄存单元之间的选择器连通相邻移位寄存单元，相邻逻辑单元之间的选择器连通相邻逻辑单元。各移位寄存单元在第一时钟信号、第二时钟信号和第一启动脉冲信号作用下、逻辑单元在第一逻辑信号作用下控制该扫描驱动电路以G1,G2,G3,G4,G5,G6…的顺序输出扫描信号。
第二种情况：选择控制信号Sel为第二状态时，第一时钟信号、第二时钟信号、第一启动脉冲信号、第二启动脉冲信号、第一逻辑信号和第二逻辑信号均有效，扫描信号以相邻4个输出行号为一组顺序输出，其中，一组内扫描信号输出顺为N、N+2、N+1和N+3，N为该组内的第一个输出行号，即可以控制该扫描驱动电路以G1,G3,G2,G4,G5,G7,G6,G8…的顺序输出扫描信号。
由于选择器的作用，奇数行移位寄存单元通过应的奇数行选择器连通，偶数行移位寄存单元通过对应的偶数行选择器连通，而相邻奇数行移位寄存单元和偶数行移位寄存单元不连通。奇数行移位寄存单元在第一时钟信号和第一启动脉冲信号作用下，偶数行移位寄存单元在第二时钟信号和第二启动脉冲信号作用下，奇数行逻辑单元在第一逻辑信号作用下，偶数行逻辑单元在第二逻辑信号作用下，可以控制该扫描驱动电路以G1,G3,G2,G4,G5,G7,G6,G8…的顺序输出扫描信号。
具体的，例如选择控制信号Sel为第二状态时，第一时钟信号和第一启动脉冲信号开启，S\R1打开输出扫描信号G1，同时S\R1输出类似的启动信号并通过选择器输出给S\R3，S\R3打开输出扫描信号G3。此时，结合S\R3输出类似启动信号的延时及关闭第一时钟信号，打开第二时钟信号和第二启动脉冲信号，保持选择控制信号Sel为第二状态，S\R2打开输出扫描信号G2，同时S\R2输出类似的启动信号通过选择器输出给S\R4，S\R4打开输出扫描信号G4。接下来是打开第一时钟信号和第一启动脉冲信号，保持选择控制信号Sel为第二状态，则输出扫描信号G5,G7，依次类推。
当然，改变移位寄存单元和逻辑单元通过选择器的连接顺序，以及调整对应的时钟信号、启动脉冲信号和逻辑信号的条件下，可以以任意顺序输出扫描信号。对于扫描信号的输出波形，可以通过时序控制电路TCON控制第一时钟信号和第二时钟信号、第一启动脉冲信号和第二启动脉冲信号、第一逻辑信号和第二逻辑信号的波形，来满足补偿电路所需要的扫描控制信号。
如图4所示为现有一4T1C内部补偿电路原理示意图，图3所示的扫描驱动信号通过图4的DATA端输入，在控制信号SEL1、SEL2以及输入信号IN和驱动信号Vdd作用下，输出给有机发光二极管OLED。控制信号SEL1、SEL2及DATA端输入数据时序如图5所示，其对应产生DATA端输入数据的图3的各控制信号及输出信号的时序如图6所示。
如图7所示为根据本发明的另一个实施例的一种AMOLED扫描驱动电路内部基本功能模块示意图。如图7所示，多个移位寄存单元S/R并行排列的，逻辑单元与移位寄存单元一一对应连接，在相邻移位寄存单元之间和相邻逻辑单元之间设置有选择器，部分移位寄存单元之间和部分逻辑单元之间通过选择器连通，选择器由选择控制信号Sel控制。
为实现扫描驱动信号的输出，对应每个逻辑单元的输出端还依次连接有电平转换单元L/S和数字缓存单元D/B，这两种单元在开启电压Vg,on控制下输出扫描驱动信号，在关闭电压Vg,off控制下停止输出扫描驱动信号。
如图7所示，移位寄存单元之间和逻辑单元之间通过选择器隔行连接，其中，奇数行移位寄存单元之间和奇数行逻辑单元之间通过对应的奇数行选择器连接，偶数行移位寄存单元之间和偶数行逻辑单元之间通过对应的偶数行选择器连接。并且，各移位寄存单元通过布局在上的移位寄存单元对应行的选择器间隔两行连接，各逻辑单元通过布局在上的逻辑单元对应行的选择器间隔两行 连接。即第一行移位寄存单元S/R1通过第一行对应的选择器与第四行移位寄存单元S/R4连接，第二行逻辑单元通过第二行对应的选择器与第五行逻辑单元连接。
如图7所示，时钟信号包括第一时钟信号CPV1、第二时钟信号CPV2、第三时钟信号CPV3、第四时钟信号CPV4和第五时钟信号CPV5共5个时钟信号；启动信号包括第一启动脉冲信号STV1、第二启动脉冲信号STV2和第三启动脉冲信号STV3；逻辑信号包括第一逻辑信号ENA、第二逻辑信号ENB和第三逻辑信号ENC。
图7所示的AMOLED扫描驱动电路可以输出三种波形的扫描信号，具体的，第一种情况：选择控制信号Sel为第一状态时(例如Sel＝00)，第一时钟信号、第二时钟信号、第一启动脉冲信号和第一逻辑信号有效，扫描信号按输出行号依序输出，即可以控制该扫描驱动电路以G1,G2,G3,G4,G5,G6…的顺序输出。此时，相邻移位寄存单元之间的选择器连通相邻移位寄存单元，相邻逻辑单元之间的选择器连通相邻逻辑单元。各移位寄存单元在第一时钟信号、第二时钟信号和第一启动脉冲信号作用下、逻辑单元在第一逻辑信号作用下控制该扫描驱动电路以G1,G2,G3,G4,G5,G6…的顺序输出扫描信号。
第二种情况：选择控制信号Sel为第二状态时(例如Sel＝01)，第一时钟信号、第二时钟信号、第一启动脉冲信号、第二启动脉冲信号、第一逻辑信号和第二逻辑信号均有效，扫描信号以相邻4个输出行号分为一组顺序输出，其中，一组内扫描信号输出顺为N、N+2、N+1和N+3，N为该组内的第一个输出行号，即可以控制该扫描驱动电路以G1,G3,G2,G4,G5,G7…的顺序输出扫描信号。此时，由于选择器的作用，奇数行移位寄存单元通过应的奇数行选择器连通，偶数行移位寄存单元通过对应的偶数行选择器连通，而相邻奇数行移位寄存单元和偶数行移位寄存单元不连通。奇数行移位寄存单元在第一时钟信号和第一启动脉冲信号作用下，偶数行移位寄存单元在第二时钟信号和第二启动脉冲信号作用下，奇数行逻辑单元在第一逻辑信号作用下，偶数行逻辑单元在第二逻辑信号作用下，可以控制该扫描驱动电路以G1,G3,G2,G4,G5,G7…的顺序输出扫描信号，具体信号配合过程与图3相同，此处不再详述。
第三种情况：选择控制信号Sel为第三状态时(例如Sel＝10)，第三时钟信号、第四时钟信号和第五时钟信号、第一启动脉冲信号、第二启动脉冲信号、第三启动脉冲信号、第一逻辑信号、第二逻辑信号和第三逻辑信号均有效 下，扫描信号以相邻6个输出行号分为一组顺序输出，其中，一组内扫描信号输出顺为N、N+3、N+1、N+4、N+2和N+5，N为该组内的第一个输出行号，即可以控制该扫描驱动电路以G1,G4,G2,G5,G3,G6…的顺序输出扫描信号。
具体的，选择控制信号Sel为第三状态时，第三时钟信号、第一启动脉冲信号和第一逻辑信号共同作用时，G1,G4输出信号；第四时钟信号、第二启动脉冲信号和第二逻辑信号共同作用时，G2,G5输出信号；第五时钟信号、第三启动脉冲信号和第三逻辑信号共同作用时，G3,G6输出信号，依次类推。这样，就可以以G1,G4,G2,G5,G3,G6…的顺序输出扫描信号
当然，改变移位寄存单元和逻辑单元通过选择器的连接顺序，以及调整对应的时钟信号、启动脉冲信号和逻辑信号的条件下，可以以任意顺序输出扫描信号。对于扫描信号的输出波形，可以通过时序控制电路TCON控制各信号来满足补偿电路所需要的扫描控制信号。
根据本发明的另一个方面，还提供了一种AMOLED扫描驱动方法，包括：通过选择控制信号控制相邻移位寄存单元之间和相邻逻辑单元之间设置的、连通部分移位寄存单元之间和部分逻辑单元之间的选择器，结合时钟信号及启动脉冲信号控制移位寄存单元、逻辑信号控制逻辑单元，以输出不同的扫描驱动信号
进一步地，对应图3的AMOLED扫描驱动电路，时钟信号包括第一时钟信号和第二时钟信号，启动脉冲信号包括第一启动脉冲信号和第二启动脉冲信号，逻辑信号包括第一逻辑信号和第二逻辑信号，
当选择控制信号为第一状态，第一时钟信号、第二时钟信号、第一启动脉冲信号和第一逻辑信号有效时，扫描信号按输出行号依序输出，即可以控制该扫描驱动电路以G1,G2,G3,G4,G5,G6,G7,G8…顺序输出扫描信号；
当选择控制信号为第二状态，第一时钟信号、第二时钟信号、第一启动脉冲信号、第二启动脉冲信号、第一逻辑信号和第二逻辑信号均有效，扫描信号以相邻4个输出行号分为一组顺序输出，其中，一组内扫描信号输出顺为N、N+2、N+1和N+3，N为该组内的第一个输出行号，即可以G1,G3,G2,G4,G5,G7,G6,G8…顺序输出扫描信号。
对应图7的AMOLED扫描驱动电路，时钟信号包括第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号和第五时钟信号，启动信号包括第一启动脉冲信号、第二启动脉冲信号和第三启动脉冲信号，逻辑信号包括第一逻辑信号、第二逻辑信号和第三逻辑信号。
当选择控制信号为第一状态时，第一时钟信号、第二时钟信号、第一启动脉冲信号和第一逻辑信号有效，扫描信号按输出行号依序输出，即可以以G1,G2,G3,G4,G5,G6…的顺序输出扫描信号。
选择控制信号为第二状态时，第一时钟信号、第二时钟信号、第一启动脉冲信号、第二启动脉冲信号、第一逻辑信号和第二逻辑信号均有效，扫描信号以相邻4个输出行号分为一组顺序输出，其中，一组内扫描信号输出顺为N、N+2、N+1和N+3，N为该组内的第一个输出行号，即以G1,G3,G2,G4,G5,G7…的顺序输出扫描信号。
选择控制信号为第三状态时，第三时钟信号、第四时钟信号和第五时钟信号、第一启动脉冲信号、第二启动脉冲信号、第三启动脉冲信号、第一逻辑信号、第二逻辑信号和第三逻辑信号均有效，扫描信号以相邻6个输出行号分为一组顺序输出，其中，一组内扫描信号输出顺为N、N+3、N+1、N+4、N+2和N+5，N为该组内的第一个输出行号，N为该组内的第一个输出行号,即以G1,G4,G2,G5,G3,G6…的顺序输出扫描信号。
根据本发明的另一个方面，还提供了一种液晶显示面板，包括以上所述的AMOLED扫描驱动电路和采用以上所述的AMOLED扫描驱动方法。
根据本发明的另一个方面，还提供了一种液晶显示装置，包括以上所述的液晶显示面板。
虽然本发明所揭露的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属技术领域内的技术人员，在不脱离本发明所揭露的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (20)

  1. 一种AMOLED扫描驱动电路，包括：
    移位寄存单元；
    逻辑单元，
    其中，在相邻移位寄存单元之间和相邻逻辑单元之间设置有选择器，部分移位寄存单元之间和部分逻辑单元之间通过选择器连通，在选择控制信号控制选择器、时钟信号及启动脉冲信号控制移位寄存单元、逻辑信号控制逻辑单元情况下输出不同的扫描驱动信号。
  2. 根据权利要求1所述的电路，其中，所述移位寄存单元之间和所述逻辑单元之间通过选择器隔行连接，其中，奇数行移位寄存单元之间和奇数行逻辑单元之间通过对应的奇数行选择器连接，偶数行移位寄存单元之间和偶数行逻辑单元之间通过对应的偶数行选择器连接。
  3. 根据权利要求2所述的电路，其中，所述逻辑单元的输出端还依次连接有电平转换单元和数字缓存单元。
  4. 根据权利要求1所述的电路，其中，所述移位寄存单元之间和所述逻辑单元之间通过选择器隔行连接，
    奇数行移位寄存单元之间和奇数行逻辑单元之间通过对应的奇数行选择器连接，偶数行移位寄存单元之间和偶数行逻辑单元之间通过对应的偶数行选择器连接；
    各移位寄存单元通过布局在前的移位寄存单元对应行的选择器间隔两行连接，各逻辑单元通过布局在前的逻辑单元对应行的选择器间隔两行连接。
  5. 根据权利要求4所述的电路，其中，所述逻辑单元的输出端还依次连接有电平转换单元和数字缓存单元。
  6. 一种AMOLED扫描驱动方法，该方法用于驱动AMOLED扫描驱动电路，所述电路包括：
    移位寄存单元；
    逻辑单元，
    其中，在相邻移位寄存单元之间和相邻逻辑单元之间设置有选择器，部分移位寄存单元之间和部分逻辑单元之间通过选择器连通，在选择控制信号控制选择器、时钟信号及启动脉冲信号控制移位寄存单元、逻辑信号控制逻辑单元情况下输出不同的扫描驱动信号，
    所述方法包括：
    通过选择控制信号控制相邻移位寄存单元之间和相邻逻辑单元之间设置的、连通部分移位寄存单元和部分逻辑单元的选择器，结合时钟信号及启动脉冲信号控制移位寄存单元、逻辑信号控制逻辑单元，从而输出不同的扫描驱动信号。
  7. 根据权利要求6所述的方法，该方法用于驱动AMOLED扫描驱动电路，所述电路包括：
    所述移位寄存单元之间和所述逻辑单元之间通过选择器隔行连接，其中，奇数行移位寄存单元之间和奇数行逻辑单元之间通过对应的奇数行选择器连接，偶数行移位寄存单元之间和偶数行逻辑单元之间通过对应的偶数行选择器连接，
    所述方法包括：
    所述时钟信号包括第一时钟信号和第二时钟信号，所述启动脉冲信号包括第一启动脉冲信号和第二启动脉冲信号，所述逻辑信号包括第一逻辑信号和第二逻辑信号，
    当选择控制信号为第一状态，第一时钟信号、第二时钟信号、第一启动脉冲信号和第一逻辑信号有效，扫描信号按输出行号依序输出；
    当选择控制信号为第二状态，第一时钟信号、第二时钟信号、第一启动脉冲信号、第二启动脉冲信号、第一逻辑信号和第二逻辑信号均有效，扫描信号以相邻4个输出行号为一组顺序输出，其中，一组内扫描信号输出顺为N、N+2、N+1和N+3，N为该组内的第一个输出行号。
  8. 根据权利要求6所述的方法，该方法用于驱动AMOLED扫描驱动电路，所述电路包括：
    所述移位寄存单元之间和所述逻辑单元之间通过选择器隔行连接，
    奇数行移位寄存单元之间和奇数行逻辑单元之间通过对应的奇数行选择器连接，偶数行移位寄存单元之间和偶数行逻辑单元之间通过对应的偶数行选择器连接；
    各移位寄存单元通过布局在前的移位寄存单元对应行的选择器间隔两行连接，各逻辑单元通过布局在前的逻辑单元对应行的选择器间隔两行连接，
    所述方法包括：
    所述时钟信号包括第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号和第五时钟信号，所述启动信号包括第一启动脉冲信号、第二启动脉冲信号和第三启动脉冲信号，所述逻辑信号包括第一逻辑信号、第二逻辑信号和 第三逻辑信号，
    当选择控制信号为第一状态，第一时钟信号、第二时钟信号、第一启动脉冲信号和第一逻辑信号有效，扫描信号按输出行号依序输出；
    选择控制信号为第二状态，第一时钟信号、第二时钟信号、第一启动脉冲信号、第二启动脉冲信号、第一逻辑信号和第二逻辑信号均有效，扫描信号以相邻4个输出行号为一组顺序输出，其中，一组内扫描信号输出顺为N、N+2、N+1和N+3，N为该组内的第一个输出行号；
    选择控制信号为第三状态，第三时钟信号、第四时钟信号和第五时钟信号、第一启动脉冲信号、第二启动脉冲信号、第三启动脉冲信号、第一逻辑信号、第二逻辑信号和第三逻辑信号均有效，扫描信号以相邻6个输出行号为一组顺序输出，其中，一组内扫描信号输出顺为N、N+3、N+1、N+4、N+2和N+5，N为该组内的第一个输出行号。
  9. 一种液晶显示面板，包括AMOLED扫描驱动电路，所述电路包括：
    移位寄存单元；
    逻辑单元，
    其中，在相邻移位寄存单元之间和相邻逻辑单元之间设置有选择器，部分移位寄存单元之间和部分逻辑单元之间通过选择器连通，在选择控制信号控制选择器、时钟信号及启动脉冲信号控制移位寄存单元、逻辑信号控制逻辑单元情况下输出不同的扫描驱动信号。
  10. 根据权利要求9所述的面板，其中，
    所述移位寄存单元之间和所述逻辑单元之间通过选择器隔行连接，其中，奇数行移位寄存单元之间和奇数行逻辑单元之间通过对应的奇数行选择器连接，偶数行移位寄存单元之间和偶数行逻辑单元之间通过对应的偶数行选择器连接。
  11. 根据权利要求9所述的面板，其中，
    所述移位寄存单元之间和所述逻辑单元之间通过选择器隔行连接，
    奇数行移位寄存单元之间和奇数行逻辑单元之间通过对应的奇数行选择器连接，偶数行移位寄存单元之间和偶数行逻辑单元之间通过对应的偶数行选择器连接；
    各移位寄存单元通过布局在前的移位寄存单元对应行的选择器间隔两行连接，各逻辑单元通过布局在前的逻辑单元对应行的选择器间隔两行连接。
  12. 根据权利要求9所述的面板，其中，
    通过选择控制信号控制相邻移位寄存单元之间和相邻逻辑单元之间设置的、连通部分移位寄存单元和部分逻辑单元的选择器，结合时钟信号及启动脉冲信号控制移位寄存单元、逻辑信号控制逻辑单元，从而输出不同的扫描驱动信号。
  13. 根据权利要求12所述的面板，其中，
    所述时钟信号包括第一时钟信号和第二时钟信号，所述启动脉冲信号包括第一启动脉冲信号和第二启动脉冲信号，所述逻辑信号包括第一逻辑信号和第二逻辑信号，
    当选择控制信号为第一状态，第一时钟信号、第二时钟信号、第一启动脉冲信号和第一逻辑信号有效，扫描信号按输出行号依序输出；
    当选择控制信号为第二状态，第一时钟信号、第二时钟信号、第一启动脉冲信号、第二启动脉冲信号、第一逻辑信号和第二逻辑信号均有效，扫描信号以相邻4个输出行号为一组顺序输出，其中，一组内扫描信号输出顺为N、N+2、N+1和N+3，N为该组内的第一个输出行号。
  14. 根据权利要求12所述的面板，其中，
    所述时钟信号包括第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号和第五时钟信号，所述启动信号包括第一启动脉冲信号、第二启动脉冲信号和第三启动脉冲信号，所述逻辑信号包括第一逻辑信号、第二逻辑信号和第三逻辑信号，
    当选择控制信号为第一状态，第一时钟信号、第二时钟信号、第一启动脉冲信号和第一逻辑信号有效，扫描信号按输出行号依序输出；
    选择控制信号为第二状态，第一时钟信号、第二时钟信号、第一启动脉冲信号、第二启动脉冲信号、第一逻辑信号和第二逻辑信号均有效，扫描信号以相邻4个输出行号为一组顺序输出，其中，一组内扫描信号输出顺为N、N+2、N+1和N+3，N为该组内的第一个输出行号；
    选择控制信号为第三状态，第三时钟信号、第四时钟信号和第五时钟信号、第一启动脉冲信号、第二启动脉冲信号、第三启动脉冲信号、第一逻辑信号、第二逻辑信号和第三逻辑信号均有效，扫描信号以相邻6个输出行号为一组顺序输出，其中，一组内扫描信号输出顺为N、N+3、N+1、N+4、N+2和N+5，N为该组内的第一个输出行号。
  15. 一种液晶显示装置，包括液晶显示面板，所述液晶显示面板包括AMOLED扫描驱动电路，所述电路包括：
    移位寄存单元；
    逻辑单元，
    其中，在相邻移位寄存单元之间和相邻逻辑单元之间设置有选择器，部分移位寄存单元之间和部分逻辑单元之间通过选择器连通，在选择控制信号控制选择器、时钟信号及启动脉冲信号控制移位寄存单元、逻辑信号控制逻辑单元情况下输出不同的扫描驱动信号。
  16. 根据权利要求15所述的装置，其中，
    所述移位寄存单元之间和所述逻辑单元之间通过选择器隔行连接，其中，奇数行移位寄存单元之间和奇数行逻辑单元之间通过对应的奇数行选择器连接，偶数行移位寄存单元之间和偶数行逻辑单元之间通过对应的偶数行选择器连接。
  17. 根据权利要求15所述的装置，其中，
    所述移位寄存单元之间和所述逻辑单元之间通过选择器隔行连接，
    奇数行移位寄存单元之间和奇数行逻辑单元之间通过对应的奇数行选择器连接，偶数行移位寄存单元之间和偶数行逻辑单元之间通过对应的偶数行选择器连接；
    各移位寄存单元通过布局在前的移位寄存单元对应行的选择器间隔两行连接，各逻辑单元通过布局在前的逻辑单元对应行的选择器间隔两行连接。
  18. 根据权利要求15所述的装置，其中，
    通过选择控制信号控制相邻移位寄存单元之间和相邻逻辑单元之间设置的、连通部分移位寄存单元和部分逻辑单元的选择器，结合时钟信号及启动脉冲信号控制移位寄存单元、逻辑信号控制逻辑单元，从而输出不同的扫描驱动信号。
  19. 根据权利要求18所述的装置，其中，
    所述时钟信号包括第一时钟信号和第二时钟信号，所述启动脉冲信号包括第一启动脉冲信号和第二启动脉冲信号，所述逻辑信号包括第一逻辑信号和第二逻辑信号，
    当选择控制信号为第一状态，第一时钟信号、第二时钟信号、第一启动脉冲信号和第一逻辑信号有效，扫描信号按输出行号依序输出；
    当选择控制信号为第二状态，第一时钟信号、第二时钟信号、第一启动脉冲信号、第二启动脉冲信号、第一逻辑信号和第二逻辑信号均有效，扫描信号以相邻4个输出行号为一组顺序输出，其中，一组内扫描信号输出顺为N、N+2、N+1和N+3，N为该组内的第一个输出行号。
  20. 根据权利要求18所述的装置，其中，
    所述时钟信号包括第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号和第五时钟信号，所述启动信号包括第一启动脉冲信号、第二启动脉冲信号和第三启动脉冲信号，所述逻辑信号包括第一逻辑信号、第二逻辑信号和第三逻辑信号，
    当选择控制信号为第一状态，第一时钟信号、第二时钟信号、第一启动脉冲信号和第一逻辑信号有效，扫描信号按输出行号依序输出；
    选择控制信号为第二状态，第一时钟信号、第二时钟信号、第一启动脉冲信号、第二启动脉冲信号、第一逻辑信号和第二逻辑信号均有效，扫描信号以相邻4个输出行号为一组顺序输出，其中，一组内扫描信号输出顺为N、N+2、N+1和N+3，N为该组内的第一个输出行号；
    选择控制信号为第三状态，第三时钟信号、第四时钟信号和第五时钟信号、第一启动脉冲信号、第二启动脉冲信号、第三启动脉冲信号、第一逻辑信号、第二逻辑信号和第三逻辑信号均有效，扫描信号以相邻6个输出行号为一组顺序输出，其中，一组内扫描信号输出顺为N、N+3、N+1、N+4、N+2和N+5，N为该组内的第一个输出行号。
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