WO2018032684A1 - Chuck, reaction chamber and semiconductor processing equipment - Google Patents

Chuck, reaction chamber and semiconductor processing equipment Download PDF

Info

Publication number
WO2018032684A1
WO2018032684A1 PCT/CN2016/112387 CN2016112387W WO2018032684A1 WO 2018032684 A1 WO2018032684 A1 WO 2018032684A1 CN 2016112387 W CN2016112387 W CN 2016112387W WO 2018032684 A1 WO2018032684 A1 WO 2018032684A1
Authority
WO
WIPO (PCT)
Prior art keywords
wafer
bearing surface
chuck
gas
roughness
Prior art date
Application number
PCT/CN2016/112387
Other languages
French (fr)
Chinese (zh)
Inventor
张虎威
Original Assignee
北京北方微电子基地设备工艺研究中心有限责任公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 北京北方微电子基地设备工艺研究中心有限责任公司 filed Critical 北京北方微电子基地设备工艺研究中心有限责任公司
Publication of WO2018032684A1 publication Critical patent/WO2018032684A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/02—Details
    • H01J37/20—Means for supporting or positioning the objects or the material; Means for adjusting diaphragms or lenses associated with the support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67207—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67207—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • H01L21/67213—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process comprising at least one ion or electron beam chamber
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping

Definitions

  • the present invention relates to the field of semiconductor manufacturing, and in particular to a chuck, a reaction chamber, and a semiconductor processing apparatus.
  • Electrostatic Chuck is widely used in the manufacturing process of integrated circuits, especially plasma etching, physical vapor deposition (PVD), chemical vapor deposition (Chemical Vapor Deposition).
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • CVD requires ESC to fix the wafer in the reaction chamber, provide DC bias to the wafer, and rapidly cool the surface of the wafer so that the high temperature generated by the wafer surface during the process can be effectively controlled.
  • an electrostatic chuck includes an insulating layer 1 and an aluminum base 4 for supporting the insulating layer 1.
  • the upper surface of the insulating layer 1 is made of a ceramic material for carrying and insulating the wafer 2.
  • a DC electrode (not shown) is embedded in the insulating layer 1 to electrically electrostatically attract the insulating layer 1 and the wafer 2.
  • a cooling passage 3 is provided in the insulating layer 1 for conveying a cooling gas between the insulating layer 1 and the wafer 2 to cool the wafer 2.
  • a cooling water passage 41 is provided inside the aluminum base 4, and the insulating layer 1 is cooled by passing cooling water into the cooling water passage 41.
  • FIG. 2 is a plan view of the conventional electrostatic chuck shown in FIG. 1.
  • an annular boss 10 and a plurality of bumps 11 are disposed on the upper surface of the insulating layer 1.
  • the annular boss 10 is circumferentially disposed at the edge of the insulating layer 1 for sealing the edge of the wafer 2.
  • a plurality of bumps 11 are located inside the annular boss 10 and are evenly distributed, and the upper surface of the bump 11 and the upper surface of the annular boss 10 are in contact with the wafer 2 for supporting the wafer 2 in common.
  • the heat transfer between the insulating layer 1 and the wafer 2 mainly depends on the plurality of bumps 11 contacting the lower surface of the wafer 2, and the cooling gas between the insulating layer 1 and the wafer 2, but due to the bumps 11 and the wafer 2
  • the lower surface is a point contact, and the contact area is limited, which cannot meet the requirement of rapid cooling of the wafer 2.
  • the surface temperature of the wafer 2 rises rapidly, so that the wafer 2 is damaged due to high temperature.
  • the present invention is directed to at least one of the technical problems existing in the prior art, and proposes a chuck, a reaction chamber, and a semiconductor processing apparatus.
  • the chuck, the reaction chamber and the semiconductor processing apparatus provided by the invention can improve the efficiency of heat conduction of the wafer to the chuck, thereby avoiding wafer damage caused by excessive temperature rise of the wafer surface.
  • a chuck comprising an insulating layer and a base body, the insulating layer comprising a first bearing surface and a second bearing surface surrounding the outer circumference of the first bearing surface, the first bearing surface a central region for carrying a wafer, the second bearing surface for carrying an edge region of the wafer, wherein the first bearing surface has a first roughness, and the first roughness can be guaranteed to be located at the first Under the premise that the gas between the bearing surface and the wafer is evenly distributed, the contact area between the wafer and the first bearing surface is increased.
  • the first roughness is 0.6-0.8 um.
  • the second bearing surface has a second roughness, and the second roughness enables the second bearing surface to be in close contact with the wafer to seal the gas between the first bearing surface and the wafer.
  • the second roughness is less than or equal to 0.4 um.
  • the first roughness is greater than the second roughness.
  • At least two gas passages are disposed under the insulating layer for introducing gas between the first bearing surface and the wafer.
  • each of the gas passages is an annular passage, and at least two of the annular passages are concentric rings.
  • the annular channel comprises: a circular annular channel, an elliptical annular channel and/or an irregular annular channel.
  • the annular passage of the outermost ring is located at an edge of the first bearing surface.
  • the annular passage is centered on a center of the first bearing surface.
  • the present invention also provides a reaction chamber comprising the above-described chuck provided by the present invention.
  • the present invention also provides an inverse semiconductor processing apparatus including the above-described reaction chamber provided by the present invention.
  • the chuck provided by the present invention has an insulating layer including a first bearing surface and a second bearing surface surrounding the outer circumference of the first bearing surface, the first bearing surface and the second bearing surface for respectively carrying the central area and the edge area of the wafer .
  • the first bearing surface has a first roughness, which can increase the contact area between the wafer and the bearing surface under the premise of ensuring uniform distribution of the gas between the first bearing surface and the wafer, thereby Improve the efficiency of heat transfer from the wafer to the insulating layer of the chuck, improve the cooling effect on the wafer, thereby not only improving the temperature-controlled cooling process of the conventional wafer, but also solving the new wafer (such as system integrated wafer SOG) in the high temperature process.
  • the problem of rapid rise in wafer temperature prevents high temperature damage of the wafer.
  • the reaction chamber provided by the invention can not only improve the process effect of temperature control and cooling of the conventional wafer by using the above-mentioned chuck provided by the invention, but also solve the problem that the wafer temperature rises rapidly when the new wafer is subjected to a high temperature process. To avoid high temperature damage to the wafer.
  • the semiconductor processing apparatus provided by the invention can not only improve the process effect of the temperature control cooling of the conventional wafer by using the reaction chamber provided by the invention, but also can avoid the temperature rise of the wafer surface too fast when the new wafer is subjected to a high temperature process. Causes high temperature damage to the wafer.
  • Figure 1 is a partial cross-sectional view of a conventional electrostatic chuck
  • Figure 2 is a plan view of the conventional electrostatic chuck shown in Figure 1;
  • FIG. 3 is a cross-sectional view of a chuck according to an embodiment of the present invention.
  • Figure 4 is an enlarged view of the area I in Figure 3;
  • Fig. 5 is a schematic view showing the structure and positional relationship of a gas passage in an embodiment of the present invention.
  • the reference numerals are: insulating layer 1, wafer 2, cooling channel 3, aluminum base 4, cooling water channel 41, annular boss 10, bump 11, insulating layer 5, substrate 7, gas passage 8, gas distribution plate 9.
  • FIG. 3 is a cross-sectional view of a chuck according to an embodiment of the present invention.
  • Figure 4 is an enlarged view of the area I in Figure 3.
  • the chuck includes an insulating layer 5 and a base body 7, wherein the insulating layer 5 includes a first bearing surface 51 and a second bearing surface 52 surrounding the outer circumference of the first bearing surface 51, A carrier surface 51 is used to carry the central area of the wafer 6, and a second carrier surface 52 is used to carry the edge regions of the wafer 6.
  • the first bearing surface 51 has a first roughness, which can increase the wafer 6 and the first bearing surface 51 under the premise that the gas between the first bearing surface 51 and the wafer 6 is evenly distributed. The area of contact between.
  • the gas is delivered between the first bearing surface 51 and the wafer 6 to increase heat transfer therebetween.
  • the gas may be an inert gas such as helium.
  • the first roughness can save the first bearing surface 51 and the wafer 6.
  • the gap enables the gas to form a convection in the gap, thereby achieving uniform distribution of the gas, thereby improving the heat dissipation efficiency of the wafer 6 to the gas.
  • the first bearing surface 51 and the lower surface of the wafer 6 still belong to the surface contact, which ensures the contact area between the two, thereby improving the efficiency of heat conduction of the wafer 6 to the chuck and improving the cooling effect on the wafer 6.
  • the new wafer (such as the system integrated wafer SOG) can be prevented from being damaged by the high temperature of the wafer 6 due to the excessive temperature rise of the surface of the wafer 6 during the high temperature process. .
  • the first roughness ranges from 0.6 to 0.8 um. Within this range of values, the contact area between the first carrying surface 51 and the wafer 6 is maximized, so that the efficiency of heat transfer of the wafer 6 to the first carrying surface 51 can be improved.
  • the roughness is the roughness of the corresponding surface, the rougher the surface, the greater the roughness; the smoother the surface, the greater the roughness.
  • the second bearing surface 52 has a second roughness, which enables the second bearing surface 52 to be in close contact with the wafer 6, thereby sealing the gas between the first bearing surface 51 and the wafer 6, thereby avoiding Gas leaks.
  • the second roughness is less than or equal to 0.4 um. Within this range of values, the sealing effect on the gas is better.
  • the first roughness is greater than the second roughness.
  • the first bearing surface is more favorable for heat conduction of the wafer to the first bearing surface, and the second bearing surface can be in closer contact with the wafer during electrostatic adsorption, sealing the first The gas between the bearing surface and the wafer.
  • a gas passage may be disposed under the insulating layer.
  • the chuck provided in this embodiment is provided with a gas passage 8 , specifically a first gas passage 81 and a second gas passage 82 , between the first bearing surface 51 and the wafer 6 below the insulating layer 5 .
  • Pass the above gas the first gas passage 81 and the second gas passage 82 are both annular passages and are concentric rings.
  • the annular passage of the outermost ring that is, the second gas passage 82 is located at a position on the first bearing surface 51 adjacent to the second bearing surface 52, that is, the second gas passage 82 is located at the edge of the first bearing surface 51. Therefore, it is possible to improve the heat dissipation efficiency of the edge region of the wafer 6 to the gas.
  • the region inside the second gas passage 82 is the region where the first bearing surface 51 is located, and the region can be further divided by the first gas passage 81. It is an intermediate area 511 and a central area 512.
  • the first roughness of the intermediate region 511 and the central region 512 can be designed to be the same or different in order to accommodate different heat dissipation requirements and adsorption requirements.
  • the annular passage is a circular passage and is centered on the center of the first bearing surface 51. This makes it possible to distribute the gas more evenly between the first bearing surface 51 and the wafer 6, so that the heat dissipation efficiency of the wafer 6 to the gas can be further improved.
  • the present invention is not limited thereto, and in practical applications, the number of gas passages may be three or more.
  • the shape of the gas passage is not limited to the circular passage adopted in the embodiment, and it may also employ, for example, an elliptical annular passage and/or an irregular annular passage.
  • the irregular annular passage may include a passage formed by a closed curve of any shape, and may also include a passage formed by any non-closed curve of a serpentine passage, a spiral passage, or the like.
  • the above chuck is an electrostatic chuck.
  • a gas distribution plate 9 is disposed between the insulating layer 5 and the base 7, wherein the insulating layer 5 is made of an insulating material, such as ceramic, the first bearing surface 51 and the first The second bearing surface 52 is the surface of the insulating layer 5.
  • a DC electrode (not shown) is provided in the insulating layer 5, and a direct current is applied to the DC electrode to cause electrostatic attraction between the DC electrode and the wafer 6, thereby fixing the wafer 6.
  • the gas passage 8 is disposed in the gas distribution
  • the plate 9 is in the shape of a groove; and a plurality of intake holes are provided in the insulating layer 5 to introduce a gas above the insulating layer 5.
  • the gas passage 82 is disposed in the gas distribution plate 9 in which a gas passage inlet 822 is provided to introduce gas from an external gas source to the gas passage 82 via the base 7.
  • a plurality of intake holes 821 communicating with the gas passages 82 are uniformly distributed in the insulating layer 5 to uniformly introduce the gas in the gas passages 82 above the insulating layer 5 to cool the wafer 6.
  • the gas passage is disposed in the gas distribution plate in the embodiment, the gas passage may be disposed in the base body in a practical application, and uniformly connected to the gas passage in the gas distribution plate and the insulation layer.
  • the chuck may not include a gas distribution plate, so that the gas passage may be disposed in the base body, and a plurality of air inlet holes communicating with the gas passage are uniformly disposed in the insulation layer; or The thickness of the insulating layer is increased, and a gas passage is disposed therein, and a plurality of intake holes communicating with the gas passage are uniformly disposed on the upper surface of the insulating layer. That is to say, in practical applications, it is only necessary to arrange the gas passage under the insulating layer and to uniformly introduce the gas above the insulating layer, without particularly limiting in which layer the gas passage is specifically disposed.
  • the base 7 is made of a metal material such as aluminum for supporting and cooling the insulating layer 5. Specifically, a cooling water passage 71 is provided in the base body 7, and the insulating layer 5 is cooled by passing cooling water into the cooling water passage 71, thereby indirectly carrying away heat generated by the wafer 6.
  • an embodiment of the present invention further provides a reaction chamber in which a chuck is disposed for carrying a wafer, and the chuck can adopt the chuck provided by the above embodiment of the present invention.
  • the reaction chamber provided by the embodiment of the present invention can not only improve the process effect of temperature control and cooling of the conventional wafer by using the chuck provided by the above embodiment of the present invention, but also can avoid New wafers (such as system-integrated wafer SOG) cause high temperature damage to the wafer due to excessive temperature rise on the wafer surface during high temperature processing.
  • New wafers such as system-integrated wafer SOG
  • an embodiment of the present invention further provides a semiconductor processing apparatus including a reaction chamber using the reaction chamber provided by the above embodiment of the present invention.
  • the semiconductor processing apparatus provided by the embodiments of the present invention can not only improve the process effect of the temperature control cooling of the conventional wafer by using the reaction chamber provided by the above embodiments of the present invention, but also avoid the novel wafer (such as the system integrated wafer SOG).
  • the novel wafer such as the system integrated wafer SOG.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

Provided are a chuck, a reaction chamber and a semiconductor processing equipment. The chuck comprises an insulating layer (5) and a substrate (7). The insulating layer (5) comprises a first bearing surface (51) for bearing a central area of a wafer (6) and a second bearing surface (52) surrounding the outer periphery of the first bearing surface (51) for bearing an edge area of the wafer (6), wherein the first bearing surface (51) has a first roughness that can increase contact area between the wafer (6) and the first bearing surface (51) under a condition that gas between the first bearing surface (51) and the wafer (6) is evenly distributed. The reaction chamber comprises the chuck. The semiconductor processing equipment comprises the reaction chamber. The chuck, the reaction chamber and the semiconductor processing equipment can improve heat conduction efficiency from the wafer to the chuck, thereby avoiding damage caused by too fast heating up of the wafer surface.

Description

卡盘、反应腔室及半导体加工设备Chuck, reaction chamber and semiconductor processing equipment 技术领域Technical field
本发明涉及半导体制造领域，具体地，涉及一种卡盘、反应腔室及半导体加工设备。The present invention relates to the field of semiconductor manufacturing, and in particular to a chuck, a reaction chamber, and a semiconductor processing apparatus.
背景技术Background technique
静电卡盘(Electro Static Chuck，简称ESC)广泛的应用于集成电路的制造工艺过程中，特别是等离子体刻蚀、物理气相沉积(Physical Vapor Deposition，简称PVD)、化学气相沉积(Chemical Vapor Deposition，简称CVD)等工艺，都需要ESC在反应腔室内固定晶片、为晶片提供直流偏压，以及对晶片表面进行迅速冷却，以使晶片表面在工艺中产生的高温能够得到有效控制。Electrostatic Chuck (ESC) is widely used in the manufacturing process of integrated circuits, especially plasma etching, physical vapor deposition (PVD), chemical vapor deposition (Chemical Vapor Deposition). For example, CVD) requires ESC to fix the wafer in the reaction chamber, provide DC bias to the wafer, and rapidly cool the surface of the wafer so that the high temperature generated by the wafer surface during the process can be effectively controlled.
图1为现有的静电卡盘的局部剖视图。请参阅图1，静电卡盘包括绝缘层1和用于支撑该绝缘层1的铝基座4，其中，绝缘层1的上表面采用陶瓷材料制造而成，用以承载晶片2且与其保持绝缘。在绝缘层1内部嵌有直流电极(图中未示出)，电导通后能够使绝缘层1与晶片2产生静电吸附力。而且，在绝缘层1内设置有冷却通道3，用以将冷却气体输送至绝缘层1与晶片2之间，以对晶片2进行冷却。在铝基座4的内部设有冷却水道41，通过向该冷却水道41中通入冷却水来冷却绝缘层1。1 is a partial cross-sectional view of a conventional electrostatic chuck. Referring to FIG. 1, an electrostatic chuck includes an insulating layer 1 and an aluminum base 4 for supporting the insulating layer 1. The upper surface of the insulating layer 1 is made of a ceramic material for carrying and insulating the wafer 2. . A DC electrode (not shown) is embedded in the insulating layer 1 to electrically electrostatically attract the insulating layer 1 and the wafer 2. Further, a cooling passage 3 is provided in the insulating layer 1 for conveying a cooling gas between the insulating layer 1 and the wafer 2 to cool the wafer 2. A cooling water passage 41 is provided inside the aluminum base 4, and the insulating layer 1 is cooled by passing cooling water into the cooling water passage 41.
图2为图1所示现有的静电卡盘的俯视图。请参阅图2，在绝缘层1的上表面设置有环形凸台10和多个凸点11。其中，环形凸台10环绕设置在绝缘层1的边缘处，用以对晶片2的边缘进行密封。多个凸点11均位于环形凸台10的内侧，且均匀分布，并且凸点11的上表面与环形凸台10的上表面均与晶片2相接触，用以共同支撑晶片2。 2 is a plan view of the conventional electrostatic chuck shown in FIG. 1. Referring to FIG. 2, an annular boss 10 and a plurality of bumps 11 are disposed on the upper surface of the insulating layer 1. The annular boss 10 is circumferentially disposed at the edge of the insulating layer 1 for sealing the edge of the wafer 2. A plurality of bumps 11 are located inside the annular boss 10 and are evenly distributed, and the upper surface of the bump 11 and the upper surface of the annular boss 10 are in contact with the wafer 2 for supporting the wafer 2 in common.
上述静电卡盘在实际应用中不可避免地存在以下问题：The electrostatic chuck described above inevitably has the following problems in practical applications:
绝缘层1与晶片2之间的热量传递主要依靠多个凸点11与晶片2的下表面相接触，以及绝缘层1与晶片2之间的冷却气体，但是，由于凸点11与晶片2的下表面之间属于点接触，接触面积有限，无法满足晶片2快速冷却的需求，尤其当进行高温工艺时，晶片2的表面温度快速上升，使得晶片2因高温而损坏。The heat transfer between the insulating layer 1 and the wafer 2 mainly depends on the plurality of bumps 11 contacting the lower surface of the wafer 2, and the cooling gas between the insulating layer 1 and the wafer 2, but due to the bumps 11 and the wafer 2 The lower surface is a point contact, and the contact area is limited, which cannot meet the requirement of rapid cooling of the wafer 2. Especially when the high temperature process is performed, the surface temperature of the wafer 2 rises rapidly, so that the wafer 2 is damaged due to high temperature.
发明内容Summary of the invention
本发明旨在至少解决现有技术中存在的技术问题之一，提出了一种卡盘、反应腔室及半导体加工设备。本发明提供的卡盘、反应腔室及半导体加工设备可以提高晶片向卡盘进行热传导的效率，从而可以避免因晶片表面升温过快而造成晶片损坏。The present invention is directed to at least one of the technical problems existing in the prior art, and proposes a chuck, a reaction chamber, and a semiconductor processing apparatus. The chuck, the reaction chamber and the semiconductor processing apparatus provided by the invention can improve the efficiency of heat conduction of the wafer to the chuck, thereby avoiding wafer damage caused by excessive temperature rise of the wafer surface.
为实现本发明的目的而提供一种卡盘，包括绝缘层和基体，所述绝缘层包括第一承载面和环绕在所述第一承载面外周的第二承载面，所述第一承载面用于承载晶片的中心区域，所述第二承载面用于承载晶片的边缘区域，其中，所述第一承载面具有第一粗糙度，所述第一粗糙度能够在保证位于所述第一承载面与晶片之间的气体均匀分布的前提下，增大晶片与所述第一承载面之间的接触面积。To achieve the object of the present invention, a chuck comprising an insulating layer and a base body, the insulating layer comprising a first bearing surface and a second bearing surface surrounding the outer circumference of the first bearing surface, the first bearing surface a central region for carrying a wafer, the second bearing surface for carrying an edge region of the wafer, wherein the first bearing surface has a first roughness, and the first roughness can be guaranteed to be located at the first Under the premise that the gas between the bearing surface and the wafer is evenly distributed, the contact area between the wafer and the first bearing surface is increased.
优选的，所述第一粗糙度为0.6-0.8um。Preferably, the first roughness is 0.6-0.8 um.
优选的，所述第二承载面具有第二粗糙度，所述第二粗糙度能使所述第二承载面与晶片紧密接触，从而密封所述第一承载面与晶片之间的气体。Preferably, the second bearing surface has a second roughness, and the second roughness enables the second bearing surface to be in close contact with the wafer to seal the gas between the first bearing surface and the wafer.
优选的，所述第二粗糙度小于或等于0.4um。Preferably, the second roughness is less than or equal to 0.4 um.
优选的，所述第一粗糙度大于所述第二粗糙度。Preferably, the first roughness is greater than the second roughness.
优选的，在所述绝缘层的下方设置有至少两个气体通道，用以向所述第一承载面与晶片之间通入气体。 Preferably, at least two gas passages are disposed under the insulating layer for introducing gas between the first bearing surface and the wafer.
优选的，每个所述气体通道为环形通道，且至少两个所述环形通道为同心环。Preferably, each of the gas passages is an annular passage, and at least two of the annular passages are concentric rings.
优选的，所述环形通道包括：圆环形通道、椭圆环形通道和/或不规则环状通道。Preferably, the annular channel comprises: a circular annular channel, an elliptical annular channel and/or an irregular annular channel.
优选的，在至少两个所述环形通道中，最外环的所述环形通道位于所述第一承载面的边缘处。Preferably, in at least two of the annular passages, the annular passage of the outermost ring is located at an edge of the first bearing surface.
优选的，所述圆环形通道以所述第一承载面的中心为圆心。Preferably, the annular passage is centered on a center of the first bearing surface.
作为另一个技术方案，本发明还提供一种反应腔室，该反应腔室包括本发明提供的上述卡盘。As another technical solution, the present invention also provides a reaction chamber comprising the above-described chuck provided by the present invention.
作为另一个技术方案，本发明还提供一种反半导体加工设备，该半导体加工设备包括本发明提供的上述反应腔室。As another technical solution, the present invention also provides an inverse semiconductor processing apparatus including the above-described reaction chamber provided by the present invention.
本发明具有以下有益效果：The invention has the following beneficial effects:
本发明提供的卡盘，其绝缘层包括第一承载面和环绕在该第一承载面外周的第二承载面，第一承载面和第二承载面用于分别承载晶片的中心区域和边缘区域。该第一承载面具有第一粗糙度，该第一粗糙度能够在保证位于第一承载面与晶片之间的气体均匀分布的前提下，增大晶片与承载面之间的接触面积，从而可以提高晶片向卡盘的绝缘层进行热传导的效率，改善对晶片的冷却效果，从而不仅可以改善常规晶片的控温冷却的工艺效果，而且可以解决新型晶片(如***集成晶片SOG)在高温工艺时，晶片温度快速升高的问题，从而避免晶片高温损坏。The chuck provided by the present invention has an insulating layer including a first bearing surface and a second bearing surface surrounding the outer circumference of the first bearing surface, the first bearing surface and the second bearing surface for respectively carrying the central area and the edge area of the wafer . The first bearing surface has a first roughness, which can increase the contact area between the wafer and the bearing surface under the premise of ensuring uniform distribution of the gas between the first bearing surface and the wafer, thereby Improve the efficiency of heat transfer from the wafer to the insulating layer of the chuck, improve the cooling effect on the wafer, thereby not only improving the temperature-controlled cooling process of the conventional wafer, but also solving the new wafer (such as system integrated wafer SOG) in the high temperature process. The problem of rapid rise in wafer temperature prevents high temperature damage of the wafer.
本发明提供的反应腔室，其通过采用本发明提供的上述卡盘，不仅可以改善常规晶片的控温冷却的工艺效果，而且可以解决新型晶片在进行高温工艺时，晶片温度快速升高的问题，从而避免晶片高温损坏。The reaction chamber provided by the invention can not only improve the process effect of temperature control and cooling of the conventional wafer by using the above-mentioned chuck provided by the invention, but also solve the problem that the wafer temperature rises rapidly when the new wafer is subjected to a high temperature process. To avoid high temperature damage to the wafer.
本发明提供的半导体加工设备，其通过采用本发明提供的反应腔室，不仅可以改善常规晶片的控温冷却的工艺效果，而且可以避免新型晶片在进行高温工艺时，因晶片表面升温过快，造成晶片出现高温损坏。 The semiconductor processing apparatus provided by the invention can not only improve the process effect of the temperature control cooling of the conventional wafer by using the reaction chamber provided by the invention, but also can avoid the temperature rise of the wafer surface too fast when the new wafer is subjected to a high temperature process. Causes high temperature damage to the wafer.
附图说明DRAWINGS
图1为现有的静电卡盘的局部剖视图；Figure 1 is a partial cross-sectional view of a conventional electrostatic chuck;
图2为图1所示现有的静电卡盘的俯视图；Figure 2 is a plan view of the conventional electrostatic chuck shown in Figure 1;
图3为本发明实施例提供的卡盘的剖视图；3 is a cross-sectional view of a chuck according to an embodiment of the present invention;
图4为图3中I区域的放大图；Figure 4 is an enlarged view of the area I in Figure 3;
图5为本发明实施例中的气体通道的结构和位置关系示意图。Fig. 5 is a schematic view showing the structure and positional relationship of a gas passage in an embodiment of the present invention.
其中，附图标记为：绝缘层1、晶片2、冷却通道3、铝基座4、冷却水道41、环形凸台10、凸点11、绝缘层5、基体7、气体通道8、气体分布板9、第一承载面51、第二承载面52、晶片6、第一气体通道81、第二气体通道82、进气孔821、气体通道入口822、中间区域511和中心区域512。Wherein, the reference numerals are: insulating layer 1, wafer 2, cooling channel 3, aluminum base 4, cooling water channel 41, annular boss 10, bump 11, insulating layer 5, substrate 7, gas passage 8, gas distribution plate 9. First bearing surface 51, second bearing surface 52, wafer 6, first gas passage 81, second gas passage 82, intake aperture 821, gas passage inlet 822, intermediate region 511 and central region 512.
具体实施方式detailed description
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图来对本发明提供的卡盘、反应腔室及半导体加工设备进行详细描述。In order to enable those skilled in the art to better understand the technical solutions of the present invention, the chuck, the reaction chamber and the semiconductor processing apparatus provided by the present invention are described in detail below with reference to the accompanying drawings.
图3为本发明实施例提供的卡盘的剖视图。图4为图3中I区域的放大图。请一并参阅图3和图4，卡盘包括绝缘层5和基体7，其中，该绝缘层5包括第一承载面51和环绕在该第一承载面51外周的第二承载面52，第一承载面51用于承载晶片6的中心区域，第二承载面52用于承载晶片6的边缘区域。其中，第一承载面51具有第一粗糙度，该第一粗糙度能够在保证位于第一承载面51与晶片6之间的气体均匀分布的前提下，增大晶片6与第一承载面51之间的接触面积。该气体被输送至第一承载面51与晶片6之间，以增加二者之间的热量传递。气体可以采用惰性气体，例如氦气。FIG. 3 is a cross-sectional view of a chuck according to an embodiment of the present invention. Figure 4 is an enlarged view of the area I in Figure 3. Referring to FIG. 3 and FIG. 4 together, the chuck includes an insulating layer 5 and a base body 7, wherein the insulating layer 5 includes a first bearing surface 51 and a second bearing surface 52 surrounding the outer circumference of the first bearing surface 51, A carrier surface 51 is used to carry the central area of the wafer 6, and a second carrier surface 52 is used to carry the edge regions of the wafer 6. The first bearing surface 51 has a first roughness, which can increase the wafer 6 and the first bearing surface 51 under the premise that the gas between the first bearing surface 51 and the wafer 6 is evenly distributed. The area of contact between. The gas is delivered between the first bearing surface 51 and the wafer 6 to increase heat transfer therebetween. The gas may be an inert gas such as helium.
进一步说，上述第一粗糙度能够使第一承载面51与晶片6之间存 在间隙，该间隙能够使气体在该间隙中形成对流，从而实现气体的均匀分布，进而可以提高晶片6向气体的散热效率。同时，第一承载面51与晶片6的下表面之间仍然属于面接触，保证了二者之间的接触面积，从而可以提高晶片6向卡盘进行热传导的效率，改善对晶片6的冷却效果，进而不仅可以改善常规晶片6的控温冷却的工艺效果，而且可以避免新型晶片(如***集成晶片SOG)在进行高温工艺时，因晶片6的表面升温过快而导致晶片6因高温而损坏。Further, the first roughness can save the first bearing surface 51 and the wafer 6. In the gap, the gap enables the gas to form a convection in the gap, thereby achieving uniform distribution of the gas, thereby improving the heat dissipation efficiency of the wafer 6 to the gas. At the same time, the first bearing surface 51 and the lower surface of the wafer 6 still belong to the surface contact, which ensures the contact area between the two, thereby improving the efficiency of heat conduction of the wafer 6 to the chuck and improving the cooling effect on the wafer 6. Moreover, not only can the process effect of the temperature control cooling of the conventional wafer 6 be improved, but also the new wafer (such as the system integrated wafer SOG) can be prevented from being damaged by the high temperature of the wafer 6 due to the excessive temperature rise of the surface of the wafer 6 during the high temperature process. .
优选的，上述第一粗糙度的取值范围在0.6-0.8um。在该取值范围内，第一承载面51与晶片6之间的接触面积最大，从而可以提高晶片6向第一承载面51进行热传导的效率。这里，粗糙度即为相应表面的粗糙程度，表面越粗糙，则粗糙度越大；表面越光滑，则粗糙度越大。Preferably, the first roughness ranges from 0.6 to 0.8 um. Within this range of values, the contact area between the first carrying surface 51 and the wafer 6 is maximized, so that the efficiency of heat transfer of the wafer 6 to the first carrying surface 51 can be improved. Here, the roughness is the roughness of the corresponding surface, the rougher the surface, the greater the roughness; the smoother the surface, the greater the roughness.
优选的，第二承载面52具有第二粗糙度，该第二粗糙度能使第二承载面52与晶片6紧密接触，从而密封第一承载面51与晶片6之间的气体，进而可以避免气体泄漏。优选的，第二粗糙度小于或者等于0.4um。在该取值范围内，对气体的密封效果较好。Preferably, the second bearing surface 52 has a second roughness, which enables the second bearing surface 52 to be in close contact with the wafer 6, thereby sealing the gas between the first bearing surface 51 and the wafer 6, thereby avoiding Gas leaks. Preferably, the second roughness is less than or equal to 0.4 um. Within this range of values, the sealing effect on the gas is better.
可选的，使第一粗糙度大于第二粗糙度。在第一粗糙度高于第二粗糙度时，第一承载面更有利于晶片向第一承载面进行热传导，第二承载面与晶片在进行静电吸附时能进行更紧密的接触，密封第一承载面和晶片之间的气体。Optionally, the first roughness is greater than the second roughness. When the first roughness is higher than the second roughness, the first bearing surface is more favorable for heat conduction of the wafer to the first bearing surface, and the second bearing surface can be in closer contact with the wafer during electrostatic adsorption, sealing the first The gas between the bearing surface and the wafer.
可选的，为提高晶片的散热效率，可以在绝缘层的下方设置气体通道。请参阅图5，其中示出了气体通道的结构和位置关系。具体地，本实施例提供的卡盘，在绝缘层5的下方设置有气体通道8，具体为第一气体通道81和第二气体通道82，用以向第一承载面51与晶片6之间通入上述气体。在本实施例中，第一气体通道81和第二气体通道82均为环形通道，且为同心环。通过采用环形的气体通道8，可以使气体在第一承载面51与晶片6之间分布得更加均匀，从而可以进一步提高 晶片6向气体的散热效率。Optionally, in order to improve the heat dissipation efficiency of the wafer, a gas passage may be disposed under the insulating layer. Referring to Figure 5, the structure and positional relationship of the gas passages are shown. Specifically, the chuck provided in this embodiment is provided with a gas passage 8 , specifically a first gas passage 81 and a second gas passage 82 , between the first bearing surface 51 and the wafer 6 below the insulating layer 5 . Pass the above gas. In the present embodiment, the first gas passage 81 and the second gas passage 82 are both annular passages and are concentric rings. By using the annular gas passage 8, the gas can be distributed more evenly between the first bearing surface 51 and the wafer 6, thereby further improving The heat dissipation efficiency of the wafer 6 to the gas.
优选的，最外环的环形通道，即，第二气体通道82位于第一承载面51上的临近第二承载面52的位置处，即，第二气体通道82位于第一承载面51的边缘处，从而能够提高晶片6的边缘区域向气体的散热效率。Preferably, the annular passage of the outermost ring, that is, the second gas passage 82 is located at a position on the first bearing surface 51 adjacent to the second bearing surface 52, that is, the second gas passage 82 is located at the edge of the first bearing surface 51. Therefore, it is possible to improve the heat dissipation efficiency of the edge region of the wafer 6 to the gas.
进一步的，由于第二气体通道82位于第一承载面51的边缘处，因此，第二气体通道82内侧的区域即为第一承载面51所在区域，该区域可以被第一气体通道81进一步划分为中间区域511和中心区域512。在实际应用中，可以将中间区域511和中心区域512的第一粗糙度设计为相同的或者不同的，以便适应不同的散热需求和吸附需求。Further, since the second gas passage 82 is located at the edge of the first bearing surface 51, the region inside the second gas passage 82 is the region where the first bearing surface 51 is located, and the region can be further divided by the first gas passage 81. It is an intermediate area 511 and a central area 512. In practical applications, the first roughness of the intermediate region 511 and the central region 512 can be designed to be the same or different in order to accommodate different heat dissipation requirements and adsorption requirements.
进一步优选的，上述环形通道为圆环形通道，且以第一承载面51的中心为圆心。这样可以使气体在第一承载面51与晶片6之间分布得更加均匀，从而可以进一步提高晶片6向气体的散热效率。Further preferably, the annular passage is a circular passage and is centered on the center of the first bearing surface 51. This makes it possible to distribute the gas more evenly between the first bearing surface 51 and the wafer 6, so that the heat dissipation efficiency of the wafer 6 to the gas can be further improved.
需要说明的是，在本实施例中，在绝缘层的下方设置有两个气体通道，但是本发明并不局限于此，在实际应用中，气体通道的数量还可以为三个以上。此外，气体通道的形状并不局限于本实施例采用的圆环形通道，其还可以采用诸如椭圆环形通道和/或不规则环状通道。需要说明的是，本发明中，不规则环状通道可以包括任意形状的闭合曲线构成的通道，也可以包括蛇形通道、螺旋线形通道等的任意非闭合曲线构成的通道。It should be noted that in the present embodiment, two gas passages are provided under the insulating layer, but the present invention is not limited thereto, and in practical applications, the number of gas passages may be three or more. Further, the shape of the gas passage is not limited to the circular passage adopted in the embodiment, and it may also employ, for example, an elliptical annular passage and/or an irregular annular passage. It should be noted that, in the present invention, the irregular annular passage may include a passage formed by a closed curve of any shape, and may also include a passage formed by any non-closed curve of a serpentine passage, a spiral passage, or the like.
可选的，上述卡盘为静电卡盘。具体地，请一并参阅图3和图4，在绝缘层5和基体7之间设置有气体分布板9，其中，绝缘层5采用绝缘材料制作，例如陶瓷，上述第一承载面51和第二承载面52即为该绝缘层5的表面。并且，在该绝缘层5内设置有直流电极(图中未示出)，通过向该直流电极通入直流电，使直流电极与晶片6产生静电吸附力，从而实现对晶片6的固定。优选的，上述气体通道8设置在该气体分布 板9中，且呈槽状；并且，在绝缘层5中设置多个进气孔，以将气体引入到绝缘层5的上方。Optionally, the above chuck is an electrostatic chuck. Specifically, please refer to FIG. 3 and FIG. 4 together, a gas distribution plate 9 is disposed between the insulating layer 5 and the base 7, wherein the insulating layer 5 is made of an insulating material, such as ceramic, the first bearing surface 51 and the first The second bearing surface 52 is the surface of the insulating layer 5. Further, a DC electrode (not shown) is provided in the insulating layer 5, and a direct current is applied to the DC electrode to cause electrostatic attraction between the DC electrode and the wafer 6, thereby fixing the wafer 6. Preferably, the gas passage 8 is disposed in the gas distribution The plate 9 is in the shape of a groove; and a plurality of intake holes are provided in the insulating layer 5 to introduce a gas above the insulating layer 5.
具体地，以气体通道82为例详细说明气体通道8的结构和气体流通路径。气体通道82设置在气体分布板9中，在基体7中设置有气体通道入口822，以将来自外部气源的气体经由基体7引入到气体通道82。在绝缘层5中均匀分布有与气体通道82相连通的多个进气孔821，以将气体通道82内的气体均匀地引入到绝缘层5的上方，以便对晶片6进行冷却。Specifically, the structure of the gas passage 8 and the gas flow path will be described in detail by taking the gas passage 82 as an example. The gas passage 82 is disposed in the gas distribution plate 9 in which a gas passage inlet 822 is provided to introduce gas from an external gas source to the gas passage 82 via the base 7. A plurality of intake holes 821 communicating with the gas passages 82 are uniformly distributed in the insulating layer 5 to uniformly introduce the gas in the gas passages 82 above the insulating layer 5 to cool the wafer 6.
需要说明的是，尽管本实施例中气体通道设置在气体分布板中，但是在实际应用中也可以将气体通道设置在基体中，并在气体分布板和绝缘层中均匀设置与气体通道相连通的多个进气孔，以将气体通道内的气体均匀地引入到绝缘层的上方。进一步地，在实际应用中，卡盘也可以不包含气体分布板，这样，可以将气体通道设置在基体中，并在绝缘层中均匀设置与气体通道相连通的多个进气孔；或者可以将绝缘层的厚度增加，并将气体通道设置于其内，且在绝缘层的上表面均匀设置与气体通道相连通的多个进气孔。也就是说，在实际应用中，只要将气体通道设置在绝缘层的下方并能使气体均匀地引入到绝缘层的上方即可，而不必特别限定气体通道具体设置在哪一层中。It should be noted that although the gas passage is disposed in the gas distribution plate in the embodiment, the gas passage may be disposed in the base body in a practical application, and uniformly connected to the gas passage in the gas distribution plate and the insulation layer. A plurality of intake holes to uniformly introduce a gas in the gas passage above the insulating layer. Further, in practical applications, the chuck may not include a gas distribution plate, so that the gas passage may be disposed in the base body, and a plurality of air inlet holes communicating with the gas passage are uniformly disposed in the insulation layer; or The thickness of the insulating layer is increased, and a gas passage is disposed therein, and a plurality of intake holes communicating with the gas passage are uniformly disposed on the upper surface of the insulating layer. That is to say, in practical applications, it is only necessary to arrange the gas passage under the insulating layer and to uniformly introduce the gas above the insulating layer, without particularly limiting in which layer the gas passage is specifically disposed.
基体7采用诸如铝等的金属材料制作，用于支撑和冷却绝缘层5。具体地，在基体7内设置有冷却水道71，通过向冷却水道71中通入冷却水，来冷却绝缘层5，从而间接带走由晶片6产生的热量。The base 7 is made of a metal material such as aluminum for supporting and cooling the insulating layer 5. Specifically, a cooling water passage 71 is provided in the base body 7, and the insulating layer 5 is cooled by passing cooling water into the cooling water passage 71, thereby indirectly carrying away heat generated by the wafer 6.
作为另一个技术方案，本发明实施例还提供一种反应腔室，在该反应腔室内设置有卡盘，用于承载晶片，该卡盘可采用本发明上述实施例提供的卡盘。As another technical solution, an embodiment of the present invention further provides a reaction chamber in which a chuck is disposed for carrying a wafer, and the chuck can adopt the chuck provided by the above embodiment of the present invention.
本发明实施例提供的反应腔室，其通过采用本发明上述实施例提供的卡盘，不仅可以改善常规晶片的控温冷却的工艺效果，而且可以避免 新型晶片(如***集成晶片SOG)在进行高温工艺时，因晶片表面升温过快，造成晶片出现高温损坏。The reaction chamber provided by the embodiment of the present invention can not only improve the process effect of temperature control and cooling of the conventional wafer by using the chuck provided by the above embodiment of the present invention, but also can avoid New wafers (such as system-integrated wafer SOG) cause high temperature damage to the wafer due to excessive temperature rise on the wafer surface during high temperature processing.
作为另一个技术方案，本发明实施例还提供一种半导体加工设备，包括反应腔室，该反应腔室采用本发明上述实施例提供的反应腔室。As another technical solution, an embodiment of the present invention further provides a semiconductor processing apparatus including a reaction chamber using the reaction chamber provided by the above embodiment of the present invention.
本发明实施例提供的半导体加工设备，其通过采用本发明上述实施例提供的反应腔室，不仅可以改善常规晶片的控温冷却的工艺效果，而且可以避免新型晶片(如***集成晶片SOG)在进行高温工艺时，因晶片表面升温过快，造成晶片出现高温损坏。The semiconductor processing apparatus provided by the embodiments of the present invention can not only improve the process effect of the temperature control cooling of the conventional wafer by using the reaction chamber provided by the above embodiments of the present invention, but also avoid the novel wafer (such as the system integrated wafer SOG). When the high temperature process is performed, the wafer surface is heated too fast, causing high temperature damage to the wafer.
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。 It is to be understood that the above embodiments are merely exemplary embodiments employed to explain the principles of the invention, but the invention is not limited thereto. Various modifications and improvements can be made by those skilled in the art without departing from the spirit and scope of the invention. These modifications and improvements are also considered to be within the scope of the invention.

Claims (12)

  1. 一种卡盘，包括绝缘层和基体，其特征在于，所述绝缘层包括第一承载面和环绕在所述第一承载面外周的第二承载面，所述第一承载面用于承载晶片的中心区域，所述第二承载面用于承载晶片的边缘区域，其中，A chuck comprising an insulating layer and a substrate, wherein the insulating layer comprises a first bearing surface and a second bearing surface surrounding an outer circumference of the first bearing surface, the first bearing surface for carrying a wafer a central area for carrying an edge region of the wafer, wherein
    所述第一承载面具有第一粗糙度，所述第一粗糙度能够在保证位于所述第一承载面与晶片之间的气体均匀分布的前提下，增大晶片与所述第一承载面之间的接触面积。The first bearing surface has a first roughness, and the first roughness can increase the wafer and the first bearing surface while ensuring uniform distribution of gas between the first bearing surface and the wafer. The area of contact between.
  2. 根据权利要求1所述的卡盘，其特征在于，所述第一粗糙度为0.6-0.8um。The chuck of claim 1 wherein said first roughness is between 0.6 and 0.8 um.
  3. 根据权利要求1所述的卡盘，其特征在于，所述第二承载面具有第二粗糙度，所述第二粗糙度能使所述第二承载面与晶片紧密接触，从而密封所述第一承载面与晶片之间的气体。The chuck according to claim 1, wherein said second bearing surface has a second roughness, said second roughness enabling said second bearing surface to be in intimate contact with said wafer, thereby sealing said first A gas between the carrier surface and the wafer.
  4. 根据权利要求3所述的卡盘，其特征在于，所述第二粗糙度小于或等于0.4um。The chuck of claim 3 wherein said second roughness is less than or equal to 0.4 um.
  5. 根据权利要求3所述的卡盘，其特征在于，所述第一粗糙度大于所述第二粗糙度。The chuck of claim 3 wherein said first roughness is greater than said second roughness.
  6. 根据权利要求1所述的卡盘，其特征在于，在所述第一承载面的下方设置有至少两个气体通道，且所述气体通道与所述第一承载面的上方相通，用以向所述第一承载面与晶片之间通入气体。The chuck according to claim 1, wherein at least two gas passages are disposed below the first bearing surface, and the gas passage communicates with an upper portion of the first bearing surface for A gas is introduced between the first bearing surface and the wafer.
  7. 根据权利要求6所述的卡盘，其特征在于，每个所述气体通道为环 形通道，且至少两个所述环形通道为同心环。A chuck according to claim 6 wherein each of said gas passages is a ring a channel, and at least two of the annular channels are concentric rings.
  8. 根据权利要求7所述的卡盘，其特征在于，所述环形通道包括：圆环形通道、椭圆环形通道和/或不规则环状通道。The chuck of claim 7 wherein said annular passage comprises: an annular passage, an elliptical annular passage, and/or an irregular annular passage.
  9. 根据权利要求7所述的卡盘，其特征在于，在至少两个所述环形通道中，最外环的所述环形通道位于所述第一承载面的边缘处。A chuck according to claim 7, wherein in at least two of said annular passages, said annular passage of the outermost ring is located at an edge of said first bearing surface.
  10. 根据权利要求8所述的卡盘，其特征在于，所述圆环形通道以所述第一承载面的中心为圆心。The chuck according to claim 8, wherein said annular passage is centered on a center of said first bearing surface.
  11. 一种反应腔室，其特征在于，所述反应腔室包括权利要求1-10任一项所述的卡盘。A reaction chamber, characterized in that the reaction chamber comprises the chuck of any of claims 1-10.
  12. 一种半导体加工设备，其特征在于，所述半导体加工设备包括权利要求11所述的反应腔室。 A semiconductor processing apparatus, characterized in that the semiconductor processing apparatus comprises the reaction chamber of claim 11.
PCT/CN2016/112387 2016-08-16 2016-12-27 Chuck, reaction chamber and semiconductor processing equipment WO2018032684A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610675069.3A CN107768300B (en) 2016-08-16 2016-08-16 Chuck, reaction chamber and semiconductor processing equipment
CN201610675069.3 2016-08-16

Publications (1)

Publication Number Publication Date
WO2018032684A1 true WO2018032684A1 (en) 2018-02-22

Family

ID=61196152

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/112387 WO2018032684A1 (en) 2016-08-16 2016-12-27 Chuck, reaction chamber and semiconductor processing equipment

Country Status (3)

Country Link
CN (1) CN107768300B (en)
TW (1) TWI642139B (en)
WO (1) WO2018032684A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021520639A (en) * 2018-04-09 2021-08-19 アプライド マテリアルズ インコーポレイテッドＡｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ，Ｉｎｃｏｒｐｏｒａｔｅｄ Carbon hardmasks and related methods for patterning applications

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020003911A1 (en) * 2018-06-26 2020-01-02 株式会社キルトプランニングオフィス Illumination device
US11430685B2 (en) * 2019-03-19 2022-08-30 Ngk Insulators, Ltd. Wafer placement apparatus and method of manufacturing the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101211810A (en) * 2006-12-30 2008-07-02 北京北方微电子基地设备工艺研究中心有限责任公司 Electrostatic chuck apparatus
US20080190367A1 (en) * 2007-02-12 2008-08-14 Samsung Electronics Co., Ltd. Chuck assembly and high density plasma equipment having the same
CN104124127A (en) * 2013-04-27 2014-10-29 北京北方微电子基地设备工艺研究中心有限责任公司 Pallet and plasma processing equipment
CN105074902A (en) * 2013-03-29 2015-11-18 住友大阪水泥股份有限公司 Electrostatic chuck device
CN105390368A (en) * 2014-09-09 2016-03-09 北京北方微电子基地设备工艺研究中心有限责任公司 Wafer precleaning cavity and semiconductor processing equipment

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3859937B2 (en) * 2000-06-02 2006-12-20 住友大阪セメント株式会社 Electrostatic chuck
JP4439135B2 (en) * 2001-04-27 2010-03-24 京セラ株式会社 Electrostatic chuck
US6552892B2 (en) * 2001-05-09 2003-04-22 Axcelis Technologies, Inc. Method and apparatus for the grounding of process wafers by the use of conductive regions created by ion implantation into the surface of an electrostatic clamp
JP2003224180A (en) * 2002-01-28 2003-08-08 Kyocera Corp Wafer support member
US20040055709A1 (en) * 2002-09-19 2004-03-25 Applied Materials, Inc. Electrostatic chuck having a low level of particle generation and method of fabricating same
CN100468619C (en) * 2006-08-23 2009-03-11 北京北方微电子基地设备工艺研究中心有限责任公司 Temperature control device of etching equipment and its method for controlling wafer temperature
CN102449754B (en) * 2009-05-15 2015-10-21 恩特格林斯公司 There is the electrostatic chuck of polymer protrusions
KR100997374B1 (en) * 2009-08-21 2010-11-30 주식회사 코미코 Electrode static chuck and method of manufacturing the same
TWI558841B (en) * 2009-12-22 2016-11-21 應用材料股份有限公司 Slit valve tunnel support

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101211810A (en) * 2006-12-30 2008-07-02 北京北方微电子基地设备工艺研究中心有限责任公司 Electrostatic chuck apparatus
US20080190367A1 (en) * 2007-02-12 2008-08-14 Samsung Electronics Co., Ltd. Chuck assembly and high density plasma equipment having the same
CN105074902A (en) * 2013-03-29 2015-11-18 住友大阪水泥股份有限公司 Electrostatic chuck device
CN104124127A (en) * 2013-04-27 2014-10-29 北京北方微电子基地设备工艺研究中心有限责任公司 Pallet and plasma processing equipment
CN105390368A (en) * 2014-09-09 2016-03-09 北京北方微电子基地设备工艺研究中心有限责任公司 Wafer precleaning cavity and semiconductor processing equipment

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021520639A (en) * 2018-04-09 2021-08-19 アプライド マテリアルズ インコーポレイテッドＡｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ，Ｉｎｃｏｒｐｏｒａｔｅｄ Carbon hardmasks and related methods for patterning applications
US11784042B2 (en) 2018-04-09 2023-10-10 Applied Materials, Inc. Carbon hard masks for patterning applications and methods related thereto
JP7407121B2 (en) 2018-04-09 2023-12-28 アプライド マテリアルズ インコーポレイテッド Carbon hard masks and related methods for patterning applications

Also Published As

Publication number Publication date
CN107768300B (en) 2021-09-17
CN107768300A (en) 2018-03-06
TWI642139B (en) 2018-11-21
TW201807774A (en) 2018-03-01

Similar Documents

Publication Publication Date Title
US8282769B2 (en) Shower head and plasma processing apparatus having same
JP5660753B2 (en) High temperature cathode for plasma etching
TW202044478A (en) Placing table and substrate processing apparatus
JP5893516B2 (en) Processing apparatus for processing object and mounting table for processing object
US20090194264A1 (en) Substrate mounting table, substrate processing apparatus and substrate temperature control method
JPH04211146A (en) Electrostatic chuck
KR20190082333A (en) Process kit design for chamber heater and wafer rotation mechanism
CN111684580B (en) Quick response base assembly for selective pre-cleaning
WO2018032684A1 (en) Chuck, reaction chamber and semiconductor processing equipment
TW201442143A (en) Substrate support chuck cooling for deposition chamber
JP2006066417A (en) Electrostatic chuck and tray for substrate conveyance
TWI757242B (en) Thermal management systems and methods for wafer processing systems
US20210066049A1 (en) Stage and plasma processing apparatus
CN110797291A (en) Device for self-centering a preheating component
KR20190088078A (en) A rotatable electrostatic chuck having a rear gas supply part
TW202109591A (en) Sheath and temperature control of process kit
TWI809007B (en) Focus ring for semiconductor manufacturing apparatus and semiconductor manufacturing apparatus
TW202038374A (en) Electrostatic chuck with improved thermal coupling for temperature sensitive processes
TWI827502B (en) Electrostatic chuck for high temperature processing chamber and forming method thereof
US20230075462A1 (en) Electrostatic edge ring mounting system for substrate processing
TW201442139A (en) Pallet and plasma machining apparatus
TW202123304A (en) High conductance lower shield for process chamber
JP2011003913A (en) Electrostatic chuck
JP2015076457A (en) Substrate processing apparatus
JP7361588B2 (en) Edge ring and substrate processing equipment

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16913436

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16913436

Country of ref document: EP

Kind code of ref document: A1