WO2018018424A1 - Procédé de régulation de température et système sur puce associé - Google Patents

Procédé de régulation de température et système sur puce associé Download PDF

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Publication number
WO2018018424A1
WO2018018424A1 PCT/CN2016/091785 CN2016091785W WO2018018424A1 WO 2018018424 A1 WO2018018424 A1 WO 2018018424A1 CN 2016091785 W CN2016091785 W CN 2016091785W WO 2018018424 A1 WO2018018424 A1 WO 2018018424A1
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WO
WIPO (PCT)
Prior art keywords
threads
chip
core
temperature control
allocation policy
Prior art date
Application number
PCT/CN2016/091785
Other languages
English (en)
Chinese (zh)
Inventor
张升泽
Original Assignee
张升泽
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 张升泽 filed Critical 张升泽
Priority to PCT/CN2016/091785 priority Critical patent/WO2018018424A1/fr
Publication of WO2018018424A1 publication Critical patent/WO2018018424A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring

Definitions

  • the present invention relates to the field of electronic chips, and in particular, to a chip-based temperature control method and system.
  • the chip also has its own unique place. In a broad sense, as long as it is a semiconductor wafer manufactured by microfabrication, it can be called a chip, and there is no circuit inside.
  • a semiconductor light source chip for example, a mechanical chip such as a MEMS gyroscope; or a biochip such as a DNA chip.
  • the intersection of the chip and the integrated circuit is on the "circuit on the silicon wafer.”
  • the chipset is a series of interrelated chipsets that are interdependent and can play a bigger role, such as the processor inside the computer and the North-South Bridge chipset, the RF, baseband and power management chipset in the phone. .
  • a chip-based temperature control method is provided, which solves the shortcomings of the prior art that temperature calculation and management cannot be realized.
  • a chip-based temperature control method comprising the steps of:
  • the temperature of each core is calculated based on the number of threads for temperature control.
  • the obtaining, according to the allocation policy, the number of threads of each kernel is specific, including:
  • the number of threads per core is allocated according to the load balancing allocation policy.
  • the obtaining, according to the allocation policy, the number of threads of each kernel is specific, including:
  • the number of threads per core is allocated based on the number-averaged allocation policy.
  • a chip-based temperature control system comprising:
  • the obtaining unit is configured to acquire a total thread of the multi-core chip
  • An allocation unit for knowing the number of threads of each kernel according to an allocation policy
  • the allocating unit is specifically configured to allocate a number of threads of each core according to a load balancing allocation policy.
  • the allocating unit is specifically configured to allocate a number of threads of each core according to a quantity-averaged allocation policy.
  • the technical solution provided by the specific embodiment of the present invention acquires the total thread of the multi-core chip, learns the number of threads of each core according to the allocation strategy, calculates the temperature of each core according to the number of threads, and therefore has the function of implementing chip-based temperature control and management. advantage.
  • FIG. 1 is a flow chart of a chip-based temperature control method provided by the present invention.
  • FIG. 2 is a structural diagram of a chip-based temperature control system provided by the present invention.
  • FIG. 1 is a flowchart of a chip-based temperature control method according to a first preferred embodiment of the present invention. The method is implemented by an electronic chip. The method is as shown in FIG. 1 and includes the following steps:
  • Step S101 Acquire a total thread of the multi-core chip
  • Step S102 Obtain a number of threads of each kernel according to an allocation policy.
  • Step S103 Calculate the temperature of each core according to the number of threads to perform temperature control.
  • the technical solution provided by the specific embodiment of the present invention acquires the total thread of the multi-core chip, learns the number of threads of each core according to the allocation strategy, calculates the temperature of each core according to the number of threads, and therefore has the function of implementing chip-based temperature control and management. advantage.
  • the implementation method of the foregoing step S102 may be specifically:
  • the number of threads per core is allocated according to the load balancing allocation policy.
  • the implementation method of the foregoing step S103 may be specifically:
  • the number of threads per core is allocated based on the number-averaged allocation policy.
  • FIG. 2 is a chip-based temperature control system according to a second preferred embodiment of the present invention.
  • the system includes:
  • the obtaining unit 201 is configured to acquire a total thread of the multi-core chip
  • the allocating unit 202 is configured to learn the number of threads of each kernel according to the allocation policy
  • the calculation control unit 203 is configured to calculate the temperature of each core according to the number of threads for temperature control.
  • the technical solution provided by the specific embodiment of the present invention acquires the total thread of the multi-core chip, learns the number of threads of each core according to the allocation strategy, calculates the temperature of each core according to the number of threads, and therefore has the function of implementing chip-based temperature control and management. advantage.
  • the foregoing allocating unit 202 is specifically configured to allocate a number of threads of each core according to a load balancing allocation policy.
  • the foregoing allocating unit 202 is specifically configured to allocate, according to the number-averaged allocation policy, the number of threads of each core.
  • Computer readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another.
  • a storage medium may be any available media that can be accessed by a computer.
  • the computer readable medium may include random access memory (Random) Access Memory, RAM), Read-Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (Electrically Erasable Programmable Read-Only Memory, EEPROM), Compact Disc Read-Only Memory, CD-ROM, or other optical disc storage, magnetic storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also. Any connection may suitably be a computer readable medium.
  • a disk and a disc include a compact disc (CD), a laser disc, a compact disc, a digital versatile disc (DVD), a floppy disk, and a Blu-ray disc, wherein the disc is usually magnetically copied, and the disc is The laser is used to optically replicate the data. Combinations of the above should also be included within the scope of the computer readable media.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Control Of Temperature (AREA)

Abstract

L'invention concerne un procédé de régulation de température et un système sur puce associé. Le procédé comprend les étapes suivantes : l'obtention du nombre total de fils d'une puce à noyaux multiples (S101) ; l'apprentissage, selon une stratégie d'attribution, d'une quantité de fils de chaque noyau (S102) ; et le calcul, en fonction de la quantité de fils, de la température de chaque noyau (S103). La solution technique selon l'invention permet avantageusement la gestion et la régulation de température.
PCT/CN2016/091785 2016-07-26 2016-07-26 Procédé de régulation de température et système sur puce associé WO2018018424A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2016/091785 WO2018018424A1 (fr) 2016-07-26 2016-07-26 Procédé de régulation de température et système sur puce associé

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2016/091785 WO2018018424A1 (fr) 2016-07-26 2016-07-26 Procédé de régulation de température et système sur puce associé

Publications (1)

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WO2018018424A1 true WO2018018424A1 (fr) 2018-02-01

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WO (1) WO2018018424A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112485645A (zh) * 2020-11-30 2021-03-12 海光信息技术股份有限公司 芯片测试温度控制方法、控制***、温控板卡及测试***
CN112514340A (zh) * 2018-08-03 2021-03-16 中兴通讯股份有限公司 多结构参考信号

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040128663A1 (en) * 2002-12-31 2004-07-01 Efraim Rotem Method and apparatus for thermally managed resource allocation
CN1894668A (zh) * 2004-03-29 2007-01-10 索尼计算机娱乐公司 处理器、多处理器***、处理器***、信息处理装置和温度控制方法
CN101076770A (zh) * 2004-09-28 2007-11-21 英特尔公司 根据可用并行数目改变每条指令能量的方法和设备
CN101256515A (zh) * 2008-03-11 2008-09-03 浙江大学 多核处理器操作***负载均衡的实现方法
CN101916209A (zh) * 2010-08-06 2010-12-15 华东交通大学 一种多核处理器集群任务资源分配方法
CN106294063A (zh) * 2016-07-26 2017-01-04 张升泽 基于芯片的温度控制方法及***

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040128663A1 (en) * 2002-12-31 2004-07-01 Efraim Rotem Method and apparatus for thermally managed resource allocation
CN1894668A (zh) * 2004-03-29 2007-01-10 索尼计算机娱乐公司 处理器、多处理器***、处理器***、信息处理装置和温度控制方法
CN101076770A (zh) * 2004-09-28 2007-11-21 英特尔公司 根据可用并行数目改变每条指令能量的方法和设备
CN101256515A (zh) * 2008-03-11 2008-09-03 浙江大学 多核处理器操作***负载均衡的实现方法
CN101916209A (zh) * 2010-08-06 2010-12-15 华东交通大学 一种多核处理器集群任务资源分配方法
CN106294063A (zh) * 2016-07-26 2017-01-04 张升泽 基于芯片的温度控制方法及***

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112514340A (zh) * 2018-08-03 2021-03-16 中兴通讯股份有限公司 多结构参考信号
CN112514340B (zh) * 2018-08-03 2022-06-17 中兴通讯股份有限公司 多结构参考信号
CN112485645A (zh) * 2020-11-30 2021-03-12 海光信息技术股份有限公司 芯片测试温度控制方法、控制***、温控板卡及测试***

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