WO2018014625A1 - 一种像素电路及其驱动方法、显示面板和显示装置 - Google Patents

一种像素电路及其驱动方法、显示面板和显示装置 Download PDF

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Publication number
WO2018014625A1
WO2018014625A1 PCT/CN2017/083059 CN2017083059W WO2018014625A1 WO 2018014625 A1 WO2018014625 A1 WO 2018014625A1 CN 2017083059 W CN2017083059 W CN 2017083059W WO 2018014625 A1 WO2018014625 A1 WO 2018014625A1
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Prior art keywords
control
module
signal
switching transistor
data
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PCT/CN2017/083059
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English (en)
French (fr)
Inventor
王雨
杨飞
吴月
李全虎
孟松
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京东方科技集团股份有限公司
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Priority to US15/565,907 priority Critical patent/US10283072B2/en
Publication of WO2018014625A1 publication Critical patent/WO2018014625A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/38—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using electrochromic devices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/15—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on an electrochromic effect
    • G02F1/163—Operation of electrochromic cells, e.g. electrodeposition cells; Circuit arrangements therefor
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/15—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on an electrochromic effect
    • G02F1/163—Operation of electrochromic cells, e.g. electrodeposition cells; Circuit arrangements therefor
    • G02F2001/1635—Operation of electrochromic cells, e.g. electrodeposition cells; Circuit arrangements therefor the pixel comprises active switching elements, e.g. TFT
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G09G2300/0866—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes by means of changes in the pixel supply voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0275—Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current

Definitions

  • the supply voltage signal remains low during the color development phase and remains high during the fade phase.
  • the data signal and the first control signal are converted to an on potential at a time when the color development phase and the fade phase begin.
  • control module includes a second switching transistor.
  • the gate of the second switching transistor is a control end of the control module, the source is an input end of the control module, and the drain is an output end of the control module.
  • a display device comprising the above display panel.
  • the conduction delay of the control module can be changed in the power supply voltage signal, thereby effectively removing the interference of the power supply voltage signal, avoiding display fluctuation caused by the change of the power supply voltage signal, thereby improving the display effect.
  • FIG. 1 is a schematic structural diagram of a pixel circuit according to an embodiment
  • FIG. 5 is a circuit timing diagram of the pixel circuit shown in FIG. 3;
  • FIG. 6 is a schematic flow chart of a driving method of a pixel circuit according to an embodiment.
  • a pixel circuit may include a data writing module 1, a control module 2, a driving module 3, and an electrochromic device 4.
  • the input terminal of the driving module 3 is connected to the power supply voltage signal terminal VDD to receive a power supply voltage signal.
  • the driving module 3 may be configured to drive the electrochromic device 4 to perform color development or fading according to a power supply voltage signal output from the power supply voltage signal terminal VDD under the control of the data signal.
  • the control end of the control module 2 is connected to the second control signal terminal G2 to receive the second control signal, the input end of the control module 2 is connected to the output end of the driving module 3, and the output end of the control module 2 and one end of the electrochromic device 4 Connected, the other end of the electrochromic device 4 is grounded to GND.
  • the control module 2 can be configured to control the conduction of the drive module 3 and the electrochromic device 4 based on a second control signal output by the second control signal terminal G2.
  • the control module controls the conduction to delay the conduction from a change in a power supply voltage signal.
  • the pixel circuit includes a data writing module, a control module, a driving module, and an electrochromic device.
  • the control end of the data writing module is connected to the first control signal end, the input end is connected to the data signal end, and the output end is connected to the control end of the driving module.
  • the data writing module may be configured to provide the data signal output by the data signal end to the control end of the driving module under the control of the first control signal outputted by the first control signal terminal.
  • the control end of the control module is connected to the second control signal end, the input end is connected to the output end of the drive module, the output end is connected to one end of the electrochromic device, and the other end of the electrochromic device is grounded.
  • the control module may be configured to control conduction of the driving module and the electrochromic device based on the second control signal output by the second control signal terminal.
  • the input of the drive module is connected to the power supply voltage signal terminal.
  • the driving module may be configured to drive the electrochromic device to perform color development or fading according to a power voltage signal output from the power voltage signal terminal under the control of the data signal.
  • the control module controls the conduction such that the conduction is delayed by a change in the supply voltage signal.
  • the delay is delayed by the change of the power supply voltage signal, that is, when the power supply voltage signal changes from low potential to high potential or from high potential to low potential, the control module is in an off state, so that the driving module and the electrochromic device are not turned on. In this way, the interference of the power supply voltage signal can be effectively removed, and the display fluctuation caused by the change of the power supply voltage signal can be avoided, thereby improving the display effect.
  • first control signal, the second control signal, and the data signal provided in the embodiments of the present disclosure may be pulse signals with high and low potential changes.
  • the power supply voltage signal provided in the embodiment of the present disclosure may also be a signal with a high and low potential change.
  • the display period may include a color development stage and a fade stage, and the power supply voltage signal respectively maintains corresponding potentials in the color development stage and the fade stage to achieve color development. And faded.
  • the supply voltage signal remains low during the color development phase and remains high during the fade phase. For example, during one display period, the supply voltage signal can remain low for half of the display period and remain high for the other half of the display period.
  • the data signal and the first control signal are converted to an on potential at a time when the color development phase and the fade phase begin.
  • the second control signal is changed after a predetermined time delay after the start of the color development phase and the fade phase, for example, to a turn-on potential.
  • the predetermined time is one half of a duration during which the first control signal remains at an on potential.
  • the first switching transistor T1 may be an N-type transistor. At this time, when the first control signal is high, the first switching transistor T1 is in an on state; When the first control signal is at a low potential, the first switching transistor T1 is in an off state.
  • the first switching transistor T1 may be a P-type transistor. At this time, when the first control signal is low, the first switching transistor T1 is in an on state; when the first control signal is in a high potential At this time, the first switching transistor T1 is in an off state.
  • the data signal outputted by the data signal terminal Data is transmitted to the control terminal of the driving module 3 through the first switching transistor T1, thereby controlling Whether the drive module 3 is turned on.
  • the above is only a specific structure of the data writing module in the pixel circuit.
  • the specific structure of the data writing module is not limited to the above structure provided by the embodiment of the present disclosure, and may be other structures known to those skilled in the art. , not limited here.
  • the control module 2 may include a second switching transistor T2.
  • the gate of the second switching transistor T2 is the control terminal of the control module 2, that is, the gate is connected to the second control signal terminal G2;
  • the source of the second switching transistor T2 is the input terminal of the control module 2, that is, the source and the driving module.
  • the output of the second switching transistor T2 is the output of the control module 2, that is, the drain is connected to one end of the electrochromic device 4.
  • the second switching transistor T2 may be an N-type transistor. At this time, when the second control signal is at a high potential, the second switching transistor T2 is in an on state; when the second control signal is at a low potential, the second switching transistor T2 is in an off state.
  • the second switching transistor T2 may be a P-type transistor. At this time, when the second control signal is at a low potential, the second switching transistor T2 is in an on state; when the second control signal is at a high potential, the second switching transistor T2 is in an off state.
  • the driving module 3 and the electrochromic device 4 can be turned on, and the driving signal output by the driving module can be passed through The second switching transistor T2 is transmitted to the electrochromic device 4.
  • control module in the pixel circuit.
  • specific structure of the control module is not limited to the above structure provided by the embodiment of the present disclosure, and may be other structures known to those skilled in the art. Make a limit.
  • the driving module 3 may include a third switching transistor T3 and a capacitor C.
  • the gate of the third switching transistor T3 is the control end of the driving module 3, that is, the gate and the data are written.
  • the output end of the module 1 (which may be the drain of the first switching transistor T1 described above) is connected; the source of the third switching transistor T3 drives the input end of the module 3, that is, the source is connected to the power supply voltage signal terminal VDD; the third switching transistor
  • the drain of T3 is the output terminal of the driving module 3, that is, the drain is connected to the input terminal of the control module 2 (which may be the source of the second switching transistor T2 described above). Both ends of the capacitor C may be electrically connected to the gate and the source of the third switching transistor T3, respectively.
  • the third switching transistor T3 may be an N-type transistor. At this time, when the output terminal of the data writing module 1 outputs a high potential, the third switching transistor T3 is in an on state; when the output terminal of the data writing module 1 outputs a low potential, the third switching transistor T3 is in an off state.
  • the third switching transistor T3 may be a P-type transistor. At this time, when the output terminal of the data writing module 1 outputs a low potential, the third switching transistor T3 is in an on state; when the output terminal of the data writing module 1 outputs a high potential, the third switching transistor T3 is in an off state.
  • the data writing module 1 supplies the data signal output by the data signal terminal Data to the control terminal of the driving module 3, and the voltage of the data signal should be greater than the threshold voltage Vth, so the third The switching transistor T3 is turned on, and thus the power supply voltage signal output from the power supply voltage signal terminal VDD is transmitted to the source of the second switching transistor T2.
  • the electrochromic device 4 can be driven to perform color development or fading according to the power supply voltage signal output from the power supply voltage signal terminal VDD.
  • the above is only a specific structure of the driving module in the pixel circuit.
  • the specific structure of the driving module is not limited to the above-mentioned structure provided by the embodiment of the present disclosure, and may be other structures known to those skilled in the art. Make a limit.
  • the first switching transistor, the second switching transistor, and the third switching transistor may be thin film transistors (TFTs) or metal oxide semiconductor field effect transistors (MOS, Metal). Oxide Scmiconductor), not limited here.
  • TFTs thin film transistors
  • MOS metal oxide semiconductor field effect transistors
  • Oxide Scmiconductor Oxide Scmiconductor
  • the first switching transistor, the second switching transistor, and the third switching transistor may be N-type transistors or both P-type transistors, for the above transistors
  • the type may be determined according to actual conditions, and is not limited herein.
  • the operation of the pixel circuit shown in FIG. 2 will be described as an example.
  • all of the switching transistors are N-type transistors, and each of the N-type transistors is turned on under a high potential and turned off at a low potential.
  • An exemplary timing diagram of the various input signals of the pixel circuit shown in FIG. 2 is shown in FIG.
  • the two stages P1 and P2 in the input timing chart shown in FIG. 4 are selected as an example for detailed description. In the following description, 1 indicates a high potential, and 0 indicates a low potential.
  • the data signal is input to the gate of the third switching transistor T3 through the turned-on first switching transistor T1, so the third switching transistor T3 is turned on, and the power supply voltage signal is input to the drain of the third switching transistor T3.
  • the capacitor C In this process, the capacitor C is always in a state of charge, and the voltage difference across the capacitor C is equal to the Vgs of the third switching transistor.
  • the second control signal is delayed from a low potential to a high potential by a predetermined time.
  • the preset time may be that the first control signal is half of the high potential time, in other words, the first control signal remains at half the duration of the on potential.
  • the first switching transistor T1, the second switching transistor T2, and the third switching transistor T3 are all in an on state, so that the power supply voltage signal terminal VDD and the electrochromic device 4 are in an on state, and can be based on the power voltage signal.
  • the electrochromic device 4 is driven to develop color. After the pulse time elapses, the first control signal and the data signal turn to a low potential, and then the second control signal also goes to a low potential.
  • the power supply voltage signal changes from low to high.
  • the first control signal outputted by the first control signal terminal G1 also changes from a low potential to a high potential
  • the data signal outputted by the data signal terminal Data also changes from a low potential to a high potential
  • the first switching transistor T1 is in an on state
  • the second switching transistor T2 is in an off state.
  • the data signal is input to the gate of the third switching transistor T3 through the turned-on first switching transistor T1, so the third switching transistor T3 is turned on, and the power supply voltage signal is input to the drain of the third switching transistor T3.
  • the Vgs value of the third switching transistor changes when the power supply voltage signal changes from a low potential to a high potential, but since the second switching transistor T2 is in an off state, the change is not transmitted to the electrochromic device, and thus can be effective.
  • the interference of the power supply voltage signal is removed, and the display fluctuation caused by the change of the power supply voltage signal is avoided, thereby improving the display effect.
  • the first switching transistor T1, the second switching transistor T2, and the third switching transistor T3 are all in an on state, so that the power supply voltage signal terminal VDD and the electrochromic device 4 are in an on state, and can be based on the power voltage signal.
  • the electrochromic device 4 is driven to discolor. After the pulse time elapses, the first control signal and the data signal turn to a low potential, and then the second control signal also goes to a low potential.
  • FIG. 3 An exemplary timing diagram of the various input signals of the pixel circuit shown in FIG. 2 is shown in FIG.
  • the two stages P1 and P2 in the input timing chart shown in FIG. 5 are selected as an example for detailed description. In the following description, 1 indicates a high potential, and 0 indicates a low potential.
  • the data signal is input to the gate of the third switching transistor T3 through the turned-on first switching transistor T1, so the third switching transistor T3 is turned on, and the power supply voltage signal is input to the drain of the third switching transistor T3. pole.
  • the capacitor C In this process, the capacitor C is always in a state of charge, and the voltage difference across the capacitor C is equal to the Vgs of the third switching transistor.
  • the second control signal is delayed from a high potential to a low potential by a predetermined time.
  • the preset time may be that the first control signal is half of the low potential time, in other words, the first control signal remains at half the duration of the on potential.
  • the first switching transistor T1, the second switching transistor T2, and the third switching transistor T3 are all in an on state, so that the power supply voltage signal terminal VDD and the electrochromic device 4 are in an on state, and can be based on the power voltage signal.
  • the electrochromic device 4 is driven to develop color. After the pulse time elapses, the first control signal and the data signal turn to a high potential, and then the second control signal also goes to a high potential.
  • the first control signal outputted by the first control signal terminal G1 also changes from the high potential to the low potential
  • the data signal terminal Data output The data signal also changes from a high potential to a low potential
  • the first switching transistor T1 is in an on state
  • the second switching transistor T2 is in an off state.
  • the data signal is input to the gate of the third switching transistor T3 through the turned-on first switching transistor T1, so the third switching transistor T3 is turned on, and the power supply voltage signal is input to the drain of the third switching transistor T3.
  • the Vgs value of the third switching transistor changes when the power supply voltage signal changes from a low potential to a high potential, but since the second switching transistor T2 is in an off state, the change is not transmitted to the electrochromic device, and thus can be effective.
  • the interference of the power supply voltage signal is removed, and the display fluctuation caused by the change of the power supply voltage signal is avoided, thereby improving the display effect.
  • the first switching transistor T1, the second switching transistor T2, and the third switching transistor T3 are all in an on state, so that the power supply voltage signal terminal VDD and the electrochromic device 4 are in an on state, and can be based on the power voltage signal.
  • the electrochromic device 4 is driven to discolor.
  • the first control signal and the data signal turn to a high potential, and then the second control signal also goes to a high potential.
  • the driving method includes:
  • the data writing module provides the data signal outputted by the data signal end to the control end of the driving module under the control of the first control signal outputted by the first control signal end; the control module controls the data signal And supplying a power voltage signal outputted by the power voltage signal terminal to the input end of the control module for driving the electrochromic device for color development; and the control module controlling the driving module and the power based on the second control signal output by the second control signal terminal
  • the color changing device is turned on, and the control module controls the conduction to delay the conduction from a change in the power supply voltage signal.
  • the data writing module provides the data signal outputted by the data signal end to the control end of the driving module under the control of the first control signal outputted by the first control signal end; the driving module is under the control of the data signal Providing a power voltage signal outputted by the power voltage signal terminal to the input end of the control module for driving the electrochromic device to perform fading; and the control module controlling the driving module and the electrochromic based on the second control signal outputted by the second control signal terminal
  • the device is turned on, and the control module controls the turn-on such that the turn-on is delayed by a change in the power supply voltage signal.
  • the driving method of the above pixel circuit can effectively remove the interference of the power supply voltage signal, avoid display fluctuation caused by the change of the power supply voltage signal, and thereby improve the display effect.
  • a display panel including any of the above-described pixel circuits provided by the present disclosure is also provided. Since the principle of solving the problem in the display panel is similar to that of the foregoing pixel circuit, the implementation of the pixel circuit in the display panel can be referred to the implementation of the pixel circuit in the foregoing example, and the repeated description is omitted.
  • the display device includes the above-mentioned display panel provided by the present disclosure.
  • the display device may include any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the display device may also include other components, but since they do not relate to the core of the present invention, they are not described herein. Those of ordinary skill in the art will recognize that these other groups The components are not to be construed as limiting the invention.
  • the pixel circuit can include a data writing module, a control module, a driving module, and an electrochromic device.
  • the control end of the data writing module is connected to the first control signal end, the input end is connected to the data signal end, and the output end is connected to the control end of the driving module.
  • the data writing module may be configured to provide the data signal output by the data signal end to the control end of the driving module under the control of the first control signal outputted by the first control signal terminal.
  • the control end of the control module is connected to the second control signal end, the input end is connected to the output end of the drive module, the output end is connected to one end of the electrochromic device, and the other end of the electrochromic device is grounded.
  • the control module may be configured to control conduction of the driving module and the electrochromic device based on the second control signal output by the second control signal terminal.
  • the input of the drive module is connected to the power supply voltage signal terminal.
  • the driving module may be configured to drive the electrochromic device to perform color development or fading according to a power voltage signal output from the power voltage signal terminal under the control of the data signal.
  • the control module controls the conduction such that the conduction is delayed by a change in the supply voltage signal.
  • the conduction delay of the control module can be changed in the power supply voltage signal, the interference of the power supply voltage signal can be effectively removed, the display fluctuation caused by the change of the power supply voltage signal can be avoided, and the display effect can be improved.
  • the foregoing embodiment is only exemplified by the division of the foregoing functional modules.
  • the foregoing functions may be allocated to different functional modules as needed.
  • the internal structure of the device can be divided into different functional modules to perform all or part of the functions described above.
  • the function of one module described above may be completed by multiple modules, and the functions of the above multiple modules may also be integrated into one module.

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  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

一种像素电路及其驱动方法、显示面板和显示装置。像素电路包括：数据写入模块（1）、驱动模块（3）、控制模块（2）和电致变色器件（4）。数据写入模块（1）在第一控制信号的控制下，将数据信号端（Data）输出的数据信号提供给驱动模块（3）的控制端。驱动模块（3）在数据信号的控制下，根据电源电压信号端（VDD）输出的电源电压信号来驱动电致变色器件（4）进行显色或褪色。控制模块（2）基于第二控制信号来控制驱动模块（3）与电致变色器件（4）的导通，控制模块（2）控制该导通从而使该导通延迟于电源电压信号的变化。通过各模块的相互配合，可以实现控制模块（2）的导通延迟于电源电压信号的变化，从而可以有效去除电源电压信号的干扰，避免因电源电压信号变化造成的显示波动，进而可以提高显示效果。

Description

一种像素电路及其驱动方法、显示面板和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种像素电路及其驱动方法、显示面板和显示装置。
背景技术
随着显示技术的快速发展，显示设备的应用越来越广泛，如手机、笔记本电脑、电视、车载显示以及超市中用的电子标签显示等。然而上述显示设备一般均采用液晶显示(Liquid Crystal Display，LCD)，而液晶显示时需要使用背光源，背光源的使用使得显示设备在显示过程中的功耗较高。为了降低显示过程中的功耗，电致变色显示(ElectroChromic Display，ECD)被引入并且得到了广泛的应用。电致变色(英文：Electrochromism，简称EC)是指某些材料在外电场作用下，在低透过率的致色状态和高透过率的消色状态之间产生可逆变化的一种特殊现象。
目前，基于EC技术制造的电致变色器件(英文：Electrochromism Device，简称ECD)已被广泛应用于智能大厦的采光控制、大面积室外数字及图形显示、汽车的反射率可调后视镜、飞机变色窗等领域。常规的ECD显示面板包括若干由EC材料形成的像素单元和为像素单元提供驱动电压的ECD像素电路。每个像素单元在驱动电压作用下显示颜色。显示颜色的过程可以是显色过程，也可以是褪色过程。在显色过程中，像素单元的透过率逐渐降低，从而显示的颜色逐渐加深；反之，在褪色过程中，像素单元的透过率逐渐增大，从而显示的颜色逐渐变浅。通过调节像素单元在显色和褪色之间转换，使得ECD显示面板呈现丰富的显示效果。
但是，ECD像素电路具有的电压特性和电容特性，决定了利用常规的显示驱动方法去驱动ECD时，会造成面板显示受到像素电路中电源电压信号变化的影响，造成显示效果变差的问题。
发明内容
因此，期望提供一种像素电路及其驱动方法、显示面板和显示装 置，可以有效去除电源电压信号的干扰，避免因电源电压信号变化造成的显示波动，进而能够提高显示效果。
根据一个方面提供了一种像素电路。该像素电路包括：数据写入模块、控制模块、驱动模块和电致变色器件。所述数据写入模块的控制端与第一控制信号端连接以便接收第一控制信号，输入端与数据信号端连接以便接收数据信号，输出端与所述驱动模块的控制端连接。所述数据写入模块被配置用于在所述第一控制信号的控制下将所述数据信号提供给所述驱动模块的控制端。所述驱动模块的输入端与电源电压信号端连接以便接收电源电压信号，所述驱动模块被配置用于在所述数据信号的控制下，根据所述电源电压信号来驱动所述电致变色器件进行显色或褪色。所述控制模块的控制端与第二控制信号端连接以便接收第二控制信号，输入端与所述驱动模块的输出端连接，输出端与所述电致变色器件的一端连接。所述电致变色器件的另一端接地。所述控制模块被配置用于基于所述第二控制信号来控制所述驱动模块与所述电致变色器件的导通，所述控制模块控制所述导通从而使该导通延迟于所述电源电压信号的变化。在一个实施例中，所述像素电路的显示周期包括显色阶段和褪色阶段，所述电源电压信号在所述显色阶段和褪色阶段内分别保持相应的电位以实现显色和褪色。
在一个实施例中，所述电源电压信号在所述显色阶段内保持低电位，在所述褪色阶段内保持高电位。
在一个实施例中，所述数据信号和所述第一控制信号在所述显色阶段和褪色阶段开始的时刻转换为接通电位。
在一个实施例中，所述第二控制信号在所述显色阶段和褪色阶段开始之后延迟预定时间后转换为接通电位。
在一个实施例中，所述预定时间为所述第一控制信号保持在接通电位的持续时间的一半。
在一个实施例中，所述数据写入模块包括第一开关晶体管。所述第一开关晶体管的栅极为所述数据写入模块的控制端，源极为所述数据写入模块的输入端，漏极为所述数据写入模块的输出端。
在一个实施例中，所述控制模块包括第二开关晶体管。所述第二开关晶体管的栅极为所述控制模块的控制端，源极为所述控制模块的输入端，漏极为所述控制模块的输出端。
在一个实施例中，所述驱动模块包括第三开关晶体管和电容。所述第三开关晶体管的栅极为所述驱动模块的控制端，源极为所述驱动模块的输入端，漏极为所述驱动模块的输出端。所述电容的两端分别电连接至所述第三开关晶体管的栅极与源极。
在一个实施例中，所述第一开关晶体管、第二开关晶体管和第三开关晶体管均为N型晶体管或均为P型晶体管。
根据另一个方面还提供了一种显示面板，包括如上所述的任何一种像素电路。
根据另一个方面还提供了一种显示装置，包括上述显示面板。
根据另一个方面还提供了如上所述的任何一种像素电路的驱动方法。该方法包括：在显色阶段，数据写入模块在第一控制信号端输出的第一控制信号的控制下，将数据信号端输出的数据信号提供给驱动模块的控制端；所述驱动模块在所述数据信号的控制下，向控制模块的输入端提供电源电压信号端输出的电源电压信号，用于驱动所述电致变色器件进行显色；控制模块基于第二控制信号端输出的第二控制信号来控制所述驱动模块与所述电致变色器件的导通，所述控制模块控制所述导通从而使该导通延迟于所述电源电压信号的变化；在褪色阶段，数据写入模块在第一控制信号端输出的第一控制信号的控制下，将数据信号端输出的数据信号提供给驱动模块的控制端；所述驱动模块在所述数据信号的控制下，向控制模块的输入端提供电源电压信号端输出的电源电压信号，用于驱动所述电致变色器件进行褪色；控制模块基于第二控制信号端输出的第二控制信号来控制所述驱动模块与所述电致变色器件的导通，所述控制模块控制所述导通从而使该导通延迟于所述电源电压信号的变化。
本公开的实施例可以实现如下有益效果中的至少一个有益效果和/或其它有益效果：
本公开的实施例提供上述像素电路及其驱动方法、显示面板和显示装置。像素电路包括：数据写入模块、驱动模块、控制模块和电致变色器件。数据写入模块的控制端与第一控制信号端连接以便接收第一控制信号，输入端与数据信号端连接以便接收数据信号，输出端与驱动模块的控制端连接。数据写入模块可以被配置用于在所述第一控制信号的控制下将数据信号端输出的数据信号提供给驱动模块的控制 端。驱动模块的输入端与电源电压信号端连接以便接收电源电压信号。驱动模块可被配置用于在数据信号的控制下，根据电源电压信号端输出的电源电压信号来驱动电致变色器件进行显色或褪色。控制模块的控制端与第二控制信号端连接以便接收第二控制信号，输入端与驱动模块的输出端连接，输出端与电致变色器件的一端连接，电致变色器件的另一端接地。控制模块可被配置用于基于所述第二控制信号来控制驱动模块与电致变色器件的导通，控制模块控制所述导通从而使该导通延迟于电源电压信号的变化。通过上述各模块的相互配合，可以实现控制模块的导通延迟于电源电压信号的变化，从而可以有效去除电源电压信号的干扰，避免因电源电压信号变化造成的显示波动，进而提高了显示效果。
附图说明
为了更清楚地说明实施例的技术方案，本公开提供了下列附图以便在实施例描述时使用。应当意识到，下面描述中的附图仅仅涉及一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图，所述其它的附图也在本发明的范围内。
图1为根据一个实施例提供的像素电路的结构示意图；
图2为本根据一个实施例提供的像素电路的具体电路结构示意图；
图3为根据另一个实施例提供的像素电路的具体电路结构示意图；
图4为图2所示的像素电路的电路时序示意图；
图5为图3所示的像素电路的电路时序示意图；
图6为根据一个实施例提供的像素电路的驱动方法的流程示意图。
具体实施方式
为了使本公开实施例的目的、技术方案和优点更加清楚，下面将结合附图对这些实施例作进一步地详细描述。显然，所描述的实施例仅仅是本发明的一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
下面结合附图，对本公开实施例提供的像素电路及其驱动方法、 显示面板和显示装置的示例性具体实施方式进行详细地说明。
根据一个方面提供了一种像素电路。如图1所示，像素电路可以包括数据写入模块1、控制模块2、驱动模块3和电致变色器件4。
数据写入模块1的控制端可以与第一控制信号端G1连接以便从中接收第一控制信号，数据写入模块1的输入端可以与数据信号端Data连接以便从中接收数据信号，数据写入模块1的输出端可以与驱动模块3的控制端连接。数据写入模块1可以被配置用于在第一控制信号端G1输出的第一控制信号的控制下将数据信号端Data输出的数据信号提供给驱动模块3的控制端。
驱动模块3的输入端与电源电压信号端VDD连接以便接收电源电压信号。驱动模块3可以被配置用于在数据信号的控制下，根据电源电压信号端VDD输出的电源电压信号来驱动电致变色器件4进行显色或褪色。
控制模块2的控制端与第二控制信号端G2连接以便接收第二控制信号，控制模块2的输入端与驱动模块3的输出端连接，控制模块2的输出端与电致变色器件4的一端连接，电致变色器件4的另一端接地GND。控制模块2可以被配置用于基于第二控制信号端G2输出的第二控制信号来控制驱动模块3与电致变色器件4的导通。所述控制模块控制所述导通从而使该导通延迟于电源电压信号的变化。
在一些实施例中，上述像素电路包括：数据写入模块、控制模块、驱动模块和电致变色器件。其中，数据写入模块的控制端与第一控制信号端连接，输入端与数据信号端连接，输出端与驱动模块的控制端连接。数据写入模块可以被配置用于在第一控制信号端输出的第一控制信号的控制下，将数据信号端输出的数据信号提供给驱动模块的控制端。控制模块的控制端与第二控制信号端连接，输入端与驱动模块的输出端连接，输出端与电致变色器件的一端连接，电致变色器件的另一端接地。控制模块可以被配置用于基于第二控制信号端输出的第二控制信号来控制驱动模块与电致变色器件的导通。驱动模块的输入端与电源电压信号端连接。驱动模块可以被配置用于在数据信号的控制下，根据电源电压信号端输出的电源电压信号来驱动电致变色器件进行显色或褪色。控制模块控制所述导通从而使该导通延迟于电源电压信号的变化。通过上述各模块的相互配合，可以实现控制模块的导 通延迟于电源电压信号的变化，即在电源电压信号由低电位变为高电位或由高电位变为低电位的时刻，控制模块处于截止状态，从而使得驱动模块与电致变色器件没有导通，这样就可以有效去除电源电压信号的干扰，避免因电源电压信号变化造成的显示波动，进而可以提高显示效果。
下面结合具体实施例进行详细说明。需要说明的是，本实施例是为了更好地解释本发明，但绝对不是限制本发明。
需要说明的是，本公开实施例中提供的第一控制信号、第二控制信号和数据信号均可以是高低电位变化的脉冲信号。本公开实施例中提供的电源电压信号也可以是高低电位变化的信号。
在一些具体实施例中，在上述像素电路中，所述显示周期可以包括显色阶段和褪色阶段，所述电源电压信号在所述显色阶段和褪色阶段内分别保持相应的电位以实现显色和褪色。在一个实施例中，所述电源电压信号在所述显色阶段内保持低电位，在所述褪色阶段内保持高电位。例如，在一个显示周期内，电源电压信号可以在一半显示周期内保持低电位，在另一半显示周期内保持高电位。在一个实施例中，所述数据信号和所述第一控制信号在所述显色阶段和褪色阶段开始的时刻转换为接通电位。例如，数据信号和第一控制信号在电源电压信号变化的同时变化，即电源电压信号由低电位变为高电位或由高电位变为低电位时，数据信号和第一控制信号也同时开始变化。
在一个实施例中，所述第二控制信号在所述显色阶段和褪色阶段开始之后延迟预定时间后才发生改变，例如转换为接通电位。在一个实施例中，所述预定时间为所述第一控制信号保持在接通电位的持续时间的一半。
在具体实施时，在本公开一些实施例提供的像素电路中，如图2和如图3所示，数据写入模块1可以包括第一开关晶体管T1。其中，第一开关晶体管T1的栅极为数据写入模块1的控制端，即栅极与第一控制信号端G1连接；第一开关晶体管T1的源极为数据写入模块1的输入端，即源极与数据信号端Data连接；第一开关晶体管T1的漏极为数据写入模块1的输出端，即漏极与驱动模块3的控制端连接。
具体地，如图2所示，第一开关晶体管T1可以为N型晶体管。此时，当第一控制信号为高电位时，第一开关晶体管T1为导通状态；当 第一控制信号为低电位时，第一开关晶体管T1为截止状态。或者，如图3所示，第一开关晶体管T1可以为P型晶体管，此时，当第一控制信号为低电位时，第一开关晶体管T1为导通状态；当第一控制信号为高电位时，第一开关晶体管T1为截止状态。
具体地，当第一开关晶体管T1在第一控制信号端G1的控制下处于导通状态时，数据信号端Data输出的数据信号通过第一开关晶体管T1传输至驱动模块3的控制端，从而控制驱动模块3是否导通。
以上仅是举例说明像素电路中数据写入模块的具体结构，在具体实施时，数据写入模块的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
在具体实施时，在本公开一些实施例提供的像素电路中，如图2和如图3所示，控制模块2可以包括第二开关晶体管T2。其中，第二开关晶体管T2的栅极为控制模块2的控制端，即栅极与第二控制信号端G2连接；第二开关晶体管T2的源极为控制模块2的输入端，即源极与驱动模块3的输出端连接；第二开关晶体管T2的漏极为控制模块2的输出端，即漏极与电致变色器件4的一端连接。
具体地，如图2所示，第二开关晶体管T2可以为N型晶体管。此时，当第二控制信号为高电位时，第二开关晶体管T2为导通状态；当第二控制信号为低电位时，第二开关晶体管T2为截止状态。或者，如图3所示，第二开关晶体管T2可以为P型晶体管。此时，当第二控制信号为低电位时，第二开关晶体管T2为导通状态；当第二控制信号为高电位时，第二开关晶体管T2为截止状态。
具体地，当第二开关晶体管T2在第二信号控制端G2的控制下处于导通状态时，可以将驱动模块3与电致变色器件4导通，进而可以将驱动模块输出的驱动信号通过第二开关晶体管T2传输给电致变色器件4。
以上仅是举例说明像素电路中控制模块的具体结构，在具体实施时，控制模块的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
在具体实施时，本公开一些实施例提供的像素电路中，如图2和如图3所示，驱动模块3可以包括第三开关晶体管T3和电容C。其中，第三开关晶体管T3的栅极为驱动模块3的控制端，即栅极与数据写入 模块1的输出端(可以是上述第一开关晶体管T1的漏极)连接；第三开关晶体管T3的源极为驱动模块3的输入端，即源极与电源电压信号端VDD连接；第三开关晶体管T3的漏极为驱动模块3的输出端，即漏极与控制模块2的输入端(可以是上述第二开关晶体管T2的源极)连接。电容C的两端可以分别电连接至第三开关晶体管T3的栅极与源极。
具体地，如图2所示，第三开关晶体管T3可以为N型晶体管。此时，当数据写入模块1的输出端输出高电位时，第三开关晶体管T3为导通状态；当数据写入模块1的输出端输出低电位时，第三开关晶体管T3为截止状态。或者，如图3所示，第三开关晶体管T3可以为P型晶体管。此时，当数据写入模块1的输出端输出低电位时，第三开关晶体管T3为导通状态；当数据写入模块1的输出端输出高电位时，第三开关晶体管T3为截止状态。
具体地，当第一开关晶体管T1导通时，数据写入模块1将数据信号端Data输出的数据信号提供给驱动模块3的控制端，且数据信号的电压应大于阈值电压Vth，所以第三开关晶体管T3导通，因而将电源电压信号端VDD输出的电源电压信号传输给第二开关晶体管T2的源极。当第二开关晶体管T2导通时，就可以根据电源电压信号端VDD输出的电源电压信号来驱动电致变色器件4进行显色或褪色。
以上仅是举例说明像素电路中驱动模块的具体结构，在具体实施时，驱动模块的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
需要说明的是，在一些实施例中第一开关晶体管、第二开关晶体管和第三开关晶体管可以是薄膜晶体管(TFT，Thin Film Transistor)，也可以是金属氧化物半导体场效应管(MOS，Metal Oxide Scmiconductor)，在此不做限定。在具体实施中，这些开关晶体管的源极和漏极根据晶体管类型以及输入信号的不同，其功能可以互换，在此不做具体区分。
在具体实施时，为了简化制作工艺，在一些实施例提供的像素电路中，第一开关晶体管、第二开关晶体管和第三开关晶体管可以均为N型晶体管或均为P型晶体管，对于以上晶体管的种类可以根据实际情况而定，在此不作限定。
下面分别以图2和图3所示的像素电路为例对描述一些实施例提供的像素电路的工作过程。
首先，以图2所示的像素电路的结构为例对其工作过程加以描述。在图2所示的像素电路中，所有开关晶体管均为N型晶体管，各N型晶体管在高电位作用下导通，在低电位作用下截止。图2所示像素电路的各输入信号的示例性时序图在图4中示出。下面，选用图4所示的输入时序图中的P1和P2这两个阶段为例进行详细描述。下述描述中以1表示高电位，0表示低电位。
在P1阶段(即显色阶段)：电源电压信号端VDD输出的电源电压信号保持低电位，即VDD＝0。
当第一控制信号端G1输出的第一控制信号为高电位，数据信号端Data输出的数据信号为高电位，第二控制信号端G2输出的第二控制信号为低电位时，即G1＝1，Data＝1，G2＝0时，第一开关晶体管T1处于导通状态，第二开关晶体管T2处于截止状态。此时，数据信号通过导通的第一开关晶体管T1输入给第三开关晶体管T3的栅极，因此第三开关晶体管T3导通，将电源电压信号输入至第三开关晶体管T3的漏极。此过程电容C一直处于充电状态，电容C两端的电压差等于第三开关晶体管的Vgs。
由于控制模块的导通要延迟于电源电压的变化，因此第二控制信号由低电位变为高电位应延迟一预设时间。在一个实施例中，预设时间可以为第一控制信号为高电位时间的一半，换言之，为所述第一控制信号保持在接通电位的持续时间的一半。
在延迟所述预设时间后，第二控制信号由低电位变为高电位，第一控制信号和数据信号仍保持高电位，即G1＝1，Data＝1，G2＝1。此时第一开关晶体管T1、第二开关晶体管T2、第三开关晶体管T3均处于导通状态，因此电源电压信号端VDD与电致变色器件4之间处于导通状态，可以根据电源电压信号来驱动电致变色器件4进行显色。在脉冲时间过后第一控制信号和数据信号转为低电位，随后，第二控制信号也转为低电位。
在P2阶段(即褪色阶段)：电源电压信号端VDD输出的电源电压信号保持高电位，即VDD＝1。
在P1阶段变为P2阶段时，即在电源电压信号由低电位转为高电 位时，第一控制信号端G1输出的第一控制信号也由低电位转为高电位，数据信号端Data输出的数据信号也由低电位转为高电位，而第二控制信号端G2输出的第二控制信号保持低电位，即G1＝1，Data＝1，G2＝0。此时，第一开关晶体管T1处于导通状态，第二开关晶体管T2处于截止状态。此时，数据信号通过导通的第一开关晶体管T1输入给第三开关晶体管T3的栅极，因此第三开关晶体管T3导通，将电源电压信号输入至第三开关晶体管T3的漏极，此过程在电源电压信号由低电位转为高电位时，第三开关晶体管的Vgs值会发生变化，但是由于第二开关晶体管T2处于截止状态，此变化不会传输至电致变色器件，因此可以有效去除电源电压信号的干扰，避免了因电源电压信号变化造成的显示波动，进而提高了显示效果。
在延迟预设时间后，第二控制信号由低电位变为高电位，第一控制信号和数据信号仍保持高电位，即G1＝1，Data＝1，G2＝1。此时第一开关晶体管T1、第二开关晶体管T2、第三开关晶体管T3均处于导通状态，因此电源电压信号端VDD与电致变色器件4之间处于导通状态，可以根据电源电压信号来驱动电致变色器件4进行褪色。在脉冲时间过后第一控制信号和数据信号转为低电位，随后，第二控制信号也转为低电位。
接下来以图3所示的像素电路的结构为例对其工作过程加以描述。在图3所示的像素电路中，所有开关晶体管均为P型晶体管，各P型晶体管在低电位作用下导通，在高电位作用下截止。图2所示像素电路的各输入信号的示例性时序图在图5示出。下面，选用图5所示的输入时序图中的P1和P2这两个阶段为例进行详细描述。下述描述中以1表示高电位，0表示低电位。
在P1阶段(即显色阶段)：电源电压信号端VDD输出的电源电压信号保持低电位，即VDD＝0。
当第一控制信号端G1输出的第一控制信号为低电位，数据信号端Data输出的数据信号为低电位，第二控制信号端G2输出的第二控制信号为高电位时，即G1＝0，Data＝0，G2＝1时，第一开关晶体管T1处于导通状态，第二开关晶体管T2处于截止状态。此时，数据信号通过导通的第一开关晶体管T1输入给第三开关晶体管T3的栅极，因此第三开关晶体管T3导通，将电源电压信号输入至第三开关晶体管T3的漏 极。此过程电容C一直处于充电状态，电容C两端的电压差等于第三开关晶体管的Vgs。
由于控制模块的导通要延迟于电源电压的变化，因此第二控制信号由高电位变为低电位应延迟一预设时间。在一个实施例中，预设时间可以为第一控制信号为低电位时间的一半，换言之，为所述第一控制信号保持在接通电位的持续时间的一半。
在延迟所述预设时间后，第二控制信号由高电位变为低电位，第一控制信号和数据信号仍保持低电位，即G1＝0，Data＝0，G2＝0。此时第一开关晶体管T1、第二开关晶体管T2、第三开关晶体管T3均处于导通状态，因此电源电压信号端VDD与电致变色器件4之间处于导通状态，可以根据电源电压信号来驱动电致变色器件4进行显色。在脉冲时间过后第一控制信号和数据信号转为高电位，随后，第二控制信号也转为高电位。
在P2阶段(即褪色阶段)：电源电压信号端VDD输出的电源电压信号保持高电位，即VDD＝1。
在P1阶段变为P2阶段时，即在电源电压信号由低电位转为高电位时，第一控制信号端G1输出的第一控制信号也由高电位转为低电位，数据信号端Data输出的数据信号也由高电位转为低电位，而第二控制信号端G2输出的第二控制信号保持高电位，即G1＝0，Data＝0，G2＝1。此时，第一开关晶体管T1处于导通状态，第二开关晶体管T2处于截止状态。此时，数据信号通过导通的第一开关晶体管T1输入给第三开关晶体管T3的栅极，因此第三开关晶体管T3导通，将电源电压信号输入至第三开关晶体管T3的漏极，此过程在电源电压信号由低电位转为高电位时，第三开关晶体管的Vgs值会发生变化，但是由于第二开关晶体管T2处于截止状态，此变化不会传输至电致变色器件，因此可以有效去除电源电压信号的干扰，避免了因电源电压信号变化造成的显示波动，进而提高了显示效果。
在延迟预设时间后，第二控制信号由高电位变为低电位时，第一控制信号和数据信号仍保持低电位，即G1＝0，Data＝0，G2＝0。此时第一开关晶体管T1、第二开关晶体管T2、第三开关晶体管T3均处于导通状态，因此电源电压信号端VDD与电致变色器件4之间处于导通状态，可以根据电源电压信号来驱动电致变色器件4进行褪色。在脉冲 时间过后第一控制信号和数据信号转为高电位，随后，第二控制信号也转为高电位。
根据本公开的另一方面还提供了一种上述任一种像素电路的驱动方法。如图6所示，所述驱动方法包括：
S601、在显色阶段，数据写入模块在第一控制信号端输出的第一控制信号的控制下，将数据信号端输出的数据信号提供给驱动模块的控制端；驱动模块在数据信号的控制下，向控制模块的输入端提供电源电压信号端输出的电源电压信号，用于驱动电致变色器件进行显色；控制模块基于第二控制信号端输出的第二控制信号来控制驱动模块与电致变色器件的导通，控制模块控制所述导通从而使该导通延迟于电源电压信号的变化。
S602、在褪色阶段，数据写入模块在第一控制信号端输出的第一控制信号的控制下，将数据信号端输出的数据信号提供给驱动模块的控制端；驱动模块在数据信号的控制下，向控制模块的输入端提供电源电压信号端输出的电源电压信号，用于驱动电致变色器件进行褪色；控制模块基于第二控制信号端输出的第二控制信号来控制驱动模块与电致变色器件的导通，控制模块控制所述导通从而使该导通延迟于电源电压信号的变化。
上述像素电路的驱动方法可以有效去除电源电压信号的干扰，避免因电源电压信号变化造成的显示波动，进而可以提高显示效果。
基于同一公开构思，根据本公开的另一方面还提供了一种显示面板，该显示面板包括本公开提供的上述任一种像素电路。由于该显示面板解决问题的原理与前述一种像素电路相似，因此该显示面板中的像素电路的实施可以参见前述实例中像素电路的实施，重复之处不再赘述。
基于同一公开构思，根据本公开的另一方面还提供了一种显示装置，该显示装置包括本公开提供的上述显示面板，其具体实施可参见上述显示面板的描述，相同之处不再赘述。该显示装置可以包括：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。本领域的普通技术人员能够理解，该显示装置还可以包括其它组成部分，但是由于它们不涉及本发明的核心，因此在此不做赘述。本领域的普通技术人员知道，这些其它组 成部分不应作为对本发明的限制。该显示装置的实施可以参见上述像素电路的实施例，重复之处不再赘述。
本公开提供了上述像素电路及其驱动方法、显示面板和显示装置。在一些实施例中，所述像素电路可以包括：数据写入模块、控制模块、驱动模块和电致变色器件。其中，数据写入模块的控制端与第一控制信号端连接，输入端与数据信号端连接，输出端与驱动模块的控制端连接。数据写入模块可以被配置用于在第一控制信号端输出的第一控制信号的控制下，将数据信号端输出的数据信号提供给驱动模块的控制端。控制模块的控制端与第二控制信号端连接，输入端与驱动模块的输出端连接，输出端与电致变色器件的一端连接，电致变色器件的另一端接地。控制模块可以被配置用于基于第二控制信号端输出的第二控制信号来控制驱动模块与电致变色器件的导通。驱动模块的输入端与电源电压信号端连接。驱动模块可以被配置用于在数据信号的控制下，根据电源电压信号端输出的电源电压信号来驱动电致变色器件进行显色或褪色。控制模块控制所述导通从而使该导通延迟于电源电压信号的变化。通过上述各模块的相互配合，可以实现控制模块的导通延迟于电源电压信号的变化，可以有效去除电源电压信号的干扰，避免因电源电压信号变化造成的显示波动，进而可以提高显示效果。
可以理解的是，以上所述仅为本发明的示例性实施方式，但本发明的保护范围并不局限于此。应当指出的是，在不脱离本发明的精神和原理的前提下，本领域的普通技术人员可想到各种变化或替换，这些变化或替换都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所附权利要求的保护范围为准。
需要说明的是，上述实施例仅以上述各功能模块的划分进行举例说明，实际应用中，可以根据需要将上述功能分配给不同的功能模块完成。可以将装置的内部结构划分成不同的功能模块，以完成以上描述的全部或者部分功能。另外，上述一个模块的功能可以由多个模块来完成，上述多个模块的功能也可以集成到一个模块中完成。
本申请所使用的术语“和/或”仅仅是被用来描述一种关联对象的关联关系，表示可以存在三种关系。例如，“A和/或B”可以表示如下这三种情况：单独存在A，同时存在A和B，单独存在B。另外，本文中字符“/”一般表示前后关联对象是一种“或”的关系。
在权利要求书中，任何置于括号中的附图标记都不应当解释为限制权利要求。术语“包括”并不排除除了权利要求中所列出的元件或步骤之外的元件或步骤的存在。元件前的词语“一”或“一个”并不排除存在多个这样的元件。

Claims (13)

  1. 一种像素电路，包括：数据写入模块、驱动模块、控制模块和电致变色器件；其中，
    所述数据写入模块的控制端与第一控制信号端连接以便接收第一控制信号，输入端与数据信号端连接以便接收数据信号，输出端与所述驱动模块的控制端连接；所述数据写入模块被配置用于在所述第一控制信号的控制下将所述数据信号提供给所述驱动模块的控制端；
    所述驱动模块的输入端与电源电压信号端连接以便接收电源电压信号，所述驱动模块被配置用于在所述数据信号的控制下，根据所述电源电压信号来驱动所述电致变色器件进行显色或褪色；
    所述控制模块的控制端与第二控制信号端连接以便接收第二控制信号，输入端与所述驱动模块的输出端连接，输出端与所述电致变色器件的一端连接，所述电致变色器件的另一端接地，所述控制模块被配置用于基于所述第二控制信号来控制所述驱动模块与所述电致变色器件的导通，所述控制模块控制所述导通从而使该导通延迟于所述电源电压信号的变化。
  2. 如权利要求1所述的像素电路，其中，所述像素电路的显示周期包括显色阶段和褪色阶段，所述电源电压信号在所述显色阶段和褪色阶段内分别保持相应的电位以实现显色和褪色。
  3. 如权利要求2所述的像素电路，其中，所述电源电压信号在所述显色阶段内保持低电位，在所述褪色阶段内保持高电位。
  4. 如权利要求2或3所述的像素电路，其中，所述数据信号和所述第一控制信号在所述显色阶段和褪色阶段开始的时刻转换为接通电位。
  5. 如权利要求4所述的像素电路，其中，所述第二控制信号在所述显色阶段和褪色阶段开始之后延迟预定时间后转换为接通电位。
  6. 如权利要求5所述的像素电路，其中，所述预定时间为所述第一控制信号保持在接通电位的持续时间的一半。
  7. 如权利要求1所述的像素电路，其中，所述数据写入模块包括第一开关晶体管；其中，
    所述第一开关晶体管的栅极为所述数据写入模块的控制端，源极 为所述数据写入模块的输入端，漏极为所述数据写入模块的输出端。
  8. 如权利要求1所述的像素电路，其中，所述控制模块包括第二开关晶体管；其中，
    所述第二开关晶体管的栅极为所述控制模块的控制端，源极为所述控制模块的输入端，漏极为所述控制模块的输出端。
  9. 如权利要求1所述的像素电路，其中，所述驱动模块包括第三开关晶体管和电容；其中，
    所述第三开关晶体管的栅极为所述驱动模块的控制端，源极为所述驱动模块的输入端，漏极为所述驱动模块的输出端；
    所述电容的两端分别电连接至所述第三开关晶体管的栅极与源极。
  10. 如权利要求7-9中任一项所述的像素电路，其中，所述第一开关晶体管、第二开关晶体管和第三开关晶体管均为N型晶体管或均为P型晶体管。
  11. 一种显示面板，包括如权利要求1-10中任一项所述的像素电路。
  12. 一种显示装置，包括如权利要求11所述的显示面板。
  13. 一种如权利要求1-10中任一项所述像素电路的驱动方法，该方法包括：
    在显色阶段，数据写入模块在第一控制信号端输出的第一控制信号的控制下，将数据信号端输出的数据信号提供给驱动模块的控制端；所述驱动模块在所述数据信号的控制下，向控制模块的输入端提供电源电压信号端输出的电源电压信号，用于驱动所述电致变色器件进行显色；控制模块基于第二控制信号端输出的第二控制信号来控制所述驱动模块与所述电致变色器件的导通，所述控制模块控制所述导通从而使该导通延迟于所述电源电压信号的变化；
    在褪色阶段，数据写入模块在第一控制信号端输出的第一控制信号的控制下，将数据信号端输出的数据信号提供给驱动模块的控制端；所述驱动模块在所述数据信号的控制下，向控制模块的输入端提供电源电压信号端输出的电源电压信号，用于驱动所述电致变色器件进行褪色；控制模块基于第二控制信号端输出的第二控制信号来控制所述驱动模块与所述电致变色器件的导通，所述控制模块控制所述导通从而使该导通延迟于所述电源电压信号的变化。
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