WO2018014381A1 - Goa电路及液晶显示器 - Google Patents
Goa电路及液晶显示器 Download PDFInfo
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- WO2018014381A1 WO2018014381A1 PCT/CN2016/094463 CN2016094463W WO2018014381A1 WO 2018014381 A1 WO2018014381 A1 WO 2018014381A1 CN 2016094463 W CN2016094463 W CN 2016094463W WO 2018014381 A1 WO2018014381 A1 WO 2018014381A1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0283—Arrangement of drivers for different directions of scanning
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/08—Details of timing specific for flat panels, other than clock recovery
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
Definitions
- the present invention relates to the field of liquid crystal display technology, and in particular to a GOA circuit and a liquid crystal display.
- the Gate Driver On Array (GOA) technology is a type of driver chip fabricated by replacing a thin film transistor (TFT) gate scan driving circuit on an array substrate instead of an external silicon chip.
- TFT thin film transistor
- kind of technology Since the GOA circuit can be directly fabricated around the panel, the thickness of the frame of the liquid crystal display (LCD) panel can be reduced, the process process can be simplified, the product cost can be reduced, and the integration degree of the liquid crystal panel can be improved.
- the existing GOA circuit usually includes a plurality of cascaded GOA units, and each stage of the GOA unit includes a pull-up control circuit, a pull-up circuit, a downlink circuit, a pull-down circuit, a bootstrap capacitor and a pull-down sustain circuit, and a potential boost. Bootstrap capacitor.
- the pull-up control circuit is responsible for controlling the opening of the pull-up circuit, generally connecting the downlink signal or the Gate signal transmitted by the GOA circuit of the previous stage; the pull-up circuit is mainly responsible for outputting the input clock signal (Clock).
- the pull-down circuit is responsible for quickly pulling the scan drive signal (that is, the potential of the TFT gate) to a low level after outputting the scan drive signal, that is, turning off the Gate signal;
- the pull-down sustain circuit is mainly responsible for maintaining the scan drive signal and the Gate signal of the pull-up circuit (commonly referred to as Q point) in a closed state (ie, a negative potential), usually with two pull-down sustaining modules alternating; the bootstrap capacitor is responsible for the second rise of the Q point.
- the structure of the GOA circuit in the prior art basically places the pull-up circuit, the pull-up control circuit and the like of the above GOA unit in the same level GOA unit, especially the two pull-down maintenance circuits are Acting on the same level of GOA circuit.
- the pull-down sustain circuits of each stage of the GOA unit are identical and independent, and there is no interaction between the pull-down sustain circuits of the adjacent two-stage GOA units, resulting in a lower effective operation efficiency of the circuit.
- the pull-down sustain circuit of each stage of the GOA unit contains more TFT elements, this not only causes the overall size of the GOA unit to be too large, but also increases the design space occupied by the GOA circuit, and also increases the power consumption of the circuit.
- the embodiment of the invention provides a GOA circuit and a liquid crystal display, which can realize a shared pull-down sustain circuit for each two-stage GOA circuit, thereby reducing the number of TFTs in the GOA circuit, thereby reducing the design space occupied by the GOA circuit.
- an embodiment of the present invention provides a Gate Driver On Array (GOA) circuit, where the GOA circuit includes a plurality of cascaded GOA units, and the Nth level GOA unit is used to control the Nth The level horizontal scanning line G(N) is charged, and the (N+4)th stage GOA unit is used to control charging of the (N+4)th horizontal scanning line G(N+4), wherein:
- GOA Gate Driver On Array
- the Nth stage GOA unit includes an Nth pull-down maintaining circuit;
- the (N+4)th GOA unit includes an (N+4) pull-down maintaining circuit; and
- the Nth pull-down maintaining circuit includes an Nth control circuit and an Nth sustain a circuit and an Nth shared circuit shared by the (N+4) pull-down maintaining circuit;
- the (N+4) pull-down maintaining circuit includes an (N+4)th control circuit and an (N+4)th sustain circuit And the Nth shared circuit shared with the Nth pull-down maintaining circuit;
- the Nth control circuit has a first control terminal Q(N) and a second control terminal, the second control terminal of the Nth control circuit is connected to the first low frequency control signal, and the first control terminal Q of the Nth control circuit (N) and the first low frequency control signal for controlling a potential of an output terminal P(N) of the Nth control circuit to be a high potential or a low potential; wherein the Nth maintaining circuit is electrically connected to the Nth control An output terminal P(N) of the circuit, a first control terminal Q(N), and the Nth horizontal scanning line G(N) for high potential at an output terminal P(N) of the Nth control circuit Maintaining a potential of the first control terminal Q(N) of the Nth control circuit and the Nth horizontal scanning line G(N) to a low potential;
- the (N+4) control circuit has a first control terminal Q(N+4) and a second control terminal, and the second control terminal of the (N+4)th control circuit is connected to the second low frequency control signal, a first control terminal Q(N+4) of the (N+4)th control circuit and the second low frequency control signal for controlling the (N+4)th control
- the output terminal P(N+4) of the circuit is high or low;
- the (N+4)th maintaining circuit is electrically connected to the output terminal P(N+4) of the (N+4)th control circuit, a first control terminal Q(N+4) and said (N+4)th horizontal scanning line G(N+4) for outputting P(N+) at said (N+4)th control circuit 4) when the potential is high, maintaining the potential of the first control terminal Q (N+4) of the (N+4)th control circuit and the (N+4)th horizontal scanning line G(N+4) Is low potential; wherein the first low frequency control signal and the second low frequency control signal have opposite phases;
- the Nth shared circuit When the output terminal P(N) of the Nth control circuit is at a high potential, and the output terminal P(N+4) of the (N+4)th control circuit is at a high potential, the Nth shared circuit operates And sharing the potential of the first control terminal Q(N) of the Nth control circuit with the potential of the first control terminal Q(N+4) of the (N+4)th control circuit, and maintaining the low potential
- the Nth shared circuit shares the potential of the Nth horizontal scanning line G(N) with the potential of the (N+4)th horizontal scanning line G(N+4), and is maintained at a low potential .
- the shared circuit includes a sixty-first transistor, a sixty-second transistor, a sixty-third transistor, and a sixty-fourth transistor, wherein:
- a gate of the sixty-first transistor and a gate of the sixty-third transistor are electrically connected to an output terminal P(N) of the Nth control circuit, and a source level electrical property of the sixty-first transistor
- a drain of the 61st transistor is electrically connected to a drain of the 62nd transistor
- a source of the 62nd transistor The first control terminal Q (N+4) of the (N+4)th control circuit is electrically connected, and the gate of the sixty-second transistor and the gate of the sixty-fourth transistor are electrically connected
- a source of the sixty-third transistor is electrically connected to the (N+4)th horizontal scanning line G (N+4)
- the drain of the sixty-third transistor is electrically connected to the drain of the sixty-fourth transistor, and the source of the sixty-fourth transistor is electrically connected to the Nth horizontal scan line G (N) ).
- the Nth control circuit includes a fifty-first transistor, a fifty-second transistor, a fifty-third transistor, and a fifty-fourth transistor, wherein:
- the gate of the fifty-first transistor, the drain of the fifty-first transistor, and the drain of the fifty-third transistor are electrically connected to the second control end of the Nth control circuit, Fifty-one crystal a source of the transistor is electrically connected to a drain of the fifty-second transistor and a gate of the fifty-third transistor, and a gate of the fifty-second transistor is electrically connected to the first control circuit a control terminal Q(N), the source of the fifty-third transistor is electrically connected to the drain of the fifty-fourth transistor and the output terminal P(N) of the Nth control circuit, the fifth a source of twelve transistors and a source of the fifty-fourth transistor input a direct current low voltage;
- the Nth sustain circuit comprises a thirty-second transistor and a forty-second transistor, wherein:
- a gate of the thirty-second transistor and a gate of the forty-second transistor are electrically connected to an output terminal P(N) of the Nth control circuit, and a drain electrical property of the thirty-second transistor Connecting the Nth horizontal scan line G(N), the drain of the forty-second transistor is electrically connected to the first control terminal Q(N) of the Nth control circuit, the thirty-second transistor a source and a source of the forty-second transistor input the DC low voltage;
- the Nth horizontal scanning line G(N) and the first control terminal Q(N) of the Nth control circuit are maintained at a low potential .
- the (N+4)th control circuit includes a fifty-fifth transistor, a fifty-sixth transistor, a fifty-seventh transistor, and a fifty-eighth transistor, wherein:
- the gate of the fifty-fifth transistor, the drain of the fifty-fifth transistor, and the drain of the fifty-seventh transistor are electrically connected to the second control end of the (N+4)th control circuit
- the source of the fifty-fifth transistor is electrically connected to the drain of the fifty-sixth transistor and the gate of the fifty-seventh transistor
- the gate of the fifty-sixth transistor is electrically connected a first control terminal Q(N+4) of the (N+4) control circuit
- the source of the fifty-seventh transistor being electrically connected to the drain of the fifty-eighth transistor and the first (N +4) an output terminal P(N+4) of the control circuit, a source of the fifty-sixth transistor and a source of the fifty-eighth transistor input a direct current low voltage
- the (N+4) control circuit includes a fifty-fifth transistor, a fifty-sixth transistor, a fifty-seventh transistor, and a fifty-eighth transistor, wherein:
- the gate of the fifty-fifth transistor, the drain of the fifty-fifth transistor, and the drain of the fifty-seventh transistor are electrically connected to the second control end of the (N+4)th control circuit
- the source of the fifty-fifth transistor is electrically connected to the drain of the fifty-sixth transistor and the gate of the fifty-seventh transistor
- the gate of the fifty-sixth transistor is electrically connected a first control terminal Q(N+4) of the (N+4) control circuit
- the source of the fifty-seventh transistor being electrically connected to the drain of the fifty-eighth transistor and the first (N +4) an output terminal P(N+4) of the control circuit, a source of the fifty-sixth transistor and a source of the fifty-eighth transistor input a direct current low voltage
- the (N+4)th maintaining circuit comprises a thirty-third transistor and a forty-third transistor, wherein:
- the gate of the thirty-third transistor and the gate of the forty-third transistor are electrically connected to the output terminal P(N+4) of the (N+4)th control circuit, the thirty-third The drain of the transistor is electrically connected to the Nth horizontal scan line G(N+4), and the drain of the 43rd transistor is electrically connected to the first control end of the (N+4)th control circuit Q (N+4), the source of the thirty-third transistor and the source of the forty-third transistor input the DC low voltage;
- the Nth stage GOA unit further includes an Nth pull-up control circuit, an Nth pull-up circuit, an Nth down transfer circuit, an Nth pull-down circuit, and an Nth bootstrap capacitor, wherein:
- the Nth pull-up control circuit is electrically connected to the first control terminal Q(N) of the Nth control circuit, and the Nth pull-up control circuit is connected to the downlink signal ST(N) generated by the N-2th GOA unit. -2) and the (N-2)th horizontal scanning line G(N-2);
- the Nth pull-up circuit and the Nth drop-off circuit are electrically connected to the first control terminal Q(N) of the Nth control circuit, the Nth pull-up circuit and the Nth horizontal scan line G, respectively.
- (N) electrical connection the Nth downlink transmission circuit outputs a downlink signal ST(N) generated by the Nth stage GOA unit, and the Nth pull-up circuit and the Nth downlink transmission circuit are respectively connected to the corresponding Clock signal of the N-level GOA unit;
- One end of the Nth bootstrap capacitor is electrically connected to the first control terminal Q(N) of the Nth control circuit, and the other end is electrically connected to the Nth horizontal scan line G(N);
- the Nth pull-down circuit is electrically connected to the first control terminal Q(N) and the Nth horizontal scan line G(N) of the Nth control circuit, and the Nth pulldown circuit is further connected to the DC low The voltage, the Nth pull-down circuit is also connected to the (N+2)th horizontal scanning line G(N+2).
- the (N+4)th stage GOA unit further includes an (N+4) pull-up control circuit, an (N+4) pull-up circuit, and a N+4) downlink circuit, (N+4) pull-down circuit and (N+4) bootstrap capacitor;
- the (N+4) pull-up control circuit accesses the downlink signal ST(N+2) and the (N+2)th horizontal scanning line G(N+2) generated by the (N+2)th stage GOA unit,
- the (N+4) pull-up control circuit is electrically connected to the first control terminal Q(N+4) of the (N+4)th control circuit;
- the (N+4) pull-up circuit and the (N+4)th down circuit are electrically connected to the first control terminal Q(N+4) of the (N+4)th control circuit, respectively.
- the (N+4) pull-up circuit is electrically connected to the (N+4)th horizontal scanning line G(N+4), and the (N+4)th output circuit outputs the (N+4)th stage.
- the downlink signal ST(N+4) generated by the GOA unit, the (N+4) pull-up circuit and the (N+4)th downlink circuit are all connected to the (N+4)th level GOA unit.
- One end of the (N+4) bootstrap capacitor is electrically connected to the N+4th gate signal point Q(N+4), and the other end is electrically connected to the (N+4)th horizontal scan line. G(N+4);
- the (N+4) pull-down circuit is electrically connected to the first control terminal Q (N+4) and the (N+4)th horizontal scanning line G (N+) of the (N+4)th control circuit, respectively. 4), the (N+4) pull-down circuit further inputs the DC low voltage, and the (N+4) pull-down circuit is further connected to the (N+6)th horizontal scan line G(N+6) .
- the clock signal accessed by each GOA unit is one of a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal, wherein a clock signal of the Nth stage GOA unit is accessed.
- the clock signals for accessing the (N+4)th stage GOA unit are the same.
- the period of the first low frequency control signal and the second low frequency control signal is twice the period of the clock signal accessed by each GOA unit.
- the pull-up control circuit accesses a scan enable signal; in the last stage and the penultimate stage GOA unit, the pull-down circuit accesses the scan enable signal.
- an embodiment of the present invention further provides a liquid crystal display including the above GOA circuit.
- the Nth pull-down maintaining circuit in the Nth stage GOA unit includes an Nth control circuit, an Nth sustain circuit, and an Nth share shared by the (N+4) pull-down maintaining circuit.
- a circuit, the (N+4) pull-down maintaining circuit of the (N+4)th stage GOA unit includes a (N+4)th control circuit, an (N+4)th maintaining circuit, and a common to the Nth pull-down maintaining circuit
- the Nth shared circuit; the first control terminal Q(N) of the Nth control circuit and the first low frequency control signal LC1 accessed by the second control terminal may control the output terminal P(N) of the Nth control circuit a potential; a first control terminal Q(N+4) of the (N+4)th control circuit, and a second low frequency control signal LC2 coupled to the second control terminal to control an output of the (N+4)th control circuit a potential of the terminal P(N+4); when the output terminal P(N) of the Nth control circuit and the output terminal
- FIG. 1 is a schematic diagram of a GOA circuit disclosed in an embodiment of the present invention.
- FIG. 2 is a schematic diagram of another GOA circuit disclosed in an embodiment of the present invention.
- FIG. 3 is a schematic diagram of another GOA circuit disclosed in an embodiment of the present invention.
- FIG. 4 is a schematic diagram of another GOA circuit disclosed in an embodiment of the present invention.
- FIG. 5 is a timing diagram of a clock signal in the embodiment of the present invention, and a corresponding relationship between the clock signal and each GOA unit;
- FIG. 6 is a schematic diagram of another GOA circuit disclosed in an embodiment of the present invention.
- Figure 7 is a waveform diagram of the input signal and the various key nodes of the circuit structure shown in Figure 6.
- the embodiment of the invention provides a GOA circuit and a liquid crystal display, which can realize a shared pull-down sustain circuit for each two-stage GOA circuit, and the actual effective efficiency of the circuit is low, thereby reducing the number of TFTs in the GOA circuit to reduce the occupation of the GOA circuit. Design space. The details are described below separately.
- FIG. 1 is a schematic diagram of an array substrate row driving GOA circuit according to an embodiment of the present invention.
- the GOA circuit includes a plurality of cascaded GOA units (eg, a first level GOA unit, a second level GOA unit, an Nth level GOA unit, an N+1th GOA unit, N+4 level GOA units, where N is an integer greater than or equal to 1), and each level of GOA units corresponds to a row of thin film transistors (TFTs).
- TFTs thin film transistors
- the gate voltage of each row of TFTs can be provided by a GOA circuit
- the Nth stage GOA unit is used to control charging of the Nth horizontal scanning line (G(N))
- the (N+4)th stage GOA unit is used for controlling the pair.
- the (N+4) level horizontal scanning line G (N+4) is charged.
- the GOA circuit When the same row is charged, the GOA circuit turns off the scan drive signal of the row, and then outputs an enable signal to turn on the TFT of the next row, and charges the TFT of the row. This is continued until the TFT corresponding to the last stage GOA unit is charged.
- the Nth stage GOA unit includes an Nth pull-down maintaining circuit 600; the (N+4)th stage GOA unit includes a (N+4) pull-down maintaining circuit 600'; and the Nth pull-down maintaining circuit 600 includes an Nth control circuit 601, the Nth sustain circuit 602, and the Nth sharing control circuit 600 and the (N+4) pull-down maintaining circuit 600' shared by the Nth sharing circuit 603; the (N+4) pull-down maintaining circuit 600'
- the first (N+4) control circuit 601', the (N+4)th maintaining circuit 602', and the (N+4) pull-down maintaining circuit 600' and the Nth pull-down maintaining circuit 600 are common to the The Nth sharing circuit 603; the N is a positive integer.
- the Nth control circuit 601 has a first control terminal Q(N) and a second control terminal 6012.
- the second control terminal 6012 of the Nth control circuit 601 is connected to the first low frequency control signal LC1, and the Nth control circuit 601.
- the first control terminal Q(N) and the first low frequency control signal LC1 are used to control the potential of the output terminal P(N) of the Nth control circuit 601 to be high or low;
- the Nth sustain circuit 602 is electrically connected to the output terminal P(N) of the Nth control circuit 601, the first control terminal Q(N), and the Nth horizontal scanning line G(N) for the Nth control circuit
- the output terminal P(N) of 601 is at a high potential, the potential of the first control terminal Q(N) of the Nth control circuit 601 and the Nth horizontal scanning line G(N) is maintained at a low potential.
- the (N+4) control circuit 601' has a first control terminal Q(N+4) and a second control terminal 6014, and the second control terminal 6014 of the (N+4)th control circuit 601' is connected to the second a low frequency control signal LC2, a first control terminal Q(N+4) of the (N+4)th control circuit 601' and the second low frequency control signal LC2 for controlling the (N+4)th control circuit
- the output terminal P(N+4) of 601' is high or low;
- the (N+4)th maintaining circuit 602' is electrically connected to the output terminal P of the (N+4)th control circuit 601' ( N+4), a first control terminal Q(N+4), and the (N+4)th horizontal scanning line G(N+4) for the (N+4)th control circuit 601'
- the output terminal P(N+4) is at a high potential, the first control terminal Q(N+4) and the (N+4)th level horizontal scan of the (N+4)th control circuit 601' are maintained.
- the Nth The sharing circuit 603 operates to set the potential of the first control terminal Q(N) of the Nth control circuit 601 to the potential of the first control terminal Q(N+4) of the (N+4)th control circuit 601'. Sharing, both are maintained at a low potential, and the Nth sharing circuit 603 sets the potential of the Nth horizontal scanning line G(N) to the (N+4)th horizontal scanning line G(N+4) The potential sharing is maintained at a low potential.
- Nth shared electricity Road 603 stops working.
- the Nth shared circuit 603 is equivalent to an AND gate circuit.
- the Nth pull-down maintaining circuit 600 in the Nth stage GOA unit includes an Nth control circuit 601, an Nth sustain circuit 602, and an Nth pull-down maintaining circuit 600 and the (N+4)th
- the Nth sharing circuit 603 shared by the pull-down maintaining circuit 600', the (N+4) pull-down maintaining circuit 600' of the (N+4)th stage GOA unit includes the (N+4)th control circuit 601', the (N+ 4) the sustain circuit 602' and the (N+4) pull-down maintaining circuit 600' and the Nth sharing circuit 601 shared by the Nth pull-down maintaining circuit 600;
- the first control terminal Q of the Nth control circuit 601 (N) and the first low frequency control signal LC1 accessed by the second control terminal 6012 can control the potential of the output terminal P(N) of the Nth control circuit 601; the first of the (N+4) control circuit 601'
- the control terminal Q(N+4), and the second low frequency control signal LC2 accessed by the second control terminal 6014 can
- FIG. 2 is a schematic diagram of another GOA circuit disclosed in an embodiment of the present invention.
- the GOA circuit generally shown in this embodiment is identical to the circuit structure and composition of the GOA circuit shown in FIG. 1.
- the GOA circuit includes a plurality of cascaded GOA units, and each level of the GOA unit is Corresponding to a row of thin film transistors.
- the Nth stage GOA unit includes an Nth pull-down maintaining circuit 600; the (N+4)th stage GOA unit includes a (N+4) pull-down maintaining circuit 600'; and the Nth pull-down maintaining circuit 600 includes an Nth control circuit 601, the Nth sustain circuit 602, and the Nth sharing control circuit 600 and the (N+4) pull-down maintaining circuit 600' shared by the Nth sharing circuit 603; the (N+4) pull-down maintaining circuit 600'
- the first (N+4) control circuit 601', the (N+4)th maintaining circuit 602', and the (N+4) pull-down maintaining circuit 600' and the Nth pull-down maintaining circuit 600 are common to the The Nth shared circuit 603; for details, please refer to the description of the GOA circuit shown in FIG. 1 , and details are not described herein again.
- the sharing circuit 603 includes a sixty-first transistor T61, a sixty-second transistor T62, a sixty-third transistor T63, and a sixty-fourth transistor. T64, where:
- the gate of the sixty-first transistor T61 and the gate of the sixty-third transistor T63 are electrically connected to the output terminal P(N) of the Nth control circuit 601, and the 61st transistor T61
- the source level is electrically connected to the first control terminal Q(N) of the Nth control circuit 601, and the drain of the 61st transistor T61 is electrically connected to the drain of the 62nd transistor T62;
- the source of the sixty-second transistor T62 is electrically connected to the first control terminal Q(N+4) of the (N+4)th control circuit 601', the gate of the sixty-second transistor T62, and the
- the gate of the sixty-fourth transistor T64 is electrically connected to the output terminal P(N+4) of the (N+4)th control circuit 601';
- the source of the sixty-third transistor T63 is electrically connected to the a (N+4)th horizontal scan line G(N+4), the drain of the 63rd transistor T63 is electrically connected to a drain of the 64th transistor T
- the sharing circuit 603 is equivalent to an AND circuit, only when the output terminal P(N) of the Nth control circuit 601 and the output terminal P(N+4) of the (N+4)th control circuit 601' When the potential is high, the Nth sharing circuit 603 operates.
- FIG. 3 is a schematic diagram of another GOA circuit disclosed in an embodiment of the present invention.
- the GOA circuit shown in this embodiment is identical to the circuit structure and composition of the GOA circuit shown in FIG. 1 and FIG. 2, and the details of the GOA circuit shown in FIG. 1 and FIG. Description, no longer repeat here. Further, the difference is that, in the GOA circuit described in this embodiment, the Nth control circuit 601 includes a fifty-first transistor T51, a fifty-second transistor T52, a fifty-third transistor T53, and a fiftyth.
- Four transistors T54 where:
- a gate of the fifty-first transistor T51, a drain of the fifty-first transistor T51, and a drain of the fifty-third transistor T53 are electrically connected to the second control end of the Nth control circuit 601 6012, that is, accessing the first low frequency control signal LC1
- the source of the fifty-first transistor T51 is electrically connected to the drain of the fifty-second transistor T52 and the gate of the fifty-third transistor T53
- the gate of the fifty-second transistor T52 is electrically connected to the first control terminal Q(N) of the Nth control circuit 601
- the source of the fifty-third transistor T53 is electrically connected to the fiftyth Four transistor T54
- the drain and the output terminal P(N) of the Nth control circuit 601, the source of the fifty-second transistor T52 and the source of the fifty-fourth transistor T54 are input with a DC low voltage Vss.
- the fifty-second transistor T52 and the fifty-fourth transistor T54 are turned on, and the output of the Nth control circuit 601 is turned on. P(N) is pulled low to a low potential.
- the first control terminal Q(N) of the Nth control circuit 601 When the first control terminal Q(N) of the Nth control circuit 601 is low, if the first low frequency control signal LC1 accessed by the second control terminal 6012 of the Nth control circuit 601 changes from a high potential At a low potential, the fifty-first transistor T51, the fifty-second transistor T52, the fifty-third transistor T53, and the fifty-fourth transistor T54 are all turned off, but since the first low-frequency control signal LC1 is at a high potential in the previous period, The output terminal P(N) of the Nth control circuit 601 is at a high potential, and the output terminal P(N) of the Nth control circuit 601 maintains the potential state of the previous period, that is, P(N) is high. .
- the Nth sustain circuit 602 includes a thirty-second transistor T32 and a forty-second transistor T42, wherein:
- the gate of the thirty-second transistor T32 and the gate of the forty-second transistor T42 are electrically connected to the output terminal P(N) of the Nth control circuit 601, and the thirty-second transistor T32
- the drain is electrically connected to the Nth horizontal scan line G(N), and the drain of the forty-second transistor T42 is electrically connected to the first control terminal Q(N) of the Nth control circuit 601.
- the source of the thirty-second transistor T32 and the source of the forty-second transistor T42 are input to the DC low voltage Vss;
- the thirty-second transistor T32 and the forty-second transistor T42 are turned on, and the Nth horizontal scanning line G(N) is turned on.
- the first control terminal Q(N) of the Nth control circuit 601 is maintained at a low potential.
- the (N+4)th control circuit 601' includes a fifty-fifth transistor T55, a fifty-sixth transistor T56, a fifty-seventh transistor T57, and a fifty-eighth transistor T58, wherein:
- the gate of the fifty-fifth transistor T55, the drain of the fifty-fifth transistor T55, The drain of the fifty-seventh transistor T57 is electrically connected to the second control terminal 6014 of the (N+4)th control circuit 601', that is, the second low frequency control signal LC2 is connected, and the fifty-fifth transistor T55
- the source is electrically connected to the drain of the fifty-sixth transistor T56 and the gate of the fifty-seventh transistor T57, and the gate of the fifty-sixth transistor T56 is electrically connected to the first (N+ 4)
- the first control terminal Q (N+4) of the control circuit 601', the source of the fifty-seventh transistor T57 is electrically connected to the drain of the fifty-eighth transistor T58 and the first (N+ 4)
- the output terminal P(N+4) of the control circuit 601', the source of the fifty-sixth transistor T56 and the source of the fifty-eighth transistor T58 are input with a DC low voltage
- the control signal LC2 changes from a high potential to a low potential, and the fifty-fifth transistor T55, the fifty-sixth transistor T56, the fifty-seventh transistor T57, and the fifty-eighth transistor T58 are all turned off, but due to the previous period
- the second low frequency control signal LC2 is at a high potential, and the output terminal P(N+4) of the (N+4)th control circuit 601 is at a high potential, and the (N+4)th control circuit 601' of the period is
- the output terminal P(N+4) maintains the potential state of the previous period, that is, P(N+4) is high.
- the (N+4)th maintaining circuit 602' includes a thirty-third transistor T33 and a forty-third transistor T43, wherein:
- the gate of the thirty-third transistor T33 and the gate of the forty-third transistor T43 are electrically connected to the output terminal P(N+4) of the (N+4)th control circuit 601'.
- the drain of the thirty-third transistor T33 is electrically connected to the Nth horizontal scanning line G(N+4), and the drain of the forty-third transistor T43 is electrically connected to the (N+4) control a first control terminal Q (N+4) of the circuit 601', a source of the thirty-third transistor T33, and a source of the forty-third transistor T43 are input to the DC low voltage Vss.
- FIG. 4 is a schematic circuit diagram of a GOA circuit according to an embodiment of the present invention.
- the Nth stage GOA unit further includes an Nth pull-up control circuit 100, an Nth pull-up circuit 200, an Nth down transfer circuit 300, an Nth pull-down circuit 400, and an Nth bootstrap capacitor 500.
- the Nth pull-up control circuit 100, the N-th pull-up circuit 200, the Nth drop-off circuit 300, the N-th pull-down circuit 400, and the Nth bootstrap capacitor 500 are respectively connected to the first of the Nth control circuit 601.
- the control terminal Q(N), the Nth pull-up circuit 200, the Nth pull-down circuit 400, and the Nth bootstrap capacitor 500 are electrically connected to the Nth horizontal scanning line G(N), respectively.
- the Nth pull-up control circuit 100 is electrically connected to the first control terminal Q(N) of the Nth control circuit 601, and the Nth pull-up control circuit 100 is connected to the next (N-2)-level GOA unit. Transmitting signal ST(N-2) and (N-2)th horizontal scanning line G(N-2);
- the Nth pull-up circuit 200 and the Nth downlink circuit 300 are electrically connected to the first control terminal Q(N) of the Nth control circuit 601, and the Nth pull-up circuit 200 and the Nth stage.
- the horizontal scan line G(N) is electrically connected, and the Nth down pass circuit 300 outputs a down signal ST(N) generated by the Nth stage GOA unit, and the Nth pull-up circuit 200 and the Nth down-transfer circuit 300 Each accessing a clock signal corresponding to the Nth stage GOA unit;
- the Nth bootstrap capacitor 500 includes a capacitor Cb1. One end of the capacitor Cb1 is electrically connected to the first control terminal Q(N) of the Nth control circuit 601, and the other end is electrically connected to the Nth level. Scan line G(N);
- the Nth pull-down circuit 400 is electrically connected to the first control terminal Q(N) and the Nth horizontal scanning line G(N) of the Nth control circuit 601, and the Nth pulldown circuit 400 is further connected to the The DC low voltage Vss is also applied to the (N+2)th horizontal scanning line G(N+2).
- the (N+4)th GOA unit is further included
- the (N+4) bootstrap capacitor 500' are respectively connected to the first control terminal Q(N+4) of the (N+4)th control circuit 601', the (N+4) pull-up circuit The 200', the (N+4) pull-down circuit 400' and the (N+4) bootstrap capacitor 500' are electrically connected to the (N+4)th horizontal scanning line G(N+4), respectively.
- the (N+4) pull-up control circuit 100' accesses the downlink signal ST(N+2) and the (N+2)th horizontal scanning line G (N+2) generated by the (N+2)th stage GOA unit.
- the first (N+4) pull-up control circuit is electrically connected to the first control terminal Q(N+4) of the (N+4)th control circuit 601';
- the (N+4) pull-up circuit 200' and the (N+4)th pass-down circuit 300' are electrically connected to the first control terminal Q (N+) of the (N+4)th control circuit 601', respectively. 4), the (N+4) pull-up circuit 200' is electrically connected to the (N+4)th horizontal scan line G(N+4), and the (N+4)th pass circuit 300' outputs a downlink signal ST(N+4) generated by the (N+4)th stage GOA unit, and the (N+4)th pull-up circuit 200' and the (N+4)th-throw circuit 300' are both Accessing a clock signal corresponding to the (N+4)th stage GOA unit;
- the (N+4) bootstrap capacitor 500' includes a capacitor Cb2, one end of the capacitor Cb2 is electrically connected to the N+4th gate signal point Q (N+4), and the other end is electrically connected to the The (N+4)th horizontal scanning line G(N+4);
- the (N+4) pull-down circuit 400' is electrically connected to the first control terminal Q(N+4) and the (N+4)th horizontal scan line of the (N+4)th control circuit 601', respectively.
- G(N+4), the (N+4) pull-down circuit 400' further accesses the DC low voltage Vss, and the (N+4) pull-down circuit 400' is further connected to the (N+6)th stage.
- Horizontal scanning line G (N+6) is
- the pass mode adopted by the GOA circuit is transmitted to the Nth stage from the N-2th stage.
- the ST signal is the start signal of the GOA circuit, but is turned on at the beginning of the scan, and is always at a low potential.
- the ST signal is responsible for starting the first and second stage GOA units, and the start signal of the subsequent Nth stage GOA circuit is generated by the ST(N-2) signal of the downstream circuit portion of the previous N-2th stage circuit, so that It is possible to turn on the GOA driving circuit step by step to realize the line scan driving.
- the Nth stage GOA unit receives the downlink signal ST(N-2) generated by the N-2th GOA unit, The scan drive signal G(N-2) generated by the N-2 stage GOA unit, the scan drive signal G(N+2) generated by the N+2 stage GOA unit, and the DC low voltage Vss and the clock signals CK1 to CK4 One CK signal, the Nth stage GOA unit outputs a scan drive signal G(N) and a down signal ST(N) through different transistors.
- Such a structure can ensure that the GOA signal is transmitted step by step, and each scan line is charged step by step.
- the pull-up control circuit of the Nth stage GOA unit can receive the downlink signal ST(N-2) and the N-2th GOA unit generated by the N-2th GOA unit. Any one of the scan drive signals G(N-2) may be used.
- the GOA circuit includes a plurality of cascaded GOA units, and the GOA circuit further includes a first low frequency control signal LC1, a second low frequency control signal LC2, a DC low voltage VSS, and four clock signal numbers CK1, CK2 disposed at the periphery of each GOA unit. , CK3, CK4 metal wire.
- a clock signal is generally used to control each row of TFTs to be turned on or off, and a clock signal is outputted to a horizontal scanning line of each GOA unit through a pull-up circuit.
- Different clock signals (such as CK-1, CK-2, CK-3, CK-m, etc.) can be simultaneously output to a plurality of cascaded GOA units included in the GOA circuit to output the clock signal to the gate of the TFT.
- the clock signals CK1, CK2, CK3, and CK4 are respectively input to the pull-up circuits of the Nth, N+1th, N+2, and N+3 GOA units to respectively correspond to the horizontal scanning lines of the display area. Charge it.
- FIG. 5 is a timing diagram of a clock signal in the embodiment of the present invention, and a corresponding relationship between the clock signal and each GOA unit.
- the clock signal accessed by each GOA unit is one of the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4, wherein the first clock signal CK1 and The third clock signal CK3 is completely opposite.
- the clock signals input to the Nth and N+4th GOA units at the timing are just the same (refer to the CK signal diagram of FIG. 5), which avoids the problem of mischarge caused by sharing the Q point.
- the following takes an example in which the Nth-level GOA unit accesses the clock signal CK1 as an example.
- the phase of the first low frequency control signal LC1 and the second low frequency control signal LC2 are opposite.
- the period of LC1 and LC2 is exactly twice that of the clock signal number CK(m).
- the CK signal Duty Ratio is 50%.
- FIG. 6 is a diagram of a GOA circuit disclosed in an embodiment of the present invention. Circuit diagram of the N-level GOA unit and the (N+4)-th grade GOA unit. As shown in FIG. 6, the circuit diagram of the N+4th stage GOA unit is similar to the structure of the Nth stage GOA unit. For details, refer to the related descriptions in FIG. 1 to FIG. 4 above, and details are not described herein again.
- the structure of the Nth stage GOA unit includes: an Nth pull-up control circuit 100, an Nth pull-up circuit 200, an Nth downlink circuit 300, an Nth pull-down circuit 400, an Nth bootstrap capacitor 500, and an Nth pulldown maintenance. Circuit.
- the Nth pull-down maintaining circuit includes an Nth control circuit 601, an Nth sustain circuit 602, and an Nth shared circuit 603.
- the Nth sharing circuit 603 includes a sixty-first transistor T61, a sixty-second transistor T62, a sixty-third transistor T63, and a sixty-fourth transistor T64, wherein the gate of the sixty-first transistor T61 in the shared circuit
- the gate of the sixty-third transistor T63 is electrically connected to the output terminal P(N) of the Nth control circuit 601 in the Nth stage GOA unit, and the source of the 61st transistor T61 is electrically connected to the Nth control circuit 601.
- the first control terminal Q(N), the drain of the sixty-first transistor T61 is electrically connected to the drain of the sixty-second transistor T62; the source of the sixty-second transistor T62 is electrically connected to the N-th stage GOA unit.
- the gate of the pole and the sixty-fourth transistor T64 is electrically connected to the output terminal P(N+4) of the (N+4)th control circuit 601' in the N+4th stage GOA unit; the 63rd transistor T63
- the source level is electrically connected to the output terminal G(N+4) of the (N+4)th stage GOA unit, that is, the (N+4)th horizontal scanning line G(N+4), and the leakage of the 63rd transistor T63
- the level is electrically connected to the drain of the 64th transistor T64
- the source of the sixty-fourth transistor T64 is electrically connected to the Nth horizontal scanning line G(N).
- the Nth control circuit 601 includes a fifty-first transistor T51, a fifty-second transistor T52, a fifty-third transistor T53, and a fifty-fourth transistor T54, wherein the fifty-first transistor T51 has a gate and a drain thereof.
- the first low frequency control signal LC1 is input to the pole;
- the fifth clock transistor T52 has a gate electrically connected to the first control terminal Q(N) of the Nth control circuit 601, and the source input DC low voltage Vss;
- the thirteenth transistor T53 has a drain inputting a first low frequency control signal LC1, and a source electrically connected to an output terminal P(N) of the Nth control circuit 601, wherein the source of the fifty first transistor T51, the fifty-second The drain of the transistor T52 and the gate of the fifty-third transistor T53 are electrically connected together;
- the fifth fourteen transistor T54 has a gate electrically connected to the first control terminal Q of the Nth control circuit 601 ( N), the drain is electrically connected to the output terminal P(N) of the Nth control circuit 601, and the source input is DC low. Press Vss.
- the Nth sustain circuit 602 includes a thirty-second transistor T32 and a forty-second transistor T42, wherein the thirty-second transistor T32 has its gate electrically connected to the output terminal P(N) of the Nth control circuit 601,
- the drain is electrically connected to the output terminal G(N) of the Nth stage GOA unit, the source input DC low voltage Vss, and the 42nd transistor T42 is electrically connected to the output terminal P of the Nth control circuit 601.
- the drain is electrically connected to the first control terminal Q(N) of the Nth control circuit 601, and the source is input with the DC low voltage Vss.
- the pull-down maintaining module 600 composed of the Nth control circuit 601, the Nth sustain circuit 602, and the Nth shared circuit 603 is mainly responsible for maintaining the low potentials of Q(N) and G(N).
- the Nth pull-up control circuit 100 includes an eleventh transistor T11, and the gate of the eleventh thin film transistor T11 is input from the first two stages of the GOA unit of the Nth stage GOA unit (the (N-2)th stage GOA unit
- the circuit's downlink signal ST(N-2), the drain and the source are electrically connected to the (N-2)th horizontal scanning line G(N-2) and the first control terminal of the Nth control circuit, respectively Q(N);
- the Nth pull-up control circuit 100 is for controlling the potential of Q(N).
- the Nth pull-up circuit 200 includes a 21st transistor T21.
- the gate of the 21st transistor T21 is electrically connected to the first control terminal Q(N) of the Nth control circuit, and the drain access corresponds to
- the clock signal of the Nth stage GOA unit is electrically connected to the Nth horizontal scanning line G(N), that is, the output terminal G(N) of the Nth stage GOA unit.
- the pull-up circuit 200 is configured to control the output of the scan driving signal by the Nth stage GOA unit according to the potential of the first control terminal Q(N) of the Nth control circuit and the potential of the clock signal accessed by the Nth stage GOA unit. G(N).
- the Nth downlink circuit 300 includes a 22nd transistor T22.
- the gate of the 22nd transistor T22 is electrically connected to the first control terminal Q(N) of the Nth control circuit 601.
- the source outputs the Nth stage down signal ST(N).
- the Nth downlink transmission circuit 300 is configured to output the output of the Nth stage GOA unit according to the potential of the first control terminal Q(N) of the Nth control circuit 601 and the potential of the clock signal accessed by the Nth stage GOA unit.
- the Nth stage transmits the signal ST(N).
- the Nth pull-down circuit 400 includes a 41st transistor T41 and a 31st transistor T31.
- the gates of the 41st transistor T41 and the 31st transistor T31 are electrically connected to the Nth stage GOA unit.
- the output terminal G(N+2) of the two-stage GOA unit (the N+2th GOA unit), that is, the (N+2)th horizontal scanning line G(N+2), the forty-first transistor T41 and the third Eleven crystal
- the source of the transistor T31 is connected to the DC low voltage Vss, wherein the drain of the T41 is electrically connected to the Nth horizontal scan line G(N), and the drain of the 31st transistor T31 is electrically connected to the first The first control terminal Q(N) of the N control circuit.
- the pull-down circuit 400 is configured to quickly pull down the potential of the scan driving signal G(N) and the first control terminal Q(N) of the Nth control circuit 601 after outputting the scan driving signal G(N).
- the bootstrap capacitor circuit 500 includes a capacitor Cb1. One end of the capacitor Cb1 is electrically connected to the first control terminal Q(N) of the Nth control circuit 601, and the other end is electrically connected to the Nth horizontal scan line G ( N). The bootstrap capacitor is responsible for the secondary rise of Q(N).
- the gate and the drain of the eleventh transistor T11 in the pull-up control circuit are both connected to the scan enable signal ST, and only the twenty-first transistor T21 outputs the first stage GOA unit.
- the scan drive signal G(1), the source of the twenty-second transistor T22 has no output, that is, the output is low.
- the gate and the drain of the eleventh transistor T11 in the pull-up control circuit are both connected to the scan enable signal ST, and only the twenty-first transistor T21 outputs the first-stage GOA unit.
- the scan drive signal G(2), the source of the twenty-second transistor T22 has no output, that is, the output is low.
- the gates of the forty-first transistor T41 and the thirty-first transistor T31 in the pull-down circuit are both connected to the scan enable signal ST.
- the gates of the transistors T52 and T54 are connected to the first control terminal Q(N) of the Nth control circuit 601, and the source is connected to the DC low voltage Vss, which is mainly used for Q(N).
- Vss DC low voltage
- the gate of T51 is connected to the first low-frequency control signal LC1
- the source of T51 is connected to the gate of T53
- the source of T53 is connected to the Nth.
- the output terminal P(N) of the control circuit 601 mainly turns on T51 and T53 through the high potential of LC1 when Q(N) is at a low potential, and maintains Q(N) and G when P(N) is at a high potential.
- transistor T31 is mainly used to discharge Q (N) charge
- T41 is mainly used to pull down G (N).
- the Nth stage GOA unit G(N) shares the pull-down maintaining circuit with the (N+4)th stage GOA unit G(N+4), and the function of the sharing circuit 603 is similar to the AND gate circuit.
- the Nth stage GOA unit G(N) has only one set of pull-down maintaining circuits, and the driving signal is provided by the first low frequency control signal LC1; G(N+4)
- the stage GOA circuit also has only one set of pull-down sustain circuits that provide drive signals by the second low frequency control signal LC2.
- FIG. 7 is a waveform diagram of an input signal and respective key nodes of the circuit structure shown in FIG. 6.
- ST(N-2), ST(N), ST(N+2), and ST(N+4) are the (N-2)th GOA unit, the Nth-level GOA unit, and the (N), respectively. +2) Down signal generated by the GOA unit and the (N+4)th GOA unit.
- the first low frequency control signal LC1 is at a low potential
- the second low frequency control signal LC2 is at a high potential
- the first control terminal Q(N) of the Nth control circuit 601 and the first control terminal Q(N+4) of the (N+4)th control circuit 601' are both at a low level
- the (N+4)-level GOA unit has no scan drive signals G(N) and G(N+4) outputs, both of which are at a low potential; since LC2 is at a high potential, the (N+4)-level GOA unit
- the transistors T55 and T57 are turned on, the output terminal P(N+4) of the (N+4)th control circuit 601' is at a high potential, and the transistors T33 and T43 are turned on to maintain Q(N+4) or at a low potential of Vss;
- both P(N) and P(N+4) are at a high potential. Since the gates of T61 and T63 in the shared module are both connected to P(N), the gates of T62 and T64 are connected to P(N+4), T61, T62, T63, T64 are all turned on, so that the Q(N) and Q(N+4) equipotentials of the upper and lower two-stage GOA circuits, G(N) and G(N+4), etc. The potentials are both maintained at a low potential.
- the start signal ST(N+2) of the (N+4)th GOA unit is not turned on, Q(N+4) and G(N+4) are always at a low potential; LC1 is at a high potential, LC2 At a low potential, the Nth stage GOA unit receives the downlink signal ST(N-2) generated by the (N-2)th GOA unit, and ST(N-2) is first at a high potential, followed by a low potential, G(N -2) Synchronous with the ST(N-2) signal, which is also at a high potential first, followed by a low potential, and the CK1 signal is first low and then high.
- the crystal in the Nth pull-up control circuit 100 when ST(N-2) is at a high potential in the t2 period The tube T1 is turned on, and the high level signal of G(N-2) is transmitted to the first control terminal Q(N) of the Nth control circuit 601, that is, the Q(N) point is at a high potential due to the opening of ST(N-2). And charging the upper board of the bootstrap capacitor Cb1.
- the high-potential CK1 signal continues to charge the bootstrap capacitor Cb1 through the transistor T22, and the potential of Q(N) is secondarily raised. Therefore, Q(N) is at a high potential throughout the t2 period.
- the (N+2)th GOA outputs a low potential G(N+2), and at the beginning of time t3, outputs a high potential G(N+2) and ST(N). +2).
- G(N+2) starts to be turned on, and the transistors T31 and T41 are both turned on to quickly pull the Nth horizontal scanning line G(N) of the Nth stage GOA unit to a low potential, and the Nth control circuit 601
- the high potential of the first control terminal Q(N) is also pulled to the low potential of Vss, that is, the high potential of the Q(N) point becomes low due to the pulldown of G(N+2), and remains thereafter.
- the low potential state while the LC1 is also low in the t3 period, T51, T53 are in the off state, so the P(N) point still maintains the low potential of the t2 period, and the AND module of the shared module still does not work.
- Q(N+4) is at a high potential at this time due to the turn-on of ST(N+2) and G(N+2), and charges the upper board of capacitor Cb2, and also because Q(N+4) is high.
- the potential, T22', T21' is turned on, because CK1 is at a low potential during the time when ST(N+2) is turned on, and the (N+4)th stage of the (N+4)th GOA unit outputs a low potential.
- ST(N+2) is turned on for only half of the time in the t3 period, and ST(N+2) is at the low level during the t3 period, at which time a high potential CK1 signal is input to the (N+4)th.
- Level GOA The formerly charged Cb2 can still turn on the transistors T22', T21', and the (N+4)th stage GOA unit outputs the high-level N+4 stage down signal ST(N+4) and the scan driving signal G.
- G(N+6) starts to open, and the transistors T31' and T41' are both turned on, and the (N+4)th horizontal scanning line G(N+4) in the (N+4)th stage GOA unit is quickly turned on.
- the potential is pulled to a low potential, and the high potential of Q(N+4) becomes the low potential of Vss due to the pull-down of G(N+6), and remains low until then; P(N+4) is due to LC2
- the first low frequency control signal LC1 is at a high potential, the transistors T51 and T53 are turned on, so P(N) is at a high potential, and the transistors T32 and T34 are also turned on to maintain Q ( N) is still at a low potential of Vss.
- the first low frequency control signal LC1 is at a low potential, and the P(N) point is maintained at a high potential during the t4 period, because the second low frequency control signal LC2 becomes a high potential, and P(N+4) is also raised to a high potential.
- Transistors T33 and T43 are turned on, Q(N+4) is still at a low potential of Vss; at this time, transistors T61, T62, T63, and T64 in the shared circuit are all turned on, and the AND gate circuit starts to work, and the upper and lower levels of GOA circuits share the pull-down maintenance.
- the circuit is such that the potentials of Q(N) and Q(N+4) of the upper and lower GOA units are equal, and the potentials of G(N) and G(N+4) are both maintained at a low potential.
- the first low frequency control signals LC1 and second in opposite phases Under the action of the low frequency control signal LC2 signal, P(N) and P(N+4) are both at high potential, and the shared module maintains the on state of t5 period.
- the Q(N) and Q(N+ of the upper and lower GOA circuits 4), G(N) and G(N+4) are simultaneously pulled down by LC1 and LC2 alternately.
- the threshold voltages of the four transistors T61, T62, T63, and T64 of the shared circuit drift, they mainly function as a conduction sharing circuit, and do not affect the operation of the pull-down sustain circuit shared by each two-stage GOA unit.
- the GOA circuit composed of GOA units can greatly reduce the number of TFTs in the GOA circuit, reduce the design space occupied by the GOA circuit, and realize a narrower frame design of the liquid crystal display.
- all of the transistors in the above figures are N-type metal oxide semiconductor (NMOS) crystals. tube.
- NMOS N-type metal oxide semiconductor
- the transistor in FIG. 6 may be replaced by a P-type metal oxide semiconductor (PMOS) transistor, and accordingly, the timing diagrams of the respective input signals are also changed accordingly, and no further description is made here.
- PMOS P-type metal oxide semiconductor
- Embodiments of the present invention also provide a liquid crystal display including the GOA circuit shown in any of FIGS. Please refer to the above description of the GOA circuit shown in FIG. 1 to FIG. 6, and details are not described herein again.
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Abstract
公开了一种GOA电路,包括级联的多个GOA单元,第N级GOA单元控制对第N级水平扫描线充电,第N级GOA单元的下拉维持电路(600)包括第N控制电路(601)、第N维持电路(602)和第N共享电路(603);第N+4级GOA单元的下拉维持电路(600')包括第(N+4)控制电路(601')、第(N+4)维持电路(602')和第N共享电路(603);第N控制电路(601)的第一控制端Q(N)和接有第一控制信号(LC1)的第二控制端(6012)调控其输出端P(N)的电位;第(N+4)控制电路(601')的第一控制端Q(N+4)和接有低频控制信号(LC2)的第二控制端(6014)调控其输出端P(N+4)的电位;当P(N)和P(N+4)均为高电位时,第N共享电路(603)工作,将Q(N)与Q(N+4)的电位共享,将第N级、第N+4级水平扫描线的电位共享。
Description
本发明要求2016年07月21日递交的发明名称为“一种GOA电路及液晶显示器”的申请号201610587413.3的在先申请的优先权,上述在先申请的内容以引入的方式并入本文本中。
本发明涉及液晶显示技术领域,具体涉及一种GOA电路及一种液晶显示器。
阵列基板行驱动(Gate Driver On Array,GOA)技术,是一种将薄膜晶体管(Thin Film Transistor,TFT)的栅极扫描驱动电路制作在阵列基板上,以替代外接硅芯片制作的驱动芯片的一种技术。由于GOA电路可直接制作在面板周围,如此不但可以降低液晶显示器(Liquid Crystal Display,LCD)的面板的边框厚度,简化制程工艺,还可以降低产品成本,提高液晶面板的集成度。
现有的GOA电路,通常包括级联的多个GOA单元,每一级GOA单元包括上拉控制电路、上拉电路、下传电路、下拉电路、自举电容和下拉维持电路以及负责电位抬升的自举(Boast)电容。其中,所述上拉控制电路负责控制所述上拉电路的打开,一般连接前面级GOA电路传递过来的下传信号或者Gate信号;所述上拉电路主要负责将输入的时钟信号(Clock)输出为栅极(Gate)信号;所述下拉电路负责在输出扫描驱动信号后,快速将该扫描驱动信号(也即是TFT栅极的电位)拉低为低电平,即关闭Gate信号;所述下拉维持电路则主要负责将扫描驱动信号和上拉电路的Gate信号(通常称为Q点)维持在关闭状态(即负电位),通常有两个下拉维持模块交替作用;所述自举电容则负责Q点的二次抬升。
现有技术中的GOA电路结构基本是将上述GOA单元的上拉电路、上拉控制电路等几部分放置在同一级GOA单元中,尤其是两个下拉维持电路是交
替作用在同一级GOA电路的。然而,每一级GOA单元的下拉维持电路之间都相同且各自独立,而且相邻两级GOA单元的下拉维持电路之间无相互作用,导致电路实际作用效率较低。另外,由于每一级GOA单元的下拉维持电路包含较多的TFT元件,这样不但会导致GOA单元整体尺寸过大,增加GOA电路所占用的设计空间,同时也会增加电路功耗。
发明内容
本发明实施例提供一种GOA电路及液晶显示器,可以实现每两级GOA电路共享下拉维持电路,从而缩减GOA电路中TFT的数量,以减少GOA电路所占用的设计空间。
第一方面,本发明实施例提供了一种阵列基板行驱动(Gate Driver On Array,GOA)电路,所述GOA电路包括级联的多个GOA单元,第N级GOA单元用于控制对第N级水平扫描线G(N)充电,第(N+4)级GOA单元用于控制对第(N+4)级水平扫描线G(N+4)充电,其中:
所述第N级GOA单元包括第N下拉维持电路;第(N+4)级GOA单元包括第(N+4)下拉维持电路;所述第N下拉维持电路包括第N控制电路、第N维持电路和与所述第(N+4)下拉维持电路共有的第N共享电路;所述第(N+4)下拉维持电路包括第(N+4)控制电路、第(N+4)维持电路和与所述第N下拉维持电路共有的所述第N共享电路;
第N控制电路具有第一控制端Q(N)和第二控制端,所述第N控制电路的第二控制端接入第一低频控制信号,所述第N控制电路的第一控制端Q(N)和所述第一低频控制信号用于控制所述第N控制电路的输出端P(N)的电位为高电位或者低电位;所述第N维持电路电性连接所述第N控制电路的输出端P(N)、第一控制端Q(N)和所述第N级水平扫描线G(N),用于在所述第N控制电路的输出端P(N)为高电位时,维持所述第N控制电路的第一控制端Q(N)和所述第N级水平扫描线G(N)的电位为低电位;
第(N+4)控制电路具有第一控制端Q(N+4)和第二控制端,所述第(N+4)控制电路的第二控制端接入第二低频控制信号,所述第(N+4)控制电路的第一控制端Q(N+4)和所述第二低频控制信号用于控制所述第(N+4)控制电
路的输出端P(N+4)为高电位或者低电位;所述第(N+4)维持电路电性连接所述第(N+4)控制电路的输出端P(N+4)、第一控制端Q(N+4)和所述第(N+4)级水平扫描线G(N+4),用于在所述第(N+4)控制电路的输出端P(N+4)为高电位时,维持所述第(N+4)控制电路的第一控制端Q(N+4)和所述第(N+4)级水平扫描线G(N+4)的电位为低电位;其中,所述第一低频控制信号和第二低频控制信号的相位相反;
当所述第N控制电路的输出端P(N)为高电位,并且所述第(N+4)控制电路的输出端P(N+4)为高电位时,所述第N共享电路工作,将所述第N控制电路的第一控制端Q(N)的电位与所述第(N+4)控制电路的第一控制端Q(N+4)的电位共享,均维持在低电位,所述第N共享电路将所述第N级水平扫描线G(N)的电位与所述第(N+4)级水平扫描线G(N+4)的电位共享,均维持在低电位。
其中,当所述第N控制电路的输出端P(N)为低电位时,或者所述第(N+4)控制电路的输出端P(N+4)为低电位时,所述第N共享电路停止工作。
其中,所述共享电路包括第六十一晶体管、第六十二晶体管、第六十三晶体管和第六十四晶体管,其中:
所述第六十一晶体管的栅极和所述第六十三晶体管的栅极电性连接所述第N控制电路的输出端P(N),所述第六十一晶体管的源级电性连接所述第N控制电路的第一控制端Q(N),所述第六十一晶体管的漏级电性连接所述第六十二晶体管的漏级;所述第六十二晶体管的源级电性连接所述第(N+4)控制电路的第一控制端Q(N+4),所述第六十二晶体管的栅极和所述第六十四晶体管的栅极电性连接所述第(N+4)控制电路的输出端P(N+4);所述第六十三晶体管的源级电性连接所述第(N+4)级水平扫描线G(N+4),所述第六十三晶体管的漏级电性连接所述第六十四晶体管的漏级,所述第六十四晶体管的源极电性连接所述第N级水平扫描线G(N)。
其中,所述第N控制电路包括第五十一晶体管、第五十二晶体管、第五十三晶体管和第五十四晶体管,其中:
所述第五十一晶体管的栅极、所述第五十一晶体管的漏极、所述第五十三晶体管的漏极电性连接所述第N控制电路的第二控制端,所述第五十一晶体
管的源极电性连接所述第五十二晶体管的漏极和所述第五十三晶体管的栅极,所述第五十二晶体管的栅极电性连接所述第N控制电路的第一控制端Q(N),所述第五十三晶体管的源极电性连接所述第五十四晶体管的漏极和所述第N控制电路的输出端P(N),所述第五十二晶体管的源极和所述第五十四晶体管的源极输入直流低电压;
当所述第N控制电路的第一控制端Q(N)为低电位时,若所述第N控制电路的第二控制端为高电位,则所述第N控制电路的输出端P(N)为高电位;
当所述第N控制电路的第一控制端Q(N)为低电位时,若所述第N控制电路的第二控制端从高电位变为低电位,则所述第N控制电路的输出端P(N)为高电位。
其中,所述第N维持电路包括第三十二晶体管和第四十二晶体管,其中:
所述第三十二晶体管的栅极和所述第四十二晶体管的栅极电性连接所述第N控制电路的输出端P(N),所述第三十二晶体管的漏极电性连接所述第N级水平扫描线G(N),所述第四十二晶体管的漏极电性连接所述第N控制电路的第一控制端Q(N),所述第三十二晶体管的源极和所述第四十二晶体管的源极输入所述直流低电压;
当所述第N控制电路的输出端P(N)为高电位时,所述第N级水平扫描线G(N)和所述第N控制电路的第一控制端Q(N)维持低电位。
所述第(N+4)控制电路包括第五十五晶体管、第五十六晶体管、第五十七晶体管和第五十八晶体管,其中:
所述第五十五晶体管的栅极、所述第五十五晶体管的漏极、所述第五十七晶体管的漏极电性连接所述第(N+4)控制电路的第二控制端,所述第五十五晶体管的源极电性连接所述第五十六晶体管的漏极和所述第五十七晶体管的栅极,所述第五十六晶体管的栅极电性连接所述第(N+4)控制电路的第一控制端Q(N+4),所述第五十七晶体管的源极电性连接所述第五十八晶体管的漏极和所述第(N+4)控制电路的输出端P(N+4),所述第五十六晶体管的源极和所述第五十八晶体管的源极输入直流低电压;
当所述第(N+4)控制电路的第一控制端Q(N+4)为低电位时,若所述
第(N+4)控制电路的第二控制端为高电位,则所述第(N+4)控制电路的输出端P(N+4)为高电位;
当所述第(N+4)控制电路的第一控制端Q(N+4)为低电位时,若所述第(N+4)控制电路的第二控制端从高电位变为低电位,则所述第(N+4)控制电路的输出端P(N+4)为高电位。
其中,所述第(N+4)控制电路包括第五十五晶体管、第五十六晶体管、第五十七晶体管和第五十八晶体管,其中:
所述第五十五晶体管的栅极、所述第五十五晶体管的漏极、所述第五十七晶体管的漏极电性连接所述第(N+4)控制电路的第二控制端,所述第五十五晶体管的源极电性连接所述第五十六晶体管的漏极和所述第五十七晶体管的栅极,所述第五十六晶体管的栅极电性连接所述第(N+4)控制电路的第一控制端Q(N+4),所述第五十七晶体管的源极电性连接所述第五十八晶体管的漏极和所述第(N+4)控制电路的输出端P(N+4),所述第五十六晶体管的源极和所述第五十八晶体管的源极输入直流低电压;
当所述第(N+4)控制电路的第一控制端Q(N+4)为低电位时,若所述第(N+4)控制电路的第二控制端为高电位,则所述第(N+4)控制电路的输出端P(N+4)为高电位;
当所述第(N+4)控制电路的第一控制端Q(N+4)为低电位时,若所述第(N+4)控制电路的第二控制端从高电位变为低电位,则所述第(N+4)控制电路的输出端P(N+4)为高电位。
其中,所述第(N+4)维持电路包括第三十三晶体管和第四十三晶体管,其中:
所述第三十三晶体管的栅极和所述第四十三晶体管的栅极电性连接所述第(N+4)控制电路的输出端P(N+4),所述第三十三晶体管的漏极电性连接所述第N级水平扫描线G(N+4),所述第四十三晶体管的漏极电性连接所述第(N+4)控制电路的第一控制端Q(N+4),所述第三十三晶体管的源极和所述第四十三晶体管的源极输入所述直流低电压;
当所述第(N+4)控制电路的输出端P(N+4)为高电位时,所述第(N+4)级水平扫描线G(N+4)和所述第(N+4)控制电路的第一控制端Q(N+4)
维持低电位。
其中,所述第N级GOA单元还包括第N上拉控制电路、第N上拉电路、第N下传电路、第N下拉电路和第N自举电容,其中:
所述第N上拉控制电路电性连接所述第N控制电路的第一控制端Q(N),第N上拉控制电路接入第N-2级GOA单元产生的下传信号ST(N-2)和第(N-2)级水平扫描线G(N-2);
所述第N上拉电路和第N下传电路分别电性连接所述第N控制电路的第一控制端Q(N),所述第N上拉电路与所述第N级水平扫描线G(N)电性连接,所述第N下传电路输出第N级GOA单元产生的下传信号ST(N),所述第N上拉电路和第N下传电路均接入对应所述第N级GOA单元的时钟信号;
所述第N自举电容的一端电性连接于所述第N控制电路的第一控制端Q(N),另一端电性连接所述第N级水平扫描线G(N);
所述第N下拉电路分别电性连接所述第N控制电路的第一控制端Q(N)和第N级水平扫描线G(N),所述第N下拉电路还接入所述直流低电压,所述第N下拉电路还连接第(N+2)级水平扫描线G(N+2)。
其中,在第(N+4)级GOA单元中,所述第(N+4)级GOA单元还包括第(N+4)上拉控制电路、第(N+4)上拉电路、第(N+4)下传电路、第(N+4)下拉电路和第(N+4)自举电容;
第(N+4)上拉控制电路接入第(N+2)级GOA单元产生的下传信号ST(N+2)和第(N+2)级水平扫描线G(N+2),所述第(N+4)上拉控制电路电性连接所述第(N+4)控制电路的第一控制端Q(N+4);
所述第(N+4)上拉电路和第(N+4)下传电路分别电性连接所述第(N+4)控制电路的第一控制端Q(N+4),所述第(N+4)上拉电路与所述第(N+4)级水平扫描线G(N+4)电性连接,所述第(N+4)下传电路输出第(N+4)级GOA单元产生的下传信号ST(N+4),所述第(N+4)上拉电路和第(N+4)下传电路均接入对应所述第(N+4)级GOA单元的时钟信号;
所述第(N+4)自举电容的一端电性连接于第N+4级栅极信号点Q(N+4),另一端电性连接所述第(N+4)级水平扫描线G(N+4);
所述第(N+4)下拉电路分别电性连接所述第(N+4)控制电路的第一控制端Q(N+4)和第(N+4)级水平扫描线G(N+4),所述第(N+4)下拉电路还接入所述直流低电压,所述第(N+4)下拉电路还连接第(N+6)级水平扫描线G(N+6)。
其中,每个GOA单元接入的时钟信号为第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号中的一个,其中,接入所述第N级GOA单元的时钟信号和接入所述第(N+4)级GOA单元的时钟信号相同。
其中,所述第一低频控制信号和第二低频控制信号的周期为每个GOA单元接入的时钟信号周期的2倍。
其中,在第一级和第二级GOA单元中,所述上拉控制电路接入一扫描启动信号;在最后一级和倒数第二级GOA单元中,所述下拉电路接入扫描启动信号。
第二方面,本发明实施例还提供了一种包括上述GOA电路的液晶显示器。
本发明实施例中提供的GOA电路,第N级GOA单元中的第N下拉维持电路包括第N控制电路、第N维持电路和与所述第(N+4)下拉维持电路共有的第N共享电路,第(N+4)级GOA单元的第(N+4)下拉维持电路包括第(N+4)控制电路、第(N+4)维持电路和与所述第N下拉维持电路共有的所述第N共享电路;第N控制电路的第一控制端Q(N)以及第二控制端接入的第一低频控制信号LC1可以控制所述第N控制电路的输出端P(N)的电位;第(N+4)控制电路的第一控制端Q(N+4),以及第二控制端接入的第二低频控制信号LC2可以控制所述第(N+4)控制电路的输出端P(N+4)的电位;当所述第N控制电路的输出端P(N)和所述第(N+4)控制电路的输出端P(N+4)均为高电位时,所述第N共享电路工作,将所述第N控制电路的第一控制端Q(N)的电位与所述第(N+4)控制电路的第一控制端Q(N+4)的电位共享,以及将所述第N级水平扫描线G(N)的电位与所述第(N+4)级水平扫描线G(N+4)的电位共享,这样可使第N级GOA单元和第(N+4)级GOA单元交替被第N下拉维持电路和第(N+4)下拉维持电路下拉,提高GOA电路的实际作用效率。另外,第N级GOA单元、第(N+4)级GOA单元之间共享电路的存在,还可以缩减GOA电路中薄膜晶体管的数目,减少GOA
电路所占用的设计空间。
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1是本发明实施例公开的一种GOA电路的示意图;
图2是本发明实施例公开的另一种GOA电路的示意图;
图3是本发明实施例公开的另一种GOA电路的示意图;
图4是本发明实施例公开的另一种GOA电路的示意图;
图5是本发明实施例中时钟信号的时序图,以及时钟信号与各GOA单元的对应关系示意;
图6是本发明实施例公开的另一种GOA电路的示意图;
图7是图6中所示电路结构的输入信号和各个关键节点的波形示意图。
下面将结合本发明实施方式中的附图,对本发明实施方式中的技术方案进行清楚、完整地描述。显然,所描述的实施方式是本发明的一部分实施方式,而不是全部实施方式。基于本发明中的实施方式,本领域普通技术人员在没有做出创造性劳动的前提下所获得的所有其他实施方式,都应属于本发明保护的范围。
此外,以下各实施例的说明是参考附加的图示,用以例示本发明可用以实施的特定实施例。本发明中所提到的方向用语,例如,“上”、“下”、“前”、“后”、“左”、“右”、“内”、“外”、“侧面”等,仅是参考附加图式的方向,因此,使用的方向用语是为了更好、更清楚地说明及理解本发明,而不是指示或暗指所指的装置或元件必须具有特定的方位、以特定的方位构造和操作,因此不能理解为对本发明的限制。
在本发明的描述中,需要说明的是,除非另有明确的规定和限定,术语“安
装”、“相连”、“连接”应做广义理解,例如,可以是固定连接,也可以是可拆卸地连接,或者一体地连接;可以是机械连接;可以是直接相连,也可以通过中间媒介间接相连,可以是两个元件内部的连通。对于本领域的普通技术人员而言,可以具体情况理解上述术语在本发明中的具体含义。
此外,在本发明的描述中,除非另有说明,“多个”的含义是两个或两个以上。若本说明书中出现“工序”的用语,其不仅是指独立的工序,在与其它工序无法明确区别时,只要能实现所述工序所预期的作用则也包括在本用语中。另外,本说明书中用“~”表示的数值范围是指将“~”前后记载的数值分别作为最小值及最大值包括在内的范围。在附图中,结构相似或相同的单元用相同的标号表示。
本发明实施例提供了一种GOA电路及液晶显示器,可以实现每两级GOA电路共享下拉维持电路,电路实际作用效率较低,还从而缩减GOA电路中TFT的数量,以减少GOA电路所占用的设计空间。以下分别进行详细说明。
请查阅图1,图1是本发明实施例公开的一种阵列基板行驱动GOA电路的示意图。
在本实施例中,所述GOA电路包括多个级联的GOA单元(例如,第1级GOA单元、第2级GOA单元...第N级GOA单元、第N+1级GOA单元、第N+4级GOA单元,其中,N为大于等于1的整数),每一级GOA单元均对应一行薄膜晶体管(Thin Film Transistor,TFT)。每一行TFT的栅极电压可以通过GOA电路提供,第N级GOA单元用于控制对第N级水平扫描线(G(N))充电,第(N+4)级GOA单元用于控制对第(N+4)级水平扫描线G(N+4)充电。当同一行充电完毕后,则该GOA电路将该行的扫描驱动信号关闭,然后再输出开启信号将下一行的TFT打开,并对该行的TFT进行充电。如此依序下去,直至最后一级GOA单元对应的TFT充电完毕。
所述第N级GOA单元包括第N下拉维持电路600;第(N+4)级GOA单元包括第(N+4)下拉维持电路600’;所述第N下拉维持电路600包括第N控制电路601、第N维持电路602,以及第N下拉维持电路600与所述第(N+4)下拉维持电路600’共有的第N共享电路603;所述第(N+4)下拉维持电路600’
包括第(N+4)控制电路601’、第(N+4)维持电路602’,以及所述第(N+4)下拉维持电路600’与所述第N下拉维持电路600共有的所述第N共享电路603;所述N为正整数。
第N控制电路601具有第一控制端Q(N)和第二控制端6012,所述第N控制电路601的第二控制端6012接入第一低频控制信号LC1,所述第N控制电路601的第一控制端Q(N)和所述第一低频控制信号LC1用于控制所述第N控制电路601的输出端P(N)的电位为高电位或者低电位;所述第N维持电路602电性连接所述第N控制电路601的输出端P(N)、第一控制端Q(N)和所述第N级水平扫描线G(N),用于在所述第N控制电路601的输出端P(N)为高电位时,维持所述第N控制电路601的第一控制端Q(N)和所述第N级水平扫描线G(N)的电位为低电位。
第(N+4)控制电路601’具有第一控制端Q(N+4)和第二控制端6014,所述第(N+4)控制电路601’的第二控制端6014接入第二低频控制信号LC2,所述第(N+4)控制电路601’的第一控制端Q(N+4)和所述第二低频控制信号LC2用于控制所述第(N+4)控制电路601’的输出端P(N+4)为高电位或者低电位;所述第(N+4)维持电路602’电性连接所述第(N+4)控制电路601’的输出端P(N+4)、第一控制端Q(N+4)和所述第(N+4)级水平扫描线G(N+4),用于在所述第(N+4)控制电路601’的输出端P(N+4)为高电位时,维持所述第(N+4)控制电路601’的第一控制端Q(N+4)和所述第(N+4)级水平扫描线G(N+4)的电位为低电位;其中,所述第一低频控制信号LC1和第二低频控制信号LC2的相位相反;
当所述第N控制电路601的输出端P(N)为高电位,并且所述第(N+4)控制电路601’的输出端P(N+4)为高电位时,所述第N共享电路603工作,将所述第N控制电路601的第一控制端Q(N)的电位与所述第(N+4)控制电路601’的第一控制端Q(N+4)的电位共享,均维持在低电位,所述第N共享电路603将所述第N级水平扫描线G(N)的电位与所述第(N+4)级水平扫描线G(N+4)的电位共享,均维持在低电位。
其中,当所述第N控制电路601的输出端P(N)为低电位时,或者所述第(N+4)控制电路601’的输出端P(N+4)为低电位时,所述第N共享电
路603停止工作。所述第N共享电路603相当于一与门电路。
在图1描述的电路结构中,第N级GOA单元中的第N下拉维持电路600包括第N控制电路601、第N维持电路602以及第N下拉维持电路600与所述第(N+4)下拉维持电路600’共有的第N共享电路603,第(N+4)级GOA单元的第(N+4)下拉维持电路600’包括第(N+4)控制电路601’、第(N+4)维持电路602’以及所述第(N+4)下拉维持电路600’与所述第N下拉维持电路600共有的所述第N共享电路603;第N控制电路601的第一控制端Q(N)以及第二控制端6012接入的第一低频控制信号LC1可以控制所述第N控制电路601的输出端P(N)的电位;第(N+4)控制电路601’的第一控制端Q(N+4),以及第二控制端6014接入的第二低频控制信号LC2可以控制所述第(N+4)控制电路601’的输出端P(N+4)的电位;当所述第N控制电路601的输出端P(N)和所述第(N+4)控制电路601’的输出端P(N+4)均为高电位时,所述第N共享电路603工作,将所述第N控制电路601的第一控制端Q(N)的电位与所述第(N+4)控制电路601’的第一控制端Q(N+4)的电位共享,以及将所述第N级水平扫描线G(N)的电位与所述第(N+4)级水平扫描线G(N+4)的电位共享,这样可使第N级GOA单元和第(N+4)级GOA单元交替被第N下拉维持电路600和第(N+4)下拉维持电路600’下拉,提高GOA电路的实际作用效率。
请参阅图2,图2是本发明实施例公开的另一种GOA电路的示意图。
如图2所示,本实施例总所示的GOA电路与图1所示的GOA电路的电路架构及组成整体相同,所述GOA电路包括多个级联的GOA单元,每一级GOA单元均对应一行薄膜晶体管。所述第N级GOA单元包括第N下拉维持电路600;第(N+4)级GOA单元包括第(N+4)下拉维持电路600’;所述第N下拉维持电路600包括第N控制电路601、第N维持电路602,以及第N下拉维持电路600与所述第(N+4)下拉维持电路600’共有的第N共享电路603;所述第(N+4)下拉维持电路600’包括第(N+4)控制电路601’、第(N+4)维持电路602’,以及所述第(N+4)下拉维持电路600’与所述第N下拉维持电路600共有的所述第N共享电路603;具体请参看上文对图1所示GOA电路的描述,在此不再赘述。
进一步地,其区别在于,本实施例中所描述的GOA电路中,所述共享电路603包括第六十一晶体管T61、第六十二晶体管T62、第六十三晶体管T63和第六十四晶体管T64,其中:
所述第六十一晶体管T61的栅极和所述第六十三晶体管T63的栅极电性连接所述第N控制电路601的输出端P(N),所述第六十一晶体管T61的源级电性连接所述第N控制电路601的第一控制端Q(N),所述第六十一晶体管T61的漏级电性连接所述第六十二晶体管T62的漏级;所述第六十二晶体管T62的源级电性连接所述第(N+4)控制电路601’的第一控制端Q(N+4),所述第六十二晶体管T62的栅极和所述第六十四晶体管T64的栅极电性连接所述第(N+4)控制电路601’的输出端P(N+4);所述第六十三晶体管T63的源级电性连接所述第(N+4)级水平扫描线G(N+4),所述第六十三晶体管T63的漏级电性连接所述第六十四晶体管T64的漏级,所述第六十四晶体管T64的源极电性连接所述第N级水平扫描线G(N)。所述共享电路603相当于一与门电路,只有当所述第N控制电路601的输出端P(N)和所述第(N+4)控制电路601’的输出端P(N+4)均为高电位时,所述第N共享电路603才工作。
请参阅图3,图3是本发明实施例公开的另一种GOA电路的示意图。如图3所示,本实施例总所示的GOA电路与图1及图2所示的GOA电路的电路架构及组成整体相同,具体请参看上文对图1及图2所示GOA电路的描述,在此不再赘述。进一步地,其区别在于,本实施例中所描述的GOA电路中,所述第N控制电路601包括第五十一晶体管T51、第五十二晶体管T52、第五十三晶体管T53和第五十四晶体管T54,其中:
所述第五十一晶体管T51的栅极、所述第五十一晶体管T51的漏极、所述第五十三晶体管T53的漏极电性连接所述第N控制电路601的第二控制端6012,即接入第一低频控制信号LC1,所述第五十一晶体管T51的源极电性连接所述第五十二晶体管T52的漏极和所述第五十三晶体管T53的栅极,所述第五十二晶体管T52的栅极电性连接所述第N控制电路601的第一控制端Q(N),所述第五十三晶体管T53的源极电性连接所述第五十四晶体管T54
的漏极和所述第N控制电路601的输出端P(N),所述第五十二晶体管T52的源极和所述第五十四晶体管T54的源极输入直流低电压Vss。
当所述第N控制电路601的第一控制端Q(N)为高电位时,所述第五十二晶体管T52和第五十四晶体管T54打开,将所述第N控制电路601的输出端P(N)拉低为低电位。
当所述第N控制电路601的第一控制端Q(N)为低电位时,若所述第N控制电路601的第二控制端6012接入的第一低频控制信号LC1为高电位,所述第五十一晶体管T51和第五十三晶体管T53打开,则所述第N控制电路601的输出端P(N)为高电位。
当所述第N控制电路601的第一控制端Q(N)为低电位时,若所述第N控制电路601的第二控制端6012接入的第一低频控制信号LC1从高电位变为低电位,第五十一晶体管T51、第五十二晶体管T52、第五十三晶体管T53和第五十四晶体管T54均关闭,但由于上一时段第一低频控制信号LC1是处于高电位、所述第N控制电路601的输出端P(N)为高电位,则此时段所述第N控制电路601的输出端P(N)维持上一时段的电位状态,即P(N)为高电位。
进一步地,所述第N维持电路602包括第三十二晶体管T32和第四十二晶体管T42,其中:
所述第三十二晶体管T32的栅极和所述第四十二晶体管T42的栅极电性连接所述第N控制电路601的输出端P(N),所述第三十二晶体管T32的漏极电性连接所述第N级水平扫描线G(N),所述第四十二晶体管T42的漏极电性连接所述第N控制电路601的第一控制端Q(N),所述第三十二晶体管T32的源极和所述第四十二晶体管T42的源极输入所述直流低电压Vss;
当所述第N控制电路601的输出端P(N)为高电位时,所述第三十二晶体管T32和第四十二晶体管T42打开,将所述第N级水平扫描线G(N)和所述第N控制电路601的第一控制端Q(N)维持在低电位。
进一步地,所述第(N+4)控制电路601’包括第五十五晶体管T55、第五十六晶体管T56、第五十七晶体管T57和第五十八晶体管T58,其中:
所述第五十五晶体管T55的栅极、所述第五十五晶体管T55的漏极、所
述第五十七晶体管T57的漏极电性连接所述第(N+4)控制电路601’的第二控制端6014,即接入第二低频控制信号LC2,所述第五十五晶体管T55的源极电性连接所述第五十六晶体管T56的漏极和所述第五十七晶体管T57的栅极,所述第五十六晶体管T56的栅极电性连接所述第(N+4)控制电路601’的第一控制端Q(N+4),所述第五十七晶体管T57的源极电性连接所述第五十八晶体管T58的漏极和所述第(N+4)控制电路601’的输出端P(N+4),所述第五十六晶体管T56的源极和所述第五十八晶体管T58的源极输入直流低电压Vss。
当所述第(N+4)控制电路601’的第一控制端Q(N+4)为高电位时,所述第五十六晶体管T56和第五十八晶体管T58打开,将所述第(N+4)控制电路601’的输出端P(N+4)拉低成低电位。
当所述第(N+4)控制电路的第一控制端Q(N+4)为低电位时,若所述第N控制电路601的第二控制端6014接入的第二低频控制信号LC2为高电位,所述第五十五晶体管T55和第五十七晶体管T57打开,则所述第N控制电路601的输出端P(N+4)为高电位。
当所述第(N+4)控制电路的第一控制端Q(N+4)为低电位时,若所述第(N+4)控制电路的第二控制端6014接入的第二低频控制信号LC2从高电位变为低电位,则所述第五十五晶体管T55、第五十六晶体管T56、第五十七晶体管T57和第五十八晶体管T58均关闭,但由于上一时段第二低频控制信号LC2是处于高电位、所述第(N+4)控制电路601的输出端P(N+4)为高电位,则此时段所述第(N+4)控制电路601’的输出端P(N+4)维持上一时段的电位状态,即P(N+4)为高电位。
进一步地,所述第(N+4)维持电路602’包括第三十三晶体管T33和第四十三晶体管T43,其中:
所述第三十三晶体管T33的栅极和所述第四十三晶体管T43的栅极电性连接所述第(N+4)控制电路601’的输出端P(N+4),所述第三十三晶体管T33的漏极电性连接所述第N级水平扫描线G(N+4),所述第四十三晶体管T43的漏极电性连接所述第(N+4)控制电路601’的第一控制端Q(N+4),所述第三十三晶体管T33的源极和所述第四十三晶体管T43的源极输入所述
直流低电压Vss。
当所述第(N+4)控制电路的输出端P(N+4)为高电位时,所述第三十三晶体管T33和第四十三晶体管T43打开,将所述第(N+4)级水平扫描线G(N+4)和所述第(N+4)控制电路601’的第一控制端Q(N+4)维持在低电位。
请参阅图4,图4是本发明实施例公开的一种GOA电路的电路示意图。
其中,所述第N级GOA单元还包括第N上拉控制电路100、第N上拉电路200、第N下传电路300、第N下拉电路400和第N自举电容500。其中,所述第N上拉控制电路100、第N上拉电路200、第N下传电路300、第N下拉电路400和第N自举电容500分别连接所述第N控制电路601的第一控制端Q(N),所述第N上拉电路200、第N下拉电路400和第N自举电容500分别与所述第N级水平扫描线G(N)电性连接。
所述第N上拉控制电路100电性连接所述第N控制电路601的第一控制端Q(N),第N上拉控制电路100接入第(N-2)级GOA单元产生的下传信号ST(N-2)和第(N-2)级水平扫描线G(N-2);
所述第N上拉电路200和第N下传电路300分别电性连接所述第N控制电路601的第一控制端Q(N),所述第N上拉电路200与所述第N级水平扫描线G(N)电性连接,所述第N下传电路300输出第N级GOA单元产生的下传信号ST(N),所述第N上拉电路200和第N下传电路300均接入对应所述第N级GOA单元的时钟信号;
所述第N自举电容500包括一电容Cb1,所述电容Cb1的一端电性连接所述第N控制电路601的第一控制端Q(N),另一端电性连接所述第N级水平扫描线G(N);
所述第N下拉电路400分别电性连接所述第N控制电路601的第一控制端Q(N)和第N级水平扫描线G(N),所述第N下拉电路400还接入所述直流低电压Vss,所述第N下拉电路400还接入第(N+2)级水平扫描线G(N+2)。
类似地,在第(N+4)级GOA单元中:所述第(N+4)级GOA单元还包
括第(N+4)上拉控制电路100’、第(N+4)上拉电路200’、第(N+4)下传电路300’、第(N+4)下拉电路400’和第(N+4)自举电容500’。其中,所述第(N+4)上拉控制电路100’、第(N+4)上拉电路200’、第(N+4)下传电路300’、第(N+4)下拉电路400’和第(N+4)自举电容500’分别连接所述第(N+4)控制电路601’的第一控制端Q(N+4),所述第(N+4)上拉电路200’、第(N+4)下拉电路400’和第(N+4)自举电容500’分别与所述第(N+4)级水平扫描线G(N+4)电性连接。
第(N+4)上拉控制电路100’接入第(N+2)级GOA单元产生的下传信号ST(N+2)和第(N+2)级水平扫描线G(N+2),所述第(N+4)上拉控制电路电性连接所述第(N+4)控制电路601’的第一控制端Q(N+4);
所述第(N+4)上拉电路200’和第(N+4)下传电路300’分别电性连接所述第(N+4)控制电路601’的第一控制端Q(N+4),所述第(N+4)上拉电路200’与所述第(N+4)级水平扫描线G(N+4)电性连接,所述第(N+4)下传电路300’输出第(N+4)级GOA单元产生的下传信号ST(N+4),所述第(N+4)上拉电路200’和第(N+4)下传电路300’均接入对应所述第(N+4)级GOA单元的时钟信号;
所述第(N+4)自举电容500’包括一电容Cb2,所述电容Cb2的一端电性连接于第N+4级栅极信号点Q(N+4),另一端电连接于所述第(N+4)级水平扫描线G(N+4);
所述第(N+4)下拉电路400’分别电性连接所述第(N+4)控制电路601’的第一控制端Q(N+4)和第(N+4)级水平扫描线G(N+4),所述第(N+4)下拉电路400’还接入所述直流低电压Vss,所述第(N+4)下拉电路400’还连接第(N+6)级水平扫描线G(N+6)。
该GOA电路采用的级传方式是第N-2级传给第N级。ST信号为GOA电路的启动信号,只是在开始扫描的时候打开,后面一直处于低电位。ST信号负责启动第一级和第二级GOA单元,而后面的第N级GOA电路的启动信号由前面第N-2级电路的下传电路部分的ST(N-2)信号负责产生,这样就可以逐级打开GOA驱动电路,实现行扫描驱动。
第N级GOA单元接收第N-2级GOA单元产生的下传信号ST(N-2)、第
N-2级GOA单元产生的扫描驱动信号G(N-2)、第N+2级GOA单元产生的扫描驱动信号G(N+2),以及直流低电压Vss、时钟信号CK1~CK4中的1个CK信号,第N级GOA单元通过不同的晶体管输出扫描驱动信号G(N)和下传信号ST(N)。这样的结构方式可以保证GOA信号逐级传递,是各扫描线被逐级充电。由于第(N-2)级GOA单元的下传信号ST(N-2)和扫描驱动信号G(N-2)均是依据同一条时钟而输出,所以ST(N-2)和G(N-2)的时序和电位相同。在本发明的另外一种实施方式中,第N级GOA单元的上拉控制电路可以接收第N-2级GOA单元产生的下传信号ST(N-2)和第N-2级GOA单元产生的扫描驱动信号G(N-2)中的任一个信号即可。
该GOA电路包括多个级联的GOA单元,GOA电路还包括设置在各GOA单元***的第一低频控制信号LC1、第二低频控制信号LC2,直流低电压VSS,以及四条时钟信号号CK1、CK2、CK3、CK4的金属线。
在GOA电路中,一般使用时钟信号控制每一行TFT开启或关闭,通过上拉电路将时钟信号输出至每个GOA单元的水平扫描线。不同的时钟信号(如CK-1、CK-2、CK-3…CK-m等)可以同时输出至GOA电路包括的多个级联的GOA单元,以便将该时钟信号输出至TFT的栅极。例如,时钟信号CK1、CK2、CK3、CK4分别输入到第N级、第N+1级、N+2级、N+3级GOA单元的上拉电路,以分别对显示区域相应的水平扫描线进行充电。
图5是本发明实施例中时钟信号的时序图,以及时钟信号与各GOA单元的对应关系示意。本实施例中,每个GOA单元接入的时钟信号为第一时钟信号CK1、第二时钟信号CK2、第三时钟信号CK3和第四时钟信号CK4中的一个,其中,第一时钟信号CK1和第三时钟信号CK3完全相反。时序上输入到第N级和第N+4级GOA单元的时钟信号刚刚相同(请参看图5的CK信号图),可以避免共享Q点后产生的错充问题。以下均以第N级GOA单元接入时钟信号CK1为例进行介绍。
其中,所述第一低频控制信号LC1和第二低频控制信号LC2的相位相反。LC1、LC2的周期刚好是时钟信号号CK(m)的2倍。CK信号占空比(Duty Ratio)为50%。
进一步地,请参阅图6,图6是本发明实施例公开的一种GOA电路中第
N级GOA单元和第(N+4)级GOA单元的电路图。如图6所示,第N+4级GOA单元的电路图与第N级GOA单元的结构类似,具体请参看上文图1-图4中的相关描述,在此不再赘述。
其中,第N级GOA单元的结构包括:第N上拉控制电路100、第N上拉电路200、第N下传电路300、第N下拉电路400、第N自举电容500和第N下拉维持电路。其中,第N下拉维持电路包括第N控制电路601、第N维持电路602和第N共享电路603。
所述第N共享电路603包括第六十一晶体管T61、第六十二晶体管T62、第六十三晶体管T63和第六十四晶体管T64,其中,共享电路中第六十一晶体管T61的栅极和第六十三晶体管T63的栅极电性连接第N级GOA单元中第N控制电路601的输出端P(N),第六十一晶体管T61的源级电性连接该第N控制电路601的第一控制端Q(N),第六十一晶体管T61的漏级电性连接第六十二晶体管T62的漏级;第六十二晶体管T62的源级电性连接该第N级GOA单元的后四级GOA单元(即第(N+4级)GOA单元)电路中第(N+4)控制电路601’的第一控制端Q(N+4),第六十二晶体管T62的栅极和第六十四晶体管T64的栅极电性连接于第N+4级GOA单元中第(N+4)控制电路601’的输出端P(N+4);第六十三晶体管T63的源级电性连接第(N+4)级GOA单元的输出端G(N+4),即第(N+4)级水平扫描线G(N+4),第六十三晶体管T63的漏级电性连接第六十四晶体管T64的漏级,第六十四晶体管T64的源极电性连接第N级水平扫描线G(N)。
所述第N控制电路601包括第五十一晶体管T51、第五十二晶体管T52、第五十三晶体管T53和第五十四晶体管T54,其中,第五十一晶体管T51,其栅极、漏极均输入第一低频控制信号LC1;第五十二晶体管T52,其栅极电性连接所述第N控制电路601的第一控制端Q(N),源极输入直流低电压Vss;第五十三晶体管T53,其漏极输入第一低频控制信号LC1,源极电性连接第N控制电路601的输出端P(N),其中,第五十一晶体管T51的源极、第五十二晶体管T52的漏极、第五十三晶体管T53的栅极这三者电性连接在一起;第五十四晶体管T54,其栅极电性连接该第N控制电路601的第一控制端Q(N),漏极电性连接第N控制电路601的输出端P(N),源极输入直流低电
压Vss。
所述第N维持电路602包括第三十二晶体管T32和第四十二晶体管T42,其中,第三十二晶体管T32,其栅极电性连接第N控制电路601的输出端P(N),漏极电性连接第N级GOA单元的输出端G(N),源极输入直流低电压Vss;第四十二晶体管T42,其栅极电性连接第N控制电路601的输出端P(N),漏极电性连接第N控制电路601的第一控制端Q(N),源极输入直流低电压Vss。
由第N控制电路601、第N维持电路602和第N共享电路603所组成的下拉维持模块600主要负责维持Q(N)和G(N)的低电位。
该第N上拉控制电路100包括第十一晶体管T11,所述第十一薄膜晶体管T11的栅极输入来自该第N级GOA单元的前两级GOA单元(第(N-2)级GOA单元)电路的下传信号ST(N-2),漏极和源极分别电性连接第(N-2)级水平扫描线G(N-2)和所述第N控制电路的第一控制端Q(N);该第N上拉控制电路100用于对Q(N)的电位进行控制。
该第N上拉电路200包括第二十一晶体管T21,该第二十一晶体管T21的栅极电性连接于所述第N控制电路的第一控制端Q(N),漏极接入对应所述第N级GOA单元的时钟信号,源极电性连接第N级水平扫描线G(N),即该第N级GOA单元的输出端G(N)。该上拉电路200用于根据该第N控制电路的第一控制端Q(N)的电位和该第N级GOA单元接入的时钟信号的电位来控制该第N级GOA单元输出扫描驱动信号G(N)。
该第N下传电路300包括第二十二晶体管T22,该第二十二晶体管T22的栅极电性连接所述第N控制电路601的第一控制端Q(N),漏极接入对于对应该第N级GOA单元的时钟信号,源极输出第N级下传信号ST(N)。该第N下传电路300用于根据该第N控制电路601的第一控制端Q(N)的电位和该第N级GOA单元接入的时钟信号的电位控制输出该第N级GOA单元输出第N级下传信号ST(N)。
该第N下拉电路400包括第四十一晶体管T41和第三十一晶体管T31,第四十一晶体管T41和第三十一晶体管T31的栅极均电性连接于该第N级GOA单元的下两级GOA单元(第N+2级GOA单元)的输出端G(N+2),即第(N+2)级水平扫描线G(N+2),第四十一晶体管T41和第三十一晶体
管T31的源极均输入直流低电压Vss,其中,T41的漏极电性连接该第N级水平扫描线G(N),所述第三十一晶体管T31的漏极电性连接所述第N控制电路的第一控制端Q(N)。该下拉电路400用于在输出扫描驱动信号G(N)后,快速拉低扫描驱动信号G(N)和该第N控制电路601的第一控制端Q(N)的电位。
该自举电容电路500包括一电容Cb1,该电容Cb1的一端电性连接该第N控制电路601的第一控制端Q(N),另一端电性连接所述第N级水平扫描线G(N)。自举电容用于负责Q(N)的二次抬升。
特别地,在第一级GOA单元中,上拉控制电路中的第十一晶体管T11的栅极和漏极均接入扫描启动信号ST,仅第二十一晶体管T21输出该第一级GOA单元的扫描驱动信号G(1),第二十二晶体管T22的源极无输出,即输出低电位。
同样地,在第二级GOA单元中,上拉控制电路中的第十一晶体管T11的栅极和漏极均接入扫描启动信号ST,仅第二十一晶体管T21输出该第一级GOA单元的扫描驱动信号G(2),第二十二晶体管T22的源极无输出,即输出低电位。
另外,在该GOA电路的最后一级和倒数第二级GOA单元中,所述下拉电路中的第四十一晶体管T41和第三十一晶体管T31的栅极均接入扫描启动信号ST。
从上述电路架构来看,晶体管T52、T54的栅极都连接该第N控制电路601的第一控制端Q(N),源极都连接直流低电压Vss,主要用于在Q(N)为高电位时,关闭下拉维持电路,使P(N)处于低电位,T51的栅极连接第一低频控制信号LC1,T51的源极与T53的栅极连接在一起,T53的源极连接第N控制电路601的输出端P(N),主要在Q(N)处于低电位时,通过LC1的高电位来打开T51、T53,使P(N)处于高电位时,维持Q(N)和G(N)的低电位;晶体管T31主要用来放掉Q(N)的电荷;T41主要用来拉低G(N)。
第N级GOA单元G(N)与第(N+4)级GOA单元G(N+4)共享下拉维持电路,共享电路603的功能类似与门电路。其中,第N级GOA单元G(N)只有一组下拉维持电路,靠第一低频控制信号LC1提供驱动信号;G(N+4)
级GOA电路也只有一组下拉维持电路,靠第二低频控制信号LC2提供驱动信号。
基于图6所示的电路,图7是图6中所示电路结构的输入信号和各个关键节点的波形示意图。图6中,ST(N-2)、ST(N)、ST(N+2)、ST(N+4)分别为第(N-2)级GOA单元、第N级GOA单元、第(N+2)级GOA单元、第(N+4)级GOA单元产生的下传信号。
以下按图7中的t1、t2、t3、t4、t5这五个时段来逐个阐述该电路的工作情况:
在t1时段,第一低频控制信号LC1处于低电位、第二低频控制信号LC2处于高电位;由于该第N级、第N+4级GOA单元的启动信号ST(N-2)、ST(N+2)未给,第N控制电路601的第一控制端Q(N)、第(N+4)控制电路601’的第一控制端Q(N+4)均处于低电位,第N级、第(N+4)级GOA单元无扫描驱动信号G(N)和G(N+4)输出,均处于低电位;因LC2处于高电位,所以第(N+4)级GOA单元中的晶体管T55、T57开启,第(N+4)控制电路601’的输出端P(N+4)处于高电位,晶体管T33、T43打开,维持Q(N+4)还是处于Vss的低电位;而对于第N级GOA单元而言,LC1在t1的上一个时刻也处于高电位,使P(N)在上一时刻处于高电位;虽然LC1在t1时刻处于低电位,但由于晶体管T51、T52、T53、T54均关闭,P(N)点仍维持在上一时刻的高电位。因此,在t1时段,P(N)和P(N+4)均处于高电位,由于共享模块内的T61、T63的栅极均连接至P(N),T62、T64的栅极均连接至P(N+4),T61、T62、T63、T64全部打开,使得上下两级GOA电路的Q(N)和Q(N+4)等电位,G(N)和G(N+4)等电位,即均维持在低电位。
在t2时段,第(N+4)级GOA单元的启动信号ST(N+2)一直没有开启,Q(N+4)和G(N+4)一直处于低电位;LC1处于高电位、LC2处于低电位,第N级GOA单元接收第(N-2)级GOA单元产生的下传信号ST(N-2),ST(N-2)先是处于高电位,之后是低电位,G(N-2)与ST(N-2)信号同步,也是先处于高电位,之后是低电位,而CK1信号先是低电位,再是高电位。
t2时段内在ST(N-2)处于高电位时,第N上拉控制电路100中的晶体
管T1打开,G(N-2)的高电平信号传至第N控制电路601的第一控制端Q(N),即Q(N)点因ST(N-2)开启而处于高电位,并对自举电容Cb1的上级板进行充电。由于Q(N)处于高电位,因此T22、T21打开,时钟信号CK1的低电位信号经由T22、T21输出低电位的第N级下传信号ST(N)和扫描驱动信号G(N);另外由于Q(N)处于高电位,晶体管T52、T54打开,P(N)点被拉低至低电位,共享模块内的T61、T63关闭,上下两级GOA单元停止共享,此时因LC2在t2的上一时刻为高电位,P(N+4)仍维持在高电位。
t2时段内在ST(N-2)处于低电位时,虽然ST(N-2)关闭、晶体管T11断开,但Q(N)通过之前充满电荷的自举电容Cb1维持在高电位,使晶体管T22、T21打开,同时有高电位的CK信号输入到该第N级GOA单元,第N级GOA单元输出高电位的第N级下传信号ST(N)和扫描驱动信号G(N),即在t2的后半段输出启动信号给第(N+2)级GOA单元。与此同时,高电位的CK1信号通过晶体管T22继续给自举电容Cb1充电,将Q(N)的电位实现二次抬升。因此,在整个t2时段内,Q(N)均处于高电位。类似地,在t2的后半段,第(N+2)级GOA输出低电位的G(N+2),并在t3时刻开始时,输出高电位的G(N+2)和ST(N+2)。
在t3时段开始时,G(N+2)开始打开,晶体管T31、T41都打开,快速将第N级GOA单元的第N级水平扫描线G(N)拉至低电位,第N控制电路601的第一控制端Q(N)的高电位也会被拉至Vss所处的低电位,即Q(N)点的高电位因G(N+2)下拉而变为低电位,此后一直保持低电位状态,而t3时段内LC1也是低电位,T51、T53处于关闭状态,所以P(N)点仍维持t2时段的低电位,共享模块的与门电路仍然不工作。而Q(N+4)在此时因ST(N+2)、G(N+2)的开启而处于高电位,并对电容Cb2的上级板充电,另外由于Q(N+4)处于高电位,T22’、T21’打开,因在ST(N+2)开启的时间内,CK1处于低电位,第(N+4)级GOA单元输出低电位的第(N+4)级下传信号ST(N+4)和扫描驱动信号G(N+4);另外由于Q(N+4)处于高电位,使晶体管T56、T58打开,P(N+4)被拉至低电位。
这里ST(N+2)在t3时段内只有一半的时间开启,而ST(N+2)在t3时段内处于低电位时,此时有高电位的CK1信号输入到该第(N+4)级GOA单
元,之前充满电荷的Cb2仍可以将晶体管T22’、T21’打开,第(N+4)级GOA单元输出高电位的第N+4级下传信号ST(N+4)和扫描驱动信号G(N+4),即第(N+4)级水平扫描线输出高电位,与此同时,第(N+4)级GOA单元中高电位的CK1信号通过晶体管T22’继续给电容Cb2充电,将Q(N+4)的电位实现二次抬升。
在t4时段,G(N+6)开始打开,晶体管T31’、T41’都打开,快速将第(N+4)级GOA单元中第(N+4)级水平扫描线G(N+4)的电位拉至低电位,Q(N+4)的高电位因G(N+6)下拉而变为Vss所处的低电位,此后一直保持低电位状态;而P(N+4)因LC2处于低电位而仍维持t3时段的低电位,此时第一低频控制信号LC1处于高电位,晶体管T51、T53打开,故P(N)处于高电位,同时晶体管T32、T34也打开,维持Q(N)还是处于Vss的低电位。
在t5时段,第一低频控制信号LC1处于低电位,P(N)点维持t4时段的高电位,因第二低频控制信号LC2变为高电位,P(N+4)也被抬升至高电位,晶体管T33、T43打开,Q(N+4)还是处于Vss的低电位;此时共享电路中的晶体管T61、T62、T63、T64全部打开,与门电路开始工作,上下两级GOA电路共享下拉维持电路,使得上下两级GOA单元的Q(N)和Q(N+4)等电位,G(N)和G(N+4)等电位,即均维持在低电位。
在t5时段之后(从t5到下一帧的t2,其中一帧指将第1级到最后一级GOA单元全部逐级打开所用的时间),在相位相反的第一低频控制信号LC1和第二低频控制信号LC2信号的作用下,P(N)和P(N+4)均处于高电位,共享模块一直维持t5时段的开启状态,上下两级GOA电路的Q(N)和Q(N+4),G(N)和G(N+4)同时被LC1和LC2交替拉低。共享电路的T61、T62、T63、T64这4个晶体管的阈值电压即使有漂移,但其主要起导通共享电路的作用,不影响每两级GOA单元共享下拉维持电路的运行。
另外,从图7中的电路结构看,由于第N级GOA单元和第(N+4)级GOA单元之间存在共享的下拉维持部分,每一级GOA单元只需要13个TFT,对于由多个GOA单元组成的GOA电路来说,可以大大缩减GOA电路中TFT的数目,减少GOA电路所占用的设计空间,实现液晶显示器的更窄边框设计。
优选地,上述图中所有晶体管均为N型金属氧化物半导体(NMOS)晶体
管。
可选地,也可以将图6中的晶体管替换为P型金属氧化物半导体(PMOS)晶体管,相应地也要对各个输入信号的时序图进行相应更改,在此就不再进行赘述。
本发明实施例还提供一种包括图1-图6中任一图所示的GOA电路的液晶显示器。请参看上述对图1-图6所示的GOA电路的描述,在此不再赘述。
在本说明书的描述中,参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施例或示例中。在本说明书中,对上述术语的示意性表述不一定指的是相同的实施例或示例。而且,描述的具体特征、结构、材料或特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上对本发明实施例所提供的共享下拉维持电路的GOA电路及液晶显示器进行了详细介绍,本文中应用了具体个例对本发明的原理及实施方式进行了阐述,以上实施例的说明只是用于帮助理解本发明的方法及其核心思想;同时,对于本领域的一般技术人员,依据本发明的思想,在具体实施方式及应用范围上均会有改变之处,综上所述,本说明书内容不应理解为对本发明的限制。
Claims (20)
- 一种阵列基板行驱动(GOA)电路,所述GOA电路包括级联的多个GOA单元,第N级GOA单元用于控制对第N级水平扫描线G(N)充电,第(N+4)级GOA单元用于控制对第(N+4)级水平扫描线G(N+4)充电,其中,N为正整数;其中,所述第N级GOA单元包括第N下拉维持电路;第(N+4)级GOA单元包括第(N+4)下拉维持电路;所述第N下拉维持电路包括第N控制电路、第N维持电路和与所述第(N+4)下拉维持电路共有的第N共享电路;所述第(N+4)下拉维持电路包括第(N+4)控制电路、第(N+4)维持电路和与所述第N下拉维持电路共有的所述第N共享电路;所述第N控制电路具有第一控制端Q(N)和第二控制端,所述第N控制电路的第二控制端接入第一低频控制信号,所述第N控制电路的第一控制端Q(N)和所述第一低频控制信号用于控制所述第N控制电路的输出端P(N)的电位为高电位或者低电位;所述第N维持电路电性连接所述第N控制电路的输出端P(N)、第一控制端Q(N)和所述第N级水平扫描线G(N),用于在所述第N控制电路的输出端P(N)为高电位时,维持所述第N控制电路的第一控制端Q(N)和所述第N级水平扫描线G(N)的电位为低电位;所述第(N+4)控制电路具有第一控制端Q(N+4)和第二控制端,所述第(N+4)控制电路的第二控制端接入第二低频控制信号,所述第(N+4)控制电路的第一控制端Q(N+4)和所述第二低频控制信号用于控制所述第(N+4)控制电路的输出端P(N+4)为高电位或者低电位;所述第(N+4)维持电路电性连接所述第(N+4)控制电路的输出端P(N+4)、第一控制端Q(N+4)和所述第(N+4)级水平扫描线G(N+4),用于在所述第(N+4)控制电路的输出端P(N+4)为高电位时,维持所述第(N+4)控制电路的第一控制端Q(N+4)和所述第(N+4)级水平扫描线G(N+4)的电位为低电位;其中,所述第一低频控制信号和第二低频控制信号的相位相反;当所述第N控制电路的输出端P(N)为高电位,并且所述第(N+4)控制电路的输出端P(N+4)为高电位时,所述第N共享电路工作,将所述第N 控制电路的第一控制端Q(N)的电位与所述第(N+4)控制电路的第一控制端Q(N+4)的电位共享,均维持在低电位,所述第N共享电路将所述第N级水平扫描线G(N)的电位与所述第(N+4)级水平扫描线G(N+4)的电位共享,均维持在低电位。
- 根据权利要求1所述的GOA电路,其中,当所述第N控制电路的输出端P(N)为低电位时,或者所述第(N+4)控制电路的输出端P(N+4)为低电位时,所述第N共享电路停止工作。
- 根据权利要求1所述的GOA电路,其中,所述共享电路包括第六十一晶体管、第六十二晶体管、第六十三晶体管和第六十四晶体管,其中:所述第六十一晶体管的栅极和所述第六十三晶体管的栅极电性连接所述第N控制电路的输出端P(N),所述第六十一晶体管的源级电性连接所述第N控制电路的第一控制端Q(N),所述第六十一晶体管的漏级电性连接所述第六十二晶体管的漏级;所述第六十二晶体管的源级电性连接所述第(N+4)控制电路的第一控制端Q(N+4),所述第六十二晶体管的栅极和所述第六十四晶体管的栅极电性连接所述第(N+4)控制电路的输出端P(N+4);所述第六十三晶体管的源级电性连接所述第(N+4)级水平扫描线G(N+4),所述第六十三晶体管的漏级电性连接所述第六十四晶体管的漏级,所述第六十四晶体管的源极电性连接所述第N级水平扫描线G(N)。
- 根据权利要求3所述的GOA电路,其中,所述第N控制电路包括第五十一晶体管、第五十二晶体管、第五十三晶体管和第五十四晶体管,其中:所述第五十一晶体管的栅极、所述第五十一晶体管的漏极、所述第五十三晶体管的漏极电性连接所述第N控制电路的第二控制端,所述第五十一晶体管的源极电性连接所述第五十二晶体管的漏极和所述第五十三晶体管的栅极,所述第五十二晶体管的栅极电性连接所述第N控制电路的第一控制端Q(N),所述第五十三晶体管的源极电性连接所述第五十四晶体管的漏极和所述第N 控制电路的输出端P(N),所述第五十二晶体管的源极和所述第五十四晶体管的源极输入直流低电压;当所述第N控制电路的第一控制端Q(N)为低电位时,若所述第N控制电路的第二控制端为高电位,则所述第N控制电路的输出端P(N)为高电位;当所述第N控制电路的第一控制端Q(N)为低电位时,若所述第N控制电路的第二控制端从高电位变为低电位,则所述第N控制电路的输出端P(N)为高电位。
- 根据权利要求4所述的GOA电路,其中,所述第N维持电路包括第三十二晶体管和第四十二晶体管,其中:所述第三十二晶体管的栅极和所述第四十二晶体管的栅极电性连接所述第N控制电路的输出端P(N),所述第三十二晶体管的漏极电性连接所述第N级水平扫描线G(N),所述第四十二晶体管的漏极电性连接所述第N控制电路的第一控制端Q(N),所述第三十二晶体管的源极和所述第四十二晶体管的源极输入所述直流低电压;当所述第N控制电路的输出端P(N)为高电位时,所述第N级水平扫描线G(N)和所述第N控制电路的第一控制端Q(N)维持低电位。
- 根据权利要求3所述的GOA电路,其中,所述第(N+4)控制电路包括第五十五晶体管、第五十六晶体管、第五十七晶体管和第五十八晶体管,其中:所述第五十五晶体管的栅极、所述第五十五晶体管的漏极、所述第五十七晶体管的漏极电性连接所述第(N+4)控制电路的第二控制端,所述第五十五晶体管的源极电性连接所述第五十六晶体管的漏极和所述第五十七晶体管的栅极,所述第五十六晶体管的栅极电性连接所述第(N+4)控制电路的第一控制端Q(N+4),所述第五十七晶体管的源极电性连接所述第五十八晶体管的漏极和所述第(N+4)控制电路的输出端P(N+4),所述第五十六晶体管的源极和所述第五十八晶体管的源极输入直流低电压;当所述第(N+4)控制电路的第一控制端Q(N+4)为低电位时,若所述第(N+4)控制电路的第二控制端为高电位,则所述第(N+4)控制电路的输出端P(N+4)为高电位;当所述第(N+4)控制电路的第一控制端Q(N+4)为低电位时,若所述第(N+4)控制电路的第二控制端从高电位变为低电位,则所述第(N+4)控制电路的输出端P(N+4)为高电位。
- 根据权利要求6所述的GOA电路,其中,所述第(N+4)维持电路包括第三十三晶体管和第四十三晶体管,其中:所述第三十三晶体管的栅极和所述第四十三晶体管的栅极电性连接所述第(N+4)控制电路的输出端P(N+4),所述第三十三晶体管的漏极电性连接所述第N级水平扫描线G(N+4),所述第四十三晶体管的漏极电性连接所述第(N+4)控制电路的第一控制端Q(N+4),所述第三十三晶体管的源极和所述第四十三晶体管的源极输入所述直流低电压;当所述第(N+4)控制电路的输出端P(N+4)为高电位时,所述第(N+4)级水平扫描线G(N+4)和所述第(N+4)控制电路的第一控制端Q(N+4)维持低电位。
- 根据权利要求3所述的GOA电路,其中,所述第N级GOA单元还包括第N上拉控制电路、第N上拉电路、第N下传电路、第N下拉电路和第N自举电容,其中:所述第N上拉控制电路电性连接所述第N控制电路的第一控制端Q(N),第N上拉控制电路接入第(N-2)级GOA单元产生的下传信号ST(N-2)和第(N-2)级水平扫描线G(N-2);所述第N上拉电路和第N下传电路分别电性连接所述第N控制电路的第一控制端Q(N),所述第N上拉电路与所述第N级水平扫描线G(N)电性连接,所述第N下传电路输出第N级GOA单元产生的下传信号ST(N),所述第N上拉电路和第N下传电路均接入对应所述第N级GOA单元的时钟信号;所述第N自举电容的一端电性连接所述第N控制电路的第一控制端Q(N),另一端电性连接所述第N级水平扫描线G(N);所述第N下拉电路分别电性连接所述第N控制电路的第一控制端Q(N)和第N级水平扫描线G(N),所述第N下拉电路还接入所述直流低电压,所述第N下拉电路还连接第(N+2)级水平扫描线G(N+2)。
- 根据权利要求3所述的GOA电路,其中,在所述第(N+4)级GOA单元中:所述第(N+4)级GOA单元还包括第(N+4)上拉控制电路、第(N+4)上拉电路、第(N+4)下传电路、第(N+4)下拉电路和第(N+4)自举电容;所述第(N+4)上拉控制电路接入第(N+2)级GOA单元产生的下传信号ST(N+2)和第(N+2)级水平扫描线G(N+2),所述第(N+4)上拉控制电路电性连接所述第(N+4)控制电路的第一控制端Q(N+4);所述第(N+4)上拉电路和第(N+4)下传电路分别电性连接所述第(N+4)控制电路的第一控制端Q(N+4),所述第(N+4)上拉电路与所述第(N+4)级水平扫描线G(N+4)电性连接,所述第(N+4)下传电路输出第(N+4)级GOA单元产生的下传信号ST(N+4),所述第(N+4)上拉电路和第(N+4)下传电路均接入对应所述第(N+4)级GOA单元的时钟信号;所述第(N+4)自举电容的一端电性连接该第(N+4)控制电路的第一控制端Q(N+4),另一端电连接于所述第(N+4)级水平扫描线G(N+4);所述第(N+4)下拉电路分别电性连接所述第(N+4)控制电路的第一控制端Q(N+4)和第(N+4)级水平扫描线G(N+4),所述第(N+4)下拉电路还接入所述直流低电压,所述第(N+4)下拉电路还连接第(N+6)级水平扫描线G(N+6)。
- 根据权利要求8所述的GOA电路,其中,每个GOA单元接入的时钟信号为第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号中的一个,其中,接入所述第N级GOA单元的时钟信号和接入所述第(N+4)级GOA单元的时钟信号相同。
- 根据权利要求10所述的GOA电路,其中,所述第一低频控制信号和第二低频控制信号的周期为每个GOA单元接入的时钟信号周期的2倍。
- 根据权利要求8所述的GOA电路,其中,在所述第一级和第二级GOA单元中,所述第一上拉控制电路和所述第二上拉控制电路接入扫描启动信号;在最后一级和倒数第二级GOA单元中,所述下拉电路接入所述扫描启动信号。
- 一种液晶显示器,其中,包括阵列基板行驱动(GOA)电路,所述GOA电路包括级联的多个GOA单元,第N级GOA单元用于控制对第N级水平扫描线G(N)充电,第(N+4)级GOA单元用于控制对第(N+4)级水平扫描线G(N+4)充电,其中,N为正整数;其中,所述第N级GOA单元包括第N下拉维持电路;第(N+4)级GOA单元包括第(N+4)下拉维持电路;所述第N下拉维持电路包括第N控制电路、第N维持电路和与所述第(N+4)下拉维持电路共有的第N共享电路;所述第(N+4)下拉维持电路包括第(N+4)控制电路、第(N+4)维持电路和与所述第N下拉维持电路共有的所述第N共享电路;所述第N控制电路具有第一控制端Q(N)和第二控制端,所述第N控制电路的第二控制端接入第一低频控制信号,所述第N控制电路的第一控制端Q(N)和所述第一低频控制信号用于控制所述第N控制电路的输出端P(N)的电位为高电位或者低电位;所述第N维持电路电性连接所述第N控制电路的输出端P(N)、第一控制端Q(N)和所述第N级水平扫描线G(N),用于在所述第N控制电路的输出端P(N)为高电位时,维持所述第N控制电路的第一控制端Q(N)和所述第N级水平扫描线G(N)的电位为低电位;所述第(N+4)控制电路具有第一控制端Q(N+4)和第二控制端,所述第(N+4)控制电路的第二控制端接入第二低频控制信号,所述第(N+4)控制电路的第一控制端Q(N+4)和所述第二低频控制信号用于控制所述第(N+4)控制电路的输出端P(N+4)为高电位或者低电位;所述第(N+4)维持电路电性连接所述第(N+4)控制电路的输出端P(N+4)、第一控制端Q(N+4) 和所述第(N+4)级水平扫描线G(N+4),用于在所述第(N+4)控制电路的输出端P(N+4)为高电位时,维持所述第(N+4)控制电路的第一控制端Q(N+4)和所述第(N+4)级水平扫描线G(N+4)的电位为低电位;其中,所述第一低频控制信号和第二低频控制信号的相位相反;当所述第N控制电路的输出端P(N)为高电位,并且所述第(N+4)控制电路的输出端P(N+4)为高电位时,所述第N共享电路工作,将所述第N控制电路的第一控制端Q(N)的电位与所述第(N+4)控制电路的第一控制端Q(N+4)的电位共享,均维持在低电位,所述第N共享电路将所述第N级水平扫描线G(N)的电位与所述第(N+4)级水平扫描线G(N+4)的电位共享,均维持在低电位。
- 根据权利要求13所述的液晶显示器,其中,所述共享电路包括第六十一晶体管、第六十二晶体管、第六十三晶体管和第六十四晶体管,其中:所述第六十一晶体管的栅极和所述第六十三晶体管的栅极电性连接所述第N控制电路的输出端P(N),所述第六十一晶体管的源级电性连接所述第N控制电路的第一控制端Q(N),所述第六十一晶体管的漏级电性连接所述第六十二晶体管的漏级;所述第六十二晶体管的源级电性连接所述第(N+4)控制电路的第一控制端Q(N+4),所述第六十二晶体管的栅极和所述第六十四晶体管的栅极电性连接所述第(N+4)控制电路的输出端P(N+4);所述第六十三晶体管的源级电性连接所述第(N+4)级水平扫描线G(N+4),所述第六十三晶体管的漏级电性连接所述第六十四晶体管的漏级,所述第六十四晶体管的源极电性连接所述第N级水平扫描线G(N)。
- 根据权利要求14所述的液晶显示器,其中,所述第N控制电路包括第五十一晶体管、第五十二晶体管、第五十三晶体管和第五十四晶体管,其中:所述第五十一晶体管的栅极、所述第五十一晶体管的漏极、所述第五十三晶体管的漏极电性连接所述第N控制电路的第二控制端,所述第五十一晶体管的源极电性连接所述第五十二晶体管的漏极和所述第五十三晶体管的栅极,所述第五十二晶体管的栅极电性连接所述第N控制电路的第一控制端Q(N), 所述第五十三晶体管的源极电性连接所述第五十四晶体管的漏极和所述第N控制电路的输出端P(N),所述第五十二晶体管的源极和所述第五十四晶体管的源极输入直流低电压;当所述第N控制电路的第一控制端Q(N)为低电位时,若所述第N控制电路的第二控制端为高电位,则所述第N控制电路的输出端P(N)为高电位;当所述第N控制电路的第一控制端Q(N)为低电位时,若所述第N控制电路的第二控制端从高电位变为低电位,则所述第N控制电路的输出端P(N)为高电位。
- 根据权利要求15所述的液晶显示器,其中,所述第N维持电路包括第三十二晶体管和第四十二晶体管,其中:所述第三十二晶体管的栅极和所述第四十二晶体管的栅极电性连接所述第N控制电路的输出端P(N),所述第三十二晶体管的漏极电性连接所述第N级水平扫描线G(N),所述第四十二晶体管的漏极电性连接所述第N控制电路的第一控制端Q(N),所述第三十二晶体管的源极和所述第四十二晶体管的源极输入所述直流低电压;当所述第N控制电路的输出端P(N)为高电位时,所述第N级水平扫描线G(N)和所述第N控制电路的第一控制端Q(N)维持低电位。
- 根据权利要求14所述的液晶显示器,其中,所述第(N+4)控制电路包括第五十五晶体管、第五十六晶体管、第五十七晶体管和第五十八晶体管,其中:所述第五十五晶体管的栅极、所述第五十五晶体管的漏极、所述第五十七晶体管的漏极电性连接所述第(N+4)控制电路的第二控制端,所述第五十五晶体管的源极电性连接所述第五十六晶体管的漏极和所述第五十七晶体管的栅极,所述第五十六晶体管的栅极电性连接所述第(N+4)控制电路的第一控制端Q(N+4),所述第五十七晶体管的源极电性连接所述第五十八晶体管的漏极和所述第(N+4)控制电路的输出端P(N+4),所述第五十六晶体管的源 极和所述第五十八晶体管的源极输入直流低电压;当所述第(N+4)控制电路的第一控制端Q(N+4)为低电位时,若所述第(N+4)控制电路的第二控制端为高电位,则所述第(N+4)控制电路的输出端P(N+4)为高电位;当所述第(N+4)控制电路的第一控制端Q(N+4)为低电位时,若所述第(N+4)控制电路的第二控制端从高电位变为低电位,则所述第(N+4)控制电路的输出端P(N+4)为高电位。
- 根据权利要求17所述的液晶显示器,其中,所述第(N+4)维持电路包括第三十三晶体管和第四十三晶体管,其中:所述第三十三晶体管的栅极和所述第四十三晶体管的栅极电性连接所述第(N+4)控制电路的输出端P(N+4),所述第三十三晶体管的漏极电性连接所述第N级水平扫描线G(N+4),所述第四十三晶体管的漏极电性连接所述第(N+4)控制电路的第一控制端Q(N+4),所述第三十三晶体管的源极和所述第四十三晶体管的源极输入所述直流低电压;当所述第(N+4)控制电路的输出端P(N+4)为高电位时,所述第(N+4)级水平扫描线G(N+4)和所述第(N+4)控制电路的第一控制端Q(N+4)维持低电位。
- 根据权利要求14所述的液晶显示器,其中,所述第N级GOA单元还包括第N上拉控制电路、第N上拉电路、第N下传电路、第N下拉电路和第N自举电容,其中:所述第N上拉控制电路电性连接所述第N控制电路的第一控制端Q(N),第N上拉控制电路接入第(N-2)级GOA单元产生的下传信号ST(N-2)和第(N-2)级水平扫描线G(N-2);所述第N上拉电路和第N下传电路分别电性连接所述第N控制电路的第一控制端Q(N),所述第N上拉电路与所述第N级水平扫描线G(N)电性连接,所述第N下传电路输出第N级GOA单元产生的下传信号ST(N),所述第N上拉电路和第N下传电路均接入对应所述第N级GOA单元的时钟信 号;所述第N自举电容的一端电性连接所述第N控制电路的第一控制端Q(N),另一端电性连接所述第N级水平扫描线G(N);所述第N下拉电路分别电性连接所述第N控制电路的第一控制端Q(N)和第N级水平扫描线G(N),所述第N下拉电路还接入所述直流低电压,所述第N下拉电路还连接第(N+2)级水平扫描线G(N+2)。
- 根据权利要求14所述的液晶显示器,其中,在所述第(N+4)级GOA单元中:所述第(N+4)级GOA单元还包括第(N+4)上拉控制电路、第(N+4)上拉电路、第(N+4)下传电路、第(N+4)下拉电路和第(N+4)自举电容;所述第(N+4)上拉控制电路接入第(N+2)级GOA单元产生的下传信号ST(N+2)和第(N+2)级水平扫描线G(N+2),所述第(N+4)上拉控制电路电性连接所述第(N+4)控制电路的第一控制端Q(N+4);所述第(N+4)上拉电路和第(N+4)下传电路分别电性连接所述第(N+4)控制电路的第一控制端Q(N+4),所述第(N+4)上拉电路与所述第(N+4)级水平扫描线G(N+4)电性连接,所述第(N+4)下传电路输出第(N+4)级GOA单元产生的下传信号ST(N+4),所述第(N+4)上拉电路和第(N+4)下传电路均接入对应所述第(N+4)级GOA单元的时钟信号;所述第(N+4)自举电容的一端电性连接该第(N+4)控制电路的第一控制端Q(N+4),另一端电连接于所述第(N+4)级水平扫描线G(N+4);所述第(N+4)下拉电路分别电性连接所述第(N+4)控制电路的第一控制端Q(N+4)和第(N+4)级水平扫描线G(N+4),所述第(N+4)下拉电路还接入所述直流低电压,所述第(N+4)下拉电路还连接第(N+6)级水平扫描线G(N+6)。
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US20180190228A1 (en) | 2018-07-05 |
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US10186223B2 (en) | 2019-01-22 |
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