WO2018009182A1

WO2018009182A1 - Resistive ram with electroforming functionality

Info

Publication number: WO2018009182A1
Application number: PCT/US2016/041096
Authority: WO
Inventors: Elijah Karpov; Jeffery D. Bielefeld; Roza Kotlyar; Prashant Majhi; Ravi Pillarisetty
Original assignee: Intel Corporation
Priority date: 2016-07-06
Filing date: 2016-07-06
Publication date: 2018-01-11

Abstract

A resistive RAM memory cell and array are described that include an electroforming functionally. One example includes a first resistive memory material, a first electrode on one side of the first resistive memory material, a second resistive memory material, a second electrode on one side of the second resistive memory material, a middle electrode between the first electrode and the second electrode, the middle electrode electrically coupled to the first resistive memory material on a side of the first resistive memory material opposite the first electrode and electrically coupled to the second resistive memory material and on a side of the second resistive memory material opposite the second electrode, and a power connector to apply a potential to the middle electrode, the potential being opposite a potential of the first electrode and the second electrode.

Description

RESISTIVE RAM WITH ELECTROFORMING FUNCTIONALITY

FIELD

The present description relates to resistive random access memory and, in particular, to such a device with an electrically active middle electrode.

BACKGROUND

NVRAM (Nonvolatile Random Access Memory) is a memory that retains its data without requiring any additional external power. Power is consumed only for reading and writing the memory. Solid state NVRAM is finding greater use in a wide variety of electronics and microelectronics devices and is moving into server and data provider systems. Solid state types of NVRAM are growing in use by offering smaller size and lower power consumption as compared to other types of memory. Currently, the dominant form of NVRAM is flash memory. However, flash requires a high voltage for programming by block to erase the memory and is limited in speed. There are other disadvantages i n the configuration and lifetime of flash memory arrays.

Alternative solid state NVRAM technologies are under development to provide faster memory access at lower power and higher density. For embedded applications, the memory is built on the same die as the processor and so compatibility with CMOS (Complementary Metal Oxide Semiconductor) logic circuitry allows costs to be reduced.

Resistive memory is one such alternative. In one configuration of resistive random access memory (ReRAM or RRAM), a thin film memory stack is built as a two-terminal device based on a dielectric memory material sandwiched between two conductive electrodes or terminals. This may be referred to as a MIM structure (Metal Insulator Metal). The memory material switches between two different non-volatile states: a high-resistance state (HRS) and a low-resistance state (LRS). A reset voltage is used to switch the ReRAM cell to HRS, and a set voltage is used to switch the ReRAM cell to the LRS.

Defects are engineered into the memory material to improve the switching speed and the conductivity of the material. An oxygen exchange layer of Ti, H Zr, or Ta has been used for the defects. More recently directional filaments are electrically formed in the memory material and are controlled to make the memory material change state. BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments are il lustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements.

Figure 1 i s a cross-sectional side view diagram of an example of a vertical ly stacked thin film MIMIM resistive memory cell built over a substrate according to an embodiment.

Figure 2 is a state diagram of the operation of a thin film MIMIM resistive memory cell according to an embodi ment.

Figure 3 is cross-sectional side view diagram of an example configuration of two RRAM cell s in series according to an embodiment.

Figure 4 is a cross-sectional side view diagram of a switching element formed from two

RRAM cells in series according to an embodiment.

Figure 5 is a cross-sectional side view diagram of an RRAM memory cell configured in metal layers abov e a substrate according to an embodiment.

Figure 6 is a cross-sectional side view diagram of an alternative RRAM memory cell configured in metal layers above a substrate according to an embodiment.

Figure 7 is an isometric view diagram of a vertical crosspoint array of RRAM memory cell s according to an embodiment.

Figure 8 i s an i sometric view diagram of a horizontal crosspoint array of RRAM memory cells according to an embodiment.

Figure 9 is a schematic diagram of a memory array and supporting circuits according to an embodiment.

Figure 10 i s a block diagram of a computing device suitable for use with embodiments.

DETAILED DESCRIPTION

As described herein, a M IM IM (Metal Insulator Metal Insulator Metal ) RRAM structure has a middle electrode which can be electrically biased. The MIMIM structure is a stack of two M IM structures in seri es with a shared middle active metal layer to form a third or middle electrode terminal . By bi asing the middle electrode the top and bottom MIM structures may be biased symmetrically to ensure that the filaments in both insulator layers are formed ith tips at the middle electrode.

Figure I i s a cross-sectional side view diagram of an example of a vertically stacked thin film MIMIM resistive memory cell 120 built over a substrate 1 16. The substrate may be silicon and suitable for MOS logic circuitry or it may be another type of substrate, suitable for a different application. As alternatives, germanium, SiGe, GaAs, and amorphous materials including glasses, organic polymers, and plastics, etc. may be used as substrates. The upper MIM stack 102 is stacked over the lower MIM stack 104 with a common middle electrode 106.

The resulting M IMIM stack has an upper word line 1 10 and a lower word line 1 12 at opposite ends of the stack. The middle electrode may be coupled to a bit line or it may be left to float. The two stacks 102, 103 each include an inactive metal layer 128, 130 closest to the outer word line electrodes 1 12, 1 13. A metal oxide or metal nitride layer may be used as a barrier layer between the memoiy material on each side and the outer word line electrodes. The memory material 124, 126 is between the respective word line electrodes and the middle electrode.

The outer inactive electrodes 128, 130 may be made of any suitable conductive material such as a metal or polysilicon. It may be exposed to the memory material or it may be protected by a barrier layer. The middle active metal electrode may be based on Cu, Ag, Ni or any other suitable active metal. The memory material s may be made of any of a variety of different materials and will be described in the context of a programmable metallization cell (PMC) that uses an electrochemical metallization effect to change states. A solid electrolyte of oxide or chalcogenide may be used, for example, or a dual layer material . As such, applying a positive voltage bias to the active electrode 106 ionizes active metal atoms (e g., Cu, Pt, or Ag) in the electrolyte material and drives those atoms through the insulator 102, 104 to be reduced at the inactive metal electrode 128, 130. The active metal atoms are driven to form conducting filaments that start at the central active electrode and grow back to the outer inactive electrode. The filaments form the conductive path for the ON state. In the same way, a negative bias reverses the growth, breaks the filaments, and creates the OFF state.

With an array of M IMIM cells as described, the voltage response of each cell is not reproducible between cel l s. In addition, each cell may be in a different state. There may be a filament produced ON state in the lower stack, in the upper stack, in both stacks, or in neither stack . In a typical memory cell array configuration, only the top and bottom electrodes are biased. If thi s approach is applied to a MIM IM RRAM cell as shown in Figure 1, then the middle electrode is floating. As a result, the orientation of the filament tips i s random and depends on its transient potential which varies from cell to cell and between stacks of the same cell . The memory material will not reliably shape into any particular configuration unless a potential is applied to al l three electrodes, top, bottom, and middle.

Figure 2 is a state diagram for a memory cell such as that of Figure 1. The states are applied to a graph of the applied voltage (V) on the horizontal scale versus the current flow (I) on the vertical scale. Starting at the origin 150, a positive voltage bias is applied to the outer electrodes 128, 130, for example through the word lines 1 10, 1 12. This causes a transition to a state 172 in which the memory cell conducts very little current. In this diagram the memory material is indicated as a solid block with or without an upper or lower triangle. The triangles represent the electroformation of conductive filaments between the outer electrodes 102, 104 and the middle electrode 106. A single triangle represents an incomplete conductive path

corresponding to an OFF state. Two connected triangles represent a completed filament conductive path corresponding to an ON state.

At a level of applied positive v oltage 152 that is beyond some threshold that depends upon the construction and form of the memory material and the active metal, the voltage is enough to cause the formation of conductive paths through the filaments. The current then increases quickly to a higher level 1 4. This corresponds to an ON state 1 74 of the memory. With increased applied voltage the current flow will also increase as more filaments connect until a peak current level 1 56 is reached. At this stage a v ery small voltage increase will cause a steep drop in current flow to an almost zero level 1 58. This is another OFF state 1 76 for the memory cel l . At thi s stage 1 76 there i s no direct path to return to the ON state 1 74 because reducing the voltage will not cause the filaments to reform. In addition, from the ON state 1 74 there is no direct path to the first low voltage OFF state 172. Once the filaments are formed reducing the v oltage will not break them.

As shown by the arrows, from the high current levels between the two points 1 54, 1 56 on the sloped line the only way to transition to a low current level 152, 1 58 is to fol low the arrow and increase the voltage. Once the voltage reaches the threshold at 1 56, 1 58, then the only way to change the state is to return to the origin 150. Through this return to the origin, the state of the memory cell does not change. In the same way if the applied voltage is not increased past the threshold 1 58 so that the memory cel l i s in the ON state I 74 anywhere between the ON state voltage levels 1 54, 1 56, then the voltage may be returned to the origin 1 50 which corresponds to no applied voltage without affecting the state of the memory cell .

To change the state of the cell, the polarity of the applied voltage is reversed. As shown by the arrows, from the origin with a negative voltage the voltage is increased until it reaches a transition point 162. At this negativ e v oltage the conductive fi laments start to form and the current flow is increased to a much higher state 164. The memory cell transitions from an OFF state 1 82 to an ON state 1 84. As with the positive applied voltage, as the v oltage increases past the threshold transition level 164, the current increases only slowly and the ON state 1 84 is maintained. If the voltage is then reduced at this stage and returned to the origin 150 or some other low level, then the memory cell state is preserved. On the other hand if the voltage is increased to the next threshold 166, the filaments are broken, the current drops 168 to near zero and the cell is again in an OFF state 186. This can only be changed by reversing the polarity and applying a voltage that exceeds the threshold state 152, 154.

Figure 3 is a cross-sectional side view diagram that shows an example configuration of two RRAM cells in series. This enables a built-in selector functionality by using CRS

(Complementary Resistive Switching). The cell has an upper RRAM portion 204 with an upper metal electrode 206, and a lower inverse RRAM portion 208 with a lower metal electrode 210. A middle electrode 2 1 2 between the two portions is shared. Each portion has a solid electrolyte material 214, 216 as described above.

The middle electrode 212 is typically allowed to float. However, by connecting the middle electrode to a known voltage during an initial state, the memory materials 2 14, 2 16 may be set to a known configuration . Thi s provides reliable performance later when the switch electrode and memory electrode are accessed to change the memory state of the stack.

Note that in thi s example, the device functions without any read/write transi stor. The

RRAM acts as the memory cell and the inv erse RRAM acts as the selector. The transistor is avoided. Thi s can significantly reduce the bit cell size and enable stacking.

Figure 4 i s a cross-sectional side view diagram of a transistor or switch 250 based on the structure of Figure 2. In this case, the MIMIM stack has a source 252 at one end, a drain 254 at the opposite end and the middle electrode 256 serv es as the gate. The same memory material i s used for the upper portion 262 between the source and gate and also for the lower portion 264 between the drain and gate. When a positiv e bias i s applied to the gate, then the filaments grow from the source and the drain to the gate to establish an ON state between the source and drain. When a negative bias is applied to the gate, then the filaments move away from the middle electrode and the connection is broken to establish an OFF state. The state of such a switch may be changed within 50- 100ns which is sufficient for many logic circuits.

Figure 5 i s a cross-sectional side view diagram of an RRA memory cell 302 configured in metal layers ov er a substrate and logic circuitry for use in a memory cel l array. The RRAM cell has an upper electrode 304, and a lower electrode 306, typically of a metal such as Cu, Pt, or Ag as described abov e. The RRAM cell also has a middle electrode 308 betw een the upper and lower electrodes and separated from the upper and lower electrodes by memory material as described abov e.

The lower electrode is coupled to a metal row word line rail 3 1 6 (M_N). The upper electrode is coupled to a metal column word li ne rail 3 14 (M_N+1 _₂). These allow for read and write operations as is typically performed with such memory arrays. The middle electrode 308 is coupled to a different metal rail. For a transistor, this electrode may be coupled to a gate input which will be different for each transistor. For a memory cell, all of the middle electrodes may be coupled to the same power rail 3 1 2 (M_N). This is indicated as being shorted to the lower column word line, however it may be coupled to another source of potential . Specifically, a horizontal connector or bus bar 322 from the middle electrode 308 is connected to a via 3 10 that connects to a power rail 3 1 2. The power rail is connected to a potential source 3 1 8.

The middle electrode potential source is used only to reset or initialize the memory cells. Accordingly, all of the memory cells may be driven with a common voltage 3 1 8 until the filaments are formed so that both upper and lower portions are in the ON state. After this the connection may be broken and the MIM IM structure 302 may be operated as a conventional memory cell . The bus bar 322, the power rail 3 12, or another part of the connection to the power supply 3 1 8 may have a fuse 320. Breaking the fuse, e.g. by exceeding the current capacity of the fuse or by laser, disconnects the middle electrode after the memory cell array has been initialized by electroforming.

In Figure 5, the word lines are indicated as M_N and M_N+1. This is to suggest that the memory cell may be implemented in metal layers (N, N+l) of a semiconductor die. The lower column line 3 1 6 may be implemented in a metal layer (layer N) that is formed over logic circuitry on a die by patterning the metal layer. The upper row line 3 14 may be implemented in a higher metal layer (layer N+l or higher) by patterning the next metal layer. In this way an array of memory cells may be formed in metal layers that otherwise may not be used for any circuitry.

Figure 6 is a cross-sectional side view diagram of an alternative memory cell in metal layers above a substrate i n which the middle electrode i s coupled to an upper metal layer for electroforming. A memory cell 342 has a lower electrode 346 coupled to a lower metal rail 356 (M_N) and an upper electrode 344 coupled to an upper rail 354 (M_{N+1 2}). The memory cell uses a resi stive RAM principle as before to store either an ON or OFF state. A middle electrode 348 is coupled through a connector 362 to a via 350. The via in thi s case is coupled to an upper rail 360 (M_N+_I). Thi s, as before, is a temporary connection that is for electroforming that is then disconnected at some point. The upper rail 360 of the middle electrode may be connected to the upper rail 354 of the top electrode or it may have a separate power supply (not shown).

Figure 7 is an isometric v iew diagram of a crosspoint vertical memory array suitable for use with the present application. The memory array 400 i s embedded over logic circuitry 402. The density of the memory array is increased because the thin film -based selector element is placed in series with the memory element at each cross-section of bit line 410 and word lines 404, 406 since the memory layers 412, 414 are stacked on top of each other. The word lines are fabricated as signal rails 404, 406 in one direction and the bit line 410 i s on a rail orthogonal to the word lines. In this diagram the many layers of dielectric, the silicon substrate under the circuitry 402 and several other features are not shown in order to not obscure the other features of the drawing.

Routing 408 for horizontal word lines 404 and 406 connects the memory cel ls to the circuitry 402 below. Similar routing 416 is included for horizontal bit lines 410. The rails may be implemented in metal layers while the routing i s implemented by vias coupled to metal layers. Additional routing (not shown) is provided to connect the middle electrodes of each memory cell for electroforming. These middle electrodes are between the word lines and the bit lines and may be connected as shown in Figures 5 and 6.

Figure 8 i s an i sometric view diagram of a crosspoint horizontal memory array 403. The array includes routing 452 for horizontal word lines 454 and 456. Contacts 458 for vertical bit lines 460 are formed directly to underlying logic circuitry (not shown ). The memory cell 462 are fabricated horizontally between the vertically stacked word lines and bit lines. As in the example of figure 7, the middle electrode connections are not shown. This may be used for electroforming and then fused, di sconnected, or cut, depending on the particular implementation . In this diagram the many layers of dielectric, the silicon substrate and the circuitry on the substrate below the metal layers of the word line and bit lines and several other features are not shown in order to not obscure the other features of the drawing.

Figures 7 and 8 represent possible crosspoint array configurations for the unique memory array described herein, however, the array may be implemented in any of a variety of other configurations, depending on the intended use and desired form factor and efficiency.

Figure 9 is a schematic of a nonv olatile RRAM array 701 including a plurality of resistive memory stacks 702, similar to that of Figure 1 each incorporating upper and middle electrodes with memory material between . The array 705 in this example i s a bidirectional cross point array including any number of independent memory stacks 702, each stack is coupled through a resistive RAM selector element ("S") with the middle and lower electrode. Each column i s associated with a bit line driv en by a column select circuit in column select circuitry 725 coupled to the upper electrode of each RRAM element. Each row is associated w ith a word line driv en by a row select circuit in row select circuitry 730 coupled to the lower electrode of each RRAM selector element. The middle electrode is not connected after initial electroforming. In operation, R/W control circuitry 720 receives memory access requests (e.g., from a local processor or communication chip in which the memory is embedded), generates the requisite control signals based on the requests (e.g., read, write 0, or write 1), and controls the row and column select circuitry 725, 730. Voltage supplies 710, 715 are controlled to provide the voltage necessary to bias the array to facilitate the requested action on one or more bitcell s 702. Row and column select circuitry 725, 730 applies the supplied voltage across array 705 to access a selected bitcell( s). Row select ci cuitry 725, column select circuitry 730, and R/W control circuitry 720 may be implemented with any known technology.

Figure 10 i llustrates a computing device 100 in accordance with one implementation. The computing device 100 houses a board 2. The board 2 may include a number of components, including but not limited to a processor 4 and at least one communication chip 6. The processor 4 is physically and electrically coupled to the board 2. In some implementations the at least one communication chip 6 i s also physically and electrically coupled to the board 2. In further implementations, the communication chip 6 is part of the processor 4.

Depending on its applications, computing device 100 may include other components that may or may not be physically and electrically coupled to the board 2. These other components include, but are not limited to, volatile memory (e.g., DRAM) 8, non-volatile memory (e g., ROM) 9, flash memory (not shown), a graphics processor 1 2, a digital signal processor (not shown ), a crypto processor (not shown), a chipset 14, an antenna 16, a display 18 such as a touchscreen display, a touchscreen controller 20, a haptic actuator array 2 1 , a battery 22, an audio codec (not shown), a video codec (not shown), a power amplifier 24, a global positioning system (GPS) device 26, a compass 28, an accelerometer (not shown), a gyroscope (not shown ), a speaker 30, a camera 32, and a mass storage device ( such as hard disk drive) 10, compact disk (CD) (not shown ), digital versatile di sk (DVD) (not shown), and so forth). These components may be connected to the system board 2, mounted to the system board, or combined with any of the other components.

The communication chip 6 enables wireless and/or wi ed communications for the transfer of data to and from the computing device 100. The term "wireless^" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channel s, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium . The term does not imply that the associated dev ices do not contain any wires, although in some embodiments they might not. The communication chip 6 may implement any of a number of wireless or wired standards or protocol s, including but not limited to Wi-Fi ( IEEE 802. 1 1 family), WiMAX ( IEEE 802. 16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+ HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, Ethernet derivatives thereof, as well as any other wireless and wired protocol s that are designated as 3G, 4G, 5G, and beyond. The computing device 100 may include a plurality of communication chips 6. For instance, a first communication chip 6 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second

communication chip 6 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

Many of the components of the computing device may include memory on a die with logic devices or may have memory or logic devices on different dies in the same package.

Embedded memory may be packaged together with a die that includes memory. The processor, memory devices, communication devices, or other components may all include or be packaged with memory or logic transistors fabricated or configured as described herein. The term

"processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

In various implementations, the computing device 100 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set- top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, wearables, and drones. In further implementations, the computing device 100 may be any other electronic device that processes data.

Embodiments may be adapted to be used with a variety of different types of packages for different implementations. References to "one embodiment", "an embodiment", "example embodiment", "various embodiments", etc., indicate that the embodiment(s) so described may include particular features, structures, or characteristics, but not every embodiment necessarily includes the particular features, structures, or characteristics. Further, some embodiments may have some, all, or none of the features described for other embodiments.

In the following description and claims, the term "coupled" along with its derivatives, may be used. "Coupled" is used to indicate that two or more elements co-operate or interact with each other, but they may or may not have intervening physical or electrical components between them.

As used in the claims, unless otherwise specified, the use of the ordinal adjectives "first", "second", "third", etc., to describe a common element, merely indicate that different instances of like elements are being referred to, and are not intended to imply that the elements so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner.

The drawings and the forgoing description give examples of embodiments. Those skilled in the art will appreciate that one or more of the described elements may well be combined into a single functional element. Alternatively, certain elements may be split into multiple functional elements. Elements from one embodiment may be added to another embodiment. For example, the speci ic location of elements as shown and described herein may be changed and are not limited to what is shown. Moreover, the actions of any flow diagram need not be implemented in the order shown; nor do all of the acts necessari ly need to be performed. Also, those acts that are not dependent on other acts may be performed in parallel with the other acts. The scope of embodiments is by no means limited by these specific examples. Numerous variations, whether explicitly given in the specification or not, such as differences in structure, dimension, and use of material, are possible. The scope of embodiments is at least as broad as given by the following claims.

The following examples pertain to further embodi ments. The various features of the different embodiments may be variously combined with some features included and others excluded to suit a variety of different applications. Some embodiments pertain to an apparatus that includes a first resi stive memory material, a first electrode on one side of the first resistive memory material, a second resistiv e memory material, a second electrode on one side of the second resistive memory material, a middle electrode between the first electrode and the second electrode, the middle electrode electrically coupled to the first resistive memory material on a side of the first resi stive memory material opposite the first electrode and electrically coupled to the second resistive memory material and on a side of the second resistive memory material opposite the second electrode, and a power connector to apply a potential to the middle electrode, the potential being opposite a potential of the first electrode and the second electrode..

Further embodiments include a fuse coupled to the power connector to connect the middle electrode to a source of potential to electro form the first and second memory resi stive memory materials, the fuse to disconnect the middle electrode from the source of potential after electroforming.

In further embodiments the fuse compri ses a metal trace that may be broken with an overcurrent.

In further embodiments the apparatus i s a memory cell of a crosspoint memory cell array, the second electrode is a selector contact, and the first resistive memory material i s a storage cell of the memory. In further embodiments the first electrode is coupled to a word line and the second electrode is coupled to a bit line.

Further embodiments include a bus bar in a metal layer over a silicon substrate, the bus bar coupled to the middle electrode power connector at one end and to a power rail at another end.

In further embodiments the bus bar is coupled to the power rai 1 through a through-silicon via.

In further embodiments the first and second resistive memory materials are a solid electrolyte of chalcogenide.

Further embodiments include a metal nitride barrier layer between the middle electrode and the first and second resistive memory materials.

In further embodiments the first electrode is coupled to a logic circuit as a source, the second electrode i s coupled to the logic circuit as a drain and the middle electrode is coupled to the logic circuit as a gate.

In further embodiments the first metal layer is formed in a first metal layer of a plurality of metal layers over logic circuitry on a silicon substrate, wherein the second metal layer is formed in a second metal layer of the plurality of metal layers and wherein the apparatus is one of multiple memory cells in an embedded array of memory cell s.

Some embodiments pertain to the apparatus above comprised by a computing system having a processor with the above apparatus as embedded memory, a mass memory, and a comm nications chip.

Some embodiments pertain to a method that includes applying a potential to a middle electrode between memory materials of a stacked memory cell, applying an opposite polarity potential a first and a second electrode of the stacked memory cell, the first and the second electrodes being on respective opposite side of the middle electrode and the respective memory material, wherein the potential electroforms filaments within the first and second memory materials, removing the potential to the middle electrode after electroforming, and applying opposite potential to the first and second electrodes to set a memory state in the stacked memory cell.

In further embodiments removing the potential compri ses breaking a fuse between a source of the potential and the middle electrode.

In further embodiments applying the potential comprises applying the potential to a power rail that i s connected to a plurality of stacked memory cell s to apply a potential to each of the plurality of stacked memory cells simultaneously. In further embodiments applying the potential comprises applying the potential through a patterned metal layer of a plurality of metal layers over logic circuitry of a silicon substrate.

Some embodiments pertain to a switchable transistor embedded in metal layers of a semiconductor die that includes a first resistive memory material , a source formed as a first metal electrode in a first metal layer of the die on one side of the first material, a second resistive memory material, a drain formed as a second metal electrode in a second metal layer of the die on one side of the second material, and a gate formed as a middle electrode between the first electrode and the second electrode, the middle electrode electrically coupled to the first resistive memory material on a side of the first resistive memory material opposite the first electrode and electrically coupled to the second resistive memory material and on a side of the second resistive memory material opposite the second electrode.

In further embodiments the gate is coupled to a third metal layer of the die and wherein the gate is coupled to a potential to initially electroform the resistive memory materials before operation.

In further embodiments the coupling to the potential i s fused.

Claims

CLAIMS:

1 . An apparatus comprising:

a first resistive memory material;

a first electrode on one side of the first resistive memory material;

a second resistive memory material;

a second electrode on one side of the second resistive memory material ;

a middle electrode between the first electrode and the second electrode, the middle electrode electrically coupled to the first resistive memory material on a side of the first resistive memory material opposite the first electrode and electrically coupled to the second resi stive memory material and on a side of the second resi stive memory material opposite the second electrode; and

a power connector to apply a potential to the middle electrode, the potential being opposite a potential of the first electrode and the second electrode.

2. The apparatus of Claim 1, further comprising a fuse coupled to the power connector to connect the middle electrode to a source of potential to electroform the first and second resistive memory materials, the fuse to disconnect the middle electrode from the source of potential after electroforming.

3. The apparatus of Claim 1 or 2, wherein the fuse compri ses a metal trace that may be broken with an overcurrent.

4. The apparatus of any one or more of claims 1-3, wherein the apparatus is a memory cell of a crosspoint memory cell array, the second electrode is a selector contact, and the first material is a storage cell of the memory.

5. The apparatus of any one or more of claims 1 -4, wherein the first electrode is coupled to a word line and the second electrode is coupled to a bit line.

6. The apparatus of any one or more of claims 1-5, further comprising a bus bar in a metal layer over a silicon substrate, the bus bar coupled to the middle electrode power connector at one end and to a power rail at another end.

7. The apparatus of Claim 6, wherein the bus bar is coupled to the power rail through a through-silicon via.

8. The apparatus of any one or more of claims 1 -7, wherein the first and second resi stive memory material s are a solid electrolyte of chalcogenide.

9. The apparatus of any one or more of claims 1 -8, further comprising a metal nitride barrier layer between the middle electrode and the first and second resistive memory materials.

10. The apparatus of any one or more of claims 1-9, wherein the first electrode is coupled to a logic circuit as a source, the second electrode is coupled to the logic circuit as a drain and the middle electrode is coupled to the logic circuit as a gate.

1 1. The apparatus of any one or more of claims 1-10, wherein the first metal layer is formed in a first metal layer of a plurality of metal layers over logic circuitry on a silicon substrate, wherein the second metal layer is formed in a second metal layer of the plurality of metal layers and wherein the apparatus is one of multiple memory cell s in an embedded array of memory cells.

1 2. The apparatus of Claim 1 1 comprised by a computing system having a processor with the apparatus of Claim 1 1 as embedded memory, a mass memory, and a communications chip.

13. A method comprising:

applying a potential to a middle electrode between memory material s of a stacked memory cell;

applying an opposite polarity potential a first and a second electrode of the stacked memory cell, the first and the second electrodes being on respective opposite side of the middle electrode and the respective memory material , wherein the potential electroform filaments within the first and second memory materials;

removing the potential to the middle electrode after electro forming; and

applying opposite potential to the first and second electrodes to set a memory state in the stacked memory cell.

14. The method of Claim 13, wherein removing the potential comprises breaking a fuse between a source of the potential and the middle electrode.

15. The method of Claim 13 or 14, wherein applying the potential comprises applying the potential to a power rail that is connected to a plurality of stacked memory cells to apply a potential to each of the plurality of stacked memory cells simultaneously.

16. The method of any one or more of claims 13- 15, wherein applying the potential comprises applying the potential through a patterned metal layer of a plurality of metal layers over logic circuitry of a silicon substrate.

1 7. A switchable transistor embedded in metal layers of a semiconductor die comprising:

a first resistive memory material;

a source formed as a first metal electrode in a first metal layer of the die on one side of the first resistive memory material; a second resistive memory material;

a drain formed as a second metal electrode in a second m etal layer of the die on one side of the second resistive memory material; and

a gate formed as a middle electrode between the first electrode and the second electrode, the middle electrode electrically coupled to the first resistive memory material on a side of the first resistive memory material opposite the first electrode and electrically coupled to the second resistive memory material and on a side of the second resistive memory material opposite the second electrode.

18. The transistor of Claim 17, wherein the gate is coupled to a third metal layer of the die and wherein the gate is coupled to a potential to initially electroform the resistive memory materials before operation.

19. The transistor of Claim 17 or 18, wherein the coupling to the potential is fused.

20. The transistor of any one or more of claims 17-19, wherein the first and second resistive memory materials are a solid electrolyte of chalcogenide.