WO2018004668A2

WO2018004668A2 - Techniques for forming thin-film bulk acoustic resonator devices

Info

Publication number: WO2018004668A2
Application number: PCT/US2016/040766
Authority: WO
Inventors: Han Wui Then; Sansaptak DASGUPTA; Marko Radosavljevic
Original assignee: Intel Corporation
Priority date: 2016-07-01
Filing date: 2016-07-01
Publication date: 2018-01-04
Also published as: WO2018004668A3

Abstract

Techniques are disclosed for fabricating an integrated circuit including one or more thin-film bulk acoustic resonator (TFBAR, also called FBAR) devices. A given TFBAR device may include a superlattice structure comprising alternating layers of an epitaxial piezoelectric material, such as aluminum nitride (AlN), and any one, or combination, of aluminum indium nitride (A1_xIn_1-xN), aluminum gallium nitride (A1_xGa_1-xN), or aluminum indium gallium nitride (A1_xInyGa_1-x-yN), the particular compositional ratios of which may be adjusted to customize resonator performance. The superlattice layers may be formed via an epitaxial deposition process, allowing for precise control over thickness. By exploiting material composition differences and utilizing appropriate selective etch chemistries and techniques, individual constituent layers may be selectively removed from the superlattice with no (or otherwise negligible) impact on other layers. In this manner, the superlattice structure may be thinned down, in nanometer-range increments, to achieve a given target resonance frequency for the host resonator device.

Description

TECHNIQUES FOR FORMING THIN-FILM BULK ACOUSTIC RESONATOR

DEVICES

BACKGROUND

With the growing number of bands and modes of communications, the quantity of radio frequency (RF) filters utilized in modern communication systems has significantly increased. Some RF filters employ thin-film bulk acoustic resonators (TFBARs, also called FBARs). Typical RF front-end technologies employing second-generation (2G), third-generation (3G), fourth-generation (4G), and long-term evolution (LTE) wireless standards utilize multiple RF filters, each with one or more constituent TFBARs.

BRIEF DESCRIPTION OF THE DRAWINGS

Figures 1-9 illustrate a process flow for forming an integrated circuit (IC) in accordance with an embodiment of the present disclosure.

Figure 10 illustrates a computing system implemented with integrated circuit structures or devices formed using the disclosed techniques in accordance with an example embodiment.

These and other features of the present embodiments will be understood better by reading the following detailed description, taken together with the figures herein described. In the drawings, each identical or nearly identical component that is illustrated in various figures may be represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing. Furthermore, as will be appreciated, the figures are not necessarily drawn to scale or intended to limit the described embodiments to the specific configurations shown. For instance, while some figures generally indicate straight lines, right angles, and smooth surfaces, an actual implementation of the disclosed techniques may have less than perfect straight lines and right angles, and some features may have surface topography or otherwise be non-smooth, given real-world limitations of fabrication processes. In short, the figures are provided merely to show example structures.

DETAILED DESCRIPTION

Techniques are disclosed for fabricating an integrated circuit including one or more thin- film bulk acoustic resonator (TFBAR, also called FBAR) devices. In accordance with some embodiments, a given TFBAR device may include a superlattice structure comprising alternating layers of an epitaxial piezoelectric material, such as aluminum nitride (A1N), and any one, or combination, of other III-N semiconductor materials. For instance, in accordance with some embodiments, aluminum indium nitride (Al_xIni_-xN), aluminum gallium nitride (Al_xGai_-xN), or aluminum indium gallium nitride (Al_xIn_yGai_-x-yN) may be interleaved with the AIN, and the particular compositional ratios thereof may be adjusted to customize resonator performance. In accordance with some embodiments, the superlattice layers may be formed via an epitaxial deposition process, allowing for precise control over film thicknesses, in some cases in the range of a few nanometers. By exploiting material composition differences and utilizing appropriate selective etch chemistries and techniques, individual constituent layers may be selectively removed from the superlattice with no (or otherwise negligible) impact on other layers, in accordance with some embodiments. In this manner, the superlattice structure may be thinned down, in nanometer-range increments, to achieve a given target resonance frequency for the host resonator device, in accordance with some embodiments. Numerous configurations and variations will be apparent in light of this disclosure.

General Overview

The particular resonance frequency of a thin-film bulk acoustic resonator (TFBAR, also called FBAR) depends, at least in part, on the thicknesses of its constituent layers. With traditional aluminum nitride (AlN)-based TFBARs, processing constraints require the AIN material to be deposited to a given thickness by sputter deposition after back electrode processing and subsequently trimmed. However, precision control over film thickness by sputter deposition is difficult, and thus sputtered AIN is generally of poorer quality than AIN layers formed, for example, by epitaxial deposition. For instance, consider the example case of a sputtered AIN film of 2 μπι thickness, which typically is characterized by X-ray diffraction (XRD) to have a full width at half maximum (FWFDVI) (002) of 2 degrees. In comparison, epitaxial AIN films can achieve thicknesses of about 0.5 μπι or less (e.g., 0.2 μπι), which are characterized by XRD to have a FWHM (002) of 0.4 degrees or less. Moreover, such film quality improvements may be obtained even in cases of epitaxial growth, for example, from a silicon (Si) substrate, which has a 41% lattice mismatch with AIN.

Thus, and in accordance with some embodiments of the present disclosure, techniques are disclosed for fabricating an integrated circuit including one or more thin-film bulk acoustic resonator (TFBAR, also called FBAR) devices. In accordance with some embodiments, a given TFBAR device may include a superlattice structure comprising alternating layers of an epitaxial piezoelectric material, such as aluminum nitride (AIN), and any one, or combination, of other III- N semiconductor materials. For instance, in accordance with some embodiments, aluminum indium nitride (Al_xIni_-xN), aluminum gallium nitride (Al_xGai_-xN), or aluminum indium gallium nitride (Al_xIn_yGai_-x-yN) may be interleaved with the AIN, and the particular compositional ratios thereof may be adjusted to customize resonator performance. In accordance with some embodiments, the superlattice layers may be formed via an epitaxial deposition process, allowing for precise control over film thicknesses, in some cases in the range of a few nanometers. By exploiting material composition differences and utilizing appropriate selective etch chemistries and techniques, individual constituent layers may be selectively removed from the superlattice with no (or otherwise negligible) impact on other layers, in accordance with some embodiments. In this manner, the superlattice structure may be thinned down, in nanometer-range increments, to achieve a given target resonance frequency for the host resonator device, in accordance with some embodiments.

In accordance with some embodiments, use of the disclosed techniques may realize improvements in controlled formation of layer thicknesses to nanometer-range precision as compared to existing sputter deposition and timed etch approaches, at least in some instances. In accordance with some embodiments, use of the disclosed techniques may provide for very precise control over the thickness of the constituent epitaxial layers of a superlattice structure and in thinning that structure to produce multiple TFBARs of different resonance frequencies over a commonly shared semiconductor substrate. In some instances, the disclosed techniques may be used in fabricating multiple TFBARs on a commonly shared semiconductor substrate, thus allowing for fabrication of multi-band, multi-mode communication filters integrated on the same die. More generally, the techniques described herein may be used, in accordance with some embodiments, to produce any desired quantity of resonator devices with as many different resonance frequencies as desired for a given target application or end-use.

In some instances, use of techniques described herein may result in III-N semiconductor superlattice structures including higher quality piezoelectric layer(s) that provide for higher electromechanical coupling and Q-factor RF devices. As will be appreciated in light of this disclosure, these improvements, in turn, may realize bandwidth increases, reductions in signal losses, and increases in the ability of the host RF filter to reject out-of-band signals. In some cases, TFBAR devices fabricated via the disclosed techniques may be utilized in RF filters and other RF devices that may be used in communication technologies that employ any one, or combination, of second-generation (2G), third-generation (3G), fourth-generation (4G), or long- term evolution (LTE) wireless standards, among others. In some instances, use of such devices may realize lower losses and higher signal integrity, from which host wireless communication platforms may benefit.

In accordance with some embodiments, structures provided as variously described herein may be configured for use, for example, in RF front-end modules in computing devices, mobile or otherwise, and various communication systems, although numerous other applications will be apparent in light of this disclosure. In accordance with some embodiments, structures provided as variously described herein may be configured for use, for example, in base stations, cellular communication towers, and the like. In accordance with some embodiments, use of the disclosed techniques may be detected, for example, by any one, or combination, of scanning electron microscopy (SEM), transmission electron microscopy (TEM), chemical composition analysis, energy-dispersive X-ray (EDX) spectroscopy, and secondary ion mass spectrometry (SIMS) of a given IC or other semiconductor structure having a plurality of resonator devices configured as variously described herein.

Methodology and Structure

Figures 1-9 illustrate a process flow for forming an IC 100 in accordance with an embodiment of the present disclosure. As can be seen from Figure 9 in particular, this process flow may be used, for example, to fabricate an IC 100 including one or more resonator devices (e.g., TFBARs) 101a, 101b, and so forth, of different resonance frequencies from a superlattice structure comprised of one or more piezoelectric III-N semiconductor materials, in accordance with some embodiments. It should be noted that although this process flow generally depicts and explains formation of two laterally adjacent resonator devices 101a and 101b, the present disclosure is not intended to be so limited, as in a more general sense, and in accordance with some embodiments, the disclosed techniques may be used to form any desired quantity of resonator devices having any desired target resonance frequencies in any desired arrangement over a commonly shared semiconductor substrate.

The process flow may begin as in Figure 1, which illustrates a cross-sectional view of an

IC 100 configured in accordance with an embodiment of the present disclosure. As can be seen, IC 100 may include a semiconductor substrate 102, which may have any of a wide range of configurations. For instance, semiconductor substrate 102 may be configured as any one, or combination, of a bulk semiconductor substrate, a silicon-on-insulator (SOI) structure or other semiconductor-on-insulator structure (XOI, where X represents a semiconductor material, such as silicon, germanium, germanium-enriched silicon, and so forth), a semiconductor wafer, and a multi-layered semiconductor structure. In some instances, semiconductor substrate 102 may be configured as a silicon-on-sapphire (SOS) structure.

Semiconductor substrate 102 may be comprised of any of a wide range of semiconductor materials. For instance, in some cases, semiconductor substrate 102 may be comprised of any one, or combination, of Group IV semiconductor materials, such as silicon (Si), germanium (Ge), or silicon-germanium (SiGe). In some instances, semiconductor substrate 102 may be comprised of Si having a crystallographic orientation of (111), (110), or (100), optionally with an offcut towards (110) in the range of about 1-10° (e.g., about 1-4°, about 4-7°, about 7-10°, or any other sub-range in the range of about 1-10°). In some other cases, semiconductor substrate 102 may be comprised of any one, or combination, of Group III-V compound semiconductor materials, such as gallium arsenide (GaAs) or indium phosphide (InP), among others. In some still other cases, semiconductor substrate 102 may be comprised of silicon carbide (SiC) or sapphire (α-Α1₂0₃). In some instances, the particular material composition of semiconductor substrate 102 may be chosen, at least in part, based on a target electrical resistivity range suitable for one or more resonator devices formed there over, as described herein. In some cases, semiconductor substrate 102 may have an electrical resistivity of about 1,000 Ω-cm or greater (e.g., about 1,200 Ω-cm or greater, about 1,500 Ω-cm or greater, and so forth).

It should be noted that semiconductor substrate 102 is not intended to be limited only to configurations and implementations as a substrate for a given host architecture, as in accordance with some other embodiments, semiconductor substrate 102 may be configured or otherwise implemented as an intermediate layer disposed in a given host architecture. Other suitable materials, configurations, and resistivity ranges for semiconductor substrate 102 will depend on a given application and will be apparent in light of this disclosure.

Also, as can be seen, IC 100 may include an electrode layer 104 disposed over a topography provided, in part or in whole, by semiconductor substrate 102. Electrode layer 104 may be comprised of any of a wide range of electrically conductive materials. For instance, in some cases, electrode layer 104 may be comprised of any one, or combination, of electrically conductive refractory materials, such as tungsten (W), molybdenum (Mo), tantalum nitride (TaN), titanium nitride (TiN), or an alloy of any thereof, to name a few. In some other cases, electrode layer 104 may be comprised of highly n-doped (e.g., n⁺) indium gallium nitride (In_xGai_-xN), where x is in the range of about 0.05-0.2. Some example suitable n-type dopants include silicon (Si) and germanium (Ge), to name a few.

Electrode layer 104 may be formed via any suitable standard, custom, or proprietary techniques, as will be apparent in light of this disclosure. In accordance with some embodiments, electrode layer 104 may be formed via any one, or combination, of a physical vapor deposition (PVD) process (e.g., sputtering), a chemical vapor deposition (CVD) process, and an atomic layer deposition (ALD) process, among others. The dimensions (e.g., z-thickness in the z-direction) of electrode layer 104 may be customized, as desired for a given target application or end-use. In some cases, electrode layer 104 may have a z-thickness in the range of about 200 nm or less (e.g., about 150 nm or less, about 100 nm or less, about 50 nm or less, or any other sub-range in the range of about 200 nm or less). Other suitable materials, formation techniques, and dimensions for electrode layer 104 will depend on a given application and will be apparent in light of this disclosure. As can be seen further, IC 100 may include a III-N semiconductor layer 106 disposed over a topography provided, in part or in whole, by electrode layer 104. In accordance with some embodiments, III-N semiconductor layer 106 may be configured as a superlattice structure (e.g., bi-layer, tri-layer, or other multi-layer) including alternating layers of III-N semiconductor materials. For instance, III-N semiconductor layer 106 may include: (1) a first constituent layer 106(i) comprised of a first III-N semiconductor material; and (2) an immediately adjacent second constituent layer 106(ii) (e.g., immediately superjacent and/or immediately subjacent) comprised of a different second III-N semiconductor material. In some instances, first and second layers 106(i) and 106(ii) may be repeated in an alternating manner (e.g., as generally can be seen in the portion of Figure 1 enclosed in the dashed box) or other given desired order. Additional third, fourth, and further constituent layers, each being comprised of a given III-N semiconductor material, optionally may be provided, in accordance with some embodiments. For consistency and ease of understanding of the present disclosure, constituent layers 106(i), 106(ii), and so forth hereinafter may be collectively referred to generally as constituent layers 106(«), except where separately referenced.

A given constituent layer 106(«) of III-N semiconductor layer 106 may be comprised of any one, or combination, of III-N semiconductor materials, including gallium nitride (GaN), aluminum nitride (A1N), indium nitride (InN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), and aluminum indium gallium nitride (AlInGaN). In some cases, III-N semiconductor layer 106 may be a superlattice structure including alternating layers of an A1N layer 106(i) and an Al_xIni_-xN layer 106(ii), where x is in the range of about 0.7-0.99. In a specific example such case, x = 0.9, and thus III-N semiconductor layer 106 includes alternating layers of A1N layer 106(i) and Alo.9Ino.1N layer 106(ii). In another specific example such case, x = 0.83, and thus III-N semiconductor layer 106 includes alternating layers of A1N layer 106(i) and Alo.83Ino.17N layer 106(ii). At x = 0.83, there may be no (or otherwise negligible) lattice mismatch between A1N layer 106(i) and Alo.83Ino.17N layer 106(ii). In some other cases, III-N semiconductor layer 106 may be a superlattice structure including alternating layers of an A1N layer 106(i) and an Al_xGai_-xN layer 106(ii), where x is in the range of about 0.01-0.5. In some other cases, III-N semiconductor layer 106 may be a superlattice structure including alternating layers of an A1N layer 106(i) and an Al_xIn_yGai_-x-yN layer 106(ii), where x is in the range of about 0.01-0.3 and y is in the range of about 0.01-0.1. In a specific example such case, x = 0.9 and y = 0.05, and thus III-N semiconductor layer 106 includes alternating layers of A1N layer 106(i) and Alo.9Ino.05Gao.05N layer 106(ii).

III-N semiconductor layer 106 may be formed via any suitable standard, custom, or proprietary techniques, as will be apparent in light of this disclosure. In accordance with some embodiments, a given constituent layer 106(«) of III-N semiconductor layer 106 may be formed via any one, or combination, of a chemical vapor deposition (CVD) process, such as metal- organic CVD (MOCVD), an epitaxy process, such as molecular beam epitaxy (MBE), or an atomic layer deposition (ALD) process, among others. The dimensions (e.g., z-thickness in the z-direction) of a given constituent layer 106(«) of III-N semiconductor layer 106 may be customized, as desired for a given target application or end-use. In some cases, a given constituent layer 106(«) of III-N semiconductor layer 106 may have a z-thickness in the range of about 1-10 nm (e.g., about 1-2.5 nm, about 2.5-5 nm, about 7-10 nm, or any other range in the sub-range of about 1-10 nm). In some instances, III-N semiconductor layer 106 may have a z- thickness in the range of about 0.5-3 μιη (e.g., about 0.5-1.75 μπι, about 1.75-3 μπι, or any other sub-range in the range of about 0.5-3 μιη). As will be appreciated in light of this disclosure, the particular z-thickness of a given constituent layer 106(«) of III-N semiconductor layer 106 may be tuned depending on how tightly spaced the target resonance frequencies are for a given target application or end-use. As will be further appreciated, precision control of such thickness may allow for very fine control in thinning a given III-N semiconductor layer 106 to provide one or multiple TFBARs of different resonance frequencies over the same semiconductor substrate 102, in accordance with some embodiments. Other suitable materials, formation techniques, configurations, and dimensions for III-N semiconductor layer 106 will depend on a given application and will be apparent in light of this disclosure.

IC 100 may include a hardmask layer 108 disposed over a topography provided, in part or in whole, by III-N semiconductor layer 106. Hardmask layer 108 may be comprised of any suitable hardmask material(s), as will be apparent in light of this disclosure. In some cases, hardmask layer 108 may be comprised of any one, or combination, of silicon nitride (Si₃N₄), silicon dioxide (Si0₂), and silicon oxynitride (SiO_xN_y), to name a few. Hardmask layer 108 may be formed via any suitable standard, custom, or proprietary technique(s), as will be apparent in light of this disclosure. In accordance with some embodiments, hardmask layer 108 may be formed via any one, or combination, of a physical vapor deposition (PVD) process (e.g., sputtering) and a chemical vapor deposition (CVD) process, among others. The dimensions (e.g., z-thickness in the z-direction) of hardmask layer 108 may be customized, as desired for a given target application or end-use. In some cases, hardmask layer 108 may have a z-thickness in the range of about 100-350 nm (e.g., about 100-225 nm, about 225-350 nm, or any other subrange in the range of about 100-350 nm). Other suitable materials, formation techniques, and dimensions for hardmask layer 108 will depend on a given application and will be apparent in light of this disclosure. The process flow may continue as in Figure 2, which illustrates a cross-sectional view of the IC 100 of Figure 1 after patterning with one or more features 110, in accordance with an embodiment of the present disclosure. A given feature 110 may be, for example, a trench, through-hole, or other opening or recess that extends through a full thickness (e.g., z-thickness in the z-direction) of hardmask layer 108, III-N semiconductor layer 106, and electrode layer 104, and into semiconductor substrate 102. A given feature 110 may be formed via any suitable standard, custom, or proprietary lithography, etch, and clean technique(s), as will be apparent in light of this disclosure. In accordance with some embodiments, a given feature 110 may be formed via any one, or combination, of a dry etch process and a wet etch process, the etch chemistry of which may be customized, as desired for a given target application or end-use. The dimensions (e.g., x-width in the x-direction; z-depth in the z-direction) and geometry of a given feature 110, as well as the pitch or other spacing of neighboring features 110, may be customized, as desired for a given target application or end-use. In some cases, a given feature 110 may have an x-width in the range of about 200-800 μιη (e.g., about 200-400 μπι, about 400-600 μπι, about 600-800 μπι, or any other sub-range in the range of about 200-800 μιη). As will be appreciated in light of this disclosure, the z-depth of a given feature 110 may be tuned, for example, so as to extend down through one or more intervening layers and into semiconductor layer 102, in accordance with some embodiments. Other suitable formation techniques, configurations, and dimensions for feature(s) 110 will depend on a given application and will be apparent in light of this disclosure.

In forming feature(s) 110, separated portions of hardmask layer 108, III-N semiconductor layer 106, and electrode layer 104 may remain over separate regions of semiconductor layer 102. For instance, as can be seen generally from Figure 2, a first stacked arrangement (e.g., a first mesa portion) including a first electrode layer portion 104a, a first III-N semiconductor layer portion 106a, and a first hardmask layer portion 108a may remain over a first portion of semiconductor substrate 102. As can be seen further, a second stacked arrangement (e.g., a second mesa portion) including a second electrode layer portion 104b, a second III-N semiconductor layer portion 106b, and a second hardmask layer portion 108b may remain over a second portion of semiconductor substrate 102.

In accordance with some embodiments, the remaining mesa portions may serve as initial defining points for what ultimately may become resonator devices 101a and 101b for IC 100 as they undergo additional processing, as described herein. The initial dimensions of a given mesa portion of either (or both) resonator device 101a or 101b may be customized, as desired for a given target application or end-use, and may depend, at least in part, on the dimensions of feature(s) 110 of IC 100. In some cases, either (or both) mesa portions of resonator devices 101a and 101b may have an x-width in the range of about 50-400 μιη (e.g., about 50-250 μπι, about 250-400 μπι, or any other sub-range in the range of about 50-400 μιη). In some cases, either (or both) mesa portions of resonator devices 101a and 101b may have a z-height in the range of about 1-3 μπι (e.g., about 1-2 μπι, about 2-3 μπι, or any other sub-range in the range of about 1-3 μιη).

The process flow may continue as in Figure 3, which illustrates a cross-sectional view of the IC 100 of Figure 2 after forming a dielectric layer 112, in accordance with an embodiment of the present disclosure. Dielectric layer 112 may be disposed over a topography provided, in part or in whole, by hardmask layer portions 108a, 108b, III-N semiconductor layer portions 106a, 106b, electrode layer portions 104a, 104b, and semiconductor substrate 102. Dielectric layer 112 may be comprised of any one, or combination, of a wide range of dielectric materials. For instance, in some embodiments, dielectric layer 112 may be comprised of an oxide, such as silicon oxide (Si0₂), aluminum oxide (A1₂0₃), hafnium oxide (Hf0₂), zirconium oxide (Zr0₂), tantalum oxide (Ta₂0₅), titanium oxide (Ti0₂), lanthanum oxide (La₂0₃), or carbon (C)-doped oxide (CDO), among others. In some embodiments, dielectric layer 112 may be comprised of a nitride, such as silicon mononitride (SiN) or silicon nitride (Si₃N₄), or an oxynitride, such as silicon oxynitride (SiON) or C-doped SiON, a carbide, such as silicon carbide (SiC), or an oxycarbonitride, such as silicon oxycarbonitride (SiOCN), among others. In some embodiments, dielectric layer 112 may be comprised of an organosilicate glass (SiCOH). In some embodiments, dielectric layer 112 may be comprised of an inorganic compound, such as hydrogen silsesquioxane (HSQ).

Dielectric layer 112 may be formed via any suitable standard, custom, or proprietary technique(s), as will be apparent in light of this disclosure. In accordance with some embodiments, dielectric layer 112 may be formed via any one, or combination, of a physical vapor deposition (PVD) process, such as sputter deposition, a spin-on deposition (SOD) process, a chemical vapor deposition (CVD) process, such as plasma-enhanced CVD (PECVD), and an atomic layer deposition (ALD) process, to name a few. The thickness (e.g., x-thickness in the x- direction; z-thickness in the z-direction) of dielectric layer 112 may be customized, as desired for a given target application or end-use. In some cases, dielectric layer 112 may have a z-thickness, for example, sufficient to fill a given feature 110. Any overburden of dielectric layer 112 may be removed, for example, via a chemical-mechanical planarization (CMP) process or other suitable planarization process. As will be appreciated in light of this disclosure, hardmask layer portions 108a, 108b may serve as a stop point in overburden removal, and thus a surface of hardmask layer portions 108a, 108b may be substantially co-planar with a surface of dielectric layer 112 (e.g., as generally can be seen in Figure 3). In accordance with some embodiments, dielectric layer 112 may be configured to serve as a shallow trench isolation (STI) layer for IC 100. Other suitable materials, formation techniques, configurations, and dimensions for dielectric layer 112 will depend on a given application and will be apparent in light of this disclosure.

The process flow may continue as in Figure 4, which illustrates a cross-sectional view of the IC 100 of Figure 3 after removing hardmask layer portion 108b and partially removing III-N semiconductor layer 106, in accordance with an embodiment of the present disclosure. As can be seen here, hardmask layer portion 108b may be removed from IC 100, exposing the surface of underlying III-N semiconductor layer portion 106b. Removal of hardmask layer portion 108b may be provided via any suitable standard, custom, or proprietary technique(s), as will be apparent in light of this disclosure. In accordance with some embodiments, hardmask layer portion 108b may be removed via any one, or combination, of a dry etch process and a wet etch process, the etch chemistry of which may be customized, as desired for a given target application or end-use. The particular etch process(es) employed may be selective to removal of the material of hardmask layer portion 108b as compared to the material of dielectric layer 112, for example, in accordance with some embodiments.

After removal of hardmask layer portion 108b, III-N semiconductor layer portion 106b may be thinned down in z-thickness, in accordance with some embodiments. For instance, III-N semiconductor layer portion 106b may undergo selective removal of one or more of its constituent layers 106(«). To that end, removal of individual constituent layers 106(«) of III-N semiconductor layer portion 106b may be provided via any one, or combination, of a dry etch process and a wet etch process, the etch chemistry of which may be customized, as desired for a given target application or end-use. In accordance with some embodiments, the applied etch chemistry may be comprised of sulfur hexafluoride (SF₆).

As previously discussed, III-N semiconductor layer portion 106b (of original III-N semiconductor layer 106) may include, at least in some embodiments, an alternating stack of a first constituent layer 106(i) and a second constituent layer 106(ii) which differ from one another in material composition. Thus, and in accordance with some embodiments, a given constituent layer 106(«) having a first material composition may be selectively removed with no, or otherwise negligible, impact on a vertically adjacent constituent layer 106(«) having a second, different material composition. For instance, a second constituent layer 106(ii) may be removed, in part or in whole, without removing a first constituent layer 106(i) vertically adjacent thereto. Equally, a first constituent layer 106(i) may be removed, in part or in whole, without removing a second constituent layer 106(ii) vertically adjacent thereto. Selective removal on a layer-by- layer basis may be possible, at least in part, because of the different material composition (and thus etch or other removal process selectivity) of vertically adjacent constituent layers 106(«) of III-N semiconductor layer portion 106b.

As will be appreciated in light of this disclosure, further selective removal of other constituent layers 106(«) may be performed until a given target z-thickness of III-N semiconductor layer portion 106b is achieved. By selectively removing constituent layers 106(«), one at a time, from III-N semiconductor layer portion 106b, fine tuning of the resonance frequency of resonator device 101b may be achieved, in accordance with some embodiments. In some cases, nanometer-range precision commensurate with the thickness of the individual constituent layers 106(«) may be achieved, in accordance with some embodiments. Consequently, resonator device 101b may differ in z-thickness from resonator device 101a by a distance (D), which may depend on the quantity and z-thicknesses of the one or more constituent layers 106(«) removed from III-N semiconductor layer portion 106b. In the example case generally illustrated by Figure 4, resonator device 101a may have a lower resonance frequency than resonator device 101b because III-N semiconductor layer portion 106a is of greater z- thickness than III-N semiconductor layer portion 106b.

The process flow may continue as in Figure 5, which illustrates a cross-sectional view of the IC 100 of Figure 4 after removing hardmask layer portion 108a and partially removing dielectric layer 112, in accordance with an embodiment of the present disclosure. As can be seen here, hardmask layer portion 108a may be removed from IC 100, exposing the surface of underlying III-N semiconductor layer portion 106a. Removal of hardmask layer portion 108a may be provided via any of the example techniques discussed above, for instance, with respect to removal of hardmask layer portion 108b, in accordance with some embodiments. As can be seen further, dielectric layer 112 may be reduced in z-thickness, for example, to a point where it is substantially co-planar with or recessed below an uppermost surface of either (or both) III-N semiconductor layer portion 106a and III-N semiconductor layer portion 106b, in accordance with some embodiments. In some cases, dielectric layer 112 may be reduced in z-thickness such that it is substantially co-planar with or recessed below the uppermost surface of whichever III-N semiconductor layer portion 106a, 106b, or other has the lowest z-thickness (e.g., partial removal of dielectric layer 112 may stop at a point which coincides with the thinnest of the superlattice structures of IC 100). Partial removal of dielectric layer 112 may be provided via any standard, custom, or proprietary lithography, etch, and clean processes, as will be apparent in light of this disclosure.

The process flow may continue as in Figure 6, which illustrates a cross-sectional view of the IC 100 of Figure 5 after patterning with one or more features 114, in accordance with an embodiment of the present disclosure. A given feature 114 may be, for example, a trench, through-hole, or other opening or recess that extends through a full thickness (e.g., z-thickness in the z-direction) of either III-N semiconductor layer portion 106a or 106b and lands on or otherwise extends into either electrode layer portion 104a or 104b. In forming a given feature 114, partial removal of III-N semiconductor layer portion 106a and electrode layer portion 104a or III-N semiconductor layer portion 106b and electrode layer portion 104b may be provided via any of the example techniques discussed above, for instance, with respect to feature(s) 110, in accordance with some embodiments. In forming a given feature 1 14, one or more sidewalls of a portion of dielectric layer 112 may be exposed (e.g., such as generally can be seen in Figure 6). Moreover, the particular dimensions and geometry of a given feature 114 may be customized, as desired for a given target application or end-use. Other suitable formation techniques, configurations, and dimensions for feature(s) 114 will depend on a given application and will be apparent in light of this disclosure.

The process flow may continue as in Figure 7, which illustrates a cross-sectional view of the IC 100 of Figure 6 after forming contact portions 116a and 116b and electrode layers 118a and 118b, in accordance with an embodiment of the present disclosure. As can be seen, a first contact portion 116a may be disposed within a feature 114 so as to contact (or otherwise be configured for electrical communication with) electrode layer portion 104a of resonator device 101a. Similarly, a second contact portion 116b may be disposed within a feature 114 so as to contact (or otherwise be configured for electrical communication with) electrode layer portion 104b of resonator device 101b. As can be seen further, a first electrode layer 118a may be disposed over a topography provided, in part or in whole, by III-N semiconductor layer portion 106a and dielectric layer 112. Similarly, a second electrode layer 118b may be disposed over a topography provided, in part or in whole, by III-N semiconductor layer portion 106b and dielectric layer 112.

As will be appreciated in light of this disclosure, first contact portion 116a, second contact portion 116b, first electrode layer 118a, and second electrode layer 118b may be provided with any of the example materials and formation techniques discussed above, for instance, with respect to electrode layer 104 (e.g., here in Figure 7, electrode layer portions 104a and 104b), in accordance with some embodiments. Moreover, the dimensions and geometry of first contact portion 116a and second contact portion 116b may be customized, as desired for a given target application or end-use, and may depend, at least in part, on the particular dimensions and geometry of a given host feature 114, in accordance with some embodiments. In some instances, either (or both) of first contact portion 116a and second contact portion 116b may extend along one or more sidewalls of a portion of dielectric layer 112 (e.g., such as generally can be seen in Figure 7). In some instances, either (or both) of first contact portion 116a and second contact portion 116b may have a portion that extends over an upper surface of a portion of dielectric layer 112 (e.g., such as generally can be seen in Figure 7). Furthermore, the dimensions and geometry of first electrode layer 118a and second electrode layer 118b may be customized, as desired for a given target application or end-use, and at least in some instances may be of any of the example dimensions and geometries discussed above, for instance, with respect to electrode layer 104 (e.g., here in Figure 7, electrode layer portions 104a and 104b), in accordance with some embodiments. Other suitable materials, formation techniques, configurations, and dimensions for first contact portion 116a, second contact portion 116b, first electrode layer 118a, and second electrode layer 118b will depend on a given application and will be apparent in light of this disclosure.

As can be seen further from Figure 7, in forming first contact portion 116a and first electrode layer 118a for resonator device 101a, a gap 120 may be provided there between, for example, to prevent electrical shorting. Similarly, in forming second contact portion 116b and second electrode layer 118b for resonator device 101b, a gap 120 may be provided there between for a similar purpose. A given gap 120 may be formed via any standard, custom, or proprietary technique(s), as will be apparent in light of this disclosure. In accordance with some embodiments, a masking and metallization process may be used to such ends. The particular dimensions and geometry of a given gap 120 may be customized, as desired for a given target application or end-use.

The process flow may continue as in Figure 8, which illustrates a cross-sectional view of the IC 100 of Figure 7 after forming a feature 122, in accordance with an embodiment of the present disclosure. A given feature 122 may be, for example, a trench, through-hole, or other opening or recess that extends through a full thickness (e.g., z-thickness in the z-direction) of a portion of dielectric layer 112 to a surface of underlying semiconductor substrate 102. In some instances, a given feature 122 may be disposed between a first contact portion 116a and a second contact portion 116b neighboring therewith (e.g., as generally can be seen in Figure 8). In forming a given feature 122, partial removal of dielectric layer 112 may be provided via any standard, custom, or proprietary lithography, etch, and clean processes, as will be apparent in light of this disclosure. Moreover, the particular dimensions and geometry of a given feature 122 may be customized, as desired for a given target application or end-use. Other suitable formation techniques, configurations, and dimensions for a given feature 122 will depend on a given application and will be apparent in light of this disclosure.

The process flow may continue as in Figure 9, which illustrates a cross-sectional view of the IC 100 of Figure 8 after forming a cavity 124 in semiconductor substrate 102, in accordance with an embodiment of the present disclosure. Partial removal of semiconductor substrate 102 to form a cavity 124 therein may be provided via any one, or combination, of a dry etch process and a wet etch process, the etch chemistry of which may be customized, as desired for a given target application or end-use. As will be appreciated in light of this disclosure, the particular etch chemistry employed in forming cavity 124 may depend on the particular material composition of semiconductor substrate 102. Thus, for instance, if semiconductor substrate 102 is a Si substrate or a Si-on-insulator (SOI) of Si-on-sapphire (SOS) substrate, then an etchant comprised of potassium hydroxide (KOH) or tetra-methyl ammonium hydroxide (TMAH) ((CH₃)₄NOH) may be utilized in removing Si material to form cavity 124, in accordance with some embodiments. If instead semiconductor substrate 102 is comprised of a Group III-V semiconductor material, such as GaAs or InP, for example, then an etchant comprised of phosphoric acid (H₃P0₄) containing hydrogen peroxide (H₂0₂) or comprised of a concentrated hydrochloric acid (HQ) or sulfuric acid (H₂S0₄) may be utilized in removing III-V material to form cavity 124, in accordance with some embodiments. Numerous other suitable etchants and etch schemes for various configurations of semiconductor substrate 102 will be apparent in light of this disclosure. Further note that the particular etch scheme employed may include either (or both) anisotropic and isotropic etching. In accordance with some embodiments, anisotropic etching may be utilized in forming feature 122, followed by isotropic etching to form cavity 124.

In any case, the etchant(s) employed in forming cavity 124 may be delivered to semiconductor substrate 102 through a given feature 122, which may serve as a sort of passageway that channels the etchant(s) to the exposed surface and, eventually, interior of semiconductor substrate 102. In a general sense, semiconductor substrate 102 may be considered, in part or in whole, a sacrificial layer (e.g., in that at least a portion thereof may be intentionally removed from IC 100). In partially removing semiconductor substrate 102, a first cavity portion 124a may form under electrode layer portion 104a of resonator device 101a, and a second cavity 124b may form under electrode layer portion 104b of resonator device 101b, in accordance with some embodiments. As will be appreciated in light of this disclosure, the particular quantity of cavities 124 (and thus cavity portions 124a, 124b, and so forth) may be customized, as desired for a given target application or end-use, and at least in some instances may be made to correspond with the particular quantity of resonator devices native to IC 100. Moreover, the particular dimensions and geometry of cavity 124 (and thus cavity portions 124a, 124b, and so forth) may be customized, as desired for a given target application or end-use. In etching thereunder, either (or both) of resonator devices 101a and 101b may extend over cavity 124 in a generally cantilevered manner over semiconductor substrate 102, in accordance with some embodiments. One or more electrical interconnection layers optionally may be formed over IC 100 to make any desired electrical connections for either (or both) of resonator devices 101a and 101b, in accordance with some embodiments.

As discussed herein, the various constituent layers of IC 100 may have any of a wide range of thicknesses (e.g., z-thicknesses in the z-direction, x-thicknesses in the x-direction, or other designated thickness), as desired for a given target application or end-use. In some instances, a given layer may be provided as a monolayer over an underlying topography. For a given IC configured as described herein, in some cases, a given constituent layer thereof may have a substantially uniform thickness over an underlying topography. In some instances, a given constituent layer may be provided as a substantially conformal layer over an underlying topography. In other instances, a given constituent layer may be provided with a non -uniform or otherwise varying thickness over an underlying topography. For example, in some cases, a first portion of a given layer may have a thickness within a first range, whereas a second portion thereof may have a thickness within a second, different range. In some instances, a given layer may have first and second portions having average thicknesses that are different from one another by about 20% or less, about 15% or less, about 10% or less, or about 5% or less. Numerous configurations and variations will be apparent in light of this disclosure.

Furthermore, as discussed herein, the various constituent layers of IC 100 may be disposed over one or more other constituent layers. In some cases, a first constituent layer may be disposed directly on a second constituent layer with no layers intervening. In some other cases, one or more intervening layers may be disposed between a first constituent layer and a second constituent layer underlying. In a more general sense, a given constituent layer may be disposed superjacent to another given constituent layer, optionally with one or more intervening layers, in accordance with some embodiments.

Example System

Figure 10 illustrates a computing system 1000 implemented with integrated circuit structures or devices formed using the disclosed techniques in accordance with an example embodiment. As can be seen, the computing system 1000 houses a motherboard 1002. The motherboard 1002 may include a number of components, including, but not limited to, a processor 1004 and at least one communication chip 1006, each of which can be physically and electrically coupled to the motherboard 1002, or otherwise integrated therein. As will be appreciated, the motherboard 1002 may be, for example, any printed circuit board, whether a main board, a daughterboard mounted on a main board, or the only board of system 1000, etc. Depending on its applications, computing system 1000 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 1002. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). Any of the components included in computing system 1000 may include one or more integrated circuit structures or devices formed using the disclosed techniques in accordance with an example embodiment. In some embodiments, multiple functions can be integrated into one or more chips (e.g., for instance, note that the communication chip 1006 can be part of or otherwise integrated into the processor 1004).

The communication chip 1006 enables wireless communications for the transfer of data to and from the computing system 1000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 1006 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing system 1000 may include a plurality of communication chips 1006. For instance, a first communication chip 1006 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1006 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 1004 of the computing system 1000 includes an integrated circuit die packaged within the processor 1004. In some embodiments, the integrated circuit die of the processor includes onboard circuitry that is implemented with one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein. The term "processor" may refer to any device or portion of a device that processes, for instance, electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 1006 also may include an integrated circuit die packaged within the communication chip 1006. In accordance with some such example embodiments, the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices formed using the disclosed techniques as described herein. As will be appreciated in light of this disclosure, note that multi -standard wireless capability may be integrated directly into the processor 1004 (e.g., where functionality of any chips 1006 is integrated into processor 1004, rather than having separate communication chips). Further note that processor 1004 may be a chip set having such wireless capability. In short, any number of processor 1004 and/or communication chips 1006 can be used. Likewise, any one chip or chip set can have multiple functions integrated therein.

In various implementations, the computing device 1000 may be a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device that processes data or employs one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein. Further Example Embodiments

The following examples pertain to further embodiments, from which numerous permutations and configurations will be apparent.

Example 1 is an integrated circuit including: a semiconductor substrate having a cavity formed therein; a first resonator device of a first resonance frequency, the first resonator device disposed over a first region of the cavity in the semiconductor substrate and including a first III- N semiconductor superlattice structure including at least one epitaxial piezoelectric layer; and a second resonator device of a second resonance frequency that differs from the first resonance frequency, the second resonator device disposed over a second region of the cavity in the semiconductor substrate and including a second III-N semiconductor superlattice structure including at least one epitaxial piezoelectric layer.

Example 2 includes the subject matter of any of Examples 1, 3-4, and 8-13, wherein at least one of the first III-N semiconductor superlattice structure and the second III-N semiconductor superlattice structure includes: an aluminum nitride (AIN) layer; and an aluminum indium nitride (Al_xIni_-xN) layer disposed over the AIN layer, wherein x is in the range of about 0.7-0.99.

Example 3 includes the subject matter of Example 2, wherein the Al_xIni_-xN layer includes

Example 4 includes the subject matter of Example 2, wherein the Al_xIni_-xN layer includes Alo.83Ino.17N. Example 5 includes the subject matter of any of Examples 1 and 8-13, wherein at least one of the first III-N semiconductor superlattice structure and the second III-N semiconductor superlattice structure includes: an aluminum nitride (A1N) layer; and an aluminum gallium nitride (Al_xGai_-xN) layer disposed over the A1N layer, wherein x is in the range of about 0.01- 0.5.

Example 6 includes the subject matter of any of Examples 1 and 7-13, wherein at least one of the first III-N semiconductor superlattice structure and the second III-N semiconductor superlattice structure includes: an aluminum nitride (A1N) layer; and an aluminum indium gallium nitride (Al_xIn_yGai_-x-yN) layer disposed over the A1N layer, wherein x is in the range of about 0.01-0.3 and y is in the range of about 0.01-0.1.

Example 7 includes the subject matter of Example 6, wherein the Al_xIn_yGai_-x-yN layer includes Alo.9Ino.05Gao.05N.

Example 8 includes the subject matter of any of Examples 1-7 and 9-13, wherein at least one of the first III-N semiconductor superlattice structure and the second III-N semiconductor superlattice structure includes at least one III-N semiconductor layer having a z-thickness in the range of about 1-10 nm.

Example 9 includes the subject matter of any of Examples 1-8 and 10-13, wherein the second III-N semiconductor superlattice structure is of a different z-thickness than the first III-N semiconductor superlattice structure.

Example 10 includes the subject matter of any of Examples 1-9 and 11-13, wherein at least one of the first III-N semiconductor superlattice structure and the second III-N semiconductor superlattice structure includes a plurality of epitaxial piezoelectric layers.

Example 11 includes the subject matter of any of Examples 1-10 and 12-13 and further includes at least one of: a first electrode disposed on a first side of the first III-N semiconductor superlattice structure; a second electrode disposed on a second side of the first III-N semiconductor superlattice structure; a third electrode disposed on a first side of the second III-N semiconductor superlattice structure; and a fourth electrode disposed on a second side of the second III-N semiconductor superlattice structure.

Example 12 includes the subject matter of Example 11, wherein at least one of the first electrode, the second electrode, the third electrode, and the fourth electrode includes at least one of tungsten (W), molybdenum (Mo), tantalum nitride (TaN), titanium nitride (TiN), and an alloy of any thereof.

Example 13 includes the subject matter of Example 11, wherein at least one of the first electrode, the second electrode, the third electrode, and the fourth electrode includes n-doped indium gallium nitride (In_xGai_-xN), wherein x is in the range of about 0.05-0.2. Example 14 is a method of fabricating an integrated circuit, the method including: forming a first resonator device over a first region of a semiconductor substrate, the first resonator device of a first resonance frequency and including a first III-N semiconductor superlattice structure including at least one epitaxial piezoelectric layer; forming a second resonator device over a second region of a semiconductor substrate, the second resonator device of a second resonance frequency that differs from the first resonance frequency and including a second III-N semiconductor superlattice structure including at least one epitaxial piezoelectric layer; and forming a cavity within the semiconductor substrate, wherein the cavity extends under at least one of the first resonator device and the second resonator device.

Example 15 includes the subject matter of any of Examples 14, 16-17, and 21-26, wherein at least one of the first III-N semiconductor superlattice structure and the second III-N semiconductor superlattice structure includes: an aluminum nitride (AIN) layer; and an aluminum indium nitride (Al_xIni_-xN) layer disposed over the AIN layer, wherein x is in the range of about 0.7-0.99.

Example 16 includes the subject matter of Example 15, wherein the Al_xIni_-xN layer includes Alo.9Ino.1N.

Example 17 includes the subject matter of Example 15, wherein the Al_xIni_-xN layer includes Alo.83Ino.17N.

Example 18 includes the subject matter of any of Examples 14 and 21-26, wherein at least one of the first III-N semiconductor superlattice structure and the second III-N semiconductor superlattice structure includes: an aluminum nitride (AIN) layer; and an aluminum gallium nitride (Al_xGai_-xN) layer disposed over the AIN layer, wherein x is in the range of about 0.01-0.5.

Example 19 includes the subject matter of any of Examples 14 and 20-26, wherein at least one of the first III-N semiconductor superlattice structure and the second III-N semiconductor superlattice structure includes: an aluminum nitride (AIN) layer; and an aluminum indium gallium nitride (Al_xIn_yGai_-x-yN) layer disposed over the AIN layer, wherein x is in the range of about 0.01-0.3 and y is in the range of about 0.01-0.1.

Example 20 includes the subject matter of Example 19, wherein the Al_xIn_yGai_-x-yN layer includes Alo.9Ino.05Gao.05N.

Example 21 includes the subject matter of any of Examples 14-20 and 22-26, wherein at least one of the first III-N semiconductor superlattice structure and the second III-N semiconductor superlattice structure includes at least one III-N semiconductor layer having a z- thickness in the range of about 1-10 nm. Example 22 includes the subject matter of any of Examples 14-21 and 23-26, wherein the second III-N semiconductor superlattice structure is of a different z-thickness than the first III-N semiconductor superlattice structure.

Example 23 includes the subject matter of any of Examples 14-22 and 24-26, wherein at least one of the first III-N semiconductor superlattice structure and the second III-N semiconductor superlattice structure includes a plurality of epitaxial piezoelectric layers.

Example 24 includes the subject matter of any of Examples 14-23 and 25-26 and further includes at least one of: forming a first electrode disposed on a first side of the first III-N semiconductor superlattice structure; forming a second electrode disposed on a second side of the first III-N semiconductor superlattice structure; forming a third electrode disposed on a first side of the second III-N semiconductor superlattice structure; and forming a fourth electrode disposed on a second side of the second III-N semiconductor superlattice structure.

Example 25 includes the subject matter of Example 24, wherein at least one of the first electrode, the second electrode, the third electrode, and the fourth electrode includes at least one of tungsten (W), molybdenum (Mo), tantalum nitride (TaN), titanium nitride (TiN), and an alloy of any thereof.

Example 26 includes the subject matter of Example 24, wherein at least one of the first electrode, the second electrode, the third electrode, and the fourth electrode includes n-doped indium gallium nitride (In_xGai_-xN), wherein x is in the range of about 0.05-0.2.

Example 27 is an integrated circuit including: a semiconductor substrate; a first thin-film bulk acoustic resonator (TFBAR) device of a first resonance frequency, the first TFBAR device disposed over a first region of the semiconductor substrate and including a first III-N semiconductor superlattice structure including alternating layers of epitaxial aluminum nitride (A1N) and at least one other III-N semiconductor layer; and a second TFBAR device of a second resonance frequency that differs from the first resonance frequency, the second TFBAR device disposed over a second region of the semiconductor substrate and including a second III-N semiconductor superlattice structure including alternating layers of epitaxial A1N and at least one other III-N semiconductor layer.

Example 28 includes the subject matter of any of Examples 27 and 29-34, wherein the first TFBAR device further includes: a first electrode disposed on a first side of the first III-N semiconductor superlattice structure; and a second electrode disposed on a second side of the first III-N semiconductor superlattice structure; wherein at least one of the first electrode and the second electrode includes at least one of an electrically conductive refractory material and indium gallium nitride (InGaN) doped with at least one of silicon and germanium. Example 29 includes the subject matter of any of Examples 27-28 and 30-34, wherein the second TFBAR device further includes: a first electrode disposed on a first side of the second III-N semiconductor superlattice structure; and a second electrode disposed on a second side of the second III-N semiconductor superlattice structure; wherein at least one of the first electrode and the second electrode includes at least one of an electrically conductive refractory material and indium gallium nitride (InGaN) doped with at least one of silicon and germanium.

Example 30 includes the subject matter of any of Examples 27-29 and 31-34, wherein the semiconductor substrate includes a Group IV semiconductor material.

Example 31 includes the subject matter of any of Examples 27-30 and 32-34, wherein the semiconductor substrate includes a Group III-V compound semiconductor material.

Example 32 includes the subject matter of any of Examples 27-31 and 33-34 and further includes a third TFBAR device of a third resonance frequency that differs from both the first resonance frequency and the second resonance frequency, the third TFBAR device disposed over a third region of the semiconductor substrate and including a third III-N semiconductor superlattice structure including alternating layers of epitaxial A1N and at least one other III-N semiconductor layer.

Example 33 includes a radio frequency (RF) filter including an integrated circuit including the subject matter of any of Examples 27-32 and 34.

Example 34 includes a mobile computing device including the RF filter including the subj ect matter of Example 33.

The foregoing description of example embodiments has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. Many modifications and variations are possible in light of this disclosure. It is intended that the scope of the present disclosure be limited not by this detailed description, but rather by the claims appended hereto. Future-filed applications claiming priority to this application may claim the disclosed subject matter in a different manner and generally may include any set of one or more limitations as variously disclosed or otherwise demonstrated herein.

Claims

CLAIMS What is claimed is:

1. An integrated circuit comprising:

a semiconductor substrate having a cavity formed therein;

a first resonator device of a first resonance frequency, the first resonator device disposed over a first region of the cavity in the semiconductor substrate and comprising a first III-N semiconductor superlattice structure comprising at least one epitaxial piezoelectric layer; and

a second resonator device of a second resonance frequency that differs from the first resonance frequency, the second resonator device disposed over a second region of the cavity in the semiconductor substrate and comprising a second III-N semiconductor superlattice structure comprising at least one epitaxial piezoelectric layer.

2. The integrated circuit of claim 1, wherein at least one of the first III-N semiconductor superlattice structure and the second III-N semiconductor superlattice structure comprises:

an aluminum nitride (A1N) layer; and

an aluminum indium nitride (Al_xIni_-xN) layer disposed over the A1N layer, wherein x is in the range of about 0.7-0.99.

3. The integrated circuit of claim 2, wherein the Al_xIni_-xN layer comprises

4. The integrated circuit of claim 2, wherein the Al_xIni_-xN layer comprises

5. The integrated circuit of claim 1, wherein at least one of the first III-N semiconductor superlattice structure and the second III-N semiconductor superlattice structure comprises:

an aluminum nitride (A1N) layer; and

an aluminum gallium nitride (Al_xGai_-xN) layer disposed over the A1N layer, wherein x is in the range of about 0.01-0.5.

6. The integrated circuit of claim 1, wherein at least one of the first III-N semiconductor superlattice structure and the second III-N semiconductor superlattice structure comprises:

an aluminum nitride (A1N) layer; and

an aluminum indium gallium nitride (Al_xIn_yGai_-x-yN) layer disposed over the A1N layer, wherein x is in the range of about 0.01-0.3 and y is in the range of about 0.01- 0.1.

7. The integrated circuit of claim 6, wherein the Al_xIn_yGai_-x-yN layer comprises

8. The integrated circuit of claim 1, wherein at least one of the first III-N semiconductor superlattice structure and the second III-N semiconductor superlattice structure comprises at least one III-N semiconductor layer having a z-thickness in the range of about 1- 10 nm.

9. The integrated circuit of any of claims 1-8 further comprising at least one of: a first electrode disposed on a first side of the first III-N semiconductor superlattice structure;

a second electrode disposed on a second side of the first III-N semiconductor superlattice structure;

a third electrode disposed on a first side of the second III-N semiconductor superlattice structure; and

a fourth electrode disposed on a second side of the second III-N semiconductor superlattice structure.

10. The integrated circuit of claim 9, wherein at least one of the first electrode, the second electrode, the third electrode, and the fourth electrode comprises at least one of tungsten (W), molybdenum (Mo), tantalum nitride (TaN), titanium nitride (TiN), and an alloy of any thereof.

11. The integrated circuit of claim 9, wherein at least one of the first electrode, the second electrode, the third electrode, and the fourth electrode comprises n-doped indium gallium nitride (In_xGai_-xN), wherein x is in the range of about 0.05-0.2.

12. A method of fabricating an integrated circuit, the method comprising: forming a first resonator device over a first region of a semiconductor substrate, the first resonator device of a first resonance frequency and comprising a first III-N semiconductor superlattice structure comprising at least one epitaxial piezoelectric layer;

forming a second resonator device over a second region of a semiconductor substrate, the second resonator device of a second resonance frequency that differs from the first resonance frequency and comprising a second III-N semiconductor superlattice structure comprising at least one epitaxial piezoelectric layer; and forming a cavity within the semiconductor substrate, wherein the cavity extends under at least one of the first resonator device and the second resonator device.

13. The method of claim 12, wherein at least one of the first III-N semiconductor superlattice structure and the second III-N semiconductor superlattice structure comprises:

an aluminum nitride (A1N) layer; and

14. The method of claim 12, wherein at least one of the first III-N semiconductor superlattice structure and the second III-N semiconductor superlattice structure comprises:

an aluminum nitride (A1N) layer; and

15. The method of claim 12, wherein at least one of the first III-N semiconductor superlattice structure and the second III-N semiconductor superlattice structure comprises:

an aluminum nitride (A1N) layer; and

16. The method of claim 12, wherein at least one of the first III-N semiconductor superlattice structure and the second III-N semiconductor superlattice structure comprises at least one III-N semiconductor layer having a z-thickness in the range of about 1-10 nm.

17. The method of any of claims 12-16 further comprising at least one of:

forming a first electrode disposed on a first side of the first III-N semiconductor superlattice structure;

forming a second electrode disposed on a second side of the first III-N semiconductor superlattice structure;

forming a third electrode disposed on a first side of the second III-N semiconductor superlattice structure; and

forming a fourth electrode disposed on a second side of the second III-N semiconductor superlattice structure.

18. The method of claim 17, wherein at least one of the first electrode, the second electrode, the third electrode, and the fourth electrode comprises at least one of tungsten (W), molybdenum (Mo), tantalum nitride (TaN), titanium nitride (TiN), and an alloy of any thereof.

19. The method of claim 17, wherein at least one of the first electrode, the second electrode, the third electrode, and the fourth electrode comprises n-doped indium gallium nitride (In_xGai_-xN), wherein x is in the range of about 0.05-0.2.

20. An integrated circuit comprising:

a semiconductor substrate;

a first thin-film bulk acoustic resonator (TFBAR) device of a first resonance frequency, the first TFBAR device disposed over a first region of the semiconductor substrate and comprising a first III-N semiconductor superlattice structure comprising alternating layers of epitaxial aluminum nitride (A1N) and at least one other III-N semiconductor layer; and

a second TFBAR device of a second resonance frequency that differs from the first resonance frequency, the second TFBAR device disposed over a second region of the semiconductor substrate and comprising a second III-N semiconductor superlattice structure comprising alternating layers of epitaxial A1N and at least one other III-N semiconductor layer.

21. The integrated circuit of claim 20, wherein the semiconductor substrate comprises a Group IV semiconductor material.

22. The integrated circuit of claim 20, wherein the semiconductor substrate comprises a Group III-V compound semiconductor material.

23. The integrated circuit of claim 20 further comprising a third TFBAR device of a third resonance frequency that differs from both the first resonance frequency and the second resonance frequency, the third TFBAR device disposed over a third region of the semiconductor substrate and comprising a third III-N semiconductor superlattice structure comprising alternating layers of epitaxial A1N and at least one other III-N semiconductor layer.

24. A radio frequency (RF) filter comprising the integrated circuit of any of claims

20-23.

25. A mobile computing device comprising the RF filter of claim 24.