WO2018004565A1

WO2018004565A1 - Techniques for forming iii-n semiconductor devices with integrated diamond heat spreader

Info

Publication number: WO2018004565A1
Application number: PCT/US2016/040051
Authority: WO
Inventors: Sansaptak DASGUPTA; Han Wui Then; Marko Radosavljevic; Paul B. Fischer
Original assignee: Intel Corporation
Priority date: 2016-06-29
Filing date: 2016-06-29
Publication date: 2018-01-04

Abstract

Techniques are disclosed for forming III-N semiconductor devices including integrated diamond heat spreader structures. In accordance with some embodiments, through-hole features may be formed in a silicon (Si) or other semiconductor substrate under a back side of a power amplifier device and filled, in part or in whole, with diamond material. In accordance with other embodiments, one or more layers of diamond material may be formed over a front side of a power amplifier device. The presence of diamond layers or structures (or both) may serve to facilitate heat dissipation for the host architecture, in accordance with some embodiments. The disclosed techniques may be used, for example, in fabricating high-power-density gallium nitride (GaN)-based radio frequency (RF) power amplifiers having integrated diamond heat spreaders configured to provide efficient heat extraction and thermal conductivity from the front and/or back side thereof. The improved heat extraction performance may lead to improved device reliability.

Description

TECHNIQUES FOR FORMING III-N SEMICONDUCTOR DEVICES WITH INTEGRATED DIAMOND HEAT SPREADER

BACKGROUND

Power amplifiers, voltage regulators, and other wireless communication and power management devices can utilize solid-state transistor devices. A field-effect transistor (FET) is a semiconductor device that includes three terminals: a gate, a source, and a drain. Through application of an electric field produced by the gate, the electrical conductivity of a nearby semiconductor channel may be controlled in a manner that allows charge carriers, such as electrons or holes, to flow between the source and drain. In instances where the charge carriers are electrons, the FET is referred to as an n-channel device. In instances where the charge carriers are holes, the FET is referred to as a p-channel device. Some FETs have a fourth terminal known as the body or substrate, which can be used to bias the transistor. A metal- oxide-semiconductor FET (MOSFET) is typically configured with an insulator between the gate and the body of the transistor, and MOSFETs are commonly used for amplifying or switching electronic signals. Complementary MOS (CMOS) devices use a combination of p-channel MOS (PMOS) and n-channel MOS (NMOS) devices to implement logic gates and other digital circuits.

BRIEF DESCRIPTION OF THE DRAWINGS

Figures 1-5 illustrate cross-sectional views of several integrated circuits (ICs) including a III-N semiconductor device layer configured in accordance with some embodiments of the present disclosure.

Figures 6A-6F illustrate a process flow for forming an IC, in accordance with another embodiment of the present disclosure.

Figures 7-8 illustrate cross-sectional views of the IC of Figure 6F after forming a metal layer, in accordance with some embodiments of the present disclosure.

Figures 9A-9G illustrate a process flow for forming an IC, in accordance with another embodiment of the present disclosure.

Figures 10A-10D illustrate a process flow for forming an IC, in accordance with another embodiment of the present disclosure.

Figures 11 A-l 1H illustrate a process flow for forming an IC, in accordance with another embodiment of the present disclosure. Figure 12 illustrates a computing system implemented with IC structures or devices formed using the disclosed techniques in accordance with an example embodiment.

These and other features of the present embodiments will be understood better by reading the following detailed description, taken together with the figures herein described. In the drawings, each identical or nearly identical component that is illustrated in various figures may be represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing. Furthermore, as will be appreciated, the figures are not necessarily drawn to scale or intended to limit the described embodiments to the specific configurations shown. For instance, while some figures generally indicate straight lines, right angles, and smooth surfaces, an actual implementation of the disclosed techniques may have less than perfect straight lines and right angles, and some features may have surface topography or otherwise be non-smooth, given real-world limitations of fabrication processes. In short, the figures are provided merely to show example structures.

DETAILED DESCRIPTION

Techniques are disclosed for forming III-N semiconductor devices including integrated diamond heat spreader structures. The techniques are particularly well-suited for use, for example, with power amplifiers and other devices prone to high heat generation. In accordance with some embodiments, one or more through-hole features may be formed in a silicon (Si) or other semiconductor substrate under a back side of a power amplifier device, and the resultant feature(s) may be filled, in part or in whole, with diamond material. In accordance with other embodiments, one or more layers of diamond material may be formed over a front side of a power amplifier device. In either case, the presence of diamond layers or structures (or both) may serve to facilitate heat dissipation for the power amplifier or other host architecture, in accordance with some embodiments. The disclosed techniques may be used, for example, in fabricating high-power-density gallium nitride (GaN)-based radio frequency (RF) power amplifiers having integrated diamond heat spreaders configured to provide efficient heat extraction and thermal conductivity from the front side or the back side (or both) thereof. In some instances, the improved heat extraction performance may lead to improved device reliability. Numerous configurations and variations will be apparent in light of this disclosure. General Overview

Gallium nitride (GaN)-based radio frequency (RF) power amplifiers typically have a high output power (P_out) density. During operation, channel temperatures rise, resulting in self- heating, and if the device temperature exceeds a certain threshold, current collapse and eventual device failure may result. These difficulties are compounded in the case of GaN-on-silicon (GaN-on-Si) configurations, as Si is not a particularly good thermal conductor. Although diamond is an efficient thermal conductor and is compatible for integration with GaN-based platforms, diamond substrates available for direct growth of GaN tend to be very small in size, making existing approaches insufficient for scaling to high-volume manufacturing. Moreover, RF front-ends typically utilize Si-based complementary metal-oxide-semiconductor (CMOS) circuitry for logic and other functional circuitry, and thus complete integration of such diverse material systems and components on diamond substrates may not be feasible.

Thus, and in accordance with some embodiments of the present disclosure, techniques are disclosed for forming III-N semiconductor devices including integrated diamond heat spreader structures. In accordance with some embodiments, one or more through-hole features may be formed in a silicon (Si) or other semiconductor substrate under a back side of a power amplifier (PA) device, and the resultant feature(s) may be filled, in part or in whole, with diamond material. In accordance with some other embodiments, one or more layers of diamond material may be formed over a front side of a PA device. In either case, the presence of diamond layers or structures (or both) may serve to facilitate heat dissipation for the host architecture, in accordance with some embodiments. The disclosed techniques may be used, for example, in fabricating high-power-density gallium nitride (GaN)-based radio frequency (RF) PAs and other III-N-based hot-running circuitry having integrated diamond heat spreaders configured to provide efficient heat extraction and thermal conductivity from the front side or the back side (or both) thereof. In some instances, the improved heat extraction performance may lead to improved device reliability.

In accordance with some embodiments, structures provided as variously described herein may be configured for use, for example, in RF front-end modules in computing devices, mobile or otherwise, although numerous other applications will be apparent in light of this disclosure. In accordance with some embodiments, structures provided as variously described herein may be configured for use, for example, in base stations, cellular communication towers, and the like. In some instances, the disclosed techniques may be used, for example, in co-integrating high- performance voltage regulator (VR) circuits and RF front-end devices in GaN with Si CMOS. In accordance with some embodiments, use of the disclosed techniques may be detected, for example, by any one, or combination, of scanning electron microscopy (SEM), transmission electron microscopy (TEM), chemical composition analysis, energy-dispersive X-ray (EDX) spectroscopy, and secondary ion mass spectrometry (SFMS) of a given IC or other transistor structure having a diamond layer configured as variously described herein. Example III-N Semiconductor Integrated Circuit Structures

Figure 1 illustrates a cross-sectional view of an integrated circuit (IC) 100a including a III-N semiconductor device layer 10a configured in accordance with an embodiment of the present disclosure. As can be seen, IC 100a includes a semiconductor substrate 102, which may have any of a wide range of configurations. For instance, semiconductor substrate 102 may be configured as any one, or combination, of a bulk semiconductor substrate, a silicon-on-insulator (SOI) structure or other semiconductor-on-insulator structure (XOI, where X represents a semiconductor material, such as silicon, germanium, germanium-enriched silicon, and so forth), a semiconductor wafer, and a multi-layered semiconductor structure. In accordance with some embodiments, semiconductor substrate 102 may be comprised of any one, or combination, of semiconductor materials, such as silicon (Si), germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), and sapphire (A1₂0₃), among others. In some embodiments, semiconductor substrate 102 may be comprised of Si having a crystallographic orientation of (111), (110), or (100), optionally with an offcut towards (110) in the range of about 1-10° (e.g., about 1-4°, about 4-7°, about 7-10°, or any other sub-range in the range of about 1-10°). Other suitable materials and configurations for semiconductor substrate 102 will depend on a given application and will be apparent in light of this disclosure.

Also, IC 100a includes a buffer layer 104 disposed over a topography provided, in part or in whole, by semiconductor substrate 102. In accordance with some embodiments, buffer layer 104 may be configured to serve, at least in part, as a nucleation layer for forming a III-N semiconductor layer 106 (discussed below). To that end, buffer layer 104 may be comprised of any one, or combination, of suitable nucleation material(s), such as aluminum nitride (A1N), aluminum gallium nitride (AlGaN), or an alloy of any thereof, to name a few. The dimensions (e.g., z-thickness in the z-direction) of buffer layer 104 may be customized, as desired for a given target application or end-use. In some cases, buffer layer 104 may have a z-thickness in the range of about 10-500 nm (e.g., about 10-250 nm, about 250-500 nm, or any other sub-range in the range of about 10-500 nm). Other suitable materials, configurations, and dimensions for buffer layer 104 will depend on a given application and will be apparent in light of this disclosure.

As can be seen further, IC 100a includes: (1) a III-N semiconductor layer 106 disposed over a topography provided, in part or in whole, by buffer layer 104; (2) a III-N semiconductor layer 108 disposed over a topography provided, in part or in whole, by III-N semiconductor layer 106; and (3) a III-N semiconductor layer 110 disposed over a topography provided, in part or in whole, by III-N semiconductor layer 108. Each of III-N semiconductor layers 106, 108, and 110 may be comprised of any one, or combination, of III-N semiconductor materials, including gallium nitride (GaN), aluminum nitride (A1N), indium nitride (InN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), and aluminum indium gallium nitride (AlInGaN).

In some embodiments, any (or all) of III-N semiconductor layers 106, 108, and 110 may include one or more three-dimensional semiconductor structures, such as island-like semiconductor bodies or nanowire or nanoribbon semiconductor bodies, to name a few. In some embodiments, any (or all) of III-N semiconductor layers 106, 108, and 110 may be configured as a single-layer structure, whereas in some other embodiments, any (or all) of III-N semiconductor layers 106, 108, and 110 may be configured as a bi-layer, tri -layer, or other multi-layer structure. In some cases, any (or all) of III-N semiconductor layers 106, 108, and 110 may be configured such that each of a first constituent layer and an immediately adjacent constituent layer (e.g., immediately superjacent and/or immediately subjacent) is comprised of the same III-N semiconductor material. In some other cases, any (or all) of III-N semiconductor layers 106, 108, and 110 may be configured as a superlattice structure including alternating layers of III-N semiconductor materials. For instance, a given III-N semiconductor layer 106, 108, or 110 may include a first constituent layer comprised of a first III-N semiconductor material and an immediately adjacent constituent layer (e.g., immediately superjacent and/or immediately subjacent) comprised of a different second III-N semiconductor material. In some such instances, the first and second constituent layers may be repeated in an alternating manner or other given desired order. Additional third, fourth, and further constituent layers optionally may be provided, in accordance with some embodiments.

In a more general sense, IC 100a may include one or more semiconductor layers formed as blanket films over semiconductor substrate 102, in accordance with some embodiments. In accordance with some embodiments, III-N semiconductor layer 110 may be a polarization layer configured to induce a two-dimensional electron gas (2DEG) in underlying III-N semiconductor layer 108. In a specific example case, IC 100a may include a Si substrate 102, an A1N buffer layer 104, a multi-layer stack of AlGaN layers 106, a GaN layer 108, and either (or both) an AlGaN or AlInN capping layer 110. Numerous configurations and variations for each of III-N semiconductor layers 106, 108, and 110 will be apparent in light of this disclosure.

Figure 2 illustrates a cross-sectional view of an IC 100b including a III-N semiconductor device layer 10b configured in accordance with an embodiment of the present disclosure. As can be seen, IC 100b includes a semiconductor substrate 102 and a shallow trench isolation (STI) layer 112 disposed over a topography provided, in part or in whole, by semiconductor substrate 102 and patterned with one or more features 112a (e.g., STI trenches). STI layer 112 may be comprised of any of a wide range of suitable dielectric materials, as will be apparent in light of this disclosure. In some cases, STI layer 112 may be comprised of an oxide, such as silicon oxide (Si0₂), aluminum oxide (A1₂0₃), hafnium oxide (Hf0₂), zirconium oxide (Zr0₂), tantalum oxide (Ta₂0₅), titanium oxide (Ti0₂), lanthanum oxide (La₂0₃), or carbon (C)-doped oxide (CDO), among others. In some other cases, STI layer 112 may be comprised of a nitride, such as silicon nitride (Si₃N₄). In some other cases, STI layer 112 may be comprised of an oxynitride, such as silicon oxynitride (SiON) or C-doped SiON. In some other cases, STI layer 112 may be comprised of a carbide, such as silicon carbide (SiC). In some other cases, STI layer 112 may be comprised of an oxycarbonitride, such as silicon oxycarbonitride (SiOCN).

As can be seen further, IC 100b optionally includes a buffer layer 104 disposed within features 112a, over a topography provided, in part or in whole, by semiconductor substrate 102 and STI layer 112. When included, optional buffer layer 104 may be provided with any of the example materials, configurations, and dimensions discussed above, for instance, with respect to buffer layer 104 of IC 100a, in accordance with some embodiments. Also, IC 100b includes: (1) a III-N semiconductor layer 108 disposed over a topography provided, in part or in whole, by STI layer 112 and semiconductor substrate 102 (or buffer layer 104, if optionally included); and (2) a III-N semiconductor layer 110 disposed over a topography provided, in part or in whole, by III-N semiconductor layer 108 and STI layer 1 12. As will be appreciated in light of this disclosure, feature(s) 112a may be utilized in forming III-N semiconductor layer 108, for example, by providing aspect ratio trapping (ART) of defects. Feature(s) 112a of the patterned STI layer 112 may be at least partially filled with III-N semiconductor material (and, optionally, buffer layer 104 material), resulting in epitaxial lateral overgrowth (ELO) of the III-N material over a topography of STI layer 112, in accordance with some embodiments.

Figure 3 illustrates a cross-sectional view of an IC 100c including a III-N semiconductor device layer 10c configured in accordance with an embodiment of the present disclosure. Also, as can be seen, IC 100c optionally includes a buffer layer 104 disposed within feature 112b, over a topography provided, in part or in whole, by semiconductor substrate 102 and STI layer 112. When included, optional buffer layer 104 may be provided with any of the example materials, configurations, and dimensions discussed above, for instance, with respect to buffer layer 104 of ICs 100a and 100b, in accordance with some embodiments. As can be seen further, IC 100c includes a semiconductor substrate 102 and an STI layer 112 disposed over a topography provided, in part or in whole, by semiconductor substrate 102 and patterned with a feature 112b. Also, IC 100c includes: (1) a III-N semiconductor layer 108 disposed over a topography provided, in part or in whole, by STI layer 112 and semiconductor substrate 102 (or buffer layer 104, if optionally included); and (2) a III-N semiconductor layer 110 disposed over a topography provided, in part or in whole, by III-N semiconductor layer 108 and STI layer 112. As will be appreciated in light of this disclosure, feature 112b may be utilized in forming III-N semiconductor layer 108, for example, by providing ART of defects. Feature 112b of the patterned STI layer 112 may be at least partially filled with III-N semiconductor material (and, optionally, buffer layer 104 material), resulting in ELO of the III-N semiconductor material over a topography of STI layer 112, in accordance with some embodiments.

Figure 4 illustrates a cross-sectional view of an IC lOOd including a III-N semiconductor device layer lOd configured in accordance with an embodiment of the present disclosure. As can be seen, IC lOOd is configured much the same as IC 100c and further includes source/drain (S/D) portions 114 disposed over a topography provided, in part or in whole, by III-N semiconductor layer 110. S/D portions 114 may be comprised of any one, or combination, of suitable S/D materials, such as GaN, InGaN, or SiC, to name a few. In accordance with some embodiments, a given S/D portion 114 may be doped, at least in part, with a p-type dopant, such as boron (B) or magnesium (Mg), thereby providing p-type S/D portion(s). In accordance with some embodiments, a given S/D portion 114 may be doped, at least in part, with an n-type dopant, such as Si, arsenic (As), or phosphorous (P), thereby providing n-type S/D portion(s). The particular dopant type and concentration, as well as the doping profile (e.g., dopant gradient or other variation, if any) may be customized, as desired for a given target application or end-use.

IC lOOd further includes a gate portion 116 disposed over a topography provided, in part or in whole, by III-N semiconductor layer 108. In accordance with some embodiments, gate portion 116 may include one or more gate dielectric layers and one or more gates disposed there over. In an example case, gate portion 116 may be configured as a replacement metal gate (RMG) process layer including one or more dummy gate dielectric layers and one or more RMG process gates disposed there over. In accordance with some embodiments, a given gate dielectric layer (dummy or otherwise) of gate portion 116 may be comprised of any one, or combination, of suitable dielectric materials, such as aluminum oxide (A1₂0₃), hafnium oxide (Hf0₂), silicon dioxide (Si0₂), silicon nitride (Si₃N₄), and zirconium dioxide (Zr0₂), to name a few. In accordance with some embodiments, a given gate (RMG process gate or otherwise) of gate portion 116 may be comprised of any one, or combination, of suitable metals or metal nitrides, such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), titanium nitride (TiN), or an alloy of any thereof, to name a few.

Figure 5 illustrates a cross-sectional view of an IC lOOe including a III-N semiconductor device layer lOe configured in accordance with an embodiment of the present disclosure. As can be seen here, IC lOOe includes two ICs lOOd at least partially isolated from one another via a dielectric layer 118, as well as operatively coupled with one another via an electrically conductive feature 120 connecting gate portions 116. As will be appreciated in light of this disclosure, IC lOOe of Figure 5 is configured in a manner that provides greater electrical impedance (Z), for example, than IC lOOd of Figure 4. Electrically conductive feature 120 may be a metal line or other electrically conductive body comprised of any suitable electrically conductive materials, such as any on, or combination, of copper (Cu), aluminum (Al), tungsten (W), or an alloy of any thereof, to name a few.

IC lOOe further includes a dielectric layer 122 disposed over a topography provided, in part or in whole, by electrically conductive feature 120, gate portions 116, and dielectric layer 118. Each of dielectric layers 118 and 122 may be comprised of any of the example materials discussed above, for instance, with respect to STI layer 112, in accordance with some embodiments. In some cases, dielectric layer 118 and dielectric layer 122 may differ in material composition, whereas in other cases, they may be of the same material composition.

For consistency and ease of understanding of the present disclosure, ICs lOOa-lOOe hereinafter may be collectively referred to generally as ICs 100, except where separately referenced. In addition, III-N semiconductor device layers lOa-lOe hereinafter may be collectively referred to generally as III-N semiconductor device layers 10, except where separately referenced. In accordance with some embodiments, a given IC 100 may be configured as a transistor device, such as a III-N semiconductor-based radio frequency (RF) power amplifier (PA). In some cases, a transistor device provided as variously described herein may be configured as a metal layer zero (M0) transistor device, though the present disclosure is not intended to be so limited, as other metal layers (e.g., Ml through M9, any beyond) may host such devices, in accordance with some embodiments. In some cases, interconnects and dielectrics may be utilized to form an RF PA of larger electrical impedance (e.g., such as is discussed above with respect to Figure 5).

Methodologies and Structure

Figures 6A-6F illustrate a process flow for forming an IC 200 in accordance with an embodiment of the present disclosure. As can be seen from Figure 6F in particular, this process flow may be used, for example, to fabricate an IC 200 including one or more diamond bodies 132 disposed under a back side of a III-N semiconductor device layer 10, in accordance with some embodiments.

The process flow may begin as in Figure 6 A, which illustrates a cross-sectional view of an IC 200 configured in accordance with an embodiment of the present disclosure. As can be seen, IC 200 may include a semiconductor substrate 102 (discussed above) patterned with one or more features 130. A given feature 130 may be, for example, a trench, through-hole, or other opening or recess that extends through at least a partial thickness (e.g., z-thickness in the z- direction) of semiconductor substrate 102.

A given feature 130 may be formed via any suitable standard, custom, or proprietary lithography, etch, and clean technique(s), as will be apparent in light of this disclosure. In accordance with some embodiments, a given feature 130 may be formed via any one, or combination, of a dry etch process and a wet etch process, the etch chemistry of which may be customized, as desired for a given target application or end-use.

The dimensions (e.g., x-width in the x-direction; z-height in the z-direction) and geometry of a given feature 130, as well as the pitch or other spacing of neighboring features 130, may be customized, as desired for a given target application or end-use. In some cases, a given feature 130 may have a z-height in the range of about 200-550 μιη (e.g., about 200- 375 μιη, about 375-550 μιτι, or any other sub-range in the range of about 200-550 μιη). In some cases, a given feature 130 may have an x-width in the range of about 1-10 μιη (e.g., about 1- 4 μιη, about 4-7 μιτι, about 7-10 μιτι, or any other sub-range in the range of about 1-10 μιη). In some instances, a given feature 130 may have a geometry (top-down; side) that is generally polygonal in shape (e.g., rectangular, square, pentagonal, hexagonal, and so forth). In some other instances, a given feature 130 may have a geometry (top-down; side) that is generally curvilinear in shape (e.g., circular, elliptical, arcuate, parabolic, and so forth). In some embodiments, a given feature 130 may be generally prismatic in shape (e.g., quadrangular prismatic, pentagonal prismatic, hexagonal prismatic, and so forth). In some embodiments, a given feature 130 may be generally cylindrical in shape (e.g., circular cylindrical, elliptical cylindrical, and so forth). In some cases, a given feature 130 may have substantially vertical sidewalls (e.g., within about 2° of being vertically straight). In some cases, a given feature 130 may have tapered sidewalls (e.g., outside of about 2° of being vertically straight).

Moreover, the quantity, arrangement, and density of features 130 may be customized, as desired for a given target application or end-use, and in some instances may depend, at least in part, on the areal footprint of the back side of a given III-N semiconductor device layer 10 (Figure 6C) to be disposed there over, in accordance with some embodiments. In some embodiments, feature(s) 130 may be distributed, in part or in whole, as a regular array in which all (or some sub-set) of feature(s) 130 are arranged in a systematic manner in relation to one another. In some embodiments, feature(s) 130 may be distributed, in part or in whole, as a semi- regular array in which a sub-set of feature(s) 130 are arranged in a systematic manner in relation to one another, but at least one other feature 130 is not so arranged. In some embodiments, feature(s) 130 may be distributed, in part or in whole, as an irregular array in which all (or some sub-set) of feature(s) 130 are not arranged in a systematic manner in relation to one another. In some cases, neighboring features 130 may be spaced apart from one another by a distance in the range of about 1-10 μιη (e.g., about 1-4 μπι, about 4-7 μπι, about 7-10 μπι, or any other subrange in the range of about 1-10 μιη). Other suitable formation techniques, configurations, and dimensions for feature(s) 130 of semiconductor substrate 102 will depend on a given application and will be apparent in light of this disclosure.

The process flow may continue as in Figure 6B, which illustrates a cross-sectional view of the IC 200 of Figure 6A after forming a diamond layer 132, in accordance with an embodiment of the present disclosure. As can be seen here, diamond layer 132 may comprise one or more through-body via (TBV)-like bodies, in accordance with some embodiments. However, the present disclosure is not intended to be so limited only to TBV-like diamond bodies, as in accordance with some other embodiments, diamond layer 132 may be formed as one or more layers (e.g., coatings, films, and so forth), such as generally can be seen with respect to Figure IOC, for example, discussed below.

Diamond layer 132 may be comprised of a diamond material, synthetic or naturally occurring (or both), and may be disposed, at least in part, within feature(s) 130 of semiconductor substrate 102, in accordance with some embodiments. Diamond layer 132 may be formed via a chemical vapor deposition (CVD) process or any other suitable standard, custom, or proprietary technique(s), as will be apparent in light of this disclosure. In accordance with some embodiments, diamond layer 132 may be formed, in part or in whole, via a CVD process provided at a temperature in the range of about 600-800 °C (e.g., about 600-700 °C, about 700- 800 °C, or any other sub-range in the range of about 600-800 °C). Also, CVD of diamond layer 132 may utilize any suitable standard, custom, or proprietary carbon (C) precursors, as will be apparent in light of this disclosure.

Any overburden of diamond layer 132 may be removed, for example, via a chemical - mechanical planarization (CMP) process or other suitable planarization process. The dimensions (e.g., x-width in the x-direction; z-height in the z-direction) and geometry of a given diamond body 132, as well as the pitch or other spacing of neighboring diamond bodies 132, may be customized, as desired for a given target application or end-use. In some instances, the dimensions and geometry of a given diamond body 132 may depend, at least in part, on the particular dimensions and geometry of a given host feature 130 of semiconductor substrate 102. In some cases, a given diamond body 132 may have at least one of a z-height and an x-width less than or about equal to the example z-height and x-width ranges discussed above, for instance, with respect to feature(s) 130.

Moreover, the quantity, arrangement, and density of diamond bodies 132 may be customized, as desired for a given target application or end-use, and in some instances may depend, at least in part, on the particular quantity, arrangement, and density of host feature(s) 130 and the areal footprint of the back side of III-N semiconductor device layer 10 (Figure 6C) to be disposed there over, in accordance with some embodiments. In some embodiments, diamond body(-ies) 132 may be distributed, in part or in whole, as a regular array in which all (or some sub-set) of diamond body(-ies) 132 are arranged in a systematic manner in relation to one another. In some embodiments, diamond body(-ies) 132 may be distributed, in part or in whole, as a semi-regular array in which a sub-set of diamond body(-ies) 132 are arranged in a systematic manner in relation to one another, but at least one other diamond body 132 is not so arranged. In some embodiments, diamond body(-ies) 132 may be distributed, in part or in whole, as an irregular array in which all (or some sub-set) of diamond body(-ies) 132 are not arranged in a systematic manner in relation to one another. In some instances, neighboring diamond bodies 132 may be spaced apart from one another by any of the example distances discussed above, for instance, with respect to feature(s) 130, in accordance with some embodiments. Other suitable materials, formation techniques, configurations, and dimensions for diamond layer 132 will depend on a given application and will be apparent in light of this disclosure.

The process flow may continue as in Figure 6C, which illustrates a cross-sectional view of the IC 200 of Figure 6B after forming a III-N semiconductor device layer 10, in accordance with an embodiment of the present disclosure. As can be seen here, III-N semiconductor device layer 10 (discussed above) may be disposed over a topography provided, in part or in whole, by a given diamond body 132 and semiconductor substrate 102, in accordance with some embodiments. III-N semiconductor device layer 10 may be configured as any of the various III- N semiconductor device layers lOa-lOe discussed above, for instance, with respect to ICs 100a- lOOe of Figures 1-5, in accordance with some embodiments. Other suitable configurations for III-N semiconductor device layer 10 will depend on a given application and will be apparent in light of this disclosure.

As generally can be seen from the portions of Figure 6C enclosed by dashed ellipses, a given portion of an STI layer 112 (discussed above) optionally utilized in forming a III-N semiconductor layer 108 of III-N semiconductor device layer 10 may be formed over a given diamond body 132. In these example configurations, a given diamond body 132 may be physically contacted with or otherwise disposed under STI layer 112 of III-N semiconductor device layer 10, in accordance with some embodiments. It should be noted, however, that the portions of IC 200 in the dashed ellipses of Figure 6C are illustrative of example configurations of III-N semiconductor device layer 10, and the present disclosure is not intended to be limited only to the example configurations shown, as III-N semiconductor device layer 10 may have any of a wide range of configurations, as discussed above, in accordance with some embodiments. As can be seen in Figure 6C (and the views enclosed in dashed ellipses), one or more diamond bodies may be disposed under a back side of III-N semiconductor device layer 10, in accordance with some embodiments.

The process flow may continue as in Figure 6D, which illustrates a cross-sectional view of the IC 200 of Figure 6C after forming a dielectric layer 134, in accordance with an embodiment of the present disclosure. Dielectric layer 134 may be disposed over a topography provided, in part or in whole, by III-N semiconductor device layer 10 and semiconductor substrate 102. Dielectric layer 134 may be comprised of any one, or combination, of a wide range of dielectric materials. For instance, in some embodiments, dielectric layer 134 may be comprised of an oxide, such as silicon oxide (Si0₂), aluminum oxide (A1₂0₃), hafnium oxide (Hf0₂), zirconium oxide (Zr0₂), tantalum oxide (Ta₂0₅), titanium oxide (Ti0₂), lanthanum oxide (La₂0₃), or carbon (C)-doped oxide (CDO), among others. In some embodiments, dielectric layer 134 may be comprised of a nitride, such as silicon mononitride (SiN) or silicon nitride (Si₃N₄), or an oxynitride, such as silicon oxynitride (SiON) or C-doped SiON, a carbide, such as silicon carbide (SiC), or an oxycarbonitride, such as silicon oxycarbonitride (SiOCN), among others. In some embodiments, dielectric layer 134 may be comprised of an organosilicate glass (SiCOH). In some embodiments, dielectric layer 134 may be comprised of an inorganic compound, such as hydrogen silsesquioxane (HSQ).

Dielectric layer 134 may be formed via any suitable standard, custom, or proprietary technique(s), as will be apparent in light of this disclosure. In accordance with some embodiments, dielectric layer 134 may be formed via any one, or combination, of a physical vapor deposition (PVD) process, such as sputter deposition, a spin-on deposition (SOD) process, a chemical vapor deposition (CVD) process, such as plasma-enhanced CVD (PECVD), and an atomic layer deposition (ALD) process, to name a few.

The thickness (e.g., x-thickness in the x-direction; z-thickness in the z-direction) of dielectric layer 134 may be customized, as desired for a given target application or end-use. In some cases, dielectric layer 134 may have a z-thickness, for example, in the range of about 10 nm-1 μπι (e.g., about 10-250 nm, about 250-500 nm, about 500-750 nm, about 750 nm- 1 μηι, or any other sub-range in the range of about 10 nm-1 μιη). Other suitable materials, formation techniques, configurations, and dimensions for dielectric layer 134 will depend on a given application and will be apparent in light of this disclosure.

The process flow may continue as in Figure 6E, which illustrates a cross-sectional view of the IC 200 of Figure 6D after forming a transistor layer 136, in accordance with an embodiment of the present disclosure. Transistor layer 136 may be at least partially disposed within dielectric layer 134, over a topography provided, in part or in whole, by III-N semiconductor device layer 10. In accordance with some embodiments, transistor layer 136 may comprise one or more frontend transistor devices, the particular configuration of which may be customized, as desired for a given target application or end-use. In some cases, transistor layer 136 may be operatively coupled with III-N semiconductor device layer 10. In accordance with some embodiments, transistor layer 136 also may be electrically connected with one or more backend electrically conductive layers (e.g., interconnects), the particular configuration of which may be customized, as desired for a given target application or end-use.

The process flow may continue as in Figure 6F, which illustrates a cross-sectional view of the IC 200 of Figure 6E after partially removing semiconductor substrate 102, in accordance with an embodiment of the present disclosure. Partial removal of material from semiconductor substrate 102 may be provided via a CMP process or any other suitable standard, custom, or proprietary lithography, etch, and clean technique(s), as will be apparent in light of this disclosure. In partially removing semiconductor substrate 102 from IC 200, a given diamond body 132 disposed therein may be exposed for further processing, for example, such as is discussed below with respect to Figures 7-8.

In some cases, the process flow of Figures 6A-6F optionally may continue as in either (or both) of Figures 7-8, which illustrate cross-sectional views of the IC 200 of Figure 6F after forming a metal layer 140, in accordance with some embodiments of the present disclosure. Metal layer 140 may be disposed over a topography provided, in part or in whole, by a given diamond body 132 and semiconductor substrate 102. In some embodiments, metal layer 140 may disposed, in part or in whole, over a surface of semiconductor substrate 102 (e.g., at least partially above a plane of a surface of semiconductor substrate 102), under a back side of III-N semiconductor device layer 10, such as is generally shown in Figure 7. In some other embodiments, metal layer 140 may be disposed, in part or in whole, within a feature 138 formed in semiconductor substrate 102 (e.g., at least partially below a plane of a surface of semiconductor substrate 102), under a back side of III-N semiconductor device layer 10, such as is generally shown in Figure 8. A given feature 138 may be, for example, a trench, through-hole, or other opening or recess that extends through at least a partial thickness (e.g., z-thickness in the z-direction) of semiconductor substrate 102. As will be appreciated in light of this disclosure, partial removal of material from diamond layer 132 and semiconductor substrate 102 in forming a given feature 138 may be provided via any of the example formation techniques discussed above, for instance, with respect to feature(s) 130, in accordance with some embodiments.

Metal layer 140 may be comprised of any of a wide range of suitable thermally conductive metals. For instance, metal layer 140 may be comprised of any one, or combination, of copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), cobalt (Co), silver (Ag), gold (Au), titanium (Ti), tantalum (Ta), or an alloy of any thereof, to name a few. Metal layer 140 may be formed via any suitable standard, custom, or proprietary technique(s), as will be apparent in light of this disclosure. In accordance with some embodiments, metal layer 140 may be formed via any one, or combination, of an electroplating process, an electroless deposition process, an ALD process, a PVD process, and a CVD process, among others.

The dimensions (e.g., x-width in the x-direction; z-thickness in the z-direction) and geometry of metal layer 140 may be customized, as desired for a given target application or end- use. In some cases, metal layer 140 may have a z-thickness in the range of about 50-150 μιη (e.g., about 50-100 μπι, about 100-150 μπι, or any other sub-range in the range of about 50- 150 μιη). In some instances, the x-width of metal layer 140 may substantially coincide with the x-width of III-N semiconductor device layer 10 (e.g., such as generally can be seen in Figures 7- 8). In some instances, the x-width of metal layer 140 may be sufficient to cover (e.g., span across) one or more diamond bodies 132 disposed within semiconductor substrate 102.

As will be further appreciated, the dimensions (e.g., x-width in the x-direction; z-height in the z-direction) and geometry of a given feature 138 may be customized, as desired for a given target application or end-use. In some cases, a given feature 138 may be provided with any of the example dimensions and geometries discussed above, for instance, with respect to metal layer 140, in accordance with some embodiments. Other suitable formation techniques, configurations, and dimensions for metal layer 140 (and a given optional feature 138) will depend on a given application and will be apparent in light of this disclosure.

Figures 9A-9G illustrate a process flow for forming an IC 300 in accordance with another embodiment of the present disclosure. As can be seen from Figure 9G in particular, this process flow may be used, for example, to fabricate an IC 300 including one or more diamond bodies 132 disposed under a back side of a III-N semiconductor device layer 10, in accordance with some embodiments.

The process flow may begin as in Figure 9A, which illustrates a cross-sectional view of an IC 300 configured in accordance with an embodiment of the present disclosure. As can be seen here, IC 300 includes a semiconductor substrate 102 and a III-N semiconductor device layer 10 disposed over a topography provided, in part or in whole, by semiconductor substrate 102. Next, the process flow may continue as in Figure 9B, which illustrates a cross-sectional view of the IC 300 of Figure 9A after forming a dielectric layer 134, in accordance with an embodiment of the present disclosure. Dielectric layer 134 may be disposed over a topography provided, in part or in whole, by III-N semiconductor device layer 10 and semiconductor substrate 102. Thereafter, the process flow may continue as in Figure 9C, which illustrates a cross-sectional view of the IC 300 of Figure 9B after forming a transistor layer 136, in accordance with an embodiment of the present disclosure. Transistor layer 136 may be disposed, in part or in whole, within dielectric layer 134, over III-N semiconductor device layer 10. As will be appreciated in light of this disclosure, the description provided above for each of semiconductor substrate 102, III-N semiconductor device layer 10, dielectric layer 134, and transistor layer 136 may apply equally here in the context of the process flow of Figures 9A-9G, in accordance with some embodiments.

The process flow may continue as in Figure 9D, which illustrates a cross-sectional view of the IC 300 of Figure 9C after bonding with a carrier substrate 142, in accordance with an embodiment of the present disclosure. Carrier substrate 142 (e.g., a carrier wafer) may be comprised of any one, or combination, of suitable carrier substrate materials, such as Si or a glass, to name a few. Bonding of carrier substrate 142 may be provided via any suitable standard, custom, or proprietary bonding technique(s), as will be apparent in light of this disclosure.

The process flow may continue as in Figure 9E, which illustrates a cross-sectional view of the IC 300 of Figure 9D after removing semiconductor substrate 102, in accordance with an embodiment of the present disclosure. Removal of semiconductor substrate 102 from IC 300 may be provided via any suitable standard, custom, or proprietary backgrinding or etch-and- clean technique(s), as will be apparent in light of this disclosure. In removing semiconductor substrate 102 from IC 300, III-N semiconductor device layer 10, dielectric layer 134, and transistor layer 136 may remain behind, bonded with carrier substrate 142, in accordance with some embodiments.

The process flow may continue as in Figure 9F, which illustrates a cross-sectional view of the IC 300 of Figure 9E after bonding with a semiconductor substrate 144, in accordance with an embodiment of the present disclosure. As can be seen here, semiconductor substrate 144 may have a diamond layer 132 (e.g., comprising one or more constituent diamond bodies 132) and a dielectric layer 146 disposed therein, in accordance with some embodiments. As will be appreciated in light of this disclosure, semiconductor substrate 144 may be provided with any of the example materials and configurations discussed above, for instance, with respect to semiconductor substrate 102, in accordance with some embodiments. As will be further appreciated, the description provided above for diamond layer 132 may apply equally here in the context of the process flow of Figures 9A-9G, in accordance with some embodiments. As will be still further appreciated, dielectric layer 146 may be provided with any of the example materials, formation techniques, configurations, and dimensions discussed above, for instance, with respect to dielectric layer 134, in accordance with some embodiments. Bonding between semiconductor substrate 144 (with its attendant diamond layer 132 and dielectric layer 146) and dielectric layer 134 and III-N semiconductor device layer 10 may be provided via an oxide-oxide bonding process or any other suitable standard, custom, or proprietary bonding technique(s), as will be apparent in light of this disclosure. As generally can be seen from the portion of Figure 9F enclosed by the dashed ellipse, a given portion of an STI layer 112 optionally utilized in forming III-N semiconductor layer 108 of a III-N semiconductor device layer 10 may be bonded with a given portion of dielectric layer 148 of semiconductor substrate 144, in accordance with some embodiments. In this example configuration, a given diamond body 132 may be physically contacted with or otherwise disposed under III-N semiconductor layer 108 of III-N semiconductor device layer 10, in accordance with some embodiments. It should be noted, however, that the portions of IC 300 in the dashed ellipse of Figure 9F are illustrative of an example configuration of III-N semiconductor device layer 10, and the present disclosure is not intended to be limited only to the example configuration shown, as III-N semiconductor device layer 10 may have any of a wide range of configurations, as discussed above, in accordance with some embodiments.

The process flow may continue as in Figure 9G, which illustrates a cross-sectional view of the IC 300 of Figure 9F after removing carrier substrate 142, in accordance with an embodiment of the present disclosure. Carrier substrate 142 may be removed from IC 300 via any suitable standard, custom, or proprietary backgrinding or etch-and-clean technique(s), as will be apparent in light of this disclosure. In removing carrier substrate 142, III-N semiconductor device layer 10, dielectric layer 134, and transistor layer 136 may remain behind, bonded with semiconductor substrate 144, diamond layer 132, and dielectric layer 146.

Figures 10A-10D illustrate a process flow for forming an IC 400 in accordance with another embodiment of the present disclosure. As can be seen from Figure 10D in particular, this process flow may be used, for example, to fabricate an IC 400 including one or more diamond layers 132 disposed over a front side of a III-N semiconductor device layer 10, in accordance with some embodiments.

The process flow may begin as in Figure 10A, which illustrates a cross-sectional view of an IC 400 configured in accordance with an embodiment of the present disclosure. As can be seen here, IC 400 includes a semiconductor substrate 102 and a III-N semiconductor device layer 10 disposed over a topography provided, in part or in whole, by semiconductor substrate 102. In addition, IC 400 includes a dielectric layer 134 disposed over III-N semiconductor device layer 10 and semiconductor substrate 102, as well as a transistor layer 136 disposed, in part or in whole, within dielectric layer 134, over III-N semiconductor device layer 10. As will be appreciated in light of this disclosure, the description provided above for each of semiconductor substrate 102, III-N semiconductor device layer 10, dielectric layer 134, and transistor layer 136 may apply equally here in the context of the process flow of Figures 10A-10D, in accordance with some embodiments.

The process flow may continue as in Figure 10B, which illustrates a cross-sectional view of the IC 400 of Figure 10A after partially removing dielectric layer 134, in accordance with an embodiment of the present disclosure. Partial removal of material from dielectric layer 134 may be provided via any suitable standard, custom, or proprietary lithography, etch, and clean technique(s), as will be apparent in light of this disclosure. In accordance with some embodiments, in partially removing dielectric layer 134, the thickness (e.g., the x-thickness in the x-direction) of dielectric layer 134 alongside sidewalls of III-N semiconductor device layer 10 may be reduced, exposing the surface of underlying semiconductor substrate 102.

The process flow may continue as in Figure IOC, which illustrates a cross-sectional view of the IC 400 of Figure 10B after forming a diamond layer 132, in accordance with an embodiment of the present disclosure. Diamond layer 132 may be disposed over a topography provided, in part or in whole, by transistor layer 136, dielectric layer 134, and semiconductor substrate 102. As will be appreciated in light of this disclosure, the description provided above for diamond layer 132 may apply equally here in the context of the process flow of Figures 10A- 10D, in accordance with some embodiments. In some embodiments, diamond layer 132 may be configured as a single-layer structure, whereas in some other embodiments, diamond layer 132 may be configured as a bi-layer, tri-layer, or other multi-layer structure.

The dimensions (e.g., x-thickness in the x-direction; z-thickness in the z-direction) of diamond layer 132 (in total or of a given constituent layer thereof) may be customized, as desired for a given target application or end-use. In some cases, diamond layer 132 may have at least one of an x-thickness and a z-thickness in the range of about 1-100 μπι (e.g., about 1-25 μπι, about 25-50 μπι, about 50-75 μπι, about 75-100 μπι, or any other sub-range in the range of about 1-100 μπι). In some instances, diamond layer 132 may have at least one of an x-thickness and a z-thickness in the range of about 5-10 μπι. Other suitable configurations and dimensions for diamond layer 132 will depend on a given application and will be apparent in light of this disclosure.

The process flow may continue as in Figure 10D, which illustrates a cross-sectional view of the IC 400 of Figure IOC after forming a cavity 150 in semiconductor substrate 102, in accordance with an embodiment of the present disclosure. Cavity 150 may be formed in a back side of semiconductor substrate 102, under a back side of III-N semiconductor device layer 10 (e.g., such that III-N semiconductor device layer 10 is vertically adjacent to cavity 150), in accordance with some embodiments. To that end, cavity 150 may be formed via any suitable standard, custom, or proprietary lithography, etch, and clean technique(s), as will be apparent in light of this disclosure. In accordance with some embodiments, cavity 150 may be formed via any one, or combination, of a dry etch process and a wet etch process, the etch chemistry of which may be customized, as desired for a given target application or end-use. In a more general sense, in forming cavity 150, semiconductor substrate 102 may be undercut or otherwise thinned, in accordance with some embodiments. In accordance with some embodiments, cavity 150 may remain empty (e.g., as an air gap unfilled with any material), whereas in some other embodiments, cavity 150 may be filled, in part or in whole, with one or more process materials (e.g., A1N).

The dimensions (e.g., z-depth in the z-direction; x-width in the x-direction) and geometry of cavity 150 may be customized, as desired for a given target application or end-use. In some cases, cavity 150 may have a z-depth in the range of about 200-550 μπι (e.g., about 200- 375 μπι, about 375-550 μπι, or any other sub-range in the range of about 200-550 μπι). In some cases, the x-width of cavity 150 may be made to substantially coincide with the x-width of any one or combination of III-N semiconductor device layer 10, dielectric layer 134, and diamond layer 132 (e.g., such as generally can be seen in Figure 9D). In some instances, cavity 150 may have a geometry (top-down; side) that is generally polygonal in shape (e.g., rectangular, square, pentagonal, hexagonal, and so forth). In some instances, cavity 150 may have a geometry (top- down; side) that is generally curvilinear in shape (e.g., circular, elliptical, arcuate, parabolic, and so forth). In some embodiments, cavity 150 may be generally prismatic in shape (e.g., quadrangular prismatic, pentagonal prismatic, hexagonal prismatic, and so forth). In some embodiments, cavity 150 may be generally cylindrical in shape (e.g., circular cylindrical, elliptical cylindrical, and so forth). In some cases, cavity 150 may have substantially vertical sidewalls (e.g., within about 2° of being vertically straight). In some cases, cavity 150 may have tapered sidewalls (e.g., outside of about 2° of being vertically straight).

In forming cavity 150, a portion 102a of semiconductor substrate 102 may remain intact under a back side of III-N semiconductor device layer 10, in accordance with some embodiments. In some instances, portion 102a may serve to provide mechanical support for III- N semiconductor device layer 10. The thickness (e.g., z-thickness in the z-direction) of portion 102a may be customized, as desired for a given target application or end-use. In some cases, portion 102a may have a z-thickness in the range of about 5-50 μπι (e.g., about 5-25 μπι, about 25-50 μπι, or any other sub-range in the range of about 5-50 μπι). The amount of portion 102a present in IC 400 may be tuned by varying the particular dimensions and geometry of cavity 150, in accordance with some embodiments. Other suitable formation techniques, configurations, and dimensions for cavity 150 and portion 102a of semiconductor substrate 102 will depend on a given application and will be apparent in light of this disclosure.

Figures 11A-11H illustrate a process flow for forming an IC 500 in accordance with another embodiment of the present disclosure. As can be seen from Figure 11H in particular, this process flow may be used, for example, to fabricate an IC 500 including one or more diamond layers 132 disposed over a front side of a III-N semiconductor device layer 10, in accordance with some embodiments. Furthermore, this process flow may be used, in accordance with some embodiments, in layer transferring a III-N semiconductor device layer 10 with a front- side diamond layer 132 to a CMOS semiconductor substrate 154, such that the back side of the III-N semiconductor device layer 10 is at the top of an interconnect stack, proximate a bump connection layer and exposed to air for heat conduction.

The process flow may begin as in Figure 11 A, which illustrates a cross-sectional view of an IC 500 configured in accordance with an embodiment of the present disclosure. As can be seen here, IC 500 includes a semiconductor substrate 102 and a III-N semiconductor device layer 10 disposed over a topography provided, in part or in whole, by semiconductor substrate 102. In addition, IC 500 includes a dielectric layer 134 disposed over III-N semiconductor device layer 10 and semiconductor substrate 102, as well as a transistor layer 136 disposed, in part or in whole, within dielectric layer 134, over III-N semiconductor device layer 10. Furthermore, IC 500 includes a diamond layer 132 disposed over transistor layer 136, dielectric layer 134, and semiconductor substrate 102. As will be appreciated in light of this disclosure, the description provided above for each of semiconductor substrate 102, III-N semiconductor device layer 10, diamond layer 132, dielectric layer 134, and transistor layer 136 may apply equally here in the context of the process flow of Figures 11 A-l 1H, in accordance with some embodiments.

The process flow may continue as in Figure 1 IB, which illustrates a cross-sectional view of the IC 500 of Figure 11A after forming a dielectric layer 152, in accordance with an embodiment of the present disclosure. Dielectric layer 152 may be disposed over a topography provided, in part or in whole, by diamond layer 132 and semiconductor substrate 102. As will be appreciated in light of this disclosure, dielectric layer 152 may be provided with any of the example materials, formation techniques, configurations, and dimensions discussed above, for instance, with respect to dielectric layer 134, in accordance with some embodiments.

The process flow may continue as in Figure 11C, which illustrates a cross-sectional view of the IC 500 of Figure 11B after bonding with a semiconductor substrate 154 including a dielectric layer 156, in accordance with an embodiment of the present disclosure. Bonding between dielectric layer 156 (with its attendant semiconductor substrate 154) and dielectric layer 152 may be provided via an oxide-oxide bonding process or any other suitable standard, custom, or proprietary bonding technique(s), as will be apparent in light of this disclosure. As will be appreciated in light of this disclosure, semiconductor substrate 154 may be provided with any of the example materials and configurations discussed above, for instance, with respect to semiconductor substrate 102, in accordance with some embodiments. In some cases, semiconductor substrate 154 may be configured as a Si-based complementary metal -oxide- semi conductor (CMOS) device layer. As will be further appreciated, dielectric layer 156 may be provided with any of the example materials, formation techniques, dimensions, and configurations discussed above, for instance, with respect to dielectric layer 134, in accordance with some embodiments. In some cases, dielectric layer 156 and dielectric layer 134 may differ in material composition, whereas in other cases, they may be of the same material composition.

The process flow may continue as in Figure 1 ID, which illustrates a cross-sectional view of the IC 500 of Figure 11C after removing semiconductor substrate 102, in accordance with an embodiment of the present disclosure. Removal of semiconductor substrate 102 from IC 500 may be provided via any suitable standard, custom, or proprietary backgrinding or etch-and- clean technique(s), as will be apparent in light of this disclosure. In removing semiconductor substrate 102 from IC 500, III-N semiconductor device layer 10, diamond layer 132, dielectric layer 134, transistor layer 136, and dielectric layer 152 may remain behind, bonded with dielectric layer 156 over semiconductor substrate 154, in accordance with some embodiments.

The process flow may continue as in Figure 1 IE, which illustrates a cross-sectional view of the IC 500 of Figure 11D after forming a dielectric layer 158, in accordance with an embodiment of the present disclosure. Dielectric layer 158 may be disposed over a topography provided, in part or in whole, by III-N semiconductor device layer 10, dielectric layer 134, diamond layer 132, and dielectric layer 152. As will be appreciated in light of this disclosure, dielectric layer 158 may be provided with any of the example materials, formation techniques, and configurations discussed above, for instance, with respect to dielectric layer 134, in accordance with some embodiments. In some cases, dielectric layer 158 and dielectric layer 152 may differ in material composition, whereas in other cases, they may be of the same material composition. The thickness (e.g., z-thickness in the z-direction) of dielectric layer 158 may be customized, as desired for a given target application or end-use. In some cases, dielectric layer 158 may have a z-thickness in the range of about 0.1-3 μπι (e.g., about 0.1-1.5 μπι, about 1.5- 3 μπι, or any other sub-range in the range of about 0.1-3 μπι).

The process flow may continue as in Figure 1 IF, which illustrates a cross-sectional view of the IC 500 of Figure 1 IE after patterning thereof with one or more features 160, in accordance with an embodiment of the present disclosure. A given feature 160 may be, for example, a trench, through-hole, or other opening or recess that extends through at least a partial thickness (e.g., z-thickness in the z-direction) of at least one of dielectric layer 158, dielectric layer 152, and dielectric layer 156. In some cases, a given feature 160 may extend through a full thickness (e.g., z-thickness in the z-direction) of dielectric layer 158 so as to expose an underlying surface of III-N semiconductor device layer 10. In some cases, a given feature 160 may extend through a full thickness (e.g., z-thickness in the z-direction) of dielectric layer 156 so as to expose an underlying surface of semiconductor substrate 154. As will be appreciated in light of this disclosure, a given feature 160 may be provided with any of the example formation techniques, configurations, dimensions, geometries, and arrangements discussed above, for instance, with respect to feature(s) 134, in accordance with some embodiments.

The process flow may continue as in Figure 11G, which illustrates a cross-sectional view of the IC 500 of Figure 1 IF after forming an electrically conductive layer 162, in accordance with an embodiment of the present disclosure. As can be seen here, in forming electrically conductive layer 162, a given feature 160 of IC 500 may be filled, in part or in whole, with electrically conductive material. In accordance with some embodiments, electrically conductive layer 162 may comprise one or more electrically conductive through-body vias (TBVs). In some cases, at least a portion of electrically conductive layer 162 may extend through dielectric layer 158 to an exposed surface of III-N semiconductor device layer 10. In some cases, at least a portion of electrically conductive layer 162 may extend through dielectric layer 158, dielectric layer 152, and dielectric layer 156 to an exposed surface of semiconductor substrate 154. As will be appreciated in light of this disclosure, electrically conductive layer 162 may be provided with any of the example materials and formation techniques discussed above, for instance, with respect to metal layer 140 and electrically conductive feature 120, in accordance with some embodiments. As will be further appreciated, electrically conductive layer 162 may be provided with any of the example configurations, dimensions, geometries, and arrangements discussed above, for instance, with respect to feature(s) 134, in accordance with some embodiments.

The process flow may continue as in Figure 11H, which illustrates a cross-sectional view of the IC 500 of Figure 11G after forming a dielectric layer 164 and an electrically conductive layer 166, in accordance with an embodiment of the present disclosure. Dielectric layer 164 may be disposed over a topography provided, in part or in whole, by dielectric layer 158 and electrically conductive layer 162. As will be appreciated in light of this disclosure, dielectric layer 164 may be provided with any of the example materials, formation techniques, and configurations discussed above, for instance, with respect to dielectric layer 134, in accordance with some embodiments. In some cases, dielectric layer 164 and dielectric layer 158 may differ in material composition, whereas in other cases, they may be of the same material composition. The thickness (e.g., z-thickness in the z-direction) of dielectric layer 164 may be customized, as desired for a given target application or end-use. In some cases, dielectric layer 164 may have a z-thickness in the range of about 0.1-3 μιη (e.g., about 0.1-1.5 μπι, about 1.5-3 μπι, or any other sub-range in the range of about 0.1-3 μιη).

Electrically conductive layer 166 may be disposed over a topography provided, in part or in whole, by dielectric layer 164. As will be further appreciated in light of this disclosure, electrically conductive layer 166 may be provided with any of the example materials and formation techniques discussed above, for instance, with respect to metal layer 140 and electrically conductive feature 120, in accordance with some embodiments. In some cases, electrically conductive layer 166 may comprise one or more electrically conductive bumps.

As discussed herein, the various constituent layers of ICs 100, 200, 300, 400, and 500 may have any of a wide range of thicknesses (e.g., z-thicknesses in the z-direction, x-thicknesses in the x-direction, or other designated thickness), as desired for a given target application or end- use. In some instances, a given layer may be provided as a monolayer over an underlying topography. For a given IC configured as described herein, in some cases, a given constituent layer thereof may have a substantially uniform thickness over an underlying topography. In some instances, a given constituent layer may be provided as a substantially conformal layer over an underlying topography. In other instances, a given constituent layer may be provided with a non-uniform or otherwise varying thickness over an underlying topography. For example, in some cases, a first portion of a given layer may have a thickness within a first range, whereas a second portion thereof may have a thickness within a second, different range. In some instances, a given layer may have first and second portions having average thicknesses that are different from one another by about 20% or less, about 15% or less, about 10% or less, or about 5%) or less. Numerous configurations and variations will be apparent in light of this disclosure.

Furthermore, as discussed herein, the various constituent layers of ICs 100, 200, 300, 400, and 500 may be disposed over one or more other constituent layers. In some cases, a first constituent layer may be disposed directly on a second constituent layer with no layers intervening. In some other cases, one or more intervening layers may be disposed between a first constituent layer and a second constituent layer underlying. In a more general sense, a given constituent layer may be disposed superjacent to another given constituent layer, optionally with one or more intervening layers, in accordance with some embodiments.

Example System

Figure 12 illustrates a computing system 1000 implemented with integrated circuit structures or devices formed using the disclosed techniques in accordance with an example embodiment. As can be seen, the computing system 1000 houses a motherboard 1002. The motherboard 1002 may include a number of components, including, but not limited to, a processor 1004 and at least one communication chip 1006, each of which can be physically and electrically coupled to the motherboard 1002, or otherwise integrated therein. As will be appreciated, the motherboard 1002 may be, for example, any printed circuit board, whether a main board, a daughterboard mounted on a main board, or the only board of system 1000, etc. Depending on its applications, computing system 1000 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 1002. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). Any of the components included in computing system 1000 may include one or more integrated circuit structures or devices formed using the disclosed techniques in accordance with an example embodiment. In some embodiments, multiple functions can be integrated into one or more chips (e.g., for instance, note that the communication chip 1006 can be part of or otherwise integrated into the processor 1004).

The communication chip 1006 enables wireless communications for the transfer of data to and from the computing system 1000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 1006 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing system 1000 may include a plurality of communication chips 1006. For instance, a first communication chip 1006 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1006 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 1004 of the computing system 1000 includes an integrated circuit die packaged within the processor 1004. In some embodiments, the integrated circuit die of the processor includes onboard circuitry that is implemented with one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein. The term "processor" may refer to any device or portion of a device that processes, for instance, electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 1006 also may include an integrated circuit die packaged within the communication chip 1006. In accordance with some such example embodiments, the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices formed using the disclosed techniques as described herein. As will be appreciated in light of this disclosure, note that multi -standard wireless capability may be integrated directly into the processor 1004 (e.g., where functionality of any chips 1006 is integrated into processor 1004, rather than having separate communication chips). Further note that processor 1004 may be a chip set having such wireless capability. In short, any number of processor 1004 and/or communication chips 1006 can be used. Likewise, any one chip or chip set can have multiple functions integrated therein.

In various implementations, the computing device 1000 may be a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device that processes data or employs one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein.

Further Example Embodiments

The following examples pertain to further embodiments, from which numerous permutations and configurations will be apparent.

Example 1 is an integrated circuit including: a semiconductor layer; a transistor device disposed on the semiconductor layer and including a III-N semiconductor layer, wherein the transistor device has a first side proximate the semiconductor layer and a second side opposite the first side; and a diamond layer disposed on at least one of the first side and the second side of the transistor device.

Example 2 includes the subject matter of any of Examples 1 and 3-17, wherein: the semiconductor layer includes at least one through-hole disposed therein on the first side of the transistor device; and the diamond layer includes at least one diamond body disposed within the at least one through-hole and in physical contact with the transistor device. Example 3 includes the subject matter of any of Examples 1-2 and 4-17, wherein: the transistor device further includes a shallow trench isolation (STI) layer patterned with at least one feature; and the III-N semiconductor layer of the transistor device is at least partially disposed within the at least one feature.

Example 4 includes the subject matter of Example 3, wherein the diamond layer is in physical contact with the STI layer of the transistor device.

Example 5 includes the subject matter of Example 3, wherein the diamond layer is in physical contact with the III-N semiconductor layer of the transistor device.

Example 6 includes the subject matter of any of Examples 1-5 and 7-17 and further includes a metal layer disposed on the first side of the transistor device, wherein the metal layer is in physical contact with the diamond layer.

Example 7 includes the subject matter of Example 6, wherein the metal layer is disposed at least partially within the semiconductor substrate.

Example 8 includes the subject matter of any of Examples 1-7 and 9-17 and further includes a dielectric layer disposed on the second side of the transistor device, wherein the diamond layer is in physical contact with at least a portion of the dielectric layer.

Example 9 includes the subject matter of any of Examples 1-8 and 10-17, wherein the semiconductor substrate includes a cavity formed therein on the first side of the transistor device.

Example 10 includes the subject matter of Example 9, wherein a portion of the semiconductor substrate disposed between the cavity and the transistor device has a z-thickness in the range of about 5-50 μπι.

Example 11 includes the subject matter of any of Examples 1-10 and 12-17 and further includes: a dielectric layer disposed on the first side of the transistor device; and an electrically conductive bump layer disposed on the dielectric layer.

Example 12 includes the subject matter of any of Examples 1-11 and 13-17, wherein the transistor device further includes: a polarization layer disposed on the III-N semiconductor layer; a source portion disposed on the polarization layer; a drain portion disposed on the polarization layer; and a gate portion disposed on the polarization layer, between the source portion and the drain portion.

Example 13 includes the subject matter of any of Examples 1-12 and 16-17, wherein the semiconductor layer includes silicon (Si) having a crystallographic orientation of (111).

Example 14 includes the subject matter of any of Examples 1-12 and 16-17, wherein the semiconductor layer includes silicon (Si) having a crystallographic orientation of (110). Example 15 includes the subject matter of any of Examples 1-12 and 16-17, wherein the semiconductor layer includes silicon (Si) having a crystallographic orientation of (100) with an offcut toward (111) in the range of about 1-10°.

Example 16 includes the subject matter of any of Examples 1-15 and 17, wherein the semiconductor layer includes a silicon (Si) complementary metal-oxide-semiconductor (CMOS) layer.

Example 17 includes the subject matter of any of Examples 1-16, wherein the transistor device includes a power amplifier.

Example 18 is a method of fabricating an integrated circuit, the method including: forming a transistor device on a semiconductor layer, the transistor device including a III-N semiconductor layer, wherein the transistor device has a first side proximate the semiconductor layer and a second side opposite the first side; and forming a diamond layer on at least one of the first side and the second side of the transistor device.

Example 19 includes the subject matter of any of Examples 18 and 20-34 and further includes: forming at least one through-hole in the semiconductor layer on the first side of the transistor device, wherein the diamond layer includes at least one diamond body disposed within the at least one through-hole and in physical contact with the transistor device.

Example 20 includes the subject matter of any of Examples 18-19 and 21-34, wherein: the transistor device further includes a shallow trench isolation (STI) layer patterned with at least one feature; and the III-N semiconductor layer of the transistor device is at least partially disposed within the at least one feature.

Example 21 includes the subject matter of Example 20, wherein the diamond layer is in physical contact with the STI layer of the transistor device.

Example 22 includes the subject matter of Example 20, wherein the diamond layer is in physical contact with the III-N semiconductor layer of the transistor device.

Example 23 includes the subject matter of any of Examples 18-22 and 24-34 and further includes: forming a metal layer on the first side of the transistor device, wherein the metal layer is in physical contact with the diamond layer.

Example 24 includes the subject matter of Example 23, wherein the metal layer is disposed at least partially within the semiconductor substrate.

Example 25 includes the subject matter of any of Examples 18-24 and 26-34 and further includes: forming a dielectric layer on the second side of the transistor device, wherein the diamond layer is in physical contact with at least a portion of the dielectric layer. Example 26 includes the subject matter of any of Examples 18-25 and 27-34 and further includes: forming a cavity within the semiconductor substrate on the first side of the transistor device.

Example 27 includes the subject matter of Example 26, wherein a portion of the semiconductor substrate disposed between the cavity and the transistor device has a z-thickness in the range of about 5-50 μπι.

Example 28 includes the subject matter of any of Examples 18-27 and 29-34 and further includes: forming a dielectric layer on the first side of the transistor device; and forming an electrically conductive bump layer on the dielectric layer.

Example 29 includes the subject matter of any of Examples 18-28 and 30-34, wherein the transistor device further includes: a polarization layer disposed on the III-N semiconductor layer; a source portion disposed on the polarization layer; a drain portion disposed on the polarization layer; and a gate portion disposed on the polarization layer, between the source portion and the drain portion.

Example 30 includes the subject matter of any of Examples 18-29 and 33-34, wherein the semiconductor layer includes silicon (Si) having a crystallographic orientation of (111).

Example 31 includes the subject matter of any of Examples 18-29 and 33-34, wherein the semiconductor layer includes silicon (Si) having a crystallographic orientation of (110).

Example 32 includes the subject matter of any of Examples 18-29 and 33-34, wherein the semiconductor layer includes silicon (Si) having a crystallographic orientation of (100) with an offcut toward (111) in the range of about 1-10°.

Example 33 includes the subject matter of any of Examples 18-32 and 34, wherein the semiconductor layer includes a silicon (Si) complementary metal-oxide-semiconductor (CMOS) layer.

Example 34 includes the subject matter of any of Examples 18-33, wherein the transistor device includes a power amplifier.

Example 35 is an integrated circuit including: a silicon (Si) substrate; a first transistor device disposed over the Si substrate and including: a gallium nitride (GaN) layer disposed over the Si substrate; a polarization layer disposed over the GaN layer; at least one of a source portion and a drain portion disposed over the polarization layer; and a gate portion disposed over the

GaN layer; and a diamond layer in physical contact with at least one of the GaN layer, the source portion, the drain portion, and the gate portion.

Example 36 includes the subject matter of any of Examples 35 and 37-42, wherein the diamond layer is: at least partially disposed within the Si substrate; and in physical contact with the GaN layer. Example 37 includes the subject matter of any of Examples 35-36 and 38-42 and further includes a shallow trench isolation (STI) layer patterned with at least one feature, wherein the GaN layer is at least partially disposed within the at least one feature.

Example 38 includes the subject matter of Example 37, wherein the diamond layer is in physical contact with the STI layer.

Example 39 includes the subject matter of any of Examples 35-38 and 40-42, wherein the Si substrate includes a cavity formed therein vertically adjacent the GaN layer.

Example 40 includes the subject matter of any of Examples 35-39 and 41-42 and further includes a metal layer disposed either on or within the Si substrate and in physical contact with the diamond layer.

Example 41 includes the subject matter of any of Examples 35-40 and 42, wherein the Si substrate includes a Si complementary metal -oxide-semiconductor (CMOS) layer.

Example 42 includes the subject matter of any of Examples 35-41 and further includes a second transistor device operatively coupled with the first transistor device.

The foregoing description of example embodiments has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. Many modifications and variations are possible in light of this disclosure. It is intended that the scope of the present disclosure be limited not by this detailed description, but rather by the claims appended hereto. Future-filed applications claiming priority to this application may claim the disclosed subject matter in a different manner and generally may include any set of one or more limitations as variously disclosed or otherwise demonstrated herein.

Claims

CLAIMS What is claimed is:

1. An integrated circuit comprising:

a semiconductor layer;

a transistor device disposed on the semiconductor layer and comprising a III-N semiconductor layer, wherein the transistor device has a first side proximate the semiconductor layer and a second side opposite the first side; and a diamond layer disposed on at least one of the first side and the second side of the transistor device.

2. The integrated circuit of claim 1, wherein:

the semiconductor layer includes at least one through-hole disposed therein on the first side of the transistor device; and

the diamond layer comprises at least one diamond body disposed within the at least one through-hole and in physical contact with the transistor device.

3. The integrated circuit of claim 1, wherein:

the transistor device further comprises a shallow trench isolation (STI) layer patterned with at least one feature; and

the III-N semiconductor layer of the transistor device is at least partially disposed within the at least one feature.

4. The integrated circuit of claim 3, wherein the diamond layer is in physical contact with the STI layer of the transistor device.

5. The integrated circuit of claim 3, wherein the diamond layer is in physical contact with the III-N semiconductor layer of the transistor device.

6. The integrated circuit of claim 1 further comprising a metal layer disposed on the first side of the transistor device, wherein the metal layer is in physical contact with the diamond layer.

7. The integrated circuit of claim 6, wherein the metal layer is disposed at least partially within the semiconductor substrate.

8. The integrated circuit of claim 1 further comprising a dielectric layer disposed on the second side of the transistor device, wherein the diamond layer is in physical contact with at least a portion of the dielectric layer.

9. The integrated circuit of claim 1, wherein:

the semiconductor substrate includes a cavity formed therein on the first side of the transistor device; and

a portion of the semiconductor substrate disposed between the cavity and the transistor device has a z-thickness in the range of about 5-50 μπι.

10. The integrated circuit of claim 1, wherein the transistor device further comprises: a polarization layer disposed on the III-N semiconductor layer;

a source portion disposed on the polarization layer;

a drain portion disposed on the polarization layer; and

a gate portion disposed on the polarization layer, between the source portion and the drain portion.

11. The integrated circuit of any of claims 1-10, wherein the semiconductor layer comprises a silicon (Si) complementary metal -oxide-semiconductor (CMOS) layer.

12. The integrated circuit of any of claims 1-10, wherein the transistor device comprises a power amplifier.

13. A method of fabricating an integrated circuit, the method comprising:

forming a transistor device on a semiconductor layer, the transistor device comprising a III-N semiconductor layer, wherein the transistor device has a first side proximate the semiconductor layer and a second side opposite the first side; and forming a diamond layer on at least one of the first side and the second side of the transistor device.

14. The method of claim 13 further comprising: forming at least one through-hole in the semiconductor layer on the first side of the transistor device, wherein the diamond layer comprises at least one diamond body disposed within the at least one through-hole and in physical contact with the transistor device.

15. The method of claim 13, wherein:

16. The method of claim 15, wherein the diamond layer is in physical contact with the STI layer of the transistor device.

17. The method of claim 15, wherein the diamond layer is in physical contact with the III-N semiconductor layer of the transistor device.

18. The method of claim 13 further comprising:

forming a metal layer on the first side of the transistor device, wherein the metal layer is in physical contact with the diamond layer.

19. The method of claim 13 further comprising:

forming a dielectric layer on the second side of the transistor device, wherein the diamond layer is in physical contact with at least a portion of the dielectric layer.

20. The method of claim 13 further comprising:

forming a cavity within the semiconductor substrate on the first side of the transistor device, wherein a portion of the semiconductor substrate disposed between the cavity and the transistor device has a z-thickness in the range of about 5-50 μπι.

21. The method of claim 13, wherein the transistor device further comprises:

a polarization layer disposed on the III-N semiconductor layer;

a source portion disposed on the polarization layer;

a drain portion disposed on the polarization layer; and a gate portion disposed on the polarization layer, between the source portion and the drain portion.

22. The method of any of claims 13-21, wherein the transistor device comprises a power amplifier.

23. An integrated circuit comprising:

a silicon (Si) substrate;

a first transistor device disposed over the Si substrate and comprising:

a gallium nitride (GaN) layer disposed over the Si substrate;

a polarization layer disposed over the GaN layer;

at least one of a source portion and a drain portion disposed over the polarization layer; and

a gate portion disposed over the GaN layer; and

a diamond layer in physical contact with at least one of the GaN layer, the source portion, the drain portion, and the gate portion.

24. The integrated circuit of claim 23, wherein the diamond layer is:

at least partially disposed within the Si substrate; and

in physical contact with the GaN layer.

25. The integrated circuit of claim 23 further comprising a shallow trench isolation (STI) layer patterned with at least one feature, wherein:

the GaN layer is at least partially disposed within the at least one feature; and

the diamond layer is in physical contact with the STI layer.