WO2018000924A1 - 传输帧的方法和装置 - Google Patents

传输帧的方法和装置 Download PDF

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Publication number
WO2018000924A1
WO2018000924A1 PCT/CN2017/082064 CN2017082064W WO2018000924A1 WO 2018000924 A1 WO2018000924 A1 WO 2018000924A1 CN 2017082064 W CN2017082064 W CN 2017082064W WO 2018000924 A1 WO2018000924 A1 WO 2018000924A1
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Prior art keywords
sequence
bits
modulation
padding
coding
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PCT/CN2017/082064
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English (en)
French (fr)
Inventor
吴涛
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华为技术有限公司
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Priority to EP17818921.3A priority Critical patent/EP3462651B1/en
Publication of WO2018000924A1 publication Critical patent/WO2018000924A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H03M13/6356—Error control coding in combination with rate matching by repetition or insertion of dummy data, i.e. rate reduction
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0072—Error control for data other than payload data, e.g. control data
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes

Definitions

  • the present application relates to the field of communications and, more particularly, to a method and apparatus for transmitting frames.
  • Wireless Fidelity is a wireless network communication technology brand that is held by the Wi-Fi Alliance to improve interoperability between 802.11-based wireless network products using the 802.11 family of protocols.
  • the wireless LAN can be called a Wi-Fi network.
  • 802.11ad is a branch of the Institute of Electrical and Electronics Engineers (IEEE) 802.11 (or WLAN, WLAN) system that operates in the 60 GHz high band.
  • IEEE Institute of Electrical and Electronics Engineers
  • Single carrier modulation is a type of 802.11ad technology.
  • the 802.11ad single-carrier based header (Header) is designed to transmit a 64-bit Header sequence.
  • the frame structure determined in the standard discussion of 802.11ay adds an enhanced directional multi-gigabit header (EDMG Header) field to 802.11ad for indicating control signaling in 802.11ay.
  • EDMG Header enhanced directional multi-gigabit header
  • the existing EDMG Header design scheme divides the bits in the EDMG Header sequence into multiple 64-bit sequences in order to follow the design in 802.11ad, and uses the design of the Header in 802.11ad to transmit the frame, but this method
  • the coded modulation transmission is performed in units of 64 bits each, and the transmission performance is limited, especially under long-distance transmission conditions, and the performance requirements of the transmission cannot be satisfied.
  • the present application provides a method and apparatus for transmitting a frame, which can improve the transmission performance of a frame.
  • a method for transmitting a frame comprising: acquiring an initial enhanced directional multi-gigabit frame header EDMG Header sequence, wherein the EDMG Header sequence includes N control bits, and N is a positive integer; The initial EDMG Header sequence performs a padding operation to obtain a padding sequence, where the padding sequence includes N information bits and L padding bits, and the N information bits are the N control bits or the N information bits Obtaining the N control bits by performing scrambling on the N control bits; performing 1/2 Low Density Parity Check Code (LDPC) encoding on the padding sequence to obtain a coding sequence, where the coding sequence is obtained.
  • LDPC Low Density Parity Check Code
  • N information bits, L padding bits, and N+L parity bits generated by encoding are a positive integer; and N information bits and all parity bits in the coding sequence form a first sequence And obtaining a second sequence according to the first sequence, wherein the first sequence and the second sequence are the same length; modulating the first sequence to obtain a first modulation sequence, Modulating the second sequence to obtain a second modulation sequence; inserting a guard interval GI between the first modulation sequence and the second modulation sequence, and obtaining a coded modulated EDMG Header sequence according to a sequence inserted after the guard interval , the coded modulated EDMG Header sequence and to be sent The data is combined to obtain a frame and the frame is transmitted.
  • the present invention performs unified 1/2 LDPC encoding on the control bits in the EDMG Header sequence, and directly obtains two sequences including all control bits according to the encoded coding sequence, and then performs the two sequences.
  • the frame is modulated and transmitted, and the transmission performance of the frame can be improved by such a retransmission design.
  • the bits in the EDMG Header sequence may be directly padded.
  • the padding sequence includes N information bits and L padding bits, and the N information bits may be N in the EDMG Header sequence. Control bits.
  • the EDMG Header sequence may be scrambled before the EDMG Header sequence is filled, and then the scrambled sequence is filled. Accordingly, the padding sequence includes N information bits and L padding bits, N information bits may be obtained by scrambling N control bits.
  • the EDMG Header sequence may include a part of Cyclic Redundancy Check (CRC) bits, and the number of CRC bits may be 16 or 32.
  • CRC Cyclic Redundancy Check
  • the present invention implements frame retransmission by constructing two sequences each including N information bits. Such a design can better meet the needs of long-distance frame transmission and improve transmission performance.
  • the length of the code sequence may be 672, ie the code sequence comprises 672 bits.
  • the first sequence and the second sequence have the same length, both of which are 448. That is to say, in one embodiment of the present invention, two sequences including 448 bits can be directly constructed from the coding sequence, and a guard interval is inserted between the two sequences. It is not necessary to construct two 224-bit sequences from the coding sequence, and then combine the two 224-bit sequences into a 448-bit sequence, so that unified coding can improve the performance of the transmission frame.
  • information bits are uniformly coded and two 448-bit sequences are directly constructed from the encoded code sequence to implement retransmission of signaling without dividing the encoded sequence into multiple
  • a 64-bit sequence is used for each 64-bit sequence, which enables 802.11ad, which enables retransmission of signaling, improves the performance of the transmitted frame, and improves transmission accuracy.
  • the obtaining the second sequence according to the first sequence includes: performing the first sequence Performing an exclusive OR operation to obtain the second sequence; or performing an interleaving process on the first sequence to obtain the second sequence.
  • the sequence after scrambling the sequences b 1 , b 2 , . . . , b 112 is q 1 , q 2 ,... , q 112 .
  • the padding sequence is q 1 , q 2 ,..., q 112 , 0 1 , 0 2 ,..., 0 224
  • the coding sequence is q 1 , q 2 ,..., q 112 , 0 1 , 0 2 ,..., 0 224 , p 1 , p 2 ,...,p 336
  • p 1 , p 2 , . . . , p 336 are parity bit sequences generated by 1/2 LDPC encoding.
  • the first sequence constructed by the above coding sequence may be q 1 , q 2 , . . . , q 112 , p 1 , p 2 , . . . , p 336
  • the second sequence may be an exclusive OR operation or interleaving process on the first sequence. of.
  • the performing an exclusive-OR operation on the first sequence includes: adopting the first sequence Performing an exclusive OR operation on a set of pseudo-random sequences to obtain the second sequence; or, using the sequence ⁇ 0, 1, 0, 1...0, 1 ⁇ or sequence for the first sequence ⁇ 1, 0, 1...1, 0 ⁇ performs an exclusive OR operation to obtain the second sequence.
  • the first sequence is modulated to obtain a first modulation sequence
  • the second sequence is modulated to obtain a second
  • the modulation sequence includes: performing ⁇ /2 BPSK modulation or BPSK modulation on the first sequence to obtain a first modulation sequence; and performing ⁇ /2 BPSK modulation or BPSK modulation on the second sequence to obtain a second modulation sequence.
  • a second aspect provides a method for transmitting a frame, comprising: acquiring an initial enhanced directional multi-gigabit frame header EDMG Header sequence, wherein the initial EDMG Header sequence includes N control bits, and N is a positive integer; The initial EDMG Header sequence performs a padding operation to obtain a padding sequence, where the padding sequence includes N information bits and L padding bits, and the N information bits are the N control bits or the N pieces The information bits are obtained by scrambling the N control bits; performing 1/2 low-density parity check code LDPC coding on the padding sequence to obtain a coding sequence, where the coding sequence includes N information bits, L padding bits and N+L parity bits generated by encoding, L is a positive integer; forming N first information bits and first part parity bits in the coding sequence to form the first sequence, and according to The N information bits and the second partial parity bits in the coding sequence obtain the second sequence, wherein the first sequence and the second sequence have the same length, the first part The even parity bits and
  • the obtaining according to the N information bits and the second partial parity bit in the coding sequence includes forming N information bits and second partial parity bits in the coding sequence into the second sequence.
  • the sum of the N information bits and the N+L parity bits is greater than 448, in which case the sequence constructed directly from the information bits and parity bits in the coding sequence If the length is greater than 448, a part of the bits need to be discarded, so that the resulting sequence length is 448. That is, when N>112, the first sequence of 448 bits may be formed by the N information bits and the first partial parity bits, and the second sequence of 448 bits is constructed according to the N information bits and the second partial parity bits. The first sequence and the second sequence thus obtained include N information bits, and the information bits are retransmitted, which can improve the accuracy of the transmission frame and improve the transmission performance.
  • the sequence after scrambling the sequences b 1 , b 2 , . . . , b N is q 1 , q 2 , . . . , q N.
  • the padding sequence is q 1 , q 2 ,...,q N ,0 1 ,0 2 ,...,0 336-N
  • the coding sequence is q 1 , q 2 ,...,q N ,0 1 ,0 2 ,...,0 336-N , p 1 , p 2 ,..., p 336 .
  • p 1 , p 2 , . . . , p 336 are parity bit sequences generated by 1/2 LDPC encoding.
  • the first sequence constructed by the above coding sequence may be q 1 , q 2 , ..., q N , p 1 , p 2 , ..., p 448-N
  • the third sequence constructed by the above coding sequence may be q 1 , q 2 , ..., q N , p 1 , p 2 , ... p 560-2N , p 448-N+1 , ... p 336
  • the second sequence may be obtained by performing an exclusive OR operation or interleaving process on the third sequence.
  • the first sequence may be q 1 , q 2 , . . . , q 128 , p 1 , p 2 , . . . , p 320
  • the third sequence may be q 1 , q 2 , . . . , q 128 . , p 1 , p 2 ,...p 304 , p 321 ,...p 336 .
  • the obtaining the second sequence according to the N information bits and the second partial parity bits in the coding sequence comprises: forming N information bits and a second partial parity bit in the coding sequence a third sequence; performing an exclusive OR operation or an interleaving process on the third sequence to obtain the second sequence.
  • the performing, by performing an exclusive OR operation or an interleaving process on the third sequence, to obtain the second sequence includes: The three sequences are XORed using a set of pseudo-random sequences to obtain the second sequence; or, for the third sequence, the sequence ⁇ 0, 1, 0, 1...0, 1 ⁇ or the sequence ⁇ 1, 0, An exclusive OR operation is performed by 1...1, 0 ⁇ to obtain the second sequence.
  • the first partial parity bit and the second partial parity bit constitute all parity bits.
  • the first partial parity bits form a first set
  • the second partial parity bits form a second set
  • the union of the first set and the second set constitutes all parity bits.
  • the common bit number in the first partial parity bit and the second partial parity bit is greater than a threshold
  • the threshold is a preset value, or the threshold is determined by the number of all parity bits.
  • the first partial parity bits constitute a first set
  • the second partial parity bits constitute a second set
  • the intersection of the first set and the second set constitutes a third set, in the third set
  • a guard interval is inserted between the first modulation sequence and the second modulation sequence, and protection is also inserted before the first modulation sequence and after the second modulation sequence. Interval, the EDMG Header is obtained, and the EDMG Header and the data to be transmitted are combined to obtain the frame, and the frame is transmitted.
  • the modulating the first sequence to obtain a first modulation sequence, and modulating the second sequence to obtain a second The modulation sequence includes: performing ⁇ /2 BPSK modulation or BPSK modulation on the first sequence to obtain a first modulation sequence; and performing ⁇ /2 BPSK modulation or BPSK modulation on the second sequence to obtain a second modulation sequence.
  • the modulation of the first sequence and the second sequence in the present application may be BPSK modulation or ⁇ /2 BPSK modulation.
  • an apparatus for transmitting a frame comprising: an obtaining unit, configured to obtain an initial enhanced directional multi-gigabit frame header EDMG Header sequence, where the initial EDMG Header sequence includes N control bits, N a padding unit, configured to perform a padding operation on the initial EDMG Header sequence obtained by the acquiring unit to obtain a padding sequence, where the padding sequence includes N information bits and L padding bits, and the N pieces of information
  • the bit is the N control bits or the N information bits are obtained by scrambling the N control bits, and the coding unit is configured to perform 1/2 low on the padding sequence obtained by the padding unit.
  • LDPC encoding the density parity check code to obtain a coded sequence, wherein the code sequence includes N information bits, L padding bits, and N+L parity bits generated by the code, L is a positive integer; Forming a first sequence by forming N information bits and all parity bits in the coding sequence obtained by the coding unit, and obtaining a second sequence according to the first sequence, The first sequence and the second sequence are the same length; the modulating unit is configured to separately modulate the first sequence and the second sequence obtained by the constructing unit to obtain a first modulation sequence and a second modulation a sequence; a processing and transmission unit for the first modulation sequence obtained at the modulation unit and A guard interval GI is inserted between the second modulation sequences, and a coded and modulated EDMG Header sequence is obtained according to the sequence after the guard interval is inserted, and the coded modulated EDMG Header sequence is combined with the data to be transmitted to obtain a frame, and transmitted.
  • the frame is a positive integer
  • the present invention performs unified 1/2 LDPC encoding on the control bits in the EDMG Header sequence, and directly obtains two sequences including all control bits according to the encoded coding sequence, and then performs the two sequences.
  • the frame is modulated and transmitted, and the transmission performance of the frame can be improved by such a retransmission design.
  • the constructing unit is specifically configured to perform an exclusive OR operation on the first sequence to obtain the second Sequence, or, interleaving the first sequence to obtain the second sequence.
  • the constructing unit is specifically configured to perform an exclusive-OR operation on the first sequence by using a set of pseudo-random sequences to obtain the second a sequence; or, performing an exclusive OR operation on the first sequence using the sequence ⁇ 0, 1, 0, 1...0, 1 ⁇ or the sequence ⁇ 1, 0, 1...1, 0 ⁇ to obtain the second sequence.
  • the modulating unit is specifically configured to perform ⁇ /2 BPSK modulation or BPSK modulation on the first sequence to obtain a first modulation sequence. And performing ⁇ /2 BPSK modulation or BPSK modulation on the second sequence to obtain a second modulation sequence.
  • the apparatus for transmitting a frame according to the third aspect of the present application may refer to the method flow of the transmission frame in the first aspect of the present application, and the respective units/modules in the apparatus and the other operations and/or functions described above respectively implement the first
  • the corresponding flow in the method shown in the aspect is not repeated here for brevity.
  • a fourth aspect provides an apparatus for transmitting a frame, comprising: an obtaining unit, configured to acquire an initial enhanced directional multi-gigabit frame header EDMG Header sequence, where the initial EDMG Header sequence includes N control bits, N a padding unit, configured to perform a padding operation on the initial EDMG Header sequence obtained by the acquiring unit to obtain a padding sequence, where the padding sequence includes N information bits and L padding bits, and the N pieces of information
  • the bit is the N control bits or the N information bits are obtained by scrambling the N control bits, and the coding unit is configured to perform 1/2 low on the padding sequence obtained by the padding unit.
  • the LDPC encoding the density parity check code to obtain a coded sequence, wherein the code sequence includes N information bits, L padding bits, and N+L parity bits generated by the code, L is a positive integer; And N pieces of information bits and the first part of parity bits in the coding sequence obtained by the coding unit form the first sequence, and are obtained according to the coding unit.
  • the N information bits and the second partial parity bits in the coding sequence obtain the second sequence, wherein the first sequence and the second sequence have the same length, the first partial parity bit and The second partial parity bit includes not all the same bits;
  • the modulating unit is configured to separately modulate the first sequence and the second sequence obtained by the structural unit to obtain a first modulation sequence and a second modulation sequence.
  • a processing and transmission unit configured to insert a guard interval GI between the first modulation sequence and the second modulation sequence obtained by the modulation unit, and obtain a coded modulated EDMG Header according to a sequence after inserting the guard interval A sequence, the coded modulated EDMG Header sequence and the data to be transmitted are combined to obtain a frame, and the frame is transmitted.
  • the constructing unit is specifically configured to form the N information bits and the second partial parity bits in the coding sequence to form the second sequence.
  • the constructing unit when N>112, is specifically configured to use the N information bits and the second part in the coding sequence.
  • the parity bits constitute a third sequence, and the second sequence is subjected to an exclusive OR operation or an interleaving process to obtain the second sequence.
  • the constructing unit is specifically configured to perform an exclusive-OR operation on the third sequence by using a set of pseudo-random sequences to obtain the a second sequence, or XORing the sequence with the sequence ⁇ 0, 1, 0, 1...0, 1 ⁇ or the sequence ⁇ 1, 0, 1...1, 0 ⁇ to obtain the second sequence .
  • the first partial parity bit and the second partial parity bit constitute all parity bits.
  • the common bit number in the first partial parity bit and the second partial parity bit is greater than a threshold
  • the threshold is a preset value, or the threshold is determined by the number of all parity bits.
  • the processing and transmission unit is specifically configured to insert a guard interval between the first modulation sequence and the second modulation sequence, and insert a guard interval before the first modulation sequence and after the second modulation sequence.
  • the modulating unit is specifically configured to perform ⁇ /2 BPSK modulation or BPSK modulation on the first sequence to obtain a first modulation sequence, And performing ⁇ /2 BPSK modulation or BPSK modulation on the second sequence to obtain a second modulation sequence.
  • the apparatus for transmitting a frame according to the fourth aspect of the present application may refer to the method flow of the transmission frame in the second aspect of the present application, and the respective units/modules in the apparatus and the other operations and/or functions described above respectively implement the second
  • the corresponding flow in the method shown in the aspect is not repeated here for brevity.
  • a method of transmitting a frame comprising receiving a frame as described in the first aspect, and demodulating and decoding the frame.
  • a method of transmitting a frame comprising receiving a frame as described in the second aspect, and demodulating and decoding the frame.
  • FIG. 1 is a schematic diagram of a scenario of a communication system to which the present application is applicable.
  • FIG. 2 is a schematic flowchart of a method for transmitting a frame according to an embodiment of the present invention.
  • FIG. 3 is a schematic flowchart of a method for transmitting a frame according to another embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a frame structure in an 802.11ay protocol according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of an EDMG Header field in a frame structure in an 802.11ay protocol according to an embodiment of the present invention.
  • FIG. 6 is a schematic flowchart of a method for transmitting a frame according to another embodiment of the present invention.
  • FIG. 7 is a schematic flowchart of a method for transmitting a frame according to another embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of an apparatus for transmitting a frame according to an embodiment of the present invention.
  • FIG. 9 is a schematic structural diagram of an apparatus for transmitting a frame according to another embodiment of the present invention.
  • FIG. 10 is a schematic structural diagram of an apparatus for transmitting a frame according to another embodiment of the present invention.
  • FIG. 11 is a schematic structural diagram of an apparatus for transmitting a frame according to another embodiment of the present invention.
  • FIG. 1 is a schematic diagram of a scenario of a communication system to which the present application is applicable.
  • the communication system of Figure 1 includes an AP and three STAs. For example, STA1, STA2, and STA3 in FIG.
  • the AP can communicate with STA1, STA2, and STA3.
  • an AP can schedule multiple STAs for signaling transmission and demodulation. It should be noted that the number of STAs is not limited, and the present invention is exemplified by only three examples.
  • the technical solution of the present invention can be applied to various communication systems that need to transmit frames, for example, WLAN, Wi-Fi, etc. using multi-user multiple input multiple output (MU-MIMO) technology.
  • MU-MIMO multi-user multiple input multiple output
  • the AP is an access point for mobile users to enter the wired network. It is mainly deployed in the home, inside the building, and inside the campus. The typical coverage radius is tens of meters to hundreds of meters. Of course, it can also be deployed outdoors.
  • An AP is equivalent to a bridge connecting a wired network and a wireless network. Its main function is to connect the wireless network clients together and then connect the wireless network to the Ethernet.
  • the main standard adopted by AP is the Institute of Electrical and Electronics Engineers (IEEE) 802.11 series.
  • the AP may be a terminal device or a network device with a Wi-Fi chip.
  • the AP may be a device supporting the 802.11ay system, and optionally, the AP may also support multiple WLAN technologies such as 802.11ay, 802.11ad, 802.11ac, 802.11n, 802.11g, 802.11b, and 802.11a. device of.
  • STA which can be a wireless communication chip, a wireless sensor or a wireless communication terminal.
  • the site can support the 802.11ay system. Further optionally, the site supports multiple WLAN formats such as 802.11ay, 802.11ad, 802.11ac, 802.11n, 802.11g, 802.11b, and 802.11a.
  • FIG. 2 is a schematic flowchart of a method for transmitting a frame according to an embodiment of the present invention.
  • the method shown in FIG. 2 can be performed by the AP in FIG. 1 or by the STA in FIG. 1.
  • the devices that perform the method of Figure 2 can be collectively referred to as a transmitter.
  • the specific process of the method for transmitting frames shown in FIG. 2 is as follows:
  • the initial EDMG Header sequence includes N control bits, and N is a positive integer.
  • the CRC bits may be included in the N control bits in the initial EDMG Header sequence.
  • the order of CRC check and scrambling processing for the bit sequence to be transmitted may be interchanged, and the initial EDMG Header sequence may be obtained after scrambling and/or CRC check.
  • the bit sequence to be transmitted may not be scrambled, and the sequence obtained after the CRC check is used as the initial EDMG Header sequence.
  • the padding sequence includes N information bits and L padding bits, and N information bits are N control bits or N information bits are obtained by scrambling N control bits.
  • the padding bits in the present application may be 0 bits.
  • the padding operation is to satisfy the requirement of the number of bits in the subsequent LDPC encoding. For example, to perform 1/2 LDPC encoding, and the encoded sequence should satisfy 672 bits, the number of bits in the bit sequence before encoding should satisfy 1/2 of 672, that is, 336. Moreover, the number of parity bits generated by 1/2 LDPC encoding is also 1/2 of 672, that is, 336.
  • the code sequence includes N control bits, L padding bits, and N+L parity bits generated by the code, where L is a positive integer.
  • the N information bits and all the parity bits in the coding sequence form a first sequence, and the second sequence is obtained according to the first sequence.
  • the first sequence and the second sequence have the same length.
  • the bit sequence EDMG Header sequence to be transmitted is b 1 , b 2 , ..., b 112
  • the sequence after scrambling the sequences b 1 , b 2 , ..., b 112 is q 1 , q 2 ,...,q 112 .
  • the padding sequence is q 1 , q 2 ,..., q 112 , 0 1 , 0 2 ,..., 0 224
  • the coding sequence is q 1 , q 2 ,..., q 112 , 0 1 , 0 2 ,..., 0 224 , p 1 , p 2 ,...,p 336 .
  • p 1 , p 2 , . . . , p 336 are parity bit sequences generated by 1/2 LDPC encoding.
  • the first sequence constructed by the above coding sequence may be q 1 , q 2 , . . . , q 112 , p 1 , p 2 , . . . , p 336
  • the second sequence may be an exclusive OR operation or interleaving process on the first sequence. of.
  • the first sequence can be directly used as the second sequence without performing an exclusive OR operation or an interleaving process.
  • both the first sequence and the second sequence are 448 in length.
  • the XOR operation in the present application may be a sequence ⁇ 0, 1, 0, 1...0, 1 ⁇ or a sequence ⁇ 1, 0, 1...1, 0 ⁇ , or a set of pseudo-random sequences may be used. There is no limit to this.
  • both the first sequence and the second sequence may be modulated by Binary Phase Shift Keying (BPSK) modulation or ⁇ /2BPSK modulation, thereby obtaining a corresponding first modulation.
  • BPSK Binary Phase Shift Keying
  • Insert a guard interval GI between the first modulation sequence and the second modulation sequence obtain a coded modulated EDMG Header sequence according to the sequence inserted after the guard interval, and combine the coded modulated EDMG Header sequence with the data to be sent. Frame and transmit the frame.
  • Inserting a guard interval between the first modulation sequence and the second modulation sequence can be distinguished from the 802.11ad design of the header.
  • 802.11ad two 224-bit sequences are constructed, and two 224-bit sequences are directly combined to form a 448-bit sequence, and no guard interval is inserted in the two 224 bit sequences.
  • the bit sequence is reversed to form another 448-bit sequence, and a guard interval is inserted between the two 448-bit sequences to obtain a coded modulated EDMG Header sequence, and the coded modulated EDMG Header sequence is combined with the data to be transmitted.
  • the frame is constructed and transmitted.
  • the application is directly constructed to obtain 448 bits, and the implementation is simpler.
  • a guard interval may be inserted before and after the first modulation sequence and the second modulation sequence, so that the obtained frame is transmitted to improve the reliability of the transmission frame.
  • the present invention performs unified 1/2 LDPC encoding on the control bits in the EDMG Header sequence, and directly obtains two sequences including all control bits according to the encoded coding sequence, and then performs the two sequences.
  • the frame is modulated and transmitted, and the transmission performance of the frame can be improved by such a retransmission design.
  • the method of FIG. 1 may be performed by a transmitter of a single carrier system, and after receiving a frame, the receiver may block the received frame, delete the cyclic prefix in each block, and Perform a Fourier transform on the data group after deleting the cyclic prefix and transform it into the frequency domain. Then, the data transformed into the frequency domain is subjected to frequency domain equalization processing using frequency domain channel information, and the data after frequency domain equalization is transformed into the time domain by inverse Fourier transform to demodulate and decode the time domain signal.
  • the two received sequences of length 448 can be separately demodulated to obtain two corresponding log likelihood ratios, and the two log likelihood ratios are combined.
  • FIG. 3 is a schematic flowchart of a method for transmitting a frame according to another embodiment of the present invention.
  • the method shown in FIG. 3 may be performed by the AP in FIG. 1 or by the STA in FIG. 1.
  • the devices that perform the method of Figure 3 can be collectively referred to as a transmitter.
  • the specific process of the method for transmitting frames shown in FIG. 3 is as follows:
  • the initial EDMG Header sequence includes N control bits, and N is a positive integer.
  • the CRC bits may be included in the N control bits in the initial EDMG Header sequence.
  • the order of CRC check and scrambling processing for the bit sequence to be transmitted may be interchanged, and the initial EDMG Header sequence may be obtained after scrambling and/or CRC check.
  • the bit sequence to be transmitted may not be scrambled, and the sequence obtained after the CRC check is used as the initial EDMG Header sequence.
  • the padding sequence includes N information bits and L padding bits, and N information bits are N control bits or N information bits are obtained by scrambling N control bits.
  • the initial EDMG Header sequence may be padded with 0 bits on the basis of the initial EDMG Header sequence.
  • the padding operation is to satisfy the requirement of the number of bits in the subsequent LDPC encoding.
  • the number of bits in the bit sequence before encoding should satisfy 1/2 of 672, that is, 336.
  • the number of parity bits generated by 1/2 LDPC encoding is also 1/2 of 672, that is, 336.
  • the code sequence includes N control bits, L padding bits, and N+L parity bits generated by the code, where L is a positive integer.
  • the N information bits and the first partial parity bits in the coding sequence form a first sequence, and obtain a second sequence according to the N information bits and the second partial parity bits in the coding sequence, where the first The sequence and the second sequence have the same length, and the first partial parity bit and the second partial parity bit do not all have the same parity bits.
  • the bit sequence EDMG Header sequence to be transmitted is b 1 , b 2 , . . . , b N
  • the sequence after scrambling the sequences b 1 , b 2 , . . . , b N is q 1 , q 2 ,...,q N
  • the padding sequence is q 1 , q 2 ,...,q N ,0 1 ,0 2 ,...,0 336-N
  • the coding sequence is q 1 , q 2 ,...,q N ,0 1 ,0 2 ,...,0 336-N , p 1 , p 2 ,..., p 336 .
  • p 1 , p 2 , . . . , p 336 are parity bit sequences generated by 1/2 LDPC encoding.
  • the first sequence constructed by the above coding sequence may be q 1 , q 2 , ..., q N , p 1 , p 2 , ..., p 448-N
  • the third sequence constructed by the above coding sequence may be q 1 , q 2 , ..., q N , p 1 , p 2 , ... p 560-2N , p 448-N+1 , ... p 336
  • the second sequence may be obtained by performing an exclusive OR operation or interleaving process on the third sequence.
  • the third sequence can be directly used as the second sequence without processing. Only when the second sequence is processed to obtain the second sequence, the third sequence has a slightly lower performance gain as the second sequence.
  • both the first sequence and the second sequence are 448 in length.
  • the XOR operation in the present application may be a sequence ⁇ 0, 1, 0, 1...0, 1 ⁇ or a sequence ⁇ 1, 0, 1...1, 0 ⁇ , or a set of pseudo-random sequences may be used. There is no limit to this.
  • the first partial parity bits form a first set
  • the second partial parity bits form a second set
  • the union of the first set and the second set constitutes all parity bits.
  • both the first sequence and the second sequence may be modulated by Binary Phase Shift Keying (BPSK) modulation or ⁇ /2BPSK modulation, thereby obtaining a corresponding first modulation.
  • BPSK Binary Phase Shift Keying
  • Insert a guard interval GI between the first modulation sequence and the second modulation sequence obtain a coded modulated EDMG Header sequence according to the sequence after the guard interval is inserted, and combine the coded modulated EDMG Header sequence with the data to be sent. Frame and transmit the frame.
  • Inserting a guard interval between the first modulation sequence and the second modulation sequence can be distinguished from the 802.11ad design of the header.
  • 802.11ad two 224-bit sequences are constructed, and two 224-bit sequences are directly combined to form a 448-bit sequence, and no guard interval is inserted in the two 224 bit sequences.
  • the bit sequence is reversed to form another 448-bit sequence, and a guard interval is inserted between the two 448-bit sequences to obtain a code-modulated EDMG Header sequence, which combines the coded modulated EDMG Header sequence with the data to be transmitted.
  • the frame is constructed and transmitted.
  • the application is directly constructed to obtain 448 bits, and the implementation is simpler.
  • a guard interval may be inserted before and after the first modulation sequence and the second modulation sequence, so that the obtained frame is transmitted to improve the reliability of the transmission frame.
  • the present invention performs unified 1/2 LDPC encoding on the control bits in the EDMG Header sequence, and directly obtains two sequences including all control bits according to the encoded coding sequence, and then performs the two sequences.
  • the frame is modulated and transmitted, and the transmission performance of the frame can be improved by such a retransmission design.
  • the method of FIG. 1 may be performed by a transmitter of a single carrier system, and after receiving a frame, the receiver may block the received frame, delete the cyclic prefix in each block, and Perform a Fourier transform on the data group after deleting the cyclic prefix and transform it into the frequency domain. Then, the data transformed into the frequency domain is subjected to frequency domain equalization processing using frequency domain channel information, and the data after frequency domain equalization is transformed into the time domain by inverse Fourier transform to demodulate and decode the time domain signal.
  • the two received sequences of length 448 can be separately demodulated to obtain two corresponding log likelihood ratios, and the two log likelihood ratios are combined.
  • the frame structure includes a Legacy Short Training Field (STF) field, a Channel Estimation (CE) field, a Header field, an EDMG-Header field, and an EDMG load (Payload). Field.
  • STF Legacy Short Training Field
  • CE Channel Estimation
  • Payload EDMG load
  • the EDMG-Header can be coded and modulated according to the design of the EDMG-Header, and the frame can be output.
  • the STF is used for synchronization, frequency offset estimation, and automatic Gain Control (AGC) adjustment, and the receiver can synchronize according to the received STF signal.
  • AGC automatic Gain Control
  • the CE is used for channel estimation, that is, the receiver can perform channel estimation based on the received CE signal.
  • the Header field is used to indicate an indication signal, and can be used, for example, to indicate a modulation scheme of the data frame or the like.
  • the EDMG-Header is used to indicate control signaling in 802.11ay.
  • EDMG Payload is used to transfer data in 80.211ay.
  • the receiver can implement demodulation, decoding, and the like of the data according to the received Header signal and the EDMG-Header signal. This application mainly introduces the design of EDMG-Header.
  • FIG. 5 is a schematic diagram of an EDMG Header field in a frame structure in an 802.11ay protocol according to an embodiment of the present invention.
  • the EDMG Header field in this application is composed of two consecutive sequence insertion guard intervals (GI), as shown in FIG.
  • the two sequences are a first modulation sequence and a second modulation sequence, and the lengths of the first modulation sequence and the second modulation sequence are both 448.
  • the first modulation sequence includes 448 symbols
  • the second modulation sequence includes 448. symbol.
  • the GI may be composed of 64 symbols. Inserting a guard interval can reduce Inter-Symbol Interference (ISI) and Inter-Channel Interference (ICI) caused by multipath.
  • the receiver can also perform channel equalization and phase offset estimation based on the guard interval.
  • FIG. 6 is a schematic flowchart of a method for transmitting a frame according to another embodiment of the present invention.
  • the method of FIG. 6 may be performed by a transmitter, which may be the AP in FIG. 1 or the STA in FIG.
  • FIG. 6 exemplifies an example in which an initial EDMG Header sequence includes 112 control bits.
  • the initial EDMG Header sequence includes 112 control bits: b 1 , b 2 , ..., b 112 .
  • the 112 control bits may include information bits and CRC bits.
  • the number of information bits and check bits is not limited.
  • 96 information bits and 16 CRC check bits are taken as an example for illustration.
  • the EDMG Header (96) in Figure 6 indicates that the initial EDMG Header sequence includes 96 information bits, and the CRC (16) indicates that the initial EDMG Header sequence includes 16 CRC bits.
  • 96 information bits and 16 CRC bits are denoted as b 1 , b 2 , ..., b 112 .
  • the initial EDMG Header sequence in 802.11ay in question includes 82 information bits, where the information bits can be extended, for example, by filling 14 information bits to form the 96 information bits of the present application. If the bits to be transmitted are less than 112, some bits can be filled in the information bits to form 96 information bits.
  • the 112 control bits b 1 , b 2 , ..., b 112 are scrambled to obtain scrambling sequences q 1 , q 2 , ..., q 112 .
  • the scrambling in the present application may be an optional step or may not be scrambled. That is to say, the sequence b 1 , b 2 , ..., b 112 can be directly operated as follows, and the scrambled sequences q 1 , q 2 , ..., q 112 can be operated as follows. The following is an example of processing the scrambled sequence as an example.
  • the sequence q 1 , q 2 , . . . , q 112 is padded such that the padding fill sequence has a length of 336.
  • padding 0 bits yields a stuffing sequence q 1 , q 2 , . . . , q 112 , 0 1 , 0 2 , . . . , 0 224 .
  • the 0 bits in the coding sequence are removed, resulting in a first sequence q 1 , q 2 , . . . , q 112 , p 1 , p 2 , . . . , p 336 .
  • the first sequence includes 96 information bits, 16 CRC bits and 336 parity bits.
  • the first sequence q 1 , q 2 , . . . , q 112 , p 1 , p 2 , . . . , p 336 is subjected to ⁇ /2 BPSK or BPSK modulation and mapping processing to obtain a first modulation sequence.
  • the first sequence q 1 , q 2 , . . . , q 112 , p 1 , p 2 , . . . , p 336 is subjected to an exclusive OR operation or an interleaving process to obtain a second sequence.
  • the first sequence q 1 , q 2 , . . . , q 112 , p 1 , p 2 , . . . , p 336 may be scrambled using a set of pseudo-random sequences to obtain a second sequence.
  • an exclusive OR operation may be performed on the first sequence using a sequence of ⁇ 0, 1, 0, 1...0, 1 ⁇ or ⁇ 1, 0, 1...1, 0 ⁇ , the ⁇ 0, 1, 0
  • the sequence of 1...0,1 ⁇ or ⁇ 1,0,1...1,0 ⁇ is arranged at intervals of 0 and 1.
  • the length of the sequence is 448, and the number of 0 and 1 is 224.
  • the sequence of ⁇ 0,1,0,1...0,1 ⁇ can also be written as mod(k,2), and the sequence of ⁇ 1,0,1...1,0 ⁇ can be written as mod(k,2), where mod() is For the remainder operation, k is a positive integer from 0 to 447.
  • interleaving the removal sequences q 1 , q 2 , . . . , q 112 , p 1 , p 2 , . . . , p 336 may use a simple interleaver to reverse the first sequence to obtain a second sequence p. 336 , p 335 , . . . , p 2 , p 1 , q 112 , . . . q 2 , q 1 .
  • Step 205 is an optional step.
  • the first sequence obtained in step 203 may be directly used as the second sequence without performing step 205.
  • the process proceeds to step 204 and step 206, and the first sequence is performed.
  • the modulation mapping is performed, that is, the second sequence is equal to the first sequence and the second modulation sequence is also equal to the first modulation sequence.
  • the second sequence is subjected to ⁇ /2 BPSK or BPSK modulation and mapping processing to obtain a second modulation sequence.
  • a guard interval is inserted before and after the first modulation sequence and the second modulation sequence, as shown in FIG. 4, specifically, a guard interval is inserted before the first modulation sequence, and a first modulation sequence and a second modulation sequence are inserted.
  • the guard interval is inserted after the second modulation sequence.
  • the guard interval can be composed of 64 symbols.
  • guard interval After the guard interval is inserted, two consecutive 448-bit modulation sequences with guard intervals are inserted, and the guard interval and the two modulation sequences are combined with the data to be transmitted to form a frame, which can be used for transmission.
  • the initial EDMG Header since the initial EDMG Header includes 82 information bits, in order to adopt the method of transmitting 64 bits in the existing 802.11ad, 30 padding bits are filled in the EDMG Header to make up 128 bits. And divided into two 64 bits to use the modulation scheme of EDMG Header in 802.11ad respectively.
  • the scheme of the present application does not necessarily require 30 padding bits, so that the scheme can transmit 16 padding bits less. But the performance gain can be increased by 2dB.
  • the input LDPC decoder obtains 336 bit estimates b 1 , b 2 , ..., b 336 , wherein the first 112 bit estimates are estimates of 112 control bits for the transmitter to transmit the EDMG Header sequence.
  • FIG. 7 is a schematic flowchart of a method for transmitting a frame according to another embodiment of the present invention.
  • the method of FIG. 7 may be performed by a transmitter, which may be the AP in FIG. 1 or the STA in FIG.
  • FIG. 7 illustrates an example in which the initial EDMG Header sequence includes 128 control bits. It should be understood that the method of transmitting frames shown in FIG. 7 can be used for the number of control bits greater than 112.
  • the initial EDMG Header sequence includes 128 control bits: b 1 , b 2 , ..., b 128 .
  • the 128 control bits may include information bits and CRC bits. The number of information bits and check bits is not limited.
  • 112 information bits and 16 CRC check bits are taken as an example for illustration.
  • the EDMG Header (112) in Figure 7 indicates that the initial EDMG Header sequence includes 112 information bits, and the CRC (16) indicates that the initial EDMG Header sequence includes 16 CRC bits.
  • the EDMG Header sequence in 802.11ay in question includes 82 information bits, where information bits can be extended, for example, padding 30 information bits to form 112 information bits of the present application.
  • 112 information bits and 16 CRC bits are denoted as b 1 , b 2 , ..., b 128 .
  • the 128 control bits b 1 , b 2 , ..., b 128 are scrambled to obtain scrambling sequences q 1 , q 2 , ..., q 128 .
  • the scrambling in the present application may be an optional step or may not be scrambled. That is to say, the sequence b 1 , b 2 , . . . , b 128 can be directly operated as follows, and the scrambled sequences q 1 , q 2 , . . . , q 128 can also be operated as follows. The following is an example of processing the scrambled sequences q 1 , q 2 , . . . , q 128 as an example.
  • the sequence q 1 , q 2 , . . . , q 128 is padded so that the length of the padding sequence after padding is 336.
  • padding 0 bits yields a padding sequence q 1 , q 2 , . . . , q 128 , 0 1 , 0 2 , . . . , 0 208 .
  • the 0 bits in the coding sequence are removed, and the 128 information bits and the first partial parity bits in the coding sequence form a first sequence, the first sequence having a length of exactly 448.
  • the first sequence is: q 1 , q 2 , . . . , q 128 , p 1 , p 2 , . . . , p 320 .
  • the 128 information bits in the coding sequence are q 1 , q 2 , ..., q 128 .
  • the first sequence q 1 , q 2 , . . . , q 112 , p 1 , p 2 , . . . , p 320 is subjected to ⁇ /2 BPSK or BPSK modulation, and the mapping process is performed to obtain a first modulation sequence.
  • the 0 bits in the coding sequence are removed, and the 128 information bits and the second partial parity bits in the coding sequence form a third sequence, and the length of the third sequence is also exactly 448.
  • the third sequence is: q 1 , q 2 , . . . , q 128 , p 1 , p 2 , . . . , p 304 , p 321 , . . . , p 336 .
  • the second sequence is performed by performing an exclusive OR operation or interleaving process on the third sequence q 1 , q 2 , . . . , q 128 , p 1 , p 2 , . . . , p 304 , p 321 , . . . , p 336 .
  • the removal sequences q 1 , q 2 , . . . , q 128 , p 1 , p 2 , . . . , p 304 , p 321 , . . . , p 336 may be scrambled using a set of pseudo-random sequences to obtain a second sequence.
  • a sequence of ⁇ 0, 1, 0, 1...0, 1 ⁇ may be XORed on the removal sequence, and 0 and 1 in the sequence of ⁇ 0, 1, 0, 1...0, 1 ⁇ Arranged at intervals, the length of the sequence is 448, and the sequence of ⁇ 0, 1, 0, 1...0, 1 ⁇ can also be written as mod(k, 2), where mod() is the remainder operation and k is the positive from 0 to 447. Integer.
  • the sequence of ⁇ 1, 0, 1...1, 0 ⁇ may be exclusive-ORed on the removal sequence, and the sequence of ⁇ 1, 0, 1...1, 0 ⁇ is arranged at intervals of 0 and 1.
  • the length is 448, and the sequence of ⁇ 1, 0, 1...1, 0 ⁇ can also be written as mod(k+1, 2), where mod() is a remainder operation and k is a positive integer from 0 to 447.
  • interleaving the removal sequences q 1 , q 2 , . . . , q 128 , p 1 , p 2 , . . . , p 304 , p 321 , . . . , p 336 may use a simple interleaver to sequence the third sequence. In reverse order, a second sequence p 336 , p 335 , . . . , p 321 , p 304 , . . . , p 2 , p 1 , q 128 , . . . q 2 , q 1 is obtained .
  • step 306 is an optional step.
  • the third sequence constructed in step 305 may be directly used as a sequence for performing modulation mapping, and after step 305, directly proceed to step 307 to perform modulation mapping on the sequence.
  • a second modulation sequence is obtained. That is to say, the constructed third sequence is considered to be the second sequence that needs to be coded and modulated.
  • a guard interval is inserted before and after the first modulation sequence and the second modulation sequence, as shown in FIG. 4, specifically, a guard interval is inserted before the first modulation sequence, and a first modulation sequence and a second modulation sequence are inserted.
  • the guard interval is inserted after the second modulation.
  • the guard interval can be composed of 64 symbols.
  • guard interval After the guard interval is inserted, two consecutive 448-bit modulation sequences with guard intervals are inserted, and the guard interval and the two modulation sequences together form a frame, which can be used for transmission.
  • the present application performs a one-time code modulation mapping on the EDMG Header sequence, and does not need to divide the bits into multiple 64 bits in order to follow the 802.11ad scheme. Thus, frame retransmission can be realized, and the performance of the transmission frame can be improved.
  • the simulation results show that the technical solution of the present application can also improve the gain compared to the scheme of using 802.11ad. For example, when transmitting 128 bits, the gain can be increased by 1 dB.
  • the receiver can receive the frame and demodulate the frame.
  • the receiver can perform demodulation decoding of the frame according to the following manner: (n) and y(n) are respectively demodulated to obtain LLR x (n) and LLR y (n); LLR x (n) and LLR y (n) are combined to obtain four sequences LLR 1 (n), LLR 2 (n), LLR 3 (n), LLR 4 (n), the four sequences are constructed as follows:
  • n 0,1,2,...,127;
  • n 0,1,2,...,303;
  • LLR' [LLR 1 , LLR 2 , 0 1 , 0 2 ,...,0 208 ,LLR 3 ,LLR 4 ,]; input the sequence LLR' into the LDPC decoder to obtain 336 bit estimates b 1 , b 2 ,..., b 336 , where the first 128 bits are estimated An estimate of 128 control bits of the EDMG Header sequence is sent for the transmitter.
  • FIG. 8 is a schematic structural diagram of an apparatus for transmitting a frame according to an embodiment of the present application.
  • the apparatus of Figure 8 can perform the methods performed by the transmitters in the various flows of Figures 2 and 6.
  • the apparatus 10 of FIG. 8 includes an acquisition unit 11, a filling unit 12, an encoding unit 13, a construction unit 14, a modulation unit 15, a processing and transmission unit 16.
  • the obtaining unit 11 is configured to acquire an initial enhanced directional multi-giant bit EDMG Header sequence.
  • the initial EDMG Header sequence includes N control bits, and N is a positive integer.
  • the padding unit 12 is configured to perform a padding operation on the initial EDMG Header sequence acquired by the acquiring unit to obtain a padding sequence.
  • the padding sequence includes N information bits and L padding bits, and N information bits are N control bits or N information bits are obtained by scrambling N control bits.
  • the encoding unit 13 is configured to perform 1/2 low-density parity check code LDPC encoding on the padding sequence obtained by the padding unit to obtain a coding sequence.
  • the code sequence includes N information bits, L padding bits, and N+L parity bits generated by the code, where L is a positive integer.
  • the constructing unit 14 is configured to form, by the coding unit, N information bits and all parity bits in the coding sequence to form a first sequence, and obtain a second sequence according to the first sequence. Wherein the first sequence and the second sequence have the same length.
  • the modulating unit 15 is configured to separately modulate the first sequence and the second sequence obtained by the constructing unit to obtain a first modulation sequence and a second modulation sequence.
  • the processing and transmission unit 16 is configured to insert a guard interval GI between the first modulation sequence and the second modulation sequence obtained by the modulation unit, and obtain a coded modulated EDMG Header sequence according to the sequence after the guard interval is inserted, and the coded modulated The EDMG Header sequence is combined with the data to be transmitted to obtain a frame and transmit the frame.
  • the present invention performs unified 1/2 LDPC encoding on the control bits in the EDMG Header sequence, and directly obtains two sequences including all control bits according to the encoded coding sequence, and then performs the two sequences.
  • the frame is modulated and transmitted, and the transmission performance of the frame can be improved by such a retransmission design.
  • the apparatus for transmitting a frame according to the present application may refer to a method flow corresponding to the transmission frame of the present application, and each unit/module in the apparatus and the other operations and/or functions described above are respectively implemented in order to implement a corresponding flow in the method, for the sake of brevity. I will not repeat them here.
  • FIG. 9 is a schematic structural diagram of an apparatus for transmitting a frame according to another embodiment of the present invention.
  • the apparatus of Figure 9 can perform the methods performed by the transmitters in the various flows of Figures 3 and 7.
  • the apparatus 20 of FIG. 9 includes an acquisition unit 21, a filling unit 22, an encoding unit 23, a construction unit 24, a modulation unit 25, a processing and transmission unit 26.
  • the obtaining unit 21 is configured to acquire an initial enhanced directional multi-giant bit EDMG Header sequence.
  • the initial EDMG Header sequence includes N control bits, and N is a positive integer.
  • the padding unit 22 is configured to perform a padding operation on the initial EDMG Header sequence acquired by the acquiring unit to obtain a padding sequence.
  • the padding sequence includes N information bits and L padding bits, and N information bits are N control bits or N information bits are obtained by scrambling N control bits.
  • the encoding unit 23 is configured to perform 1/2 low-density parity check code LDPC encoding on the padding sequence obtained by the padding unit to obtain a coding sequence.
  • the code sequence includes N information bits, L padding bits, and N+L parity bits generated by the code, where L is a positive integer.
  • the constructing unit 24 is configured to form the first sequence by the N information bits and the first partial parity bits in the coding sequence obtained by the coding unit, and the N information bits and the second partial parity in the coding sequence obtained according to the coding unit.
  • the bit is obtained to obtain a second sequence.
  • the lengths of the first sequence and the second sequence are the same, and the bits included in the first partial parity bit and the second partial parity bit are not all the same.
  • the modulating unit 25 is configured to separately modulate the first sequence and the second sequence obtained by the constructing unit to obtain a first modulation sequence and a second modulation sequence.
  • the processing and transmission unit 26 is configured to insert a guard interval GI between the first modulation sequence and the second modulation sequence obtained by the modulation unit, and obtain a coded modulated EDMG Header sequence according to the sequence after the guard interval is inserted, and the coded modulated The EDMG Header sequence is combined with the data to be transmitted to obtain a frame and transmit the frame.
  • the present invention performs unified 1/2 LDPC encoding on the control bits in the EDMG Header sequence, and directly obtains two sequences including all control bits according to the encoded coding sequence, and then performs the two sequences.
  • the frame is modulated and transmitted, and the transmission performance of the frame can be improved by such a retransmission design.
  • the apparatus for transmitting a frame according to the present application may refer to a method flow corresponding to the transmission frame of the present application, and each unit/module in the apparatus and the other operations and/or functions described above are respectively implemented in order to implement a corresponding flow in the method, for the sake of brevity. I will not repeat them here.
  • FIG. 10 is a schematic structural diagram of an apparatus for transmitting a frame according to another embodiment of the present invention.
  • the apparatus of Figure 10 can perform the methods performed by the transmitters in the various flows of Figures 2 and 6.
  • the apparatus 30 of FIG. 10 includes a transmitter 31, a processor 32, and a memory 33.
  • Processor 32 controls the operation of device 30 and can be used to process signals.
  • Memory 33 can include read only memory and random access memory and provides instructions and data to processor 32.
  • the various components of device 30 are coupled together by a bus system 34, which in addition to the data bus includes a power bus, a control bus, and a status signal bus. However, for clarity of description, various buses are labeled as bus system 34 in the figure.
  • processor 32 may be implemented by processor 32.
  • each step of the above method may be completed by an integrated logic circuit of hardware in the processor 32 or an instruction in the form of software.
  • the processor 32 can be a general purpose processor, a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component that can implement or perform the disclosure in this application.
  • a general purpose processor can be a microprocessor or any conventional processor or the like.
  • the steps of the method disclosed in connection with the present application may be directly embodied by hardware processor execution or by a combination of hardware and software modules in a processor.
  • the software module can be located in a conventional storage medium such as random access memory, flash memory, read only memory, programmable read only memory or electrically erasable programmable memory, registers, and the like.
  • the storage medium is located in the memory 33, and the processor 32 reads the information in the memory 33 and, in conjunction with its hardware, performs the steps of the above method.
  • the processor 32 may obtain an initial EDMG Header sequence, perform a padding operation on the initial EDMG Header sequence to obtain a padding sequence, and perform a 1/2 low-density parity check code LDPC encoding on the padding sequence to obtain a coding sequence;
  • the N information bits and all the check bits form a first sequence, and obtain a second sequence according to the first sequence; modulate the first sequence to obtain a first modulation sequence, and modulate the second sequence to obtain a second modulation sequence And obtaining a frame according to the first modulation sequence and the second modulation sequence.
  • the initial EDMG Header sequence includes N control bits, N is a positive integer, and the padding sequence includes N information bits and L.
  • the padding bits, the N information bits are N control bits or the N information bits are obtained by scrambling N control bits, and the coding sequence includes N information bits, L padding bits, and N+L generated by the coding.
  • the check bit, L is a positive integer, and the first sequence and the second sequence have the same length.
  • the processor 32 may further insert a guard interval GI between the first modulation sequence and the second modulation sequence, and obtain a coded modulated EDMG Header sequence according to the sequence after the guard interval is inserted, and encode and modulate the EDMG Header sequence.
  • the transmitted data is combined to get the frame.
  • the transmitter 31 can transmit the above frame.
  • the present invention performs unified 1/2 LDPC encoding on the control bits in the EDMG Header sequence, and directly obtains two sequences including all control bits according to the encoded coding sequence, and then performs the two sequences.
  • the frame is modulated and transmitted, and the transmission performance of the frame can be improved by such a retransmission design.
  • the apparatus for transmitting frames according to the present application may refer to the method flow of the transmission frame of the present application, and the respective units/modules in the apparatus and the other operations and/or functions described above are respectively implemented in order to implement the corresponding processes in the method, for the sake of brevity. This will not be repeated here.
  • FIG. 11 is a schematic structural diagram of an apparatus for transmitting a frame according to another embodiment of the present invention.
  • the apparatus of Figure 11 can perform the methods performed by the transmitters in the various flows of Figures 3 and 7.
  • the apparatus 40 of FIG. 11 includes a transmitter 41, a processor 42, and a memory 43.
  • Processor 42 controls the operation of device 40 and can be used to process signals.
  • Memory 43 may include read only memory and random access memory and provides instructions and data to processor 42.
  • the various components of device 40 are coupled together by a bus system 44, which in addition to the data bus includes a power bus, a control bus, and a status signal bus. However, for clarity of description, various buses are labeled as bus system 44 in the figure.
  • processor 42 may be implemented by processor 42.
  • each step of the above method may be completed by an integrated logic circuit of hardware in the processor 42 or an instruction in the form of software.
  • the processor 42 can be a general purpose processor, a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component that can implement or perform the disclosure in this application.
  • a general purpose processor can be a microprocessor or any conventional processor or the like.
  • the steps of the method disclosed in connection with the present application may be directly embodied by hardware processor execution or by a combination of hardware and software modules in a processor.
  • the software module can be located in a conventional storage medium such as random access memory, flash memory, read only memory, programmable read only memory or electrically erasable programmable memory, registers, and the like.
  • the storage medium is located in the memory 43, and the processor 42 reads the information in the memory 43 and performs the steps of the above method in combination with its hardware.
  • the processor 42 may obtain an initial EDMG Header sequence, perform a padding operation on the initial EDMG Header sequence to obtain a padding sequence, and perform a 1/2 low-density parity check code LDPC encoding on the padding sequence to obtain a coding sequence;
  • the N information bits and the first partial parity bits form a first sequence, and obtain a second sequence according to the N information bits and the second partial parity bits in the coding sequence; and modulating the first sequence to obtain a first modulation sequence, And modulating the second sequence to obtain a second modulation sequence; obtaining a frame according to the first modulation sequence and the second modulation sequence.
  • the initial EDMG Header sequence includes N control bits, N is a positive integer, the padding sequence includes N information bits and L padding bits, N information bits are N control bits or N information bits are N control
  • the bit sequence is scrambled, and the code sequence includes N information bits, L padding bits, and N+L check bits generated by the code, L is a positive integer, and the first sequence and the second sequence have the same length, the first part is The check bits and the second partial check bits include not all the same check bits.
  • the processor 22 may further insert a guard interval GI between the first modulation sequence and the second modulation sequence, and according to the insertion
  • the sequence after entering the guard interval obtains the coded modulated EDMG Header sequence, and combines the coded modulated EDMG Header sequence with the data to be transmitted to obtain a frame.
  • the transmitter 21 can transmit the above frame.
  • the present invention performs unified 1/2 LDPC encoding on the control bits in the EDMG Header sequence, and directly obtains two sequences including all control bits according to the encoded coding sequence, and then performs the two sequences.
  • the frame is modulated and transmitted, and the transmission performance of the frame can be improved by such a retransmission design.
  • the apparatus for transmitting frames according to the present application may refer to the method flow of the transmission frame of the present application, and the respective units/modules in the apparatus and the other operations and/or functions described above are respectively implemented in order to implement the corresponding processes in the method, for the sake of brevity. This will not be repeated here.
  • the size of the sequence numbers of the above processes does not mean the order of execution, and the order of execution of each process should be determined by its function and internal logic, and should not be implemented in the present application.
  • the process constitutes any limitation.
  • RAM random access memory
  • ROM read-only memory
  • EPROM electrically programmable read-only memory
  • EEPROM electrically erasable Electrically Erasable Programmable Read-Only Memory
  • CD-ROM Compact Disc Read-Only Memory
  • the disclosed systems, devices, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

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Abstract

本申请提供了一种传输帧的方法和装置。该方法包括对获取的EDMG Header序列进行填充操作、1/2 LDPC编码，并根据编码得到的编码序列构造第一序列和第二序列，使得第一序列和第二序列中都包括EDMG Header序列中所有比特，并包括部分或全部的编码序列中的奇偶校验编码比特，且使得第一序列和第二序列的长度相同，这样在对第一序列和第二序列进行调制并调制后的两个序列中间***保护间隔后得到帧，并传输该帧。这样能够提高帧的传输性能。

Description

传输帧的方法和装置
本申请要求于2016年6月29日提交中国专利局、申请号为201610495415.X、发明名称为“传输帧的方法和装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信领域，并且更具体地，涉及传输帧的方法和装置。
背景技术
802.11系列标准对无线局域网络(Wireless Local Area Networks，WLAN)的标准化使得WLAN技术的成本大大降低。无线保真(Wireless Fidelity，Wi-Fi)是一个无线网路通信技术的品牌，由Wi-Fi联盟所持有，目的是改善基于802.11标准的无线网络产品之间的互通性，使用802.11系列协议的无线局域网可以称为Wi-Fi网络。
目前，802.11标准，历经802.11a,802.11b,802.11g,802.11n和802.11ac等各个版本，技术发展越来越成熟。802.11ad是电气和电子工程师协会(Institute of Electrical and Electronics Engineers，IEEE)802.11(或称为WLAN，无线局域网)***中的一个分支，工作于60GHz高频段，单载波调制是802.11ad技术的一种实现方法。802.11ad基于单载波的帧头(Header)的设计可以传输64比特的Header序列。
目前，802.11ay的标准讨论中确定的帧结构相比802.11ad增加了增强方向性多吉比特帧头(enhanced directional multi-gigabit Header，EDMG Header)字段，用于指示802.11ay中的控制信令。现有的EDMG Header设计方案为了沿用802.11ad中的设计，将EDMG Header序列中填充比特之后，划分为多个64比特的序列，以沿用802.11ad中Header的设计进行帧的传输，但这种方法以每个64比特为单元进行编码调制发送，传输性能有限制，尤其在长距离的传输条件下，不能满足传输的性能要求。
发明内容
本申请提供一种传输帧的方法和装置，能够提高帧的传输性能。
第一方面，提供了一种传输帧的方法，包括：获取初始的增强方向性多吉比特帧头EDMG Header序列，其中，所述EDMG Header序列包括N个控制比特，N为正整数；对所述初始的EDMG Header序列进行填充操作，得到填充序列，其中，所述填充序列包括N个信息比特和L个填充比特，所述N个信息比特为所述N个控制比特或所述N个信息比特为对所述N个控制比特进行加扰得到的；对所述填充序列进行1/2低密度奇偶校验码(Low Density Parity Check Code，LDPC)编码，得到编码序列，其中，所述编码序列包括N个信息比特、L个填充比特和编码产生的N+L个奇偶校验比特，L为正整数；将所述编码序列中的N个信息比特和全部的奇偶校验比特构成第一序列，并根据所述第一序列得到第二序列，其中，所述第一序列和所述第二序列的长度相同；对所述第一序列进行调制得到第一调制序列，并对所述第二序列进行调制得到第二调制序列；在所述第一调制序列和所述第二调制序列之间***保护间隔GI，根据***保护间隔后的序列得到编码调制后的EDMG Header序列，所述编码调制后的EDMG Header序列和待发送的 数据结合得到帧，并传输所述帧。
本申请通过对EDMG Header序列中的控制比特在进行填充操作后进行统一的1/2LDPC编码，并根据编码后的编码序列直接得到都包括所有控制比特的两个序列，再对这两个序列进行调制得到帧并传输该帧，通过这样的重传设计可以提高帧的传输性能。
在本发明的一个实施例中，可以直接对EDMG Header序列中的比特进行填充，相应地，填充序列包括N个信息比特和L个填充比特，N个信息比特可以为EDMG Header序列中的N个控制比特。在本发明的另一实施例中，也可以在对EDMG Header序列进行填充操作之前，先对EDMG Header序列进行加扰处理，然后对加扰处理后的序列进行填充操作，相应地，填充序列包括N个信息比特和L个填充比特，N个信息比特可以为对N个控制比特进行加扰得到的。
本发明一个实施例中，EDMG Header序列包括的N个控制比特中可以有部分的循环冗余校验(Cyclic Redundancy Check,CRC)比特，CRC比特数目可以为16或32等。
本申请通过构造出两个都包括N个信息比特的序列实现帧的重传，这样的设计更能满足长距离的帧传输的需要，提高传输性能。
结合第一方面，在第一方面的一种实现方式中，所述编码序列的长度为672，所述第一序列和所述第二序列的长度都为448，N+L＝336。
在本发明的一个实施例中，编码序列的长度可以为672，即编码序列包括672个比特。第一序列和第二序列的长度相同，都为448，也就是说，本发明一个实施例中可以由编码序列直接构造出两个都包括448比特的序列，在两个序列之间***保护间隔，而不需要由编码序列构造出两个224比特的序列，然后将两个224比特的序列组合成448比特的序列，这样进行统一编码能够提高传输帧的性能。
在本发明的一个实施例中，对信息比特进行统一编码并由编码后的编码序列直接构造出两个448比特的序列，实现信令的重传，而不需要将编码后的序列分为多个64比特的序列，并对每个64比特的序列采用802.11ad的方法，这样能够实现信令的重传，可以提高传输帧的性能，提高传输准确性。
结合第一方面及其上述实现方式，在第一方面的另一种实现方式中，当N＝112时，所述根据所述第一序列得到所述第二序列包括：对所述第一序列进行异或操作，得到所述第二序列；或者，对所述第一序列进行交织处理，得到所述第二序列。
例如，N＝112时，假设EDMG Header序列为b1，b2，…，b112，对序列b1，b2，…，b112进行加扰处理后的序列为q1，q2，…，q112。填充序列为q1，q2，…，q112，01，02，…，0224，编码序列为q1，q2，…，q112，01，02，…，0224，p1，p2，…，p336。其中，p1，p2，…，p336为1/2LDPC编码产生的奇偶校验比特序列。由上述编码序列构造的第一序列可以为q1，q2，…，q112，p1，p2，…，p336，第二序列可以是对第一序列进行异或操作或交织处理得到的。
在本发明的一个实施例中，如果需要传输的EDMG Header序列的长度小于112，可以对EDMG Header序列进行填充操作，使得EDMG Header序列的长度达到112，并使用上述N＝112时传输帧的方法。
结合第一方面及其上述实现方式，在第一方面的另一种实现方式中，所述对所述第一序列进行异或操作，得到所述第二序列包括：对所述第一序列采用一组伪随机序列进行异或操作，得到所述第二序列；或者，对所述第一序列采用序列{0,1,0,1…0,1}或序列 {1,0,1…1,0}进行异或操作，得到所述第二序列。
结合第一方面及其上述实现方式，在第一方面的另一种实现方式中，所述对所述第一序列进行调制得到第一调制序列，并对所述第二序列进行调制得到第二调制序列包括：对所述第一序列进行π/2BPSK调制或BPSK调制，得到第一调制序列；对所述第二序列进行π/2BPSK调制或BPSK调制，得到第二调制序列。
第二方面，提供了一种传输帧的方法，包括：获取初始的增强方向性多吉比特帧头EDMG Header序列，其中，所述初始的EDMG Header序列包括N个控制比特，N为正整数；对所述初始的EDMG Header序列进行填充操作，得到填充序列，其中，所述填充序列包括N个信息比特和L个填充比特，所述N个信息比特为所述N个控制比特或所述N个信息比特为对所述N个控制比特进行加扰得到的；对所述填充序列进行1/2低密度奇偶校验码LDPC编码，得到编码序列，其中，所述编码序列包括N个信息比特、L个填充比特和编码产生的N+L个奇偶校验比特，L为正整数；将所述编码序列中的N个信息比特和第一部分奇偶校验比特构成所述第一序列，并根据所述编码序列中的N个信息比特和第二部分奇偶校验比特得到所述第二序列，其中，所述第一序列和所述第二序列的长度相同，所述第一部分奇偶校验比特和所述第二部分奇偶校验比特包括的比特不全部相同；对所述第一序列进行调制得到第一调制序列，并对所述第二序列进行调制得到第二调制序列；在所述第一调制序列和所述第二调制序列之间***保护间隔GI，根据***保护间隔后的序列得到编码调制后的EDMG Header序列，所述编码调制后的EDMG Header序列和待发送的数据结合得到帧，并传输所述帧。
结合第二方面，在第二方面的一种实现方式中，所述编码序列的长度为672，所述第一序列和所述第二序列的长度都为448，N+L＝336。
结合第二方面及其上述实现方式，在第二方面的另一种实现方式中，当N＞112时，所述根据所述编码序列中的N个信息比特和第二部分奇偶校验比特得到所述第二序列包括：将所述编码序列中的N个信息比特和第二部分奇偶校验比特构成所述第二序列。
在本发明的一个实施例中如果N＞112，N个信息比特和N+L个奇偶校验比特之和大于448，这时直接由编码序列中的信息比特和奇偶校验比特构造的序列的长度大于448，需要舍弃一部分比特，使得构造所得的序列长度为448。即，N＞112时，可以由N个信息比特和第一部分奇偶校验比特构成448比特的第一序列，并根据N个信息比特和第二部分奇偶校验比特构造448比特的第二序列，这样得到的第一序列和第二序列中都包括N个信息比特，对信息比特进行了重传，能够提高传输帧的准确性，提高传输性能。
如果N＞112，假设EDMG Header序列为b1，b2，…，bN，对序列b1，b2，…，bN进行加扰处理后的序列为q1，q2，…，qN。填充序列为q1，q2，…，qN，01，02，…，0336-N，编码序列为q1，q2，…，qN，01，02，…，0336-N，p1，p2，…，p336。其中，p1，p2，…，p336为1/2LDPC编码产生的奇偶校验比特序列。由上述编码序列构造的第一序列可以为q1，q2，…，qN，p1，p2，…，p448-N，由上述编码序列构造的第三序列可以是q1，q2，…，qN，p1，p2，…p560-2N，p448-N+1，…p336，第二序列可以是对第三序列进行异或操作或交织处理得到的。
特别地，N＝128时，第一序列可以为q1，q2，…，q128，p1，p2，…，p320，第三序列可以是q1，q2，…，q128，p1，p2，…p304，p321，…p336。
结合第二方面及其上述实现方式，在第二方面的另一种实现方式中，当N＞112时， 所述根据所述编码序列中的N个信息比特和第二部分奇偶校验比特得到所述第二序列包括：将所述编码序列中的N个信息比特和第二部分奇偶校验比特构成第三序列；对所述第三序列进行异或操作或交织处理，得到所述第二序列。
结合第二方面及其上述实现方式，在第二方面的另一种实现方式中，所述对所述第三序列进行异或操作或交织处理，得到所述第二序列包括：对所述第三序列采用一组伪随机序列进行异或操作，得到所述第二序列；或者，对所述第三序列采用序列{0,1,0,1…0,1}或序列{1,0,1…1,0}进行异或操作，得到所述第二序列。
结合第二方面及其上述实现方式，在第二方面的另一种实现方式中，所述第一部分奇偶校验比特和所述第二部分奇偶校验比特构成全部的奇偶校验比特。
在本发明的一个实施例中，第一部分奇偶校验比特构成第一集合，第二部分奇偶校验比特构成第二集合，第一集合和第二集合的并集构成全部的奇偶校验比特。这样在构造第一序列和第二序列时充分利用奇偶校验比特，可以提高传输帧的传输性能。
结合第二方面及其上述实现方式，在第二方面的另一种实现方式中，所述第一部分奇偶校验比特和所述第二部分奇偶校验比特中的公共比特数大于阈值，所述阈值为预设值，或者，所述阈值是由全部奇偶校验比特的数目确定的。
在本发明的一个实施例中，第一部分奇偶校验比特构成第一集合，第二部分奇偶校验比特构成第二集合，第一集合和第二集合的交集构成第三集合，第三集合中的比特个数越接近全部的奇偶校验比特数，构造序列时舍弃的奇偶校验比特数就越少，传输帧时的性能可以越好。
在本发明的一个实施例中，在所述第一调制序列和所述第二调制序列之间***保护间隔，并在所述第一调制序列之前和所述第二调制序列之后也都***保护间隔，得到所述EDMG Header，所述EDMG Header和待发送的数据结合得到所述帧，并传输所述帧。
结合第二方面及其上述实现方式，在第二方面的另一种实现方式中，所述对所述第一序列进行调制得到第一调制序列，并对所述第二序列进行调制得到第二调制序列包括：对所述第一序列进行π/2BPSK调制或BPSK调制，得到第一调制序列；对所述第二序列进行π/2BPSK调制或BPSK调制，得到第二调制序列。
换句话说，本申请中对第一序列和第二序列的调制方式可以为BPSK调制或π/2BPSK调制。
第三方面，提供了一种传输帧的装置，包括：获取单元，用于获取初始的增强方向性多吉比特帧头EDMG Header序列，其中，所述初始的EDMG Header序列包括N个控制比特，N为正整数；填充单元，用于对获取单元获取的所述初始的EDMG Header序列进行填充操作得到填充序列，其中，所述填充序列包括N个信息比特和L个填充比特，所述N个信息比特为所述N个控制比特或所述N个信息比特为对所述N个控制比特进行加扰得到的；编码单元，用于对所述填充单元得到的所述填充序列进行1/2低密度奇偶校验码LDPC编码，得到编码序列，其中，所述编码序列包括N个信息比特、L个填充比特和编码产生的N+L个奇偶校验比特，L为正整数；构造单元，用于将所述编码单元得到的所述编码序列中的N个信息比特和全部的奇偶校验比特构成第一序列，并根据所述第一序列得到第二序列，其中，所述第一序列和所述第二序列的长度相同；调制单元，用于对所述构造单元得到的所述第一序列和第二序列分别进行调制得到第一调制序列和第二调制序列；处理和传输单元，用于在所述调制单元得到的所述第一调制序列和 所述第二调制序列之间***保护间隔GI，并根据***保护间隔后的序列得到编码调制后的EDMG Header序列，所述编码调制后的EDMG Header序列和待发送的数据结合得到帧，并传输所述帧。
本申请通过对EDMG Header序列中的控制比特在进行填充操作后进行统一的1/2LDPC编码，并根据编码后的编码序列直接得到都包括所有控制比特的两个序列，再对这两个序列进行调制得到帧并传输该帧，通过这样的重传设计可以提高帧的传输性能。
结合第三方面，在第三方面的一种实现方式中，所述编码序列的长度为672，所述第一序列和所述第二序列的长度都为448，N+L＝336。
结合第三方面及其上述实现方式，在第三方面的另一种实现方式中，当N＝112时，所述构造单元具体用于对所述第一序列进行异或操作得到所述第二序列，或者，对所述第一序列进行交织处理得到所述第二序列。
结合第三方面及其上述实现方式，在第三方面的另一种实现方式中，所述构造单元具体用于对所述第一序列采用一组伪随机序列进行异或操作得到所述第二序列；或者，对所述第一序列采用序列{0,1,0,1…0,1}或序列{1,0,1…1,0}进行异或操作得到所述第二序列。
结合第三方面及其上述实现方式，在第三方面的另一种实现方式中，所述调制单元具体用于对所述第一序列进行π/2BPSK调制或BPSK调制，得到第一调制序列，并对所述第二序列进行π/2BPSK调制或BPSK调制，得到第二调制序列。
根据本申请第三方面的传输帧的装置可以参照本申请的第一方面中的传输帧的方法流程，并且，该装置中的各个单元/模块和上述其他操作和/或功能分别为了实现第一方面所示方法中的相应流程，为了简洁，在此不再赘述。
第四方面，提供了一种传输帧的装置，包括：获取单元，用于获取初始的增强方向性多吉比特帧头EDMG Header序列，其中，所述初始的EDMG Header序列包括N个控制比特，N为正整数；填充单元，用于对获取单元获取的所述初始的EDMG Header序列进行填充操作得到填充序列，其中，所述填充序列包括N个信息比特和L个填充比特，所述N个信息比特为所述N个控制比特或所述N个信息比特为对所述N个控制比特进行加扰得到的；编码单元，用于对所述填充单元得到的所述填充序列进行1/2低密度奇偶校验码LDPC编码，得到编码序列，其中，所述编码序列包括N个信息比特、L个填充比特和编码产生的N+L个奇偶校验比特，L为正整数；构造单元，用于将所述编码单元得到的所述编码序列中的N个信息比特和第一部分奇偶校验比特构成所述第一序列，并根据所述编码单元得到的所述编码序列中的N个信息比特和第二部分奇偶校验比特得到所述第二序列，其中，所述第一序列和所述第二序列的长度相同，所述第一部分奇偶校验比特和所述第二部分奇偶校验比特包括的比特不全部相同；调制单元，用于对所述构造单元得到的所述第一序列和第二序列分别进行调制得到第一调制序列和第二调制序列；处理和传输单元，用于在所述调制单元得到的所述第一调制序列和所述第二调制序列之间***保护间隔GI，并根据***保护间隔后的序列得到编码调制后的EDMG Header序列，所述编码调制后的EDMG Header序列和待发送的数据结合得到帧，并传输所述帧。
结合第四方面，在第四方面的一种实现方式中，所述编码序列的长度为672，所述第一序列和所述第二序列的长度都为448，N+L＝336。
结合第四方面及其上述实现方式，在第四方面的另一种实现方式中，当N＞112时， 所述构造单元具体用于将所述编码序列中的N个信息比特和第二部分奇偶校验比特构成所述第二序列。
结合第四方面及其上述实现方式，在第四方面的另一种实现方式中，当N＞112时，所述构造单元具体用于将所述编码序列中的N个信息比特和第二部分奇偶校验比特构成第三序列，对所述第三序列进行异或操作或交织处理得到所述第二序列。
结合第四方面及其上述实现方式，在第四方面的另一种实现方式中，所述构造单元具体用于对所述第三序列采用一组伪随机序列进行异或操作，得到所述第二序列，或者，对所述第三序列采用序列{0,1,0,1…0,1}或序列{1,0,1…1,0}进行异或操作，得到所述第二序列。
结合第四方面及其上述实现方式，在第四方面的另一种实现方式中，所述第一部分奇偶校验比特和所述第二部分奇偶校验比特构成全部的奇偶校验比特。
结合第四方面及其上述实现方式，在第四方面的另一种实现方式中，所述第一部分奇偶校验比特和所述第二部分奇偶校验比特中的公共比特数大于阈值，所述阈值为预设值，或者，所述阈值是由全部的奇偶校验比特的数目确定的。
在本发明的一个实施例中，处理和传输单元具体用于在第一调制序列和第二调制序列之间***保护间隔，并在第一调制序列之前和第二调制序列之后也都***保护间隔，得到编码调制后的EDMG Header序列，编码调制后的EDMG Header序列和待发送的数据结合得到帧，并传输帧。
结合第四方面及其上述实现方式，在第四方面的另一种实现方式中，所述调制单元具体用于对所述第一序列进行π/2BPSK调制或BPSK调制，得到第一调制序列，并对所述第二序列进行π/2BPSK调制或BPSK调制，得到第二调制序列。
根据本申请第四方面的传输帧的装置可以参照本申请的第二方面中的传输帧的方法流程，并且，该装置中的各个单元/模块和上述其他操作和/或功能分别为了实现第二方面所示方法中的相应流程，为了简洁，在此不再赘述。
第五方面，提供了一种传输帧的方法，包括接收如第一方面所述的帧，并对所述帧进行解调解码。
根据本申请的传输帧的方法中的帧的构成方式可以参照第一方面中的帧的构成方式，为避免重复，在此不再详细赘述。
第六方面，提供了一种传输帧的方法，包括接收如第二方面所述的帧，并对所述帧进行解调解码。
根据本申请的传输帧的方法中的帧的构成方式可以参照第二方面中的帧的构成方式，为避免重复，在此不再详细赘述。
附图说明
图1是可应用本申请的通信***的场景示意图。
图2是本发明一个实施例的传输帧的方法的示意性流程图。
图3是本发明另一实施例的传输帧的方法的示意性流程图。
图4是本发明一个实施例的802.11ay协议中帧结构的示意图。
图5是本发明一个实施例的802.11ay协议中帧结构中EDMG Header字段的示意图。
图6是本发明另一实施例的传输帧的方法的示意性流程图。
图7是本发明另一实施例的传输帧的方法的示意性流程图。
图8是本发明一个实施例的传输帧的装置的示意性结构图。
图9是本发明另一实施例的传输帧的装置的示意性结构图。
图10是本发明另一实施例的传输帧的装置的示意性结构图。
图11是本发明另一实施例的传输帧的装置的示意性结构图。
具体实施方式
下面将结合本申请中的附图，对本申请中的技术方案进行清楚、完整地描述。
图1是可应用本申请的通信***的场景示意图。图1的通信***包括一个AP和三个STA。例如，图1中的STA1、STA2和STA3。AP可以与STA1、STA2和STA3进行通信。该***中，AP可以调度多个STA进行信令传输与解调。需要说明的是，STA的数目不做限制，本发明仅以三个为例进行示例性说明。
本发明的技术方案，可以应用于各种需要传输帧的通信***，例如，应用多用户多输入多输出(Multi-User multiple input multiple output，MU-MIMO)技术的WLAN，Wi-Fi等。
接入点(Access Point，AP)，也称之为无线访问接入点或热点等。AP是移动用户进入有线网络的接入点，主要部署于家庭、大楼内部以及园区内部，典型覆盖半径为几十米至上百米，当然，也可以部署于户外。AP相当于一个连接有线网和无线网的桥梁，其主要作用是将各个无线网络客户端连接到一起，然后将无线网络接入以太网。目前AP主要采用的标准为电气和电子工程师协会(Institute of Electrical and Electronics Engineers，IEEE)802.11系列。具体地，AP可以是带有Wi-Fi芯片的终端设备或者网络设备。可选地，AP可以为支持802.11ay制式的设备，进一步可选地，该AP还可以为支持802.11ay、802.11ad、802.11ac、802.11n、802.11g、802.11b及802.11a等多种WLAN制式的设备。
站点(Station，STA)，可以是无线通讯芯片、无线传感器或无线通信终端。例如：支持Wi-Fi通讯功能的移动电话、支持Wi-Fi通讯功能的平板电脑、支持Wi-Fi通讯功能的机顶盒和支持Wi-Fi通讯功能的计算机。可选地，站点可以支持802.11ay制式，进一步可选地，该站点支持802.11ay、802.11ad、802.11ac、802.11n、802.11g、802.11b及802.11a等多种WLAN制式。
图2是本发明一个实施例的传输帧的方法的示意性流程图。图2所示的方法可以由图1中的AP执行，也可以由图1中的STA执行。执行图2方法的设备可以统称为发射机。图2所示的传输帧的方法的具体流程如下：
101，获取初始的增强方向性多吉比特帧头EDMG Header序列。其中，初始的EDMG Header序列包括N个控制比特，N为正整数。
初始的EDMG Header序列中的N个控制比特中可以包括CRC比特。对需要传输的比特序列进行CRC校验和加扰处理的顺序可以互换，加扰和/或CRC校验后可以得到初始的EDMG Header序列。本申请中，也可以不对需要传输的比特序列进行加扰处理，CRC校验后得到的序列作为初始的EDMG Header序列。
102，对初始的EDMG Header序列进行填充操作得到填充序列。其中，填充序列包括N个信息比特和L个填充比特，N个信息比特为N个控制比特或N个信息比特为对N个控制比特进行加扰得到的。
本申请中，对初始的EDMG Header序列进行填充操作时可以在初始的EDMG Header序列的基础上填充0比特，即本申请中的填充比特可以为0比特。填充操作是为了满足后续的LDPC编码时的比特数的要求。例如，要进行1/2LDPC编码，且编码后的序列要满足672个比特，编码前的比特序列中的比特数应满足672的1/2，即336。且，1/2LDPC编码产生的奇偶校验比特数也为672的1/2，即336。
103，对填充序列进行1/2低密度奇偶校验码LDPC编码得到编码序列。其中，编码序列包括N个控制比特、L个填充比特和编码产生的N+L个奇偶校验比特，L为正整数。
如果要满足编码后的序列要满足672个比特，那么要满足N+L＝336。
104，将编码序列中的N个信息比特和全部的奇偶校验比特构成第一序列，并根据第一序列得到第二序列，第一序列和所述第二序列的长度相同。
如果N＝112，假设需要传输的比特序列EDMG Header序列为b1，b2，…，b112，对序列b1，b2，…，b112进行加扰处理后的序列为q1，q2，…，q112。填充序列为q1，q2，…，q112，01，02，…，0224，编码序列为q1，q2，…，q112，01，02，…，0224，p1，p2，…，p336。其中，p1，p2，…，p336为1/2LDPC编码产生的奇偶校验比特序列。由上述编码序列构造的第一序列可以为q1，q2，…，q112，p1，p2，…，p336，第二序列可以是对第一序列进行异或操作或交织处理得到的。
另外，本申请中可以直接将第一序列作为第二序列，而不进行异或操作或交织处理。
在本发明的一个实施例中，第一序列和第二序列的长度均为448。
本申请中的异或操可以是采用序列{0,1,0,1…0,1}或序列{1,0,1…1,0}，也可以是采用一组伪随机序列，本申请对此不做限制。
105，对第一序列进行调制得到第一调制序列，并对第二序列进行调制得到第二调制序列。
在本发明的一个实施例中，对第一序列和第二序列进行调制时可以都采用二进制相移键控(Binary Phase Shift Keying，BPSK)调制或π/2BPSK调制，进而得到相应的第一调制序列和第二调制序列。
106，在第一调制序列和第二调制序列之间***保护间隔GI，根据***保护间隔后的序列得到编码调制后的EDMG Header序列，将编码调制后的EDMG Header序列和待发送的数据结合构成帧，并传输该帧。
在第一调制序列和第二调制序列之间***保护间隔，可以区别于802.11ad对Header的设计。802.11ad的设计中，构造出两个224比特的序列，并将两个224比特的序列直接组合构成一个448比特序列，而并未在两个224的比特序列中***保护间隔，再将这个448比特序列进行倒序，构成另一个448比特的序列，并在两个448比特的序列之间***保护间隔，得到编码调制后的EDMG Header序列，将编码调制后的EDMG Header序列和待发送的数据结合构成帧并传输该帧。而本申请是直接构造得到448比特，实现方式更简单。
另外，本发明一个实施例中，还可以在第一调制序列和第二调制序列的前后都***保护间隔，这样得到的帧进行传输可以提高传输帧的可靠性。
本申请通过对EDMG Header序列中的控制比特在进行填充操作后进行统一的1/2LDPC编码，并根据编码后的编码序列直接得到都包括所有控制比特的两个序列，再对这两个序列进行调制得到帧并传输该帧，通过这样的重传设计可以提高帧的传输性能。
在本发明的一个实施例中，图1的方法可以由单载波***的发射机执行，接收机在收到帧后，可以将接收到的帧进行分块，删除每一块中的循环前缀，并对删除循环前缀后的数据组进行傅里叶变换，将其变换到频域。再对变换到频域后的数据利用频域信道信息进行频域均衡处理，将完成频域均衡后的数据通过傅里叶逆变换变回时域，以对时域信号进行解调解码处理。
具体地，接收机对帧解调解码时，可以对接收的两个长度为448的序列分别进行解调，得到两个对应的对数似然比，并将两个对数似然比合并得到一个或多个序列，并将一个或多个序列合并，并在中间增加比特0，使得合并后的序列长度为672，然后对长度为672的序列进行LDPC解码得到336个比特估值，并从336个比特估值中确定发射机发送的EDMG Header序列的N个控制比特的估值。
图3是本发明另一实施例的传输帧的方法的示意性流程图。图3所示的方法可以由图1中的AP执行，也可以由图1中的STA执行。执行图3方法的设备可以统称为发射机。图3所示的传输帧的方法的具体流程如下：
201，获取初始的增强方向性多吉比特帧头EDMG Header序列。其中，初始的EDMG Header序列包括N个控制比特，N为正整数。
初始的EDMG Header序列中的N个控制比特中可以包括CRC比特。对需要传输的比特序列进行CRC校验和加扰处理的顺序可以互换，加扰和/或CRC校验后可以得到初始的EDMG Header序列。本申请中，也可以不对需要传输的比特序列进行加扰处理，CRC校验后得到的序列作为初始的EDMG Header序列。
202，对初始的EDMG Header序列进行填充操作得到填充序列。其中，填充序列包括N个信息比特和L个填充比特，N个信息比特为N个控制比特或N个信息比特为对N个控制比特进行加扰得到的。
本申请中，对初始的EDMG Header序列进行填充操作时可以在初始的EDMG Header序列的基础上填充0比特。填充操作是为了满足后续的LDPC编码时的比特数的要求。例如，要进行1/2LDPC编码，且编码后的序列要满足672个比特，编码前的比特序列中的比特数应满足672的1/2，即336。且，1/2LDPC编码产生的奇偶校验比特数也为672的1/2，即336。
203，对填充序列进行1/2低密度奇偶校验码LDPC编码得到编码序列。其中，编码序列包括N个控制比特、L个填充比特和编码产生的N+L个奇偶校验比特，L为正整数。
如果要满足编码后的序列要满足672个比特，那么要满足N+L＝336。
204，将编码序列中的N个信息比特和第一部分奇偶校验比特构成第一序列，并根据编码序列中的N个信息比特和第二部分奇偶校验比特得到第二序列，其中，第一序列和所述第二序列的长度相同，第一部分奇偶校验比特和第二部分奇偶校验比特包括的校验比特不全部相同。
如果N＞112，假设需要传输的比特序列EDMG Header序列为b1，b2，…，bN，对序列b1，b2，…，bN进行加扰处理后的序列为q1，q2，…，qN。填充序列为q1，q2，…，qN，01，02，…，0336-N，编码序列为q1，q2，…，qN，01，02，…，0336-N，p1，p2，…，p336。其中，p1，p2，…，p336为1/2LDPC编码产生的奇偶校验比特序列。由上述编码序列构造的第一序列可以为q1，q2，…，qN，p1，p2，…，p448-N，由上述编码序列构造的第三序列可以是q1，q2，…，qN，p1，p2，…p560-2N，p448-N+1，…p336，第二序 列可以是对第三序列进行异或操作或交织处理得到的。
在本发明的一个实例中，可以直接将第三序列作为第二序列，而不进行处理。只是相比对第三序列进行处理得到第二序列而言，直接将第三序列作为第二序列性能增益略差些。
在本发明的一个实施例中，第一序列和第二序列的长度均为448。
本申请中的异或操可以是采用序列{0,1,0,1…0,1}或序列{1,0,1…1,0}，也可以是采用一组伪随机序列，本申请对此不做限制。
在本发明的一个实施例中，第一部分奇偶校验比特构成第一集合，第二部分奇偶校验比特构成第二集合，第一集合和第二集合的并集构成全部的奇偶校验比特。这样在构造第一序列和第二序列时充分利用奇偶校验比特，可以提高传输帧的传输性能。第一集合和第二集合的交集构成第三集合，第三集合中的比特个数越接近全部的奇偶校验比特数，构造序列时舍弃的奇偶校验比特数就越少，传输帧时的性能可以越好。
205，对第一序列进行调制得到第一调制序列，并对第二序列进行调制得到第二调制序列。
在本发明的一个实施例中，对第一序列和第二序列进行调制时可以都采用二进制相移键控(Binary Phase Shift Keying，BPSK)调制或π/2BPSK调制，进而得到相应的第一调制序列和第二调制序列。
206，在第一调制序列和第二调制序列之间***保护间隔GI，根据***保护间隔后的序列得到编码调制后的EDMG Header序列，将编码调制后的EDMG Header序列和待发送的数据结合构成帧，并传输该帧。
在第一调制序列和第二调制序列之间***保护间隔，可以区别于802.11ad对Header的设计。802.11ad的设计中，构造出两个224比特的序列，并将两个224比特的序列直接组合构成一个448比特序列，而并未在两个224的比特序列中***保护间隔，再将这个448比特序列进行倒序，构成另一个448比特的序列，并在两个448比特的序列之间***保护间隔，得到码调制后的EDMG Header序列，将编码调制后的EDMG Header序列和待发送的数据结合构成帧并传输该帧。而本申请是直接构造得到448比特，实现方式更简单。
另外，本发明一个实施例中，还可以在第一调制序列和第二调制序列的前后都***保护间隔，这样得到的帧进行传输可以提高传输帧的可靠性。
本申请通过对EDMG Header序列中的控制比特在进行填充操作后进行统一的1/2LDPC编码，并根据编码后的编码序列直接得到都包括所有控制比特的两个序列，再对这两个序列进行调制得到帧并传输该帧，通过这样的重传设计可以提高帧的传输性能。
在本发明的一个实施例中，图1的方法可以由单载波***的发射机执行，接收机在收到帧后，可以将接收到的帧进行分块，删除每一块中的循环前缀，并对删除循环前缀后的数据组进行傅里叶变换，将其变换到频域。再对变换到频域后的数据利用频域信道信息进行频域均衡处理，将完成频域均衡后的数据通过傅里叶逆变换变回时域，以对时域信号进行解调解码处理。
具体地，接收机对帧解调解码时，可以对接收的两个长度为448的序列分别进行解调，得到两个对应的对数似然比，并将两个对数似然比合并得到一个或多个序列，并将一个或多个序列合并，并在中间增加比特0，使得合并后的序列长度为672，然后对长度 为672的序列进行LDPC解码得到336个比特估值，并从336个比特估值中确定发射机发送的EDMG Header序列的N个控制比特的估值。
图4是本发明一个实施例的802.11ay协议中帧结构的示意图。在802.11ay标准讨论中，帧结构包括短训练字段(Legacy Short Training field，STF)字段、信道估计(Channel Estimation，CE)字段、帧头(Header)字段、EDMG-Header字段和EDMG负荷(Payload)字段。本申请中可以根据EDMG-Header的设计对EDMG-Header进行编码调制等处理，并输出帧。STF用来进行同步、频偏估计、自动增益控制字段(Auto Gain Control，AGC)调整，接收机可以根据接收到的STF信号实现同步。CE用来进行信道估计，即接收机可以根据接收到的CE信号进行信道估计。Header字段用于表示指示信号，例如可以用于表示该数据帧的调制方式等。EDMG-Header用于指示802.11ay中的控制信令。EDMG Payload用于传输80.211ay中的数据。接收机可以根据接收到的Header信号和EDMG-Header信号实现对数据的解调解码编码等。本申请主要介绍EDMG-Header的设计。
图5是本发明一个实施例的802.11ay协议中帧结构中EDMG Header字段的示意图。本申请中的EDMG Header字段是由两个连续的序列***保护间隔(guard interval，GI)构成的，如图5所示。两个序列为第一调制序列和第二调制序列，且第一调制序列和第二调制序列的长度都为448，换句话说，第一调制序列包括448个符号，第二调制序列包括448个符号。本申请中，需要在第一调制序列之前、第一调制序列和第二调制序列之间、以及第二调制序列之后都***GI，GI可以是由64个符号(symbols)构成的。***保护间隔可以减少多径造成的符号间干扰(Inter-Symbol Interference，ISI)和信道间干扰(Inter-Channel Interference，ICI)。接收机还可以根据保护间隔进行信道均衡和相位偏差估计。
上文中从发射机的角度详细描述了根据本发明的实施例的传输帧的方法，下面结合图6和图7的具体实施例详细描述根据本申请的传输帧的方法。应注意，这些例子只是为了帮助本领域技术人员更好地理解本申请，而非限制本申请的范围。图6和图7分别以N＝112和N＝128为例进行示例性说明。
图6是本发明另一实施例的传输帧的方法的示意性流程图。图6的方法可以由发射机执行，这里的发射机可以为图1中的AP，也可以为图1中的STA。图6以初始的EDMG Header序列包括112个控制比特为例进行示例性说明。
初始的EDMG Header序列包括112个控制比特：b1，b2，…，b112。112个控制比特可以包括信息比特和CRC比特，信息比特和校验比特的数目不做限定，这里以96个信息比特和16个CRC校验比特为例进行示例性说明。图6中用EDMG Header(96)表示初始的EDMG Header序列中包括96个信息比特，用CRC(16)表示初始的EDMG Header序列中包括16个CRC比特。这里将96个信息比特和16个CRC比特记为b1，b2，…，b112。讨论中的802.11ay中初始的EDMG Header序列包括82个信息比特，这里可以对信息比特进行扩展，例如填充14个信息比特构成本申请的96个信息比特。如果需要传输的比特小于112，可以在信息比特位填充一些比特构成96个信息比特。
对112个控制比特b1，b2，…，b112进行加扰得到加扰序列q1，q2，…，q112。应理解，本申请中的加扰为可选步骤，也可以不做加扰处理。也即是说可以直接对序列b1，b2，…，b112进行如下流程的操作，也可以对加扰后的序列q1，q2，…，q112进行如下流 程的操作。下面以对加扰后的序列进行处理为例进行示例性说明。
201，填充比特。
对序列q1，q2，…，q112进行填充操作，使得填充后的填充序列的长度为336。例如，填充0比特，得到填充序列q1，q2，…，q112，01，02，…，0224。
202，对填充后的填充序列进行1/2LDPC编码。
对填充序列q1，q2，…，q112，01，02，…，0224进行1/2LDPC编码，得到编码序列q1，q2，…，q112，01，02，…，0224，p1，p2，…，p336。其中，p1，p2，…，p336为编码产生的奇偶校验比特。
203，移除0比特。
将编码序列中的0比特移除，得到第一序列q1，q2，…，q112，p1，p2，…，p336。该第一序列包括96个信息比特，16个CRC比特和336个就校验比特。
204，对第一序列进行调制映射得到第一调制序列。
对第一序列q1，q2，…，q112，p1，p2，…，p336进行π/2BPSK或BPSK调制、映射处理后得到第一调制序列。
205，对第一序列进行异或操作或交织处理得到第二序列。
对第一序列q1，q2，…，q112，p1，p2，…，p336进行异或操作或交织处理得到第二序列。例如，可以对第一序列q1，q2，…，q112，p1，p2，…，p336采用一组伪随机序列进行加扰处理，得到第二序列。又如，还可以对第一序列采用一组{0,1,0,1…0,1}或{1,0,1…1,0}序列进行异或操作，该{0,1,0,1…0,1}序列或{1,0,1…1,0}中0与1间隔排列，序列的长度为448，其中0和1的个数都为224。{0,1,0,1…0,1}序列也可以写成mod(k,2)，{1,0,1…1,0}序列可以写成mod(k,2)，其中mod()为取余操作，k为从0至447的正整数。再如，对移除序列q1，q2，…，q112，p1，p2，…，p336进行交织处理可以采用一个简单的交织器将第一序列进行倒序，得到第二序列p336，p335，…，p2，p1，q112，…q2，q1。
步骤205为可选步骤。在本发明的一个实施例中，也可以直接将步骤203得到的第一序列作为第二序列，而不进行步骤205操作，在得到第一序列后同时进入步骤204和步骤206，对第一序列进行调制映射，也就是说，第二序列等于第一序列，第二调制序列也等于第一调制序列。
206，将第二序列进行调制映射得到第二调制序列。
对第二序列进行π/2BPSK或BPSK调制、映射处理后得到第二调制序列。
207，在第一调制序列和第二调制序列的前后都***保护间隔。
在第一调制序列和第二调制序列的前后都***保护间隔，如图4所示，确切地说，在第一调制序列之前***保护间隔，在第一调制序列和第二调制序列之间***保护间隔，在第二调制序列之后***保护间隔。保护间隔可以为由64个符号构成的。
***保护间隔后构成插有保护间隔的两个连续的448比特的调制序列，保护间隔和两个调制序列结合待发送的数据共同构成帧，该帧可以用来传输。
现有802.11ay的I/Q方案中，由于初始的EDMG Header中包括82个信息比特，为了采用现有802.11ad中传输64比特的方法，在EDMG Header中填充30个填充比特以凑够128比特，并分为两个64比特来分别使用802.11ad中EDMG Header的调制方案。采用本申请的方案不一定需要30个填充比特，这样，该方案可以少传输16个填充比特， 但性能上增益可以增加2dB。
在本发明的一个实施例中，发射机传输帧之后，接收机可以接收该帧，并对该帧进行解调解码。假设第一序列和第二序列分别用x(n)，y(n)表示，其中n＝0，1，2，…，447，接收机可以根据下列方式实现对帧的解调解码：对x(n)和y(n)分别进行解调得到对
Figure PCTCN2017082064-appb-000001
输入LDPC解码器中得到336个比特估值b1，b2，…，b336，其中，前112个比特估值即为发射机发送EDMG Header序列的112个控制比特的估值。
图7是本发明另一实施例的传输帧的方法的示意性流程图。图7的方法可以由发射机执行，这里的发射机可以为图1中的AP，也可以为图1中的STA。图7以初始的EDMG Header序列包括128个控制比特为例进行示例性说明，应理解，控制比特数目大于112都可以用图7所示的传输帧的方法。
初始的EDMG Header序列包括128个控制比特：b1，b2，…，b128。128个控制比特可以包括信息比特和CRC比特，信息比特和校验比特的数目不做限定，这里以112个信息比特和16个CRC校验比特为例进行示例性说明。图7中用EDMG Header(112)表示初始的EDMG Header序列中包括112个信息比特，用CRC(16)表示初始的EDMG Header序列中包括16个CRC比特。讨论中的802.11ay中EDMG Header序列包括82个信息比特，这里可以对信息比特进行扩展，例如填充30个信息比特构成本申请的112个信息比特。这里将112个信息比特和16个CRC比特记为b1，b2，…，b128。
对128个控制比特b1，b2，…，b128进行加扰得到加扰序列q1，q2，…，q128。应理解，本申请中的加扰为可选步骤，也可以不做加扰处理。也即是说可以直接对序列b1，b2，…，b128进行如下流程的操作，也可以对加扰后的序列q1，q2，…，q128进行如下流程的操作。下面以对加扰后的序列q1，q2，…，q128进行处理为例进行示例性说明。
301，填充比特。
对序列q1，q2，…，q128进行填充操作，使得填充后填充序列的长度为336。例如，填充0比特，得到填充序列q1，q2，…，q128，01，02，…，0208。
302，对填充后的填充序列进行1/2LDPC编码。
对填充序列q1，q2，…，q128，01，02，…，0208进行1/2LDPC编码，得到编码序列q1，q2，…，q128，01，02，…，0208，p1，p2，…，p336。
303，构造第一序列。
将编码序列中的0比特移除，将编码序列中的128个信息比特和第一部分奇偶校验比特构成第一序列，第一序列的长度正好为448。例如，第一序列为：q1，q2，…，q128，p1，p2，…，p320。这里编码序列中的128个信息比特为q1，q2，…，q128。
304，对第一序列进行调制映射，得到第一调制序列。
对第一序列q1，q2，…，q112，p1，p2，…，p320进行π/2BPSK或BPSK调制、映射处理后得到第一调制序列。
305，构造第三序列。
将编码序列中的0比特移除，将编码序列中的128个信息比特和第二部分奇偶校验比特构成第三序列，第三序列的长度也正好为448。例如，第三序列为：q1，q2，…，q128， p1，p2，…，p304，p321，…，p336。
306，对第三序列进行异或操作或交织处理，得到第二序列。
对第三序列q1，q2，…，q128，p1，p2，…，p304，p321，…，p336进行异或操作或交织处理得到第二序列。例如，可以对移除序列q1，q2，…，q128，p1，p2，…，p304，p321，…，p336采用一组伪随机序列进行加扰处理，得到第二序列。又如，还可以对移除序列采用一组{0,1,0,1…0,1}序列进行异或操作，该{0,1,0,1…0,1}序列中0与1间隔排列，序列的长度为448，{0,1,0,1…0,1}序列也可以写成mod(k,2)，其中mod()为取余操作，k为从0至447的正整数。又如，还可以对移除序列采用一组{1,0,1…1,0}序列进行异或操作，该{1,0,1…1,0}序列中0与1间隔排列，序列的长度为448，{1,0,1…1,0}序列也可以写成mod(k+1,2)，其中mod()为取余操作，k为从0至447的正整数。再如，对移除序列q1，q2，…，q128，p1，p2，…，p304，p321，…，p336进行交织处理可以采用一个简单的交织器将第三序列进行倒序，得到第二序列p336，p335，…，p321，p304，…，p2，p1，q128，…q2，q1。
应理解，步骤306为可选步骤。在本发明的一个实施例中，在本发明的一个实施例中，也可以直接将步骤305构造的第三序列作为需要进行调制映射的序列，步骤305后直接进入步骤307，对序列进行调制映射得到第二调制序列。也就是说，构造出的第三序列即认为是需要进行编码调制的第二序列。
307，对第二序列进行调制映射，得到第二调制序列。
对第二序列p336，p335，…，p321，p304，…，p2，p1，q128，…q2，q1进行π/2BPSK或BPSK调制、映射处理后得到第二调制序列。
308，在第一调制序列和第二调制序列的前后都***保护间隔。
在第一调制序列和第二调制序列的前后都***保护间隔，如图4所示，确切地说，在第一调制序列之前***保护间隔，在第一调制序列和第二调制序列之间***保护间隔，在第二调制之后***保护间隔。保护间隔可以为由64个符号构成的。
***保护间隔后构成插有保护间隔的两个连续的448比特的调制序列，保护间隔和两个调制序列共同构成帧，该帧可以用于传输。
本申请对EDMG Header序列进行一次性的编码调制映射，而不需为了沿用802.11ad的方案，将比特分为多份64比特，这样，能够实现帧的重传，提高传输帧的性能。模拟结果显示，相对沿用802.11ad的方案本申请的技术方案还可以提高增益，例如，传输128个比特时可以提高1dB的增益。
在本发明的一个实施例中，发射机传输帧之后，接收机可以接收该帧，并对该帧进行解调解码。假设第一序列和第二序列分别用x(n)，y(n)表示，其中n＝0，1，2，…，447，接收机可以根据下列方式实现对帧的解调解码：对x(n)和y(n)分别进行解调得到LLRx(n)和LLRy(n)；将LLRx(n)和LLRy(n)进行合并得到四个序列LLR1(n)，LLR2(n)，LLR3(n)，LLR4(n)，这四个序列的构成方式如下：
Figure PCTCN2017082064-appb-000002
n＝0，1，2，…，127；
Figure PCTCN2017082064-appb-000003
n＝0，1，2，…，303；
LLR3(n)＝LLRx(n+128+304)，n＝0，1，2，…，15；
LLR4(n)＝LLRy(n+128+304)，n＝0，1，2，…，15；
在LLR1(n)，LLR2(n)，LLR3(n)，LLR4(n)中增加比特0组成新的长度为672的序列LLR′＝[LLR1,LLR2,01,02,…，0208,LLR3,LLR4,]；将序列LLR′输入LDPC解码器中得到336个比特估值b1，b2，…，b336，其中，前128个比特估值即为发射机发送EDMG Header序列的128个控制比特的估值。
上文中结合图1到图7，详细描述了根据本申请的传输帧的方法，下面将结合图8和图11中传输帧的装置的框图描述根据本申请的传输帧的装置。
图8是本申请一个实施例的传输帧的装置的示意性结构图。图8的装置可以执行图2和图6中各流程中发射机所执行的方法。图8的装置10包括获取单元11、填充单元12、编码单元13、构造单元14、调制单元15、处理和传输单元16。
获取单元11用于获取初始的增强方向性多吉比特头EDMG Header序列。其中，初始的EDMG Header序列包括N个控制比特，N为正整数。
填充单元12用于对获取单元获取的初始的EDMG Header序列进行填充操作得到填充序列。其中，填充序列包括N个信息比特和L个填充比特，N个信息比特为N个控制比特或N个信息比特为对N个控制比特进行加扰得到的。
编码单元13用于对填充单元得到的填充序列进行1/2低密度奇偶校验码LDPC编码得到编码序列。其中，编码序列包括N个信息比特、L个填充比特和编码产生的N+L个奇偶校验比特，L为正整数。
构造单元14用于将编码单元得到的所述编码序列中的N个信息比特和全部的奇偶校验比特构成第一序列，并根据第一序列得到第二序列。其中，第一序列和第二序列的长度相同。
调制单元15用于对构造单元得到的第一序列和第二序列分别进行调制得到第一调制序列和第二调制序列。
处理和传输单元16用于在调制单元得到的第一调制序列和第二调制序列之间***保护间隔GI，并根据***保护间隔后的序列得到编码调制后的EDMG Header序列，将编码调制后的EDMG Header序列和待发送的数据结合得到帧，并传输帧。
本申请通过对EDMG Header序列中的控制比特在进行填充操作后进行统一的1/2LDPC编码，并根据编码后的编码序列直接得到都包括所有控制比特的两个序列，再对这两个序列进行调制得到帧并传输该帧，通过这样的重传设计可以提高帧的传输性能。
根据本申请的传输帧的装置可以参照对应本申请的传输帧的方法流程，并且，该装置中的各个单元/模块和上述其他操作和/或功能分别为了实现方法中的相应流程，为了简洁，在此不再赘述。
图9是本发明另一实施例的传输帧的装置的示意性结构图。图9的装置可以执行图3和图7中各流程中发射机所执行的方法。图9的装置20包括获取单元21、填充单元22、编码单元23、构造单元24、调制单元25、处理和传输单元26。
获取单元21用于获取初始的增强方向性多吉比特头EDMG Header序列。其中，初始的EDMG Header序列包括N个控制比特，N为正整数。
填充单元22用于对获取单元获取的初始的EDMG Header序列进行填充操作得到填充序列。其中，填充序列包括N个信息比特和L个填充比特，N个信息比特为N个控制比特或N个信息比特为对N个控制比特进行加扰得到的。
编码单元23用于对填充单元得到的填充序列进行1/2低密度奇偶校验码LDPC编码得到编码序列。其中，编码序列包括N个信息比特、L个填充比特和编码产生的N+L个奇偶校验比特，L为正整数。
构造单元24用于将编码单元得到的编码序列中的N个信息比特和第一部分奇偶校验比特构成第一序列，并根据编码单元得到的编码序列中的N个信息比特和第二部分奇偶校验比特得到第二序列。其中，第一序列和第二序列的长度相同，第一部分奇偶校验比特和第二部分奇偶校验比特包括的比特不全部相同。
调制单元25用于对构造单元得到的第一序列和第二序列分别进行调制得到第一调制序列和第二调制序列。
处理和传输单元26用于在调制单元得到的第一调制序列和第二调制序列之间***保护间隔GI，并根据***保护间隔后的序列得到编码调制后的EDMG Header序列，将编码调制后的EDMG Header序列和待发送的数据结合得到帧，并传输帧。
本申请通过对EDMG Header序列中的控制比特在进行填充操作后进行统一的1/2LDPC编码，并根据编码后的编码序列直接得到都包括所有控制比特的两个序列，再对这两个序列进行调制得到帧并传输该帧，通过这样的重传设计可以提高帧的传输性能。
根据本申请的传输帧的装置可以参照对应本申请的传输帧的方法流程，并且，该装置中的各个单元/模块和上述其他操作和/或功能分别为了实现方法中的相应流程，为了简洁，在此不再赘述。
图10是本发明另一实施例的传输帧的装置的示意性结构图。图10的装置可以执行图2和图6中各流程中发射机所执行的方法。图10的装置30包括发射机31、处理器32和存储器33。处理器32控制装置30的操作，并可用于处理信号。存储器33可以包括只读存储器和随机存取存储器，并向处理器32提供指令和数据。装置30的各个组件通过总线***34耦合在一起，其中总线***34除包括数据总线之外，还包括电源总线、控制总线和状态信号总线。但是为了清楚说明起见，在图中将各种总线都标为总线***34。
上述本申请揭示的方法可以应用于处理器32中，或者由处理器32实现。在实现过程中，上述方法的各步骤可以通过处理器32中的硬件的集成逻辑电路或者软件形式的指令完成。处理器32可以是通用处理器、数字信号处理器、专用集成电路、现场可编程门阵列或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件，可以实现或者执行本申请中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者任何常规的处理器等。结合本申请所公开的方法的步骤可以直接体现为硬件处理器执行完成，或者用处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器33，处理器32读取存储器33中的信息，结合其硬件完成上述方法的步骤。
具体地，处理器32可以获取初始的EDMG Header序列，对初始的EDMG Header序列进行填充操作得到填充序列，对填充序列进行1/2低密度奇偶校验码LDPC编码得到编码序列；将编码序列中的N个信息比特和全部的校验比特构成第一序列，并根据第一序列得到第二序列；对第一序列进行调制得到第一调制序列，并对第二序列进行调制得到第二调制序列；根据所述第一调制序列和所述第二调制序列得到帧。其中，初始的EDMG Header序列包括N个控制比特，N为正整数，填充序列包括N个信息比特和L 个填充比特，N个信息比特为N个控制比特或N个信息比特为对N个控制比特进行加扰得到的，编码序列包括N个信息比特、L个填充比特和编码产生的N+L个校验比特，L为正整数，第一序列和第二序列的长度相同。
处理器32还可以在第一调制序列和第二调制序列之间***保护间隔GI，并根据***保护间隔后的序列得到编码调制后的EDMG Header序列，并将编码调制后的EDMG Header序列和待发送的数据结合得到帧。
发射机31可以传输上述帧。
本申请通过对EDMG Header序列中的控制比特在进行填充操作后进行统一的1/2LDPC编码，并根据编码后的编码序列直接得到都包括所有控制比特的两个序列，再对这两个序列进行调制得到帧并传输该帧，通过这样的重传设计可以提高帧的传输性能。
根据本申请的传输帧的装置可以参照本申请的传输帧的方法流程，并且，该装置中的各个单元/模块和上述其他操作和/或功能分别为了实现方法中的相应流程，为了简洁，在此不再赘述。
图11是本发明另一实施例的传输帧的装置的示意性结构图。图11的装置可以执行图3和图7中各流程中发射机所执行的方法。图11的装置40包括发射机41、处理器42和存储器43。处理器42控制装置40的操作，并可用于处理信号。存储器43可以包括只读存储器和随机存取存储器，并向处理器42提供指令和数据。装置40的各个组件通过总线***44耦合在一起，其中总线***44除包括数据总线之外，还包括电源总线、控制总线和状态信号总线。但是为了清楚说明起见，在图中将各种总线都标为总线***44。
上述本申请揭示的方法可以应用于处理器42中，或者由处理器42实现。在实现过程中，上述方法的各步骤可以通过处理器42中的硬件的集成逻辑电路或者软件形式的指令完成。处理器42可以是通用处理器、数字信号处理器、专用集成电路、现场可编程门阵列或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件，可以实现或者执行本申请中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者任何常规的处理器等。结合本申请所公开的方法的步骤可以直接体现为硬件处理器执行完成，或者用处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器43，处理器42读取存储器43中的信息，结合其硬件完成上述方法的步骤。
具体地，处理器42可以获取初始的EDMG Header序列，对初始的EDMG Header序列进行填充操作得到填充序列，对填充序列进行1/2低密度奇偶校验码LDPC编码得到编码序列；将编码序列中的N个信息比特和第一部分校验比特构成第一序列，并根据编码序列中的N个信息比特和第二部分校验比特得到第二序列；对第一序列进行调制得到第一调制序列，并对第二序列进行调制得到第二调制序列；根据第一调制序列和所述第二调制序列得到帧。其中，初始的EDMG Header序列包括N个控制比特，N为正整数，填充序列包括N个信息比特和L个填充比特，N个信息比特为N个控制比特或N个信息比特为对N个控制比特进行加扰得到的，编码序列包括N个信息比特、L个填充比特和编码产生的N+L个校验比特，L为正整数，第一序列和第二序列的长度相同，第一部分校验比特和第二部分校验比特包括的校验比特不全部相同。
处理器22还可以在第一调制序列和第二调制序列之间***保护间隔GI，并根据插 入保护间隔后的序列得到编码调制后的EDMG Header序列，并将编码调制后的EDMG Header序列和待发送的数据结合得到帧。
发射机21可以传输上述帧。
本申请通过对EDMG Header序列中的控制比特在进行填充操作后进行统一的1/2LDPC编码，并根据编码后的编码序列直接得到都包括所有控制比特的两个序列，再对这两个序列进行调制得到帧并传输该帧，通过这样的重传设计可以提高帧的传输性能。
根据本申请的传输帧的装置可以参照本申请的传输帧的方法流程，并且，该装置中的各个单元/模块和上述其他操作和/或功能分别为了实现方法中的相应流程，为了简洁，在此不再赘述。
应理解，说明书通篇中提到的“一个实施例”或“一实施例”意味着与实施例有关的特定特征、结构或特性包括在本发明的至少一个实施例中。因此，在整个说明书各处出现的“在一个实施例中”或“在一实施例中”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。
应理解，本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
应理解，在本发明的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请的实施过程构成任何限定。
本领域普通技术人员可以意识到，结合本文中所公开的实施例中描述的各方法步骤和单元，能够以电子硬件、计算机软件或者二者的结合来实现，为了清楚地说明硬件和软件的可互换性，在上述说明中已经按照功能一般性地描述了各实施例的步骤及组成。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。本领域普通技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。
结合本文中所公开的实施例描述的方法或步骤可以用硬件、处理器执行的软件程序，或者二者的结合来实施。软件程序可以置于随机存储器(Random Access Memory，RAM)、内存、只读存储器(Read-Only Memory，ROM)、电可编程只读存储器(Electrically Programmable Read-Only Memory，EPROM)、电可擦除可编程只读存储器(Electrically Erasable Programmable Read-Only Memory，EEPROM)、寄存器、硬盘、可移动磁盘、致密盘只读存储器(Compact Disc Read-Only Memory，CD-ROM)、或技术领域内所公知的任意其它形式的存储介质中。
在本申请所提供的几个实施例中，应该理解到，所揭露的***、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个***，或一些特征可以忽略，或不执行。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
尽管通过参考附图并结合优选实施例的方式对本发明进行了详细描述，但本申请并不限于此。在不脱离本申请的精神和实质的前提下，本领域普通技术人员可以对本申请的实施例进行各种等效的修改或替换，而这些修改或替换都应在本申请的涵盖范围内。

Claims (26)

  1. 一种传输帧的方法，其特征在于，包括：
    获取初始的增强方向性多吉比特帧头EDMG Header序列，其中，所述初始的EDMG Header序列包括N个控制比特，N为正整数；
    对所述初始的EDMG Header序列进行填充操作，得到填充序列，其中，所述填充序列包括N个信息比特和L个填充比特，所述N个信息比特为所述N个控制比特或所述N个信息比特为对所述N个控制比特进行加扰得到的；
    对所述填充序列进行1/2低密度奇偶校验码LDPC编码，得到编码序列，其中，所述编码序列包括N个信息比特、L个填充比特和编码产生的N+L个奇偶校验比特，L为正整数；
    将所述编码序列中的N个信息比特和全部的奇偶校验比特构成第一序列，并根据所述第一序列得到第二序列，其中，所述第一序列和所述第二序列的长度相同；
    对所述第一序列进行调制得到第一调制序列，并对所述第二序列进行调制得到第二调制序列；
    在所述第一调制序列和所述第二调制序列之间***保护间隔GI，根据***保护间隔后的序列得到编码调制后的EDMG Header序列，所述编码调制后的EDMG Header序列和待发送的数据结合得到帧，并传输所述帧。
  2. 如权利要求1所述的方法，其特征在于，所述编码序列的长度为672，所述第一序列和所述第二序列的长度都为448，N+L＝336。
  3. 如权利要求1或2所述的方法，其特征在于，当N＝112时，所述根据所述第一序列得到所述第二序列包括：
    对所述第一序列进行异或操作，得到所述第二序列；或者，
    对所述第一序列进行交织处理，得到所述第二序列。
  4. 如权利要求3所述的方法，其特征在于，所述对所述第一序列进行异或操作，得到所述第二序列包括：
    对所述第一序列采用一组伪随机序列进行异或操作，得到所述第二序列；或者，
    对所述第一序列采用序列{0,1,0,1…0,1}或序列{1,0,1…1,0}进行异或操作，得到所述第二序列。
  5. 如权利要求1-4中任一项所述的方法，其特征在于，所述对所述第一序列进行调制得到第一调制序列，并对所述第二序列进行调制得到第二调制序列包括：
    对所述第一序列进行π/2BPSK调制或BPSK调制，得到第一调制序列；
    对所述第二序列进行π/2BPSK调制或BPSK调制，得到第二调制序列。
  6. 一种传输帧的方法，其特征在于，包括：
    获取初始的增强方向性多吉比特帧头EDMG Header序列，其中，所述初始的EDMG Header序列包括N个控制比特，N为正整数；
    对所述初始的EDMG Header序列进行填充操作，得到填充序列，其中，所述填充序列包括N个信息比特和L个填充比特，所述N个信息比特为所述N个控制比特或所述N个信息比特为对所述N个控制比特进行加扰得到的；
    对所述填充序列进行1/2低密度奇偶校验码LDPC编码，得到编码序列，其中，所述编码序列包括N个信息比特、L个填充比特和编码产生的N+L个奇偶校验比特，L为 正整数；
    将所述编码序列中的N个信息比特和第一部分奇偶校验比特构成所述第一序列，并根据所述编码序列中的N个信息比特和第二部分奇偶校验比特得到所述第二序列，其中，所述第一序列和所述第二序列的长度相同，所述第一部分奇偶校验比特和所述第二部分奇偶校验比特包括的比特不全部相同；
    对所述第一序列进行调制得到第一调制序列，并对所述第二序列进行调制得到第二调制序列；
    在所述第一调制序列和所述第二调制序列之间***保护间隔GI，根据***保护间隔后的序列得到编码调制后的EDMG Header序列，所述编码调制后的EDMG Header序列和待发送的数据结合得到帧，并传输所述帧。
  7. 如权利要求6所述的方法，其特征在于，所述编码序列的长度为672，所述第一序列和所述第二序列的长度都为448，N+L＝336。
  8. 如权利要求6或7所述的方法，其特征在于，当N＞112时，所述根据所述编码序列中的N个信息比特和第二部分奇偶校验比特得到所述第二序列包括：
    将所述编码序列中的N个信息比特和第二部分奇偶校验比特构成所述第二序列。
  9. 如权利要求6或7所述的方法，其特征在于，当N＞112时，所述根据所述编码序列中的N个信息比特和第二部分奇偶校验比特得到所述第二序列包括：
    将所述编码序列中的N个信息比特和第二部分奇偶校验比特构成第三序列；
    对所述第三序列进行异或操作或交织处理，得到所述第二序列。
  10. 如权利要求9所述的方法，其特征在于，所述对所述第三序列进行异或操作或交织处理，得到所述第二序列包括：
    对所述第三序列采用一组伪随机序列进行异或操作，得到所述第二序列；或者，
    对所述第三序列采用序列{0,1,0,1…0,1}或序列{1,0,1…1,0}进行异或操作，得到所述第二序列。
  11. 如权利要求6-10中任一项所述的方法，其特征在于，所述第一部分奇偶校验比特和所述第二部分奇偶校验比特构成全部的奇偶校验比特。
  12. 如权利要求6-11中任一项所述的方法，其特征在于，所述第一部分奇偶校验比特和所述第二部分奇偶校验比特中的公共比特数大于阈值，所述阈值为预设值，或者，所述阈值是由全部的奇偶校验比特的数目确定的。
  13. 如权利要求6-12中任一项所述的方法，其特征在于，所述对所述第一序列进行调制得到第一调制序列，并对所述第二序列进行调制得到第二调制序列包括：
    对所述第一序列进行π/2BPSK调制或BPSK调制，得到第一调制序列；
    对所述第二序列进行π/2BPSK调制或BPSK调制，得到第二调制序列。
  14. 一种传输帧的装置，其特征在于，包括：
    获取单元，用于获取初始的增强方向性多吉比特帧头EDMG Header序列，其中，所述初始的EDMG Header序列包括N个控制比特，N为正整数；
    填充单元，用于对获取单元获取的所述初始的EDMG Header序列进行填充操作得到填充序列，其中，所述填充序列包括N个信息比特和L个填充比特，所述N个信息比特为所述N个控制比特或所述N个信息比特为对所述N个控制比特进行加扰得到的；
    编码单元，用于对所述填充单元得到的所述填充序列进行1/2低密度奇偶校验码 LDPC编码，得到编码序列，其中，所述编码序列包括N个信息比特、L个填充比特和编码产生的N+L个奇偶校验比特，L为正整数；
    构造单元，用于将所述编码单元得到的所述编码序列中的N个信息比特和全部的奇偶校验比特构成第一序列，并根据所述第一序列得到第二序列，其中，所述第一序列和所述第二序列的长度相同；
    调制单元，用于对所述构造单元得到的所述第一序列和第二序列分别进行调制得到第一调制序列和第二调制序列；
    处理和传输单元，用于在所述调制单元得到的所述第一调制序列和所述第二调制序列之间***保护间隔GI，并根据***保护间隔后的序列得到编码调制后的EDMG Header序列，所述编码调制后的EDMG Header序列和待发送的数据结合得到帧，并传输所述帧。
  15. 如权利要求14所述的装置，其特征在于，所述编码序列的长度为672，所述第一序列和所述第二序列的长度都为448，N+L＝336。
  16. 如权利要求13或14所述的装置，其特征在于，当N＝112时，所述构造单元具体用于对所述第一序列进行异或操作得到所述第二序列，或者，对所述第一序列进行交织处理得到所述第二序列。
  17. 如权利要求16所述的装置，其特征在于，所述构造单元具体用于对所述第一序列采用一组伪随机序列进行异或操作得到所述第二序列；或者，对所述第一序列采用序列{0,1,0,1…0,1}或序列{1,0,1…1,0}进行异或操作得到所述第二序列。
  18. 如权利要求14-17中任一项所述的装置，其特征在于，所述调制单元具体用于对所述第一序列进行π/2BPSK调制或BPSK调制，得到第一调制序列，并对所述第二序列进行π/2BPSK调制或BPSK调制，得到第二调制序列。
  19. 一种传输帧的装置，其特征在于，包括：
    获取单元，用于获取初始的增强方向性多吉比特帧头EDMG Header序列，其中，所述初始的EDMG Header序列包括N个控制比特，N为正整数；
    填充单元，用于对获取单元获取的所述初始的EDMG Header序列进行填充操作得到填充序列，其中，所述填充序列包括N个信息比特和L个填充比特，所述N个信息比特为所述N个控制比特或所述N个信息比特为对所述N个控制比特进行加扰得到的；
    编码单元，用于对所述填充单元得到的所述填充序列进行1/2低密度奇偶校验码LDPC编码，得到编码序列，其中，所述编码序列包括N个信息比特、L个填充比特和编码产生的N+L个奇偶校验比特，L为正整数；
    构造单元，用于将所述编码单元得到的所述编码序列中的N个信息比特和第一部分奇偶校验比特构成所述第一序列，并根据所述编码单元得到的所述编码序列中的N个信息比特和第二部分奇偶校验比特得到所述第二序列，其中，所述第一序列和所述第二序列的长度相同，所述第一部分奇偶校验比特和所述第二部分奇偶校验比特包括的比特不全部相同；
    调制单元，用于对所述构造单元得到的所述第一序列和第二序列分别进行调制得到第一调制序列和第二调制序列；
    处理和传输单元，用于在所述调制单元得到的所述第一调制序列和所述第二调制序列之间***保护间隔GI，并根据***保护间隔后的序列得到编码调制后的EDMG Header序列，所述编码调制后的EDMG Header序列和待发送的数据结合得到帧，并传输所述帧。
  20. 如权利要求19所述的装置，其特征在于，所述编码序列的长度为672，所述第一序列和所述第二序列的长度都为448，N+L＝336。
  21. 如权利要求19或20所述的装置，其特征在于，当N＞112时，所述构造单元具体用于将所述编码序列中的N个信息比特和第二部分奇偶校验比特构成所述第二序列。
  22. 如权利要求19或20所述的装置，其特征在于，当N＞112时，所述构造单元具体用于将所述编码序列中的N个信息比特和第二部分奇偶校验比特构成第三序列，对所述第三序列进行异或操作或交织处理得到所述第二序列。
  23. 如权利要求22所述的装置，其特征在于，所述构造单元具体用于对所述第三序列采用一组伪随机序列进行异或操作，得到所述第二序列，或者，对所述第三序列采用序列{0,1,0,1…0,1}或序列{1,0,1…1,0}进行异或操作，得到所述第二序列。
  24. 如权利要求19-23中任一项所述的装置，其特征在于，所述第一部分奇偶校验比特和所述第二部分奇偶校验比特构成全部的奇偶校验比特。
  25. 如权利要求19-24中任一项所述的装置，其特征在于，所述第一部分奇偶校验比特和所述第二部分奇偶校验比特中的公共比特数大于阈值，所述阈值为预设值，或者，所述阈值是由全部的奇偶校验比特的数目确定的。
  26. 如权利要求19-25中任一项所述的装置，其特征在于，所述调制单元具体用于对所述第一序列进行π/2BPSK调制或BPSK调制，得到第一调制序列，并对所述第二序列进行π/2BPSK调制或BPSK调制，得到第二调制序列。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101626360A (zh) * 2009-07-31 2010-01-13 清华大学 数字信号传输方法及***
CN103780554A (zh) * 2014-01-13 2014-05-07 宁波大学 抗噪声数字无线广播信号传输方法
CN104618067A (zh) * 2015-02-16 2015-05-13 中国科学院上海高等研究院 Ngb-w***中物理帧信令信道的编码与调制方法
CN104618072A (zh) * 2015-02-16 2015-05-13 中国科学院上海高等研究院 Ngb-w***中逻辑帧信令信道的编码与调制方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2320574B1 (en) * 2009-08-21 2019-10-09 Avago Technologies International Sales Pte. Limited Header encoding for single carrier (SC) and/or orthogonal frequency division multiplexing (OFDM) using shortening, puncturing, and/or repetition
US10044635B2 (en) * 2014-12-09 2018-08-07 Qualcomm Incorporated Frame formats for channel bonding and MIMO transmissions

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101626360A (zh) * 2009-07-31 2010-01-13 清华大学 数字信号传输方法及***
CN103780554A (zh) * 2014-01-13 2014-05-07 宁波大学 抗噪声数字无线广播信号传输方法
CN104618067A (zh) * 2015-02-16 2015-05-13 中国科学院上海高等研究院 Ngb-w***中物理帧信令信道的编码与调制方法
CN104618072A (zh) * 2015-02-16 2015-05-13 中国科学院上海高等研究院 Ngb-w***中逻辑帧信令信道的编码与调制方法

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
See also references of EP3462651A4 *
ZHU, QI ET AL.: "Performance Analysis of LDPC Codes for IEEE 802.16a OFDM System in Multipath Fading Channel", ACTA ELECTRONICA SINICA, vol. 33, no. 4, 30 April 2005 (2005-04-30), pages 624 - 628, XP009511545 *

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