WO2017203873A1 - Solid-state electronic imaging device and method for controlling same - Google Patents

Solid-state electronic imaging device and method for controlling same Download PDF

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Publication number
WO2017203873A1
WO2017203873A1 PCT/JP2017/014926 JP2017014926W WO2017203873A1 WO 2017203873 A1 WO2017203873 A1 WO 2017203873A1 JP 2017014926 W JP2017014926 W JP 2017014926W WO 2017203873 A1 WO2017203873 A1 WO 2017203873A1
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Prior art keywords
sampling
output
circuit
signal
pulse
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PCT/JP2017/014926
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French (fr)
Japanese (ja)
Inventor
善工 古田
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富士フイルム株式会社
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Priority to CN201780031980.3A priority Critical patent/CN109155828B/en
Priority to JP2018519137A priority patent/JP6491797B2/en
Publication of WO2017203873A1 publication Critical patent/WO2017203873A1/en
Priority to US16/190,713 priority patent/US10531037B2/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/616—Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/617—Noise processing, e.g. detecting, correcting, reducing or removing noise for reducing electromagnetic interference, e.g. clocking noise
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors

Definitions

  • the present invention relates to a solid-state electronic imaging device and a control method thereof.
  • CMOS Complementary-Metal-Oxide-Semiconductor
  • CCD Charge-Coupled Device
  • signal charges are accumulated in the photodiode when the photodiode is exposed.
  • the signal charge accumulated in the photodiode is converted into an analog signal (voltage signal), and a video signal is obtained by sampling the converted analog signal. Since the video signal obtained in this way may be distorted due to various factors, there is one that adjusts the timing pulse timing of a CDS (correlated double sampling) circuit (Patent Document 1).
  • CDS correlated double sampling
  • Patent Document 2 In order to prevent beat noise caused by the jumping of the clock of the microcomputer to the video synchronization clock, there is also one that delays the phase of the video signal processing clock (Patent Document 2). In addition, there is a device that prevents noise generated by driving a digital circuit from being mixed into an analog signal (Patent Document 3).
  • FIG. 17 shows periodic noise (periodic noise), horizontal synchronization signal HD (horizontal driving signal), a ramp wave without noise (reference signal), a ramp wave (periodic signal) including periodic noise, and periodicity. It shows the signal fluctuation amount (the fluctuation amount of the video signal) due to noise.
  • periodic noise periodic noise
  • horizontal synchronization signal HD horizontal driving signal
  • ramp wave without noise reference signal
  • ramp wave periodic signal
  • It shows the signal fluctuation amount (the fluctuation amount of the video signal) due to noise.
  • FIG. 18 is an example of the subject image 110 in which periodic noise appears. Due to the periodic noise, beat-like streaks appear as noise 111 in the vertical direction of the subject image 110. In any of Patent Documents 1 to 3, it is not considered to make the noise 111 inconspicuous.
  • This invention aims to make periodic noise inconspicuous.
  • a solid-state electronic image pickup device includes a plurality of photoelectric conversion elements arranged in a row direction and a column direction, a reset pulse for resetting a signal charge accumulated in the photoelectric conversion elements, and a periodic horizontal synchronization signal.
  • a pulse output circuit that outputs a read pulse that is output after the output of the (horizontal drive signal) and that reads out the signal charge accumulated in the photoelectric conversion element, and in response to the output of the read pulse from the pulse output circuit, the photoelectric conversion element Amplification circuit that converts accumulated signal charge into analog signal and outputs it, and increases or decreases during the first sampling period from reset pulse output from pulse output circuit to read pulse output from pulse output circuit
  • the first reference signal is output, and the read pulse output from the pulse output circuit is output from the pulse output circuit.
  • a reference signal output circuit that outputs a second reference signal that increases or decreases during the second sampling period until the output of the first pulse, and the level of the first reference signal that is output from the reference signal output circuit is the first level
  • the level of the first sampling circuit that samples the analog signal output from the amplifier circuit in response to the reference level and the level of the second reference signal output from the reference signal output circuit has become the second reference level.
  • a second sampling circuit that samples an analog signal output from the amplifier circuit in response to the sampling, and analog signal sampling in the first sampling period by the first sampling circuit and analog in the second sampling period in the second sampling circuit Sampling that makes at least one of the signal sampling non-periodic Characterized in that it comprises a control means.
  • the present invention also provides a control method suitable for a solid-state electronic imaging device. That is, in this method, the pulse output circuit outputs a reset pulse for resetting signal charges accumulated in a plurality of photoelectric conversion elements arranged in the row direction and the column direction, and outputs a periodic horizontal synchronizing signal. A readout pulse that is output later and reads out the signal charge accumulated in the photoelectric conversion element is output, and the amplification circuit outputs the signal charge accumulated in the photoelectric conversion element in accordance with the output of the readout pulse from the pulse output circuit.
  • the reference signal output circuit increases or decreases in the first sampling period from the reset pulse output from the pulse output circuit to the read pulse output from the pulse output circuit.
  • the second reference signal that increases or decreases during the second sampling period at the first sampling period is output, and the first sampling circuit outputs the first reference signal level from the reference signal output circuit as the first reference level.
  • the analog signal output from the amplifier circuit is sampled in response to the fact that the second sampling signal is output from the reference signal output circuit to the second reference level.
  • the sampling control means samples the analog signal in the first sampling period by the first sampling circuit and the analog signal in the second sampling period in the second sampling circuit. At least one of the samplings is aperiodic.
  • the sampling control means makes the analog signal in the first sampling period non-periodic by setting at least one of the output timing of the first reference signal and the output timing of the second reference signal from the reference signal output circuit. And at least one of the sampling of the analog signal in the second sampling period is aperiodic.
  • the sampling control means changes the sampling of the analog signal in the first sampling period and the sampling of the analog signal in the second sampling period by aperiodically changing at least one of the first reference level and the second reference level. At least one of these may be aperiodic.
  • the sampling interval between the sampling of the analog signal in the first sampling period and the sampling of the analog signal in the second sampling period may be constant.
  • the sampling interval between the sampling of the analog signal in the first sampling period and the sampling of the analog signal in the second sampling period may be different for each period of the horizontal synchronization signal.
  • a differential circuit that outputs a differential analog signal representing a difference between the first analog signal obtained by sampling in the first sampling circuit and the second analog signal obtained by sampling in the second sampling circuit. Also good.
  • the sampling control means detects the analog signal in the first sampling period from the output timing of the horizontal synchronization signal in response to the periodic noise determining means determining that the subject image contains a certain amount of periodic noise. At least one of the shift amount until the sampling of the signal and the shift amount from the output timing of the horizontal synchronization signal to the sampling of the analog signal in the second sampling period will be shifted to a set value or more.
  • the sampling control means By sampling the analog signal in the first sampling period, the sampling control means makes at least one of the output timing of the first reference signal and the output timing of the second reference signal from the reference signal output circuit non-periodic.
  • the first sampling process in which at least one of the sampling of the analog signal in the second sampling period is aperiodic is performed, the first included in the subject image represented by the differential analog signal output from the differential circuit. 1 periodic noise and the sampling control means aperiodically changing at least one of the first reference level and the second reference level, thereby sampling the analog signal in the first sampling period and the second reference level.
  • Sample analog signal during sampling period Comparing means for comparing the second periodic noise included in the subject image represented by the differential analog signal output from the difference circuit when the second sampling process is performed in which at least one of the two is aperiodic
  • the first sampling processing is performed by the sampling control means, and the second period is detected by the comparing means.
  • Control means for causing the sampling control means to perform the second sampling processing when it is determined that the first periodic noise is larger than the characteristic noise.
  • a drive circuit that generates a horizontal synchronization signal and outputs it to the pulse output circuit may be further provided.
  • the first reference signal is repeatedly increased or decreased in the first sampling period, for example.
  • the second reference signal is repeatedly increased or decreased in the second sampling period, for example.
  • the first reference signal is output after a first fixed period has elapsed from the output of the reset pulse
  • the second reference signal is output after the second fixed period has elapsed from the output of the reset pulse.
  • the sampling control means makes the reset pulse output timing by the pulse output circuit non-periodic.
  • the signal charge accumulated in the photoelectric conversion element is reset by a reset pulse synchronized with the horizontal synchronization signal and read by a read pulse.
  • the signal charge read from the photoelectric conversion element is converted into an analog signal by the amplifier circuit.
  • a first reference signal that increases or decreases in the first sampling period from the reset pulse output to the read pulse output is output, and a first reference signal that increases or decreases in the second sampling period from the reset pulse output to the read pulse output is output. 2 reference signals are output.
  • the analog signal output from the amplifier circuit is sampled when the first reference signal reaches the first reference level, and the analog signal output from the amplifier circuit is sampled when the second reference signal reaches the second reference level. .
  • a difference signal between two analog signals obtained by two samplings represents a video signal.
  • At least one of sampling of the analog signal in the first sampling period and sampling of the analog signal in the second sampling period is aperiodic. Since it is aperiodic in this way, it is possible to prevent the occurrence of periodic noise in the image (subject image) represented by the obtained video signal. Periodic noise is less noticeable.
  • FIG. 1 shows an embodiment of the present invention, and is a block diagram showing an electrical configuration of a digital camera 1.
  • the overall operation of the digital camera 1 is controlled by the control device 11.
  • the digital camera 1 includes an imaging device 2 (solid-state electronic imaging device) controlled by a control device 11 and driven by a drive circuit 3.
  • an imaging device 2 solid-state electronic imaging device
  • the subject is imaged by the imaging device 2, and a video signal representing the subject image is output from the imaging device 2.
  • the video signal output from the imaging device 2 is input to the analog / digital conversion circuit 4 and converted into digital image data by the analog / digital conversion circuit 4.
  • Digital image data is input to the signal processing circuit 5 and subjected to predetermined signal processing such as gamma correction and white balance adjustment.
  • the digital image data output from the signal processing circuit 5 is given to the display control circuit 6, and the subject image is displayed on the display screen of the display device 7 under the control of the display control circuit 6.
  • a shutter release signal is input to the control device 11.
  • the subject is imaged by the imaging device 2 as described above, and a video signal representing the subject image is output from the imaging device 2.
  • the video signal is converted into digital image data by the analog / digital conversion circuit 4, and predetermined signal processing is performed by the signal processing circuit 5.
  • the digital image data output from the signal processing circuit 5 is input to the recording control circuit 9, and the digital image data is recorded on the memory card 10 by the recording control circuit 9.
  • the digital camera 1 is provided with a mode switch 13 for setting various imaging modes, and an imaging mode setting signal output from the mode switch 13 is input to the control device 11.
  • a touch panel 8 is formed on the display screen of the display device 7, and signals indicating various commands are generated by operating the touch panel 8, and these command signals are sent to the control device 11. input. Further, a memory 12 that stores predetermined data is connected to the control device 11.
  • FIG. 2 is a block diagram showing an electrical configuration of the image pickup apparatus 2.
  • the imaging device 2 shown in FIG. 2 is a CMOS (Complementary Metal Metal Oxide Semiconductor) type imaging device 2.
  • the imaging device 2 may be of a CCD (Charge-Coupled Device) type.
  • a plurality of photoelectric conversion elements (photodiodes) 22 are arranged in the row direction (horizontal direction) and the column direction (vertical direction), respectively.
  • An FDA (Floating Diffusion Amplifier) 23 (amplifier circuit) is connected to the photoelectric conversion element 22.
  • the FDA 23 of each column is connected to a common vertical signal line 24 for each column.
  • a CDS (correlated double sampling) circuit 30 is connected to each vertical signal line 24.
  • the output of the CDS circuit 30 is connected to the output line 28.
  • the imaging device 2 includes a ramp wave generation circuit (reference signal generation circuit, sawtooth wave generation circuit) 27.
  • a common reset pulse line 25 and readout pulse line 26 are connected to each row of photoelectric conversion elements 22.
  • the horizontal synchronization signal HD (horizontal synchronization signal, Horizontal Driving pulse) is output from the drive circuit 3 to the imaging device 2.
  • the horizontal synchronization signal HD is input to the pulse output circuit 21.
  • a reset pulse synchronized with the horizontal synchronization signal HD is output from the pulse output circuit 21 to the reset pulse line 25 for each row, and the readout pulse line 26 from the pulse output circuit 21 is synchronized with the horizontal synchronization signal HD.
  • a read pulse is output for each row.
  • the reset pulse is a pulse for resetting the signal charge accumulated in the photoelectric conversion element 22, and is synchronized with the periodic horizontal synchronizing signal HD.
  • the read pulse is a pulse for reading the signal charge accumulated in the photoelectric conversion element.
  • the video signal is converted to an analog signal (voltage signal) by the FDA 23 and is given to the vertical signal line 24.
  • the analog signal is input to the CDS circuit 30 connected to the vertical signal line 24.
  • the FDA 23 is an amplifier circuit that converts the signal charge accumulated in the photoelectric conversion element 22 into an analog signal and outputs it in accordance with the output of the readout pulse from the pulse output circuit 21.
  • the reset pulse output from the pulse output circuit 21 is also input to the ramp wave generation circuit 27.
  • the ramp wave generation circuit 27 outputs the first ramp wave W1 and the second ramp wave W2 (see FIG. 4).
  • the first ramp wave W1 and the second ramp wave W2 are input to the CDS circuit 30.
  • the CDS circuit 30 calculates a differential signal from the analog signal.
  • the calculated difference signal is output from the imaging device 2 through the output line 28 as a video signal from the CDS circuit 30.
  • a video signal representing the subject image is output from the imaging device 2 for each row.
  • the reset pulse and the readout pulse are output from the pulse output circuit 21 in order in the column direction or in the direction opposite to the column direction.
  • FIG. 3 is a block diagram showing an electrical configuration of the CDS circuit 30.
  • FIG. 4 is a time chart of signals flowing through the circuits and the like constituting the CDS circuit 30.
  • a reset pulse is output from the pulse output circuit 21 between time t2 and time t3 after the output of the horizontal synchronization signal HD. To do.
  • the reset pulse is given to the photoelectric conversion element 22, and unnecessary signal charges accumulated in the photoelectric conversion element 22 are swept out.
  • the first ramp wave (first reference signal) W1 is output from the ramp wave generation circuit 27 (reference signal output circuit).
  • the first ramp wave W1 is input to the comparison circuit 33 included in the CDS circuit 30.
  • the first ramp wave W1 decreases (may be increased) to a certain level over time.
  • the analog signal output from the FDA 23 and input to the CDS circuit 30 is input to the first sampling circuit 31, the second sampling circuit 32, and the comparison circuit 33.
  • the level of the analog signal output from the FDA 23 is compared with the level of the first ramp wave W1 output from the ramp wave generation circuit 27.
  • the first sampling from the comparison circuit 33 is performed between the time t5 and the time t6. ⁇ Pulse is output.
  • the first sampling pulse is input to the first sampling circuit 31, and the analog signal input to the first sampling circuit 31 is sampled by the first sampling circuit 31.
  • the signal sampled in the first sampling circuit 31 is output from the first sampling circuit 31 as a reset signal (first analog signal) and input to the negative input terminal of the difference circuit 34.
  • a read pulse is output from the pulse output circuit 21.
  • the period from the reset pulse output by the pulse output circuit 21 to the read pulse output by the pulse output circuit 21 is referred to as a first sampling period. It can be said that the first ramp wave W1 (first reference signal) increases or decreases during the first sampling period.
  • the signal charge accumulated in the photoelectric conversion element 22 is given to the FDA 23, and an analog signal is output from the FDA 23.
  • the analog signal output from the FDA 23 is input to the first sampling circuit 31, the second sampling circuit 32, and the comparison circuit 33 included in the CDS circuit 30.
  • the ramp wave generating circuit 27 outputs the second ramp wave W2 (second reference signal), and the second ramp wave W2 is Input to the comparison circuit 33.
  • the comparison circuit 33 compares the level of the analog signal output from the FDA 23 with the level of the second ramp wave W2.
  • the second sampling pulse is output from the comparison circuit 33 between time t10 and time t11. Is output.
  • the second sampling pulse is input to the second sampling circuit 32, and the analog signal input to the second sampling circuit 32 is sampled by the second sampling circuit 32.
  • the signal sampled in the second sampling circuit 32 is output from the second sampling circuit 32 as a data signal (second analog signal) and input to the plus input terminal of the difference circuit 34.
  • next horizontal synchronizing signal HD falls at time t12, and the next reset pulse is output at time t13.
  • the period from the output of the readout pulse to the output of the reset pulse is referred to as a second sampling period. It can be said that the second ramp wave W2 (second reference signal) increases or decreases during the second sampling period.
  • the difference analog signal is output from the difference circuit 34 as a video signal.
  • FIG. 5 is a time chart of the output timing of the horizontal synchronization signal HD, the reset pulse, and the ramp wave.
  • the reset pulse is output after the periodic horizontal synchronizing signal HD is output.
  • FIG. 5 shows three types of ramp wave output timing.
  • the output timing of these ramp waves is controlled by the control device 11 (sampling control means).
  • the output of the first ramp wave W1 starts after the period of ⁇ t1 has elapsed (as shown in FIG. 4, the decrease of the first ramp wave W1 starts.
  • the second ramp wave W2 starts to be output after the lapse of the period ⁇ t2 after the reset pulse is output (as shown in FIG. 4, the second ramp wave W2 starts to decrease).
  • a reset pulse is aperiodically output from the pulse output circuit 21 at the first output timing.
  • “non-periodic” may be different from “periodic” in which a certain phenomenon (change in pulse output, reference signal output, or reference level) occurs at regular intervals. Random ones may be used, and one subject image may not be generated twice during the display of one subject image. It does not have to coincide with the period of periodic noise.
  • the second output timing is such that the output timing of the first ramp wave W1 is gradually delayed (shifted) for each cycle of the horizontal synchronization signal HD.
  • the first horizontal scanning period the horizontal sync signal output interval, the period from the rise of the horizontal sync signal to the rise of the next horizontal sync signal is referred to as the horizontal scan period.
  • the output of W1 starts after the lapse of ⁇ t1 from the output of the reset pulse
  • the output of the second ramp wave W2 starts after the lapse of ⁇ t2 ( ⁇ t2 is greater than ⁇ t1) from the output of the reset pulse.
  • the output of the first ramp wave W1 is delayed from the output timing of the first horizontal scanning period, and ⁇ t1 + ⁇ 1 from the output of the reset pulse.
  • the output of the second ramp wave W2 starts after the lapse of ⁇ t2 + ⁇ 1 from the output of the reset pulse.
  • the output of the first ramp wave W1 is further delayed from the output timing of the second horizontal scanning period, and the reset pulse is output. It starts after a period of ⁇ t1 + ⁇ 2 ( ⁇ 2 is larger than ⁇ 1) from the output. The same applies to the subsequent horizontal scanning period.
  • the output timing of both the first ramp wave W1 and the second ramp wave W2 is aperiodic.
  • the timing at which the level of the first ramp wave W1 becomes equal to the first reference level V1 is also the second ramp wave W2.
  • the timing at which the level becomes equal to the second reference level V2 is also aperiodic.
  • the control device 11 samples the reset signal (analog signal) in the first sampling period by the first sampling circuit 31 and the data in the second sampling period by the second sampling circuit 32. Any sampling of the signal (analog signal) is aperiodic.
  • the imaging device 2 is affected by the periodic noise, and the ramp wave (first ramp wave W1, second ramp wave W2) includes the periodic noise. Even in such a case, the periodic noise is excluded from the video signal output from the difference circuit. As shown in FIG. 18, the streak noise 111 is prevented from occurring in the subject image 110 in advance.
  • the output timing of the first ramp wave W1 is after the lapse of ⁇ t1 from the output of the reset pulse, but the output timing of the second ramp wave W2 is 1 of the horizontal synchronization signal HD. It gradually delays (shifts) every cycle.
  • the output of the second ramp wave W2 starts after the period of ⁇ t2 has elapsed from the output of the reset pulse.
  • the output timing of the second ramp wave W2 is delayed from the output timing of the first horizontal scanning period, and from the reset pulse output. It starts after the period of ⁇ t2 + ⁇ 1.
  • the output timing of the second ramp wave W2 is further delayed than the output timing in the second horizontal scanning period, and the reset pulse is output.
  • ⁇ t2 + ⁇ 2 ( ⁇ 2 is greater than ⁇ 1). The same applies to the subsequent horizontal scanning period.
  • the output timing of the first ramp wave W1 is periodic, but the output timing of the second ramp wave W2 is aperiodic.
  • the timing at which the level of the second ramp wave W2 becomes equal to the second reference level V2 becomes aperiodic.
  • the control device 11 periodically samples the reset signal (analog signal) in the first sampling period by the first sampling circuit 31, but the second sampling circuit 32 in the second sampling period. Sampling of the data signal (analog signal) becomes aperiodic. Since the video signal is represented by the difference circuit 34 by the difference between the data signal obtained by non-periodic sampling and the reset signal obtained by periodic sampling, imaging is performed as described with reference to FIG. Even when the apparatus 2 is affected by the periodic noise, the periodic noise is excluded from the video signal output from the difference circuit 34. As shown in FIG. 18, the streak noise 111 is prevented from occurring in the subject image 110 in advance.
  • the output timing of the first ramp wave W1 is periodic and the output timing of the second ramp wave W2 is aperiodic, but the output timing of the first ramp wave W1 is aperiodic.
  • the output timing of the second ramp wave W2 may be periodic.
  • the control device 11 sets at least one of sampling of the reset signal (analog signal) in the first sampling period and sampling of the data signal (analog signal) in the second sampling period to be aperiodic. can do.
  • the sampling interval between the sampling of the reset signal in the first sampling period and the sampling of the data signal in the second sampling period is ⁇ t2 ⁇ t1, which is constant. In this way, the sampling interval is constant. It may be.
  • the sampling interval between the sampling of the reset signal in the first sampling period and the sampling of the data signal in the second sampling period is different for each period of the horizontal synchronization signal HD. As described above, the sampling interval may be different for each cycle of the horizontal synchronization signal HD.
  • 6 and 7 are flowcharts showing a processing procedure for determining the output timing of the first ramp wave W1 and the output timing of the second ramp wave W2. 6 and 7 show a processing procedure of the second output timing of FIG.
  • a reset pulse is output from the pulse output circuit 21 (YES in step 41)
  • a first ramp wave W1 that gradually decreases after the period of ⁇ t1 from the output of the reset pulse is generated from the ramp wave generation circuit 27.
  • Output step 42.
  • the analog signal output from the FDA 23 is sampled by the first sampling circuit 31, and a reset signal is obtained.
  • the ramp wave generating circuit 27 When a certain period ( ⁇ t2 ⁇ t1) has elapsed from the output of the first ramp wave W1 (YES in step 43), that is, when a period of ⁇ t2 has elapsed from the output of the reset pulse, the ramp wave generating circuit 27 outputs the second ramp wave. W2 is output (step 44). When the second ramp wave W2 becomes equal to the second reference level V2, the analog signal output from the FDA 23 is sampled by the second sampling circuit 32 to obtain a data signal.
  • the control unit 11 sets the ramp wave generation circuit 27 so as to shift the output timing of the first ramp wave W1 (step 45). . If the control of the imaging device 2 is not completed (NO in step 46), when one horizontal scanning period has elapsed (step 47), the next horizontal scanning period starts and a reset pulse is output from the pulse output circuit 21 ( YES at step 41). In the next horizontal scanning period, the output timing of the first ramp wave W1 is shifted.
  • the first ramp wave W1 and the second ramp wave W2 are output, a process for shifting the output timing of the first ramp wave W1 is performed, and the sampling of the first ramp wave W1 becomes aperiodic. Since the second ramp wave W2 is output after a lapse of a certain period of the first ramp wave W1, the second ramp wave W2 is also non-periodic.
  • 8 and 9 are flowcharts showing other processing procedures for determining the output timing of the first ramp wave W1 and the output timing of the second ramp wave W2. 8 and 9 show a processing procedure of the third output timing of FIG.
  • the reset pulse is output from the pulse output circuit 21 (YES in step 51).
  • the first ramp wave W1 is output from the pulse output circuit 21 (step 53).
  • the analog signal output from the FDA 23 is sampled by the first sampling circuit 31, and a reset signal is obtained.
  • the second ramp wave W2 is output from the ramp wave generation circuit 27 (step 55).
  • the analog signal output from the FDA 23 is sampled by the second sampling circuit 32 to obtain a data signal.
  • the pulse output circuit 21 is controlled by the controller 11 to shift (delay) the output timing of the second ramp wave W2 (step) 56). If the control of the imaging device 2 is not completed (NO in step 57), when one horizontal scanning period has elapsed (YES in step 58), the next horizontal scanning period starts and a reset pulse is output from the pulse output circuit 21. (YES in step 51). When the period of ⁇ t1 has elapsed from the output of the reset pulse (YES in step 52), the first ramp wave W1 is output again (step 53), and when the period of ⁇ t2 + ⁇ 1 has elapsed from the output of the reset pulse (step 54).
  • the second ramp wave W2 is output (step 55).
  • the shift of the period for determining the timing for outputting the second ramp wave W2 is repeated.
  • Sampling of the second ramp wave W2 is non-periodic.
  • FIG. 10 and FIG. 11 are flowcharts showing a processing procedure for changing the first reference level V1 and the second reference level V2.
  • the processing procedure shown in FIGS. 10 and 11 includes a first reference level V1 used for sampling in the first sampling period and a second reference level V2 used for sampling in the second sampling period. By changing every horizontal scanning period, at least one of sampling in the first sampling period and sampling in the second sampling period is made aperiodic.
  • the first ramp wave W1 is output from the ramp wave generation circuit 27 after a period of ⁇ t1 has elapsed from the output of the reset pulse (step 62). ).
  • the first sampling pulse is input to the first sampling circuit 31.
  • the analog signal output from the FDA 23 is sampled by the first sampling circuit 31, and a reset signal is obtained.
  • the second ramp wave W2 is output from the ramp wave generation circuit 27 after the lapse of ⁇ t2 from the reset pulse output (step 65).
  • the second sampling pulse is input to the second sampling circuit 32.
  • the analog signal output from the FDA 23 is sampled by the second sampling circuit 32 to obtain a data signal.
  • the first circuit set in the comparison circuit 33 included in the CDS circuit 30 is set.
  • the reference level V1 and the second reference level V2 are changed by the control device 11 (step 68). However, even if the reference levels of both the first reference level V1 and the second reference level V2 are not changed, one of the first reference level V1 and the second reference level V2 is changed. Just do it.
  • step 70 If the control of the imaging device 2 is not completed (NO in step 69), when one horizontal scanning period has elapsed (YES in step 70), the next horizontal scanning period starts and a reset pulse is output from the pulse output circuit 21. (YES in step 61). Thereafter, when the first ramp wave W1 is output and the level of the output first ramp wave W1 becomes equal to the first reference level V1 (YES in step 62 and step 63), the first sampling circuit 31 Sampling is performed. When the second ramp wave W2 is output and the level of the output second ramp wave W2 becomes equal to the second reference level V2 (YES in step 65 and step 66), the second sampling circuit 32 Sampling is performed.
  • the first reference level V1 and the second reference level V2 are changed (changed to different values for each horizontal scanning period). From the above, the sampling by the first sampling circuit 31 performed when the first reference level V1 and the level of the first ramp wave W1 are equal, and the second reference level V2 and the level of the second ramp wave W2 The timing of sampling by the second sampling circuit 32 performed by the equality becomes aperiodic.
  • 12 and 13 are flowcharts showing another processing procedure for determining the output timing of the first ramp wave W1 and the output timing of the second ramp wave W2. 12 and 13 show that the reset pulse is aperiodic when the first ramp wave W1 and the second ramp wave W2 are output at the first output timing of FIG.
  • a reset pulse is output from the pulse output circuit 21 (step 82).
  • the ramp wave generating circuit 27 outputs the first ramp wave W1 (step 84).
  • the first ramp wave W1 becomes equal to the first reference level V1
  • the analog signal output from the FDA 23 is sampled by the first sampling circuit 31, and a reset signal is obtained.
  • the ramp wave generation circuit 27 When a period ⁇ t2 (second constant period) has elapsed from the output of the reset pulse (YES in step 85), the ramp wave generation circuit 27 outputs the second ramp wave W2 (step 86). When the second ramp wave W2 becomes equal to the second reference level V2, the analog signal output from the FDA 23 is sampled by the second sampling circuit 32 to obtain a data signal.
  • the control device 11 controls so that the output timing of the reset pulse output from the pulse output circuit 21 is shifted (delayed). (Step 87). If the control of the image pickup device 2 is not completed (NO in step 88), when one horizontal scanning period has elapsed (YES in step 89), the next horizontal synchronization signal HD is output (YES in step 81), and the pulse output circuit A reset pulse is output from 21 (step 82). When the ⁇ t1 period (first constant period) has elapsed from the output of the reset pulse, the first ramp wave W1 is output.
  • a second ramp wave W2 is output.
  • the reset pulse output timing is shifted, so the output timing of the first ramp wave W1 and the output timing of the second ramp wave W2 are also non-periodic.
  • the first ramp wave W1 and the second ramp wave W2 are shifted for each cycle of the horizontal synchronizing signal HD.
  • FIG. 14 is a flowchart showing the processing procedure of the digital camera 1.
  • the differential analog signal output from the differential circuit 34 included in the CDS circuit 30 is converted into digital image data in the analog / digital conversion circuit 4 and input to the control device 11 via the signal processing circuit 5.
  • the control device 11 (periodic noise determination means), it is determined whether or not the input digital image data (differential analog signal) includes periodic noise more than a certain value (periodic noise level is more than a certain value) (step) 91).
  • the periodic noise is included above a certain level (YES in step 91), it is considered that the periodic noise has a great influence on the subject image (image).
  • At least one of the two sampling pulse output timings is shifted to a set value or more (step 92). Even when the periodic noise is large and the influence on the subject image is large, at least one of the output timing of the first sampling pulse and the output timing of the second sampling pulse according to the magnitude of the periodic noise. Since one of them is shifted beyond the set value, the influence of periodic noise on the subject image can be suppressed.
  • the method of shifting the output timing of the first sampling pulse and the output timing of the second sampling pulse may be any of the methods described with reference to FIGS.
  • the set values are the deviation amount of the output timing of the first sampling pulse and the deviation amount of the output timing of the second sampling pulse. If the periodic noise is above a certain level, at least one of these shift amounts is shifted to a set value or more. For example, in the case of the first output timing shown in FIG. 5, the reset pulse deviation amount is a set value, and in the case of the second output timing and the third output timing shown in FIG. ⁇ 2 is a set value.
  • the differential analog signal does not contain periodic noise above a certain level (NO in step 91)
  • neither the output timing of the first sampling pulse nor the output timing of the second sampling pulse need be shifted.
  • at least one of the output timing of the first sampling pulse and the second sampling pulse may be shifted to a value smaller than the set value.
  • FIG. 15 is a flowchart showing another processing procedure of the digital camera 1.
  • the first sampling process and the second sampling process are performed (step 101).
  • the first sampling process is performed at least of the output timing of the first ramp wave W1 and the output timing of the second ramp wave W2 as shown in FIGS.
  • the second sampling process analog signals in the first sampling period are changed by aperiodically changing at least one of the first reference level V1 and the second reference level V2 as shown in FIGS.
  • At least one of the sampling of the signal and the sampling of the analog signal in the second sampling period is aperiodic.
  • the first periodic noise included in the subject image represented by the differential analog signal output from the difference circuit 34 and the second sampling process are performed when the second sampling process is performed.
  • the control device 11 detects the second periodic noise included in the subject image represented by the differential analog signal output from the control unit, and controls the first periodic noise and the second periodic noise.
  • the comparison is performed by the device 11 (comparison means) (step 102).
  • the first sampling process removes the periodic noise rather than the second sampling process. Since it is considered possible, the CDS circuit 30 is controlled by the control device 11 (control means) so that the first sampling process is performed (step 104).
  • the CDS circuit 30 is controlled by the control device 11 (control means) so that the second sampling process is performed (step 105).
  • FIG. 16 shows another example of the second ramp wave W2.
  • the second ramp wave W2 shown in FIG. 4 decreases in the second sampling period.
  • the second ramp wave W2 shown in FIG. 16 decreases from time t21 to time t22 in the second sampling period, is reset at time t22 (increased to a constant level), and starts from time t22. It decreases again during time t23. In this manner, the decrease of the second ramp wave W2 may be repeated during the second sampling period.
  • the second ramp wave W2 shown in FIG. 4 decreases in the second sampling period, but may increase instead of decreasing. Furthermore, the second ramp wave W2 shown in FIG. 16 may not be repeatedly decreased during the second sampling period, but may be repeatedly increased (repeated or increased).
  • first ramp wave W1 shown in FIG. 4 is also decreased in the first sampling period, but may be decreased but not increased. Also, the first ramp wave W1 shown in FIG. 4 may be repeatedly reduced (or increased) in the same manner as the second ramp wave W2 shown in FIG.

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Abstract

Provided are: a solid-state electronic imaging device that allows periodic noise to be less noticeable; and a method for controlling the same. In the solid-state electronic imaging device having multiple photoelectric conversion elements arranged therein, a second ramp wave (W2) is outputted that is reduced during a second sampling period that starts when a read pulse for reading signal charges accumulated in the photoelectric conversion elements is outputted and that ends when a reset pulse for resetting the signal charges accumulated in the photoelectric conversion elements is outputted. When the level of the second ramp wave (W2) reaches a second reference level (V2), a second sampling pulse is outputted, and a voltage signal converted from the signal charges is sampled. Intervals of the sampling are non-periodic. Even when periodic noise influences the solid-state electronic imaging device, the periodic noise can be eliminated from an object image obtained by imaging.

Description

固体電子撮像装置およびその制御方法Solid-state electronic imaging device and control method thereof
　この発明は，固体電子撮像装置およびその制御方法に関する。 The present invention relates to a solid-state electronic imaging device and a control method thereof.
　CMOS(Complementary Metal Oxide Semiconductor)型の固体電子撮像素子，ＣＣＤ(Charge Coupled Device)型の固体電子撮像素子などにおいては，フォトダイオードが露光されることによりフォトダイオードに信号電荷が蓄積される。フォトダイオードに蓄積された信号電荷はアナログ信号（電圧信号）に変換され，変換されたアナログ信号がサンプリングされることにより，映像信号が得られる。このようにして得られる映像信号が種々の要因により歪むことがあるので，ＣＤＳ（correlated double sampling）回路のタイミングパルスのタイミングを調整するものがある(特許文献１)。また，映像同期クロックへのマイコンのクロックの飛び込みに起因するビートノイズを防ぐために，映像信号処理用クロックの位相を遅延するものもある(特許文献２)。さらに，デジタル回路の駆動により生ずるノイズのアナログ信号への混入を防ぐものなどもある(特許文献３)。 In a CMOS (Complementary-Metal-Oxide-Semiconductor) type solid-state electronic image sensor, a CCD (Charge-Coupled Device) -type solid-state electronic image sensor, signal charges are accumulated in the photodiode when the photodiode is exposed. The signal charge accumulated in the photodiode is converted into an analog signal (voltage signal), and a video signal is obtained by sampling the converted analog signal. Since the video signal obtained in this way may be distorted due to various factors, there is one that adjusts the timing pulse timing of a CDS (correlated double sampling) circuit (Patent Document 1). In addition, in order to prevent beat noise caused by the jumping of the clock of the microcomputer to the video synchronization clock, there is also one that delays the phase of the video signal processing clock (Patent Document 2). In addition, there is a device that prevents noise generated by driving a digital circuit from being mixed into an analog signal (Patent Document 3).
特開2012-239650号公報JP 2012-239650 A 特開2008-187511号公報JP 2008-187511 A 特開2007-36425号公報JP 2007-36425 A
　図17は，周期性ノイズ（周期的なノイズ），水平同期信号ＨＤ(horizontal driving signal)，ノイズが無いランプ波（基準信号），周期性ノイズが含まれたランプ波（基準信号）および周期性ノイズによる信号変動量（映像信号の変動量）を示している。ランプ波に周期性ノイズが含まれていない場合には，ランプ波が所定のレベルとなる時刻ｔｓ１において，フォトダイオードに蓄積された信号電荷が変換されたアナログ信号がサンプリングされ，映像信号が得られる。ランプ波に周期性ノイズが含まれていない場合には，得られた映像信号にはノイズの影響は無い。しかしながら，ランプ波に周期性ノイズが含まれている場合には，ランプ波が所定のレベルとなる時刻は時刻ｔｓ１から時刻ｔｓ２にずれる。時刻ｔｓ２において，フォトダイオードに蓄積された信号電荷が変換されたアナログ信号がサンプリングされ，周期性ノイズによる周期的な信号変動量が形成されてしまう。この周期的な信号変動量により，撮像により得られた画像に周期性ノイズが目立ってしまう。図18は，周期性ノイズが現れている被写体像110の一例である。周期性ノイズのために，被写体像110の垂直方向に，ビート状の筋がノイズ111として現れている。特許文献１から３のいずれにおいても，このようなノイズ111を目立たなくすることは考えられていない。 FIG. 17 shows periodic noise (periodic noise), horizontal synchronization signal HD (horizontal driving signal), a ramp wave without noise (reference signal), a ramp wave (periodic signal) including periodic noise, and periodicity. It shows the signal fluctuation amount (the fluctuation amount of the video signal) due to noise. When the periodic noise is not included in the ramp wave, an analog signal obtained by converting the signal charge accumulated in the photodiode is sampled at time ts1 when the ramp wave reaches a predetermined level, and a video signal is obtained. . When the periodic noise is not included in the ramp wave, the obtained video signal is not affected by the noise. However, when periodic noise is included in the ramp wave, the time at which the ramp wave reaches a predetermined level is shifted from time ts1 to time ts2. At time ts2, an analog signal obtained by converting the signal charge accumulated in the photodiode is sampled, and a periodic signal fluctuation amount due to periodic noise is formed. Due to this periodic signal fluctuation amount, periodic noise becomes conspicuous in an image obtained by imaging. FIG. 18 is an example of the subject image 110 in which periodic noise appears. Due to the periodic noise, beat-like streaks appear as noise 111 in the vertical direction of the subject image 110. In any of Patent Documents 1 to 3, it is not considered to make the noise 111 inconspicuous.
　この発明は，周期性ノイズを目立たなくすることを目的とする。 This invention aims to make periodic noise inconspicuous.
　この発明による固体電子撮像装置は，行方向および列方向のそれぞれに配置された複数の光電変換素子，光電変換素子に蓄積されている信号電荷をリセットするリセット・パルスを，周期的な水平同期信号（水平駆動信号）の出力後に出力し，かつ光電変換素子に蓄積されている信号電荷を読み出す読み出しパルスを出力するパルス出力回路，パルス出力回路からの読み出しパルスの出力に応じて，光電変換素子に蓄積されている信号電荷をアナログ信号に変換して出力する増幅回路，パルス出力回路からのリセット・パルスの出力からパルス出力回路からの読み出しパルスの出力までの第１のサンプリング期間に増加または減少する第１の基準信号を出力し，かつパルス出力回路からの読み出しパルスの出力からパルス出力回路からのリセット・パルスの出力までの第２のサンプリング期間に増加または減少する第２の基準信号を出力する基準信号出力回路，基準信号出力回路から出力される第１の基準信号のレベルが第１の基準レベルとなったことに応じて増幅回路から出力するアナログ信号をサンプリングする第１のサンプリング回路，基準信号出力回路から出力される第２の基準信号のレベルが第２の基準レベルとなったことに応じて増幅回路から出力するアナログ信号をサンプリングする第２のサンプリング回路，ならびに第１のサンプリング回路による第１のサンプリング期間におけるアナログ信号のサンプリングおよび第２のサンプリング回路における第２のサンプリング期間におけるアナログ信号のサンプリングの少なくとも一方を非周期的とするサンプリング制御手段を備えていることを特徴とする。 A solid-state electronic image pickup device according to the present invention includes a plurality of photoelectric conversion elements arranged in a row direction and a column direction, a reset pulse for resetting a signal charge accumulated in the photoelectric conversion elements, and a periodic horizontal synchronization signal. A pulse output circuit that outputs a read pulse that is output after the output of the (horizontal drive signal) and that reads out the signal charge accumulated in the photoelectric conversion element, and in response to the output of the read pulse from the pulse output circuit, the photoelectric conversion element Amplification circuit that converts accumulated signal charge into analog signal and outputs it, and increases or decreases during the first sampling period from reset pulse output from pulse output circuit to read pulse output from pulse output circuit The first reference signal is output, and the read pulse output from the pulse output circuit is output from the pulse output circuit. A reference signal output circuit that outputs a second reference signal that increases or decreases during the second sampling period until the output of the first pulse, and the level of the first reference signal that is output from the reference signal output circuit is the first level The level of the first sampling circuit that samples the analog signal output from the amplifier circuit in response to the reference level and the level of the second reference signal output from the reference signal output circuit has become the second reference level. A second sampling circuit that samples an analog signal output from the amplifier circuit in response to the sampling, and analog signal sampling in the first sampling period by the first sampling circuit and analog in the second sampling period in the second sampling circuit Sampling that makes at least one of the signal sampling non-periodic Characterized in that it comprises a control means.
　この発明は，固体電子撮像装置に適した制御方法も提供している。すなわち，この方法は，パルス出力回路が，行方向および列方向のそれぞれに配置された複数の光電変換素子に蓄積されている信号電荷をリセットするリセット・パルスを，周期的な水平同期信号の出力後に出力し，かつ光電変換素子に蓄積されている信号電荷を読み出す読み出しパルスを出力し，増幅回路が，パルス出力回路からの読み出しパルスの出力に応じて，光電変換素子に蓄積されている信号電荷をアナログ信号に変換して出力し，基準信号出力回路が，パルス出力回路からのリセット・パルスの出力からパルス出力回路からの読み出しパルスの出力までの第１のサンプリング期間に増加または減少する第１の基準信号を出力し，かつパルス出力回路からの読み出しパルスの出力からパルス出力回路からのリセット・パルスの出力までの第２のサンプリング期間に増加または減少する第２の基準信号を出力し，第１のサンプリング回路が，基準信号出力回路から出力される第１の基準信号のレベルが第１の基準レベルとなったことに応じて増幅回路から出力するアナログ信号をサンプリングし，第２のサンプリング回路が，基準信号出力回路から出力される第２の基準信号のレベルが第２の基準レベルとなったことに応じて増幅回路から出力するアナログ信号をサンプリングし，サンプリング制御手段が，第１のサンプリング回路による第１のサンプリング期間におけるアナログ信号のサンプリングおよび第２のサンプリング回路における第２のサンプリング期間におけるアナログ信号のサンプリングの少なくとも一方を非周期的とする。 The present invention also provides a control method suitable for a solid-state electronic imaging device. That is, in this method, the pulse output circuit outputs a reset pulse for resetting signal charges accumulated in a plurality of photoelectric conversion elements arranged in the row direction and the column direction, and outputs a periodic horizontal synchronizing signal. A readout pulse that is output later and reads out the signal charge accumulated in the photoelectric conversion element is output, and the amplification circuit outputs the signal charge accumulated in the photoelectric conversion element in accordance with the output of the readout pulse from the pulse output circuit. The reference signal output circuit increases or decreases in the first sampling period from the reset pulse output from the pulse output circuit to the read pulse output from the pulse output circuit. Output a reference pulse and output a reset pulse from the pulse output circuit from the read pulse output from the pulse output circuit The second reference signal that increases or decreases during the second sampling period at the first sampling period is output, and the first sampling circuit outputs the first reference signal level from the reference signal output circuit as the first reference level. The analog signal output from the amplifier circuit is sampled in response to the fact that the second sampling signal is output from the reference signal output circuit to the second reference level. In response, the analog signal output from the amplifier circuit is sampled, and the sampling control means samples the analog signal in the first sampling period by the first sampling circuit and the analog signal in the second sampling period in the second sampling circuit. At least one of the samplings is aperiodic.
　サンプリング制御手段は，たとえば，基準信号出力回路からの第１の基準信号の出力タイミングおよび第２の基準信号の出力タイミングの少なくとも一方を非周期的とすることにより，第１のサンプリング期間におけるアナログ信号のサンプリングおよび第２のサンプリング期間におけるアナログ信号のサンプリングの少なくとも一方を非周期的とする。 The sampling control means, for example, makes the analog signal in the first sampling period non-periodic by setting at least one of the output timing of the first reference signal and the output timing of the second reference signal from the reference signal output circuit. And at least one of the sampling of the analog signal in the second sampling period is aperiodic.
　サンプリング制御手段は，第１の基準レベルおよび第２の基準レベルの少なくとも一方を非周期的に変更することにより，第１のサンプリング期間におけるアナログ信号のサンプリングおよび第２のサンプリング期間におけるアナログ信号のサンプリングの少なくとも一方を非周期的としてもよい。 The sampling control means changes the sampling of the analog signal in the first sampling period and the sampling of the analog signal in the second sampling period by aperiodically changing at least one of the first reference level and the second reference level. At least one of these may be aperiodic.
　第１のサンプリング期間におけるアナログ信号のサンプリングと第２のサンプリング期間におけるアナログ信号のサンプリングとのサンプリング間隔が一定でもよい。 The sampling interval between the sampling of the analog signal in the first sampling period and the sampling of the analog signal in the second sampling period may be constant.
　第１のサンプリング期間におけるアナログ信号のサンプリングと第２のサンプリング期間におけるアナログ信号のサンプリングとのサンプリング間隔が水平同期信号の周期ごとに異なってもよい。 The sampling interval between the sampling of the analog signal in the first sampling period and the sampling of the analog signal in the second sampling period may be different for each period of the horizontal synchronization signal.
　第１のサンプリング回路におけるサンプリングにより得られた第１のアナログ信号と第２のサンプリング回路におけるサンプリングにより得られた第２のアナログ信号との差分を表す差分アナログ信号を出力する差分回路をさらに備えてもよい。 And a differential circuit that outputs a differential analog signal representing a difference between the first analog signal obtained by sampling in the first sampling circuit and the second analog signal obtained by sampling in the second sampling circuit. Also good.
　差分回路から出力した差分アナログ信号によって表される被写体像に周期性ノイズが一定以上含まれているかどうかを判定する周期性ノイズ判定手段をさらに備えてもよい。この場合，サンプリング制御手段は，周期性ノイズ判定手段によって被写体像に周期性ノイズが一定以上含まれていると判定されたことに応じて，水平同期信号の出力タイミングから第１のサンプリング期間におけるアナログ信号のサンプリングまでのずれ量および水平同期信号の出力タイミングから第２のサンプリング期間におけるアナログ信号のサンプリングまでのずれ量の少なくとも一方を設定値以上にずらすものとなろう。 It may further comprise periodic noise determination means for determining whether or not the periodic noise is included in the subject image represented by the differential analog signal output from the difference circuit. In this case, the sampling control means detects the analog signal in the first sampling period from the output timing of the horizontal synchronization signal in response to the periodic noise determining means determining that the subject image contains a certain amount of periodic noise. At least one of the shift amount until the sampling of the signal and the shift amount from the output timing of the horizontal synchronization signal to the sampling of the analog signal in the second sampling period will be shifted to a set value or more.
　サンプリング制御手段を，基準信号出力回路からの第１の基準信号の出力タイミングおよび第２の基準信号の出力タイミングの少なくとも一方を非周期的とすることにより，第１のサンプリング期間におけるアナログ信号のサンプリングおよび第２のサンプリング期間におけるアナログ信号のサンプリングの少なくとも一方を非周期的とする第１のサンプリング処理を行った場合に差分回路から出力した差分アナログ信号によって表される被写体像に含まれている第１の周期性ノイズと，サンプリング制御手段を，第１の基準レベルおよび第２の基準レベルの少なくとも一方を非周期的に変更することにより，第１のサンプリング期間におけるアナログ信号のサンプリングおよび第２のサンプリング期間におけるアナログ信号のサンプリングの少なくとも一方を非周期的とする第２のサンプリング処理を行った場合に差分回路から出力した差分アナログ信号によって表される被写体像に含まれている第２の周期性ノイズとを比較する比較手段，ならびに比較手段によって第１の周期性ノイズよりも第２の周期性ノイズの方が大きいと判定された場合には第１のサンプリング処理をサンプリング制御手段に行わせ，比較手段によって第２の周期性ノイズよりも第１の周期性ノイズの方が大きいと判定された場合には第２のサンプリング処理をサンプリング制御手段に行わせる制御手段をさらに備えてもよい。 By sampling the analog signal in the first sampling period, the sampling control means makes at least one of the output timing of the first reference signal and the output timing of the second reference signal from the reference signal output circuit non-periodic. When the first sampling process in which at least one of the sampling of the analog signal in the second sampling period is aperiodic is performed, the first included in the subject image represented by the differential analog signal output from the differential circuit. 1 periodic noise and the sampling control means aperiodically changing at least one of the first reference level and the second reference level, thereby sampling the analog signal in the first sampling period and the second reference level. Sample analog signal during sampling period Comparing means for comparing the second periodic noise included in the subject image represented by the differential analog signal output from the difference circuit when the second sampling process is performed in which at least one of the two is aperiodic When the second periodic noise is determined to be larger than the first periodic noise by the comparing means, the first sampling processing is performed by the sampling control means, and the second period is detected by the comparing means. Control means for causing the sampling control means to perform the second sampling processing when it is determined that the first periodic noise is larger than the characteristic noise.
　水平同期信号を生成してパルス出力回路に出力する駆動回路をさらに備えてもよい。 A drive circuit that generates a horizontal synchronization signal and outputs it to the pulse output circuit may be further provided.
　第１の基準信号は，たとえば，第１のサンプリング期間において増加または減少が繰り返される。 The first reference signal is repeatedly increased or decreased in the first sampling period, for example.
　第２の基準信号は，たとえば，第２のサンプリング期間において増加または減少が繰り返される。 The second reference signal is repeatedly increased or decreased in the second sampling period, for example.
　たとえば，第１の基準信号は，リセット・パルスの出力から第１の一定期間経過後に出力され，かつ第２の基準信号は，リセット・パルスの出力から第２の一定期間経過後に出力される。この場合，サンプリング制御手段は，パルス出力回路によるリセット・パルスの出力タイミングを非周期的とすることが好ましい。 For example, the first reference signal is output after a first fixed period has elapsed from the output of the reset pulse, and the second reference signal is output after the second fixed period has elapsed from the output of the reset pulse. In this case, it is preferable that the sampling control means makes the reset pulse output timing by the pulse output circuit non-periodic.
　光電変換素子に蓄積されている信号電荷は，水平同期信号に同期するリセット・パルスによってリセットされ，読み出しパルスによって読み出される。光電変換素子から読み出された信号電荷は，増幅回路によってアナログ信号に変換される。リセット・パルス出力から読み出しパルス出力までの第１のサンプリング期間に増加または減少する第１の基準信号が出力され，リセット・パルス出力から読み出しパルス出力までの第２のサンプリング期間に増加または減少する第２の基準信号が出力される。第１の基準信号が第１の基準レベルとなると増幅回路から出力されるアナログ信号がサンプリングされ，第２の基準信号が第２の基準レベルとなると増幅回路から出力されるアナログ信号がサンプリングされる。２回のサンプリングで得られた２つのアナログ信号の差分信号が映像信号を表している。この発明によると，第１のサンプリング期間におけるアナログ信号のサンプリングおよび第２のサンプリング期間におけるアナログ信号のサンプリングの少なくとも一方が非周期的とされる。このように非周期的とされるので，得られる映像信号によって表される画像（被写体像）に周期性ノイズが生じてしまうことが未然に防止される。周期性ノイズが目立たなくなる。 The signal charge accumulated in the photoelectric conversion element is reset by a reset pulse synchronized with the horizontal synchronization signal and read by a read pulse. The signal charge read from the photoelectric conversion element is converted into an analog signal by the amplifier circuit. A first reference signal that increases or decreases in the first sampling period from the reset pulse output to the read pulse output is output, and a first reference signal that increases or decreases in the second sampling period from the reset pulse output to the read pulse output is output. 2 reference signals are output. The analog signal output from the amplifier circuit is sampled when the first reference signal reaches the first reference level, and the analog signal output from the amplifier circuit is sampled when the second reference signal reaches the second reference level. . A difference signal between two analog signals obtained by two samplings represents a video signal. According to the present invention, at least one of sampling of the analog signal in the first sampling period and sampling of the analog signal in the second sampling period is aperiodic. Since it is aperiodic in this way, it is possible to prevent the occurrence of periodic noise in the image (subject image) represented by the obtained video signal. Periodic noise is less noticeable.
ディジタル・カメラの電気的構成を示すブロック図である。It is a block diagram which shows the electric constitution of a digital camera. 撮像装置の電気的構成を示すブロック図である。It is a block diagram which shows the electric constitution of an imaging device. ＣＤＳ回路の電気的構成を示すブロック図である。It is a block diagram which shows the electric constitution of a CDS circuit. 水平同期信号ＨＤ，リセット・パルス等のタイム・チャートである。4 is a time chart of a horizontal synchronization signal HD, a reset pulse, and the like. ランプ波の出力タイミング等を示すタイム・チャートである。It is a time chart which shows the output timing etc. of a ramp wave. ランプ波の出力処理手順の一部を示すフローチャートである。It is a flowchart which shows a part of output process procedure of a ramp wave. ランプ波の出力処理手順の一部を示すフローチャートである。It is a flowchart which shows a part of output process procedure of a ramp wave. ランプ波の出力処理手順の一部を示すフローチャートである。It is a flowchart which shows a part of output process procedure of a ramp wave. ランプ波の出力処理手順の一部を示すフローチャートである。It is a flowchart which shows a part of output process procedure of a ramp wave. 第１の基準レベルと第２の基準レベルとの変更処理手順の一部を示すフローチャートである。It is a flowchart which shows a part of change process procedure of a 1st reference level and a 2nd reference level. 第１の基準レベルと第２の基準レベルとの変更処理手順の一部を示すフローチャートである。It is a flowchart which shows a part of change process procedure of a 1st reference level and a 2nd reference level. リセット・パルスの出力タイミングの変更処理手順を示すフローチャートである。It is a flowchart which shows the change process procedure of the output timing of a reset pulse. リセット・パルスの出力タイミングの変更処理手順を示すフローチャートである。It is a flowchart which shows the change process procedure of the output timing of a reset pulse. 第１のサンプリング・パルスおよび第２のサンプリング・パルスの出力タイミングをずらす処理手順を示すフローチャートである。It is a flowchart which shows the process sequence which shifts the output timing of a 1st sampling pulse and a 2nd sampling pulse. 第１のサンプリング処理または第２のサンプリング処理を決定する処理手順を示すフローチャートである。It is a flowchart which shows the process sequence which determines a 1st sampling process or a 2nd sampling process. 第２のランプ波の一例である。It is an example of the 2nd ramp wave. 周期性ノイズ，水平同期信号ＨＤ等のタイム・チャートである。6 is a time chart of periodic noise, horizontal synchronization signal HD, and the like. 筋状のノイズが現れている被写体像の一例である。It is an example of the to-be-photographed image which the stripe noise appears.
　図１は，この発明の実施例を示すもので，ディジタル・カメラ１の電気的構成を示すブロック図である。 FIG. 1 shows an embodiment of the present invention, and is a block diagram showing an electrical configuration of a digital camera 1.
　ディジタル・カメラ１の全体の動作は，制御装置11によって統括される。 The overall operation of the digital camera 1 is controlled by the control device 11.
　ディジタル・カメラ１には，制御装置11によって制御され，かつ駆動回路３によって駆動する撮像装置２（固体電子撮像装置）が含まれている。駆動回路３によって撮像装置２が駆動することにより，撮像装置２によって被写体が撮像され，被写体像を表す映像信号が撮像装置２から出力する。撮像装置２から出力した映像信号は，アナログ／ディジタル変換回路４に入力し，アナログ／ディジタル変換回路４においてディジタル画像データに変換される。 The digital camera 1 includes an imaging device 2 (solid-state electronic imaging device) controlled by a control device 11 and driven by a drive circuit 3. When the imaging device 2 is driven by the drive circuit 3, the subject is imaged by the imaging device 2, and a video signal representing the subject image is output from the imaging device 2. The video signal output from the imaging device 2 is input to the analog / digital conversion circuit 4 and converted into digital image data by the analog / digital conversion circuit 4.
　ディジタル画像データは，信号処理回路５に入力し，ガンマ補正，白バランス調整などの所定の信号処理が行われる。信号処理回路５から出力したディジタル画像データは表示制御回路６に与えられ，表示制御回路６の制御のもとに表示装置７の表示画面に被写体像が表示される。 Digital image data is input to the signal processing circuit 5 and subjected to predetermined signal processing such as gamma correction and white balance adjustment. The digital image data output from the signal processing circuit 5 is given to the display control circuit 6, and the subject image is displayed on the display screen of the display device 7 under the control of the display control circuit 6.
　シャッタ・ボタン14が押されると，シャッタ・レリーズ信号が制御装置11に入力する。すると，上述のように撮像装置２によって被写体が撮像され，被写体像を表す映像信号が撮像装置２から出力する。映像信号は，アナログ／ディジタル変換回路４においてディジタル画像データに変換され，信号処理回路５において所定の信号処理が行われる。信号処理回路５から出力したディジタル画像データは記録制御回路９に入力し，記録制御回路９によってメモリ・カード10にディジタル画像データが記録される。 When the shutter button 14 is pressed, a shutter release signal is input to the control device 11. Then, the subject is imaged by the imaging device 2 as described above, and a video signal representing the subject image is output from the imaging device 2. The video signal is converted into digital image data by the analog / digital conversion circuit 4, and predetermined signal processing is performed by the signal processing circuit 5. The digital image data output from the signal processing circuit 5 is input to the recording control circuit 9, and the digital image data is recorded on the memory card 10 by the recording control circuit 9.
　ディジタル・カメラ１には，様々な撮像モードを設定するモード・スイッチ13が設けられており，モード・スイッチ13から出力する撮像モード設定信号は，制御装置11に入力する。 The digital camera 1 is provided with a mode switch 13 for setting various imaging modes, and an imaging mode setting signal output from the mode switch 13 is input to the control device 11.
　また，表示装置７の表示画面には，タッチ・パネル８が形成されており，タッチ・パネル８を操作することにより，様々な指令を示す信号が発生し，それらの指令信号は制御装置11に入力する。さらに，制御装置11には，所定のデータを記憶するメモリ12が接続されている。 A touch panel 8 is formed on the display screen of the display device 7, and signals indicating various commands are generated by operating the touch panel 8, and these command signals are sent to the control device 11. input. Further, a memory 12 that stores predetermined data is connected to the control device 11.
　図２は，撮像装置２の電気的構成を示すブロック図である。 FIG. 2 is a block diagram showing an electrical configuration of the image pickup apparatus 2.
　図２に示す撮像装置２は，ＣＭＯＳ（Complementary Metal Oxide Semiconductor）型の撮像装置２である。撮像装置２は，ＣＣＤ(Charge Coupled Device)型のものでもよい。 The imaging device 2 shown in FIG. 2 is a CMOS (Complementary Metal Metal Oxide Semiconductor) type imaging device 2. The imaging device 2 may be of a CCD (Charge-Coupled Device) type.
　撮像装置２には，行方向（水平方向）および列方向（垂直方向）にそれぞれ複数の光電変換素子（フォトダイオード）22が配置されている。光電変換素子22には，ＦＤＡ（Floating Diffusion Amplifier）23(増幅回路)が接続されている。各列のＦＤＡ23は，列ごとに共通の垂直信号ライン24に接続されている。それぞれの垂直信号ライン24には，ＣＤＳ（correlated double sampling）回路30が接続されている。ＣＤＳ回路30の出力は出力ライン28に接続されている。撮像装置２には，ランプ波発生回路（基準信号発生回路，のこぎり波発生回路）27が含まれている。 In the imaging device 2, a plurality of photoelectric conversion elements (photodiodes) 22 are arranged in the row direction (horizontal direction) and the column direction (vertical direction), respectively. An FDA (Floating Diffusion Amplifier) 23 (amplifier circuit) is connected to the photoelectric conversion element 22. The FDA 23 of each column is connected to a common vertical signal line 24 for each column. A CDS (correlated double sampling) circuit 30 is connected to each vertical signal line 24. The output of the CDS circuit 30 is connected to the output line 28. The imaging device 2 includes a ramp wave generation circuit (reference signal generation circuit, sawtooth wave generation circuit) 27.
　各行の光電変換素子22には，行ごとに共通のリセット・パルス・ライン25および読み出しパルス・ライン26が接続されている。 A common reset pulse line 25 and readout pulse line 26 are connected to each row of photoelectric conversion elements 22.
　駆動回路３から撮像装置２に，水平同期信号ＨＤ（水平同期信号，Horizontal Driving pulse）が出力する。水平同期信号ＨＤはパルス出力回路21に入力する。すると，パルス出力回路21からリセット・パルス・ライン25に水平同期信号ＨＤに同期したリセット・パルスが行ごとに出力し，かつパルス出力回路21から読み出しパルス・ライン26に水平同期信号ＨＤに同期した読み出しパルスが行ごとに出力する。リセット・パルスは，光電変換素子22に蓄積されている信号電荷をリセットするパルスで，周期的な水平同期信号ＨＤに同期する。読み出しパルスは，光電変換素子に蓄積されている信号電荷を読み出すパルスである。パルス出力回路21からリセット・パルス・ライン25にリセット・パルスが行ごとに出力すると，リセット・パルスが出力されたリセット・パルス・ライン25に接続されている同一行の光電変換素子22にリセット・パルスが印加される。すると，リセット・パルスが印加された同一行の光電変換素子22がリセットされ，光電変換素子22に蓄積されている信号電荷が掃き出される（たとえば，不要電荷の基板掃き出し）。パルス出力回路21から読み出しパルス・ライン26に読み出しパルスが行ごとに出力すると，読み出しパルスが出力された読み出しパルス・ライン26に接続されている同一行の光電変換素子22に蓄積されている信号電荷がＦＤＡ23に与えられる。映像信号はＦＤＡ23によってアナログ信号（電圧信号）とされ，垂直信号ライン24に与えられる。アナログ信号は，垂直信号ライン24に接続されているＣＤＳ回路30に入力する。ＦＤＡ23が，パルス出力回路21からの読み出しパルスの出力に応じて，光電変換素子22に蓄積されている信号電荷をアナログ信号に変換して出力する増幅回路である。 The horizontal synchronization signal HD (horizontal synchronization signal, Horizontal Driving pulse) is output from the drive circuit 3 to the imaging device 2. The horizontal synchronization signal HD is input to the pulse output circuit 21. Then, a reset pulse synchronized with the horizontal synchronization signal HD is output from the pulse output circuit 21 to the reset pulse line 25 for each row, and the readout pulse line 26 from the pulse output circuit 21 is synchronized with the horizontal synchronization signal HD. A read pulse is output for each row. The reset pulse is a pulse for resetting the signal charge accumulated in the photoelectric conversion element 22, and is synchronized with the periodic horizontal synchronizing signal HD. The read pulse is a pulse for reading the signal charge accumulated in the photoelectric conversion element. When a reset pulse is output from the pulse output circuit 21 to the reset pulse line 25 for each row, the reset signal is reset to the photoelectric conversion element 22 in the same row connected to the reset pulse line 25 from which the reset pulse was output. A pulse is applied. Then, the photoelectric conversion elements 22 in the same row to which the reset pulse is applied are reset, and signal charges accumulated in the photoelectric conversion elements 22 are swept out (for example, unnecessary charges are swept out of the substrate). When a readout pulse is output from the pulse output circuit 21 to the readout pulse line 26 for each row, the signal charge accumulated in the photoelectric conversion elements 22 in the same row connected to the readout pulse line 26 from which the readout pulse is output. Is given to FDA23. The video signal is converted to an analog signal (voltage signal) by the FDA 23 and is given to the vertical signal line 24. The analog signal is input to the CDS circuit 30 connected to the vertical signal line 24. The FDA 23 is an amplifier circuit that converts the signal charge accumulated in the photoelectric conversion element 22 into an analog signal and outputs it in accordance with the output of the readout pulse from the pulse output circuit 21.
　パルス出力回路21から出力されるリセット・パルスは，ランプ波発生回路27にも入力する。詳しくは後述するように，リセット・パルスがランプ波発生回路27に入力することにより，ランプ波発生回路27から第１のランプ波Ｗ１および第２のランプ波Ｗ２(図４参照)が出力され，これらの第１のランプ波Ｗ１および第２のランプ波Ｗ２はＣＤＳ回路30に入力する。第１のランプ波Ｗ１が第１の基準レベルとなったタイミングでＣＤＳ回路30に入力したアナログ圧信号と，第２のランプ波Ｗ２が第２の基準レベルとなったタイミングでＣＤＳ回路30に入力したアナログ信号との差分信号がＣＤＳ回路30において算出される。算出された差分信号が，ＣＤＳ回路30から映像信号として出力ライン28を介して撮像装置２から出力する。 The reset pulse output from the pulse output circuit 21 is also input to the ramp wave generation circuit 27. As will be described in detail later, when the reset pulse is input to the ramp wave generation circuit 27, the ramp wave generation circuit 27 outputs the first ramp wave W1 and the second ramp wave W2 (see FIG. 4). The first ramp wave W1 and the second ramp wave W2 are input to the CDS circuit 30. The analog pressure signal input to the CDS circuit 30 when the first ramp wave W1 becomes the first reference level and the analog pressure signal input to the CDS circuit 30 when the second ramp wave W2 becomes the second reference level The CDS circuit 30 calculates a differential signal from the analog signal. The calculated difference signal is output from the imaging device 2 through the output line 28 as a video signal from the CDS circuit 30.
　各行の光電変換素子22ごとにリセット・パルスおよび読み出しパルスが与えられることにより，被写体像を表す映像信号が行ごとに撮像装置２から出力する。リセット・パルスおよび読み出しパルスは，列方向または列方向とは逆方向に順にパルス出力回路21から出力する。 When a reset pulse and a readout pulse are given to the photoelectric conversion elements 22 in each row, a video signal representing the subject image is output from the imaging device 2 for each row. The reset pulse and the readout pulse are output from the pulse output circuit 21 in order in the column direction or in the direction opposite to the column direction.
　図３は，ＣＤＳ回路30の電気的構成を示すブロック図である。図４は，ＣＤＳ回路30を構成する回路等を流れる信号のタイム・チャートである。 FIG. 3 is a block diagram showing an electrical configuration of the CDS circuit 30. As shown in FIG. FIG. 4 is a time chart of signals flowing through the circuits and the like constituting the CDS circuit 30.
　パルス出力回路21に水平同期信号ＨＤが入力し，時刻ｔ１において水平同期信号ＨＤが立ち上がると，水平同期信号ＨＤの出力後の時刻ｔ２から時刻ｔ３の間にパルス出力回路21からリセット・パルスが出力する。リセット・パルスは，光電変換素子22に与えられ，光電変換素子22に蓄積されている不要な信号電荷が掃き出される。リセット・パルスの出力から第１の一定期間が経過し，時刻ｔ４となると，ランプ波発生回路27(基準信号出力回路)から第１のランプ波(第１の基準信号)Ｗ１が出力する。第１のランプ波Ｗ１は，ＣＤＳ回路30に含まれている比較回路33に入力する。第１のランプ波Ｗ１は，時間の経過とともに一定レベルまで減少(増加でもよい)する。 When the horizontal synchronization signal HD is input to the pulse output circuit 21 and the horizontal synchronization signal HD rises at time t1, a reset pulse is output from the pulse output circuit 21 between time t2 and time t3 after the output of the horizontal synchronization signal HD. To do. The reset pulse is given to the photoelectric conversion element 22, and unnecessary signal charges accumulated in the photoelectric conversion element 22 are swept out. When the first fixed period elapses from the output of the reset pulse and time t4 is reached, the first ramp wave (first reference signal) W1 is output from the ramp wave generation circuit 27 (reference signal output circuit). The first ramp wave W1 is input to the comparison circuit 33 included in the CDS circuit 30. The first ramp wave W1 decreases (may be increased) to a certain level over time.
　ＦＤＡ23から出力し，ＣＤＳ回路30に入力したアナログ信号は，第１のサンプリング回路31，第２のサンプリング回路32および比較回路33に入力する。比較回路33において，ＦＤＡ23から出力したアナログ信号のレベルとランプ波発生回路27から出力した第１のランプ波Ｗ１のレベルとが比較される。時刻ｔ５となり，第１のランプ波Ｗ１のレベルが，比較回路33にあらかじめ設定されている第１の基準レベルＶ１と等しくなると，時刻ｔ５から時刻ｔ６の間に，比較回路33から第１のサンプリング・パルスが出力する。第１のサンプリング・パルスは，第１のサンプリング回路31に入力し，第１のサンプリング回路31に入力しているアナログ信号が第１のサンプリング回路31においてサンプリングされる。第１のサンプリング回路31においてサンプリングされた信号がリセット信号（第１のアナログ信号）として第１のサンプリング回路31から出力し，差分回路34のマイナス入力端子に入力する。 The analog signal output from the FDA 23 and input to the CDS circuit 30 is input to the first sampling circuit 31, the second sampling circuit 32, and the comparison circuit 33. In the comparison circuit 33, the level of the analog signal output from the FDA 23 is compared with the level of the first ramp wave W1 output from the ramp wave generation circuit 27. At time t5, when the level of the first ramp wave W1 becomes equal to the first reference level V1 preset in the comparison circuit 33, the first sampling from the comparison circuit 33 is performed between the time t5 and the time t6.・ Pulse is output. The first sampling pulse is input to the first sampling circuit 31, and the analog signal input to the first sampling circuit 31 is sampled by the first sampling circuit 31. The signal sampled in the first sampling circuit 31 is output from the first sampling circuit 31 as a reset signal (first analog signal) and input to the negative input terminal of the difference circuit 34.
　リセット・パルスの出力から第２の一定期間が経過し，時刻ｔ７となると，パルス出力回路21から読み出しパルスが出力する。パルス出力回路21によるリセット・パルスの出力からパルス出力回路21による読み出しパルスの出力までを第１のサンプリング期間ということにする。第１のランプ波Ｗ１(第１の基準信号)は第１のサンプリング期間に増加または減少するということができる。 When the second fixed period has elapsed from the output of the reset pulse and when time t7 is reached, a read pulse is output from the pulse output circuit 21. The period from the reset pulse output by the pulse output circuit 21 to the read pulse output by the pulse output circuit 21 is referred to as a first sampling period. It can be said that the first ramp wave W1 (first reference signal) increases or decreases during the first sampling period.
　時刻ｔ７から時刻ｔ８の間にパルス出力回路21から読み出しパルスが出力すると，光電変換素子22に蓄積されている信号電荷がＦＤＡ23に与えられ，ＦＤＡ23からアナログ信号が出力する。ＦＤＡ23から出力したアナログ信号は，ＣＤＳ回路30に含まれている第１のサンプリング回路31，第２のサンプリング回路32および比較回路33に入力する。また，リセット・パルスから第２の一定期間が経過し，時刻ｔ９となると，ランプ波発生回路27から第２のランプ波Ｗ２(第２の基準信号)が出力し，第２のランプ波Ｗ２は比較回路33に入力する。比較回路33において，ＦＤＡ23から出力されたアナログ信号のレベルと第２のランプ波Ｗ２のレベルとが比較される。時刻ｔ10において，第２のランプ波Ｗ２のレベルが比較回路33にあらかじめ設定されている第２の基準レベルＶ２と等しくなると，時刻ｔ10から時刻ｔ11の間に比較回路33から第２のサンプリング・パルスが出力する。第２のサンプリング・パルスは第２のサンプリング回路32に入力し，第２のサンプリング回路32に入力しているアナログ信号が第２のサンプリング回路32においてサンプリングされる。第２のサンプリング回路32においてサンプリングされた信号がデータ信号(第２のアナログ信号)として第２のサンプリング回路32から出力し，差分回路34のプラス入力端子に入力する。 When a read pulse is output from the pulse output circuit 21 between time t7 and time t8, the signal charge accumulated in the photoelectric conversion element 22 is given to the FDA 23, and an analog signal is output from the FDA 23. The analog signal output from the FDA 23 is input to the first sampling circuit 31, the second sampling circuit 32, and the comparison circuit 33 included in the CDS circuit 30. When the second fixed period has elapsed from the reset pulse and time t9 is reached, the ramp wave generating circuit 27 outputs the second ramp wave W2 (second reference signal), and the second ramp wave W2 is Input to the comparison circuit 33. The comparison circuit 33 compares the level of the analog signal output from the FDA 23 with the level of the second ramp wave W2. When the level of the second ramp wave W2 becomes equal to the second reference level V2 preset in the comparison circuit 33 at time t10, the second sampling pulse is output from the comparison circuit 33 between time t10 and time t11. Is output. The second sampling pulse is input to the second sampling circuit 32, and the analog signal input to the second sampling circuit 32 is sampled by the second sampling circuit 32. The signal sampled in the second sampling circuit 32 is output from the second sampling circuit 32 as a data signal (second analog signal) and input to the plus input terminal of the difference circuit 34.
　その後，次の水平同期信号ＨＤが時刻ｔ12において立下り，時刻ｔ13となると次のリセット・パルスが出力する。読み出しパルスの出力からリセット・パルスの出力までを第２のサンプリング期間ということにする。第２のランプ波Ｗ２(第２の基準信号)は第２のサンプリング期間に増加または減少するということができる。 Thereafter, the next horizontal synchronizing signal HD falls at time t12, and the next reset pulse is output at time t13. The period from the output of the readout pulse to the output of the reset pulse is referred to as a second sampling period. It can be said that the second ramp wave W2 (second reference signal) increases or decreases during the second sampling period.
　第１のサンプリング回路31におけるサンプリングにより得られたリセット信号(第１のアナログ信号)と，第２のサンプリング回路32におけるサンプリングにより得られたリセット信号(第２のアナログ信号)と，の差分を表す差分アナログ信号が映像信号として差分回路34から出力する。 It represents the difference between the reset signal (first analog signal) obtained by sampling in the first sampling circuit 31 and the reset signal (second analog signal) obtained by sampling in the second sampling circuit 32. The difference analog signal is output from the difference circuit 34 as a video signal.
　図５は，水平同期信号ＨＤ，リセット・パルスおよびランプ波の出力タイミングのタイム・チャートである。 FIG. 5 is a time chart of the output timing of the horizontal synchronization signal HD, the reset pulse, and the ramp wave.
　上述のように，周期的な水平同期信号ＨＤが出力された後にリセット・パルスが出力される。 As described above, the reset pulse is output after the periodic horizontal synchronizing signal HD is output.
　図５では，ランプ波の出力タイミングが３種類示されている。これらのランプ波の出力タイミングは，制御装置11（サンプリング制御手段）によって制御される。 FIG. 5 shows three types of ramp wave output timing. The output timing of these ramp waves is controlled by the control device 11 (sampling control means).
　第１の出力タイミングは，リセット・パルスの出力後，Δｔ１の期間の経過後に第１のランプ波Ｗ１の出力が開始し（図４に示したように，第１のランプ波Ｗ１の減少が開始する），リセット・パルスの出力後Δｔ２の期間の経過後に第２のランプ波Ｗ２の出力が開始する（図４に示したように，第２のランプ波Ｗ２の減少が開始する）。 In the first output timing, after the reset pulse is output, the output of the first ramp wave W1 starts after the period of Δt1 has elapsed (as shown in FIG. 4, the decrease of the first ramp wave W1 starts. The second ramp wave W2 starts to be output after the lapse of the period Δt2 after the reset pulse is output (as shown in FIG. 4, the second ramp wave W2 starts to decrease).
　第１の出力タイミングでは，リセット・パルスの出力タイミングが周期的（水平同期信号ＨＤの周期に一致）であると，第１のランプ波Ｗ１の出力タイミングおよび第２のランプ波Ｗ２の出力タイミングのいずれも周期的となる。このため，図17を参照して説明したように周期性ノイズが存在した場合，図18に示すように被写体像110に筋状のノイズ111が現れてしまう。ノイズ111を抑えるために，この実施例においては後述するように，第１の出力タイミングでは，リセット・パルスが非周期的にパルス出力回路21から出力する。この明細書において「非周期的」とは，一定の現象(パルス出力，基準信号出力，基準レベルの変更)が一定時間ごとに起きる「周期的」とは異なればよい。ランダムなものでもよいし，１つの被写体像を表示する間に２度と同じ状態が起きないものでもよい。周期性ノイズの周期と一致しなければよい。 In the first output timing, if the reset pulse output timing is periodic (corresponding to the cycle of the horizontal synchronizing signal HD), the output timing of the first ramp wave W1 and the output timing of the second ramp wave W2 Both are periodic. Therefore, when periodic noise exists as described with reference to FIG. 17, a streak-like noise 111 appears in the subject image 110 as shown in FIG. In order to suppress the noise 111, in this embodiment, as will be described later, a reset pulse is aperiodically output from the pulse output circuit 21 at the first output timing. In this specification, “non-periodic” may be different from “periodic” in which a certain phenomenon (change in pulse output, reference signal output, or reference level) occurs at regular intervals. Random ones may be used, and one subject image may not be generated twice during the display of one subject image. It does not have to coincide with the period of periodic noise.
　第２の出力タイミングは，第１のランプ波Ｗ１の出力タイミングが水平同期信号ＨＤの１周期ごとに徐々に遅れる(ずれる)ものである。第１回目の水平走査期間（水平同期信号の出力間隔であり，水平同期信号の立ち上がりから次の水平同期信号の立ち上がりまでの期間を水平走査期間ということにする。）では，第１のランプ波Ｗ１の出力は，リセット・パルスの出力からΔｔ１の期間の経過後に開始し，第２のランプ波Ｗ２の出力は，リセット・パルスの出力からΔｔ２(Δｔ２はΔｔ１より大きい)の期間の経過後に開始する。第１回目の水平走査期間の次の第２回目の水平走査期間では，第１のランプ波Ｗ１の出力は，第１回目の水平走査期間の出力タイミングよりも遅れ，リセット・パルスの出力からΔｔ１＋Δ１の期間の経過後に開始し，第２のランプ波Ｗ２の出力は，リセット・パルスの出力からΔｔ２＋Δ１の期間の経過後に開始する。さらに，第２回目の水平走査期間の次の第３回目の水平走査期間では，第１のランプ波Ｗ１の出力は，第２回目の水平走査期間の出力タイミングよりもさらに遅れ，リセット・パルスの出力からΔｔ１＋Δ２(Δ２はΔ１より大きい)の期間の経過後に開始する。その後の水平走査期間も同様である。 The second output timing is such that the output timing of the first ramp wave W1 is gradually delayed (shifted) for each cycle of the horizontal synchronization signal HD. In the first horizontal scanning period (the horizontal sync signal output interval, the period from the rise of the horizontal sync signal to the rise of the next horizontal sync signal is referred to as the horizontal scan period). The output of W1 starts after the lapse of Δt1 from the output of the reset pulse, and the output of the second ramp wave W2 starts after the lapse of Δt2 (Δt2 is greater than Δt1) from the output of the reset pulse. To do. In the second horizontal scanning period subsequent to the first horizontal scanning period, the output of the first ramp wave W1 is delayed from the output timing of the first horizontal scanning period, and Δt1 + Δ1 from the output of the reset pulse. The output of the second ramp wave W2 starts after the lapse of Δt2 + Δ1 from the output of the reset pulse. Further, in the third horizontal scanning period subsequent to the second horizontal scanning period, the output of the first ramp wave W1 is further delayed from the output timing of the second horizontal scanning period, and the reset pulse is output. It starts after a period of Δt1 + Δ2 (Δ2 is larger than Δ1) from the output. The same applies to the subsequent horizontal scanning period.
　第２の出力タイミングでは，第１のランプ波Ｗ１および第２のランプ波Ｗ２のいずれの出力タイミングも非周期的となっている。第１のランプ波Ｗ１および第２のランプ波Ｗ２の出力タイミングが非周期的となると，第１のランプ波Ｗ１のレベルが第１の基準レベルＶ１と等しくなるタイミングも，第２のランプ波Ｗ２のレベルが第２の基準レベルＶ２と等しくなるタイミングも，非周期的となる。 At the second output timing, the output timing of both the first ramp wave W1 and the second ramp wave W2 is aperiodic. When the output timing of the first ramp wave W1 and the second ramp wave W2 is aperiodic, the timing at which the level of the first ramp wave W1 becomes equal to the first reference level V1 is also the second ramp wave W2. The timing at which the level becomes equal to the second reference level V2 is also aperiodic.
　このために，制御装置11（サンプリング制御手段）によって，第１のサンプリング回路31による第１のサンプリング期間におけるリセット信号(アナログ信号)のサンプリングおよび第２のサンプリング回路32による第２のサンプリング期間におけるデータ信号(アナログ信号)のサンプリングのいずれも非周期的となる。これにより，図17を参照して説明したように，撮像装置２が周期性ノイズの影響を受け，ランプ波(第１のランプ波Ｗ１，第２のランプ波Ｗ２)に周期性ノイズが含まれた場合でも，差分回路34から出力する映像信号からは周期性ノイズが排除される。図18に示したように被写体像110に筋状のノイズ111が発生してしまうことが未然に防止される。 For this purpose, the control device 11 (sampling control means) samples the reset signal (analog signal) in the first sampling period by the first sampling circuit 31 and the data in the second sampling period by the second sampling circuit 32. Any sampling of the signal (analog signal) is aperiodic. As a result, as described with reference to FIG. 17, the imaging device 2 is affected by the periodic noise, and the ramp wave (first ramp wave W1, second ramp wave W2) includes the periodic noise. Even in such a case, the periodic noise is excluded from the video signal output from the difference circuit. As shown in FIG. 18, the streak noise 111 is prevented from occurring in the subject image 110 in advance.
　第３の出力タイミングにおいては，第１のランプ波Ｗ１の出力タイミングはリセット・パルスの出力からΔｔ１の期間の経過後であるが，第２のランプ波Ｗ２の出力タイミングが水平同期信号ＨＤの１周期ごとに徐々に遅れる(ずれる)ものである。第１回目の水平走査期間では，第２のランプ波Ｗ２の出力は，リセット・パルスの出力からΔｔ２の期間の経過後に開始する。第１回目の水平走査期間での次の第２回目の水平走査期間では，第２のランプ波Ｗ２の出力タイミングは第１回目の水平走査期間の出力タイミングよりも遅れ，リセット・パルスの出力からΔｔ２＋Δ１の期間の経過後に開始する。第２回目の水平走査期間の次の第３回目の水平走査期間では，第２のランプ波Ｗ２の出力タイミングは第２回目の水平走査期間での出力タイミングよりもさらに遅れ，リセット・パルスの出力からΔｔ２＋Δ２(Δ２はΔ１より大きい)の期間の経過後に開始する。その後の水平走査期間も同様である。 At the third output timing, the output timing of the first ramp wave W1 is after the lapse of Δt1 from the output of the reset pulse, but the output timing of the second ramp wave W2 is 1 of the horizontal synchronization signal HD. It gradually delays (shifts) every cycle. In the first horizontal scanning period, the output of the second ramp wave W2 starts after the period of Δt2 has elapsed from the output of the reset pulse. In the second horizontal scanning period next to the first horizontal scanning period, the output timing of the second ramp wave W2 is delayed from the output timing of the first horizontal scanning period, and from the reset pulse output. It starts after the period of Δt2 + Δ1. In the third horizontal scanning period subsequent to the second horizontal scanning period, the output timing of the second ramp wave W2 is further delayed than the output timing in the second horizontal scanning period, and the reset pulse is output. To Δt2 + Δ2 (Δ2 is greater than Δ1). The same applies to the subsequent horizontal scanning period.
　第３の出力タイミングでは，第１のランプ波Ｗ１の出力タイミングは周期的であるが，第２のランプ波Ｗ２の出力タイミングが非周期的となっている。第２のランプ波Ｗ２の出力タイミングが非周期的となると，第２のランプ波Ｗ２のレベルが第２の基準レベルＶ２と等しくなるタイミングが，非周期的となる。 At the third output timing, the output timing of the first ramp wave W1 is periodic, but the output timing of the second ramp wave W2 is aperiodic. When the output timing of the second ramp wave W2 becomes aperiodic, the timing at which the level of the second ramp wave W2 becomes equal to the second reference level V2 becomes aperiodic.
　このために，制御装置11によって，第１のサンプリング回路31による第１のサンプリング期間におけるリセット信号(アナログ信号)のサンプリングは周期的であるが，第２のサンプリング回路32による第２のサンプリング期間におけるデータ信号(アナログ信号)のサンプリングが非周期的となる。映像信号は，差分回路34によって，非周期的なサンプリングにより得られるデータ信号と周期的なサンプリングにより得られるリセット信号との差分によって表されるから，図17を参照して説明したように，撮像装置２が周期性ノイズの影響を受けた場合でも，差分回路34から出力する映像信号からは周期性ノイズが排除される。図18に示したように被写体像110に筋状のノイズ111が発生してしまうことが未然に防止される。 Therefore, the control device 11 periodically samples the reset signal (analog signal) in the first sampling period by the first sampling circuit 31, but the second sampling circuit 32 in the second sampling period. Sampling of the data signal (analog signal) becomes aperiodic. Since the video signal is represented by the difference circuit 34 by the difference between the data signal obtained by non-periodic sampling and the reset signal obtained by periodic sampling, imaging is performed as described with reference to FIG. Even when the apparatus 2 is affected by the periodic noise, the periodic noise is excluded from the video signal output from the difference circuit 34. As shown in FIG. 18, the streak noise 111 is prevented from occurring in the subject image 110 in advance.
　第３のタイミングでは，第１のランプ波Ｗ１の出力タイミングが周期的であり，第２のランプ波Ｗ２の出力タイミングが非周期的であるが，第１のランプ波Ｗ１の出力タイミングを非周期的とし，第２のランプ波Ｗ２の出力タイミングを周期的としてもよい。 At the third timing, the output timing of the first ramp wave W1 is periodic and the output timing of the second ramp wave W2 is aperiodic, but the output timing of the first ramp wave W1 is aperiodic. The output timing of the second ramp wave W2 may be periodic.
　第２の出力タイミングまたは第３の出力タイミングのように，ランプ波発生回路27からの第１のランプ波Ｗ１の出力タイミングおよび第２のランプ波Ｗ２の出力タイミングの少なくとも一方を非周期的とすることにより，制御装置11(サンプリング制御手段)は，第１のサンプリング期間におけるリセット信号（アナログ信号）のサンプリングおよび第２のサンプリング期間におけるデータ信号（アナログ信号）のサンプリングの少なくとも一方を非周期的とすることができる。 As in the second output timing or the third output timing, at least one of the output timing of the first ramp wave W1 and the output timing of the second ramp wave W2 from the ramp wave generation circuit 27 is aperiodic. Accordingly, the control device 11 (sampling control means) sets at least one of sampling of the reset signal (analog signal) in the first sampling period and sampling of the data signal (analog signal) in the second sampling period to be aperiodic. can do.
　第２の出力タイミングでは，第１のサンプリング期間におけるリセット信号のサンプリングと第２のサンプリング期間におけるデータ信号のサンプリングとのサンプリング間隔がΔｔ２－Δｔ１となり，一定であるが，このようにサンプリング間隔が一定となってもよい。また，第３の出力タイミングでは，第１のサンプリング期間におけるリセット信号のサンプリングと第２のサンプリング期間におけるデータ信号のサンプリングとのサンプリング間隔が水平同期信号ＨＤの周期ごとに異なっている。このようにサンプリング間隔が水平同期信号ＨＤの周期ごとに異なってもよい。 At the second output timing, the sampling interval between the sampling of the reset signal in the first sampling period and the sampling of the data signal in the second sampling period is Δt2−Δt1, which is constant. In this way, the sampling interval is constant. It may be. Further, at the third output timing, the sampling interval between the sampling of the reset signal in the first sampling period and the sampling of the data signal in the second sampling period is different for each period of the horizontal synchronization signal HD. As described above, the sampling interval may be different for each cycle of the horizontal synchronization signal HD.
　図６および図７は，第１のランプ波Ｗ１の出力タイミングと第２のランプ波Ｗ２の出力タイミングとを決定する処理手順を示すフローチャートである。図６および図７は，図５の第２の出力タイミングの処理手順を示している。 6 and 7 are flowcharts showing a processing procedure for determining the output timing of the first ramp wave W1 and the output timing of the second ramp wave W2. 6 and 7 show a processing procedure of the second output timing of FIG.
　パルス出力回路21からリセット・パルスが出力されると(ステップ41でＹＥＳ)，リセット・パルスの出力からΔｔ１の期間を経過して徐々に減少する第１のランプ波Ｗ１がランプ波発生回路27から出力する(ステップ42)。第１のランプ波Ｗ１が第１の基準レベルＶ１と等しくなると，ＦＤＡ23から出力されるアナログ信号が第１のサンプリング回路31においてサンプリングされ，リセット信号が得られる。 When a reset pulse is output from the pulse output circuit 21 (YES in step 41), a first ramp wave W1 that gradually decreases after the period of Δt1 from the output of the reset pulse is generated from the ramp wave generation circuit 27. Output (step 42). When the first ramp wave W1 becomes equal to the first reference level V1, the analog signal output from the FDA 23 is sampled by the first sampling circuit 31, and a reset signal is obtained.
　第１のランプ波Ｗ１の出力から一定期間（Δｔ２－Δｔ１）経過すると(ステップ43でＹＥＳ)，すなわち，リセット・パルスの出力からΔｔ２の期間経過すると，ランプ波発生回路27から第２のランプ波Ｗ２が出力する(ステップ44)。第２のランプ波Ｗ２が第２の基準レベルＶ２と等しくなると，ＦＤＡ23から出力されるアナログ信号が第２のサンプリング回路32においてサンプリングされ，データ信号が得られる。 When a certain period (Δt2−Δt1) has elapsed from the output of the first ramp wave W1 (YES in step 43), that is, when a period of Δt2 has elapsed from the output of the reset pulse, the ramp wave generating circuit 27 outputs the second ramp wave. W2 is output (step 44). When the second ramp wave W2 becomes equal to the second reference level V2, the analog signal output from the FDA 23 is sampled by the second sampling circuit 32 to obtain a data signal.
　第１のランプ波Ｗ１と第２のランプ波Ｗ２とが出力されると，第１のランプ波Ｗ１の出力タイミングをずらすように制御装置11によってランプ波発生回路27が設定される(ステップ45)。撮像装置２の制御が終了でなければ(ステップ46でＮＯ)，１水平走査期間が経過すると(ステップ47)，次の水平走査期間が開始し，パルス出力回路21からリセット・パルスが出力する(ステップ41でＹＥＳ)。次の水平走査期間では，第１のランプ波Ｗ１の出力タイミングがずれる。第１のランプ波Ｗ１と第２のランプ波Ｗ２とが出力されると，第１のランプ波Ｗ１の出力タイミングをずらす処理が行われ，第１のランプ波Ｗ１のサンプリングが非周期となる。第２のランプ波Ｗ２は第１のランプ波Ｗ１の一定期間経過後に出力されるから第２のランプ波Ｗ２も非周期となる。 When the first ramp wave W1 and the second ramp wave W2 are output, the control unit 11 sets the ramp wave generation circuit 27 so as to shift the output timing of the first ramp wave W1 (step 45). . If the control of the imaging device 2 is not completed (NO in step 46), when one horizontal scanning period has elapsed (step 47), the next horizontal scanning period starts and a reset pulse is output from the pulse output circuit 21 ( YES at step 41). In the next horizontal scanning period, the output timing of the first ramp wave W1 is shifted. When the first ramp wave W1 and the second ramp wave W2 are output, a process for shifting the output timing of the first ramp wave W1 is performed, and the sampling of the first ramp wave W1 becomes aperiodic. Since the second ramp wave W2 is output after a lapse of a certain period of the first ramp wave W1, the second ramp wave W2 is also non-periodic.
　図８および図９は，第１のランプ波Ｗ１の出力タイミングと第２のランプ波Ｗ２の出力タイミングとを決定する他の処理手順を示すフローチャートである。図８および図９は，図５の第３の出力タイミングの処理手順を示している。 8 and 9 are flowcharts showing other processing procedures for determining the output timing of the first ramp wave W1 and the output timing of the second ramp wave W2. 8 and 9 show a processing procedure of the third output timing of FIG.
　パルス出力回路21からリセット・パルスが出力される(ステップ51でＹＥＳ)。リセット・パルスの出力からΔｔ１の期間を経過すると(ステップ52でＹＥＳ)，パルス出力回路21から第１のランプ波Ｗ１が出力する(ステップ53)。第１のランプ波Ｗ１が第１の基準レベルＶ１と等しくなると，ＦＤＡ23から出力されるアナログ信号が第１のサンプリング回路31においてサンプリングされ，リセット信号が得られる。 The reset pulse is output from the pulse output circuit 21 (YES in step 51). When the period Δt1 has elapsed from the reset pulse output (YES in step 52), the first ramp wave W1 is output from the pulse output circuit 21 (step 53). When the first ramp wave W1 becomes equal to the first reference level V1, the analog signal output from the FDA 23 is sampled by the first sampling circuit 31, and a reset signal is obtained.
　リセット・パルスの出力からΔｔ２の期間を経過すると(ステップ54でＹＥＳ)，ランプ波発生回路27から第２のランプ波Ｗ２が出力する(ステップ55)。第２のランプ波Ｗ２が第２の基準レベルＶ２と等しくなると，ＦＤＡ23から出力されるアナログ信号が第２のサンプリング回路32においてサンプリングされ，データ信号が得られる。 When the period Δt2 has elapsed from the output of the reset pulse (YES in step 54), the second ramp wave W2 is output from the ramp wave generation circuit 27 (step 55). When the second ramp wave W2 becomes equal to the second reference level V2, the analog signal output from the FDA 23 is sampled by the second sampling circuit 32 to obtain a data signal.
　第１のランプ波Ｗ１と第２のランプ波Ｗ２とが出力されると，第２のランプ波Ｗ２の出力タイミングをずらす(遅らせる)ように制御装置11によってパルス出力回路21が制御される(ステップ56)。撮像装置２の制御が終了でなければ(ステップ57でＮＯ)，１水平走査期間が経過すると(ステップ58でＹＥＳ)，次の水平走査期間が開始し，パルス出力回路21からリセット・パルスが出力する(ステップ51でＹＥＳ)。リセット・パルスの出力からΔｔ１の期間が経過すると(ステップ52でＹＥＳ)，再び第１のランプ波Ｗ１が出力し(ステップ53)，リセット・パルスの出力からΔｔ２＋Δ１の期間が経過すると(ステップ54)，第２のランプ波Ｗ２が出力する(ステップ55)。第１のランプ波Ｗ１と第２のランプ波Ｗ２とが出力されると，第２のランプ波Ｗ２を出力するタイミングを決定する期間のずらしが繰り返される。第２のランプ波Ｗ２のサンプリングが非周期となる。 When the first ramp wave W1 and the second ramp wave W2 are output, the pulse output circuit 21 is controlled by the controller 11 to shift (delay) the output timing of the second ramp wave W2 (step) 56). If the control of the imaging device 2 is not completed (NO in step 57), when one horizontal scanning period has elapsed (YES in step 58), the next horizontal scanning period starts and a reset pulse is output from the pulse output circuit 21. (YES in step 51). When the period of Δt1 has elapsed from the output of the reset pulse (YES in step 52), the first ramp wave W1 is output again (step 53), and when the period of Δt2 + Δ1 has elapsed from the output of the reset pulse (step 54). , The second ramp wave W2 is output (step 55). When the first ramp wave W1 and the second ramp wave W2 are output, the shift of the period for determining the timing for outputting the second ramp wave W2 is repeated. Sampling of the second ramp wave W2 is non-periodic.
　図10および図11は，第１の基準レベルＶ１と第２の基準レベルＶ２とを変更する処理手順を示すフローチャートである。 FIG. 10 and FIG. 11 are flowcharts showing a processing procedure for changing the first reference level V1 and the second reference level V2.
　図10および図11に示す処理手順は，第１のサンプリング期間におけるサンプリングに利用される第１の基準レベルＶ１と第２のサンプリング期間におけるサンプリングに利用される第２の基準レベルＶ２とを，１水平走査期間ごとに変更することにより，第１のサンプリング期間におけるサンプリングと第２のサンプリング期間におけるサンプリングとの少なくとも一方を非周期的とするものである。 The processing procedure shown in FIGS. 10 and 11 includes a first reference level V1 used for sampling in the first sampling period and a second reference level V2 used for sampling in the second sampling period. By changing every horizontal scanning period, at least one of sampling in the first sampling period and sampling in the second sampling period is made aperiodic.
　パルス出力回路21からリセット・パルスが出力されると(ステップ61でＹＥＳ)，リセット・パルスの出力からΔｔ１の期間の経過後にランプ波発生回路27から第１のランプ波Ｗ１が出力する(ステップ62)。第１のランプ波Ｗ１が第１の基準レベルＶ１と等しくなると(ステップ63でＹＥＳ)，第１のサンプリング回路31に第１のサンプリング・パルスが入力する。ＦＤＡ23から出力したアナログ信号が第１のサンプリング回路31によってサンプリングされ，リセット信号が得られる。 When the reset pulse is output from the pulse output circuit 21 (YES in step 61), the first ramp wave W1 is output from the ramp wave generation circuit 27 after a period of Δt1 has elapsed from the output of the reset pulse (step 62). ). When the first ramp wave W1 becomes equal to the first reference level V1 (YES in step 63), the first sampling pulse is input to the first sampling circuit 31. The analog signal output from the FDA 23 is sampled by the first sampling circuit 31, and a reset signal is obtained.
　リセット・パルスの出力からΔｔ２の期間の経過後にランプ波発生回路27から第２のランプ波Ｗ２が出力する(ステップ65)。第２のランプ波Ｗ２が第２の基準レベルＶ２と等しくなると(ステップ66でＹＥＳ)，第２のサンプリング回路32に第２のサンプリング・パルスが入力する。ＦＤＡ23から出力したアナログ信号が第２のサンプリング回路32によってサンプリングされ，データ信号が得られる。 The second ramp wave W2 is output from the ramp wave generation circuit 27 after the lapse of Δt2 from the reset pulse output (step 65). When the second ramp wave W2 becomes equal to the second reference level V2 (YES in step 66), the second sampling pulse is input to the second sampling circuit 32. The analog signal output from the FDA 23 is sampled by the second sampling circuit 32 to obtain a data signal.
　第１のサンプリング回路31における第１のサンプリング期間におけるサンプリングおよび第２のサンプリング回路32における第２のサンプリング期間におけるサンプリングが行われると，ＣＤＳ回路30に含まれる比較回路33に設定されている第１の基準レベルＶ１および第２の基準レベルＶ２が制御装置11によって変更させられる(ステップ68)。もっとも，第１の基準レベルＶ１および第２の基準レベルＶ２の両方の基準レベルが変更させられなくとも，第１の基準レベルＶ１および第２の基準レベルＶ２のいずれか一方の基準レベルが変更されればよい。 When sampling in the first sampling period in the first sampling circuit 31 and sampling in the second sampling period in the second sampling circuit 32 are performed, the first circuit set in the comparison circuit 33 included in the CDS circuit 30 is set. The reference level V1 and the second reference level V2 are changed by the control device 11 (step 68). However, even if the reference levels of both the first reference level V1 and the second reference level V2 are not changed, one of the first reference level V1 and the second reference level V2 is changed. Just do it.
　撮像装置２の制御が終了でなければ(ステップ69でＮＯ)，１水平走査期間が経過すると(ステップ70でＹＥＳ)，次の水平走査期間が開始し，パルス出力回路21からリセット・パルスが出力する(ステップ61でＹＥＳ)。その後，第１のランプ波Ｗ１が出力され，出力された第１のランプ波Ｗ１のレベルが第１の基準レベルＶ１と等しくなると(ステップ62，ステップ63でＹＥＳ)，第１のサンプリング回路31によるサンプリングが行われる。また，第２のランプ波Ｗ２が出力され，出力された第２のランプ波Ｗ２のレベルが第２の基準レベルＶ２と等しくなると(ステップ65，ステップ66でＹＥＳ)，第２のサンプリング回路32によるサンプリングが行われる。第１のサンプリング回路31によるサンプリングおよび第２のサンプリング回路32によるサンプリングが行われると，第１の基準レベルＶ１および第２の基準レベルＶ２が変更(水平走査期間ごとに異なる値に変更)させられるから，第１の基準レベルＶ１と第１のランプ波Ｗ１のレベルとが等しくなることによって行われる第１のサンプリング回路31によるサンプリングおよび第２の基準レベルＶ２と第２のランプ波Ｗ２のレベルとが等しくなることによって行われる第２のサンプリング回路32によるサンプリングのタイミングが非周期的となる。 If the control of the imaging device 2 is not completed (NO in step 69), when one horizontal scanning period has elapsed (YES in step 70), the next horizontal scanning period starts and a reset pulse is output from the pulse output circuit 21. (YES in step 61). Thereafter, when the first ramp wave W1 is output and the level of the output first ramp wave W1 becomes equal to the first reference level V1 (YES in step 62 and step 63), the first sampling circuit 31 Sampling is performed. When the second ramp wave W2 is output and the level of the output second ramp wave W2 becomes equal to the second reference level V2 (YES in step 65 and step 66), the second sampling circuit 32 Sampling is performed. When sampling by the first sampling circuit 31 and sampling by the second sampling circuit 32 are performed, the first reference level V1 and the second reference level V2 are changed (changed to different values for each horizontal scanning period). From the above, the sampling by the first sampling circuit 31 performed when the first reference level V1 and the level of the first ramp wave W1 are equal, and the second reference level V2 and the level of the second ramp wave W2 The timing of sampling by the second sampling circuit 32 performed by the equality becomes aperiodic.
　図12および図13は，第１のランプ波Ｗ１の出力タイミングと第２のランプ波Ｗ２の出力タイミングとを決定する他の処理手順を示すフローチャートである。図12および図13は，図５の第１の出力タイミングにおいて第１のランプ波Ｗ１および第２のランプ波Ｗ２を
出力する場合にリセット・パルスを非周期的にするものである。 12 and 13 are flowcharts showing another processing procedure for determining the output timing of the first ramp wave W1 and the output timing of the second ramp wave W2. 12 and 13 show that the reset pulse is aperiodic when the first ramp wave W1 and the second ramp wave W2 are output at the first output timing of FIG.
　駆動回路３から水平同期信号ＨＤが出力され(ステップ81)，出力された水平同期信号ＨＤがパルス出力回路21に入力すると，パルス出力回路21からリセット・パルスが出力される(ステップ82)。リセット・パルスの出力からΔｔ１の期間(第１の一定期間)が経過すると(ステップ83でＹＥＳ)，ランプ波発生回路27から第１のランプ波Ｗ１が出力する(ステップ84)。第１のランプ波Ｗ１が第１の基準レベルＶ１と等しくなると，ＦＤＡ23から出力されるアナログ信号が第１のサンプリング回路31においてサンプリングされ，リセット信号が得られる。 When the horizontal synchronization signal HD is output from the drive circuit 3 (step 81) and the output horizontal synchronization signal HD is input to the pulse output circuit 21, a reset pulse is output from the pulse output circuit 21 (step 82). When the period Δt1 (first constant period) has elapsed from the output of the reset pulse (YES in step 83), the ramp wave generating circuit 27 outputs the first ramp wave W1 (step 84). When the first ramp wave W1 becomes equal to the first reference level V1, the analog signal output from the FDA 23 is sampled by the first sampling circuit 31, and a reset signal is obtained.
　リセット・パルスの出力からΔｔ２の期間(第２の一定期間)が経過すると(ステップ85でＹＥＳ)，ランプ波発生回路27から第２のランプ波Ｗ２が出力する(ステップ86)。第２のランプ波Ｗ２が第２の基準レベルＶ２と等しくなると，ＦＤＡ23から出力されるアナログ信号が第２のサンプリング回路32においてサンプリングされ，データ信号が得られる。 When a period Δt2 (second constant period) has elapsed from the output of the reset pulse (YES in step 85), the ramp wave generation circuit 27 outputs the second ramp wave W2 (step 86). When the second ramp wave W2 becomes equal to the second reference level V2, the analog signal output from the FDA 23 is sampled by the second sampling circuit 32 to obtain a data signal.
　第１のランプ波Ｗ１と第２のランプ波Ｗ２とが出力されると，パルス出力回路21から出力されるリセット・パルスの出力タイミングがずらされる(遅らされる)ように制御装置11によって制御される(ステップ87)。撮像装置２の制御が終了でなければ(ステップ88でＮＯ)，１水平走査期間が経過すると(ステップ89でＹＥＳ)，次の水平同期信号ＨＤが出力し(ステップ81でＹＥＳ)，パルス出力回路21からリセット・パルスが出力する(ステップ82)。リセット・パルスの出力からΔｔ１の期間(第１の一定期間)が経過すると，第１のランプ波Ｗ１が出力し，リセット・パルスの出力からΔｔ２の期間(第２の一定期間)が経過すると，第２のランプ波Ｗ２が出力する。第１のランプ波Ｗ１および第２のランプ波Ｗ２が出力すると，リセット・パルスの出力タイミングがずらされるから，第１のランプ波Ｗ１の出力タイミングおよび第２のランプ波Ｗ２の出力タイミングも非周期となり，第１のランプ波Ｗ１および第２のランプ波Ｗ２は水平同期信号ＨＤの周期ごとにずれる。 When the first ramp wave W1 and the second ramp wave W2 are output, the control device 11 controls so that the output timing of the reset pulse output from the pulse output circuit 21 is shifted (delayed). (Step 87). If the control of the image pickup device 2 is not completed (NO in step 88), when one horizontal scanning period has elapsed (YES in step 89), the next horizontal synchronization signal HD is output (YES in step 81), and the pulse output circuit A reset pulse is output from 21 (step 82). When the Δt1 period (first constant period) has elapsed from the output of the reset pulse, the first ramp wave W1 is output. When the period of Δt2 (second constant period) has elapsed from the output of the reset pulse, A second ramp wave W2 is output. When the first ramp wave W1 and the second ramp wave W2 are output, the reset pulse output timing is shifted, so the output timing of the first ramp wave W1 and the output timing of the second ramp wave W2 are also non-periodic. Thus, the first ramp wave W1 and the second ramp wave W2 are shifted for each cycle of the horizontal synchronizing signal HD.
　図14は，ディジタル・カメラ１の処理手順を示すフローチャートである。 FIG. 14 is a flowchart showing the processing procedure of the digital camera 1.
　ＣＤＳ回路30に含まれている差分回路34から出力する差分アナログ信号がアナログ／ディジタル変換回路４においてディジタル画像データに変換され，信号処理回路５を介して制御装置11に入力する。制御装置11（周期性ノイズ判定手段）において，入力したディジタル画像データ(差分アナログ信号)に周期性ノイズが一定以上含まれているか（周期性ノイズのレベルが一定以上）どうかが判断される(ステップ91)。 The differential analog signal output from the differential circuit 34 included in the CDS circuit 30 is converted into digital image data in the analog / digital conversion circuit 4 and input to the control device 11 via the signal processing circuit 5. In the control device 11 (periodic noise determination means), it is determined whether or not the input digital image data (differential analog signal) includes periodic noise more than a certain value (periodic noise level is more than a certain value) (step) 91).
　周期性ノイズが一定以上含まれている場合には(ステップ91でＹＥＳ)，周期性ノイズが被写体像（画像）に与える影響が大きいと考えられるため，第１のサンプリング・パルスの出力タイミングおよび第２のサンプリング・パルスの出力タイミングの少なくとも一方が，設定値以上にずらされる(ステップ92)。周期性ノイズが大きく，被写体像に与える影響が大きい場合であっても，その周期性ノイズの大きさに合わせて第１のサンプリング・パルスの出力タイミングおよび第２のサンプリング・パルスの出力タイミングの少なくとも一方が設定値以上にずらされるので，周期性ノイズが被写体像に与える影響を抑えることができる。第１のサンプリング・パルスの出力タイミングのみを設定値以上にずらしてもよいし，第２のサンプリング・パルスの出力タイミングのみを設定値以上にずらしてもよいし，第１のサンプリング・パルスの出力タイミングと第２のサンプリング・パルスの出力タイミングの両方を設定値以上にずらしてもよい。第１のサンプリング・パルスの出力タイミングおよび第２のサンプリング・パルスの出力タイミングをずらす方法は，図６から図13を参照して説明した方法のいずれでもよい。設定値は，第１のサンプリング・パルスの出力タイミングのずれ量および第２のサンプリング・パルスの出力タイミングのずれ量のことである。周期性ノイズが一定以上の場合には，少なくとも，これらのずれ量の一方が設定値以上にずらされる。たとえば，図５に示す第１の出力タイミングの場合には，リセット・パルスのずれ量が設定値であり，図５に示す第２の出力タイミングおよび第３の出力タイミングの場合には，Δ１，Δ２が設定値である。 If the periodic noise is included above a certain level (YES in step 91), it is considered that the periodic noise has a great influence on the subject image (image). At least one of the two sampling pulse output timings is shifted to a set value or more (step 92). Even when the periodic noise is large and the influence on the subject image is large, at least one of the output timing of the first sampling pulse and the output timing of the second sampling pulse according to the magnitude of the periodic noise. Since one of them is shifted beyond the set value, the influence of periodic noise on the subject image can be suppressed. Only the output timing of the first sampling pulse may be shifted above the set value, only the output timing of the second sampling pulse may be shifted above the set value, or the output of the first sampling pulse Both the timing and the output timing of the second sampling pulse may be shifted to a set value or more. The method of shifting the output timing of the first sampling pulse and the output timing of the second sampling pulse may be any of the methods described with reference to FIGS. The set values are the deviation amount of the output timing of the first sampling pulse and the deviation amount of the output timing of the second sampling pulse. If the periodic noise is above a certain level, at least one of these shift amounts is shifted to a set value or more. For example, in the case of the first output timing shown in FIG. 5, the reset pulse deviation amount is a set value, and in the case of the second output timing and the third output timing shown in FIG. Δ2 is a set value.
　差分アナログ信号に周期性ノイズが一定以上含まれていない場合には(ステップ91でＮＯ)，第１のサンプリング・パルスの出力タイミングおよび第２のサンプリング・パルスの出力タイミングのいずれもずらさなくともよいし，第１のサンプリング・パルスの出力タイミングおよび第２のサンプリング・パルスの少なくとも一方を，設定値よりも小さな値にずらすようにしてもよい。 If the differential analog signal does not contain periodic noise above a certain level (NO in step 91), neither the output timing of the first sampling pulse nor the output timing of the second sampling pulse need be shifted. However, at least one of the output timing of the first sampling pulse and the second sampling pulse may be shifted to a value smaller than the set value.
　図15は，ディジタル・カメラ１の他の処理手順を示すフローチャートである。 FIG. 15 is a flowchart showing another processing procedure of the digital camera 1.
　図15に示す処理においては，第１のサンプリング処理と第２のサンプリング処理とが行われる(ステップ101)。第１のサンプリング処理は，図６および図７，図８および図９または図12および図13に示すようにして第１のランプ波Ｗ１の出力タイミングおよび第２のランプ波Ｗ２の出力タイミングの少なくとも一方を非周期的とすることにより，第１のサンプリング期間におけるアナログ信号のサンプリングおよび第２のサンプリング期間におけるアナログ信号のサンプリングの少なくとも一方を非周期的とするものである。第２のサンプリング処理は，図10および図11に示すようにして第１の基準レベルＶ１および第２の基準レベルＶ２の少なくとも一方を非周期的に変更することにより，第１のサンプリング期間におけるアナログ信号のサンプリングおよび第２のサンプリング期間におけるアナログ信号のサンプリングの少なくとも一方を非周期的とするものである。 In the process shown in FIG. 15, the first sampling process and the second sampling process are performed (step 101). The first sampling process is performed at least of the output timing of the first ramp wave W1 and the output timing of the second ramp wave W2 as shown in FIGS. By making one non-periodic, at least one of the sampling of the analog signal in the first sampling period and the sampling of the analog signal in the second sampling period is made non-periodic. In the second sampling process, analog signals in the first sampling period are changed by aperiodically changing at least one of the first reference level V1 and the second reference level V2 as shown in FIGS. At least one of the sampling of the signal and the sampling of the analog signal in the second sampling period is aperiodic.
　第１のサンプリング処理を行った場合に差分回路34から出力した差分アナログ信号によって表される被写体像に含まれている第１の周期性ノイズと第２のサンプリング処理を行った場合に差分回路34から出力した差分アナログ信号によって表される被写体像に含まれている第２の周期性ノイズとが制御装置11によって検出され，これらの第１の周期性ノイズと第２の周期性ノイズとが制御装置11(比較手段)によって比較される(ステップ102)。 When the first sampling process is performed, the first periodic noise included in the subject image represented by the differential analog signal output from the difference circuit 34 and the second sampling process are performed when the second sampling process is performed. The control device 11 detects the second periodic noise included in the subject image represented by the differential analog signal output from the control unit, and controls the first periodic noise and the second periodic noise. The comparison is performed by the device 11 (comparison means) (step 102).
　比較の結果，第１の周期性ノイズよりも第２の周期性ノイズの方が大きければ(ステップ103でＹＥＳ)，第２のサンプリング処理よりも第１のサンプリング処理の方が周期性ノイズを除去できると考えられるので，第１のサンプリング処理が行われるようにＣＤＳ回路30が制御装置11（制御手段）によって制御される(ステップ104)。 As a result of the comparison, if the second periodic noise is larger than the first periodic noise (YES in step 103), the first sampling process removes the periodic noise rather than the second sampling process. Since it is considered possible, the CDS circuit 30 is controlled by the control device 11 (control means) so that the first sampling process is performed (step 104).
　第２の周期性ノイズよりも第１の周期性ノイズの方が大きければ(ステップ103でＮＯ)，第１のサンプリング処理よりも第２のサンプリング処理の方が周期性ノイズを除去できると考えられるので，第２のサンプリング処理が行われるようにＣＤＳ回路30が制御装置11（制御手段）によって制御される(ステップ105)。 If the first periodic noise is larger than the second periodic noise (NO in step 103), it is considered that the second sampling process can remove the periodic noise rather than the first sampling process. Therefore, the CDS circuit 30 is controlled by the control device 11 (control means) so that the second sampling process is performed (step 105).
　周期性ノイズを，より除去できる方法のサンプリング処理が行われるようになる。 Sampling processing that can remove periodic noise is performed.
　図16は，第２のランプ波Ｗ２の他の一例である。 FIG. 16 shows another example of the second ramp wave W2.
　図４に示す第２のランプ波Ｗ２は，第２のサンプリング期間において減少するものである。これに対して，図16に示す第２のランプ波Ｗ２は，第２のサンプリング期間において時刻ｔ21から時刻ｔ22の間において減少し，時刻ｔ22においてリセットされ(一定レベルに増加され)，時刻ｔ22から時刻ｔ23の間に再び減少している。このように第２のサンプリング期間に第２のランプ波Ｗ２の減少が繰り返されてもよい。 The second ramp wave W2 shown in FIG. 4 decreases in the second sampling period. On the other hand, the second ramp wave W2 shown in FIG. 16 decreases from time t21 to time t22 in the second sampling period, is reset at time t22 (increased to a constant level), and starts from time t22. It decreases again during time t23. In this manner, the decrease of the second ramp wave W2 may be repeated during the second sampling period.
　また，図４に示す第２のランプ波Ｗ２は，第２のサンプリング期間において減少しているが，減少でなく増加するものでもよい。さらに，図16に示す第２のランプ波Ｗ２も，第２のサンプリング期間に減少が繰り返されるものではなく，増加が繰り返される（増加または減少が繰り返される）ものでもよい。 Further, the second ramp wave W2 shown in FIG. 4 decreases in the second sampling period, but may increase instead of decreasing. Furthermore, the second ramp wave W2 shown in FIG. 16 may not be repeatedly decreased during the second sampling period, but may be repeatedly increased (repeated or increased).
　さらに，図４に示す第１のランプ波Ｗ１も，第１のサンプリング期間において減少しているが，減少しているが，減少でなく，増加するものでもよい。また，図４に示す第１のランプ波Ｗ１も，図16に示す第２のランプ波Ｗ２と同様に，減少(または増加)が繰り返されるものでもよい。 Further, the first ramp wave W1 shown in FIG. 4 is also decreased in the first sampling period, but may be decreased but not increased. Also, the first ramp wave W1 shown in FIG. 4 may be repeatedly reduced (or increased) in the same manner as the second ramp wave W2 shown in FIG.
　１　ディジタル・カメラ，２　撮像装置，３　駆動回路，４　アナログ／ディジタル変換回路，５　信号処理回路，６　表示制御回路，７　表示装置，８　タッチ・パネル，９　記録制御回路，　10　メモリ・カード，11　制御装置，12　メモリ，13　モード・スイッチ，14　シャッタ・ボタン，21　パルス出力回路，22　光電変換素子，24　垂直信号ライン，25　リセット・パルス・ライン，26　読み出しパルス・ライン，27　ランプ波発生回路，28　出力ライン，30　ＣＤＳ回路，31　第１のサンプリング回路，32　第２のサンプリング回路，33　比較回路，34　差分回路，110　被写体像，111　ノイズ，ＨＤ　水平同期信号，Ｖ１　第１の基準レベル，Ｖ２　第２の基準レベル，Ｗ１　第１のランプ波，Ｗ２　第２のランプ波 1 digital camera, 2 imaging device, 3 drive circuit, 4 analog / digital conversion circuit, 5 signal processing circuit, 6 display control circuit, 7 display device, 8 touch panel, 9 recording control circuit, 10 memory card, 11 Control device, 12 memory, 13 mode switch, 14 shutter button, 21 pulse output circuit, 22 photoelectric conversion element, 24 vertical signal line, 25 reset pulse line, 26 readout pulse line, 27 ramp wave generation circuit, 28 output lines, 30 CDS circuit, 31 first sampling circuit, 32 second sampling circuit, 33 comparison circuit, 34 difference circuit, 110 subject image, 111 noise, HD horizontal sync signal, V1 first reference level, V2 Second reference level, W1 first ramp wave, W2 second ramp wave

Claims (13)

  1. 　行方向および列方向のそれぞれに配置された複数の光電変換素子，
    　上記光電変換素子に蓄積されている信号電荷をリセットするリセット・パルスを，周期的な水平同期信号の出力後に出力し，かつ上記光電変換素子に蓄積されている信号電荷を読み出す読み出しパルスを出力するパルス出力回路，
    　上記パルス出力回路からの読み出しパルスの出力に応じて，上記光電変換素子に蓄積されている信号電荷をアナログ信号に変換して出力する増幅回路，
    　上記パルス出力回路からのリセット・パルスの出力から上記パルス出力回路からの読み出しパルスの出力までの第１のサンプリング期間に増加または減少する第１の基準信号を出力し，かつ上記パルス出力回路からの読み出しパルスの出力から上記パルス出力回路からのリセット・パルスの出力までの第２のサンプリング期間に増加または減少する第２の基準信号を出力する基準信号出力回路，
    　上記基準信号出力回路から出力される第１の基準信号のレベルが第１の基準レベルとなったことに応じて上記増幅回路から出力するアナログ信号をサンプリングする第１のサンプリング回路，
    　上記基準信号出力回路から出力される第２の基準信号のレベルが第２の基準レベルとなったことに応じて上記増幅回路から出力するアナログ信号をサンプリングする第２のサンプリング回路，ならびに
    　上記第１のサンプリング回路による第１のサンプリング期間におけるアナログ信号のサンプリングおよび上記第２のサンプリング回路における第２のサンプリング期間におけるアナログ信号のサンプリングの少なくとも一方を非周期的とするサンプリング制御手段，
    　を備えた固体電子撮像装置。     A plurality of photoelectric conversion elements arranged in each of the row direction and the column direction;
    A reset pulse for resetting the signal charge accumulated in the photoelectric conversion element is output after the periodic horizontal synchronization signal is output, and a readout pulse for reading the signal charge accumulated in the photoelectric conversion element is output. Pulse output circuit,
    An amplifying circuit for converting a signal charge accumulated in the photoelectric conversion element into an analog signal in accordance with an output of a readout pulse from the pulse output circuit;
    Outputting a first reference signal that increases or decreases during a first sampling period from the output of a reset pulse from the pulse output circuit to the output of a read pulse from the pulse output circuit, and from the pulse output circuit A reference signal output circuit that outputs a second reference signal that increases or decreases during a second sampling period from the output of the readout pulse to the output of the reset pulse from the pulse output circuit;
    A first sampling circuit for sampling an analog signal output from the amplifier circuit in response to the level of the first reference signal output from the reference signal output circuit becoming the first reference level;
    A second sampling circuit for sampling the analog signal output from the amplifier circuit in response to the level of the second reference signal output from the reference signal output circuit becoming the second reference level; Sampling control means for aperiodic at least one of sampling of the analog signal in the first sampling period by the sampling circuit and sampling of the analog signal in the second sampling period in the second sampling circuit;
    A solid-state electronic imaging device.
  2. 　上記サンプリング制御手段は，
    　上記基準信号出力回路からの第１の基準信号の出力タイミングおよび第２の基準信号の出力タイミングの少なくとも一方を非周期的とすることにより，第１のサンプリング期間におけるアナログ信号のサンプリングおよび第２のサンプリング期間におけるアナログ信号のサンプリングの少なくとも一方を非周期的とする，
    　請求項１に記載の固体電子撮像装置。     The sampling control means is
    By making at least one of the output timing of the first reference signal and the output timing of the second reference signal from the reference signal output circuit non-periodic, sampling of the analog signal in the first sampling period and second At least one of the sampling of the analog signal in the sampling period is aperiodic,
    The solid-state electronic imaging device according to claim 1.
  3. 　上記サンプリング制御手段は，
    　上記第１の基準レベルおよび上記第２の基準レベルの少なくとも一方を非周期的に変更することにより，第１のサンプリング期間におけるアナログ信号のサンプリングおよび第２のサンプリング期間におけるアナログ信号のサンプリングの少なくとも一方を非周期的とする，
    　請求項１に記載の固体電子撮像装置。     The sampling control means is
    At least one of sampling of the analog signal in the first sampling period and sampling of the analog signal in the second sampling period by aperiodically changing at least one of the first reference level and the second reference level Is aperiodic,
    The solid-state electronic imaging device according to claim 1.
  4. 　第１のサンプリング期間におけるアナログ信号のサンプリングと第２のサンプリング期間におけるアナログ信号のサンプリングとのサンプリング間隔が一定である，
    　請求項１から３のうち，いずれか一項に記載の固体電子撮像装置。     The sampling interval between the sampling of the analog signal in the first sampling period and the sampling of the analog signal in the second sampling period is constant,
    The solid-state electronic imaging device according to any one of claims 1 to 3.
  5. 　第１のサンプリング期間におけるアナログ信号のサンプリングと第２のサンプリング期間におけるアナログ信号のサンプリングとのサンプリング間隔が水平同期信号の周期ごとに異なる，
    　請求項１から３のうち，いずれか一項に記載の固体電子撮像装置。     The sampling interval between the sampling of the analog signal in the first sampling period and the sampling of the analog signal in the second sampling period is different for each period of the horizontal synchronization signal.
    The solid-state electronic imaging device according to any one of claims 1 to 3.
  6. 　上記第１のサンプリング回路におけるサンプリングにより得られた第１のアナログ信号と上記第２のサンプリング回路におけるサンプリングにより得られた第２のアナログ信号との差分を表す差分アナログ信号を出力する差分回路，
    　をさらに備えた請求項１から５のうち，いずれか一項に記載の固体電子撮像装置。     A differential circuit for outputting a differential analog signal representing a difference between the first analog signal obtained by sampling in the first sampling circuit and the second analog signal obtained by sampling in the second sampling circuit;
    The solid-state electronic imaging device according to any one of claims 1 to 5, further comprising:
  7. 　上記差分回路から出力した差分アナログ信号によって表される被写体像に周期性ノイズが一定以上含まれているかどうかを判定する周期性ノイズ判定手段をさらに備え，
    　上記サンプリング制御手段は，
    　上記周期性ノイズ判定手段によって被写体像に周期性ノイズが一定以上含まれていると判定されたことに応じて，水平同期信号の出力タイミングから第１のサンプリング期間におけるアナログ信号のサンプリングまでのずれ量および水平同期信号の出力タイミングから第２のサンプリング期間におけるアナログ信号のサンプリングまでのずれ量の少なくとも一方を設定値以上にずらす，
    　請求項１に記載の固体電子撮像装置。     Periodic noise determining means for determining whether or not periodic noise is included in the subject image represented by the differential analog signal output from the difference circuit;
    The sampling control means is
    The amount of deviation from the output timing of the horizontal synchronizing signal to the sampling of the analog signal in the first sampling period in response to the periodic noise determining means determining that the subject image contains periodic noise more than a certain amount And at least one of a shift amount from the output timing of the horizontal synchronizing signal to the sampling of the analog signal in the second sampling period is shifted to a set value or more.
    The solid-state electronic imaging device according to claim 1.
  8. 　上記サンプリング制御手段を，上記基準信号出力回路からの第１の基準信号の出力タイミングおよび第２の基準信号の出力タイミングの少なくとも一方を非周期的とすることにより，第１のサンプリング期間におけるアナログ信号のサンプリングおよび第２のサンプリング期間におけるアナログ信号のサンプリングの少なくとも一方を非周期的とする第１のサンプリング処理を行った場合に上記差分回路から出力した差分アナログ信号によって表される被写体像に含まれている第１の周期性ノイズと，上記サンプリング制御手段を，上記第１の基準レベルおよび上記第２の基準レベルの少なくとも一方を非周期的に変更することにより，第１のサンプリング期間におけるアナログ信号のサンプリングおよび第２のサンプリング期間におけるアナログ信号のサンプリングの少なくとも一方を非周期的とする第２のサンプリング処理を行った場合に上記差分回路から出力した差分アナログ信号によって表される被写体像に含まれている第２の周期性ノイズとを比較する比較手段，ならびに
    　上記比較手段によって第１の周期性ノイズよりも第２の周期性ノイズの方が大きいと判定された場合には第１のサンプリング処理を上記サンプリング制御手段に行わせ，上記比較手段によって第２の周期性ノイズよりも第１の周期性ノイズの方が大きいと判定された場合には第２のサンプリング処理を上記サンプリング制御手段に行わせる制御手段，
    　をさらに備えた請求項６に記載の固体電子撮像装置。     By making the sampling control means aperiodic at least one of the output timing of the first reference signal and the output timing of the second reference signal from the reference signal output circuit, an analog signal in the first sampling period is set. Included in the subject image represented by the differential analog signal output from the differential circuit when the first sampling processing is performed in which at least one of the sampling and the sampling of the analog signal in the second sampling period is aperiodic. The first periodic noise and the sampling control means change the at least one of the first reference level and the second reference level aperiodically, whereby the analog signal in the first sampling period is changed. Sampling in the second sampling period Second periodic noise included in the subject image represented by the differential analog signal output from the differential circuit when the second sampling process is performed in which at least one of the sampling of the log signal is aperiodic; A comparison means for comparing the second periodic noise when the comparison means determines that the second periodic noise is greater than the first periodic noise, and causes the sampling control means to perform a first sampling process, Control means for causing the sampling control means to perform a second sampling process when the comparison means determines that the first periodic noise is larger than the second periodic noise;
    The solid-state electronic imaging device according to claim 6, further comprising:
  9. 　水平同期信号を生成して上記パルス出力回路に出力する駆動回路，
    　をさらに備えた請求項１から８のうち，いずれか一項に記載の固体電子撮像装置。     A driving circuit for generating a horizontal synchronizing signal and outputting it to the pulse output circuit;
    The solid-state electronic imaging device according to any one of claims 1 to 8, further comprising:
  10. 　上記第１の基準信号は，
    　上記第１のサンプリング期間において増加または減少が繰り返される，
    　請求項１から９のうち，いずれか一項に記載の固体電子撮像装置。     The first reference signal is
    The increase or decrease is repeated in the first sampling period.
    The solid-state electronic imaging device according to any one of claims 1 to 9.
  11. 　上記第２の基準信号は，
    　上記第２のサンプリング期間において増加または減少が繰り返される，
    　請求項１から10のうち，いずれか一項に記載の固体電子撮像装置。     The second reference signal is
    The increase or decrease is repeated in the second sampling period.
    The solid-state electronic imaging device according to any one of claims 1 to 10.
  12. 　上記第１の基準信号は，上記リセット・パルスの出力から第１の一定期間経過後に出力され，かつ上記第２の基準信号は，上記リセット・パルスの出力から第２の一定期間経過後に出力され，
    　上記サンプリング制御手段は，
    　上記パルス出力回路によるリセット・パルスの出力タイミングを非周期的とする，
    　請求項１に記載の固体電子撮像装置。     The first reference signal is output after a lapse of a first fixed period from the output of the reset pulse, and the second reference signal is output after a lapse of a second fixed period from the output of the reset pulse. ,
    The sampling control means is
    The output timing of the reset pulse by the pulse output circuit is aperiodic.
    The solid-state electronic imaging device according to claim 1.
  13. 　パルス出力回路が，行方向および列方向のそれぞれに配置された複数の光電変換素子に蓄積されている信号電荷をリセットするリセット・パルスを，周期的な水平同期信号の出力後に出力し，かつ上記光電変換素子に蓄積されている信号電荷を読み出す読み出しパルスを出力し，
    　増幅回路が，上記パルス出力回路からの読み出しパルスの出力に応じて，上記光電変換素子に蓄積されている信号電荷をアナログ信号に変換して出力し，
    　基準信号出力回路が，上記パルス出力回路からのリセット・パルスの出力から上記パルス出力回路からの読み出しパルスの出力までの第１のサンプリング期間に増加または減少する第１の基準信号を出力し，かつ上記パルス出力回路からの読み出しパルスの出力から上記パルス出力回路からのリセット・パルスの出力までの第２のサンプリング期間に増加または減少する第２の基準信号を出力し，
    　第１のサンプリング回路が，上記基準信号出力回路から出力される第１の基準信号のレベルが第１の基準レベルとなったことに応じて上記増幅回路から出力するアナログ信号をサンプリングし，
    　第２のサンプリング回路が，上記基準信号出力回路から出力される第２の基準信号のレベルが第２の基準レベルとなったことに応じて上記増幅回路から出力するアナログ信号をサンプリングし，
    　サンプリング制御手段が，上記第１のサンプリング回路による第１のサンプリング期間におけるアナログ信号のサンプリングおよび上記第２のサンプリング回路における第２のサンプリング期間におけるアナログ信号のサンプリングの少なくとも一方を非周期的とする，
    　固体電子撮像装置の制御方法。     The pulse output circuit outputs a reset pulse for resetting signal charges accumulated in a plurality of photoelectric conversion elements arranged in the row direction and the column direction after outputting the periodic horizontal synchronizing signal, and Outputs a read pulse that reads the signal charge accumulated in the photoelectric conversion element,
    In response to the output of the readout pulse from the pulse output circuit, the amplifier circuit converts the signal charge accumulated in the photoelectric conversion element into an analog signal and outputs the analog signal.
    A reference signal output circuit outputs a first reference signal that increases or decreases during a first sampling period from the output of the reset pulse from the pulse output circuit to the output of the read pulse from the pulse output circuit; and Outputting a second reference signal that increases or decreases during a second sampling period from the output of the readout pulse from the pulse output circuit to the output of the reset pulse from the pulse output circuit;
    The first sampling circuit samples the analog signal output from the amplifier circuit in response to the level of the first reference signal output from the reference signal output circuit becoming the first reference level,
    The second sampling circuit samples the analog signal output from the amplifier circuit in response to the second reference signal output from the reference signal output circuit becoming the second reference level;
    The sampling control means makes at least one of sampling of the analog signal in the first sampling period by the first sampling circuit and sampling of the analog signal in the second sampling period in the second sampling circuit aperiodic;
    Control method of solid-state electronic imaging device.
PCT/JP2017/014926 2016-05-25 2017-04-12 Solid-state electronic imaging device and method for controlling same WO2017203873A1 (en)

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