WO2017193558A1 - 结构化ldpc码的数据处理方法及装置 - Google Patents

结构化ldpc码的数据处理方法及装置 Download PDF

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WO2017193558A1
WO2017193558A1 PCT/CN2016/104744 CN2016104744W WO2017193558A1 WO 2017193558 A1 WO2017193558 A1 WO 2017193558A1 CN 2016104744 W CN2016104744 W CN 2016104744W WO 2017193558 A1 WO2017193558 A1 WO 2017193558A1
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positive integer
coding
check matrix
equal
value
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PCT/CN2016/104744
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French (fr)
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李立广
徐俊
许进
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中兴通讯股份有限公司
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Priority claimed from CN201610879343.9A external-priority patent/CN107370489B/zh
Application filed by 中兴通讯股份有限公司 filed Critical 中兴通讯股份有限公司
Priority to EP16901513.8A priority Critical patent/EP3457574A4/en
Publication of WO2017193558A1 publication Critical patent/WO2017193558A1/zh
Priority to US16/171,314 priority patent/US10523237B2/en
Priority to US16/730,962 priority patent/US11139835B2/en
Priority to US17/493,612 priority patent/US11683051B2/en

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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/033Theoretical methods to calculate these checking codes
    • H03M13/036Heuristic code construction methods, i.e. code construction or code search based on using trial-and-error
    • HELECTRICITY
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    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148Structural properties of the code parity-check or generator matrix
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    • HELECTRICITY
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    • H03M13/03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
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    • H03M13/03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105Decoding
    • H03M13/1131Scheduling of bit node or check node processing
    • H03M13/1137Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel
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    • H03M13/03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105Decoding
    • H03M13/1131Scheduling of bit node or check node processing
    • H03M13/114Shuffled, staggered, layered or turbo decoding schedules
    • HELECTRICITY
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    • H03M13/03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148Structural properties of the code parity-check or generator matrix
    • H03M13/116Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • HELECTRICITY
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    • H03M13/03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148Structural properties of the code parity-check or generator matrix
    • H03M13/118Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
    • H03M13/1185Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal
    • HELECTRICITY
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    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148Structural properties of the code parity-check or generator matrix
    • H03M13/118Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
    • H03M13/1185Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal
    • H03M13/1188Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal wherein in the part with the double-diagonal at least one column has an odd column weight equal or greater than three
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/615Use of computational or mathematical techniques
    • H03M13/616Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63Joint error correction and other techniques
    • H03M13/635Error control coding in combination with rate matching
    • H03M13/6356Error control coding in combination with rate matching by repetition or insertion of dummy data, i.e. rate reduction
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65Purpose and implementation aspects
    • H03M13/6508Flexibility, adaptability, parametrability and configurability of the implementation
    • H03M13/6516Support of multiple code parameters, e.g. generalized Reed-Solomon decoder for a variety of generator polynomials or Galois fields
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit

Definitions

  • the present invention relates to the field of communications, and in particular to a data processing method and apparatus for a structured LDPC code.
  • the transmitting end may perform channel coding on the information sequence to obtain an encoded codeword, interleave the encoded codeword, and map the interleaved bits into modulation symbols, and then process and transmit the modulation symbols according to the communication channel information.
  • the receiving end receives the modulation symbol data after passing through the channel, and the modulation symbol data at this time is already distorted, and specific processing is required to restore the original information sequence.
  • the receiving end can perform corresponding processing on the received data to reliably restore the original information sequence.
  • the encoding method must be visible at both ends of the transceiver.
  • the encoding processing method is based on Forward Error Correction (FEC) encoding, wherein forward error correction encoding adds some redundant information to the information sequence.
  • FEC Forward Error Correction
  • FEC codes include: convolutional codes, Turbo codes, and Low Density Parity Check (LDPC) codes.
  • the information sequence of the bit number k is FEC-encoded to obtain an n-bit FEC encoded codeword (redundant bits are n-k), and the FEC encoding code rate is k/n.
  • Convolutional coding can easily encode packets of any size, and in Turbo coding, different information sequence sizes can be supported by using two coded components that operate on the sequence of information and code interleaving methods that can support different sizes. .
  • LDPC code is a linear block code that can be defined by a very sparse parity check matrix or bipartite graph. It is the sparseness of its check matrix that can realize low complexity codec, which makes LDPC practical. .
  • the LDPC code is the most excellent channel coding under the Additive White Gaussian Noise (AWGN) channel. The performance is very close to the Shannon limit, which is better than the convolutional code and Turbo coding. .
  • AWGN Additive White Gaussian Noise
  • structured LDPC codes have become mainstream applications due to their structured features, such as IEEE802.11ac, IEEE802.11ad, IEEE802.11aj, IEEE802.16e, IEEE802.11n, DVB, microwave communication, and fiber-optic communications.
  • the parity check matrix H of such a structured LDPC code is a matrix of mb ⁇ z rows and nb ⁇ z columns, which is composed of mb ⁇ nb block matrices, each of which is a basic permutation of z ⁇ z
  • the different powers of the matrix they are the cyclic shift matrix of the unit matrix.
  • a block matrix is an all-zero matrix
  • the matrix is generally represented by -1, and if the cyclic shift s of the unit array is obtained, Equal to s, so all A basic check matrix Hb can be constructed.
  • z is the dimension indicating the standard permutation matrix, here we call z the expansion factor.
  • the structured LDPC code can be uniquely determined by the basic check matrix Hb and the spreading factor z.
  • the base check matrix Hb (2 rows and 4 columns) is as follows and the expansion factor z is equal to 4:
  • the LDPC code can use hierarchical decoding, that is, a partial parallel decoding method.
  • the parity check matrix as described above has 8 rows, indicating that there are 8 parity check codes.
  • each parity check matrix needs to be decoded separately, if all 8 parity check codes are updated, For an iteration.
  • the parity check matrix is relatively large, storage processing and the like are inconvenient, and it is much simpler to use the basic check matrix storage.
  • prime numbers are also called prime numbers, and there are infinite numbers.
  • a prime number is defined as a number in a natural number greater than 1, and no more factors other than 1 and itself are called prime numbers or prime numbers, so in general, prime numbers are integers greater than 1, such as 2, 3, 5, 7, 11, 13, 17, 19 and so on.
  • the encoder complexity is low, and the basic complexity lies in the decoder at the receiving end.
  • LDPC encoding has parallel decoding and can achieve parallel decoding, so it has higher decoding speed and throughput. the amount.
  • the basic check matrix of the LDPC code generally only adapts to a part of the length, it may not be easy to implement coding blocks of various flexible lengths, and the complexity is relatively high for adapting code blocks of different lengths.
  • the embodiment of the invention provides a data processing method and device for a structured LDPC code, so as to at least solve the problem that the processing flexibility of the data sequence of the LDPC compiled code in the related art is low.
  • determining, according to at least the coding block size CBS, the parameter kb of the basic check matrix, and the positive integer value p, the coding extension factor includes: Determining the coding spreading factor, wherein Indicates rounding up.
  • obtaining the coding block size of the structured LDPC encoding includes: the coding block size is equal to a value obtained by multiplying a parameter kb of the basic check matrix by one element of a set of ascending natural numbers.
  • the set of ascending natural numbers includes a plurality of packets, wherein a first added value of adjacent elements in the plurality of packets is equal.
  • the first added value of the i-th packet in the set of ascending natural numbers is smaller than that of the (i+1)th packet The first added value, wherein the i is a positive integer.
  • determining the coding extension factor according to the coding block size includes: the coding block size is an element value in a set of coding block sizes, and the set of coding block sizes is an ascending first natural array;
  • the coding spreading factor is an element value of a set of coding spreading factors, and the set of coding extension factors is a second natural array in ascending order.
  • the set of coding block sizes includes consecutive a elements, wherein a value of a first element of the consecutive a elements is greater than z(j) ⁇ kb, and a tail element value is less than or equal to z (
  • the coding extension factor corresponding to the consecutive a elements is z(j+1)
  • the a is a positive integer
  • the z(j) is the set of coding extensions
  • the jth element value in the factor, the j is a positive integer
  • the kb is a parameter of the base check matrix.
  • the coding extension factor is z(j+1).
  • the coding spreading factor is determined to be z. (j+1), wherein the z(j) is a j-th element value of the set of coding spreading factors.
  • the group of coding extension factors includes a plurality of packets, wherein a second added value of adjacent elements in the group of the plurality of packets is equal, and a th-th packet of the plurality of packets is The second added value is smaller than the second added value of the h+1th packet, and the h is a positive integer.
  • all of the set of coding spreading factors greater than the positive integer value p are n times the positive integer of the positive integer value p.
  • the set of coding block sizes includes at least: a product value obtained by multiplying a parameter kb of the basic parity check matrix by the set of coding extension factors, and an interval between all the product values is B.
  • the method before the encoding the data sequence to be encoded according to the basic check matrix and the coding extension factor, the method further includes: performing bit filling on the first data sequence, where performing the first data sequence
  • the bit padding comprises: dividing the first data sequence into a plurality of sub-data sequences, performing bit filling on the plurality of sub-data sequences respectively, and all sub-data sequences after padding bits constitute the data sequence to be encoded.
  • the method before the encoding the data sequence to be encoded according to the basic check matrix and the coding extension factor, the method further includes: performing bit filling on the second data sequence, wherein performing bit filling on the second data sequence
  • the method includes: dividing the second data sequence into sub-data sequences in which the number of kb bits is less than or equal to z, adding padding bits to each sub-data sequence such that the number of bits of each group of sub-data sequences reaches z, after all padding bits
  • the sub-data sequence constitutes the data sequence to be encoded, wherein kb is a parameter of a base check matrix, and z is the code spreading factor.
  • bit filling the first data sequence or bit filling the second data sequence the method further includes: adding a L-bit cyclic redundancy check CRC sequence to the third data sequence to obtain the first data sequence or the second data sequence, wherein the L is greater than or equal to 0 Integer.
  • the parameter kb of the basic check matrix is a difference between the number of columns of the basic check matrix and the number of rows of the basic check matrix, and kb is an integer greater than or equal to 4 and less than or equal to 64.
  • the positive integer value p is an LDPC decoding parallelism.
  • the positive integer value p is a fixed positive integer
  • the LDPC decoding parallel degree p includes: the positive integer value p is a positive integer power of 2 or the positive integer value p is 2 The integer power is multiplied by a prime number.
  • the positive integer value p is an element of the subset P, wherein the subset P is a subset of all positive integer factors of Pmax, and Pmax is greater than 3 and less than or equal to 1024 An integer.
  • the subset nSet includes one of: a subset of the first F elements of the positive integer set Ns, a subset of the last F elements of the positive integer set Ns, the a subset of F prime numbers in a positive integer set Ns, a subset of F odd numbers in the positive integer set Ns, and a subset of F even numbers in the positive integer set Ns, F is less than M Positive integer.
  • the coding spreading factor includes: the coding spreading factor is equal to a positive integer power of 2 and then decremented by 1, or the coding spreading factor is equal to a positive integer power of 2 and multiplied by a prime number, the prime number Includes one of the following: 3, 5, 7, 11, 13, 17, 19, 23, 29.
  • the coding spreading factor is equal to a positive integer power of 2 and is multiplied by a prime number including 3 and 5.
  • the coding spreading factor is equal to a positive integer power of 2 and is multiplied by a prime number including 5 and 7.
  • the coding spreading factor is equal to a positive integer power of 2 and is multiplied by a prime number including 3, 5, and 7.
  • the coding extension factor includes one of the following: 7, 15, 31, 63, 127, 255, 511, 1023, 2047, 4095.
  • the method after determining the coding spreading factor z according to at least one of the following parameters: the coding block size, the parameter kb of the basic check matrix, the positive integer value p, and the basic check matrix, The method also includes storing at least the base check matrix.
  • the method further includes: filling the data sequence to be encoded with a dummy bit of length k′ bits to obtain a data sequence to be encoded having a length of kb*z bits, where
  • the ratio of k' to kb*z is less than or equal to 1/4
  • k' is an integer greater than or equal to 0
  • the kb is the number of system columns of the basic check matrix
  • z is an extension used for encoding
  • the factor size, kb is an integer greater than 1
  • z is an integer greater than zero.
  • the spreading factor z is n times a positive integer value pl.
  • the positive integer value pl is an element of the subset Pset, wherein the subset Pset is a subset of all positive integer factors of Pmax, n is a natural number, and Pmax is greater than or equal to An integer of 4.
  • the positive integer value pl is an element of the subset Pset, all values of the positive integer n constitute a subset nSet, plmax is the maximum value in the subset Pset, and nmax is the largest in the subset nSet Value, where Kmax ⁇ kb ⁇ plmax ⁇ nmax ⁇ 1.2 ⁇ Kmax, and Kmax is an integer greater than 1024.
  • the Kmax is equal to 2000, 2048, 4000, 4096, 6000, 6144, 8000, 8192, 12000 or 12288.
  • the elements of the row index i and the column index j in the matrix and the hbij indicate a non-all 0 square matrix, A is a fixed integer smaller than pl and greater than or equal to 0, and Pmax is an integer greater than or equal to 4.
  • the parameter kb of the basic check matrix is the number of base check matrix system columns.
  • a data processing apparatus for a structured LDPC code comprising: an obtaining module, configured to obtain a coded block size of a structured LDPC code; and a determining module, configured to use at least one of the following parameters Determining a coding spreading factor z: the coding block size, a parameter kb of the basic parity check matrix, a positive integer value p, a basic check matrix of the mb row and the nb column, and a processing module for determining the matrix and the
  • the determining module is configured to: pass a formula Determining the coding spreading factor, wherein the CBS is the coding block size, Indicates rounding up.
  • the obtaining module is configured to: the coded block size is equal to a value obtained by multiplying a parameter kb of the basic check matrix by one element of a set of ascending natural numbers.
  • the set of ascending natural numbers includes a plurality of packets, wherein a first added value of adjacent elements in the plurality of packets is equal.
  • the first added value of the i-th packet in the set of ascending natural numbers is smaller than the first added value of the (i+1)th packet, wherein the i is a positive integer.
  • the determining module is configured to: the coding block size is an element value in a set of coding block sizes, the set of coding block sizes is an ascending first natural array; and the coding extension factor is one One of the group coding extension factors Element value, the set of coding extension factors being the second natural array in ascending order.
  • the set of coding block sizes includes consecutive a elements, wherein a value of a first element of the consecutive a elements is greater than z(j) ⁇ kb, and a tail element value is less than or equal to z (
  • the coding extension factor corresponding to the consecutive a elements is z(j+1)
  • the a is a positive integer
  • the z(j) is the set of coding extensions
  • the jth element value in the factor, the j is a positive integer
  • the kb is a parameter of the base check matrix.
  • the coding extension factor is z(j+1).
  • the coding spreading factor is determined to be z. (j+1), wherein the z(j) is a j-th element value of the set of coding spreading factors.
  • the group of coding extension factors includes a plurality of packets, wherein a second added value of adjacent elements in the group of the plurality of packets is equal, and a th-th packet of the plurality of packets is The second added value is smaller than the second added value of the h+1th packet, and the h is a positive integer.
  • all of the set of coding spreading factors greater than the positive integer value p are n times the positive integer of the positive integer value p.
  • the set of coding block sizes includes at least: a product value obtained by multiplying a parameter kb of the basic parity check matrix by the set of coding extension factors, and an interval between all the product values is B.
  • the device further includes: a first bit filling module, configured to perform bit filling on the first data sequence, where performing bit filling on the first data sequence comprises: dividing the first data sequence into multiple a plurality of sub-data sequences are bit-filled, and all sub-data sequences after the padding constitute the data sequence to be encoded.
  • a first bit filling module configured to perform bit filling on the first data sequence, where performing bit filling on the first data sequence comprises: dividing the first data sequence into multiple a plurality of sub-data sequences are bit-filled, and all sub-data sequences after the padding constitute the data sequence to be encoded.
  • the device further includes: a second bit filling module, configured to perform bit filling on the second data sequence, where performing bit filling on the second data sequence comprises: dividing the second data sequence into a sub-data sequence in which the number of kb bits is less than or equal to z, and padding bits are added to each sub-data sequence such that the number of bits of each group of sub-data sequences reaches z, and all sub-data sequences after padding constitute the data sequence to be encoded.
  • kb is the parameter of the base check matrix
  • z is the coded spread factor.
  • the apparatus further includes: an adding module, configured to add a L-bit cyclic redundancy check CRC sequence to the third data sequence to obtain the first data sequence or the second data sequence, where L is an integer greater than or equal to zero.
  • an adding module configured to add a L-bit cyclic redundancy check CRC sequence to the third data sequence to obtain the first data sequence or the second data sequence, where L is an integer greater than or equal to zero.
  • the parameter kb of the basic check matrix is a difference between the number of columns of the coding basic check matrix and the number of rows of the coding basic check matrix, and kb is one of greater than or equal to 4 and less than or equal to 64. Integer.
  • the positive integer value p is an LDPC decoding parallelism.
  • the positive integer value p is a fixed positive integer
  • the LDPC decoding parallel degree p includes: the positive integer value p is a positive integer power of 2 or the positive integer value p is 2 The integer power is multiplied by a prime number.
  • the positive integer value p is an element of the subset P, wherein the subset P is a subset of all positive integer factors of Pmax, and Pmax is greater than 3 and less than or equal to 1024 An integer.
  • the subset nSet includes one of: a subset of the first F elements of the positive integer set Ns, a subset of the last F elements of the positive integer set Ns, the a subset of F prime numbers in a positive integer set Ns, a subset of F odd numbers in the positive integer set Ns, and a subset of F even numbers in the positive integer set Ns, F is less than M Positive integer.
  • the coding spreading factor includes: the coding spreading factor is equal to a positive integer power of 2 and then decremented by 1, or the coding spreading factor is equal to a positive integer power of 2 and multiplied by a prime number, the prime number Includes one of the following: 3, 5, 7, 11, 13, 17, 19, 23, 29.
  • the coding spreading factor is equal to a positive integer power of 2 and is multiplied by a prime number including 3 and 5.
  • the coding spreading factor is equal to a positive integer power of 2 and is multiplied by a prime number including 5 and 7.
  • the coding spreading factor is equal to a positive integer power of 2 and is multiplied by a prime number including 3, 5, and 7.
  • the coding extension factor includes one of the following: 7, 15, 31, 63, 127, 255, 511, 1023, 2047, 4095.
  • the device further includes: a storage module, configured to store at least the basic check matrix.
  • the device is further configured to: after the data sequence to be encoded is encoded, fill the data sequence to be encoded with dummy bits of length k′ bits to obtain data to be encoded with a length of kb*z bits.
  • a sequence wherein a ratio of k' to kb*z is less than or equal to 1/4, k' is an integer greater than or equal to 0, the kb is a number of system columns of the basic check matrix, and z is used for encoding
  • the expansion factor size, kb is an integer greater than 1, and z is an integer greater than zero.
  • the spreading factor z is n times a positive integer value pl.
  • the positive integer value pl is an element of the subset Pset, wherein the subset Pset is a subset of all positive integer factors of Pmax, n is a natural number, and Pmax is greater than or equal to An integer of 4.
  • the positive integer value pl is an element of the subset Pset, all values of the positive integer n constitute a subset nSet, plmax is the maximum value in the subset Pset, and nmax is the largest in the subset nSet Value, where Kmax ⁇ kb ⁇ plmax ⁇ nmax ⁇ 1.2 ⁇ Kmax, and Kmax is an integer greater than 1024.
  • the Kmax is equal to 2000, 2048, 4000, 4096, 6000, 6144, 8000, 8192, 12000 or 12288.
  • the elements of the row index i and the column index j in the matrix and the hbij indicate a non-all 0 square matrix, A is a fixed integer smaller than pl and greater than or equal to 0, and Pmax is an integer greater than or equal to 4.
  • the parameter kb of the basic check matrix is the number of base check matrix system columns.
  • the LDPC coding and decoding is performed according to the basic check matrix and the coding extension factor. Therefore, the flexibility of data processing of the LDPC coding code is improved, thereby solving the problem of low data processing flexibility of the LDPC coding code in the related art.
  • FIG. 1 is a block diagram showing the hardware structure of a mobile terminal for processing data of a structured LDPC code according to an embodiment of the present invention
  • FIG. 2 is a flowchart of a data processing method for a structured LDPC code according to an embodiment of the present invention
  • FIG. 3 is a structural block diagram 1 of a data processing apparatus for a structured LDPC code according to an embodiment of the present invention
  • FIG. 4 is a structural block diagram 2 of a data processing apparatus for a structured LDPC code according to an embodiment of the present invention
  • FIG. 5 is a structural block diagram 3 of a data processing apparatus for a structured LDPC code according to an embodiment of the present invention
  • FIG. 6 is a schematic diagram of a basic check matrix in accordance with an alternative embodiment of the present invention.
  • Figure 7 is a first schematic diagram of a basic parity check matrix Hb' in accordance with an alternative embodiment of the present invention.
  • Figure 8 is a second schematic diagram of a basic parity check matrix Hb' in accordance with an alternative embodiment of the present invention.
  • FIG. 9 is a diagram showing a performance comparison of different filling methods under an additive white noise channel in accordance with an alternative embodiment of the present invention.
  • FIG. 10 is a memory diagram of an LDPC code decoder in accordance with an alternative embodiment of the present invention.
  • Embodiment 1 of the present application can be executed in a mobile terminal, a computer terminal or the like.
  • the mobile terminal 10 may include one or more. (only one is shown) processor 102 (processor 102 may include, but is not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA), a memory 104 for storing data, and a communication function. Transmission device 106.
  • processor 102 may include, but is not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA
  • memory 104 for storing data
  • Transmission device 106 Transmission device 106.
  • the structure shown in FIG. 1 is merely illustrative and does not limit the structure of the above electronic device.
  • the mobile terminal 10 may also include more or fewer components than those shown in FIG. 1, or have a different configuration than that shown in FIG.
  • the memory 104 can be used to store software programs and modules of application software, such as program instructions/modules corresponding to the carrier phase recovery method method in the embodiment of the present invention, and the processor 102 executes by executing software programs and modules stored in the memory 104.
  • Memory 104 may include high speed random access memory, and may also include non-volatile memory such as one or more magnetic storage devices, flash memory, or other non-volatile solid state memory.
  • memory 104 may further include memory remotely located relative to processor 102, which may be connected to mobile terminal 10 over a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.
  • Transmission device 106 is for receiving or transmitting data via a network.
  • the above-described network specific example may include a wireless network provided by a communication provider of the mobile terminal 10.
  • the transmission device 106 includes a Network Interface Controller (NIC) that can be connected to other network devices through a base station to communicate with the Internet.
  • the transmission device 106 can be a Radio Frequency (RF) module for communicating with the Internet wirelessly.
  • NIC Network Interface Controller
  • RF Radio Frequency
  • FIG. 2 is a flowchart of a data processing method for a structured LDPC code according to an embodiment of the present invention. As shown in FIG. 2, the process includes The following steps:
  • Step S202 obtaining a coding block size of the structured LDPC coding
  • Step S204 determining, according to one of the following parameters, a coding extension factor z: a coding block size, a parameter kb of a basic parity check matrix, a positive integer value p, a mb row, and a basic parity check matrix of the nb column;
  • Step S206 encoding the data sequence to be encoded or decoding the data sequence to be decoded according to the basic check matrix and the coding extension factor;
  • kb nb-mb
  • kb, p, mb, z and nb are all integers greater than one.
  • the data processing method of the above structured LDPC code may be, but is not limited to, applied to a scene in which a data sequence is processed.
  • LDPC encoding and decoding processing a sequence of data sequences.
  • the data processing method of the foregoing structured LDPC code may be, but is not limited to, applied to an LDPC encoder or an LDPC decoder, for example, a transmitting end that uses LDPC encoding, and a receiving end that uses LDPC decoding.
  • the coding block size of the structured LDPC coding determining the coding extension factor z according to at least one of the following parameters: the coding block size, the parameter kb of the basic check matrix, the positive integer value p; according to the basic check matrix and coding
  • the spreading factor encodes the encoded data sequence or decodes the data sequence to be decoded. It can be seen that at least one of the encoding block size of the LDPC encoding, the parameter kb of the basic parity check matrix, and the positive integer value p is used according to the above scheme.
  • the coding extension factor is determined, and the LDPC coding and decoding code is performed according to the basic check matrix and the coding extension factor.
  • the flexibility of data processing of the LDPC coding code is improved, thereby solving the problem of low data processing flexibility of the LDPC coding code in the related art.
  • effective LDPC encoding and decoding are performed on coding block sizes of different lengths, thereby reducing the complexity of the LDPC coding code.
  • the coding block size is equal to a value obtained by multiplying the parameter kb of the basic check matrix by one element of a set of ascending natural numbers.
  • a set of ascending natural numbers may include, but is not limited to, including a plurality of packets, wherein a first added value of adjacent elements in the plurality of packets is equal.
  • the first added value of the i-th packet in the set of ascending natural numbers is smaller than the first added value of the i+1th packet, where i is a positive integer.
  • the coding extension factor is determined according to the coding block size, but not limited to: the coding block size is one element value in a set of coding block sizes, and the first coding block size is in ascending order. Natural array; the coding spreading factor is an element value of a set of coding spreading factors, and a set of second natural arrays whose coding spreading factor is ascending.
  • a set of coding block sizes includes consecutive a elements, wherein a first element value of consecutive a elements is greater than z(j) ⁇ kb, and a tail element value is less than or equal to z(j+1)
  • the coding spreading factor corresponding to consecutive a elements is z(j+1)
  • a is a positive integer
  • z(j) is the j-th element value of a set of coding spreading factors
  • j is positive
  • the integer, kb is the parameter of the underlying check matrix.
  • the coding extension factor The child can be, but is not limited to, z(j+1).
  • the coding spreading factor is determined to be z(j+1), Where z(j) is the value of the jth element in a set of coding spreading factors.
  • a set of coding spreading factors may include, but is not limited to, including a plurality of packets, wherein a second added value of adjacent elements in the plurality of packets is equal, and a second increase of the h th group of the plurality of packets The value is less than the second added value of the h+1th packet, and h is a positive integer.
  • all of the set of coding spreading factors greater than the positive integer value p are n times the positive integer of the positive integer value p.
  • a set of coding block sizes may include, but is not limited to, at least: a product value obtained by multiplying a parameter kb of the basic check matrix by a set of coding spreading factors, and an integer value of B between all product values, wherein , B is a positive integer.
  • the first data sequence may be bit-filled, where the bit filling of the first data sequence includes: dividing the first data sequence into multiple sub-data sequences, and pairing the plurality of sub-data The sequences are bit-filled separately, and all sub-data sequences after padding constitute a sequence of data to be encoded.
  • the second data sequence may be bit-filled, where the bit filling of the second data sequence comprises: dividing the second data sequence into kb number of bits less than or equal to z a sub-data sequence, adding padding bits to each sub-data sequence such that the number of bits of each group of sub-data sequences reaches z, and all sub-data sequences after padding bits constitute a sequence of data to be encoded, where kb is a parameter of the base check matrix, z Is the coding extension factor.
  • the first data sequence may be obtained by adding, but not limited to, adding a L-bit cyclic redundancy check CRC sequence to the third data sequence.
  • the parameter kb of the basic check matrix is a difference between the number of columns of the basic check matrix and the number of rows of the basic check matrix, and kb is an integer greater than or equal to 4 and less than or equal to 64.
  • the positive integer value p is the LDPC decoding parallelism.
  • the positive integer value p is a fixed positive integer
  • the LDPC decoding parallel degree p includes: a positive integer power p is a positive integer power of 2 or a positive integer value p is a positive integer power of 2 and multiplied by a prime number .
  • the positive integer value p is an element of the subset P, wherein the subset P is a subset of the set of all positive integer factors of Pmax, and Pmax is an integer greater than 3 and less than or equal to 1024 .
  • the subset nSet includes one of: a subset of the first F elements in the positive integer set Ns, a subset of the last F elements in the positive integer set Ns, and F of the positive integer set Ns
  • a subset of prime numbers, a subset of F odd numbers in a positive integer set Ns, and a subset of F even numbers in a positive integer set Ns, F is a positive integer smaller than M.
  • the coding spreading factor may include, but is not limited to, including a positive integer power equal to 2 and then subtracting 1 or a positive integer power equal to 2 and multiplied by a prime number, the prime number including one of the following : 3, 5, 7, 11, 13, 17, 19, 23, 29.
  • the coded spreading factor is equal to a positive integer power of 2 and multiplied by a prime number including 3 and 5.
  • the coded spreading factor is equal to a positive integer power of 2 and multiplied by a prime number including 5 and 7.
  • the coded spreading factor is equal to a positive integer power of 2 and multiplied by a prime number including 3, 5, and 7.
  • the coding spreading factor comprises one of the following: 7, 15, 31, 63, 127, 255, 511, 1023, 2047, 4095.
  • the basic check matrix may also be stored.
  • the dummy data bit of length k′ bits may be filled in the data sequence to be encoded to obtain a data sequence to be encoded with a length of kb*z bits, where k′ and kb*z The ratio is less than or equal to 1/4, where k' is an integer greater than or equal to 0, kb is the number of system columns of the underlying check matrix, z is the size of the spreading factor used for encoding, kb is an integer greater than 1, and z is greater than 0 The integer.
  • the basic parity check matrix of the LDPC code has a certain degree of distribution.
  • the padding bit is too large, the degree distribution of the LDPC code will be damaged, which will affect the decoding performance of the LDPC code.
  • the beneficial effects within 1/4 are that the basic characteristics of the LDPC code basic check matrix are not changed much, and the decoding performance of the LDPC code is not changed much.
  • the number and location of padding bits here are known with respect to both the originating end and the receiving end, and do not include padding bits during data transmission. Since these bits are known during LDPC code decoding, It does not affect the decoding result. If all the bits in a column in the corresponding basic check matrix are padding bits, it means that the corresponding column of the basic check matrix is deleted, so the degree distribution of the basic check matrix is changed at this time. .
  • the spreading factor z is n times the positive integer value pl.
  • the positive integer value pl is an element of the subset Pset, wherein the subset Pset is a subset of the set of all positive integer factors of Pmax, n is a natural number, and Pmax is an integer greater than or equal to 4.
  • the parameter kb of the basic check matrix is the number of base check matrix system columns.
  • the data processing device of the structured LDPC code is also provided in the embodiment, and the device is used to implement the foregoing embodiments and optional implementations, and details are not described herein.
  • the term "module” may implement a combination of software and/or hardware of a predetermined function.
  • the apparatus described in the following embodiments is preferably implemented in software, hardware, or a combination of software and hardware, is also possible and contemplated.
  • FIG. 3 is a structural block diagram 1 of a data processing apparatus for a structured LDPC code according to an embodiment of the present invention. As shown in FIG. 3, the apparatus includes:
  • an obtaining module 32 configured to obtain a coding block size of the structured LDPC encoding
  • a determining module 34 coupled to the obtaining module 32, for determining a coding spreading factor z according to at least one of the following parameters: a coding block size, a parameter kb of the basic check matrix, and a positive integer value p;
  • the processing module 36 is coupled to the determining module 34, for encoding the coded data sequence according to the basic check matrix and the coding extension factor, or decoding the data sequence to be decoded;
  • kb nb-mb
  • kb, p, mb, z and nb are all integers greater than one.
  • the data processing apparatus of the above structured LDPC code may be, but is not limited to, applied to a scene in which a data sequence is processed.
  • LDPC encoding and decoding processing a sequence of data sequences.
  • the data processing apparatus of the foregoing structured LDPC code may be, but is not limited to, applied to an LDPC encoder or an LDPC decoder, for example, a transmitting end that uses LDPC encoding, and a receiving end that uses LDPC decoding.
  • the matrix and the coding extension factor are used for LDPC coding and decoding. Therefore, the flexibility of data processing of the LDPC coding code is improved, thereby solving the problem of low data processing flexibility of the LDPC coding code in the related art. Further, effective LDPC encoding and decoding are performed on coding block sizes of different lengths, thereby reducing the complexity of the LDPC coding code.
  • the determining module can be, but is not limited to, for: passing a formula Determining a coding spreading factor, where CBS is a coding block size, Indicates rounding up.
  • the obtaining module may be, but is not limited to, a parameter kb and a coded block size equal to the basic check matrix. The value obtained by multiplying one element in the ascending natural number.
  • a set of ascending natural numbers may include, but is not limited to, including a plurality of packets, wherein a first added value of adjacent elements in the plurality of packets is equal.
  • the first added value of the i-th packet in the set of ascending natural numbers is smaller than the first added value of the i+1th packet, where i is a positive integer.
  • the determining module is configured to: the coding block size is an element value in a set of coding block sizes, and the first coding array is a first natural array in ascending order; the coding extension factor is an element in a set of coding extension factors. Value, a second natural array of coded expansion factors in ascending order.
  • a set of coding block sizes includes consecutive a elements, wherein a first element value of consecutive a elements is greater than z(j) ⁇ kb, and a tail element value is less than or equal to z(j+1)
  • the coding spreading factor corresponding to consecutive a elements is z(j+1)
  • a is a positive integer
  • z(j) is the j-th element value of a set of coding spreading factors
  • j is positive
  • the integer, kb is the parameter of the underlying check matrix.
  • the coding extension factor is z(j+1).
  • the coding spreading factor is determined to be z(j+1), Where z(j) is the value of the jth element in a set of coding spreading factors.
  • a set of coding spreading factors includes a plurality of packets, wherein a second added value of adjacent elements in the plurality of packets is equal, and a second added value of the h th group of the plurality of packets is smaller than the hth
  • the second added value of +1 packet, h is a positive integer.
  • all of the set of coding spreading factors greater than the positive integer value p are n times the positive integer of the positive integer value p.
  • the set of coding block sizes includes at least: a product value obtained by multiplying a parameter kb of the basic check matrix by a set of coding extension factors, and an integer value of an interval B between all product values, where B is positive Integer.
  • FIG. 4 is a block diagram showing the structure of a data processing apparatus for a structured LDPC code according to an embodiment of the present invention. As shown in FIG. 4, the apparatus further includes:
  • the first bit filling module 42 is coupled to the processing module 36 for performing bit filling on the first data sequence, wherein performing bit filling on the first data sequence comprises: dividing the first data sequence into multiple sub-data sequences, for multiple sub- The data sequences are bit-filled separately, and all sub-data sequences after padding constitute a sequence of data to be encoded.
  • FIG. 5 is a structural block diagram 3 of a data processing apparatus for a structured LDPC code according to an embodiment of the present invention. As shown in FIG. 5, optionally, the apparatus further includes:
  • a second bit padding module 52 coupled to the processing module 36, for bit stuffing the second data sequence
  • Bit filling on the second data sequence includes: dividing the second data sequence into sub-data sequences whose kb-bit number is less than or equal to z, adding padding bits to each sub-data sequence such that the number of bits of each group of sub-data sequences reaches z
  • the sub-data sequence after all padding bits constitutes a data sequence to be encoded, where kb is a parameter of the base check matrix and z is a coding spreading factor.
  • the device further includes: an adding module, coupled to the first bit filling module 42 or the second bit filling module 52, configured to add a L-bit cyclic redundancy check CRC sequence to the third data sequence to obtain the first data sequence Or a second data sequence, wherein L is an integer greater than or equal to zero.
  • an adding module coupled to the first bit filling module 42 or the second bit filling module 52, configured to add a L-bit cyclic redundancy check CRC sequence to the third data sequence to obtain the first data sequence Or a second data sequence, wherein L is an integer greater than or equal to zero.
  • the parameter kb of the basic check matrix is a difference between the number of columns of the coded basic check matrix and the number of rows of the coded base check matrix, and kb is an integer greater than or equal to 4 and less than or equal to 64.
  • the positive integer value p may be, but is not limited to, LDPC decoding parallelism.
  • the positive integer value p is a fixed positive integer
  • the LDPC decoding parallel degree p includes: a positive integer power p is a positive integer power of 2 or a positive integer value p is a positive integer power of 2 and multiplied by a prime number .
  • the positive integer value p is an element of the subset P, wherein the subset P is a subset of the set of all positive integer factors of Pmax, and Pmax is an integer greater than 3 and less than or equal to 1024 .
  • the subset nSet includes one of: a subset of the first F elements in the positive integer set Ns, a subset of the last F elements in the positive integer set Ns, and F of the positive integer set Ns
  • a subset of prime numbers, a subset of F odd numbers in a positive integer set Ns, and a subset of F even numbers in a positive integer set Ns, F is a positive integer smaller than M.
  • the first case “a positive integer value p is a positive integer power of 2” and the second case “a positive integer value p is a positive integer power of 2 and multiplied by a prime number” is exclusive, if If the prime number is 2, then the first case and the second case are the same situation, which is unreasonable. Therefore, the case where the prime number is 2 needs to be classified into the first case. Further, the understanding of this article is: the first case is 1*2 power, and 1 is not a prime. So the prime number here is at least 3 or more.
  • the coding spreading factor comprises: a positive spreading power equal to 2 and then subtracting 1 or a positive integer power equal to 2 and multiplied by a prime number, the prime number including one of the following: 3, 5 7, 11, 13, 13, 17, 19, 23, 29.
  • the coded spreading factor is equal to a positive integer power of 2 and multiplied by a prime number including 3 and 5.
  • the coded spreading factor is equal to a positive integer power of 2 and multiplied by a prime number including 5 and 7.
  • the coded spreading factor is equal to a positive integer power of 2 and multiplied by a prime number including 3, 5, and 7.
  • the coding spreading factor comprises one of the following: 7, 15, 31, 63, 127, 255, 511, 1023, 2047, 4095.
  • the apparatus may further include: a storage module, configured to store at least the basic check matrix.
  • the device is further configured to: before the encoding the data sequence to be encoded, fill the data sequence to be encoded with dummy bits of length k′ bits to obtain a data sequence to be encoded having a length of kb*z bits, where k 'The ratio to kb*z is less than or equal to 1/4, k' is an integer greater than or equal to 0, kb is the number of system columns of the underlying check matrix, z is the size of the spreading factor used for encoding, and kb is an integer greater than 1. , z is an integer greater than zero.
  • the spreading factor z is n times the positive integer value pl.
  • the positive integer value pl is an element of the subset Pset, wherein the subset Pset is a subset of the set of all positive integer factors of Pmax, n is a natural number, and Pmax is an integer greater than or equal to 4.
  • the elements of the column index j and hbij indicate a non-all-square matrix, A is a fixed integer smaller than pl and greater than or equal to 0, and Pmax is an integer greater than or equal to 4.
  • the parameter kb of the basic check matrix is the number of base check matrix system columns.
  • each of the above modules may be implemented by software or hardware.
  • the foregoing may be implemented by, but not limited to, the foregoing modules are all located in the same processor; or, the modules are located in multiple In the processor.
  • An optional embodiment of the present invention provides an LDPC coding and decoding method, where the method includes the following steps:
  • Step 101 Obtain a coding block size of the structured LDPC code.
  • Step 102 Determine a coding spreading factor z according to at least one of the following parameters: a coding block size, a parameter kb of a basic check matrix, a positive integer value p, and a basic check matrix;
  • Step 103 Encode the data sequence to be encoded or decode the data sequence to be decoded according to the basic check matrix and the coding spreading factor.
  • determining the coding spreading factor according to at least the coding block size CBS, the parameter kb of the basic check matrix, and the positive integer value p includes: the coding spreading factor is equal to Among them, CBS is the coding block size.
  • the positive integer value p corresponds to the LDPC decoding parallelism, or is equal to an integer multiple of the decoding parallelism.
  • the coding spreading factor is related to the degree of parallelism.
  • the coding block size is equal to the parameter kb of the basic check matrix and one element of a set of ascending natural numbers Multiply the value obtained.
  • the parameter kb of the basic check matrix is the difference between the number of basic check matrix columns and the number of basic check matrix rows, and the parameter kb of the basic check matrix is equal to an integer ranging from integer 4 to 64.
  • a group of ascending natural numbers includes a plurality of groups, and the added value in the group is equal.
  • the added value of the i-th packet is smaller than the added value of the i+1th packet, where i is a positive integer.
  • the coding block size is an element value in a set of coding block sizes
  • the coding spreading factor is an element value of a set of spreading factors
  • a set of coding block sizes are a set of natural numbers in ascending order
  • a set of spreading factors are Is a set of natural numbers in ascending order.
  • a consecutive one element of a set of coding block sizes wherein the first element value of consecutive a elements is greater than z(j) ⁇ kb, and the tail element value is less than or equal to z(j+1) ⁇ kb
  • the coding spreading factor corresponding to consecutive a elements is z(j+1), where a is a positive integer and z(j) is the jth element value of a set of spreading factors.
  • the coding extension factor is limited to z(j+1).
  • a set of spreading factors including multiple packets, the added value in the packet is equal, and the added value of the h th packet is smaller than the added value of the h+1th packet, where h is a positive integer.
  • a set of coding block sizes includes at least: a product value obtained by multiplying a parameter kb of the base check matrix by a set of spreading factors, and an integer value of B between all product values, where B is a positive integer.
  • the product value obtained by multiplying the parameter kb of the basic check matrix by a set of spreading factors is actually the maximum number of system bits supported by the LDPC code under different coding spreading factors, and the coding block size may also be included between the number of bits of each system.
  • the coding block size can be made more flexible, and it is convenient to use in various communication systems, and at the same time solves the problem that the code length and the code rate flexibility of the LDPC code are insufficient.
  • the coding spreading factor is equal to a positive integer power of 2 and then decremented by 1, and more specifically, the coding spreading factor comprises: equal to 7, 15, 31, 63, 127, 255, 511, 1023, 2047, and 4095. one of.
  • cyclic redundancy check CRC
  • every z-bit packet in the parity bit of the LDPC code can be obtained as a CRC cyclic code, and the CRC check can still be performed, which is advantageous for improving the decoding performance of the LDPC code, and is iterative decoding.
  • the process accelerates the decoding convergence, reduces the decoding time and increases the decoding speed, and z is equal to the value of the spreading factor; or, the coding spreading factor can be equal to the positive power of 2 and multiplied by a prime number, more specifically, for example, A prime number is from one of 2, 3, 5, 7, 11, 13, 17, 19, 23, and 29. According to the definition of prime numbers, the integer factor is nothing except 1 and itself, then the integer is a prime number, so 1 is not a prime number.
  • the spreading factor value is used to simplify the interleaving and de-interleaving network of the LDPC code.
  • each element value in the basic check matrix corresponds to a cyclic shift number, and the above value can be used according to a certain principle, which can simplify the interleaving.
  • the network and the de-interleaving network further reduce the complexity of the LDPC code (the interleaving network occupies about 40% of the decoding complexity of the LDPC code. Once the part is reduced, the LDPC decoding complexity can be simplified).
  • the coding spreading factor may be equal to a positive integer power of 2 and multiplied by a prime number, the prime number includes 3 and 5, and the positive integer is 1, 2, 3, 4, 5, 6, 7, 8.
  • the benefit of using the spreading factor is that the LDPC decoder can be made to have low complexity and support flexible code length design.
  • the storage module, the interleaving network module, the deinterleaving network module, and the computing module are generally included, and the updated total soft information is stored in the storage module (the total soft information is the result of adding all the external information.
  • the decoder needs to allocate 1 memory block for each column in the basic check matrix (if the base check matrix size is mb row nb column, there are nb memory blocks), and each memory block is divided into Multiple address blocks, each address block can be defined as 1 word, then a single memory block can store multiple words.
  • the decoding parallelism is generally equal to the word size, and the word size refers to The number of soft bits stored in word.
  • the prime number can include 5 and 7, and the power of 2 is (1, 2, 3, 4, 5, 6, 7, 8).
  • the word size is also 256, which requires 7 words.
  • a large prime number of 7, can make the expansion factor larger and can support a larger code length.
  • the prime number can include 3, 5, and 7, and the power of 2 is (1, 2, 3, 4, 5, 6, 7, 8), and the word size is also 256, since the maximum prime number is 7.
  • An optional embodiment of the present invention further provides an LDPC codec device, the device comprising:
  • the obtaining module 201 is configured to obtain a coding block size of the structured LDPC code.
  • the determining module 202 is configured to determine a coding spreading factor z according to at least one of the following parameters: a coding block size, a parameter kb of a basic check matrix, a positive integer value p, and a basic check matrix;
  • the encoding module 203 is configured to code the data sequence to be encoded or decode the data sequence to be decoded according to the basic check matrix and the coding spreading factor.
  • the storage module 204 is configured to store at least a basic check matrix.
  • the coding block size is limited to a value obtained by multiplying the parameter kb of the basic check matrix by a set of ascending natural numbers.
  • the parameter kb of the basic check matrix is the difference between the number of basic check matrix columns and the number of basic check matrix rows, and the parameter kb of the basic check matrix is equal to an integer ranging from integer 4 to 64.
  • the added value in the group is equal.
  • the added value of the i-th packet is smaller than the added value of the i+1th packet, where i is a positive integer.
  • determining a coding spreading factor according to the coding block size and the positive integer value p including: the coding extension factor is equal to Where CBS is the coding block size, kb is the difference between the number of basic check matrix columns and the number of basic check matrix rows, and p is a positive integer.
  • the coding block size is an element value in a set of coding block sizes
  • the coding spreading factor is an element value of a set of spreading factors
  • a set of coding block sizes are a set of natural numbers in ascending order
  • a set of spreading factors are Is a set of natural numbers in ascending order
  • the dimension of a set of code block sizes is greater than or equal to the dimension of a set of spread factors.
  • a consecutive one element of a set of coding block sizes wherein the first element value of consecutive a elements is greater than z(j) ⁇ kb, and the tail element value is less than or equal to z(j+1) ⁇ kb
  • the coding spreading factor corresponding to consecutive elements a is z(j+1), where a is a positive integer and z(j) is the i-th element value of a set of spreading factors.
  • the coding block size belongs to consecutive a elements, the coding spreading factor is limited to z(j+1).
  • a set of spreading factors, including a plurality of packets the added value in the packet is equal, and the added value of the i-th packet is smaller than the added value of the i+1th packet, where i is a positive integer.
  • the set of coding block sizes includes at least: a product value obtained by multiplying a parameter kb of the basic check matrix by a set of spreading factors, and an integer value of an interval B between all product values, where B is a positive integer.
  • the coding spreading factor is equal to a positive integer power of 2 and then decremented by 1, or a positive integer power equal to 2 and multiplied by a prime number. More specifically, the coding spreading factor includes: one of 7, 15, 31, 63, 127, 255, 511, 1023, 2047, and 4095.
  • a data processing method for the structured LDPC code is also provided in this embodiment.
  • the method is used to implement the foregoing LDPC code encoding and decoding method, and has not been described again.
  • the terms "method” or “module” and the like may implement a combination of software and/or hardware of a predetermined function.
  • the methods described in the following embodiments are preferably implemented in software, hardware, or a combination of software and hardware, is also possible and contemplated.
  • a data processing method for a structured LDPC code according to an embodiment of the present invention is used for a transmitting end, and the method includes the following steps:
  • Code block segmentation which divides a code block of length CL into a plurality of coded blocks
  • a coding spreading factor z according to at least one of the following parameters: the coding block size, a parameter kb of a basic check matrix, a positive integer value p, and a basic check matrix;
  • the coding extension factor is determined by the coding block size, wherein determining the coding extension factor according to the coding block size comprises: the coding block size is an element value of a set of coding block sizes, a set of first natural arrays of coded block sizes in ascending order; and the coded spread factor is an element value of a set of coded spread factors, the set of coded spread factors being a second natural array in ascending order.
  • all of the set of coding spreading factors greater than the positive integer value p are n times the positive integer of the positive integer value p.
  • the positive integer value p is an element of the subset Pset, wherein the subset Pset is a subset of all positive integer factors of Pmax, and Pmax is greater than 3 and less than or equal to 1024.
  • An integer is the maximum decoding parallelism supported by the LDPC decoder at the data receiving end.
  • the decoding parallel degree refers to the number of parity code updates that can be simultaneously performed in the LDPC decoder
  • the Pmax refers to the maximum parallelism supported by the LDPC decoder.
  • the maximum degree of decoding parallelism supported in an LDPC decoder is Pmax, which can support other parallelisms less than Pmax, possibly adding some control circuitry.
  • An LDPC code encoding instance on the transmitting end needs to transmit a transport block size of 4000 bits.
  • the basic check matrix used in the LDPC code is as follows, and the corresponding set of coding spreading factors is [2 4 6 8 10 12 16 20 24 32 40 48 64 80 96 128 160 192 256 320 384 512 640 768 1024 1280].
  • the set of spreading factors includes [1 2 3 4 5 6 7 8] powers of 5 times 2, [10 20 40 80 160 320 640 1280]; and also includes 3 times 2 [2 2 3 4 5 6 7 8] powers, [6 12 24 48 96 192 384 768]; and also includes 2 times 2 [2 2 3 4 5 6 7 8] powers, [4 8 16 32 64 128 256 512]; and also includes 1 times 2 [2 2 3 4 5 6 7 8] powers, which is [2 4 8 16 32 64 128 256]. That is, the value of the sub-set nSet includes [1 2 3 5], and the value of the sub-set Pset includes [2 4 8 16 32 64 128 256].
  • the spreading factor in the set of coding spreading factors is equal to n times the positive integer of the positive integer value p, where n is an element of the subset nSet and p is an element of the subset Pset.
  • the basic check matrix can also be a basic check matrix or other designation.
  • the spreading factor may also be referred to as a boost value or a sub-matrix size or the like.
  • the basic check matrix used by the LDPC code is equal to:
  • This example includes the following steps:
  • 8000 bits are selected from the 13312 bits for transmission
  • the receiving end has a receiving end for receiving the transmitted LDPC codeword.
  • Said The LDPC decoding method at the receiving end includes the following steps:
  • the obtained code block size may be obtained by signaling configured by the system;
  • the corresponding set of coding spreading factors is [2 4 6 8 10 12 16 20 24 32 40 48 64 80 96 128 160 192 256 320 384 512 640 768 1024 1280].
  • the set of spreading factors includes [1 2 3 4 5 6 7 8] powers of 5 times 2, [10 20 40 80 160 320 640 1280], set to Z0; and also includes 3 times 2 [1 2 3 4 5 6 7 8] powers, [6 12 24 48 96 192 384 768], set to set Z1; and also include 2 times 2 [1 2 3 4 5 6 7 8]
  • the power is [4 8 16 32 64 128 256 512], set to set Z2; and also includes 1 times 2 [2 2 3 4 5 6 7 8] powers, which is [2 4 8 16 32 64 128 256], set to set Z3; so the decoder can support the maximum decoding parallelism of 2 to the power of 8, that is, the degree of parallelism is 256, that is, Pmax is 256, the maximum value of
  • the soft information in the decoder is stored in 5 words respectively; if there are 3 words in the set Z1; There are 2 words in the set Z2; if there is 1 word in the set Z3.
  • a decoder method similar to that described in Embodiment 2 is employed, which in turn can support flexible code length design.
  • the LDPC code may also include the following examples.
  • a set of spreading factors takes the value [18 21 30 35 42 63 70 105 126 210], which includes 2 sets [6 7 14 21 42]*3 and [6 7 14 21 42]*5, ie the sub-set Pset is [6 7 14 21 42], the subset nSet is [3 5].
  • the base check matrix is equal to:
  • the sender performs data processing according to the steps described above, confirms the spreading factor and the basic check matrix, and advances.
  • Line structured LDPC encoding the specific steps will not be described here; the receiving end is also the same, according to the above steps.
  • the maximum parallelism that can be adopted by the decoder at the receiving end is the largest element 42 in the subset Pset.
  • the degree of parallelism of the decoding can be 42 or any one smaller than 42 and 42. Integer factor.
  • the spreading factor used for encoding is [6 7 14 21 42]*3
  • a memory block composed of 3 words is used for storing soft information required for decoding, such as determining an extension used for encoding.
  • the factor is 63. At this time, since it is divided into 3 words, the actual decoding parallel degree is 31; if the spreading factor used for encoding is [6 7 14 21 42]*5, a memory block composed of 5 words is used. The soft information required for storing the decoding, for example, the spreading factor used for encoding is 70. At this time, since it is divided into 5 words, the actual decoding parallel degree 14 is obtained.
  • a data processing method for the structured LDPC code is also provided in this embodiment.
  • the method is used to implement the foregoing LDPC code encoding and decoding method, and has not been described again.
  • the terms "method” or “module” and the like may implement a combination of software and/or hardware of a predetermined function.
  • the methods described in the following embodiments are preferably implemented in software, hardware, or a combination of software and hardware, is also possible and contemplated.
  • a data processing method for a structured LDPC code according to an embodiment of the present invention is used for a transmitting end, and the method includes the following steps:
  • Code block segmentation which divides a code block of length CL into a plurality of coded blocks
  • the elements in the basic check matrix matrix include at least two types: 1. an element indicating a full 0 square matrix, which is represented by -1 in the patent, and may also be represented by a null value or the like;
  • the elements of the cyclically shifted square matrix ie, the non-all-zero square matrix
  • the basic check matrix may also include a multilateral structure, where the change in the basic check matrix includes at least: the same row index and the column index have 2 elements for indicating 2 cyclic shift specific bits The addition of the square matrix afterwards.
  • a basic check matrix is provided below for the structured LDPC encoding method.
  • the advantageous effect of using the basic check matrix described above as the coding basic check matrix of the LDPC code is similar to that of Embodiment 2.
  • the word is stored as an address, and the storage of the information is very simple, and it is convenient to support the flexible code length design.
  • the description is made by taking Hb0 as an example.
  • the memory module of the decoder is as shown in FIG.
  • the total number of columns in the base check matrix is 12 columns, so there are 12 memory blocks, each of which has 5 words.
  • 1001 corresponds to the storage block of the 0th column of the basic check matrix
  • 1002 corresponds to the first column of the basic check matrix
  • the memory blocks can be shared when in different spreading factors.
  • the storage modules of Hb0 and Hb1 may be stored by using 1003 shown in FIG. 10, and the black description stores information. Since the spreading factor is 18 and 30 at this time, the soft bit information of each column corresponding to the basic check matrix is only 18 and 30, Therefore, the soft bit information in each word is stored in one soft bit information every 7, Hb0 uses 3 words, and Hb1 uses 5 words.
  • the black description stores information, since the expansion factors are 63 and 105 at this time, corresponding to the soft bit information of each column of the basic check matrix. Only 63 and 105, so the soft bit information in each word is stored as one soft bit information every 2, Hb2 uses 3 words, and Hb3 uses 5 words.
  • the black description stores information, since the expansion factors are 126 and 210 at this time, corresponding to the soft bit information of each column of the basic check matrix. Only 126 and 210, at this time, the soft bit information in each word is filled, Hb2 uses 3 words, and Hb3 uses 5 words.
  • the beneficial effect is that the LDPC decoder can be completely unified, greatly reducing the complexity brought by using multiple decoders, and the interleaving of each column in the basic check matrix.
  • the network can be shared or implemented using a fixed circuit network, reducing complexity and decoding delay.
  • the method proposed in the optional embodiment of the present invention may be used in an LTE mobile communication system or a fifth-generation mobile communication system in the future, and the data transmission direction is that the base station sends data to the mobile user (downlink transmission service data), or the data transmission direction is mobile.
  • the user transmits data to the base station (uplink transmission service data).
  • Mobile users include: mobile devices, Access terminal, user terminal, subscriber station, subscriber unit, mobile station, remote station, remote terminal, user agent, user equipment, user equipment, or some other terminology.
  • the base station includes an access point (AP), or may be referred to as a Node B, a Radio Network Controller (RNC), an Evolved Node B (eNB), a Base Station Controller (BSC), and a base transceiver station.
  • AP access point
  • RNC Radio Network Controller
  • eNB Evolved Node B
  • BSC Base Station Controller
  • BTS Base Station Controller
  • BTS base transceiver station
  • BS base station
  • the present embodiment provides a data processing method for a structured LDPC code, which is applied to an eMBB (enhanced Mobile Broadband) scenario and a URLLC in a New RAT (New Radio Access Technology).
  • Ultra-Reliable and Low Latency Communications scenarios or mMTC (massive Machine Type Communications) scenarios The maximum downlink throughput in the eMBB scenario can reach 20 Gbps, and the maximum throughput of the uplink data can reach 10 Gbps.
  • the BLER Block Error Rate
  • the data processing method of the structured LDPC code of this embodiment includes the following steps:
  • the coding spreading factor z is determined according to at least one of the following parameters: a coding block size, a parameter kb of the basic check matrix, and a positive integer value P;
  • determining a coding spreading factor according to at least a coding block size CBS, a parameter kb of the basic check matrix, and a positive integer value p including: Determining the coding spreading factor, where Indicates rounding up.
  • obtaining the coded block size of the structured LDPC code includes: the code block size is equal to a value obtained by multiplying a parameter kb of the basic check matrix by one element of a set of ascending natural numbers. And, a set of ascending natural numbers includes a plurality of packets, wherein a first added value of adjacent elements in the plurality of packets is equal. And, the first added value of the i-th packet in the set of ascending natural numbers is smaller than the first added value of the i+1th packet, where i is a positive integer.
  • the advantage of this design is that a set of ascending natural numbers is gradually increased, so it supports a smaller coding interval when the coding block size is smaller, and a smaller variation interval at a larger length, that is, a denser coding block size is not required.
  • the communication system is more flexible, and the signaling indication is less used, the signaling interaction is less, and the system complexity is low.
  • determining a coding spreading factor according to the coding block size including: the coding block size is an element value in a set of coding block sizes, and the first coding array size is an ascending first natural array; the coding extension factor is one The group encodes an element value in the spreading factor, and a set of encoding extension factors is the second natural array in ascending order.
  • a set of coding block sizes includes consecutive a elements, wherein the first element value of consecutive a elements is greater than z(j) ⁇ kb, and the tail element value is less than or equal to z(j+ 1)
  • the coding expansion factor corresponding to consecutive a elements is z(j+1)
  • a is a positive integer
  • z(j) is the value of the jth element in a set of coding spreading factors
  • j is a positive integer
  • kb is a parameter of the basic check matrix. If the obtained coding block size is one of the consecutive a elements, the coding spreading factor is z(j+1).
  • a plurality of packets are included in a set of coding spreading factors, wherein a second added value of adjacent elements in the plurality of packets is equal, and a second added value of the h-th packet in the plurality of packets is smaller than the h+1th packet
  • the second added value, h is a positive integer.
  • a set of coding block sizes includes at least a product value obtained by multiplying a parameter kb of a base check matrix by a set of coding extension factors, and an integer value of B between all product values, where B is a positive integer.
  • the coding spreading factor is determined to be z(j+1), where z( j) is the value of the jth element in a set of coding spreading factors. All of the set of coding spreading factors greater than the first positive integer value P are positive integer multiples of the first positive integer value P.
  • the first positive integer value P is the parallel degree of LDPC code decoding, and the purpose of limiting the spreading factor to be equal to an integer multiple of the parallel degree p is that the LDPC hierarchical decoding process can make the interleaving and inverse interleaving network of the decoder not appear.
  • the address conflict problem does not require additional hardware circuitry to indicate overhead, the decoding complexity is low, and the hardware circuit area is less.
  • the method further includes: performing bit filling on the first data sequence, where performing bit filling on the first data sequence includes: using the first data
  • the sequence is divided into a plurality of sub-data sequences, and the plurality of sub-data sequences are separately pad-filled, and all the sub-data sequences after the padding constitute a data sequence to be encoded.
  • the method further includes: performing bit filling on the second data sequence, wherein performing bit filling on the second data sequence comprises: dividing the second data sequence into a sub-data sequence having a number of kb bits less than or equal to z, adding padding bits to each sub-data sequence such that the number of bits of each group of sub-data sequences reaches z, and all sub-data sequences after padding constitute a sequence of data to be encoded, wherein kb Is the parameter of the base check matrix, and z is the code extension factor.
  • the method before performing bit filling on the first data sequence or bit filling the second data sequence, the method further includes: adding a L-bit cyclic redundancy check CRC sequence to the third data sequence to obtain the first data sequence or the second A sequence of data, where L is an integer greater than or equal to zero.
  • Figure 9 shows the performance comparison under the additive white noise channel.
  • the coding block size is 1120
  • the extension factor of the structured LDPC code is 150
  • the number of padding bits is 80 bits.
  • padding1 refers to the conventional padding method (that is, 80 bits are filled in the header or the tail)
  • padding2 is the method of the present scheme.
  • the pair 1120 is divided into 8 sub-data sequences, each sub-data sequence has 140 bits, and each padding 10
  • the bits get 150 bits and are combined to obtain a systematic bit sequence. According to the performance shown in Fig. 9, it can be found that a larger gain (about 0.4 dB) can be obtained by using the filling scheme of this patent.
  • bit filling comprises: dividing the first data sequence into multiple sub-data sequences, and performing respectively on the plurality of sub-data sequences Bit stuffing, all sub-data sequences after padding bits constitute the data sequence to be encoded.
  • the method further includes bit padding, wherein the bit padding comprises: dividing the first data sequence into sub-data sequences whose kb-bit number is less than or equal to z, Adding padding bits to each sub-data sequence such that the number of bits of each group of sub-data sequences reaches z, and all sub-data sequences after padding constitute data to be encoded Sequence, where kb is the parameter of the base check matrix and z is the code extension factor.
  • the bit padding further includes: adding a L-bit cyclic redundancy check CRC sequence to the second data sequence to obtain a first data sequence, where L is an integer greater than or equal to 0.
  • the above positive integer value p is a fixed positive integer
  • the LDPC decoding parallel degree p includes: a positive integer power of 2 or a positive integer power of 2 and multiplied by a prime number.
  • the advantage is that p can be a multiple of a smaller number.
  • a smaller layered decoding parallelism p can still be implemented, and thus can be supported.
  • the parameter kb of the basic check matrix is a difference between the number of columns of the basic check matrix and the number of rows of the basic check matrix, and kb is an integer greater than or equal to 4 and less than or equal to 64.
  • the parameter kb of the basic check matrix is the number of system columns of the basic check matrix.
  • the coding spreading factor includes a positive integer power equal to 2 and then a decrement of 1, or a positive integer power equal to 2 and multiplied by a prime number. More specifically, the coding spreading factor includes one of the following: 7, 15, 31, 63, 127, 255, 511, 1023, 2047, 4095.
  • FIG. 6 is a schematic diagram of a basic check matrix according to an alternative embodiment of the present invention.
  • the source data packet size to be transmitted is 7952 bits, and the coding block size is 4000.
  • Step 2 determining a coding spreading factor z according to at least one of the following parameters: a coding block size, a parameter kb of the basic parity check matrix, and a first positive integer value P;
  • Step 3 Encode the data sequence to be encoded according to the basic check matrix and the coding extension factor.
  • FIG. 7 is a schematic diagram 1 of the basic check matrix Hb' according to an alternative embodiment of the present invention. As shown in FIG. 7, the basis for obtaining the actual coding is obtained.
  • Check matrix Hb' is a schematic diagram 1 of the basic check matrix Hb' according to an alternative embodiment of the present invention. As shown in FIG. 7, the basis for obtaining the actual coding is obtained.
  • Check matrix Hb' is a schematic diagram 1 of the basic check matrix Hb' according to an alternative embodiment of the present invention. As shown in FIG. 7, the basis for obtaining the actual coding is obtained. Check matrix Hb'.
  • the coded data sequence (2 copies of the first data sequence of 4000 bits) is encoded, and 2 pieces of lengths of 8000 bits are obtained.
  • LDPC code block The LDPC coded block is modulated and transmitted.
  • the received data is demodulated to obtain 2 soft information data sequences (data sequences to be decoded) each having a length of 8000, and the basic parity check matrix Hb' and the coding spreading factor for actual coding are used above.
  • z' 500 respectively decodes two soft information data sequences each having a length of 8000, obtains a system bit sequence of structured LDPC coding, and removes a 24-bit CRC sequence, thereby obtaining a source data packet having a length of 7952 bits.
  • This example differs from Example 1 in that the source packet size to be transmitted is 3256 bits, assuming that the coded block size of the structured LDPC code is 3360.
  • a set of ascending natural numbers includes a plurality of packets, wherein a first added value of adjacent elements in the plurality of packets is equal.
  • the first added value of the i-th packet in a set of ascending natural numbers is less than the first added value of the i+1th packet, where i is a positive integer.
  • a set of ascending natural numbers is [[2:1:200], [202:2:400], [406:6:796], [804:8:1004]].
  • FIG. 8 is a schematic diagram 2 of the basic check matrix Hb' according to an alternative embodiment of the present invention. As shown in FIG. 8, the following basic check matrix Hb' can be obtained. .
  • a set of coding block sizes includes consecutive a elements, wherein the first element value of consecutive a elements is greater than z(j) ⁇ kb, and the tail element value is less than or equal to z(j+1) ⁇
  • the coding extension factor corresponding to consecutive a elements is z(j+1)
  • a is a positive integer
  • z(j) is the value of the jth element in a set of coding spreading factors
  • j is a positive integer
  • kb is the parameter of the basic check matrix.
  • the coding extension factor is z(j+1).
  • a plurality of packets are included in a set of coding spreading factors, wherein a second added value of adjacent elements in the plurality of packets is equal, and a second added value of the h-th packet in the plurality of packets is smaller than the h+
  • the second added value of 1 packet, h is a positive integer.
  • the coded data sequence (1 part of 3392 bits of the data sequence to be encoded) is encoded to obtain 1 LDPC code having a length of 6784 bits.
  • the LDPC coded block is modulated and transmitted.
  • the number of matrix columns is nb
  • the number of matrix rows is mb
  • a data processing method for a structured LDPC code is also provided in this embodiment.
  • the terms “method” or “module” and the like may implement a combination of software and/or hardware of a predetermined function.
  • the methods described in the following embodiments are preferably implemented in software, hardware, or a combination of software and hardware, is also possible and contemplated.
  • a data processing method for a structured LDPC code according to an embodiment of the present invention is used for a transmitting end, and the method includes the following steps:
  • Code block segmentation which divides a code block of length CL into a plurality of coded blocks
  • a coding spreading factor z the coding block size, a parameter kb of the basic parity check matrix, a positive integer value p, and a basic check matrix; the expansion factor z is n times a positive integer value pl. More specifically, the positive integer value pl is an element of the subset Pset, and all values of the positive integer n constitute a subset nSet. Where plmax is the maximum value in the subset Pset, and nmax is the maximum value in the subset nSet, where Kmax ⁇ kb ⁇ plmax ⁇ nmax ⁇ 1.2 ⁇ Kmax, and Kmax is an integer greater than 1024.
  • the elements in the base check matrix matrix include at least two types: 1. An element indicating a full 0 square matrix, which is represented by -1 in this patent, and may also be represented by a null value or the like; The elements of the cyclically shifted square matrix (ie, the non-all-zero square matrix), which are integers greater than or equal to 0 and less than the spreading factor, are used to indicate the number of bits of the cyclic shift of the identity matrix.
  • the basic check matrix may also include a multilateral structure, where the change in the basic check matrix includes at least: the same row index and the column index have 2 elements for indicating 2 cyclic shift specific bits The addition of the square matrix afterwards.
  • the Kmax is equal to 2000, 2048, 4000, 4096, 6000, 6144, 8000, 8192, 12000 or 12288.
  • the values of the spreading factor z are respectively ⁇ 4 6 8 10 12 14 16 20 24 28 32 40 48 56 64 80 96 112 128 160 192 224 256 320 384 448 512 640 768 896 1024 ⁇
  • the basic check matrix of the LDPC code (corresponding to a maximum expansion factor of 1024) is:
  • the spreading factor z is equal to n times of a positive integer value pl, which is an element of the subset Pset, and the positive integer n All values constitute a subset nSet, the Pset is equal to ⁇ 2 4 8 16 32 64 128 ⁇ , the nSet is equal to ⁇ 2 3 5 6 7 8 ⁇ ; in this example, Kmax is equal to 8000.
  • the spreading factor is 256, and the basic check matrix is modified according to Embodiment 5, and the spreading factor is obtained.
  • the coding basic check matrix of 256 is not described here.
  • the data sequence to be encoded having a length of 1024 bits can be encoded, and if the code rate is 1/3, the length is 3072.
  • a specific LDPC codeword for the receiving end, according to the obtained spreading factor and the coding basic check matrix, the data sequence to be decoded having a length of 3072 can be decoded, and thus the decoded data having a length of 1024 bits can be obtained.
  • the combined data of all the code blocks is combined to obtain the original data of the transport block sent by the transmitting end.
  • Embodiment 3 It can be implemented by the decoder hardware described in Embodiment 3, which is advantageous for implementing the design of the LDPC code to support flexible code length and code rate.
  • a data processing method for a structured LDPC code is also provided in this embodiment.
  • the terms “method” or “module” and the like may implement a combination of software and/or hardware of a predetermined function.
  • the methods described in the following embodiments are preferably implemented in software, hardware, or a combination of software and hardware, is also possible and contemplated.
  • a data processing method for a structured LDPC code according to an embodiment of the present invention is used for a transmitting end, and the method includes the following steps:
  • Code block segmentation which divides a code block of length CL into a plurality of coded blocks
  • a coding spreading factor z the coding block size, a parameter kb of the basic parity check matrix, a positive integer value p, and a basic check matrix; the expansion factor z is n times a positive integer value pl. More specifically, the positive integer value pl is an element of the subset Pset, and all values of the positive integer n constitute a subset nSet. Where plmax is the maximum value in the subset Pset, and nmax is the maximum value in the subset nSet, where Kmax ⁇ kb ⁇ plmax ⁇ nmax ⁇ 1.2 ⁇ Kmax, and Kmax is an integer greater than 1024.
  • the elements in the basic check matrix matrix include at least two types: 1. an element indicating a full 0 square matrix, which is represented by -1 in the patent, and may also be represented by a null value or the like;
  • the elements of the cyclically shifted square matrix ie, the non-all-zero square matrix
  • the basic check matrix may also include a multilateral structure, where the change in the basic check matrix includes at least: the same row index and the column index have 2 elements for indicating 2 cyclic shift specific bits The addition of the square matrix afterwards.
  • the Kmax is equal to 2000, 2048, 4000, 4096, 6000, 6144, 8000, 8192, 12000 or 12288.
  • the values of the spreading factor z are respectively ⁇ 4 6 8 10 12 14 16 20 24 28 32 40 48 56 64 80 96 112 128 160 192 224 256 320 384 448 512 640 768 896 1024 ⁇
  • the basic check matrix of the LDPC code (corresponding to a maximum expansion factor of 1024) is:
  • the spreading factor z is equal to n times of a positive integer value pl, which is an element of the subset Pset, and the positive integer n All values constitute a subset nSet, the Pset is equal to a positive integer i of 2, the positive integer i is equal to ⁇ 1 2 3 4 5 6 7 ⁇ , ie Pset is equal to ⁇ 2 4 8 16 32 64 128 ⁇ , The nSet is equal to ⁇ 2 3 5 6 7 8 ⁇ , so that the set of the above-mentioned spreading factors can be obtained, and it can be found that there are more positive integer factors, which can make the decoder more friendly, that is, More decoding parallelism is used to achieve throughput requirements in different scenarios.
  • the decoding parallelism is generally a positive integer factor of the spreading factor, and if the decoding parallelism is not equal to the positive integer factor of the spreading factor, then the hardware implementation is very complicated; in this example , Kmax is equal to 8000.
  • the basic matrix described above has characteristics: in the transmission process, when the encoding code rate R is higher than the mother code R0, the q*Z bits of the q column in the system column corresponding to the basic matrix are not transmitted, and the correspondence is not transmitted.
  • the q-column of the base matrix constitutes a sub-matrix of the mb row *q column, and the difference of the column weights between any two columns in the sub-matrix is not more than 1, and the column weight refers to: indication in the corresponding column
  • the number of elements of the cyclic shift square matrix of the unit array; or the difference between the number of elements used to indicate the all-zero square matrix in any two columns of the sub-matrix is not greater than 1, and is used to indicate all zeros.
  • the elements of the square matrix are denoted by "-1" in the present embodiment, and the elements for indicating the cyclic shift square matrix of the unit array are represented by an integer of 0 to Z-1 in this embodiment. In the present embodiment, q
  • the spreading factor is 256, and the basic check matrix is modified according to Embodiment 5, and the spreading factor is obtained. 256
  • the code base check matrix is not described here.
  • the data sequence to be encoded having a length of 1024 bits can be encoded, and if the code rate is 1/3, an LDPC codeword having a length of 3072 bits is obtained; for the receiving end, The data sequence to be decoded having a length of 3072 can be decoded according to the obtained spreading factor and the coding basic check matrix, thereby obtaining decoded data having a length of 1024 bits, and combining the decoded data of all the code blocks. , the original data of the transport block sent by the sender can be obtained.
  • Embodiment 3 It can be implemented by the decoder hardware described in Embodiment 3, which is advantageous for implementing the design of the LDPC code to support flexible code length and code rate.
  • the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, by hardware, but in many cases, the former is A better implementation.
  • the technical solution of the present invention which is essential or contributes to the prior art, may be embodied in the form of a software product stored in a storage medium (such as ROM/RAM, disk,
  • the optical disc includes a number of instructions for causing a terminal device (which may be a cell phone, a computer, a server, or a network device, etc.) to perform the methods of various embodiments of the present invention.
  • Embodiments of the present invention also provide a storage medium.
  • the foregoing storage medium may be configured to store program code for performing the following steps:
  • a coding extension factor z a coding block size, a parameter kb of a basic parity check matrix, a positive integer value p, a mb row, and a basic parity check matrix of the nb column;
  • the foregoing storage medium may include, but not limited to, a USB flash drive, a Read-Only Memory (ROM), a Random Access Memory (RAM), a mobile hard disk, and a magnetic memory.
  • ROM Read-Only Memory
  • RAM Random Access Memory
  • a mobile hard disk e.g., a hard disk
  • magnetic memory e.g., a hard disk
  • the processor executes the method steps described in the foregoing embodiments according to the stored program code in the storage medium.
  • modules or steps of the present invention described above can be implemented by a general-purpose computing device, which can be centralized on a single computing device or distributed over a network of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device such that they may be stored in the storage device by the computing device and, in some cases, may be different than The steps shown or described are performed sequentially, or they are separately fabricated into individual integrated circuit modules, or a plurality of modules or steps thereof are fabricated into a single integrated circuit module. Thus, the invention is not limited to any specific combination of hardware and software.
  • the invention is applicable to the field of communication, and is used to realize the flexibility of processing data processing of the LDPC compiled code, thereby solving the problem of low data processing flexibility of the LDPC compiled code in the related art.

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Abstract

一种结构化LDPC码的数据处理方法及装置,其中该方法包括:获取结构化LDPC编码的编码块大小(S202);至少根据以下参数之一确定编码扩展因子z:编码块大小、基础校验矩阵的参数kb、正整数值p、mb行和nb列的基础校验矩阵(S204);根据基础校验矩阵和编码扩展因子对待编码数据序列进行编码或者对待译码数据序列进行译码(S206),解决了LDPC编译码的数据处理灵活度低的问题,提高了LDPC编译码数据处理的灵活度。

Description

结构化LDPC码的数据处理方法及装置 技术领域
本发明涉及通信领域,具体而言,涉及一种结构化LDPC码的数据处理方法及装置。
背景技术
数字通信***中,一般包括三个部分:发送端、信道和接收端。发送端可对信息序列进行信道编码从而获取编码码字,对编码码字进行交织,并将交织后的比特映射成调制符号,然后可以根据通信信道信息来处理和发送调制符号。在信道中,由于多径、移动等因素导致特定的信道响应,这些都会使数据传输失真,同时由于噪声和干扰也会进一步恶化数据传输。接收端接收通过信道后的调制符号数据,此时的调制符号数据已经失真,需要进行特定处理才能恢复原始信息序列。
根据发送端对信息序列的编码方法,接收端可以对接收数据进行相应处理从而可靠地恢复原始信息序列。所述的编码方法必须是收发两端都是可见的。一般地,所述编码处理方法是基于前向纠错(Forward Error Correction,简称为FEC)编码,其中,前向纠错编码在信息序列中添加一些冗余信息。接收端可以利用该冗余信息来可靠地恢复原始信息序列。
一些常见的FEC编码包括:卷积码、Turbo码和低密度奇偶校验(Low Density Parity Check,简称为LDPC)码。FEC编码过程中,对比特数目为k的信息序列进行FEC编码获得n比特的FEC编码码字(冗余比特为n-k),FEC编码码率为k/n。卷积编码可容易地对任意大小的分组进行编码,以及在Turbo编码中,通过利用对信息序列进行操作处理的两个编码分量以及可支持不同大小的编码交织方法,可支持不同的信息序列大小。
LDPC码是一种可以用非常稀疏的奇偶校验矩阵或者二分图定义的线性分组码,正是利用它的校验矩阵的稀疏性,才能实现低复杂度的编译码,从而使得LDPC走向实用化。经过各种实践和理论证明,LDPC码是在加性高斯白噪声(Additive White Gaussian Noise,简称为AWGN)信道下性能最为优良的信道编码,性能非常靠近香农极限,优于卷积码和Turbo编码。
特别是,结构化LDPC码由于具有结构化特征,逐渐成为主流应用,如在IEEE802.11ac、IEEE802.11ad、IEEE802.11aj、IEEE802.16e、IEEE802.11n、DVB、微波通信以及光纤通信等中获得大量应用。这种结构化LDPC码的奇偶校验矩阵H为mb×z行和nb×z列的矩阵,它是由mb×nb个分块矩阵构成,每个分块矩阵都是z×z的基本置换矩阵的不同幂次,它们都是单位阵的循环移位矩阵。具有如下的形式:
Figure PCTCN2016104744-appb-000001
如果
Figure PCTCN2016104744-appb-000002
Figure PCTCN2016104744-appb-000003
即z×z的全0矩阵;如果
Figure PCTCN2016104744-appb-000004
是大于或者等于0的整数,定义
Figure PCTCN2016104744-appb-000005
在这里P是一个z×z的标准置换矩阵,如下所示:
Figure PCTCN2016104744-appb-000006
通过这样的幂次
Figure PCTCN2016104744-appb-000007
就可以唯一标识每一个分块矩阵,如果某一分块矩阵为全0矩阵,矩阵一般用-1来表示,如果是单位阵的循环移位s获得,则
Figure PCTCN2016104744-appb-000008
等于s,所以所有
Figure PCTCN2016104744-appb-000009
可以构成一个基础校验矩阵Hb。而z是指示所述标准置换矩阵的维数,在此我们将z称之为扩展因子。此时,结构化LDPC码完全可以由基础校验矩阵Hb和扩展因子z唯一确定。基础校验矩阵包括多个参数:mb、nb和kb,其中,mb是基础校验矩阵行数(可以说是基础校验矩阵的校验列数),nb基础校验矩阵列数,而kb=nb-mb是基础校验矩阵的***列数。
例如,基础校验矩阵Hb(2行4列)如下而且扩展因子z等于4:
Figure PCTCN2016104744-appb-000010
则奇偶校验矩阵为:
Figure PCTCN2016104744-appb-000011
LDPC码在译码时,可以采用分层译码,即采用部分并行译码方法。如上所述的奇偶校验矩阵有8行,说明有8个奇偶校验码,在译码时,需要每个奇偶校验矩阵分别译码,如果所有8个奇偶校验码都更新数据完则为一个迭代。而在每次迭代过程中,如果采用部分并行(即分层译码),如并行度为p,即有p个奇偶校验码同时更新,则迭代中当前和 下一个p个奇偶校验码运行都是采用同一个更新模块,则译码器的复杂度要低很多,而且分层译码中下一层的数据更新可以采用当前已经更新好的数据,所以需要的迭代次数更低,译码吞吐量要高一些。如以上所示的H,如果并行度为2,则奇偶校验矩阵的每4行(基础校验矩阵的一行)有2个并行度的奇偶校验码同时更新。
一般来说,奇偶校验矩阵都是比较大的,存储处理等都不方便,采用基础校验矩阵存储就简单很多。
根据数学基本知识,质数(prime number)又称素数,有无限个。质数定义为在大于1的自然数中,除了1和它本身以外不再有其他因数的数称为质数或者素数,所以一般来说,素数是大于1的整数,例如2、3、5、7、11、13、17、19等等。
在几乎所有的FEC编码方法中,编码器复杂度较低,而基本复杂度在于接收端的译码器,LDPC编码由于本身具有并行特性进而可以采用并行译码,所以具有更高译码速度和吞吐量。但是,由于LDPC码的基础校验矩阵一般只是适应一部分长度,可能不易于实现各种灵活长度的编码块,以及对于适应不同长度的编码块时复杂度会比较高。
针对相关技术中LDPC编译码的数据序列的处理灵活度低的问题,目前还没有有效的解决方案。
发明内容
本发明实施例提供了一种结构化LDPC码的数据处理方法及装置,以至少解决相关技术中LDPC编译码的数据序列的处理灵活度低的问题。
根据本发明的一个实施例,提供了一种结构化LDPC码的数据处理方法,包括:获取结构化LDPC编码的编码块大小;至少根据以下参数之一确定编码扩展因子z:所述编码块大小、基础校验矩阵的参数kb、正整数值p、mb行和nb列的基础校验矩阵;根据所述基础校验矩阵和所述编码扩展因子对待编码数据序列进行编码或者对待译码数据序列进行译码;其中,kb=nb-mb,kb、p、mb、z和nb均是大于1的整数。
可选地,至少根据所述编码块大小CBS、所述基础校验矩阵的参数kb和所述正整数值p确定所述编码扩展因子包括:通过公式确定所述编码扩展因子,其中,
Figure PCTCN2016104744-appb-000013
表示向上取整。
可选地,获取所述结构化LDPC编码的所述编码块大小包括:所述编码块大小等于基础校验矩阵的参数kb与一组升序自然数中的一个元素相乘所获得的数值。
可选地,所述一组升序自然数中包括多个分组,其中,所述多个分组中的分组内相邻元素的第一增加值相等。
可选地,所述一组升序自然数中的第i个分组的所述第一增加值小于第i+1个分组的 所述第一增加值,其中,所述i为正整数。
可选地,根据所述编码块大小确定所述编码扩展因子包括:所述编码块大小为一组编码块大小中的一个元素值,所述一组编码块大小为升序的第一自然数组;所述编码扩展因子为一组编码扩展因子中的一个元素值,所述一组编码扩展因子为升序的第二自然数组。
可选地,所述一组编码块大小中包括连续的a个元素,其中,在所述连续的a个元素的首元素值大于z(j)×kb,且尾元素值小于或者等于z(j+1)×kb的情况下,所述连续的a个元素对应的编码扩展因子为z(j+1),所述a为正整数,所述z(j)为所述一组编码扩展因子中的第j个元素值,所述j为正整数,所述kb是基础校验矩阵的参数。
可选地,在获取的所述编码块大小为所述连续的a个元素中的一个元素的情况下,所述编码扩展因子为z(j+1)。
可选地,在所述编码块大小与所述基础校验矩阵的参数kb的比值大于z(j)且小于或者等于z(j+1)的情况下,所述编码扩展因子被确定为z(j+1),其中,所述z(j)为所述一组编码扩展因子中的第j个元素值。
可选地,所述一组编码扩展因子中包括多个分组,其中,所述多个分组的分组内相邻元素的第二增加值相等,所述多个分组中的第h个分组的所述第二增加值小于第h+1个分组的所述第二增加值,所述h为正整数。
可选地,所述一组编码扩展因子中的所有大于所述正整数值p的元素值都是所述正整数值p的正整数n倍。
可选地,所述一组编码块大小至少包括:所述基础校验矩阵的参数kb与所述一组编码扩展因子相乘得到的乘积值,以及全部所述乘积值之间间隔为B的整数值,其中,所述B为正整数。
可选地,根据所述基础校验矩阵和所述编码扩展因子对待编码数据序列进行编码之前,所述方法还包括:对第一数据序列进行比特填充,其中,对所述第一数据序列进行比特填充包括:将所述第一数据序列分成多个子数据序列,对所述多个子数据序列分别进行比特填充,所有填充比特后的子数据序列构成所述待编码数据序列。
可选地,根据基础校验矩阵和所述编码扩展因子对待编码数据序列进行编码之前,所述方法还包括:对第二数据序列进行比特填充,其中,对所述第二数据序列进行比特填充包括:将所述第二数据序列分成所述kb个比特数目小于或者等于z的子数据序列,对每个子数据序列添加填充比特使得每组子数据序列的比特数目达到z,所有填充比特后的子数据序列构成所述待编码数据序列,其中,kb是础校验矩阵的参数,z是所述编码扩展因子。
可选地,在对所述第一数据序列进行比特填充或者对所述第二数据序列进行比特填充 之前,所述方法还包括:对第三数据序列添加L比特的循环冗余校验CRC序列获得所述第一数据序列或者所述第二数据序列,其中,所述L是大于或者等于0的整数。
可选地,所述基础校验矩阵的参数kb为所述基础校验矩阵的列数和所述基础校验矩阵的行数的差值,kb是大于等于4且小于等于64的一个整数。
可选地,所述正整数值p是LDPC译码并行度。
可选地,所述正整数值p是一个固定正整数,所述LDPC译码并行度p包括:所述正整数值p为2的正整数次幂或者所述正整数值p为2的正整数次幂再乘以一个素数。
可选地,所述正整数值p是子集合P的一个元素,其中,所述子集合P是Pmax的所有正整数因子所构成集合中的一个子集,Pmax是大于3且小于或者等于1024的一个整数。
可选地,所述正整数n的所有取值构成子集合nSet,其中,所述nSet是正整数集合Ns中长度为F的一个子集,所述正整数集合Ns={1、2、3、…、M},M是大于1的整数。
可选地,所述子集合nSet包括以下之一:所述正整数集合Ns中的前F个元素构成的子集合、所述正整数集合Ns中的后F个元素构成的子集合、所述正整数集合Ns中的F个素数构成的子集合、所述正整数集合Ns中的F个奇数构成的子集合、所述正整数集合Ns中的F个偶数构成的子集合,F是小于M的正整数。
可选地,所述编码扩展因子包括:所述编码扩展因子等于2的正整数次幂然后减1,或者所述编码扩展因子等于2的正整数次幂再乘以一个素数,所述的素数包括以下之一:3、5、7、11、13、17、19、23、29。
可选地,所述编码扩展因子等于2的正整数次幂再乘以一个素数,该素数包括3和5。
可选地,所述编码扩展因子等于2的正整数次幂再乘以一个素数,该素数包括5和7。
可选地,所述编码扩展因子等于2的正整数次幂再乘以一个素数,该素数包括3、5和7。
可选地,所述编码扩展因子包括以下之一:7、15、31、63、127、255、511、1023、2047、4095。
可选地,在至少根据以下参数之一确定所述编码扩展因子z:所述编码块大小、所述基础校验矩阵的参数kb、所述正整数值p、所述基础校验矩阵之后,所述方法还包括:至少存储所述基础校验矩阵。
可选地,在对所述待编码数据序列进行编码之前,还包括:在待编码数据序列中填充长度为k’比特的哑元比特获得长度为kb*z比特的待编码数据序列,其中,所述k’与kb*z的比值小于或等于1/4,k’是大于或者等于0的整数,所述kb是所述基础校验矩阵的***列数,所述z是编码使用的扩展因子大小,kb是大于1的整数,z是大于0的整数。
可选地,所述扩展因子z均为一个正整数值pl的n倍。
可选地,所述正整数值pl是子集合Pset的一个元素,其中,所述子集合Pset是Pmax的所有正整数因子所构成集合中的一个子集,n是一个自然数,Pmax是大于等于4的整数。
可选地,所述正整数n的所有取值构成子集合nSet,其中,所述nSet是正整数集合Ns中长度为F的一个子集,所述正整数集合Ns={1、2、3、…、M},M是大于1的整数。
可选地,所述正整数值pl是子集合Pset的一个元素,所述正整数n的所有取值构成子集合nSet,plmax是子集合Pset中的最大值,nmax是子集合nSet中的最大值,其中,Kmax≤kb×plmax×nmax≤1.2×Kmax,Kmax是大于1024的整数。
可选地,所述的Kmax等于2000、2048、4000、4096、6000、6144、8000、8192、12000或者12288。
可选地,所述基础校验矩阵中指示非全0方阵的任何hbij元素的满足如下条件:mod(hbij,(Pmax/pl))=0,其中,i=0,1,2..,mb-1,j=0,1,…,nb-1,Pmax是大于等于4的整数。
可选地,所述基础校验矩阵中指示非全0方阵的任何hbij元素的满足如下条件:mod(hbij,(Pmax/pl))=A,其中i和j分别是所述基础校验矩阵中行索引i和列索引j的元素以及所述hbij指示非全0方阵,A是小于pl且大于或者等于0的固定整数,Pmax是大于等于4的整数。
可选地,基础校验矩阵的参数kb为基础校验矩阵***列数。
根据本发明的另一个实施例,提供了一种结构化LDPC码的数据处理装置,包括:获取模块,用于获取结构化LDPC编码的编码块大小;确定模块,用于至少根据以下参数之一确定编码扩展因子z:所述编码块大小、基础校验矩阵的参数kb、正整数值p、mb行和nb列的基础校验矩阵;处理模块,用于根据所述基础校验矩阵和所述编码扩展因子对待编码数据序列进行编码或者对待译码数据序列进行译码;其中,kb=nb-mb,kb、p、mb、z和nb均是大于1的整数。
可选地,所述确定模块用于:通过公式
Figure PCTCN2016104744-appb-000014
确定所述编码扩展因子,其中,所述CBS为所述编码块大小,
Figure PCTCN2016104744-appb-000015
表示向上取整。
可选地,所述获取模块用于:所述编码块大小等于基础校验矩阵的参数kb与一组升序自然数中的一个元素相乘所获得的数值。
可选地,所述一组升序自然数中包括多个分组,其中,所述多个分组中的分组内相邻元素的第一增加值相等。
可选地,所述一组升序自然数中的第i个分组的所述第一增加值小于第i+1个分组的所述第一增加值,其中,所述i为正整数。
可选地,所述确定模块用于:所述编码块大小为一组编码块大小中的一个元素值,所述一组编码块大小为升序的第一自然数组;所述编码扩展因子为一组编码扩展因子中的一 个元素值,所述一组编码扩展因子为升序的第二自然数组。
可选地,所述一组编码块大小中包括连续的a个元素,其中,在所述连续的a个元素的首元素值大于z(j)×kb,且尾元素值小于或者等于z(j+1)×kb的情况下,所述连续的a个元素对应的编码扩展因子为z(j+1),所述a为正整数,所述z(j)为所述一组编码扩展因子中的第j个元素值,所述j为正整数,所述kb是基础校验矩阵的参数。
可选地,在获取的所述编码块大小为所述连续的a个元素中的一个元素的情况下,所述编码扩展因子为z(j+1)。
可选地,在所述编码块大小与所述基础校验矩阵的参数kb的比值大于z(j)且小于或者等于z(j+1)的情况下,所述编码扩展因子被确定为z(j+1),其中,所述z(j)为所述一组编码扩展因子中的第j个元素值。
可选地,所述一组编码扩展因子中包括多个分组,其中,所述多个分组的分组内相邻元素的第二增加值相等,所述多个分组中的第h个分组的所述第二增加值小于第h+1个分组的所述第二增加值,所述h为正整数。
可选地,所述一组编码扩展因子中的所有大于所述正整数值p的元素值都是所述正整数值p的正整数n倍。
可选地,所述一组编码块大小至少包括:所述基础校验矩阵的参数kb与所述一组编码扩展因子相乘得到的乘积值,以及全部所述乘积值之间间隔为B的整数值,其中,所述B为正整数。
可选地,所述装置还包括:第一比特填充模块,用于对第一数据序列进行比特填充,其中,对所述第一数据序列进行比特填充包括:将所述第一数据序列分成多个子数据序列,对所述多个子数据序列分别进行比特填充,所有填充比特后的子数据序列构成所述待编码数据序列。
可选地,所述装置还包括:第二比特填充模块,用于对第二数据序列进行比特填充,其中,对所述第二数据序列进行比特填充包括:将所述第二数据序列分成所述kb个比特数目小于或者等于z的子数据序列,对每个子数据序列添加填充比特使得每组子数据序列的比特数目达到z,所有填充比特后的子数据序列构成所述待编码数据序列,其中,kb是础校验矩阵的参数,z是所述编码扩展因子。
可选地,所述装置还包括:添加模块,用于对第三数据序列添加L比特的循环冗余校验CRC序列获得所述第一数据序列或者所述第二数据序列,其中,所述L是大于或者等于0的整数。
可选地,所述基础校验矩阵的参数kb为所述编码基础校验矩阵的列数和所述编码基础校验矩阵的行数的差值,kb是大于等于4且小于等于64的一个整数。
可选地,所述正整数值p是LDPC译码并行度。
可选地,所述正整数值p是一个固定正整数,所述LDPC译码并行度p包括:所述正整数值p为2的正整数次幂或者所述正整数值p为2的正整数次幂再乘以一个素数。
可选地,所述正整数值p是子集合P的一个元素,其中,所述子集合P是Pmax的所有正整数因子所构成集合中的一个子集,Pmax是大于3且小于或者等于1024的一个整数。
可选地,所述正整数n的所有取值构成子集合nSet,其中,所述nSet是正整数集合Ns中长度为F的一个子集,所述正整数集合Ns={1、2、3、…、M},M是大于1的整数。
可选地,所述子集合nSet包括以下之一:所述正整数集合Ns中的前F个元素构成的子集合、所述正整数集合Ns中的后F个元素构成的子集合、所述正整数集合Ns中的F个素数构成的子集合、所述正整数集合Ns中的F个奇数构成的子集合、所述正整数集合Ns中的F个偶数构成的子集合,F是小于M的正整数。
可选地,所述编码扩展因子包括:所述编码扩展因子等于2的正整数次幂然后减1,或者所述编码扩展因子等于2的正整数次幂再乘以一个素数,所述的素数包括以下之一:3、5、7、11、13、17、19、23、29。
可选地,所述编码扩展因子等于2的正整数次幂再乘以一个素数,该素数包括3和5。
可选地,所述编码扩展因子等于2的正整数次幂再乘以一个素数,该素数包括5和7。
可选地,所述编码扩展因子等于2的正整数次幂再乘以一个素数,该素数包括3、5和7。
可选地,所述编码扩展因子包括以下之一:7、15、31、63、127、255、511、1023、2047、4095。
可选地,所述装置还包括:存储模块,用于至少存储所述基础校验矩阵。
可选地,所述装置还用于:在对所述待编码数据序列进行编码之前,在待编码数据序列中填充长度为k’比特的哑元比特获得长度为kb*z比特的待编码数据序列,其中,k’与kb*z的比值小于或等于1/4,k’是大于等于0的整数,所述kb是所述基础校验矩阵的***列数,所述z是编码使用的扩展因子大小,kb是大于1的整数,z是大于0的整数。
可选地,所述扩展因子z均为一个正整数值pl的n倍。
可选地,所述正整数值pl是子集合Pset的一个元素,其中,所述子集合Pset是Pmax的所有正整数因子所构成集合中的一个子集,n是一个自然数,Pmax是大于等于4的整数。
可选地,所述正整数n的所有取值构成子集合nSet,其中,所述nSet是正整数集合Ns中长度为F的一个子集,所述正整数集合Ns={1、2、3、…、M},M是大于1的整数。
可选地,所述正整数值pl是子集合Pset的一个元素,所述正整数n的所有取值构成子集合nSet,plmax是子集合Pset中的最大值,nmax是子集合nSet中的最大值,其中, Kmax≤kb×plmax×nmax≤1.2×Kmax,Kmax是大于1024的整数。
可选地,所述的Kmax等于2000、2048、4000、4096、6000、6144、8000、8192、12000或者12288。
可选地,所述基础校验矩阵中指示非全0方阵的任何hbij元素的满足如下条件:mod(hbij,(Pmax/pl))=0,其中,i=0,1,2..,mb-1,j=0,1,…,nb-1,Pmax是大于等于4的整数。
可选地,所述基础校验矩阵中指示非全0方阵的任何hbij元素的满足如下条件:mod(hbij,(Pmax/pl))=A,其中i和j分别是所述基础校验矩阵中行索引i和列索引j的元素以及所述hbij指示非全0方阵,A是小于pl且大于或者等于0的固定整数,Pmax是大于等于4的整数。
可选地,基础校验矩阵的参数kb为基础校验矩阵***列数。
通过本发明,获取结构化LDPC编码的编码块大小;至少根据以下参数之一确定编码扩展因子z:编码块大小、基础校验矩阵的参数kb、正整数值p、mb行和nb列的基础校验矩阵;根据基础校验矩阵和编码扩展因子对待编码数据序列进行编码或者对待译码数据序列进行译码;其中,kb=nb-mb,kb、p、mb、z和nb均是大于1的整数,由此可见,采用上述方案根据LDPC编码的编码块大小、基础校验矩阵的参数kb、正整数值p、mb行和nb列的基础校验矩阵中的至少之一确定编码扩展因子,并根据基础校验矩阵和编码扩展因子进行LDPC编译码,因此,提高了LDPC编译码数据处理的灵活度,从而解决了相关技术中LDPC编译码的数据处理灵活度低的问题。
附图说明
此处所说明的附图用来提供对本发明的进一步理解,构成本申请的一部分,本发明的示意性实施例及其说明用于解释本发明,并不构成对本发明的不当限定。在附图中:
图1是本发明实施例的一种结构化LDPC码的数据处理方法的移动终端的硬件结构框图;
图2是根据本发明实施例的一种结构化LDPC码的数据处理方法的流程图;
图3是根据本发明实施例的一种结构化LDPC码的数据处理装置的结构框图一;
图4是根据本发明实施例的一种结构化LDPC码的数据处理装置的结构框图二;
图5是根据本发明实施例的一种结构化LDPC码的数据处理装置的结构框图三;
图6是根据本发明可选实施例的基础校验矩阵的示意图;
图7是根据本发明可选实施例的基础校验矩阵Hb’的示意图一;
图8是根据本发明可选实施例的基础校验矩阵Hb’的示意图二;
图9是根据本发明可选实施例的加性白噪声信道下的不同填充方法的性能对比的示意图。
图10是根据本发明可选实施例的LDPC码译码器的存储示意图。
具体实施方式
下文中将参考附图并结合实施例来详细说明本发明。需要说明的是,在不冲突的情况下,本申请中的实施例及实施例中的特征可以相互组合。
需要说明的是,本发明的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象,而不必用于描述特定的顺序或先后次序。
实施例1
本申请实施例1所提供的方法实施例可以在移动终端、计算机终端或者类似的运算装置中执行。以运行在移动终端上为例,图1是本发明实施例的一种结构化LDPC码的数据处理方法的移动终端的硬件结构框图,如图1所示,移动终端10可以包括一个或多个(图中仅示出一个)处理器102(处理器102可以包括但不限于微处理器MCU或可编程逻辑器件FPGA等的处理装置)、用于存储数据的存储器104、以及用于通信功能的传输装置106。本领域普通技术人员可以理解,图1所示的结构仅为示意,其并不对上述电子装置的结构造成限定。例如,移动终端10还可包括比图1中所示更多或者更少的组件,或者具有与图1所示不同的配置。
存储器104可用于存储应用软件的软件程序以及模块,如本发明实施例中的载波相位恢复方法方法对应的程序指令/模块,处理器102通过运行存储在存储器104内的软件程序以及模块,从而执行各种功能应用以及数据处理,即实现上述的方法。存储器104可包括高速随机存储器,还可包括非易失性存储器,如一个或者多个磁性存储装置、闪存、或者其他非易失性固态存储器。在一些实例中,存储器104可进一步包括相对于处理器102远程设置的存储器,这些远程存储器可以通过网络连接至移动终端10。上述网络的实例包括但不限于互联网、企业内部网、局域网、移动通信网及其组合。
传输装置106用于经由一个网络接收或者发送数据。上述的网络具体实例可包括移动终端10的通信供应商提供的无线网络。在一个实例中,传输装置106包括一个网络适配器(Network Interface Controller,NIC),其可通过基站与其他网络设备相连从而可与互联网进行通讯。在一个实例中,传输装置106可以为射频(Radio Frequency,RF)模块,其用于通过无线方式与互联网进行通讯。
在本实施例中提供了一种结构化LDPC码的数据处理方法,图2是根据本发明实施例的一种结构化LDPC码的数据处理方法的流程图,如图2所示,该流程包括如下步骤:
步骤S202,获取结构化LDPC编码的编码块大小;
步骤S204,至少根据以下参数之一确定编码扩展因子z:编码块大小、基础校验矩阵的参数kb、正整数值p、mb行和nb列的基础校验矩阵;
步骤S206,根据基础校验矩阵和编码扩展因子对待编码数据序列进行编码或者对待译码数据序列进行译码;
其中,kb=nb-mb,kb、p、mb、z和nb均是大于1的整数。
可选地,上述结构化LDPC码的数据处理方法可以但不限于应用于处理数据序列的场景中。例如:LDPC编码译码处理数据序列的场景。
可选地,上述结构化LDPC码的数据处理方法可以但不限于应用于LDPC编码器或者LDPC译码器,例如:利用LDPC编码的发送端、利用LDPC解码的接收端。
通过上述步骤,获取结构化LDPC编码的编码块大小;至少根据以下参数之一确定编码扩展因子z:编码块大小、基础校验矩阵的参数kb、正整数值p;根据基础校验矩阵和编码扩展因子对待编码数据序列进行编码或者对待译码数据序列进行译码,由此可见,采用上述方案根据LDPC编码的编码块大小、基础校验矩阵的参数kb、正整数值p中的至少之一确定编码扩展因子,并根据基础校验矩阵和编码扩展因子进行LDPC编译码,因此,提高了LDPC编译码数据处理的灵活度,从而解决了相关技术中LDPC编译码的数据处理灵活度低的问题。进一步,支持对不同长度的编码块大小进行有效的LDPC编码和译码,进而降低了LDPC编译码的复杂度。
可选地,可以但不限于通过公式
Figure PCTCN2016104744-appb-000016
确定编码扩展因子,其中,CBS为编码块大小,
Figure PCTCN2016104744-appb-000017
表示向上取整。
可选地,在上述步骤S202中,编码块大小等于基础校验矩阵的参数kb与一组升序自然数中的一个元素相乘所获得的数值。
可选地,一组升序自然数中可以但不限于包括多个分组,其中,多个分组中的分组内相邻元素的第一增加值相等。
可选地,一组升序自然数中的第i个分组的第一增加值小于第i+1个分组的第一增加值,其中,i为正整数。
可选地,在上述步骤S206中,如果根据编码块大小确定编码扩展因子可以但不限于为:编码块大小为一组编码块大小中的一个元素值,一组编码块大小为升序的第一自然数组;编码扩展因子为一组编码扩展因子中的一个元素值,一组编码扩展因子为升序的第二自然数组。
可选地,一组编码块大小中包括连续的a个元素,其中,在连续的a个元素的首元素值大于z(j)×kb,且尾元素值小于或者等于z(j+1)×kb的情况下,连续的a个元素对应的编码扩展因子为z(j+1),a为正整数,z(j)为一组编码扩展因子中的第j个元素值,j为正整数,kb是基础校验矩阵的参数。
可选地,在获取的编码块大小为连续的a个元素中的一个元素的情况下,编码扩展因 子可以但不限于为z(j+1)。
可选地,在编码块大小与基础校验矩阵的参数kb的比值大于z(j)且小于或者等于z(j+1)的情况下,编码扩展因子被确定为z(j+1),其中,z(j)为一组编码扩展因子中的第j个元素值。
可选地,一组编码扩展因子中可以但不限于包括多个分组,其中,多个分组的分组内相邻元素的第二增加值相等,多个分组中的第h个分组的第二增加值小于第h+1个分组的第二增加值,h为正整数。
可选地,一组编码扩展因子中的所有大于正整数值p的元素值都是正整数值p的正整数n倍。
可选地,一组编码块大小可以但不限于至少包括:基础校验矩阵的参数kb与一组编码扩展因子相乘得到的乘积值,以及全部乘积值之间间隔为B的整数值,其中,B为正整数。
可选地,在上述步骤S206之前,可以但不限于对第一数据序列进行比特填充,其中,对第一数据序列进行比特填充包括:将第一数据序列分成多个子数据序列,对多个子数据序列分别进行比特填充,所有填充比特后的子数据序列构成待编码数据序列。
可选地,在上述步骤S206之前,可以但不限于对第二数据序列进行比特填充,其中,对第二数据序列进行比特填充包括:将第二数据序列分成kb个比特数目小于或者等于z的子数据序列,对每个子数据序列添加填充比特使得每组子数据序列的比特数目达到z,所有填充比特后的子数据序列构成待编码数据序列,其中,kb是础校验矩阵的参数,z是编码扩展因子。
可选地,在对第一数据序列进行比特填充或者对第二数据序列进行比特填充之前,可以但不限于对第三数据序列添加L比特的循环冗余校验CRC序列获得第一数据序列或者第二数据序列,其中,L是大于或者等于0的整数。
可选地,基础校验矩阵的参数kb为基础校验矩阵的列数和基础校验矩阵的行数的差值,kb是大于等于4且小于等于64的一个整数。
可选地,正整数值p是LDPC译码并行度。
可选地,正整数值p是一个固定正整数,LDPC译码并行度p包括:正整数值p为2的正整数次幂或者正整数值p为2的正整数次幂再乘以一个素数。
可选地,正整数值p是子集合P的一个元素,其中,该子集合P是Pmax的所有正整数因子所构成集合中的一个子集,Pmax是大于3且小于或者等于1024的一个整数。
可选地,正整数n的所有取值构成子集合nSet,其中,nSet是正整数集合Ns中长度为F的一个子集,正整数集合Ns={1、2、3、…、M},M是大于1的整数。
可选地,子集合nSet包括以下之一:正整数集合Ns中的前F个元素构成的子集合、正整数集合Ns中的后F个元素构成的子集合、正整数集合Ns中的F个素数构成的子集合、正整数集合Ns中的F个奇数构成的子集合、正整数集合Ns中的F个偶数构成的子集合,F是小于M的正整数。
可选地,编码扩展因子可以但不限于包括:编码扩展因子等于2的正整数次幂然后减1,或者编码扩展因子等于2的正整数次幂再乘以一个素数,该素数包括以下之一:3、5、7、11、13、17、19、23、29。可选地,编码扩展因子等于2的正整数次幂再乘以一个素数,该素数包括3和5。或者可选地,编码扩展因子等于2的正整数次幂再乘以一个素数,该素数包括5和7。以及可选地,编码扩展因子等于2的正整数次幂再乘以一个素数,该素数包括3、5和7。
可选地,编码扩展因子包括以下之一:7、15、31、63、127、255、511、1023、2047、4095。
可选地,在上述步骤S204之后,还可以存储基础校验矩阵。
可选地,对待编码数据序列进行编码之前,还可以在待编码数据序列中填充长度为k’比特的哑元比特获得长度为kb*z比特的待编码数据序列,其中k’与kb*z的比值小于或等于1/4,其中k’是大于等于0的整数,kb是基础校验矩阵的***列数,z是编码使用的扩展因子大小,kb是大于1的整数,z是大于0的整数。在进行LDPC编码时,由于LDPC码的基础校验矩阵存在一定度分布特性,如果填充比特过多会使得LDPC码的度分布特性收到破坏,会影响LDPC码的译码性能,将填充长度限制与1/4之内的有益效果在于:保证LDPC码基础校验矩阵的基本特性改变不大,保证LDPC码的译码性能改变不大。这里的填充比特的数目和位置相对于发端和收端来说都是已知的,在数据传输过程中是不包括填充比特,在LDPC码译码过程中,由于这些比特是已知的,所以其不会影响译码结果,如果对应基础校验矩阵中某一列的所有比特都是填充比特,那么意味着基础校验矩阵的对应该列删除,所以此时基础校验矩阵的度分布受到改变。
可选地,扩展因子z均为一个正整数值pl的n倍。
可选地,正整数值pl是子集合Pset的一个元素,其中,子集合Pset是Pmax的所有正整数因子所构成集合中的一个子集,n是一个自然数,Pmax是大于等于4的整数。
可选地,正整数n的所有取值构成子集合nSet,其中,nSet是正整数集合Ns中长度为F的一个子集,正整数集合Ns={1、2、3、…、M},M是大于1的整数。
可选地,基础校验矩阵中指示非全0方阵的任何hbij元素的满足如下条件:mod(hbij,(Pmax/pl))=0,其中,i=0,1,2..,mb-1,j=0,1,…,nb-1,Pmax是大于等于4的整数。
可选地,基础校验矩阵中指示非全0方阵的任何hbij元素的满足如下条件:mod(hbij,(Pmax/pl))=A,其中i和j分别是基础校验矩阵中行索引i和列索引j的元素以及hbij指示 非全0方阵,A是小于pl且大于或者等于0的固定整数,Pmax是大于等于4的整数。
可选地,基础校验矩阵的参数kb为基础校验矩阵***列数。
实施例2
在本实施例中还提供了一种结构化LDPC码的数据处理装置,该装置用于实现上述实施例及可选实施方式,已经进行过说明的不再赘述。如以下所使用的,术语“模块”可以实现预定功能的软件和/或硬件的组合。尽管以下实施例所描述的装置较佳地以软件来实现,但是硬件,或者软件和硬件的组合的实现也是可能并被构想的。
图3是根据本发明实施例的一种结构化LDPC码的数据处理装置的结构框图一,如图3所示,该装置包括:
1)获取模块32,用于获取结构化LDPC编码的编码块大小;
2)确定模块34,耦合至获取模块32,用于至少根据以下参数之一确定编码扩展因子z:编码块大小、基础校验矩阵的参数kb、正整数值p;
3)处理模块36,耦合至确定模块34,用于根据基础校验矩阵和编码扩展因子对待编码数据序列进行编码或者对待译码数据序列进行译码;
其中,kb=nb-mb,kb、p、mb、z和nb均是大于1的整数。
可选地,上述结构化LDPC码的数据处理装置可以但不限于应用于处理数据序列的场景中。例如:LDPC编码译码处理数据序列的场景。
可选地,上述结构化LDPC码的数据处理装置可以但不限于应用于LDPC编码器或者LDPC译码器,例如:利用LDPC编码的发送端、利用LDPC解码的接收端。
通过上述装置,获取模块获取结构化LDPC编码的编码块大小;确定模块至少根据以下参数之一确定编码扩展因子z:编码块大小、基础校验矩阵的参数kb、正整数值p、mb行和nb列的基础校验矩阵;处理模块根据基础校验矩阵和编码扩展因子对待编码数据序列进行编码或者对待译码数据序列进行译码;其中,kb=nb-mb,kb、p、mb、z和nb均是大于1的整数,由此可见,采用上述方案根据LDPC编码的编码块大小、基础校验矩阵的参数kb、正整数值p中的至少之一确定编码扩展因子,并根据基础校验矩阵和编码扩展因子进行LDPC编译码,因此,提高了LDPC编译码数据处理的灵活度,从而解决了相关技术中LDPC编译码的数据处理灵活度低的问题。进一步,支持对不同长度的编码块大小进行有效的LDPC编码和译码,进而降低了LDPC编译码的复杂度。
可选地,确定模块可以但不限于用于:通过公式
Figure PCTCN2016104744-appb-000018
确定编码扩展因子,其中,CBS为编码块大小,
Figure PCTCN2016104744-appb-000019
表示向上取整。
可选地,获取模块可以但不限于用于:编码块大小等于基础校验矩阵的参数kb与一 组升序自然数中的一个元素相乘所获得的数值。
可选地,一组升序自然数中可以但不限于包括多个分组,其中,多个分组中的分组内相邻元素的第一增加值相等。
可选地,一组升序自然数中的第i个分组的第一增加值小于第i+1个分组的第一增加值,其中,i为正整数。
可选地,确定模块用于:编码块大小为一组编码块大小中的一个元素值,一组编码块大小为升序的第一自然数组;编码扩展因子为一组编码扩展因子中的一个元素值,一组编码扩展因子为升序的第二自然数组。
可选地,一组编码块大小中包括连续的a个元素,其中,在连续的a个元素的首元素值大于z(j)×kb,且尾元素值小于或者等于z(j+1)×kb的情况下,连续的a个元素对应的编码扩展因子为z(j+1),a为正整数,z(j)为一组编码扩展因子中的第j个元素值,j为正整数,kb是基础校验矩阵的参数。
可选地,在获取的编码块大小为连续的a个元素中的一个元素的情况下,编码扩展因子为z(j+1)。
可选地,在编码块大小与基础校验矩阵的参数kb的比值大于z(j)且小于或者等于z(j+1)的情况下,编码扩展因子被确定为z(j+1),其中,z(j)为一组编码扩展因子中的第j个元素值。
可选地,一组编码扩展因子中包括多个分组,其中,多个分组的分组内相邻元素的第二增加值相等,多个分组中的第h个分组的第二增加值小于第h+1个分组的第二增加值,h为正整数。
可选地,一组编码扩展因子中的所有大于正整数值p的元素值都是正整数值p的正整数n倍。
可选地,一组编码块大小至少包括:基础校验矩阵的参数kb与一组编码扩展因子相乘得到的乘积值,以及全部乘积值之间间隔为B的整数值,其中,B为正整数。
图4是根据本发明实施例的一种结构化LDPC码的数据处理装置的结构框图二,如图4所示,可选地,装置还包括:
第一比特填充模块42,耦合至处理模块36,用于对第一数据序列进行比特填充,其中,对第一数据序列进行比特填充包括:将第一数据序列分成多个子数据序列,对多个子数据序列分别进行比特填充,所有填充比特后的子数据序列构成待编码数据序列。
图5是根据本发明实施例的一种结构化LDPC码的数据处理装置的结构框图三,如图5所示,可选地,装置还包括:
第二比特填充模块52,耦合至处理模块36,用于对第二数据序列进行比特填充,其 中,对第二数据序列进行比特填充包括:将第二数据序列分成kb个比特数目小于或者等于z的子数据序列,对每个子数据序列添加填充比特使得每组子数据序列的比特数目达到z,所有填充比特后的子数据序列构成待编码数据序列,其中,kb是础校验矩阵的参数,z是编码扩展因子。
可选地,装置还包括:添加模块,耦合至第一比特填充模块42或者第二比特填充模块52,用于对第三数据序列添加L比特的循环冗余校验CRC序列获得第一数据序列或者第二数据序列,其中,L是大于或者等于0的整数。
可选地,基础校验矩阵的参数kb为编码基础校验矩阵的列数和编码基础校验矩阵的行数的差值,kb是大于等于4且小于等于64的一个整数。
可选地,正整数值p可以但不限于是LDPC译码并行度。
可选地,正整数值p是一个固定正整数,LDPC译码并行度p包括:正整数值p为2的正整数次幂或者正整数值p为2的正整数次幂再乘以一个素数。
可选地,正整数值p是子集合P的一个元素,其中,该子集合P是Pmax的所有正整数因子所构成集合中的一个子集,Pmax是大于3且小于或者等于1024的一个整数。
可选地,正整数n的所有取值构成子集合nSet,其中,nSet是正整数集合Ns中长度为F的一个子集,正整数集合Ns={1、2、3、…、M},M是大于1的整数。
可选地,子集合nSet包括以下之一:正整数集合Ns中的前F个元素构成的子集合、正整数集合Ns中的后F个元素构成的子集合、正整数集合Ns中的F个素数构成的子集合、正整数集合Ns中的F个奇数构成的子集合、正整数集合Ns中的F个偶数构成的子集合,F是小于M的正整数。
需要说明的是,第一种情况“正整数值p为2的正整数次幂”和第二种情况“正整数值p为2的正整数次幂再乘以一个素数”是排他的,如果素数是2,则第一种情况和第二种情况是同一种情况,就不合理了,所以素数为2的情况需要归类到第一种情况,进一步,本文理解是:第一种情况是1*2的幂次,而1不属于素数。所以说这里的素数至少大于等于3的。
可选地,编码扩展因子包括:编码扩展因子等于2的正整数次幂然后减1,或者编码扩展因子等于2的正整数次幂再乘以一个素数,的素数包括以下之一:3、5、7、11、13、17、19、23、29。可选地,编码扩展因子等于2的正整数次幂再乘以一个素数,该素数包括3和5。或者可选地,编码扩展因子等于2的正整数次幂再乘以一个素数,该素数包括5和7。以及可选地,编码扩展因子等于2的正整数次幂再乘以一个素数,该素数包括3、5和7。
可选地,编码扩展因子包括以下之一:7、15、31、63、127、255、511、1023、2047、4095。
可选地,该装置还可以包括:存储模块,用于至少存储基础校验矩阵。
可选地,装置还用于:在对待编码数据序列进行编码之前,在待编码数据序列中填充长度为k’比特的哑元比特获得长度为kb*z比特的待编码数据序列,其中,k’与kb*z的比值小于或等于1/4,k’是大于或者等于0的整数,kb是基础校验矩阵的***列数,z是编码使用的扩展因子大小,kb是大于1的整数,z是大于0的整数。
可选地,扩展因子z均为一个正整数值pl的n倍。
可选地,正整数值pl是子集合Pset的一个元素,其中,子集合Pset是Pmax的所有正整数因子所构成集合中的一个子集,n是一个自然数,Pmax是大于等于4的整数。
可选地,正整数n的所有取值构成子集合nSet,其中,nSet是正整数集合Ns中长度为F的一个子集,正整数集合Ns={1、2、3、…、M},M是大于1的整数。
可选地,基础校验矩阵中指示非全0方阵的任何hbij元素的满足如下条件:mod(hbij,(Pmax/pl))=0,其中,i=0,1,2..,mb-1,j=0,1,…,nb-1,Pmax是大于等于4的整数。
可选地,基础校验矩阵中指示非全0方阵的任何hbij元素的满足如下条件:mod(hbij,(Pmax/pl))=A,其中i和j分别是基础校验矩阵中行索引i和列索引j的元素以及hbij指示非全0方阵,A是小于pl且大于或者等于0的固定整数,Pmax是大于等于4的整数。
可选地,基础校验矩阵的参数kb为基础校验矩阵***列数。
需要说明的是,上述各个模块是可以通过软件或硬件来实现的,对于后者,可以通过以下方式实现,但不限于此:上述模块均位于同一处理器中;或者,上述模块分别位于多个处理器中。
下面结合本发明可选实施例进行详细说明。
本发明可选实施例提供了一种LDPC编码译码方法,该方法包括以下步骤:
步骤101、获取结构化LDPC编码的编码块大小;
步骤102、至少根据以下参数之一确定编码扩展因子z:编码块大小、基础校验矩阵的参数kb、正整数值p、基础校验矩阵;
步骤103、根据基础校验矩阵和编码扩展因子对待编码数据序列进行编码或者对待译码数据序列进行译码。
可选地,至少根据编码块大小CBS、基础校验矩阵的参数kb和正整数值p确定编码扩展因子包括:编码扩展因子等于
Figure PCTCN2016104744-appb-000020
其中,CBS是编码块大小。在实际LDPC分层译码过程中,正整数值p对应于LDPC译码并行度,或者等于译码并行度的整数倍。此时编码扩展因子采用与并行度相关,好处在于使得LDPC分层译码硬件简单,不会出现译码器中交织/解交织不对应的问题。
可选地,编码块大小等于基础校验矩阵的参数kb与一组升序自然数中的一个元素相 乘所获得的数值。
可选地,基础校验矩阵的参数kb是基础校验矩阵列数和基础校验矩阵行数的差值,基础校验矩阵的参数kb等于从整数4到64范围内的一个整数。并且,一组升序自然数中,包括多个分组,分组内增加值相等。而且,可选地,一组升序自然数中,第i个分组的增加值小于第i+1个分组的增加值,其中,i是正整数。
可选地,编码块大小是一组编码块大小中的一个元素值,编码扩展因子是一组扩展因子中的一个元素值,一组编码块大小是升序的一组自然数,一组扩展因子都是升序的一组自然数。
可选地,一组编码块大小中连续a个元素,其中,连续a个元素的首元素值大于z(j)×kb,而且尾元素值小于或者等于z(j+1)×kb,则连续a个元素对应的编码扩展因子为z(j+1),其中a是正整数,z(j)是一组扩展因子中的第j个元素值。并且,若编码块大小属于连续a个元素中,则编码扩展因子限制为z(j+1)。
可选地,一组扩展因子,包括多个分组,分组内增加值相等,第h个分组的增加值小于第h+1个分组的增加值,其中,h是正整数。而且,一组编码块大小至少包括:基础校验矩阵的参数kb与一组扩展因子相乘得到的乘积值,以及所有乘积值之间间隔为B的整数值,其中,B是正整数。基础校验矩阵的参数kb与一组扩展因子相乘得到的乘积值其实就是LDPC码在不同编码扩展因子下支持的最大***比特数目,在各个***比特数目之间也可包含有编码块大小,可以使得编码块大小更加灵活,便于在各种通信***中使用,同时解决LDPC码的码长和码率灵活性不够的问题。
可选地,编码扩展因子等于2的正整数次幂然后减1,以及更为具体地,编码扩展因子包括:等于7、15、31、63、127、255、511、1023、2047和4095中的一个。此时,有利于在LDPC码中每z比特分组内包含相应数目的循环冗余校验(CRC)比特,并且根据CRC循环码的特性(循环移位任意比特依然是属于CRC循环码字空间,即依然是一个CRC循环码),所以可以获得LDPC码的校验比特中每z比特分组也是CRC循环码,依然可以进行CRC校验,有利于提高LDPC码的译码性能,并且在迭代译码过程加速译码收敛,减少译码时间从而提高译码速度,的z等于扩展因子的值;或者,编码扩展因子可以等于2的正整数次幂再乘以一个素数,更为具体的,例如,一个素数从2、3、5、7、11、13、17、19、23和29中的一个。根据素数的定义,其整数因子除了1和自身以外没有其他了,那么整数就是素数,所以1不属于素数。采用该扩展因子值,便于简化LDPC码的交织和解交织网络,根据LDPC码原理,基础校验矩阵中的每个元素值都对应一个循环移位数目,依据一定原理采用以上数值,可以简化该交织网络和解交织网络,进而降低LDPC码的复杂度(交织网络几乎占用LDPC码译码复杂度的40%左右,一旦降低该部分则LDPC译码复杂度可以得到简化)。
可选地,提供一种扩展因子取值的实例,如编码扩展因子可以等于2的正整数次幂再乘以一个素数,该素数包括3和5,正整数是1、2、3、4、5、6、7、8。采用扩展因子带来的有益效果是:可以使得LDPC译码器复杂度很低,并且支持灵活码长设计。在LDPC译码器中,一般包括存储模块、交织网络模块、解交织网络模块和计算模块等,对于存储模块中存储的是更新后的总软信息(总软信息是所有外信息相加的结果),译码器中需要为基础校验矩阵中的每列分配1个存储块(如果基础校验矩阵大小为mb行nb列,则有nb个存储块),而每个存储块会分为多个地址块,可以将每个地址块定义为1个word,则单个存储块就可以存储多个word,当LDPC译码设计时,一般来说译码并行度等于word大小,word大小是指存储于word中的软比特数目。在本实例中,由于素数的最大值为5,以及2的最大幂次为8,所以LDPC码译码器中的每个存储块有5个word,每个word的大小为28=256;在LDPC码译码过程中,先从存储模块中读取数据,经过交织网络模块,然后进入计算单元,而后再进行解交织,最后再写回存储模块;当扩展因子等于5*28=1280时,正好填满5个word,每个word有256个软比特数据,而在灵活码长(即通过改变扩展因子获得不同码长)情况下,如扩展因子为5*24=80,此时还是占用5个word,只是不同的是每个word中只存储24=16个软比特数据,而且每个word中每间隔16个数据放一个软比特数据,此时当读取word中的数据进行更新时,由于只有16个有效数据,所以此时译码中的计算单元中只有16个有效校验节点更新;而当扩展因子等于素数3的整数倍(2的幂次),此时只要3个word在工作即可,在译码器中,对于扩展因子等于素数乘以2的正整数次幂(1、2、3、4、5、6、7、8)时,素数等于3或者5,以上硬件是可以共用的,即能支持灵活码长设计。
以及,素数可以包括5和7,2的幂次为(1、2、3、4、5、6、7、8),此时word大小也为256,需要7个word,此时由于选用稍大的素数7,可以使得扩展因子较大,可以支持更大的码长。以及可选地,素数可以包括3、5和7,2的幂次为(1、2、3、4、5、6、7、8),此时word大小也为256,由于最大素数为7,所以需要7个word,当扩展因子是3的整数倍,则选择3个word工作;当扩展因子是5的整数倍,则选择5个word工作;当扩展因子是7的整数倍,则选择7个word工作;此时大的扩展因子可以保证LDPC能支持大码长的LDPC码,小的扩展因子可以保证LDPC能支持小码长的LDPC码,取值范围比较合理,使得LDPC码可以支持较大码长范围。本发明可选实施例还提供了一种LDPC编码译码装置,该装置包括:
获取模块201,用于获取结构化LDPC编码的编码块大小;
确定模块202,用于至少根据以下参数之一确定编码扩展因子z:编码块大小、基础校验矩阵的参数kb、正整数值p、基础校验矩阵;
编码模块203,用于根据基础校验矩阵和编码扩展因子对待编码数据序列进行编码或者对待译码数据序列进行译码。
存储模块204,用于至少存储基础校验矩阵。
其中,获取模块中,编码块大小限制为基础校验矩阵的参数kb与一组升序自然数相乘所获得的数值。其中,基础校验矩阵的参数kb是基础校验矩阵列数和基础校验矩阵行数的差值,基础校验矩阵的参数kb等于从整数4到64范围内的一个整数。以及,一组升序自然数中,包括多个分组,分组内增加值相等。并且,一组升序自然数中,第i个分组的增加值小于第i+1个分组的增加值,其中,i是正整数。
可选地,确定模块中,根据编码块大小和正整数值p确定编码扩展因子,包括:编码扩展因子等于
Figure PCTCN2016104744-appb-000021
其中,CBS是编码块大小,kb是基础校验矩阵列数和基础校验矩阵行数的差值,p是正整数。
可选地,编码块大小是一组编码块大小中的一个元素值,编码扩展因子是一组扩展因子中的一个元素值,一组编码块大小是升序的一组自然数,一组扩展因子都是升序的一组自然数,一组编码块大小的维数大于或者等于一组扩展因子的维数。可选地,一组编码块大小中连续a个元素,其中,连续a个元素的首元素值大于z(j)×kb,而且尾元素值小于或者等于z(j+1)×kb,则连续a个元素对应的编码扩展因子为z(j+1),其中a是正整数,z(j)是一组扩展因子中的第i个元素值。而且,若编码块大小属于连续a个元素中,则编码扩展因子限制为z(j+1)。并且,一组扩展因子,包括多个分组,分组内增加值相等,第i个分组的增加值小于第i+1个分组的增加值,其中,i是正整数。
可选地,一组编码块大小至少包括:基础校验矩阵的参数kb与一组扩展因子相乘得到的乘积值,以及所有乘积值之间间隔为B的整数值,其中,B是正整数。
可选地,编码扩展因子等于2的正整数次幂然后减1,或者等于2的正整数次幂再乘以一个素数。更为具体地,编码扩展因子包括:等于7、15、31、63、127、255、511、1023、2047和4095中的一个。
实施例3
在本实施例中还提供了一种结构化LDPC码的数据处理方法,该方法用于实现上述LDPC码编码译码方法,已经进行过说明的不再赘述。如以下所使用的,术语“方法”或“模块”等可以实现预定功能的软件和/或硬件的组合。尽管以下实施例所描述的方法较佳地以软件来实现,但是硬件,或者软件和硬件的组合的实现也是可能并被构想的。
根据本发明实施例的一种结构化LDPC码的数据处理方法,用于发送端,该方法包括以下步骤:
1、码块分割,将长度为CL的传输块进行码块分割成多份编码块;
2、依据码块分割后的编码块大小,获取结构化LDPC编码的编码块大小;
3、至少根据以下参数之一确定编码扩展因子z:所述编码块大小、基础校验矩阵的参数kb、正整数值p、基础校验矩阵;
4、根据所述基础校验矩阵和所述编码扩展因子对待编码数据序列进行编码。
可选地,步骤2中,由编码块大小确定编码扩展因子,其中根据所述编码块大小确定所述编码扩展因子包括:所述编码块大小为一组编码块大小中的一个元素值,所述一组编码块大小为升序的第一自然数组;以及所述编码扩展因子为一组编码扩展因子中的一个元素值,所述一组编码扩展因子为升序的第二自然数组。
可选地,所述一组编码扩展因子中的所有大于所述正整数值p的元素值都是所述正整数值p的正整数n倍。
可选地,所述正整数值p是子集合Pset的一个元素,其中,所述子集合Pset是Pmax的所有正整数因子所构成集合中的一个子集,Pmax是大于3且小于或者等于1024的一个整数。其中,所述的Pmax是数据接收端的LDPC译码器所支持的最大译码并行度。其中,所述译码并行度是指LDPC译码器中可以同时进行的奇偶校验码更新的数目,而所述的Pmax是指LDPC译码器所支持的最大并行度。一般来说,LDPC译码器中支持的最大译码并行度为Pmax,那么其可以支持小于Pmax的其他并行度,可能会增加一些控制电路。
以及,可选地,所述正整数n的所有取值构成子集合nSet,其中,所述nSet是正整数集合Ns中长度为F的一个子集,所述正整数集合Ns={1、2、3、…、M},M是大于1的整数,所述子集合nSet包括以下之一:所述正整数集合Ns中的前F个元素构成的子集合、所述正整数集合Ns中的后F个元素构成的子集合、所述正整数集合Ns中的F个素数构成的子集合、所述正整数集合Ns中的F个奇数构成的子集合、所述正整数集合Ns中的F个偶数构成的子集合,F是小于M的正整数。
发送端的一个LDPC码编码实例,需要发送的传输块大小4000比特,LDPC码采用的基础校验矩阵如下所示,对应的一组编码扩展因子为[2 4 6 8 10 12 16 20 24 32 40 48 64 80 96 128 160 192 256 320 384 512 640 768 1024 1280]。所述一组扩展因子中,包括5乘以2的[1 2 3 4 5 6 7 8]幂次,为[10 20 40 80 160 320 640 1280];以及还包括3乘以2的[1 2 3 4 5 6 7 8]幂次,为[6 12 24 48 96 192 384 768];以及还包括2乘以2的[1 2 3 4 5 6 7 8]幂次,为[4 8 16 32 64 128 256 512];以及还包括1乘以2的[1 2 3 4 5 6 7 8]幂次,为[2 4 8 16 32 64 128 256]。即子集合nSet取值为包括[1 2 3 5],子集合Pset取值为包括[2 4 8 16 32 64 128 256]。所述一组编码扩展因子中的扩展因子等于正整数值p的正整数n倍,其中n是所述子集合nSet的一个元素,p是所述子集合Pset的一个元素。所述基础校验矩阵亦可成为基础校验矩阵或者其他称谓。所述扩展因子亦可称为提升值或者子矩阵大小或者其他等。基础校验矩阵的参数kb是所述基础校验矩阵的***列数目,基础校验矩阵的总列数为nb,基础校验矩阵的行数为mb,其中,kb=nb-mb;例如本实例中的基础校验矩阵的***列数 为kb=8,行数为mb=18,总列数为nb=26,满足kb=nb-mb。LDPC码采用的基础校验矩阵等于:
Figure PCTCN2016104744-appb-000022
一组编码块大小为至少包括所述一组编码扩展因子与kb=8的乘积,即等于[16 32 48 64 80 96 128 160 192 256 320 384 512 640 768 1024 1280 1536 2048 2560 3072 4096 5120 6144 8192 10240]。
本实例包括以下步骤:
1、码块分割,将长度为CL=4000比特的传输块进行码块分割成多份编码块;由于传输块长度为4000比特小于以上所述一组编码块大小的最大值(10240),所以进行码块分割时,只分成1份编码块,其长度为4000比特。
2、依据码块分割后的编码块大小4000,获取结构化LDPC编码的编码块大小,其等于4000;
3、至少根据以下参数之一确定编码扩展因子z:所述编码块大小;此时由于一组编码块大小中大于4000的最小值为4096,所以LDPC码的***比特长度(即输入LDPC编码器中的比特数目)为为4096,需要填充比特数目为4096-4000=96比特。由于一组编码块大小中大小为4096对应的扩展因子为512,所以编码所使用到的扩展因子为z=512。依据扩展因子z=512对基础校验矩阵的所有元素进行修正,其中修正方法如下公式:
Figure PCTCN2016104744-appb-000023
4、根据所述基础校验矩阵和所述编码扩展因子对待编码数据序列进行编码获得长度为13312比特的LDPC码字,根据编码码率R从所述LDPC码字选择出相应码长的码字即可,例如码率为R=1/2,则可以知道需要传输的码长为4000/(1/2)=8000比特,从13312比特中选择8000比特进行传输,其中选择方法为:先对长度为512*26=13312的码字按z=512为单位进行重排,重排向量为[0~7,[8,9,11,10],12:25];从第z*2=1024比特开始进行循环选择,如果达到尾比特则从首比特开始选择,遇到填充比特跳过,选出N=8000比特的LDPC码字。发送所述的N=8000比特的LDPC码字。
对应以上所述的示例,所述有一个接收端,用于接收所述的发送的LDPC码字。所述 接收端的LDPC译码方法,包括以下步骤:
1、接收并解调收到的数据获得长度为8000个软比特信息,即获得长度为8000的待译码数据序列;
2、获取结构化LDPC编码的编码块大小,其等于4000;所述获得的编码块大小可以是通过***配置的信令获得;
3、至少根据以下参数之一确定编码扩展因子z:所述编码块大小;所述确定编码扩展因子z以及基础校验矩阵的修正方法与以上发送端所述的确定方法一致,这里不再赘述。
4、根据所述基础校验矩阵和所述编码扩展因子对长度为8000的待译码数据序列进行译码,由于基础校验矩阵的实际码长为13312,填充比特数为96,所以将填充位置的软比特信息置为很大值,将8000个软比特信息置于对应13312的码字的比特选择位置中,其他软信息(可以说是打孔比特位置或者不传输比特位置)等于0。然后对长度为13312的待译码软信息序列进行译码,输出4096个***比特,去除填充比特,获得长度为4000比特的数据。所述译码过程中,由于对应的一组编码扩展因子为[2 4 6 8 10 12 16 20 24 32 40 48 64 80 96 128 160 192 256 320 384 512 640 768 1024 1280]。所述一组扩展因子中,包括5乘以2的[1 2 3 4 5 6 7 8]幂次,为[10 20 40 80 160 320 640 1280],设为集合Z0;以及还包括3乘以2的[1 2 3 4 5 6 7 8]幂次,为[6 12 24 48 96 192 384 768],设为集合Z1;以及还包括2乘以2的[1 2 3 4 5 6 7 8]幂次,为[4 8 16 32 64 128 256 512],设为集合Z2;以及还包括1乘以2的[1 2 3 4 5 6 7 8]幂次,为[2 4 8 16 32 64 128 256],设为集合Z3;所以译码器中的可以支持最大译码并行度为2的8次幂,即并行度为256,即Pmax为256,译码器中的最大保存5个word,每个word大小为256长度。当编码所使用的扩展因子在以上所述的任意集合中,如在集合Z0中,译码器中的软信息分别存放在5个word中;如果在集合Z1中则存在3个word中;如果在集合Z2中则存在2个word中;如果在集合Z3中则存在1个word中。采用类似实施例2中所述的译码器方法,进而可以支持灵活码长的设计。
以及所述的LDPC码还可以包括如下例子。基础校验矩阵采用如下所示,大小分别为:矩阵行数mb=8,矩阵***列数kb=8,矩阵总列数nb=16。一组扩展因子取值为[18 21 30 35 42 63 70 105 126 210],即包括2个集合[6 7 14 21 42]*3和[6 7 14 21 42]*5,即子集合Pset为[6 7 14 21 42],子集合nSet为[3 5]。基础校验矩阵等于:
Figure PCTCN2016104744-appb-000024
同理发送端按照以上所述的步骤进行数据处理,确认扩展因子和基础校验矩阵,并进 行结构化LDPC编码,具体步骤这里不再赘述;接收端也同理,按以上所述步骤进行。接收端的译码器可采用的最大并行度为子集合Pset中的最大元素42,在LDPC译码器中,所述的译码并行度为可以为42或者任意一个比42小的且是42的整数因子。译码器中,如果编码使用的扩展因子是[6 7 14 21 42]*3中,则采用3个word构成的一个存储块,用于存储译码需要的软信息,如确定编码使用的扩展因子为63,此时由于分为3个word,所以实际译码并行度31;如果编码使用的扩展因子是[6 7 14 21 42]*5中,则采用5个word构成的一个存储块,用于存储译码需要的软信息,例如编码使用的扩展因子为70,此时由于分为5个word,所以实际译码并行度14。
实施例4
在本实施例中还提供了一种结构化LDPC码的数据处理方法,该方法用于实现上述LDPC码编码译码方法,已经进行过说明的不再赘述。如以下所使用的,术语“方法”或“模块”等可以实现预定功能的软件和/或硬件的组合。尽管以下实施例所描述的方法较佳地以软件来实现,但是硬件,或者软件和硬件的组合的实现也是可能并被构想的。
根据本发明实施例的一种结构化LDPC码的数据处理方法,用于发送端,该方法包括以下步骤:
1、码块分割,将长度为CL的传输块进行码块分割成多份编码块;
2、依据码块分割后的编码块大小,获取结构化LDPC编码的编码块大小;
3、确定编码扩展因子z:所述编码块大小、基础校验矩阵的参数kb、正整数值p、基础校验矩阵;所述扩展因子z都是一个正整数值pl的n倍。更为具体的,所述正整数值pl是子集合Pset的一个元素,其中,所述子集合Pset是Pmax的所有正整数因子所构成集合中的一个子集,n是一个自然数,Pmax是大于等于4的整数。以及,所述正整数n的所有取值构成子集合nSet,其中,所述nSet是正整数集合Ns中长度为F的一个子集,所述正整数集合Ns={1、2、3、…、M},M是大于1的整数。
以及所述基础校验矩阵包括以下参数:***列数kb,矩阵行数(或者校验列数)mb,矩阵总列数nb,其中,kb=nb-mb。以及基础校验矩阵矩阵中的元素至少包括两种类型:1、指示全0方阵的元素,在本专利中用-1表示,也可用空值等表示或其他描述方式;2、指示单位阵的循环移位方阵的元素(即为非全0方阵),所述元素是大于等于0且小于扩展因子的整数,用于指示单位阵的循环移位的位数。所述基础校验矩阵也可以包括多边结构,所述多变结构是指基础校验矩阵中出现至少包括:同一行索引和列索引上有2个元素,用于指示2个循环移位特定位后的方阵的相加构成。
所述基础校验矩阵中指示非全0方阵的任何hbij元素的满足如下:mod(hbij,(Pmax/pl))=0,其中,i=0,1,2..,mb-1,j=0,1,…,nb-1,Pmax是大于等于4的整数。
4、根据所述基础校验矩阵和所述编码扩展因子对待编码数据序列进行编码。
按以上,以下提供一种基础校验矩阵,用于所述结构化LDPC编码方法。所述参数Pmax=42,Pset={6 21 42},nSet={3 5},所述基础校验矩阵的扩展因子取值根据Pset和nSet确定,即等于3*Pset和5*Pset,即所有扩展因子构成集合{18 30 63 105 126 210},可见Pset是Pmax的所有正整数因子所构成集合中的一个子集。所述各个扩展因子所对应每个基础校验矩阵描述如下,其中矩阵参数为:***列数kb=8,矩阵行数(或者校验列数)mb=4,矩阵总列数nb=12,即满足kb=nb-mb。
扩展因子为18,对应p=6,n=3,基础校验矩阵Hb0:
Figure PCTCN2016104744-appb-000025
扩展因子为30,对应p=6,n=5,基础校验矩阵Hb1:
Figure PCTCN2016104744-appb-000026
扩展因子为63,对应p=21,n=3,基础校验矩阵Hb2:
Figure PCTCN2016104744-appb-000027
扩展因子为105,对应p=21,n=5,基础校验矩阵Hb3:
Figure PCTCN2016104744-appb-000028
扩展因子为126,对应p=42,n=3,基础校验矩阵Hb4:
Figure PCTCN2016104744-appb-000029
扩展因子为210,对应p=42,n=5,基础校验矩阵Hb5:
Figure PCTCN2016104744-appb-000030
可以发现以上所述的基础校验矩阵中,所述基础校验矩阵中指示非全0方阵的任何 hbij元素的满足如下:mod(hbij,(Pmax/pl))=0,在例子中的所有基础校验矩阵中所述的hbij是不等于-1的元素。
采用以上所述的基础校验矩阵作为LDPC码的编码基础校验矩阵的有益效果类似于实施例2。此时信息存储中,以word为单位作为一个地址的存储,信息的存储非常简单,便于支持灵活码长设计。如上以Hb0为例,进行描述。此时,译码器的存储模块如图10所示。基础校验矩阵的总列数都为12列,所以有12个存储块,每个存储块有5个word。图10所示的1001对应基础校验矩阵的第0列的存储块,1002对应基础校验矩阵的第1列,每个word的大小等于Pmax=42,即支持最大并行度为Pmax。当在不同扩展因子情况下,所述的存储块可以共用。Hb0和Hb1的存储模块可以采用图10所示的1003进行存储,所述黑色说明存储信息,由于此时扩展因子是18和30,对应基础校验矩阵每列的软比特信息只有18和30,所以每个word中软比特信息是按每7个存放一个软比特信息,Hb0采用3个word,Hb1采用5个word。
同理,当采用Hb2和Hb3的存储模块可以采用图10所示的1004进行存储,所述黑色说明存储信息,由于此时扩展因子是63和105,对应基础校验矩阵每列的软比特信息只有63和105,所以每个word中软比特信息是按每2个存放一个软比特信息,Hb2采用3个word,Hb3采用5个word。
同理,当采用Hb4和Hb5的存储模块可以采用图10所示的1005进行存储,所述黑色说明存储信息,由于此时扩展因子是126和210,对应基础校验矩阵每列的软比特信息只有126和210,此时每个word中软比特信息填满,Hb2采用3个word,Hb3采用5个word。
采用以上所述的扩展因子集合以及基础校验矩阵,有益效果就在于LDPC译码器可以完全统一,大大降低采用多个译码器带来的复杂度,以及基础校验矩阵中每列的交织网络可以共用或者采用固定电路网络实现,降低复杂度以及译码时延。
以及提供一种基础校验矩阵如下:扩展因子为63,对应p=21,n=3,基础校验矩阵Hb6,满足mod(hbij,(Pmax/pl))==A,其中A=1:
Figure PCTCN2016104744-appb-000031
在本发明可选实施例中提出的方法可以用于LTE移动通信***或者未来第五代移动通信***,数据传输方向为基站向移动用户发送数据(下行传输业务数据),或者数据传输方向为移动用户向基站发送数据(上行传输业务数据)。移动用户包括:移动设备、为 接入终端、用户终端、用户站、用户单元、移动站、远程站、远程终端、用户代理、用户装置、用户设备、或一些其它术语。基站包括接入点(AP)、或可以称为节点B(node B)、无线电网络控制器(RNC)、演进型Node B(Evolved Node B,eNB)、基站控制器(BSC)、基站收发台(BTS)、基站(BS)、收发机功能体(TF)、无线电路由器、无线电收发机、基本服务单元(BSS)、扩展服务单元(ESS)、无线电基站(RBS),或一些其它术语。
根据本发明可选实施例的一个方面,本可选实施例提供一种结构化LDPC码的数据处理方法,应用于new RAT(New Radio Access Technology)中的eMBB(enhanced Mobile Broadband)场景、URLLC(Ultra-Reliable and Low Latency Communications)场景或者mMTC(massive Machine Type Communications)场景中。其中eMBB场景中下行最大吞吐量可以达到20Gbps,上行数据最大吞吐量可以达到10Gbps;以及在URLLC中,可以支持可靠性最低达到10e-5的BLER(Block Error Rate)以及上下行达到最短时延达到0.5毫秒;以及mMTC能使设备电池可以使用多年不断电。本实施例的结构化LDPC码的数据处理方法包括以下步骤:
1、获取结构化LDPC编码的编码块大小;
2、至少根据以下参数之一确定编码扩展因子z:编码块大小、基础校验矩阵的参数kb和正整数值P;
3、根据基础校验矩阵和编码扩展因子对待编码数据序列进行编码或者对待译码数据序列进行译码。
可选地,至少根据编码块大小CBS、基础校验矩阵的参数kb和正整数值p确定编码扩展因子,包括:通过公式
Figure PCTCN2016104744-appb-000032
确定编码扩展因子,其中,
Figure PCTCN2016104744-appb-000033
表示向上取整。
可选地,获取结构化LDPC编码的编码块大小包括:编码块大小等于基础校验矩阵的参数kb与一组升序自然数中的一个元素相乘所获得的数值。并且,一组升序自然数中包括多个分组,其中,多个分组中的分组内相邻元素的第一增加值相等。以及,一组升序自然数中的第i个分组的第一增加值小于第i+1个分组的第一增加值,其中,i为正整数。如此设计的好处在于,一组升序自然数是逐步增加的,所以其支持编码块大小在较小长度时变化间隔较小,在较大长度时变化间隔较小,即不需要更密的编码块大小,使得通信***比较灵活,而且少用信令指示,信令交互较少,进而***复杂度低。
或者,可选地,根据编码块大小确定编码扩展因子,包括:编码块大小为一组编码块大小中的一个元素值,一组编码块大小为升序的第一自然数组;编码扩展因子为一组编码扩展因子中的一个元素值,一组编码扩展因子为升序的第二自然数组。以及,可选地,一组编码块大小中包括连续的a个元素,其中,在连续的a个元素的首元素值大于z(j)×kb,且尾元素值小于或者等于z(j+1)×kb的情况下,连续的a个元素对应的编码扩展因子为 z(j+1),a为正整数,z(j)为一组编码扩展因子中的第j个元素值,j为正整数,kb是基础校验矩阵的参数。如果在获取的编码块大小为连续的a个元素中的一个元素的情况下,编码扩展因子为z(j+1)。一组编码扩展因子中包括多个分组,其中,多个分组的分组内相邻元素的第二增加值相等,多个分组中的第h个分组的第二增加值小于第h+1个分组的第二增加值,h为正整数。一组编码块大小至少包括:础校验矩阵的参数kb与一组编码扩展因子相乘得到的乘积值,以及全部乘积值之间间隔为B的整数值,其中,B为正整数。
或者,若编码块大小与基础校验矩阵的参数kb的比值大于z(j)且小于或者等于z(j+1),则编码扩展因子被确定为z(j+1),其中,z(j)为一组编码扩展因子中的第j个元素值。一组编码扩展因子中的所有大于第一正整数值P的元素值都是第一正整数值P的正整数倍。的第一正整数值P是LDPC码译码并行度,限制扩展因子需要等于并行度p的整数倍的目的在于,LDPC分层译码过程可以使得译码器的交织和逆交织网络不会出现地址冲突问题,不需要而额外的硬件电路指示开销,译码复杂度低,对于硬件电路面积更少。
可选地,根据基础校验矩阵和编码扩展因子对待编码数据序列进行编码之前,方法还包括:对第一数据序列进行比特填充,其中,对第一数据序列进行比特填充包括:将第一数据序列分成多个子数据序列,对多个子数据序列分别进行比特填充,所有填充比特后的子数据序列构成待编码数据序列。或者,根据基础校验矩阵和编码扩展因子对待编码数据序列进行编码之前,方法还包括:对第二数据序列进行比特填充,其中,对第二数据序列进行比特填充包括:将第二数据序列分成kb个比特数目小于或者等于z的子数据序列,对每个子数据序列添加填充比特使得每组子数据序列的比特数目达到z,所有填充比特后的子数据序列构成待编码数据序列,其中,kb是础校验矩阵的参数,z是编码扩展因子。以及,在对第一数据序列进行比特填充或者对第二数据序列进行比特填充之前,方法还包括:对第三数据序列添加L比特的循环冗余校验CRC序列获得第一数据序列或者第二数据序列,其中,L是大于或者等于0的整数。如图9所示是加性白噪声信道下的性能对比,编码块大小为1120,结构化LDPC码的扩展因子为150,基础校验矩阵***列数为kb=8,填充比特数为80比特,其中图中padding1是指常规填充方法(即在首部或者尾部填充80比特),而padding2是本方案的方法,对1120分为8个子数据序列,每个子数据序列有140比特,每个填充10比特得到150比特,合并得到***比特序列,根据如图9所示性能,可以发现采用本专利的填充方案可以获得较大增益(约0.4dB)。或者,根据基础校验矩阵和编码扩展因子对待编码数据序列进行编码之前,还包括比特填充,其特征在于,比特填充包括:对第一数据序列分成多个子数据序列,对多个子数据序列分别进行比特填充,所有填充比特后的子数据序列构成待编码数据序列。在根据基础校验矩阵和编码扩展因子对待编码数据序列进行编码之前,还包括比特填充,其特征在于,比特填充包括:对第一数据序列分成kb个比特数目小于或者等于z的子数据序列,对每个子数据序列添加填充比特使得每组子数据序列的比特数目达到z,所有填充比特后的子数据序列构成待编码数据 序列,其中,kb是础校验矩阵的参数,z是编码扩展因子。比特填充之前还包括:对第二数据序列添加L比特的循环冗余校验CRC序列获得第一数据序列,其中,L是大于或者等于0的整数。
以上的正整数值p是一个固定正整数,LDPC译码并行度p包括:2的正整数次幂或者2的正整数次幂再乘以一个素数。好处在于p可以是较小数的倍数,在LDPC分层译码过程中,如果需要采用更小的硬件复杂度,那么依然可以采用更小的分层译码并行度p来实现,进而可以支持更低功耗的电路设计,如在mMTC场景中使用。
可选地,基础校验矩阵的参数kb为基础校验矩阵的列数和基础校验矩阵的行数的差值,kb是大于等于4且小于等于64的一个整数。基础校验矩阵的参数kb就是基础校验矩阵的***列数。编码扩展因子包括:编码扩展因子等于2的正整数次幂然后减1,或者编码扩展因子等于2的正整数次幂再乘以一个素数。更为具体地,编码扩展因子包括以下之一:7、15、31、63、127、255、511、1023、2047、4095。
更为具体的一个例子:
例子1
图6是根据本发明可选实施例的基础校验矩阵的示意图,在第5代移动通信中,用于发送端,eMBB场景中,需要传输的源数据包大小为7952比特,编码块大小为4000。已知基础校验矩阵(16行24列)如下,支持的最大扩展因子为zmax=1000。
如图6所示的基础校验矩阵,可以知道其参数有:基础校验矩阵行数mb=16,基础校验矩阵列数为nb=24,基础校验矩阵***列数kb=nb-mb=8。假设译码采用的并行度为p=20,每个编码块大小有24比特的循环冗余校验CRC序列,编码码率为1/2。依据以上的结构化LDPC码的数据处理方法,包括以下步骤:
步骤1、获取结构化LDPC编码的编码块大小,即等于CBS=4000;
步骤2、至少根据以下参数之一确定编码扩展因子z:编码块大小、基础校验矩阵的参数kb和第一正整数值P;
步骤2中,根据编码块大小CBS、基础校验矩阵的参数kb和第一正整数值p确定编码扩展因子,包括:通过公式
Figure PCTCN2016104744-appb-000034
确定编码扩展因子,其中,
Figure PCTCN2016104744-appb-000035
表示向上取整,可以知道扩展因子为z’=500。
步骤3、根据基础校验矩阵和编码扩展因子对待编码数据序列进行编码。
步骤3中,由于以上的基础校验矩阵是基于扩展因子z=1000的需要对基础校验矩阵进行修正,修正方式为:
Figure PCTCN2016104744-appb-000036
其中,(hij b)modified是修正后的基础校验矩阵的第i行第j列元素值,(hij b)uniform是以上的基础校验矩阵的第i行第j列元素值。由于编码码率为R=1/2,由kb可以计算出所需要的基础校验矩阵的行数为kb/R=16,直接截取如上修正后基础校验矩阵的8行和16列元素,或者先截取基础校验矩阵的8行和16列元素再进行修正,图7是根据本发明可选实施例的基础校验矩阵Hb’的示意图一,如图7所示,获得实际编码用的基础校验矩阵Hb’。
对大小为7952比特的源数据包进行码块分割(每个数据分组的比特数目尽量接近CBS-L=3976,其中L=24是CRC序列的比特数目),获得2份长度都为3976比特的第二数据序列,对2份第二数据序列添加L=24比特的循环冗余校验CRC序列获得长度都为4000比特的第一数据序列。由于结构化LDPC的实际***比特数目为kb×z'=8×500=4000kb×z=8×500=4000,编码块大小已经等于的实际***比特数目4000,所以无需再进行填充。
根据以上的实际编码用的基础校验矩阵Hb’=8和编码扩展因子z’=500对待编码数据序列(2份4000比特的第一数据序列)进行编码,获得2份长度都为8000比特的LDPC码块。调制并发送LDPC编码块。
如果用于接收端,则对接收数据进行解调获得2份长度都为8000的软信息数据序列(待译码数据序列),采用以上的实际编码用的基础校验矩阵Hb’和编码扩展因子z’=500分别对2份长度都为8000的软信息数据序列进行译码,获得结构化LDPC编码的***比特序列,去除24比特的CRC序列,可以得到长度为7952比特的源数据包。
例子2
本例子和例子1不同在于,需要传输的源数据包大小为3256比特,假设结构化LDPC码的编码块大小为3360。结构化LDPC编码的编码块大小等于基础校验矩阵的参数kb=8与一组升序自然数中的一个元素相乘所获得的数值。一组升序自然数中包括多个分组,其中,多个分组中的分组内相邻元素的第一增加值相等。一组升序自然数中的第i个分组的第一增加值小于第i+1个分组的第一增加值,其中,i为正整数。如一组升序自然数为[[2:1:200],[202:2:400],[406:6:796],[804:8:1004]]。
编码块大小3360与基础校验矩阵的参数kb=8的比值为420,大于z(302)=418且小于或者等于z(303)=424,则编码扩展因子被确定为z(303)=424。以及按z’为424对基础校验矩阵进行修正,图8是根据本发明可选实施例的基础校验矩阵Hb’的示意图二,如图8所示,可以得到如下基础校验矩阵Hb’。即满足:一组编码块大小中包括连续的a个元素,其中,在连续的a个元素的首元素值大于z(j)×kb,且尾元素值小于或者等于z(j+1)×kb的情况下,连续的a个元素对应的编码扩展因子为z(j+1),a为正整数,z(j)为一组编码扩展因子中的第j个元素值,j为正整数,kb是基础校验矩阵的参数。在获取的编码块大小为连续的a个元素中的一个元素的情况下,编码扩展因子为z(j+1)。
以及满足:一组编码扩展因子中包括多个分组,其中,多个分组的分组内相邻元素的第二增加值相等,多个分组中的第h个分组的第二增加值小于第h+1个分组的第二增加值,h为正整数。
由于结构化LDPC的实际***比特数目为kb×z=8×424=3392,对源数据包大小为3256比特(第三数据序列)添加L=24比特的循环冗余校验CRC序列获得长度为3384的第二数据序列,需要再填充8比特获得3392比特。填充方法包括,对第二数据序列分成kb=8个比特数目小于或者等于z=434的子数据序列,对每个子数据序列添加填充1比特使得每组子数据序列的比特数目达到z=434,所有填充比特后的子数据序列构成待编码数据序列,长度为3392。根据以上的实际编码用的基础校验矩阵Hb’和编码扩展因子z’=434对待编码数据序列(1份3392比特的待编码数据序列)进行编码,获得1份长度都为6784比特的LDPC码块。调制并发送LDPC编码块。
可选地,在本发明实施例、可选实施例中,矩阵列数为nb,矩阵行数为mb,矩阵***列数为kb=nb-mb。
以上实施例仅用以说明本发明的技术方案而非对其进行限制,本领域的普通技术人员可以对本发明的技术方案进行修改或者等同替换,而不脱离本发明的精神和范围,本发明的保护范围应以权利要求为准。
实施例5
在本实施例中还提供了一种结构化LDPC码的数据处理方法。如以下所使用的,术语“方法”或“模块”等可以实现预定功能的软件和/或硬件的组合。尽管以下实施例所描述的方法较佳地以软件来实现,但是硬件,或者软件和硬件的组合的实现也是可能并被构想的。
根据本发明实施例的一种结构化LDPC码的数据处理方法,用于发送端,该方法包括以下步骤:
1、码块分割,将长度为CL的传输块进行码块分割成多份编码块;
2、依据码块分割后的编码块大小,获取结构化LDPC编码的编码块大小;
3、确定编码扩展因子z:所述编码块大小、基础校验矩阵的参数kb、正整数值p、基础校验矩阵;所述扩展因子z都是一个正整数值pl的n倍。更为具体的,所述正整数值pl是子集合Pset的一个元素,以及,所述正整数n的所有取值构成子集合nSet。其中,plmax是子集合Pset中的最大值,nmax是子集合nSet中的最大值,其中,Kmax≤kb×plmax×nmax≤1.2×Kmax,Kmax是大于1024的整数。
以及获取用于结构化LDPC编码的基础校验矩阵,所述基础校验矩阵包括以下参数:***列数kb,矩阵行数(或者校验列数)mb,矩阵总列数nb,其中,kb=nb-mb。以及基 础校验矩阵矩阵中的元素至少包括两种类型:1、指示全0方阵的元素,在本专利中用-1表示,也可用空值等表示或其他描述方式;2、指示单位阵的循环移位方阵的元素(即为非全0方阵),所述元素是大于等于0且小于扩展因子的整数,用于指示单位阵的循环移位的位数。所述基础校验矩阵也可以包括多边结构,所述多变结构是指基础校验矩阵中出现至少包括:同一行索引和列索引上有2个元素,用于指示2个循环移位特定位后的方阵的相加构成。
4、根据所述基础校验矩阵和所述编码扩展因子z对待编码数据序列进行编码,或者对待译码数据序列进行译码;所述待编码数据序列的比特数目为kb×z,所述待译码数据序列的长度为nb×z。
进一步地,所述的Kmax等于2000、2048、4000、4096、6000、6144、8000、8192、12000或者12288。
在此,更为具体的一个例子:
结构化LDPC码的数据处理方法中,扩展因子z的取值分别为{4 6 8 10 12 14 16 20 24 28 32 40 48 56 64 80 96 112 128 160 192 224 256 320 384 448 512 640 768 896 1024},以及LDPC码的基础校验矩阵(对应最大扩展因子为1024)为:
Figure PCTCN2016104744-appb-000037
根据以上所述的扩展因子z的取值,可以知道,扩展因子z等于一个正整数值pl的n倍,所述正整数值pl是子集合Pset的一个元素,以及,所述正整数n的所有取值构成子集合nSet,所述Pset等于{2 4 8 16 32 64 128},所述nSet等于{2 3 5 6 7 8};在本实例中,Kmax等于8000。而所述的子集合Pset中的最大值为plmax=128,所述的子集合nSet中的最大值为nmax=8,此时可以发现:kb×plmax×nmax=8×128×8=8192,可以发现满足:Kmax≤kb×plmax×nmax≤1.2×Kmax。
根据以上所述的编码或者译码方法,若码块分割后获得编码块大小等于1024比特,则可以知道结构化LDPC编码的编码块大小为CBS=1024,从扩展因子集合中选择大于或者等于CBS/kb=1024/8=256的最小值作为结构化LDPC码的编码扩展因子,此时可以知道扩展因子为256,根据实施例5所述的对基础校验矩阵的进行修正,获得扩展因子为256的编码基础校验矩阵,这里不再赘述。根据所述获得的扩展因子和编码基础校验矩阵,可以对长度为1024比特的待编码数据序列进行编码,码率为1/3的话,获得长度为3072比 特的LDPC码字;对于接收端,可以根据所述获得的扩展因子和编码基础校验矩阵,对长度为3072的待译码数据序列进行译码,进而可以获得长度为1024比特的译码数据,将所***块的译码数据合并,即可获得发送端发送的传输块的原始数据。
可以采用与实施例3所述的译码器硬件实现,有利于实现LDPC码支持灵活码长和码率的设计。
实施例6
在本实施例中还提供了一种结构化LDPC码的数据处理方法。如以下所使用的,术语“方法”或“模块”等可以实现预定功能的软件和/或硬件的组合。尽管以下实施例所描述的方法较佳地以软件来实现,但是硬件,或者软件和硬件的组合的实现也是可能并被构想的。
根据本发明实施例的一种结构化LDPC码的数据处理方法,用于发送端,该方法包括以下步骤:
1、码块分割,将长度为CL的传输块进行码块分割成多份编码块;
2、依据码块分割后的编码块大小,获取结构化LDPC编码的编码块大小;
3、确定编码扩展因子z:所述编码块大小、基础校验矩阵的参数kb、正整数值p、基础校验矩阵;所述扩展因子z都是一个正整数值pl的n倍。更为具体的,所述正整数值pl是子集合Pset的一个元素,以及,所述正整数n的所有取值构成子集合nSet。其中,plmax是子集合Pset中的最大值,nmax是子集合nSet中的最大值,其中,Kmax≤kb×plmax×nmax≤1.2×Kmax,Kmax是大于1024的整数。
以及获取用于结构化LDPC编码的基础校验矩阵,所述基础校验矩阵包括以下参数:***列数kb,矩阵行数(或者校验列数)mb,矩阵总列数nb,其中,kb=nb-mb。以及基础校验矩阵矩阵中的元素至少包括两种类型:1、指示全0方阵的元素,在本专利中用-1表示,也可用空值等表示或其他描述方式;2、指示单位阵的循环移位方阵的元素(即为非全0方阵),所述元素是大于等于0且小于扩展因子的整数,用于指示单位阵的循环移位的位数。所述基础校验矩阵也可以包括多边结构,所述多变结构是指基础校验矩阵中出现至少包括:同一行索引和列索引上有2个元素,用于指示2个循环移位特定位后的方阵的相加构成。
4、根据所述基础校验矩阵和所述编码扩展因子z对待编码数据序列进行编码,或者对待译码数据序列进行译码;所述待编码数据序列的比特数目为kb×z,所述待译码数据序列的长度为nb×z。
进一步地,所述的Kmax等于2000、2048、4000、4096、6000、6144、8000、8192、12000或者12288。
在此,更为具体的一个例子:
结构化LDPC码的数据处理方法中,扩展因子z的取值分别为{4 6 8 10 12 14 16 20 24 28 32 40 48 56 64 80 96 112 128 160 192 224 256 320 384 448 512 640 768 896 1024},以及LDPC码的基础校验矩阵(对应最大扩展因子为1024)为:
Figure PCTCN2016104744-appb-000038
根据以上所述的扩展因子z的取值,可以知道,扩展因子z等于一个正整数值pl的n倍,所述正整数值pl是子集合Pset的一个元素,以及,所述正整数n的所有取值构成子集合nSet,所述Pset等于2的正整数i次幂,所述正整数i等于{1 2 3 4 5 6 7},即Pset等于{2 4 8 16 32 64 128},所述nSet等于{2 3 5 6 7 8},从而可以获得上述的扩展因子的取值集合,可以发现其有较多的正整数因子,进而可以使得译码器可以做得更为友好,即可以采用更多的译码并行度,以实现不同场景下的吞吐量要求,如果需要搞吞吐量,则可以使用更大译码并行度,而如果需要吞吐量较低,则可以采用小一点的译码并行度,所述译码并行度一般都是扩展因子的正整数因子,而如果译码并行度不等于扩展因子的正整数因子的话,那么硬件实现起来就会非常复杂度;在本实例中,Kmax等于8000。而所述的子集合Pset中的最大值为plmax=128,所述的子集合nSet中的最大值为nmax=8,此时可以发现:kb×plmax×nmax=8×128×8=8192,可以发现满足:Kmax≤kb×plmax×nmax≤1.2×Kmax。
以上所述的基础矩阵具有特性:传输过程中,在编码码率R高于母码R0时,对应基础矩阵的***列中的q列的q*Z比特不传输,所述对应不传输的对应基础矩阵的q列所构成mb行*q列的子矩阵中,所述子矩阵中的任意2列之间的列重的差值不大于1,所述的列重是指:对应列中指示单位阵的循环移位方阵的元素的个数;或者所述子矩阵中的任意2列中用于指示全0方阵的元素个数的差值不大于1,所述用于指示全0方阵的元素在本实施例中用“-1”表示,所述用于指示单位阵的循环移位方阵的元素在本实施例中用0~Z-1的1个整数表示。本实施例中q=2。
根据以上所述的编码或者译码方法,若码块分割后获得编码块大小等于1024比特,则可以知道结构化LDPC编码的编码块大小为CBS=1024,从扩展因子集合中选择大于或者等于CBS/kb=1024/8=256的最小值作为结构化LDPC码的编码扩展因子,此时可以知道扩展因子为256,根据实施例5所述的对基础校验矩阵的进行修正,获得扩展因子为256 的编码基础校验矩阵,这里不再赘述。根据所述获得的扩展因子和编码基础校验矩阵,可以对长度为1024比特的待编码数据序列进行编码,码率为1/3的话,获得长度为3072比特的LDPC码字;对于接收端,可以根据所述获得的扩展因子和编码基础校验矩阵,对长度为3072的待译码数据序列进行译码,进而可以获得长度为1024比特的译码数据,将所***块的译码数据合并,即可获得发送端发送的传输块的原始数据。
可以采用与实施例3所述的译码器硬件实现,有利于实现LDPC码支持灵活码长和码率的设计。
实施例7
通过以上的实施方式的描述,本领域的技术人员可以清楚地了解到根据上述实施例的方法可借助软件加必需的通用硬件平台的方式来实现,当然也可以通过硬件,但很多情况下前者是更佳的实施方式。基于这样的理解,本发明的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来,该计算机软件产品存储在一个存储介质(如ROM/RAM、磁碟、光盘)中,包括若干指令用以使得一台终端设备(可以是手机,计算机,服务器,或者网络设备等)执行本发明各个实施例的方法。
本发明的实施例还提供了一种存储介质。可选地,在本实施例中,上述存储介质可以被设置为存储用于执行以下步骤的程序代码:
S1,获取结构化LDPC编码的编码块大小;
S2,至少根据以下参数之一确定编码扩展因子z:编码块大小、基础校验矩阵的参数kb、正整数值p、mb行和nb列的基础校验矩阵;
S3,根据基础校验矩阵和编码扩展因子对待编码数据序列进行编码或者对待译码数据序列进行译码;其中,kb=nb-mb,kb、p、mb、z和nb均是大于1的整数。
可选地,在本实施例中,上述存储介质可以包括但不限于:U盘、只读存储器(ROM,Read-Only Memory)、随机存取存储器(RAM,Random Access Memory)、移动硬盘、磁碟或者光盘等各种可以存储程序代码的介质。
可选地,在本实施例中,处理器根据存储介质中已存储的程序代码执行上述实施例记载的方法步骤。
可选地,本实施例中的具体示例可以参考上述实施例及可选实施方式中所描述的示例,本实施例在此不再赘述。
显然,本领域的技术人员应该明白,上述的本发明的各模块或各步骤可以用通用的计算装置来实现,它们可以集中在单个的计算装置上,或者分布在多个计算装置所组成的网 络上,可选地,它们可以用计算装置可执行的程序代码来实现,从而,可以将它们存储在存储装置中由计算装置来执行,并且在某些情况下,可以以不同于此处的顺序执行所示出或描述的步骤,或者将它们分别制作成各个集成电路模块,或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。这样,本发明不限制于任何特定的硬件和软件结合。
以上所述仅为本发明的可选实施例而已,并不用于限制本发明,对于本领域的技术人员来说,本发明可以有各种更改和变化。凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。
工业实用性
本发明适用于通信领域,用以实现提高LDPC编译码数据处理的灵活度,从而解决相关技术中LDPC编译码的数据处理灵活度低的问题。

Claims (72)

  1. 一种结构化LDPC码的数据处理方法,包括:
    获取结构化LDPC编码的编码块大小;
    至少根据以下参数之一确定编码扩展因子z:所述编码块大小、基础校验矩阵的参数kb、正整数值p、mb行和nb列的基础校验矩阵;
    根据所述基础校验矩阵和所述编码扩展因子对待编码数据序列进行编码或者对待译码数据序列进行译码;
    其中,kb=nb-mb,kb、p、mb、z和nb均是大于1的整数。
  2. 根据权利要求1所述的方法,其中,至少根据所述编码块大小CBS、所述基础校验矩阵的参数kb和所述正整数值p确定所述编码扩展因子包括:
    通过公式
    Figure PCTCN2016104744-appb-100001
    确定所述编码扩展因子,其中,
    Figure PCTCN2016104744-appb-100002
    表示向上取整。
  3. 根据权利要求1所述的方法,其中,获取所述结构化LDPC编码的所述编码块大小包括:所述编码块大小等于基础校验矩阵的参数kb与一组升序自然数中的一个元素相乘所获得的数值。
  4. 根据权利要求3所述的方法,其中,所述一组升序自然数中包括多个分组,其中,所述多个分组中的分组内相邻元素的第一增加值相等。
  5. 根据权利要求4所述的方法,其中,所述一组升序自然数中的第i个分组的所述第一增加值小于第i+1个分组的所述第一增加值,其中,所述i为正整数。
  6. 根据权利要求1所述的方法,其中,根据所述编码块大小确定所述编码扩展因子包括:
    所述编码块大小为一组编码块大小中的一个元素值,所述一组编码块大小为升序的第一自然数组;
    所述编码扩展因子为一组编码扩展因子中的一个元素值,所述一组编码扩展因子为升序的第二自然数组。
  7. 根据权利要求6所述的方法,其中,所述一组编码块大小中包括连续的a个元素,其中,在所述连续的a个元素的首元素值大于z(j)×kb,且尾元素值小于或者等于z(j+1)×kb的情况下,所述连续的a个元素对应的编码扩展因子为z(j+1),所述a为正整数,所述z(j)为所述一组编码扩展因子中的第j个元素值,所述j为正整数,所述kb是基础校验矩阵的参数。
  8. 根据权利要求7所述的方法,其中,在获取的所述编码块大小为所述连续的a个元素中的一个元素的情况下,所述编码扩展因子为z(j+1)。
  9. 根据权利要求6所述的方法,其中,在所述编码块大小与所述基础校验矩阵的参数kb的比值大于z(j)且小于或者等于z(j+1)的情况下,所述编码扩展因子被确定为z(j+1),其中,所述z(j)为所述一组编码扩展因子中的第j个元素值,j为大于或者等于0的整数。
  10. 根据权利要求6所述的方法,其中,所述一组编码扩展因子中包括多个分组,其中,所述多个分组的分组内相邻元素的第二增加值相等,所述多个分组中的第h个分组的所述第二增加值小于第h+1个分组的所述第二增加值,所述h为正整数。
  11. 根据权利要求6所述的方法,其中,所述一组编码扩展因子中的所有大于所述正整数值p的元素值都是所述正整数值p的正整数n倍。
  12. 根据权利要求6所述的方法,其中,所述一组编码块大小至少包括:所述基础校验矩阵的参数kb与所述一组编码扩展因子相乘得到的乘积值,以及全部所述乘积值之间间隔为B的整数值,其中,所述B为正整数。
  13. 根据权利要求1所述的方法,其中,根据所述基础校验矩阵和所述编码扩展因子对待编码数据序列进行编码之前,所述方法还包括:
    对第一数据序列进行比特填充,其中,对所述第一数据序列进行比特填充包括:将所述第一数据序列分成多个子数据序列,对所述多个子数据序列分别进行比特填充,所有填充比特后的子数据序列构成所述待编码数据序列。
  14. 根据权利要求1所述的方法,其中,根据基础校验矩阵和所述编码扩展因子对待编码数据序列进行编码之前,所述方法还包括:
    对第二数据序列进行比特填充,其中,对所述第二数据序列进行比特填充包括:将所述第二数据序列分成所述kb个比特数目小于或者等于z的子数据序列,对每个子数据序列添加填充比特使得每组子数据序列的比特数目达到z,所有填充比特后的子数据序列构成所述待编码数据序列,其中,kb是础校验矩阵的参数,z是所述编码扩展因子。
  15. 根据权利要求13或者14所述的方法,其中,在对所述第一数据序列进行比特填充或者对所述第二数据序列进行比特填充之前,所述方法还包括:
    对第三数据序列添加L比特的循环冗余校验CRC序列获得所述第一数据序列或者所述第二数据序列,其中,所述L是大于或者等于0的整数。
  16. 根据权利要求2、3、7、12或者14所述的方法,其中,所述基础校验矩阵的参数kb为所述基础校验矩阵的列数和所述基础校验矩阵的行数的差值,kb是大于等于4且小于等于64的一个整数。
  17. 根据权利要求1或者2所述的方法,其中,所述正整数值p是LDPC译码并行度。
  18. 根据权利要求17所述的方法,其中,所述正整数值p是一个固定正整数,所述LDPC译码并行度p包括:所述正整数值p为2的正整数次幂或者所述正整数值p为2的正整数次幂再乘以一个素数。
  19. 根据权利要求11所述的方法,其中,所述正整数值p是子集合Pset的一个元素,其中,所述子集合Pset是Pmax的所有正整数因子所构成集合中的一个子集,Pmax是大于3且小于或者等于1024的一个整数。
  20. 根据权利要求11所述的方法,其中,所述正整数n的所有取值构成子集合nSet,其中,所述nSet是正整数集合Ns中长度为F的一个子集,所述正整数集合Ns={1、2、3、…、M},M是大于1的整数。
  21. 根据权利要求20所述的方法,其中,所述子集合nSet包括以下之一:所述正整数集合Ns中的前F个元素构成的子集合、所述正整数集合Ns中的后F个元素构成的子集合、所述正整数集合Ns中的F个素数构成的子集合、所述正整数集合Ns中的F个奇数构成的子集合、所述正整数集合Ns中的F个偶数构成的子集合,F是小于M的正整数。
  22. 根据权利要求1所述的方法,其中,所述编码扩展因子包括:所述编码扩展因子等于2的正整数次幂然后减1,或者所述编码扩展因子等于2的正整数次幂再乘以一个素数;
    该素数包括以下之一:3、5、7、11、13、17、19、23、29。
  23. 根据权利要求22所述的方法,其中,所述编码扩展因子等于2的正整数次幂再乘以一个素数,该素数包括3和5。
  24. 根据权利要求22所述的方法,其中,所述编码扩展因子等于2的正整数次幂再乘以一个素数,该素数包括5和7。
  25. 根据权利要求22所述的方法,其中,所述编码扩展因子等于2的正整数次幂再乘以一个素数,该素数包括3、5和7。
  26. 根据权利要求22所述的方法,其中,所述编码扩展因子包括以下之一:7、15、 31、63、127、255、511、1023、2047、4095。
  27. 根据权利要求1所述的方法,其中,在至少根据以下参数之一确定所述编码扩展因子z:所述编码块大小、所述基础校验矩阵的参数kb、所述正整数值p、所述基础校验矩阵之后,所述方法还包括:至少存储所述基础校验矩阵。
  28. 根据权利要求1所述的方法,其中,在对所述待编码数据序列进行编码之前,还包括:在待编码数据序列中填充长度为k’比特的哑元比特获得长度为kb*z比特的待编码数据序列,其中,k’与kb*z的比值小于或等于1/4,k’是大于或者等于0的整数,所述kb是所述基础校验矩阵的***列数,所述z是编码使用的扩展因子大小,kb是大于1的整数,z是大于0的整数。
  29. 根据权利要求1所述的方法,其中,所述扩展因子z均为一个正整数值pl的n倍。
  30. 根据权利要求29所述的方法,其中,所述正整数值pl是子集合Pset的一个元素,其中,所述子集合Pset是Pmax的所有正整数因子所构成集合中的一个子集,n是一个自然数,Pmax是大于等于4的整数。
  31. 根据权利要求29所述的方法,其中,所述正整数n的所有取值构成子集合nSet,其中,所述nSet是正整数集合Ns中长度为F的一个子集,所述正整数集合Ns={1、2、3、…、M},M是大于1的整数。
  32. 根据权利要求29所述的方法,其中,所述正整数值pl是子集合Pset的一个元素,所述正整数n的所有取值构成子集合nSet,plmax是子集合Pset中的最大值,nmax是子集合nSet中的最大值,其中,Kmax≤kb×plmax×nmax≤1.2×Kmax,Kmax是大于1024的整数。
  33. 根据权利要求32所述的方法,其中,所述的Kmax等于2000、2048、4000、4096、6000、6144、8000、8192、12000或者12288。
  34. 根据权利要求29所述的方法,其中,所述基础校验矩阵中指示非全0方阵的任何hbij元素的满足如下条件:mod(hbij,(Pmax/pl))=0,其中,i=0,1,2..,mb-1,j=0,1,…,nb-1,Pmax是大于等于4的整数。
  35. 根据权利要求29所述的方法,其中,所述基础校验矩阵中指示非全0方阵的任何hbij元素的满足如下条件:mod(hbij,(Pmax/pl))=A,其中i和j分别是所述基础校验矩阵中行索引i和列索引j的元素以及所述hbij指示非全0方阵,A是小于pl且大于或者等于0的固定整数,Pmax是大于等于4的整数。
  36. 根据权利要求1至35中任一项所述的方法,其中,基础校验矩阵的参数kb为基础校验矩阵***列数。
  37. 一种结构化LDPC码的数据处理装置,包括:
    获取模块,设置为获取结构化LDPC编码的编码块大小;
    确定模块,设置为至少根据以下参数之一确定编码扩展因子z:所述编码块大小、基础校验矩阵的参数kb、正整数值p、mb行和nb列的基础校验矩阵;
    处理模块,设置为根据所述基础校验矩阵和所述编码扩展因子对待编码数据序列进行编码或者对待译码数据序列进行译码;
    其中,kb=nb-mb,kb、p、mb、z和nb均是大于1的整数。
  38. 根据权利要求37所述的装置,其中,所述确定模块设置为:
    通过公式
    Figure PCTCN2016104744-appb-100003
    确定所述编码扩展因子,其中,所述CBS为所述编码块大小,
    Figure PCTCN2016104744-appb-100004
    表示向上取整。
  39. 根据权利要求37所述的装置,其中,所述获取模块设置为:所述编码块大小等于基础校验矩阵的参数kb与一组升序自然数中的一个元素相乘所获得的数值。
  40. 根据权利要求39所述的装置,其中,所述一组升序自然数中包括多个分组,其中,所述多个分组中的分组内相邻元素的第一增加值相等。
  41. 根据权利要求40所述的装置,其中,所述一组升序自然数中的第i个分组的所述第一增加值小于第i+1个分组的所述第一增加值,其中,所述i为正整数。
  42. 根据权利要求37所述的装置,其中,所述确定模块设置为:
    所述编码块大小为一组编码块大小中的一个元素值,所述一组编码块大小为升序的第一自然数组;
    所述编码扩展因子为一组编码扩展因子中的一个元素值,所述一组编码扩展因子为升序的第二自然数组。
  43. 根据权利要求42所述的装置,其中,所述一组编码块大小中包括连续的a个元素,其中,在所述连续的a个元素的首元素值大于z(j)×kb,且尾元素值小于或者等于z(j+1)×kb的情况下,所述连续的a个元素对应的编码扩展因子为z(j+1),所述a为正整数,所述z(j)为所述一组编码扩展因子中的第j个元素值,所述j为正整数,所述kb是基础校验矩阵的参数。
  44. 根据权利要求43所述的装置,其中,在获取的所述编码块大小为所述连续的a个元素中的一个元素的情况下,所述编码扩展因子为z(j+1)。
  45. 根据权利要求42所述的装置,其中,在所述编码块大小与所述基础校验矩阵的参数kb的比值大于z(j)且小于或者等于z(j+1)的情况下,所述编码扩展因子被确定为z(j+1),其中,所述z(j)为所述一组编码扩展因子中的第j个元素值。
  46. 根据权利要求42所述的装置,其中,所述一组编码扩展因子中包括多个分组,其中,所述多个分组的分组内相邻元素的第二增加值相等,所述多个分组中的第h个分组的所述第二增加值小于第h+1个分组的所述第二增加值,所述h为正整数。
  47. 根据权利要求42所述的装置,其中,所述一组编码扩展因子中的所有大于所述正整数值p的元素值都是所述正整数值p的正整数n倍。
  48. 根据权利要求42所述的装置,其中,所述一组编码块大小至少包括:所述基础校验矩阵的参数kb与所述一组编码扩展因子相乘得到的乘积值,以及全部所述乘积值之间间隔为B的整数值,其中,所述B为正整数。
  49. 根据权利要求37所述的装置,其中,所述装置还包括:
    第一比特填充模块,设置为对第一数据序列进行比特填充,其中,对所述第一数据序列进行比特填充包括:将所述第一数据序列分成多个子数据序列,对所述多个子数据序列分别进行比特填充,所有填充比特后的子数据序列构成所述待编码数据序列。
  50. 根据权利要求37所述的装置,其中,所述装置还包括:
    第二比特填充模块,设置为对第二数据序列进行比特填充,其中,对所述第二数据序列进行比特填充包括:将所述第二数据序列分成所述kb个比特数目小于或者等于z的子数据序列,对每个子数据序列添加填充比特使得每组子数据序列的比特数目达到z,所有填充比特后的子数据序列构成所述待编码数据序列,其中,kb是础校验矩阵的参数,z是所述编码扩展因子。
  51. 根据权利要求49或者50所述的装置,其中,所述装置还包括:
    添加模块,设置为对第三数据序列添加L比特的循环冗余校验CRC序列获得所述第一数据序列或者所述第二数据序列,其中,所述L是大于或者等于0的整数。
  52. 根据权利要求38、39、43、48或者50所述的装置,其中,所述基础校验矩阵的参数kb为所述编码基础校验矩阵的列数和所述编码基础校验矩阵的行数的差值,kb是大 于等于4且小于等于64的一个整数。
  53. 根据权利要求37或者38所述的装置,其中,所述正整数值p是LDPC译码并行度。
  54. 根据权利要求53所述的装置,其中,所述正整数值p是一个固定正整数,所述LDPC译码并行度p包括:所述正整数值p为2的正整数次幂或者所述正整数值p为2的正整数次幂再乘以一个素数。
  55. 根据权利要求47所述的装置,其中,所述正整数值p是子集合P的一个元素,其中,所述子集合P是Pmax的所有正整数因子所构成集合中的一个子集,Pmax是大于3且小于或者等于1024的一个整数。
  56. 根据权利要求47所述的装置,其中,所述正整数n的所有取值构成子集合nSet,其中,所述nSet是正整数集合Ns中长度为F的一个子集,所述正整数集合Ns={1、2、3、…、M},M是大于1的整数。
  57. 根据权利要求56所述的装置,其中,所述子集合nSet包括以下之一:所述正整数集合Ns中的前F个元素构成的子集合、所述正整数集合Ns中的后F个元素构成的子集合、所述正整数集合Ns中的F个素数构成的子集合、所述正整数集合Ns中的F个奇数构成的子集合、所述正整数集合Ns中的F个偶数构成的子集合,F是小于M的正整数。
  58. 根据权利要求37所述的装置,其中,所述编码扩展因子包括:所述编码扩展因子等于2的正整数次幂然后减1,或者所述编码扩展因子等于2的正整数次幂再乘以一个素数;
    所述的素数包括以下之一:3、5、7、11、13、17、19、23和29。
  59. 根据权利要求58所述的装置,其中,所述编码扩展因子等于2的正整数次幂再乘以一个素数,该素数包括3和5。
  60. 根据权利要求58所述的装置,其中,所述编码扩展因子等于2的正整数次幂再乘以一个素数,该素数包括5和7。
  61. 根据权利要求58所述的装置,其中,所述编码扩展因子等于2的正整数次幂再乘以一个素数,该素数包括3、5和7。
  62. 根据权利要求58所述的装置,其中,所述编码扩展因子包括以下之一:7、15、31、63、127、255、511、1023、2047、4095。
  63. 根据权利要求37所述的装置,其中,所述装置还包括:存储模块,设置为至少存储所述基础校验矩阵。
  64. 根据权利要求37所述的装置,其中,所述装置还设置为:在对所述待编码数据序列进行编码之前,在待编码数据序列中填充长度为k’比特的哑元比特获得长度为kb*z比特的待编码数据序列,其中,k’与kb*z的比值小于或等于1/4,k’是大于或者等于0的整数,所述kb是所述基础校验矩阵的***列数,所述z是编码使用的扩展因子大小,kb是大于1的整数,z是大于0的整数。
  65. 根据权利要求37所述的装置,其中,所述扩展因子z均为一个正整数值pl的n倍。
  66. 根据权利要求65所述的装置,其中,所述正整数值pl是子集合Pset的一个元素,其中,所述子集合Pset是Pmax的所有正整数因子所构成集合中的一个子集,n是一个自然数,Pmax是大于等于4的整数。
  67. 根据权利要求65所述的装置,其中,所述正整数n的所有取值构成子集合nSet,其中,所述nSet是正整数集合Ns中长度为F的一个子集,所述正整数集合Ns={1、2、3、…、M},M是大于1的整数。
  68. 根据权利要求65所述的装置,其中,所述正整数值pl是子集合Pset的一个元素,所述正整数n的所有取值构成子集合nSet,plmax是子集合Pset中的最大值,nmax是子集合nSet中的最大值,其中,Kmax≤kb×plmax×nmax≤1.2×Kmax,Kmax是大于1024的整数。
  69. 根据权利要求68所述的装置,其中,所述的Kmax等于2000、2048、4000、4096、6000、6144、8000、8192、12000或者12288。
  70. 根据权利要求65所述的装置,其中,所述基础校验矩阵中指示非全0方阵的任何hbij元素的满足如下条件:mod(hbij,(Pmax/pl))=0,其中,i=0,1,2..,mb-1,j=0,1,…,nb-1,Pmax是大于等于4的整数。
  71. 根据权利要求65所述的装置,其中,所述基础校验矩阵中指示非全0方阵的任何hbij元素的满足如下条件:mod(hbij,(Pmax/pl))=A,其中i和j分别是所述基础校验矩阵中行索引i和列索引j的元素以及所述hbij指示非全0方阵,A是小于Pi且大于或者等于0的固定整数,Pmax是大于等于4的整数。
  72. 根据权利要求37至71中任一项所述的装置,其中,基础校验矩阵的参数kb为基础校验矩阵***列数。
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