WO2017179748A1 - Method for manufacturing printed circuit board and printed circuit board manufactured by same method - Google Patents

Method for manufacturing printed circuit board and printed circuit board manufactured by same method Download PDF

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Publication number
WO2017179748A1
WO2017179748A1 PCT/KR2016/003920 KR2016003920W WO2017179748A1 WO 2017179748 A1 WO2017179748 A1 WO 2017179748A1 KR 2016003920 W KR2016003920 W KR 2016003920W WO 2017179748 A1 WO2017179748 A1 WO 2017179748A1
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WO
WIPO (PCT)
Prior art keywords
plating layer
circuit
forming
via hole
pir
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PCT/KR2016/003920
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French (fr)
Korean (ko)
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WO2017179748A9 (en
Inventor
손경애
강성원
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손경애
강성원
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Priority to PCT/KR2016/003920 priority Critical patent/WO2017179748A1/en
Publication of WO2017179748A1 publication Critical patent/WO2017179748A1/en
Publication of WO2017179748A9 publication Critical patent/WO2017179748A9/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits

Definitions

  • the present invention relates to a method of manufacturing a printed circuit board and a printed circuit board manufactured by the method.
  • the circuit on the outer layer surface of the multilayer board is connected through via holes, and additionally, there is no need to connect lead wires for connecting circuits on both sides and increase the integration efficiency of the miniaturized circuit.
  • the present invention relates to a method for manufacturing an outer layer printed circuit board of a double-sided or multi-layered substrate and an outer layer printed circuit board of a double-sided or multi-layered substrate manufactured by the method.
  • printed circuit boards are the most basic components in many fields of electrical and electronic products that are currently manufactured, and are widely used in household appliances such as TVs, VTRs, microwave ovens, desk computers, notebook PCs, and portable electronic products such as smartphones. Is being applied.
  • miniaturization of a printed circuit board circuit wiring refers to a case of 100 pitches or less (circuit width: 50, circuit spacing: 50) or less.
  • a fine pattern may be 50 pitches or less.
  • the reason why the fine circuit pitch is lowered is that the functions of smartphones, tablet PCs and wearable electronic devices such as mobile devices have recently been improved, and memory or CPU processing capacity has increased from 16 Giga Byte, 32 Giga Byte to 64 Giga Byte, Even if it is improved to 128 Giga Byte or more, more circuits must be wired in the same number of floors in order to suppress the cost increase of the product.
  • the present invention is to solve the problems of the prior art, the present invention to increase the degree of integration in the manufacturing of a printed circuit board having a miniaturization circuit on the outer layer surface of the double-sided or multi-layered substrate electrically through the via hole through the circuit on both sides of the printed circuit board It is an object of the present invention to provide a method for manufacturing a printed circuit board, and a printed circuit board manufactured by the method, which do not need to connect circuits on both sides by separate lead wires.
  • the present invention to solve this technical problem
  • PIR pattern ink resist
  • the circuits on both sides of the printed circuit board are electrically connected to each other through via holes. It is possible to simplify the structure of the printed circuit board manufactured without the need for connecting with lead wires.
  • the miniaturization circuit can fundamentally block the possibility of a short circuit that may occur when connecting the lead wire, thereby minimizing the miniaturization circuit on the printed circuit board. It is advantageous for the production of printed circuit boards to be formed.
  • FIGS. 1A to 1O are cross-sectional views illustrating a method of manufacturing a printed circuit board according to an exemplary embodiment of the present invention.
  • FIGS. 2A through 2P are cross-sectional views illustrating a method of manufacturing a printed circuit board according to another exemplary embodiment of the present invention.
  • the same reference numerals in particular, the tens and ones digits, or the same digits, tens, ones, and alphabets refer to members having the same or similar functions, and unless otherwise specified, each member in the figures The member referred to by the reference numeral may be regarded as a member conforming to these criteria.
  • FIGS. 1A to 1O are cross-sectional views illustrating a method of manufacturing a printed circuit board according to an exemplary embodiment of the present invention, and particularly, a cross-sectional view illustrating a method of manufacturing an outer layer printed circuit board of a double-sided or multilayer board.
  • a copper foil laminated plate 100 having a copper foil 104 coated on both surfaces of a substrate insulator 102 or an outer layer surface of a multilayer substrate is illustrated.
  • the copper foil laminated plate 100 is drilled to form a through hole 106 for forming a via hole.
  • the first plating layer 108 may be formed by electroless plating so that both surfaces of the copper foil laminate 100 may be electrically conductive. At this time, the first plating layer 108 is preferably formed to a thickness of 0.5 ⁇ 1.0um.
  • the electroless plating may be used as other metal materials such as copper, nickel, and carbon series.
  • dry films 110 and 112 including photoresist are adhered to both surfaces of the copper clad laminate 100 on which the first plating layer 108 is formed, and as shown in FIG. 1E, the dry films 110,
  • the etching resist 112a is formed on the entire surface of the etching resist 110a and the other surface for forming the micronization circuit 100a and the via hole circuit 100b on one surface through the exposure and development process by the photo process.
  • the micronization circuit 100a and the via hole circuit 100b formed through the exposure and development processes are formed on one surface, and the micronization circuit 100a and the via hole circuit 100b are not formed because the entire surface is exposed and developed on the other surface. Does not have features.
  • a liquid photoresist is applied to expose and develop or through a fine ink circuit (PIR) printing, thereby miniaturizing the circuit 100a and the via hole circuit ( It is also possible to form the etching resists 110a and 112a for forming 100b).
  • PIR fine ink circuit
  • the copper foil 104 and the first plating layer other than the etching resist 110a for forming the miniaturization circuit 100a and the via hole circuit 100b of one surface of the copper foil laminated plate 100 formed by a photolithography process ( 108 is etched, and the dry films used as the etching resists 110a and 112a are peeled off to form the micronization circuit 100a and the via hole circuit 100b on one surface, and the other surface is not etched, so the micronization circuit 100a is removed.
  • the via hole circuit 100b is not formed and the copper foil 104 and the first plating layer 108 remain in a ground state.
  • the dry film 114 including the photosensitizer may be re-adhered to one or both surfaces of the copper-clad laminate 100 having the micronization circuit 100a and the via hole circuit 100b formed on one surface thereof, and illustrated in FIG. 1H.
  • the photoresist is exposed and developed to form openings 114a for plating the via hole circuit 100b on one or both surfaces.
  • a liquid sensitizer is applied to expose and develop or to form a plating layer in the via hole circuit 100b through PIR (Pattern Ink Resist) printing. It is also possible to form openings for the same.
  • the dry film, the liquid photoresist, or the PIR ink serves as a plating resist during electroplating in FIG. 1I.
  • the second plating layer 116 is formed by electroplating the opening 114a for the via hole circuit 100b.
  • the second plating layer 116 is preferably formed to a thickness of 10 to 20um, it may be formed to a thickness of more or less.
  • the reason for forming the second plating layer 116 in the opening 114a for the via hole circuit 100b is that the thickness of the first plating layer performed in FIG. 1C is thin to ensure reliability of electrical conductivity in the via hole. Because you can't.
  • the electroplating may be used as other metal materials such as copper, nickel, and silver.
  • the dry film 114 used as the plating resist is removed through a predetermined peeling process to complete the micronization circuit 100a and the via hole circuit 100b on one surface or the copper foil 104 on the other surface.
  • the ground surface 100d including the first plating layer 108 and the second plating layer 116 is formed on the substrate, or the via hole land 100c is formed.
  • a) and b) of FIG. 1J are characterized in that the miniaturization circuit is wired on one surface and the miniaturization circuit is not wired on the other surface, and c) and d) are characterized in that the miniaturization circuit is wired on one surface and the other surface.
  • an etching resist for forming a miniaturization circuit 100a and a via hole circuit 100b may be formed by applying a liquid photoresist and exposing and developing or reprinting a pattern ink resist (PIR). It is also possible to form 118a and 120a.
  • the copper foil 104 and the first plating layer other than the etching resist 120a for forming the micronized circuit 100a and the via hole circuit 100b of the other surface formed by the photolithography process are formed on the copper foil laminated plate 100. 108), the second plating layer 116 is etched, or the copper foil 104 and the first plating layer 108 are etched, and then the dry films used as the etching resists 118a and 120a on both sides are peeled off to further refine the circuit on the other side. 100a and the via hole circuit 100b are completed.
  • the micronization circuit 100a and the via hole circuit 100b of the other surface are not etched.
  • a printing process or a PSR process is performed by selecting among polyimide-based, acryl-based, and epoxy-based insulating materials which are generally used to insulate the circuits or circuits on both surfaces of the etched surface, or polyimide-based
  • the insulating layer 130 is formed between circuits and circuits except for regions to be surface-treated by performing a lamination process by selecting among acrylic and epoxy insulating materials.
  • the method of applying the insulator may also include an insulator between the circuits or circuits by 3D printing or inkjet printing.
  • nickel plating, gold plating, or nickel and gold may be plated together by electroless or electrolytic plating on a region to be surface treated.
  • the metal layer 140 is formed.
  • the surface treatment may be performed by selecting the surface treatment with OSP (Organic Solderability Preservative) or silver plating instead of the nickel plating and gold plating.
  • OSP Organic Solderability Preservative
  • the metal layer 140 is preferably formed with a thickness of 3 to 7um when forming a layer by nickel plating, and when forming a layer with gold plating, it is preferable to form a thickness of 0.03 to 0.05um, It can also be formed in thicknesses above and below.
  • the process of FIGS. 1N and 1O may be performed by changing the process order.
  • an outer layer printed circuit board of a double-sided or multi-layered substrate is completed through a post-treatment process.
  • 2A to 2P are cross-sectional views illustrating a method of manufacturing a printed circuit board according to another exemplary embodiment, and are also cross-sectional views illustrating a method of manufacturing an outer layer printed circuit board of a double-sided or multilayer board.
  • a copper foil laminated plate 200 having a copper foil 204 coated on both surfaces of an insulator 202 or an outer layer surface of a multilayer substrate is illustrated.
  • the copper foil 204 of the copper-clad laminate 200 instead of the copper foil 204 of the copper-clad laminate 200, it is also possible to use other metal, such as aluminum, nickel (Ni), chromium.
  • other metal such as aluminum, nickel (Ni), chromium.
  • the copper foil laminated plate 200 is drilled to form a through hole 206 for forming a via hole.
  • the first plating layer 208 is formed by electroless plating so that both copper foil surfaces of the copper clad laminate 200 may be electrically connected to each other.
  • the first plating layer 208 is preferably formed to a thickness of 0.5 ⁇ 1.0um.
  • the electroless plating may be used as other metal materials such as copper, nickel, and carbon series.
  • a second plating layer 209 is formed on the first plating layer 208 through electrolytic plating.
  • the second plating layer 209 is preferably formed to a thickness of 5 to 10um, it may be formed to a thickness of more or less.
  • the electroplating may be used as other metal materials such as copper, nickel, and silver.
  • dry films 210 and 212 including photosensitive agents may be adhered to both surfaces of the copper-clad laminate 200 on which the second plating layer 209 is formed, and as shown in FIG.
  • the etching resists 212a are formed on the entire surface of the etching resist 210a and the other surface for forming the micronization circuit 200a and the via hole circuit 200b on one surface by exposing and developing the 210 and 212 using a photolithography process. .
  • a liquid photosensitive agent is coated to expose and develop or through a PIR (Pattern Ink Resist) printing, thereby miniaturizing the circuit 200a and the via hole circuit 200b. It is also possible to form etching resists 210a and 212a for formation.
  • the micronization circuit 200a and the via hole circuit 200b formed through the exposure and development are formed on one surface, and the micronizing circuit 200a and the via hole circuit 200b are not formed by exposing and developing the entire surface on the other surface. There is a characteristic.
  • the copper foil 204 and the first plating layer other than the etching resist 210a for forming the miniaturization circuit 200a and the via hole circuit 200b of one surface formed by the photolithography process are formed on the copper foil laminated plate 200.
  • the second plating layer 209 is etched and the dry films used as the etching resists 210a and 212a are peeled off to form the micronization circuit 200a and the via hole circuit 200b on one surface, and the other surface is not etched and micronized.
  • the circuit 200a or the via hole circuit 200b is not formed, and the copper foil 204, the first plating layer 208, and the second plating layer 209 remain in a ground state.
  • a dry film 214 including a photosensitive agent is re-adhered to one or both surfaces of the copper clad laminate 200 having the micronization circuit 200a and the via hole circuit 200b formed thereon, and illustrated in FIG. 2I.
  • exposure and development are performed by a photographic process to form openings 214a for the via hole circuit 200b on one or both surfaces.
  • the liquid sensitizer is applied to expose and develop the opening, or an opening 214a for forming a plating layer in the via hole circuit 200b through PIR (Pattern Ink Resist) printing. It is also possible to form).
  • PIR Plasma Ink Resist
  • the dry film, the liquid photoresist, or the PIR ink serves as a plating resist during electroplating in FIG. 2J.
  • a third plating layer 216 is formed by electroplating the opening 214a for the via hole circuit 200b.
  • the third plating layer 216 is preferably formed to a thickness of 5 to 10um, it may be formed to a thickness of more or less.
  • a) and b) of FIG. 2J are characterized in that the miniaturization circuit is wired on one surface and the miniaturization circuit is not wired on the other surface, and c) and d) are characterized in that the miniaturization circuit is wired on one surface and the other surface.
  • the electroplating may be used with various metal materials such as copper, nickel, and silver.
  • the dry film used as the plating resist 214 is removed through a predetermined peeling process to complete the micronization circuit 200a and the via hole circuit 200b on one surface or the copper foil 204 on the other surface.
  • the ground surface 200d including the first plating layer 208, the second plating layer 209, and the third plating layer 216 is formed on the via plate 200c, or the via hole land 200c is formed.
  • the photosensitive agent is dried on both surfaces of the copper foil laminated plate 200 on which one surface of the micronization circuit 200a and the via hole circuit 200b and the other surface of the ground surface 200d or the via hole land 200c are formed.
  • the films 218 and 220 are brought into close contact with each other, and the copper-clad laminate 200 is exposed and developed by a photolithography process as shown in FIG. 2M, and the etching resist for the micronization circuit 200a and the via hole circuit 200b of the other surface ( An etching resist 218a is formed on the entire surface of 220a) and one surface thereof.
  • the entire surface is exposed and developed so that the micronization circuit 200a and the via hole circuit 200b already formed on the one surface are not etched during etching. 218a).
  • a liquid photoresist is applied to expose and develop or through a pattern ink resist printing (PIR) to refine the micro circuit 200a and the via hole circuit 200b. It is also possible to form the etching resists 218a and 220a for formation.
  • PIR pattern ink resist printing
  • the copper foil 204 and the first plating layer other than the etching resist 220a may be formed to form the micronized circuit 200a and the via hole circuit 200b of the other surface formed by the photolithography process.
  • the dry film used as is peeled off to complete the micronization circuit 200a and the via hole circuit 200b of the other surface.
  • the insulating layer 230 forming process as shown in FIG. 2O and the metal layer 240 forming process as shown in FIG. 2P are sequentially performed.
  • a printing process or a PSR process may be performed by selecting among polyimide-based, acryl-based, and epoxy-based insulating materials which are generally used to insulate the circuits or circuits on both surfaces of the etched surface.
  • the insulating layer 230 is formed between the circuit and the circuit except for the region to be surface-treated by performing a lamination process by selecting among acrylic and epoxy insulating materials.
  • the method of applying the insulator may also include an insulator between the circuits or circuits by 3D printing or inkjet printing.
  • the surface treatment may be performed by selecting the surface treatment with OSP (Organic Solderability Preservative) or silver plating instead of the nickel plating and gold plating.
  • OSP Organic Solderability Preservative
  • the metal layer 240 is preferably formed with a thickness of 3 to 7um when the nickel plating layer is formed, and when formed with a gold plated layer, the metal layer 240 is preferably formed with a thickness of 0.03 to 0.05um. It can also be formed with the following thickness.
  • FIGS. 2O and 2P may be performed by changing the process order.
  • an outer layer printed circuit board of a double-sided or multilayer board is completed through a post-treatment process.

Abstract

The present invention provides a method for manufacturing a printed circuit board, and a printed circuit board manufactured by the method, without the need to connect circuits on both sides of the printed circuit board separately by electrically connecting the circuits on both sides of the printed circuit board through via holes, when the printed circuit board having a fine pattern on both sides or the outer surface of a multi-layer substrate is manufactured in order to increase the degree of integration. The method for manufacturing the printed circuit board comprises the steps of: (a) after a through-hole is formed to form a via hole by drilling a copper clad laminate having a copper foil coated on both sides of a substrate insulator or the outer surface of a multi-layer substrate, forming a first plating layer using electroless plating; (b) forming an etching resist for forming a fine pattern and a via hole circuit on one side of the copper clad laminate, and an etching resist entirely on the other side of the copper clad laminate by adhering a dry film comprising a photosensitizer onto both sides of the copper clad laminate having the first plating layer formed thereon or coating, exposing and developing a liquid photosensitizer or through a pattern ink resist (PIR) printing; (c) forming a fine pattern and a via hole circuit on the one side thereof by etching the copper foil and the first plating layer besides the etching resist formed on both sides of the copper clad laminate and stripping the dry film or the liquid photosensitizer or a PIR ink; (d) forming an opening of the dry film, the liquid photosensitizer or the PIR ink for the via hole circuit by re-adhering the dry film comprising the photosensitizer to the one side or both sides of the copper clad laminate or re-coating, exposing and developing the liquid photoresist, or through a pattern ink resist (PIR) re-printing; (e) after forming a second plating layer by performing electrolytic plating on the opening of the dry film, the liquid photosensitizer or the PIR ink, completing the fine pattern and the via hole circuit on the one side by stripping the dry film, the liquid photosensitizer or the PIR ink, or forming a ground plane made of the first plating layer and the second plating layer or forming a via hole land on the other side of the copper foil; (f) after re-adhering the dry film comprising the photosensitizer onto both sides of the copper clad laminate or re-coating the liquid photorsensitizer, forming an etching resist for the fine pattern and the via hole circuit on the other side thereof and an etching resist entirely on the one side thereof by exposing and developing the copper clad laminate, or through PIR re-printing; (g) after etching the copper foil, the first plating layer and the second plating layer besides the etching resist, or etching the copper foil and the first plating layer, completing the fine pattern and the via hole circuit on the other side by stripping the dry film or the liquid photosensitizer or the PIR ink used as the etching resist.

Description

인쇄회로기판의 제조방법 및 그 방법에 의해 제조된 인쇄회로기판Manufacturing method of printed circuit board and printed circuit board manufactured by the method
본 발명은 인쇄회로기판의 제조방법 및 그 방법에 의해 제조된 인쇄회로기판에 관한 것으로, 특히 양면 또는 다층기판의 외층면에 미세화 회로(Fine Pattern)를 형성하기 위해 인쇄회로기판의 제조시에 양면 또는 다층기판의 외층면의 회로가 비아홀(Via Hole)을 통해 연결하도록 하기 위한 것이며, 추가로 양면의 회로를 일일이 연결하기 위한 리드선(Lead Wire) 연결 작업이 필요 없고 미세화 회로의 집적 효율을 높일 수 있는 양면 또는 다층기판의 외층면 인쇄회로기판의 제조방법 및 그 방법에 의해 제조된 양면 또는 다층기판의 외층면 인쇄회로기판에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a printed circuit board and a printed circuit board manufactured by the method. Alternatively, the circuit on the outer layer surface of the multilayer board is connected through via holes, and additionally, there is no need to connect lead wires for connecting circuits on both sides and increase the integration efficiency of the miniaturized circuit. The present invention relates to a method for manufacturing an outer layer printed circuit board of a double-sided or multi-layered substrate and an outer layer printed circuit board of a double-sided or multi-layered substrate manufactured by the method.
일반적으로 인쇄회로기판은 현재 제조되고 있는 많은 분야의 전기, 전자제품에서 가장 기초가 되는 부품으로서, 생활 가전제품인 TV, VTR, 전자레인지, 데스크용 컴퓨터, 노트북 PC 및 휴대용 전자 제품인 스마트폰 등에 광범위하게 적용되고 있다.In general, printed circuit boards are the most basic components in many fields of electrical and electronic products that are currently manufactured, and are widely used in household appliances such as TVs, VTRs, microwave ovens, desk computers, notebook PCs, and portable electronic products such as smartphones. Is being applied.
또한, 전기, 전자기기에서 디지털 방식의 급속한 발전과 반도체 개발의 첨단화로 인해서, 소형화, 고밀도 및 고기능의 인쇄회로기판이 디지털 위성제품, DVR 감시 장치, 팜탑 컴퓨터, 반도체용 모듈, 디지털 카메라, 반도체 검사장치, 자동차 전장품은 물론이고, 방위산업 첨단무기인 미사일 탄두, 전투기 및 인공위성 등에 이르기까지 인쇄회로기판의 활용이 점차 확대되어 가고 있다. In addition, due to the rapid development of digital methods and advanced semiconductor development in electric and electronic devices, miniaturized, high-density and high-performance printed circuit boards are used for digital satellite products, DVR monitoring devices, palmtop computers, semiconductor modules, digital cameras, and semiconductor inspection. In addition to devices and automotive electronics, the use of printed circuit boards is gradually expanding to missile warheads, fighter aircraft and satellites, which are advanced weapons in the defense industry.
한편, 최근에는 스마트폰, 태블릿PC 등의 소형화 및 Iot(사물인터넷), Wearable 전자기기의 발전 등으로 인해 인쇄회로기판의 회로를 미세화(Fine) 하려는 연구가 활발히 진행되고 있다. 통상 인쇄회로기판 회로배선의 미세화라고 하면 100피치(Pitch)(회로폭: 50, 회로간격: 50) 이하인 경우를 말하며, 최근에는 미세화 회로(Fine Pattern)는 50피치 이하를 말하기도 한다. 이와 같이 미세회로의 피치(Fine Pattern Pitch)가 점점 내려가는 이유는 최근 휴대기기인 스마트폰, 태블릿PC, 웨어러블 전자기기 등의 기능이 향상되고 메모리 또는 CPU처리 용량이 16Giga Byte, 32Giga Byte에서 64Giga Byte, 128Giga Byte 이상으로 향상되더라도 제품의 단가 상승을 억제하기 위해 같은 층수에 보다 많은 회로를 배선하여야 하기 때문이다.On the other hand, recently, due to the miniaturization of smart phones, tablet PCs, the development of IoT (Internet of Things), wearable electronic devices, and the like to fine-tune the circuit of the printed circuit board (Fine) has been actively conducted. In general, miniaturization of a printed circuit board circuit wiring refers to a case of 100 pitches or less (circuit width: 50, circuit spacing: 50) or less. In recent years, a fine pattern may be 50 pitches or less. The reason why the fine circuit pitch is lowered is that the functions of smartphones, tablet PCs and wearable electronic devices such as mobile devices have recently been improved, and memory or CPU processing capacity has increased from 16 Giga Byte, 32 Giga Byte to 64 Giga Byte, Even if it is improved to 128 Giga Byte or more, more circuits must be wired in the same number of floors in order to suppress the cost increase of the product.
그런데 종래 인쇄회로기판의 경우 회로의 미세화(Fine Pattern) 보다는 상대부품과의 접점(접속)방식에 초점을 두고 있어 미세화 회로가 양면에 형성되는 인쇄회로기판의 제조에 그대로 적용하는 경우 인쇄회로기판의 양면에 형성된 회로의 전기적인 연결에 문제가 있다. 즉 종래 양면 인쇄회로기판의 경우 외부회로를 먼저 만들고 후에 Dot를 형성하는 경우에는 회로의 양쪽이 비아홀(Via Hole)을 통해서 연결이 되어 있으면 되는데, IC Chip 조립부분 또는 기타 SMD Pad의 회로부분에 앞뒤로 전기적인 연결이 안 되어 있는 경우가 많다. 이 경우에 양쪽면의 회로를 전기적으로 연결해주는 비아홀 속(내부)을 도금을 해주어야 하는데, 통전이 되지 않아 도금이 되지 않는다. However, in the case of the conventional printed circuit board, the focus is on the contact (connection) method with the counterpart parts rather than the fine pattern of the circuit, and when the miniaturized circuit is applied to the manufacturing of the printed circuit board formed on both sides of the printed circuit board, There is a problem in the electrical connection of circuits formed on both sides. In other words, in the case of a conventional double-sided printed circuit board, if an external circuit is first made and then a dot is formed later, both sides of the circuit need to be connected through a via hole. Often there is no electrical connection. In this case, it is necessary to plate the inside (inside) of the via hole that electrically connects the circuits on both sides, but the plating is not performed because it is not energized.
결국, 이와 같이 인쇄회로기판의 양면에 형성된 회로의 연결을 위해서는 앞, 뒤면 연결이 되어 있지 않은 부분에 다리선(Bridge), 일명 리드선(Lead Wire)을 일일이 연결하여 주어야 하는 추가 공정의 문제가 발생한다.As a result, in order to connect the circuits formed on both sides of the printed circuit board, there is a problem of an additional process that requires connecting bridges, or lead wires, to parts not connected to the front and rear surfaces. do.
특히 리드선을 일일이 연결한 후에도 리드선이 남는 문제가 여전히 발생하고, 미세화 회로의 경우 회로 피치(pitch)가 조밀한 부위에 리드선을 연결하는 경우 회로 간에 쇼트의 발생우려가 높아 리드선의 연결 자체가 불가능한 문제가 있다.In particular, the problem that the lead wire remains after the lead wires are connected one by one, and in the case of miniaturized circuits, when the lead wires are connected to areas where the circuit pitch is dense, there is a high possibility of short circuit between the circuits, and thus the connection of the lead wires is impossible. There is.
따라서 이와 같은 종래 기술의 문제점을 해결하기 위한 것으로서, 본 발명은 집적도를 높이기 위해 양면 또는 다층기판의 외층면에 미세화 회로를 갖는 인쇄회로기판을 제조시 인쇄회로기판 양면의 회로를 비아홀을 통해 전기적으로 연결하기 위하여 별도의 리드선으로 양쪽면의 회로를 연결할 필요가 없는 인쇄회로기판의 제조방법 및 그 방법에 의해 제조된 인쇄회로기판을 제공하는데 그 목적이 있다.Therefore, the present invention is to solve the problems of the prior art, the present invention to increase the degree of integration in the manufacturing of a printed circuit board having a miniaturization circuit on the outer layer surface of the double-sided or multi-layered substrate electrically through the via hole through the circuit on both sides of the printed circuit board It is an object of the present invention to provide a method for manufacturing a printed circuit board, and a printed circuit board manufactured by the method, which do not need to connect circuits on both sides by separate lead wires.
이와 같은 기술적 과제를 해결하기 위해 본 발명은; The present invention to solve this technical problem;
(a) 기판절연체의 양면 또는 다층기판의 외층면에 동박이 도포된 동박적층판(CCL; Copper Clad Laminate)을 드릴 가공하여 비아홀을 형성하기 위한 관통공을 형성한 후, 무전해 도금을 하여 제1도금층을 형성하는 단계; (b) 상기 제1도금층이 형성된 동박적층판의 양면에 감광제가 포함된 드라이 필름을 밀착 또는 액상 감광제를 도포하고 노광 및 현상하거나 PIR(Pattern Ink Resist) 인쇄를 통해 거쳐서 일면의 미세화 회로 및 비아홀 회로의 형성을 위한 에칭레지스트와 타면의 전체면에 에칭레지스트를 형성하는 단계; (c) 상기 동박적층판의 양면에 형성된 에칭레지스트 이외의 동박 및 제1도금층을 식각하고, 에칭레지스트로 사용된 드라이 필름 또는 액상 감광제 또는 PIR 잉크를 박리하여 일면에 미세화 회로와 비아홀 회로를 형성하는 단계; (d) 상기 동박적층판의 일면 또는 양면에 감광제가 포함된 드라이 필름을 재밀착 또는 액상 감광제를 재도포하고 노광 및 현상하거나 PIR(Pattern Ink Resist) 재인쇄를 통해 비아홀 회로를 위한 드라이 필름 또는 액상 감광제 또는 PIR 잉크의 개구부를 형성하는 단계; (e) 상기 드라이 필름 또는 액상 감광제 또는 PIR 잉크의 개구부에 전해 도금을 실시하여 제2도금층을 형성한 후, 상기 드라이 필름 또는 액상 감광제 또는 PIR 잉크를 박리하여 일면의 미세화 회로와 비아홀 회로를 완성하는 단계 또는 타면의 동박상에 제1도금층. 제2도금층으로 이루어진 그라운드(Ground)면을 형성하거나, 비아홀 랜드를 형성하는 단계; (f) 동박적층판의 양면에 감광제가 포함된 드라이 필름을 재밀착 또는 액상감광제를 재도포한 후, 동박적층판을 노광 및 현상하거나 PIR 재인쇄를 통해 거쳐서 타면의 미세화 회로와 비아홀 회로를 위한 에칭레지스트와 일면의 전체면에 에칭레지스트를 형성하는 단계; (g) 상기 에칭레지스트 이외의 동박 및 제1도금층, 제2도금층을 식각하거나, 동박 및 제1도금층을 식각한 후 에칭레지스트로 사용된 드라이 필름 또는 액상 감광제 또는 PIR 잉크를 박리하여 타면의 미세화 회로와 비아홀 회로를 완성하는 단계; 로 구성되는 것을 특징으로 하는 인쇄회로기판의 제조방법을 제공한다.(a) Drilling a copper clad laminate (CCL; Copper Clad Laminate) coated with copper foil on both sides of the substrate insulator or on the outer layer surface of the multilayer board to form through holes for forming via holes, and then electroless plating Forming a plating layer; (b) Applying a dry film containing a photosensitive agent to both sides of the copper-clad laminate plate on which the first plating layer is formed, or by applying a liquid photosensitive agent, and exposing and developing or through a PIR (Pattern Ink Resist) printing, Forming an etching resist on the entire surface of the etching resist and the other surface for forming; (c) etching the copper foil and the first plating layer other than the etching resist formed on both surfaces of the copper foil laminated plate, and peeling off the dry film, the liquid photosensitive agent, or the PIR ink used as the etching resist to form a miniaturization circuit and a via hole circuit on one surface thereof. ; (d) Dry film or liquid photoresist for via-hole circuits by re-adhering a dry film containing a photosensitive agent on one or both surfaces of the copper clad laminate or re-coating a liquid photoresist, exposing and developing the pattern ink resist (PIR) Or forming an opening in the PIR ink; (e) forming a second plating layer by electroplating the opening of the dry film or the liquid photosensitive agent or the PIR ink, and then peeling off the dry film or the liquid photosensitive agent or the PIR ink to complete the micronization circuit and the via hole circuit of one surface The first plating layer on the copper foil of the step or the other side. Forming a ground surface formed of a second plating layer or forming a via hole land; (f) Re-adhering the dry film containing the photosensitive agent on both surfaces of the copper-clad laminate, or reapplying the liquid photoresist, and then exposing and developing the copper-clad laminate, or through PIR reprinting, an etching resist for miniaturization and via hole circuits on the other side. Forming an etching resist on the entire surface of the surface; (g) Etching the copper foil, the first plating layer, and the second plating layer other than the etching resist, or etching the copper foil and the first plating layer, and then peeling off the dry film or liquid photosensitive agent or PIR ink used as the etching resist, and miniaturizing the other surface. And completing the via hole circuit; It provides a method for manufacturing a printed circuit board, characterized in that consisting of.
또한, 본 발명은;In addition, the present invention;
(a) 기판절연체의 양면 또는 다층기판의 외층면에 동박이 도포된 동박적층판을 드릴 가공하여 비아홀을 형성하기 위한 관통공을 형성한 후, 무전해 도금을 하여 제1도금층을 형성하고 상기 제1도금층상에 전해 도금을 통해 제2도금층을 형성하는 단계; (b) 상기 제2도금층이 형성된 동박적층판의 양면에 감광제가 포함된 드라이 필름을 밀착 또는 액상 감광제를 도포하고 노광 및 현상하거나 PIR(Pattern Ink Resist) 인쇄를 통해 거쳐서 일면의 미세화 회로 및 비아홀 회로 형성을 위한 에칭레지스트와 타면의 전체면에 에칭레지스트를 형성하는 단계; (c) 상기 동박적층판의 양면에 형성된 에칭레지스트 이외의 동박 및 제1도금층, 제2도금층을 식각한 후 에칭레지스트로 사용된 드라이 필름 또는 액상 감광제 또는 PIR 잉크를 박리하여 일면의 미세화 회로와 비아홀 회로를 형성하는 단계; (d) 상기 동박적층판의 일면 또는 양면에 감광제가 포함된 드라이 필름을 재밀착 또는 액상 감광제를 재도포하고 노광 및 현상하거나 PIR(Pattern Ink Resist)을 재인쇄를 통해 비아홀 회로를 위한 드라이 필름 또는 액상 감광제 또는 PIR 잉크의 개구부를 형성하는 단계; (e) 상기 드라이 필름 또는 액상 감광제 또는 PIR 잉크의 개구부에 전해 도금을 실시하여 제3도금층을 형성하고 드라이 필름 또는 액상 감광제 또는 PIR 잉크를 박리하여 일면의 미세화 회로와 비아홀 회로를 완성하는 단계 또는 타면의 동박상에 제1도금층, 제2도금층, 제3도금층으로 이루어진 그라운드(Ground)면을 형성하거나, 비아홀 랜드(Land)를 형성하는 단계; (f) 동박적층판의 양면에 감광제가 포함된 드라이 필름을 재밀착 또는 액상 감광제를 재도포하고, 상기 동박적층판을 노광 및 현상하거나 PIR 재인쇄를 통해 거쳐서 타면의 미세화 회로와 비아홀 회로를 위한 에칭레지스트와 일면의 전체면에 에칭레지스트를 형성하는 단계; (g) 상기 에칭레지스트 이외의 동박 및 제1도금층, 제2도금층, 제3도금층을 식각하거나, 동박 및 제1도금층, 제2도금층을 식각한 후 에칭레지스트로 사용된 드라이 필름 또는 액상 감광제 또는 PIR 잉크를 박리하여 타면의 미세화 회로와 비아홀 회로를 완성하는 단계; 로 구성되는 것을 특징으로 하는 인쇄회로기판의 제조방법도 제공한다.(a) Drilling through a copper foil laminated plate coated with copper foil on both sides of the substrate insulator or on the outer surface of the multilayer board to form through holes for forming via holes, and then electroless plating to form a first plating layer and Forming a second plating layer on the plating layer through electrolytic plating; (b) forming a micronized circuit and via hole circuit on one surface of the copper foil laminated plate on which the second plating layer is formed by closely contacting a dry film containing a photosensitive agent or by applying a liquid photoresist, and exposing and developing the film through PIR (Pattern Ink Resist) printing; Forming an etching resist on the entire surface of the other surface with the etching resist; (c) etching the copper foil, the first plating layer, and the second plating layer other than the etching resist formed on both surfaces of the copper foil laminated plate, and then peeling off the dry film, liquid photosensitive agent, or PIR ink used as the etching resist, and miniaturizing the circuit and via hole circuit on one surface. Forming a; (d) Dry film or liquid for via-hole circuits by re-adhering a dry film containing a photosensitive agent on one or both surfaces of the copper clad laminate or re-coating a liquid photosensitive agent and exposing and developing or reprinting a pattern ink resist (PIR). Forming openings in the photosensitizer or PIR ink; (e) forming a third plating layer by electroplating the opening of the dry film or the liquid photosensitive agent or the PIR ink, and peeling off the dry film or the liquid photosensitive agent or the PIR ink to complete the miniaturization circuit and the via hole circuit of one surface or the other surface. Forming a ground surface of the first plating layer, the second plating layer, and the third plating layer or forming a via hole land on the copper foil of the copper foil; (f) Etching resist for micronizing circuit and via hole circuit on the other side by re-adhering the dry film containing photosensitive agent on both sides of copper foil laminated plate or recoating liquid photosensitive agent, and exposing and developing copper foil laminated plate through PIR reprinting Forming an etching resist on the entire surface of the surface; (g) A dry film or liquid photosensitive agent or PIR used as an etching resist after etching the copper foil and the first plating layer, the second plating layer, and the third plating layer other than the etching resist, or after etching the copper foil and the first plating layer and the second plating layer. Peeling the ink to complete the miniaturization circuit and the via hole circuit of the other surface; Also provided is a method of manufacturing a printed circuit board, characterized in that consisting of.
아울러 본 발명은; In addition, the present invention;
상기 방법에 의해 제조된 인쇄회로기판도 제공한다.There is also provided a printed circuit board manufactured by the above method.
본 발명에 따른 인쇄회로기판은 양면 또는 다층기판의 외층면에 미세화 회로를 갖는 인쇄회로기판을 제조시 인쇄회로기판 양면의 회로를 비아홀(Via Hole)을 통해 전기적으로 연결하여 추후 기판 양면의 회로를 리드선으로 연결할 필요가 없이 제조되는 인쇄회로기판의 구조를 간소화할 수 있다.In the printed circuit board according to the present invention, when manufacturing a printed circuit board having a miniaturization circuit on the outer layer surface of a double-sided or multi-layered board, the circuits on both sides of the printed circuit board are electrically connected to each other through via holes. It is possible to simplify the structure of the printed circuit board manufactured without the need for connecting with lead wires.
특히 인쇄회로기판 양면의 회로가 비아홀(Via Hole)을 통해 연결되므로 미세화 회로의 경우 리드선으로 연결시 발생 가능한 쇼트 발생 우려를 원천적으로 차단하여 미세화 회로를 인쇄회로기판상에 고집적화할 수 있어 미세화 회로가 형성되는 인쇄회로기판의 제조에 유리하다.In particular, since the circuits on both sides of the printed circuit board are connected through via holes, the miniaturization circuit can fundamentally block the possibility of a short circuit that may occur when connecting the lead wire, thereby minimizing the miniaturization circuit on the printed circuit board. It is advantageous for the production of printed circuit boards to be formed.
도 1a 내지 1o는 본 발명의 일실시 예에 따른 인쇄회로기판의 제조방법을 설명하기 위한 단면도이다.1A to 1O are cross-sectional views illustrating a method of manufacturing a printed circuit board according to an exemplary embodiment of the present invention.
도 2a 내지 2p는 본 발명의 다른 실시 예에 따른 인쇄회로기판의 제조방법을 설명하기 위한 단면도이다.2A through 2P are cross-sectional views illustrating a method of manufacturing a printed circuit board according to another exemplary embodiment of the present invention.
이하 본 발명에 따른 인쇄회로기판의 제조방법 및 그 방법에 의해 제조된 인쇄회로기판을 첨부된 도면을 참고로 하여 상세히 기술되는 실시 예들에 의해 그 특징들을 이해할 수 있을 것이다.Hereinafter, a method of manufacturing a printed circuit board and a printed circuit board manufactured by the method according to the present invention will be understood by the embodiments described in detail with reference to the accompanying drawings.
본 발명은 다양한 변경을 가할 수 있고 여러 가지 형태를 가질 수 있는바, 구현 예(또는 실시 예)들을 본문에 상세하게 설명하고자 한다. 그러나 이는 본 발명을 특정한 개시 형태에 대해 한정하려는 것이 아니며, 본 발명의 사상 및 기술 범위에 포함되는 모든 변경, 균등물 내지 대체물을 포함하는 것으로 이해되어야 한다.As the inventive concept allows for various changes and numerous modifications, implementations (or embodiments) will be described in detail in the text. However, this is not intended to limit the present invention to a specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention.
각 도면에서 동일한 참조부호, 특히 십의 자리 및 일의 자리 수, 또는 십의 자리, 일의 자리 및 알파벳이 동일한 참조부호는 동일 또는 유사한 기능을 갖는 부재를 나타내고, 특별한 언급이 없을 경우 도면의 각 참조부호가 지칭하는 부재는 이러한 기준에 준하는 부재로 파악하면 된다.In each of the drawings, the same reference numerals, in particular, the tens and ones digits, or the same digits, tens, ones, and alphabets refer to members having the same or similar functions, and unless otherwise specified, each member in the figures The member referred to by the reference numeral may be regarded as a member conforming to these criteria.
또 각 도면에서 구성요소들은 이해의 편의 등을 고려하여 크기나 두께를 과장되게 크거나(또는 두껍게) 작게(또는 얇게) 표현하거나, 단순화하여 표현하고 있으나 이에 의하여 본 발명의 보호범위가 제한적으로 해석되어서는 안 된다.In addition, in the drawings, the components are exaggerated in size (or thick) in size (or thick) in size (or thin) or simplified in consideration of the convenience of understanding and the like, thereby limiting the scope of protection of the present invention. It should not be.
본 명세서에서 사용한 용어는 단지 특정한 구현 예(또는 실시 예)를 설명하기 위해 사용된 것으로, 본 발명을 한정하려는 의도가 아니다. 단수의 표현은 문맥상 명백하게 다르게 뜻하지 않는 한, 복수의 표현을 포함한다. 본 출원에서, ~포함하다~ 또는 ~이루어진다~ 등의 용어는 명세서상에 기재된 특징, 숫자, 단계, 동작, 구성요소, 부분품 또는 이들을 조합한 것이 존재함을 지정하려는 것이지, 하나 또는 그 이상의 다른 특징들이나 숫자, 단계, 동작, 구성요소, 부분품 또는 이들을 조합한 것들의 존재 또는 부가 가능성을 미리 배제하지 않는 것으로 이해되어야 한다.The terminology used herein is for the purpose of describing particular embodiments (or embodiments) only and is not intended to be limiting of the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms “comprises” or “consists” are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, but one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, parts, or combinations thereof.
다르게 정의되지 않는 한, 기술적이거나 과학적인 용어를 포함해서 여기서 사용되는 모든 용어들은 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에 의해 일반적으로 이해되는 것과 동일한 의미가 있다. 일반적으로 사용되는 사전에 정의되어 있는 것과 같은 용어들은 관련 기술의 문맥상 가지는 의미와 일치하는 의미가 있는 것으로 해석되어야 하며, 본 출원에서 명백하게 정의하지 않는 한, 이상적이거나 과도하게 형식적인 의미로 해석되지 않는다.Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.
이하, 상기한 바와 같은 본 발명의 바람직한 실시 예를 첨부도면을 참고하여 더욱 상세하게 설명하면 다음과 같다. 그리고 도면에서 동일부호는 동일한 요소를 지칭한다.Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention as described above in more detail as follows. In the drawings, like reference numerals refer to like elements.
먼저, 도 1a 내지 1o는 본 발명의 일실시 예에 따른 인쇄회로기판의 제조방법을 설명하기 위한 단면도로서, 특히 양면 또는 다층기판의 외층면 인쇄회로기판의 제조방법을 설명하기 위한 단면도이다.First, FIGS. 1A to 1O are cross-sectional views illustrating a method of manufacturing a printed circuit board according to an exemplary embodiment of the present invention, and particularly, a cross-sectional view illustrating a method of manufacturing an outer layer printed circuit board of a double-sided or multilayer board.
도 1a를 참조하면, 기판절연체(102)의 양면 또는 다층기판의 외층면에 동박(104)이 도포된 동박적층판(100)이 도시되어 있다.Referring to FIG. 1A, a copper foil laminated plate 100 having a copper foil 104 coated on both surfaces of a substrate insulator 102 or an outer layer surface of a multilayer substrate is illustrated.
여기서 상기 동박적층판의 동박 대신에 알루미늄, 니켈(Ni), 크롬 등의 기타 다른 금속으로 변경 사용함도 가능하다.Here, instead of the copper foil of the copper-clad laminate, it is also possible to change and use other metals such as aluminum, nickel (Ni) and chromium.
도 1b를 참조하면, 상기 동박적층판(100)을 드릴 가공하여 비아홀(Via Hole)을 형성하기 위한 관통공(106)을 형성한다.Referring to FIG. 1B, the copper foil laminated plate 100 is drilled to form a through hole 106 for forming a via hole.
도 1c를 참조하면, 상기 동박적층판(100)의 양쪽 동박면이 전기적으로 도통할 수 있도록 무전해도금을 하여 제1도금층(108)을 형성한다. 이때, 제1도금층(108)은 바람직하게는 0.5~1.0um의 두께로 형성된다.Referring to FIG. 1C, the first plating layer 108 may be formed by electroless plating so that both surfaces of the copper foil laminate 100 may be electrically conductive. At this time, the first plating layer 108 is preferably formed to a thickness of 0.5 ~ 1.0um.
여기서 상기 무전해 도금은 동, 니켈, 카본계열 등의 기타 다른 금속재질로 사용함도 가능하다.Here, the electroless plating may be used as other metal materials such as copper, nickel, and carbon series.
도 1d를 참조하면, 제1도금층(108)이 형성된 상기 동박적층판(100)의 양면에 감광제가 포함된 드라이 필름(110, 112)을 밀착하고, 도 1e에 도시된 바와 같이 드라이 필름(110, 112)을 사진 공정에 의한 노광, 현상 공정을 거쳐서 일면의 미세화 회로(100a) 및 비아홀 회로(100b) 형성을 위한 에칭레지스트(110a)와 타면의 전체면에 에칭레지스트(112a)를 형성한다.Referring to FIG. 1D, dry films 110 and 112 including photoresist are adhered to both surfaces of the copper clad laminate 100 on which the first plating layer 108 is formed, and as shown in FIG. 1E, the dry films 110, The etching resist 112a is formed on the entire surface of the etching resist 110a and the other surface for forming the micronization circuit 100a and the via hole circuit 100b on one surface through the exposure and development process by the photo process.
여기서 노광, 현상공정을 거쳐서 형성되는 미세화 회로(100a) 및 비아홀 회로(100b)는 일면에 형성되며, 타면에는 전체면 노광, 현상을 하기 때문에 미세화 회로(100a) 및 비아홀 회로(100b)는 형성되지 않는 특징이 있다.The micronization circuit 100a and the via hole circuit 100b formed through the exposure and development processes are formed on one surface, and the micronization circuit 100a and the via hole circuit 100b are not formed because the entire surface is exposed and developed on the other surface. Does not have features.
이때, 상기 도 1d 및 도 1e에 도시된 바와 같이 드라이 필름(110,112)을 이용하는 대신에 액상 감광제를 도포하여 노광 및 현상하거나 PIR(Pattern Ink Resist) 인쇄를 통해 거쳐서 미세화 회로(100a) 및 비아홀 회로(100b) 형성을 위한 에칭레지스트(110a, 112a)를 형성함도 가능하다.In this case, as shown in FIGS. 1D and 1E, instead of using the dry films 110 and 112, a liquid photoresist is applied to expose and develop or through a fine ink circuit (PIR) printing, thereby miniaturizing the circuit 100a and the via hole circuit ( It is also possible to form the etching resists 110a and 112a for forming 100b).
도 1f를 참조하면, 상기 동박적층판(100)을 사진 공정에 의해서 형성된 일면의 미세화 회로(100a) 및 비아홀 회로(100b) 형성을 위한 에칭레지스트(110a) 이외의 동박(104) 및 제1도금층(108)을 식각하고, 상기 에칭레지스트(110a, 112a)로 사용된 드라이 필름을 박리하여 일면에 미세화 회로(100a)와 비아홀 회로(100b)를 형성하며, 타면은 식각이 되지 않아 미세화 회로(100a) 또는 비아홀 회로(100b)가 형성되지 않고 동박(104) 및 제1도금층(108)이 그라운드(Ground) 상태로 남게 된다.Referring to FIG. 1F, the copper foil 104 and the first plating layer other than the etching resist 110a for forming the miniaturization circuit 100a and the via hole circuit 100b of one surface of the copper foil laminated plate 100 formed by a photolithography process ( 108 is etched, and the dry films used as the etching resists 110a and 112a are peeled off to form the micronization circuit 100a and the via hole circuit 100b on one surface, and the other surface is not etched, so the micronization circuit 100a is removed. Alternatively, the via hole circuit 100b is not formed and the copper foil 104 and the first plating layer 108 remain in a ground state.
도 1g를 참조하면, 상기 일면에 미세화 회로(100a)와 비아홀 회로(100b)가 형성된 동박적층판(100)의 일면 또는 양면에 감광제가 포함된 드라이 필름(114)을 재밀착하고, 도 1h에 도시된 바와 같이 사진 공정에 의해서 노광 및 현상하여 비아홀 회로(100b) 도금을 위한 개구부(114a)를 일면 또는 양면에 형성한다.Referring to FIG. 1G, the dry film 114 including the photosensitizer may be re-adhered to one or both surfaces of the copper-clad laminate 100 having the micronization circuit 100a and the via hole circuit 100b formed on one surface thereof, and illustrated in FIG. 1H. As described above, the photoresist is exposed and developed to form openings 114a for plating the via hole circuit 100b on one or both surfaces.
이때, 상기 도 1g 및 도 1h에 도시된 바와 같이 드라이 필름(114)을 이용하는 대신에 액상감광제를 도포하여 노광 및 현상하거나 PIR(Pattern Ink Resist) 인쇄를 통해 비아홀 회로(100b)에 도금층을 형성하기 위한 개구부를 형성함도 가능하다.In this case, instead of using the dry film 114 as shown in FIGS. 1G and 1H, a liquid sensitizer is applied to expose and develop or to form a plating layer in the via hole circuit 100b through PIR (Pattern Ink Resist) printing. It is also possible to form openings for the same.
여기서, 상기 드라이 필름 또는 액상 감광제 또는 PIR 잉크는 도 1i에서 전해 도금시 도금 레지스트(Plating Resist) 역할을 한다.Here, the dry film, the liquid photoresist, or the PIR ink serves as a plating resist during electroplating in FIG. 1I.
도 1i를 참조하면, 비아홀 회로(100b)를 위한 개구부(114a)에 전해도금을 실시하여 제2도금층(116)을 형성한다. 여기서, 제2도금층(116)은 바람직하게는 10 내지 20um의 두께로 형성하며, 그 이상이나 이하의 두께로도 형성할 수 있다.Referring to FIG. 1I, the second plating layer 116 is formed by electroplating the opening 114a for the via hole circuit 100b. Here, the second plating layer 116 is preferably formed to a thickness of 10 to 20um, it may be formed to a thickness of more or less.
이때, 상기 비아홀 회로(100b)를 위한 개구부(114a)에 제2도금층(116)을 형성하는 이유는 상기 도1c에서 수행했던 제1도금층의 두께가 얇아서 비아홀(Hole)속 전기 도통성의 신뢰성을 보장할 수 없기 때문이다.In this case, the reason for forming the second plating layer 116 in the opening 114a for the via hole circuit 100b is that the thickness of the first plating layer performed in FIG. 1C is thin to ensure reliability of electrical conductivity in the via hole. Because you can't.
여기서 상기 전해도금은 동, 니켈, 은 등의 기타 다른 금속재질로 사용함도 가능하다.Here, the electroplating may be used as other metal materials such as copper, nickel, and silver.
도 1j를 참조하면, 상기 도금 레지스트로 사용된 드라이 필름(114)을 소정의 박리 공정을 통해서 제거하여 일면의 미세화 회로(100a)와 비아홀 회로(100b)를 완성하고 또는 타면의 동박(104)상에 제1도금층(108), 제2도금층(116)으로 이루어진 그라운드면(100d)을 형성하거나, 비아홀 랜드(100c)를 형성하여 마련한다.Referring to FIG. 1J, the dry film 114 used as the plating resist is removed through a predetermined peeling process to complete the micronization circuit 100a and the via hole circuit 100b on one surface or the copper foil 104 on the other surface. The ground surface 100d including the first plating layer 108 and the second plating layer 116 is formed on the substrate, or the via hole land 100c is formed.
이때, 도 1j의 a), b)는 일면에 미세화 회로가 배선되고 타면에는 미세화 회로가 배선되지 않는 특징이 있으며, c), d)는 일면 및 타면에 모두 미세화 회로가 배선되는 특징이 있다.At this time, a) and b) of FIG. 1J are characterized in that the miniaturization circuit is wired on one surface and the miniaturization circuit is not wired on the other surface, and c) and d) are characterized in that the miniaturization circuit is wired on one surface and the other surface.
도 1k를 참조하면, 일면의 미세화 회로(100a) 및 비아홀 회로(100b)와 타면의 그라운드면(100d) 또는 비아홀 랜드(100c)가 돌출 형성된 동박적층판(100)의 양면에 감광제가 포함된 드라이 필름(118, 120)을 재밀착하고, 도 1l에 도시된 바와 같이 동박적층판(100)을 사진 공정에 의해서 노광 및 현상하여 타면의 미세화 회로(100a)와 비아홀 회로(100b)를 위한 에칭레지스트(120a)와 일면의 전체면에 에칭레지스트(118a)를 형성한다.Referring to FIG. 1K, a dry film including a photosensitive agent on both surfaces of a copper foil laminate plate 100 on which one of the micronization circuit 100a and the via hole circuit 100b and the ground surface 100d or the via hole land 100c of the other surface is protruded. (118, 120) are brought into close contact with each other, and the copper-clad laminate 100 is exposed and developed by a photolithography process as shown in FIG. 1L, and the etching resist 120a for the micronization circuit 100a and the via hole circuit 100b of the other surface is exposed. ) And the entire surface of one surface is formed with an etching resist 118a.
여기서 상기 드라이 필름(118, 120)을 이용하는 대신에 액상 감광제를 도포하여 노광 및 현상하거나 PIR(Pattern Ink Resist) 재인쇄를 통해 거쳐서 미세화 회로(100a) 및 비아홀 회로(100b) 형성을 위한 에칭레지스트(118a, 120a)를 형성함도 가능하다.Here, instead of using the dry films 118 and 120, an etching resist for forming a miniaturization circuit 100a and a via hole circuit 100b may be formed by applying a liquid photoresist and exposing and developing or reprinting a pattern ink resist (PIR). It is also possible to form 118a and 120a.
도 1m를 참조하면, 상기 동박적층판(100)을 사진 공정에 의해서 형성된 타면의 미세화 회로(100a) 및 비아홀 회로(100b) 형성을 위한 에칭레지스트(120a) 이외의 동박(104) 및 제1도금층(108), 제2도금층(116)을 식각하거나, 동박(104) 및 제1도금층(108)을 식각한 후 양쪽면의 에칭레지스트(118a, 120a)로 사용된 드라이 필름을 박리하여 타면의 미세화 회로(100a)와 비아홀 회로(100b)를 완성한다.Referring to FIG. 1M, the copper foil 104 and the first plating layer other than the etching resist 120a for forming the micronized circuit 100a and the via hole circuit 100b of the other surface formed by the photolithography process are formed on the copper foil laminated plate 100. 108), the second plating layer 116 is etched, or the copper foil 104 and the first plating layer 108 are etched, and then the dry films used as the etching resists 118a and 120a on both sides are peeled off to further refine the circuit on the other side. 100a and the via hole circuit 100b are completed.
이때, 상기 타면의 미세화 회로(100a)와 비아홀 회로(100b)를 형성하기 위해 식각시에 이미 형성된 일면의 미세화 회로(100a)와 비아홀 회로(100b)는 식각되지 않는 특징이 있다.At this time, in order to form the micronization circuit 100a and the via hole circuit 100b of the other surface, the micronization circuit 100a and the via hole circuit 100b of one surface already formed at the time of etching are not etched.
이후 도 1n에 도시된 바와 같은 절연층(130) 형성 공정과, 도 1o에 도시된 바와 같은 금속층(140) 형성 공정을 순차적으로 수행한다.Thereafter, the process of forming the insulating layer 130 as shown in FIG. 1N and the process of forming the metal layer 140 as shown in FIG. 1O are sequentially performed.
도 1n를 참조하면, 상기 식각된 양쪽면의 회로 또는 회로 사이를 절연하기 위해서 일반적으로 사용하고 있는 폴리이미드계, 아크릴계, 에폭시계의 절연재 중에 선택하여 인쇄공정 또는 PSR 공정을 수행하거나, 폴리이미드계, 아크릴계, 에폭시계의 절연재 중에 선택하여 적층공정을 수행하여 표면 처리할 영역을 제외한 회로 및 회로 사이에 절연층(130)을 형성한다.Referring to FIG. 1N, a printing process or a PSR process is performed by selecting among polyimide-based, acryl-based, and epoxy-based insulating materials which are generally used to insulate the circuits or circuits on both surfaces of the etched surface, or polyimide-based The insulating layer 130 is formed between circuits and circuits except for regions to be surface-treated by performing a lamination process by selecting among acrylic and epoxy insulating materials.
여기서, 상기 절연체 도포 방법을 3D 프린팅 또는 잉크젯 프린팅 방식으로 회로 또는 회로 사이에 절연체를 도포함도 가능하다.Here, the method of applying the insulator may also include an insulator between the circuits or circuits by 3D printing or inkjet printing.
도 1o를 참조하면, 상기 미세화 회로(100a)와 비아홀 회로(100b)의 전기 전도도를 향상시키기 위해서 표면 처리할 영역에 무전해 또는 전해 도금으로 니켈도금이나 금도금 또는 니켈과 금을 함께 이용하여 도금한 금속층(140)으로 형성한다.Referring to FIG. 1O, in order to improve the electrical conductivity of the micronization circuit 100a and the via hole circuit 100b, nickel plating, gold plating, or nickel and gold may be plated together by electroless or electrolytic plating on a region to be surface treated. The metal layer 140 is formed.
여기서, 표면 처리할 영역에 상기 니켈도금, 금도금 대신에 OSP(Organic Solderability Preservative) 또는 은도금으로 표면처리를 선택하여 수행할 수도 있다.Here, the surface treatment may be performed by selecting the surface treatment with OSP (Organic Solderability Preservative) or silver plating instead of the nickel plating and gold plating.
이때, 상기 금속층(140)은 니켈 도금으로 층을 형성하는 경우에는 3 내지 7um의 두께로 형성함이 바람직하고, 금도금으로 층을 형성하는 경우에는 0.03 내지 0.05um의 두께로 형성함이 바람직하며, 그 이상과 이하의 두께로도 형성할 수 있다.At this time, the metal layer 140 is preferably formed with a thickness of 3 to 7um when forming a layer by nickel plating, and when forming a layer with gold plating, it is preferable to form a thickness of 0.03 to 0.05um, It can also be formed in thicknesses above and below.
여기에서, 도 1m 공정 이후에 도 1n 과 도 1o 공정은 공정 순서를 바꾸어 진행함도 가능하다.Here, after the process of FIG. 1M, the process of FIGS. 1N and 1O may be performed by changing the process order.
이후, 후처리 공정을 거쳐서 양면 또는 다층기판의 외층면 인쇄회로기판을 완성하게 된다.Thereafter, an outer layer printed circuit board of a double-sided or multi-layered substrate is completed through a post-treatment process.
한편, 도 2a 내지 2p는 본 발명의 다른 실시 예에 따른 인쇄회로기판의 제조방법을 설명하기 위한 단면도로서, 이 역시 양면 또는 다층기판의 외층면 인쇄회로기판의 제조방법을 설명하기 위한 단면도이다.2A to 2P are cross-sectional views illustrating a method of manufacturing a printed circuit board according to another exemplary embodiment, and are also cross-sectional views illustrating a method of manufacturing an outer layer printed circuit board of a double-sided or multilayer board.
도 2a를 참조하면, 기판절연체(202)의 양면 또는 다층기판의 외층면에 동박(204)이 도포된 동박적층판(200)이 도시되어 있다.Referring to FIG. 2A, a copper foil laminated plate 200 having a copper foil 204 coated on both surfaces of an insulator 202 or an outer layer surface of a multilayer substrate is illustrated.
여기서 상기 동박적층판(200)의 동박(204) 대신에 알루미늄, 니켈(Ni), 크롬 등의 기타 다른 금속으로 변경 사용함도 가능하다.Here, instead of the copper foil 204 of the copper-clad laminate 200, it is also possible to use other metal, such as aluminum, nickel (Ni), chromium.
도 2b를 참조하면, 상기 동박적층판(200)을 드릴 가공하여 비아홀(Via Hole)을 형성하기 위한 관통공(206)을 형성한다.Referring to FIG. 2B, the copper foil laminated plate 200 is drilled to form a through hole 206 for forming a via hole.
도 2c를 참조하면, 동박적층판(200)의 양쪽 동박면이 전기적으로 도통할 수 있도록 무전해 도금을 하여 제1도금층(208)을 형성한다. 이때, 상기 제1도금층(208)은 바람직하게는 0.5~1.0um의 두께로 형성된다.Referring to FIG. 2C, the first plating layer 208 is formed by electroless plating so that both copper foil surfaces of the copper clad laminate 200 may be electrically connected to each other. In this case, the first plating layer 208 is preferably formed to a thickness of 0.5 ~ 1.0um.
여기서 상기 무전해 도금은 동, 니켈, 카본 계열 등의 기타 다른 금속재질로 사용함도 가능하다.Here, the electroless plating may be used as other metal materials such as copper, nickel, and carbon series.
도 2d를 참조하면, 상기 제1도금층(208)상에 전해 도금을 통해 제2도금층(209)을 형성한다. 이때, 제2도금층(209)은 바람직하게는 5 내지 10um의 두께로 형성하며, 그 이상이나 이하의 두께로도 형성할 수 있다.Referring to FIG. 2D, a second plating layer 209 is formed on the first plating layer 208 through electrolytic plating. At this time, the second plating layer 209 is preferably formed to a thickness of 5 to 10um, it may be formed to a thickness of more or less.
여기서 상기 전해도금은 동, 니켈, 은 등의 기타 다른 금속재질로 사용함도 가능하다.Here, the electroplating may be used as other metal materials such as copper, nickel, and silver.
도 2e를 참조하면, 상기 제2도금층(209)이 형성된 동박적층판(200)의 양면에 감광제가 포함된 드라이 필름(210, 212)을 밀착하고, 도 2f에 도시된 바와 같이 양면의 드라이 필름(210, 212)을 사진 공정에 의한 노광, 현상 공정을 거쳐서 일면의 미세화 회로(200a) 및 비아홀 회로(200b) 형성을 위한 에칭레지스트(210a)와 타면의 전체면에 에칭레지스트(212a)를 형성한다.Referring to FIG. 2E, dry films 210 and 212 including photosensitive agents may be adhered to both surfaces of the copper-clad laminate 200 on which the second plating layer 209 is formed, and as shown in FIG. The etching resists 212a are formed on the entire surface of the etching resist 210a and the other surface for forming the micronization circuit 200a and the via hole circuit 200b on one surface by exposing and developing the 210 and 212 using a photolithography process. .
이때, 상기 도 2e 및 도 2f의 드라이 필름(210, 212)을 이용하는 대신에 액상감광제를 도포하여 노광 및 현상하거나 PIR(Pattern Ink Resist) 인쇄를 통해 거쳐서 미세화 회로(200a) 및 비아홀 회로(200b) 형성을 위한 에칭레지스트(210a, 212a)를 형성함도 가능하다.In this case, instead of using the dry films 210 and 212 of FIGS. 2E and 2F, a liquid photosensitive agent is coated to expose and develop or through a PIR (Pattern Ink Resist) printing, thereby miniaturizing the circuit 200a and the via hole circuit 200b. It is also possible to form etching resists 210a and 212a for formation.
여기서 상기 노광, 현상을 거쳐서 형성되는 미세화 회로(200a) 및 비아홀 회로(200b)는 일면에 형성되며, 타면에는 전체면을 노광, 현상하여 미세화 회로(200a) 및 비아홀 회로(200b)는 형성되지 않는 특징이 있다.The micronization circuit 200a and the via hole circuit 200b formed through the exposure and development are formed on one surface, and the micronizing circuit 200a and the via hole circuit 200b are not formed by exposing and developing the entire surface on the other surface. There is a characteristic.
도 2g를 참조하면, 상기 동박적층판(200)을 사진 공정에 의해서 형성된 일면의 미세화 회로(200a) 및 비아홀 회로(200b) 형성을 위한 에칭레지스트(210a) 이외의 동박(204) 및 제1도금층(208), 제2도금층(209)을 식각하고 에칭레지스트(210a, 212a)로 사용된 드라이 필름을 박리하여 일면의 미세화 회로(200a)와 비아홀 회로(200b)를 형성하며, 타면은 식각되지 않고 미세화 회로(200a) 또는 비아홀 회로(200b)가 형성되지 않고 동박(204) 및 제1도금층(208), 제2도금층(209)이 그라운드(Ground)상태로 남게 된다.Referring to FIG. 2G, the copper foil 204 and the first plating layer other than the etching resist 210a for forming the miniaturization circuit 200a and the via hole circuit 200b of one surface formed by the photolithography process are formed on the copper foil laminated plate 200. 208, the second plating layer 209 is etched and the dry films used as the etching resists 210a and 212a are peeled off to form the micronization circuit 200a and the via hole circuit 200b on one surface, and the other surface is not etched and micronized. The circuit 200a or the via hole circuit 200b is not formed, and the copper foil 204, the first plating layer 208, and the second plating layer 209 remain in a ground state.
도 2h를 참조하면, 상기 일면에 미세화 회로(200a)와 비아홀 회로(200b)가 형성된 동박적층판(200)의 일면 또는 양면에 감광제가 포함된 드라이 필름(214)을 재밀착하고, 도 2i에 도시된 바와 같이 사진 공정에 의해서 노광 및 현상하여 비아홀 회로(200b)를 위한 개구부(214a)를 일면 또는 양면에 형성한다.Referring to FIG. 2H, a dry film 214 including a photosensitive agent is re-adhered to one or both surfaces of the copper clad laminate 200 having the micronization circuit 200a and the via hole circuit 200b formed thereon, and illustrated in FIG. 2I. As described above, exposure and development are performed by a photographic process to form openings 214a for the via hole circuit 200b on one or both surfaces.
이때, 상기 도 2h 및 도 2i의 드라이 필름(214)을 이용하는 대신에 액상감광제를 도포하여 노광 및 현상하거나 PIR(Pattern Ink Resist) 인쇄를 통해 비아홀 회로(200b)에 도금층을 형성하기 위한 개구부(214a)를 형성함도 가능하다.In this case, instead of using the dry film 214 of FIGS. 2H and 2I, the liquid sensitizer is applied to expose and develop the opening, or an opening 214a for forming a plating layer in the via hole circuit 200b through PIR (Pattern Ink Resist) printing. It is also possible to form).
여기서, 상기 드라이 필름 또는 액상 감광제 또는 PIR 잉크는 도 2j에서 전해 도금시 도금 레지스트(Plating Resist) 역할을 한다.Here, the dry film, the liquid photoresist, or the PIR ink serves as a plating resist during electroplating in FIG. 2J.
도 2j를 참조하면, 상기 비아홀 회로(200b)를 위한 개구부(214a)에 전해 도금을 실시하여 제3도금층(216)을 형성한다. 여기서, 제3도금층(216)은 바람직하게는 5 내지 10um의 두께로 형성하며, 그 이상이나 이하의 두께로도 형성할 수 있다.Referring to FIG. 2J, a third plating layer 216 is formed by electroplating the opening 214a for the via hole circuit 200b. Here, the third plating layer 216 is preferably formed to a thickness of 5 to 10um, it may be formed to a thickness of more or less.
이때, 도 2j의 a), b)는 일면에 미세화 회로가 배선되고 타면에는 미세화 회로가 배선되지 않는 특징이 있으며, c), d)는 일면 및 타면에 모두 미세화 회로가 배선되는 특징이 있다.In this case, a) and b) of FIG. 2J are characterized in that the miniaturization circuit is wired on one surface and the miniaturization circuit is not wired on the other surface, and c) and d) are characterized in that the miniaturization circuit is wired on one surface and the other surface.
여기서 상기 전해도금은 동, 니켈, 은 등의 다양한 금속재질로 사용함도 가능하다.Here, the electroplating may be used with various metal materials such as copper, nickel, and silver.
도 2k를 참조하면, 상기 도금 레지스트(214)로 사용된 드라이 필름을 소정의 박리 공정을 통해서 제거하여 일면의 미세화 회로(200a)와 비아홀 회로(200b)를 완성하고 또는 타면의 동박(204)상에 제1도금층(208), 제2도금층(209), 제3도금층(216)으로 이루어진 그라운드면(200d)을 형성하거나, 비아홀 랜드(200c)를 형성하여 마련한다.Referring to FIG. 2K, the dry film used as the plating resist 214 is removed through a predetermined peeling process to complete the micronization circuit 200a and the via hole circuit 200b on one surface or the copper foil 204 on the other surface. The ground surface 200d including the first plating layer 208, the second plating layer 209, and the third plating layer 216 is formed on the via plate 200c, or the via hole land 200c is formed.
도 2l을 참조하면, 상기 일면에 미세화 회로(200a) 및 비아홀 회로(200b)와 타면의 그라운드면(200d) 또는 비아홀 랜드(200c)가 돌출 형성된 동박적층판(200)의 양면에 감광제가 포함된 드라이 필름(218, 220)을 재밀착하고, 도 2m에 도시된 바와 같이 동박적층판(200)을 사진 공정에 의해서 노광 및 현상하여 타면의 미세화 회로(200a)와 비아홀 회로(200b)를 위한 에칭레지스트(220a)와 일면의 전체면에 에칭레지스트(218a)를 형성한다.Referring to FIG. 2L, the photosensitive agent is dried on both surfaces of the copper foil laminated plate 200 on which one surface of the micronization circuit 200a and the via hole circuit 200b and the other surface of the ground surface 200d or the via hole land 200c are formed. The films 218 and 220 are brought into close contact with each other, and the copper-clad laminate 200 is exposed and developed by a photolithography process as shown in FIG. 2M, and the etching resist for the micronization circuit 200a and the via hole circuit 200b of the other surface ( An etching resist 218a is formed on the entire surface of 220a) and one surface thereof.
여기서 타면의 미세화 회로(200a) 및 비아홀 회로(200b)를 형성하기 위해 식각시 상기 일면에 이미 형성된 미세화 회로(200a) 및 비아홀 회로(200b)가 식각되지 않도록 전체면을 노광, 현상하여 에칭레지스트(218a)를 형성한다.In order to form the micronization circuit 200a and the via hole circuit 200b of the other surface, the entire surface is exposed and developed so that the micronization circuit 200a and the via hole circuit 200b already formed on the one surface are not etched during etching. 218a).
이때, 상기 도 2l 및 도 2m의 드라이 필름(218, 220)을 이용하는 대신에 액상감광제를 도포하여 노광 및 현상하거나 PIR(Pattern Ink Resist) 인쇄를 통해 거쳐서 미세화 회로(200a) 및 비아홀 회로(200b) 형성을 위한 에칭레지스트(218a, 220a)를 형성함도 가능하다.In this case, instead of using the dry films 218 and 220 of FIGS. 2L and 2M, a liquid photoresist is applied to expose and develop or through a pattern ink resist printing (PIR) to refine the micro circuit 200a and the via hole circuit 200b. It is also possible to form the etching resists 218a and 220a for formation.
도 2n을 참조하면, 상기 동박적층판(200)을 사진 공정에 의해서 형성된 타면의 미세화 회로(200a) 및 비아홀 회로(200b) 형성을 위하여 에칭레지스트(220a) 이외의 동박(204) 및 제1도금층(208), 제2도금층(209), 제3도금층(216)을 식각하거나, 동박(204) 및 제1도금층(208), 제2도금층(209)을 식각한 후 상기 에칭레지스트(218a, 220a)로 사용된 드라이 필름을 박리하여 타면의 미세화 회로(200a)와 비아홀 회로(200b)를 완성한다.Referring to FIG. 2N, the copper foil 204 and the first plating layer other than the etching resist 220a may be formed to form the micronized circuit 200a and the via hole circuit 200b of the other surface formed by the photolithography process. 208, the second plating layer 209, the third plating layer 216, or the copper foil 204, the first plating layer 208, and the second plating layer 209, and the etching resists 218a and 220a. The dry film used as is peeled off to complete the micronization circuit 200a and the via hole circuit 200b of the other surface.
이후 도 2o에 도시된 바와 같은 절연층(230) 형성 공정과, 도 2p에 도시된 바와 같은 금속층(240) 형성 공정을 순차적으로 수행한다.Thereafter, the insulating layer 230 forming process as shown in FIG. 2O and the metal layer 240 forming process as shown in FIG. 2P are sequentially performed.
도 2o를 참조하면, 상기 식각된 양쪽면의 회로 또는 회로 사이를 절연하기 위해서 일반적으로 사용하고 있는 폴리이미드계, 아크릴계, 에폭시계의 절연재 중에 선택하여 인쇄공정 또는 PSR 공정을 수행하거나, 폴리이미드계, 아크릴계, 에폭시계의 절연재 중에 선택하여 적층공정을 수행하여 표면 처리할 영역을 제외한 회로 및 회로 사이에 절연층(230)을 형성한다. Referring to FIG. 2O, a printing process or a PSR process may be performed by selecting among polyimide-based, acryl-based, and epoxy-based insulating materials which are generally used to insulate the circuits or circuits on both surfaces of the etched surface. The insulating layer 230 is formed between the circuit and the circuit except for the region to be surface-treated by performing a lamination process by selecting among acrylic and epoxy insulating materials.
여기서, 상기 절연체 도포 방법을 3D 프린팅 또는 잉크젯 프린팅 방식으로 회로 또는 회로 사이에 절연체를 도포함도 가능하다.Here, the method of applying the insulator may also include an insulator between the circuits or circuits by 3D printing or inkjet printing.
도 2p를 참조하면, 미세화 회로(200a)와 비아홀 회로(200b)의 전기 전도도를 향상시키기 위해서 표면 처리할 영역에 무전해 또는 전해 도금으로 니켈도금이나 금도금 또는 니켈과 금을 함께 이용하여 도금한 금속층(240)으로 형성한다.Referring to FIG. 2P, a metal layer plated using nickel plating, gold plating, or nickel and gold together by electroless or electrolytic plating in a region to be surface-treated to improve the electrical conductivity of the micronization circuit 200a and the via hole circuit 200b. And form 240.
여기서, 표면 처리할 영역에 상기 니켈도금, 금도금 대신에 OSP(Organic Solderability Preservative) 또는 은도금으로 표면처리를 선택하여 수행할 수도 있다.Here, the surface treatment may be performed by selecting the surface treatment with OSP (Organic Solderability Preservative) or silver plating instead of the nickel plating and gold plating.
이때, 상기 금속층(240)은 니켈 도금층으로 형성하는 경우에는 3 내지 7um의 두께로 형성함이 바람직하고, 금도금층으로 형성하는 경우에는 0.03 내지 0.05um의 두께로 형성함이 바람직하며, 그 이상과 이하의 두께로도 형성할 수 있다.In this case, the metal layer 240 is preferably formed with a thickness of 3 to 7um when the nickel plating layer is formed, and when formed with a gold plated layer, the metal layer 240 is preferably formed with a thickness of 0.03 to 0.05um. It can also be formed with the following thickness.
여기서, 도 2n 공정 이후에 도 2o 와 도 2p 공정은 공정 순서를 바꾸어 진행함도 가능하다.Here, after the process of FIG. 2N, the processes of FIGS. 2O and 2P may be performed by changing the process order.
이후, 후처리 공정을 거쳐서 양면 또는 다층기판의 외층면 인쇄회로기판을 완성하게 된다.Subsequently, an outer layer printed circuit board of a double-sided or multilayer board is completed through a post-treatment process.
이상에서는 본 발명을 특정의 바람직한 실시 예들을 들어 도시하고 설명하였으나, 본 발명은 상기한 실시 예들에 한정되지 아니하며 본 발명의 정신을 벗어나지 않는 범위 내에서 당해 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에 의해 다양한 변경과 수정이 가능할 것이다.The present invention has been shown and described with reference to certain preferred embodiments, but the present invention is not limited to the above-described embodiments, and the present invention is not limited to the spirit of the present invention. Various changes and modifications may be made by the user.

Claims (10)

  1. (a) 기판절연체(102)의 양면 또는 다층기판의 외층면에 동박(104)이 도포된 동박적층판(100)을 드릴 가공하여 비아홀을 형성하기 위한 관통공(106)을 형성한 후, 무전해 도금을 하여 제1도금층(108)을 형성하는 단계;(a) Drilling the copper-clad laminate 100 coated with the copper foil 104 on both surfaces of the substrate insulator 102 or the outer layer surface of the multilayer substrate to form through-holes 106 for forming via holes, and then electroless Plating to form a first plating layer 108;
    (b) 상기 제1도금층(108)이 형성된 동박적층판(100)의 양면에 감광제가 포함된 드라이 필름(110, 112)을 밀착 또는 액상 감광제를 도포하고 노광 및 현상하거나 PIR(Pattern Ink Resist) 인쇄를 통해 거쳐서 일면의 미세화 회로(100a) 및 비아홀 회로(100b)의 형성을 위한 에칭레지스트(110a)와 타면의 전체면에 에칭레지스트(112a)를 형성하는 단계; (b) Applying the dry film (110, 112) including the photosensitive agent on both sides of the copper-clad laminate (100) on which the first plating layer 108 is formed in close contact or by applying a liquid photosensitive agent, exposure and development or PIR (Pattern Ink Resist) printing Forming an etching resist (112a) on the entire surface of the etching resist (110a) and the other surface for forming the micronization circuit (100a) and the via hole circuit (100b) of one surface through;
    (c) 상기 동박적층판(100)의 양면에 형성된 에칭레지스트(110a, 112a) 이외의 동박(104) 및 제1도금층(108)을 식각하고, 상기 에칭레지스트(110a, 112a)로 사용된 드라이 필름 또는 액상 감광제 또는 PIR 잉크를 박리하여 일면에 미세화 회로(100a)와 비아홀 회로(100b)를 형성하는 단계;(c) A dry film used for etching the copper foil 104 and the first plating layer 108 other than the etching resists 110a and 112a formed on both surfaces of the copper-clad laminate 100, and used as the etching resists 110a and 112a. Or peeling off the liquid photosensitive agent or PIR ink to form the micronization circuit 100a and the via hole circuit 100b on one surface;
    (d) 상기 동박적층판(100)의 일면 또는 양면에 감광제가 포함된 드라이 필름(114)을 재밀착 또는 액상 감광제를 재도포하고 노광 및 현상하거나 PIR(Pattern Ink Resist) 재인쇄를 통해 비아홀 회로(100b)를 위한 드라이 필름(114) 또는 액상 감광제 또는 PIR 잉크의 개구부(114a)를 일면 또는 양면에 형성하는 단계;(d) Re-adhering the dry film 114 including the photosensitive agent on one or both surfaces of the copper-clad laminate 100 or reapplying the liquid photosensitive agent and exposing and developing the via film (PIR (Pattern Ink Resist)) to reprint the via hole circuit ( Forming openings 114a of the dry film 114 or the liquid photoresist or PIR ink for 100b) on one or both sides;
    (e) 상기 드라이 필름(114) 또는 액상 감광제 또는 PIR 잉크의 개구부(114a)에 전해 도금을 실시하여 제2도금층(116)을 형성한 후, 상기 드라이 필름(114) 또는 액상 감광제 또는 PIR 잉크를 박리하여 일면의 미세화 회로(100a)와 비아홀 회로(100b)를 완성하고, 또는 타면의 동박(104) 상에 제1도금층(108), 제2도금층(116)으로 이루어진 그라운드면(100d)을 형성 하거나 비아홀 랜드(100c)를 형성하여 마련하는 단계;(e) forming a second plating layer 116 by electroplating the dry film 114 or the opening 114a of the liquid photosensitive agent or PIR ink, and then using the dry film 114 or the liquid photosensitive agent or PIR ink. Peel-off completes the miniaturization circuit 100a and via hole circuit 100b of one surface, or forms the ground surface 100d which consists of the 1st plating layer 108 and the 2nd plating layer 116 on the copper foil 104 of the other surface. Or forming and providing via hole lands 100c;
    (f) 상기 동박적층판(100)의 양면에 감광제가 포함된 드라이 필름(118, 120)을 재밀착 또는 액상감광제를 재도포한 후, 동박적층판(100)을 노광 및 현상하거나 PIR 재인쇄를 통해 거쳐서 타면의 미세화 회로(100a)와 비아홀 회로(100b)를 위한 에칭레지스트(120a)와 일면의 전체면에 에칭레지스트(118a)를 형성하는 단계;(f) Re-adhering the dry films 118 and 120 including the photosensitive agent on both surfaces of the copper foil laminated plate 100 or recoating the liquid photosensitive agent, and then exposing and developing the copper foil laminated plate 100 through PIR reprinting. Forming an etching resist 120a for the micronization circuit 100a and the via hole circuit 100b of the other surface and an etching resist 118a on the entire surface of one surface;
    (g) 상기 에칭레지스트(118a,120a) 이외의 동박(104) 및 제1도금층(108), 제2도금층(116)을 식각하거나, 동박(104) 및 제1도금층(108)을 식각한 후 상기 에칭레지스트(118a, 120a)로 사용된 드라이 필름 또는 액상 감광제 또는 PIR 잉크를 박리하여 타면의 미세화 회로(100a)와 비아홀 회로(100b)를 완성하는 단계; 로 구성되는 것을 특징으로 하는 인쇄회로기판의 제조방법.(g) Etching the copper foil 104, the first plating layer 108, and the second plating layer 116 other than the etching resists 118a and 120a, or etching the copper foil 104 and the first plating layer 108 Peeling the dry film, the liquid photoresist, or the PIR ink used as the etching resists 118a and 120a to complete the micronization circuit 100a and the via hole circuit 100b of the other surface; Method of manufacturing a printed circuit board, characterized in that consisting of.
  2. 제 1항에 있어서,The method of claim 1,
    (h) 상기 단계(g) 이후에, 상기 식각된 회로 및 회로 사이를 절연하기 위해서 폴리이미드계, 아크릴계, 에폭시계 절연재 중에 선택하여 PSR 공정을 수행하거나, 3D 프린팅, 잉크젯 프린팅 중 어느 하나의 인쇄공정 또는 폴리이미드계, 아크릴계, 에폭시계 절연재 중에 선택하여 적층공정을 수행하여 표면 처리할 영역을 제외한 회로 및 회로 사이에 절연층(130)을 형성하는 단계; 를 더 포함하는 것을 특징으로 하는 인쇄회로기판의 제조방법.(h) after step (g), to insulate between the etched circuit and the circuit, a polyimide-based, acrylic-based or epoxy-based insulating material is selected to perform a PSR process, or printing of any one of 3D printing and inkjet printing. Forming an insulating layer 130 between circuits and circuits excluding a region to be surface treated by performing a lamination process by selecting among a process or a polyimide-based, acrylic-based, or epoxy-based insulating material; Method of manufacturing a printed circuit board further comprising a.
  3. 제 1항에 있어서,The method of claim 1,
    (i) 상기 단계(g) 이후에, 상기 미세화 회로(100a)와 비아홀 회로(100b)의 전기 전도도를 향상시키기 위해서 표면 처리할 영역에 무전해 또는 전해 도금으로 니켈도금이나 금도금 또는 니켈과 금을 함께 이용하여 도금한 금속층(140)으로 형성하는 단계; 를 더 포함하는 것을 특징으로 하는 인쇄회로기판의 제조방법.(i) after step (g), nickel plating or gold plating or nickel and gold may be applied to the area to be surface-treated by electroless or electrolytic plating to improve the electrical conductivity of the micronization circuit 100a and the via hole circuit 100b. Forming a plated metal layer 140 together; Method of manufacturing a printed circuit board further comprising a.
  4. 제 1항에 있어서,The method of claim 1,
    상기 제1도금층(108)은 금속재질로 동, 니켈, 카본 계열 등으로 이루어지며, 상기 제2도금층(116)은 금속재질로 동, 니켈, 은 등으로 이루어지는 것을 특징으로 하는 인쇄회로기판의 제조방법.The first plating layer 108 is made of metal, copper, nickel, carbon, and the like, and the second plating layer 116 is made of copper, nickel, silver, or the like. Way.
  5. (a) 기판절연체(202)의 양면 또는 다층기판의 외층면에 동박(204)이 도포된 동박적층판(200)을 드릴 가공하여 비아홀을 형성하기 위한 관통공(206)을 형성한 후, 무전해 도금을 하여 제1도금층(208)을 형성하고, 상기 제1도금층(208)상에 전해 도금을 수행하여 제2도금층(209)을 형성하는 단계; (a) Drilling through the copper-clad laminate 200 coated with the copper foil 204 on both surfaces of the substrate insulator 202 or the outer layer surface of the multi-layer substrate to form through holes 206 for forming via holes, and then electroless Plating to form a first plating layer 208 and performing electroplating on the first plating layer 208 to form a second plating layer 209;
    (b) 상기 제2도금층(209)이 형성된 동박적층판(200)의 양면에 감광제가 포함된 드라이 필름(210, 212)을 밀착 또는 액상 감광제를 도포하고 노광 및 현상하거나 PIR(Pattern Ink Resist) 인쇄를 통해 거쳐서 일면의 미세화 회로(200a) 및 비아홀 회로(200b) 형성을 위한 에칭레지스트(210a)와 타면의 전체면에 에칭레지스트(212a)를 형성하는 단계;(b) Applying the dry film (210, 212) including the photosensitive agent on both sides of the copper-clad laminate 200 on which the second plating layer 209 is formed, or by applying a liquid photosensitive agent, and then exposed and developed or PIR (Pattern Ink Resist) printing Forming an etching resist 210a for forming the miniaturization circuit 200a and the via hole circuit 200b on one surface and an entire surface of the other surface through the etching resist 210a;
    (c) 상기 동박적층판(200)의 양면에 형성된 에칭레지스트(210a,212a) 이외의 동박(204) 및 제1도금층(208), 제2도금층(209)을 식각하고, 상기 에칭레지스트(210a, 212a)로 사용된 드라이 필름 또는 액상 감광제 또는 PIR 잉크를 박리하여 일면의 미세화 회로(200a)와 비아홀 회로(200b)를 형성하는 단계;(c) The copper foil 204, the first plating layer 208, and the second plating layer 209 other than the etching resists 210a and 212a formed on both surfaces of the copper foil laminated plate 200 are etched, and the etching resists 210a and Peeling the dry film, the liquid photosensitive agent, or the PIR ink used as 212a) to form the micronization circuit 200a and the via hole circuit 200b of one surface;
    (d) 상기 동박적층판(200)의 일면 또는 양면에 감광제가 포함된 드라이 필름(214)을 재밀착 또는 액상 감광제를 재도포하고 노광 및 현상하거나 PIR(Pattern Ink Resist) 재인쇄를 통해 거쳐서 비아홀 회로(200b)를 위한 드라이 필름(214) 또는 액상 감광제 또는 PIR 잉크의 개구부(214a)를 일면 또는 양면에 형성하는 단계;(d) Re-adhering the dry film 214 including the photosensitive agent on one or both surfaces of the copper-clad laminate 200 or reapplying the liquid photosensitive agent and exposing and developing the via film through PIR (Pattern Ink Resist) reprinting. Forming openings 214a of the dry film 214 or the liquid photoresist or PIR ink for the 200b, on one or both sides;
    (e) 상기 드라이 필름(214) 또는 액상 감광제 또는 PIR 잉크의 개구부(214a)에 전해 도금을 실시하여 제3도금층(216)을 형성한 후, 상기 드라이 필름(214) 또는 액상 감광제 또는 PIR 잉크를 박리하여 일면의 미세화 회로(200a)와 비아홀 회로(200b)를 완성하거나, 타면의 동박(204) 상에 제1도금층(208), 제2도금층(209), 제3도금층(216)으로 이루어진 그라운드면(200d)을 형성 하거나, 비아홀 랜드(200c)를 형성하여 마련하는 단계;(e) electroplating the dry film 214 or the opening 214a of the liquid photosensitive agent or PIR ink to form a third plating layer 216, and then drying the dry film 214 or the liquid photosensitive agent or PIR ink. Peeling to complete the micronization circuit 200a and the via hole circuit 200b on one surface, or the ground composed of the first plating layer 208, the second plating layer 209, and the third plating layer 216 on the copper foil 204 on the other surface. Forming a surface 200d or forming and forming a via hole land 200c;
    (f) 동박적층판(200)의 양면에 감광제가 포함된 드라이 필름(218,220)을 재밀착 또는 액상 감광제를 재도포한 후 상기 동박적층판(200)을 노광 및 현상하거나 PIR 재인쇄를 통해 거쳐서 타면의 미세화 회로(200a)와 비아홀 회로(200b)를 위한 에칭레지스트(220a)와 일면의 전체면에 에칭레지스트(218a)를 형성하는 단계;(f) Re-adhering the dry films 218 and 220 containing photosensitizer to both surfaces of the copper-clad laminate 200 or reapplying the liquid photoresist and exposing and developing the copper-clad laminate 200 or through PIR reprinting. Forming an etching resist 220a for the micronization circuit 200a and the via hole circuit 200b and an etching resist 218a on the entire surface of one surface;
    (g) 상기 에칭레지스트(218a,220a) 이외의 동박(204) 및 제1도금층(208), 제2도금층(209), 제3도금층(216)을 식각하거나, 동박(204) 및 제1도금층(208), 제2도금층(209)을 식각한 후, 상기 에칭레지스트(218a, 220a)로 사용된 드라이 필름 또는 액상 감광제 또는 PIR 잉크를 박리하여 타면의 미세화 회로(220a)와 비아홀 회로(200b)를 완성하는 단계; 로 구성되는 것을 특징으로 하는 인쇄회로기판의 제조방법.(g) Etching the copper foil 204 and the first plating layer 208, the second plating layer 209, the third plating layer 216 other than the etching resists 218a and 220a, or the copper foil 204 and the first plating layer 208 and the second plating layer 209, and then the dry film, the liquid photosensitive agent, or the PIR ink used as the etching resists 218a and 220a is peeled off, and the micronizing circuit 220a and the via hole circuit 200b of the other surface are peeled off. Completing the step; Method of manufacturing a printed circuit board, characterized in that consisting of.
  6. 제 5항에 있어서,The method of claim 5,
    (h) 상기 단계(g) 이후에, 상기 식각된 회로 및 회로 사이를 절연하기 위해서 폴리이미드계, 아크릴계, 에폭시계 절연재 중에 선택하여 PSR 공정을 수행하거나, 3D 프린팅, 잉크젯 프린팅 중 어느 하나의 인쇄공정 또는 폴리이미드계, 아크릴계, 에폭시계 절연재 중에 선택하여 적층공정을 수행하여 표면 처리할 영역을 제외한 회로 및 회로 사이에 절연층(230)을 형성하는 단계; 를 더 포함하는 것을 특징으로 하는 인쇄회로기판의 제조방법.(h) after step (g), to insulate between the etched circuit and the circuit, a polyimide-based, acrylic-based or epoxy-based insulating material is selected to perform a PSR process, or printing of any one of 3D printing and inkjet printing. Forming an insulating layer 230 between a circuit and a circuit except for a region to be surface-treated by performing a lamination process by selecting among a process or a polyimide-based, acrylic-based, or epoxy-based insulating material; Method of manufacturing a printed circuit board further comprising a.
  7. 제 5항에 있어서,The method of claim 5,
    (i) 상기 단계(g) 이후에, 상기 미세화 회로(200a)와 비아홀 회로(200b)의 전기 전도도를 향상시키기 위해서 표면 처리할 영역에 무전해 또는 전해 도금으로 니켈도금이나 금도금 또는 니켈과 금을 함께 이용하여 도금한 금속층(240)으로 형성하는 단계; 를 더 포함하는 것을 특징으로 하는 인쇄회로기판의 제조방법.(i) after step (g), nickel plating or gold plating or nickel and gold may be applied to the area to be surface-treated by electroless or electrolytic plating in order to improve the electrical conductivity of the micronization circuit 200a and the via hole circuit 200b. Forming by using the plated metal layer 240 together; Method of manufacturing a printed circuit board further comprising a.
  8. 제 5항에 있어서,The method of claim 5,
    상기 제1도금층(208)은 금속재질로 동, 니켈, 카본계열 등으로 이루어지며, 상기 제2도금층(209) 및 제3도금층(216)은 금속재질로 동, 니켈, 은 등으로 이루어지는 것을 특징으로 하는 인쇄회로기판의 제조방법.The first plating layer 208 is made of metal, copper, nickel, carbon, etc., and the second plating layer 209 and the third plating layer 216 is made of metal, copper, nickel, silver, etc. A method of manufacturing a printed circuit board.
  9. 제1항 또는 제5항에 있어서,The method according to claim 1 or 5,
    상기 동박적층판은 금속재질로 동, 알루미늄, 니켈, 크롬 등으로 이루어지는 것을 특징으로 하는 인쇄회로기판의 제조방법.      The copper clad laminate is a metal material, the manufacturing method of a printed circuit board, characterized in that made of copper, aluminum, nickel, chromium, and the like.
  10. 제 1항 내지 제 9항 중에 어느 한 항에 따라서 제조된 인쇄회로기판.A printed circuit board manufactured according to any one of claims 1 to 9.
PCT/KR2016/003920 2016-04-15 2016-04-15 Method for manufacturing printed circuit board and printed circuit board manufactured by same method WO2017179748A1 (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050031221A (en) * 2003-09-29 2005-04-06 삼성전기주식회사 Printed circuit board without electrolytic plating lead line and manufacturing method thereof
KR100498977B1 (en) * 2002-12-31 2005-07-01 삼성전기주식회사 Method of plating the conductive layer on the wall of the cavity in E-BGA PCB
KR100723489B1 (en) * 2005-06-17 2007-05-31 삼성전자주식회사 semiconductor apparatus improving a reliability and manufacturing method the same
KR20140077441A (en) * 2012-12-14 2014-06-24 타이코에이엠피(유) Printed circuit board and manufacture method thereof
KR20140123273A (en) * 2013-04-12 2014-10-22 타이코에이엠피(유) Printed circuit board and manufacturing method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100498977B1 (en) * 2002-12-31 2005-07-01 삼성전기주식회사 Method of plating the conductive layer on the wall of the cavity in E-BGA PCB
KR20050031221A (en) * 2003-09-29 2005-04-06 삼성전기주식회사 Printed circuit board without electrolytic plating lead line and manufacturing method thereof
KR100723489B1 (en) * 2005-06-17 2007-05-31 삼성전자주식회사 semiconductor apparatus improving a reliability and manufacturing method the same
KR20140077441A (en) * 2012-12-14 2014-06-24 타이코에이엠피(유) Printed circuit board and manufacture method thereof
KR20140123273A (en) * 2013-04-12 2014-10-22 타이코에이엠피(유) Printed circuit board and manufacturing method thereof

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