WO2017179150A1 - Power conversion device and method for controlling same - Google Patents

Power conversion device and method for controlling same Download PDF

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Publication number
WO2017179150A1
WO2017179150A1 PCT/JP2016/061896 JP2016061896W WO2017179150A1 WO 2017179150 A1 WO2017179150 A1 WO 2017179150A1 JP 2016061896 W JP2016061896 W JP 2016061896W WO 2017179150 A1 WO2017179150 A1 WO 2017179150A1
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WIPO (PCT)
Prior art keywords
phase
pwm signal
signal pattern
minimum
generation unit
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PCT/JP2016/061896
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French (fr)
Japanese (ja)
Inventor
敏 川村
裕也 西守
今村　直樹
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三菱電機株式会社
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Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP2018509932A priority Critical patent/JP6377297B2/en
Priority to PCT/JP2016/061896 priority patent/WO2017179150A1/en
Publication of WO2017179150A1 publication Critical patent/WO2017179150A1/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode

Definitions

  • the present invention relates to a power conversion device that drives a motor by converting a direct current input into alternating current, and a control method for the power conversion device.
  • the present invention has been made to solve the above-described problems, and it is an object of the present invention to make it easy to ensure the bus current detection time.
  • a plurality of switching elements are turned on and off according to a three-phase PWM (Pulse Width Modulation) signal pattern, so that an inverter circuit that converts direct current into three-phase alternating current is connected to the direct current side of the inverter circuit
  • a current detection element that generates a signal corresponding to the current
  • a phase current reproduction unit that reproduces the phase current of the inverter circuit based on the signal generated in the current detection element and the three-phase PWM signal pattern, and the phase current reproduction
  • a duty generation unit that generates a duty ratio of a three-phase PWM signal pattern based on the phase current reproduced by the unit, and a magnitude relationship between the duty ratios of the three-phase PWM signal pattern generated by the duty generation unit; Classify into maximum phase with maximum duty ratio, minimum phase with minimum duty, and intermediate phase with intermediate duty When generating a three-phase PWM signal pattern based on the duty ratio generated by the determination unit and the duty generation unit, the cycle of the intermediate-phase
  • the cycle of the intermediate phase PWM signal pattern is set to be twice or more the cycle of the maximum phase or minimum phase PWM signal pattern. Current detection time can be easily secured.
  • FIG. 3 is a circuit diagram illustrating a configuration example of an inverter circuit of the power conversion device according to the first embodiment.
  • 3A and 3B are diagrams illustrating a hardware configuration example of the power conversion device according to the first embodiment. It is a graph which shows the duty ratio of the PWM signal pattern of the U phase, V phase, and W phase which were produced
  • generation part. 5 is a graph in which the center of the amplitude of the duty ratio shown in FIG. 4 is corrected to 0.5. 6 is a graph in which the duty ratios of the U-phase, V-phase, and W-phase PWM signal patterns shown in FIG.
  • a maximum phase, a minimum phase, and an intermediate phase are classified into a maximum phase, a minimum phase, and an intermediate phase. It is a graph which shows a waveform in case the duty ratio of an intermediate phase is the standard value 0.5 or more. It is a graph which shows a waveform in case the duty ratio of an intermediate phase is less than the reference value 0.5. It is a graph which shows the threshold value of the intermediate
  • 5 is a graph showing an example in which the duty ratio of the intermediate phase of the maximum phase, intermediate phase, and minimum phase PWM signal patterns in the first embodiment is 0.5 or more.
  • 6 is a graph illustrating an example in which the duty ratio of the intermediate phase of the PWM signal pattern of the maximum phase, the intermediate phase, and the minimum phase in the first embodiment is less than 0.5. It is a graph which shows the example in case the duty ratio of an intermediate phase is close to 1 of the PWM signal pattern of the maximum phase, intermediate phase, and minimum phase in Embodiment 2 of this invention.
  • Embodiment 4 of this invention It is a reference example for assisting the understanding of the rule of the PWM signal operation in Embodiment 4 of this invention, and is a graph which shows the example which maximized the time of the zero voltage vector in a PWM signal pattern.
  • 10 is a graph showing PWM signal patterns of maximum phase, intermediate phase, and minimum phase generated by the PWM signal generation unit of the fourth embodiment. It is a graph which shows the PWM signal pattern of the maximum phase, intermediate
  • 14 is a graph showing PWM signal patterns of maximum phase, intermediate phase, and minimum phase generated by a PWM signal generation unit in the power conversion device according to the sixth embodiment.
  • 14 is a graph showing PWM signal patterns of maximum phase, intermediate phase, and minimum phase generated by a PWM signal generation unit in the power conversion device according to the sixth embodiment.
  • 10 is a graph showing PWM signal patterns of a maximum phase, an intermediate phase, and a minimum phase generated by a PWM signal generation unit in a power conversion device according to an eighth embodiment. It is a graph which shows the PWM signal pattern of the maximum phase, intermediate
  • FIG. 1 is a block diagram showing a configuration example of a power conversion device 1 according to Embodiment 1 of the present invention.
  • the power conversion device 1 converts a direct current into a three-phase alternating current of U phase, V phase, and W phase and outputs it to the electric motor 10 to drive the electric motor 10.
  • the electric motor 10 is a synchronous motor using a permanent magnet, for example.
  • the electric motor 10 includes a rotor angle sensor 11 that detects the angle of the rotor.
  • the rotor angle sensor 11 detects the rotor angle of the electric motor 10 and outputs it to the power conversion device 1.
  • the illustrated power conversion apparatus 1 includes an inverter circuit 2 that converts a direct current into a three-phase alternating current by turning on and off a plurality of switching elements according to a three-phase PWM signal pattern of a U phase, a V phase, and a W phase, and an inverter circuit 2 Current detecting element 3 that is connected to the DC side of the signal generating a signal corresponding to the current, and a phase that reproduces the phase current of the inverter circuit 2 based on the signal generated in the current detecting element 3 and the three-phase PWM signal pattern.
  • a determination unit 6 that determines the magnitude relationship of the duty ratios of the signal patterns and classifies the maximum phase, the minimum phase that is the minimum, and the intermediate phase that is the middle, with the maximum duty ratio;
  • the period of the intermediate phase PWM signal pattern is set to be twice or more the period of the maximum phase or minimum phase PWM signal pattern.
  • a PWM signal generation unit 7 for performing the above operation.
  • FIG. 2 is a circuit diagram illustrating a configuration example of the inverter circuit 2 of the power conversion device 1 according to the first embodiment.
  • the inverter circuit 2 includes three phases, a U phase, a V phase, and a W phase.
  • switching elements UH, VH, WH on the upper arm side and switching elements UL, VL, WL on the lower arm side are installed.
  • the switching elements UH, UL, VH, VL, WH, WL are turned on / off according to the PWM signal pattern from the PWM signal generation unit 7 to generate a three-phase alternating current for driving the electric motor 10.
  • a current detection element 3 that generates a signal corresponding to the bus current is connected to the DC side of the inverter circuit 2.
  • the current detection element 3 is, for example, a shunt resistor or a DC converter.
  • the phase current reproduction unit 4, the duty generation unit 5, the determination unit 6, and the PWM signal generation unit 7 in the power conversion device 1 may be a processing circuit 100 that is dedicated hardware as illustrated in FIG.
  • the processor 101 may execute a program stored in the memory 102 as illustrated in 3B.
  • the processing circuit 100 is, for example, a single circuit, a composite circuit, a program An integrated processor, a parallel-programmed processor, an ASIC (Application-Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array), or a combination of these.
  • the functions of the phase current reproduction unit 4, the duty generation unit 5, the determination unit 6, and the PWM signal generation unit 7 may be realized by a plurality of processing circuits 11, or the functions of the respective units are realized by a single processing circuit 100. May be.
  • the function of each unit is software, firmware, or a combination of software and firmware. It is realized by.
  • Software or firmware is described as a program and stored in the memory 102.
  • the processor 101 reads out and executes a program stored in the memory 102, thereby realizing the function of each unit. That is, the power conversion device 1 is reproduced with the step of reproducing the phase current of the inverter circuit 2 based on the signal generated in the current detection element 3 and the three-phase PWM signal pattern when executed by the processor 101.
  • a memory 102 is provided for storing a program that results in the step of making the period of the PWM signal pattern more than twice as long. That. It can also be said that this program causes the computer to execute the procedures or methods of the phase current reproduction unit 4, the duty generation unit 5, the determination unit 6, and the PWM signal generation unit 7.
  • the processor 101 is, for example, a CPU (Central Processing Unit), a processing device, an arithmetic device, a microprocessor, a microcomputer (hereinafter referred to as a microcomputer), or a DSP (Digital Signal Processor).
  • the memory 102 is, for example, a RAM (Random Access Memory), a ROM (Read Only Memory), an EPROM (Erasable Programmable ROM), an EEPROM (Electrically EPROM), a flash memory, an SSD (Solid State Nonvolatile) or the like. It may be a semiconductor memory, a magnetic disk such as a hard disk or a flexible disk, or an optical disk such as a CD (Compact Disc) or a DVD (Digital Versatile Disc).
  • a part is implement
  • the processing circuit 100 in the power conversion device 1 can realize the above-described functions by hardware, software, firmware, or a combination thereof.
  • the phase current reproduction unit 4 detects the voltage across the shunt resistor, which is the current detection element 3, and converts the detected voltage into a bus current value. Then, the phase current reproduction unit 4 uses a method described later on the basis of the bus current value detected using the current detection element 3 and the three-phase PWM signal pattern generated by the PWM signal generation unit 7. The phase current is reproduced and output to the duty generation unit 5.
  • the duty generation unit 5 performs vector control using the three-phase phase current reproduced by the phase current reproduction unit 4 and the rotor angle of the electric motor 10 detected by the rotor angle sensor 11, and a three-phase PWM signal pattern The duty ratio is generated.
  • a known technique such as a method described in Japanese Patent No. 5300944 can be used.
  • the duty generation unit 5 outputs the duty ratio of the generated three-phase PWM signal pattern to the determination unit 6.
  • FIG. 4 is a graph showing the duty ratio of the U-phase, V-phase, and W-phase PWM signal patterns generated by the duty generator 5.
  • the duty generation unit 5 drives the switching element UH on the U-phase upper arm side, the switching element VH on the V-phase upper arm side, and the switching element WH on the W-phase upper arm side, A sinusoidal duty ratio with a phase shift is generated.
  • the reason why the waveform is discontinuous in the portion surrounded by the broken line in FIG. 4 is that the dq axis current is feedback-controlled every 4 ms in the vector control of the duty generator 5.
  • the duty generation unit 5 may perform offset correction on the duty ratio of each phase so that the center of the amplitude of the duty ratio of the U-phase, V-phase, and W-phase PWM signals is 0.5.
  • the duty generation unit 5 offsets the duty ratio of each phase so that the center of the amplitude becomes 0.5, and then outputs the duty ratio to the determination unit 6.
  • FIG. 5 is a graph in which the center of the amplitude of the duty ratio shown in FIG. 4 is corrected to 0.5. By correcting so that the center of the amplitude of the duty ratio becomes 0.5, the voltage utilization rate is improved.
  • the determination unit 6 determines the magnitude relationship between the duty ratios of the U-phase, V-phase, and W-phase PWM signal patterns generated by the duty generation unit 5, and the maximum phase with the maximum duty ratio, the minimum phase with the minimum, And the intermediate phase which is intermediate.
  • the determination unit 6 outputs the duty ratio of the three-phase PWM signal pattern and the determination result of the magnitude relationship to the PWM signal generation unit 7.
  • FIG. 6 is a graph in which the duty ratios of the U-phase, V-phase, and W-phase PWM signal patterns shown in FIG. 5 are classified into a maximum phase, a minimum phase, and an intermediate phase.
  • the determination unit 6 samples the duty ratio of the U-phase, V-phase, and W-phase PWM signal patterns generated by the duty generation unit 5 in accordance with the carrier period. Then, the determination unit 6 classifies the phase having the largest duty ratio among the duty ratios of the three phases sampled at a certain timing as the maximum phase, and sets the phase having the smallest duty ratio as the minimum phase. Classify and classify a phase having a duty ratio that is an intermediate value as an intermediate phase. In FIG. 6, at time T1, the maximum phase is switched from the W phase to the U phase.
  • the duty ratio of the W phase which is an intermediate phase, falls below 0.5.
  • the minimum phase is switched from the V phase to the W phase.
  • the duty ratio of the V phase that is the intermediate phase exceeds 0.5.
  • Times T1 to T5 in FIG. 6 are the same as the times T1 to T5 in FIG.
  • the waveforms of the maximum phase and the minimum phase are as follows.
  • the line is symmetrical with respect to a straight line having a duty ratio of 0.5. This is because the duty generation unit 5 in FIG. 5 corrects the duty ratios of the U phase, the V phase, and the W phase so that the center of the amplitude becomes 0.5.
  • the PWM signal generation unit 7 generates a PWM signal of the maximum phase, the minimum phase, and the intermediate phase based on the carrier wave having a predetermined period and the duty ratios of the maximum phase, the minimum phase, and the intermediate phase received from the determination unit 6. Generate a pattern. At that time, the PWM signal generation unit 7 operates the PWM signal pattern of the maximum phase, the minimum phase, and the intermediate phase so as to ensure the bus current detection time, and then converts the PWM signal pattern of the U phase, the V phase, and the W phase. And output to the inverter circuit 2 and the phase current reproduction unit 4.
  • phase current reproduction method by the phase current reproduction unit 4 and a PWM signal operation method by the PWM signal generation unit 7 will be described.
  • the switching elements UH and UL paired in the inverter circuit 2 is turned on, only one of VH and VL is turned on, and only one of WH and WL is turned on.
  • the state of the first set is “the switching element on the upper arm side of one phase of the three phases is on, and the switching elements on the lower arm side of the remaining two phases are on”.
  • the switching element on the lower arm side of a certain one phase is turned off, and the switching elements on the upper arm side of the remaining two phases are turned off.
  • the state of the second set is “the switching element on the lower arm side of one phase out of the three phases is on, and the switching element on the upper arm side of the remaining two phases is on”.
  • the switching element on the upper arm side of a certain one phase is turned off, and the switching elements on the lower arm side of the remaining two phases are turned off.
  • the U-phase current with the upper arm side only turned on matches the bus current.
  • the W-phase current with the lower arm side turned on becomes the reverse current of the bus current.
  • the remaining one-phase phase current is calculated as (the total value of the obtained two-phase phase currents) ⁇ ( ⁇ 1).
  • the phase current reproduction unit 4 can reproduce the three-phase phase current from the bus current value by the above method.
  • the time during which the two sets of states are maintained that is, the bus current detection time is shortened. If the bus current detection time is shortened, an accurate value cannot be detected.
  • FIG. 7 is a graph showing a waveform when the duty ratio of the intermediate phase is a reference value of 0.5 or more.
  • FIG. 8 is a graph showing a waveform when the duty ratio of the intermediate phase is less than the reference value 0.5.
  • the top waveform is the maximum phase PWM signal pattern for driving the switching element on the upper arm side.
  • the PWM signal is in the high voltage section, the switching element that has received the PWM signal is turned on.
  • the PWM signal is in the low voltage section, the switching element that has received the PWM signal is turned off.
  • the second waveform from the top is an intermediate phase PWM signal pattern for driving the switching element on the upper arm side.
  • the third waveform from the top is a minimum phase PWM signal pattern for driving the switching element on the upper arm side.
  • the fourth waveform from the top is the first carrier wave, the maximum phase threshold, and the minimum phase threshold.
  • the fifth waveform from the top is the second carrier wave and the intermediate phase threshold.
  • the sixth waveform from the top shows the actual bus current, the bus current value detected by the current detection element 3, and the bus current detection timing.
  • the PWM signal generation unit 7 generates a sawtooth wave carrier wave or a triangular wave carrier wave having a predetermined period, and uses this as a first carrier wave. 7 and 8, the first carrier wave is a sawtooth wave, the carrier period is 0.1 ms, and the carrier frequency is 10 kHz. Then, the PWM signal generation unit 7 calculates the maximum phase threshold (1-duty ratio) from the maximum phase duty ratio received from the determination unit 6 and compares it with the first carrier wave. The PWM signal generation unit 7 sets the maximum phase PWM signal pattern as a high voltage interval when (1-duty ratio) ⁇ (first carrier wave), and sets the maximum phase PWM signal pattern as a low voltage interval otherwise. And
  • the PWM signal generation unit 7 uses the minimum phase duty ratio received from the determination unit 6 as the minimum phase threshold and compares it with the first carrier wave.
  • the PWM signal generation unit 7 sets the minimum phase PWM signal pattern as a high voltage interval when (duty ratio)> (first carrier wave), and sets the minimum phase PWM signal pattern as a low voltage interval otherwise. .
  • the PWM signal generation unit 7 generates a second carrier wave that is a double cycle of the first carrier wave.
  • the second carrier wave has a waveform that is drawn for one period every two periods with respect to the first carrier wave.
  • the PWM signal generation unit 7 calculates the threshold value of the intermediate phase from the duty ratio of the intermediate phase received from the determination unit 6 and compares it with the second carrier wave. At the time of comparison, the PWM signal generator 7 changes the threshold value of the intermediate phase with a reference value 0.5 as a boundary, which is a half value of the total value of the duty ratio of the maximum phase and the duty ratio of the minimum phase.
  • the PWM signal generation unit 7 calculates the threshold value ⁇ 2 ⁇ (duty ratio) ⁇ 1 ⁇ of the intermediate phase and ⁇ 2 ⁇ (duty ratio) ⁇ 1 ⁇ > ( In the case of the second carrier wave), the intermediate phase PWM signal pattern is set as the high voltage section, and in other cases, the intermediate phase PWM signal pattern is set as the low voltage section.
  • the PWM signal generation unit 7 calculates the threshold value of the intermediate phase ⁇ 1-2 ⁇ (duty ratio) ⁇ and ⁇ 1-2 ⁇ (duty ratio) ⁇ When ( ⁇ second carrier wave), the intermediate phase PWM signal pattern is set as a high voltage interval, and otherwise, the intermediate phase PWM signal pattern is set as a low voltage interval.
  • an intermediate-phase PWM signal pattern having a period twice as long as the maximum-phase and minimum-phase PWM signal patterns is generated as shown in FIGS.
  • a low voltage section having a short duration in the maximum phase PWM signal pattern is output first, and a high voltage section having a long duration is output later.
  • a low voltage interval with a short duration is output first, and a low voltage interval with a long duration is output later.
  • the duty ratio of the intermediate phase is 0.5 or more, a high voltage section having a long duration among the PWM signal patterns of the intermediate phase is output first, and a low voltage section having a short duration is output later.
  • the duty ratio of the intermediate phase is less than 0.5, the low voltage section having a long duration among the PWM signal patterns of the intermediate phase is output first, and the high voltage section having a short duration is output later.
  • the phase current reproducing unit 4 detects the bus current in the energized state of the first set immediately before the end of the first first carrier cycle, and then the second set immediately before the end of the second first carrier cycle. It is necessary to detect the bus current in the energized state.
  • a section having a longer duration between the high voltage section and the low voltage section of the intermediate phase PWM signal pattern is arranged. Therefore, the period when the PWM signal pattern of any one of the maximum phase, the minimum phase and the intermediate phase is in the high voltage section and the remaining two phase PWM signal patterns are in the low voltage section is the first first carrier cycle. Of 0.5 or more.
  • the detection value of the current detection element 3 is stabilized by the bus current detection timing immediately before the first carrier wave returns to zero.
  • a section having a shorter duration between the high voltage section and the low voltage section of the intermediate phase PWM signal pattern is arranged.
  • the cycle of the intermediate phase PWM signal pattern is twice the cycle of the maximum phase and minimum phase PWM signal patterns, a long bus current detection time can be secured even in the second set of energized states.
  • the phase current reproduction unit 4 can be used even in a current detection circuit with a slow response. Therefore, the selection range of the microcomputer or circuit component used for the power converter 1 is expanded, and the cost increase can be suppressed. Furthermore, since the bus current detection timing is fixed to the timing immediately before the first carrier wave returns to 0, the processing is simple and the power conversion device 1 can be configured using an inexpensive low-function microcomputer. is there.
  • the PWM signal generation unit 7 may reverse the maximum phase PWM signal pattern to obtain the minimum phase PWM signal pattern. Conversely, the PWM signal generation unit 7 may invert the minimum phase PWM signal pattern to obtain the maximum phase PWM signal pattern.
  • the second carrier wave is used to generate the intermediate phase PWM signal pattern.
  • the intermediate phase of the intermediate phase as shown in FIGS. 9 and 10 is used. You may make it change a threshold value for every period of a 1st carrier wave.
  • FIG. 9 is a graph showing the threshold value of the intermediate layer compared with the first carrier wave when the duty ratio of the intermediate phase is 0.5 or more. As a result of the comparison, the PWM signal pattern of the intermediate phase shown in FIG. Generated.
  • FIG. 10 is a graph showing the threshold value of the intermediate layer compared with the first carrier wave when the duty ratio of the intermediate phase is less than 0.5. As a result of the comparison, the PWM signal pattern of the intermediate phase shown in FIG. Generated. By changing the threshold of the intermediate layer for each carrier period, one carrier wave is sufficient.
  • a sawtooth carrier wave is used, but a triangular carrier wave may be used.
  • a triangular carrier wave When a triangular carrier wave is used, a PWM signal pattern that is symmetrical with respect to the top or valley bottom of the triangular wave can be generated.
  • the width of the high voltage section and the low voltage section of the PWM signal pattern is irregularly changed, so that there are few merits of using a triangular wave carrier wave.
  • the sawtooth wave carrier wave can be generated using a timer that keeps counting pulses in one simple direction, so that the PWM signal generator 7 can be configured using an inexpensive low-function microcomputer. It is.
  • the PWM signal generation unit 7 is synchronized with a sawtooth wave carrier wave generation circuit using an analog circuit or a digital circuit, a carrier wave / threshold comparator, a reset circuit for resetting the carrier wave generation circuit, and a reset timing.
  • the hardware can be easily configured using dedicated hardware such as a sample and hold circuit that samples and holds the duty ratio from the determination unit 6.
  • the PWM signal generation unit 7 uses 0.5, which is half the total value of the duty ratios of the maximum phase and the minimum phase, as a reference value, the duty ratio of the intermediate phase crosses this reference value 0.5.
  • the phase of the intermediate phase PWM signal pattern is shifted by 180 degrees, the high voltage section and the low voltage section are output in reverse order. A specific example will be described with reference to FIGS. 11 and 12.
  • FIG. 11 is a graph showing the duty ratio of the intermediate phase and the threshold value of the intermediate phase when the duty ratio of the intermediate phase is 0.5 or more or less than 0.5.
  • Times T1 to T5 in FIG. 11 are the same as the times T1 to T5 in FIGS.
  • the threshold value of the intermediate phase is ⁇ 2 ⁇ (duty ratio) ⁇ 1 ⁇
  • the duty ratio of the intermediate phase is less than 0.5
  • the intermediate phase threshold value is ⁇ 1-2 ⁇ (duty ratio) ⁇ .
  • FIG. 12 is a graph showing PWM signal patterns before and after time T2 when the duty ratio of the W phase, which is an intermediate phase, falls below the reference value 0.5.
  • the top waveform is a U-phase PWM signal pattern which is the maximum phase.
  • the second waveform from the top is a W-phase PWM signal pattern that is an intermediate phase, and the duty ratio becomes 0.5 or more at time T2.
  • the third waveform from the top is the V-phase PWM signal pattern which is the minimum phase.
  • the PWM signal generation unit 7 generates the fourth to sixth PWM signal patterns from the top by rearranging the maximum phase, intermediate phase, and minimum phase PWM signal patterns.
  • the fourth waveform from the top is the U-phase PWM signal pattern
  • the fifth waveform from the top is the V-phase PWM signal pattern
  • the sixth waveform from the top is the W-phase PWM signal pattern.
  • the PWM signal generator 7 reverses the phase of the second carrier period at time T2 when the duty ratio of the intermediate phase becomes equal to or higher than the reference value 0.5. Therefore, as shown in FIG. 12, the phase of the PWM signal pattern immediately after the time T2 of the W phase that is the intermediate phase is shifted by 180 degrees, and the order of the high voltage section and the low voltage section is reversed. Thereby, when the duty ratio of the intermediate phase exceeds 0.5, the PWM signal pattern of the intermediate phase is not disturbed.
  • the PWM signal generation unit 7 is configured to switch the phase between the phase having the maximum duty ratio and the intermediate phase, or the switching from the minimum phase to the intermediate phase.
  • the phase of the intermediate phase PWM signal pattern may be changed. An example of the case where the phase having the maximum duty ratio and the intermediate phase are switched will be described with reference to FIGS. 11 and 13.
  • FIG. 13 is a graph showing a PWM signal pattern around time T1 when the maximum phase is switched from the W phase to the U phase.
  • the top waveform is the PWM signal pattern of the maximum phase, and the maximum phase is switched from the W phase to the U phase at time T1.
  • the second waveform from the top is the PWM signal pattern of the intermediate phase, and the intermediate phase is switched from the U phase to the W phase at time T1.
  • the third waveform from the top is the minimum phase PWM signal pattern, and the minimum phase is the V phase.
  • the PWM signal generation unit 7 generates the fourth to sixth PWM signal patterns from the top by rearranging the maximum phase, intermediate phase, and minimum phase PWM signal patterns.
  • the fourth waveform from the top is the U-phase PWM signal pattern
  • the fifth waveform from the top is the V-phase PWM signal pattern
  • the sixth waveform from the top is the W-phase PWM signal pattern.
  • the PWM signal generation unit 7 resets the phase order of the second carrier period at time T1 when the W phase is switched from the maximum phase to the intermediate phase, and generates the second carrier wave immediately after time T1. Then, the PWM signal generation unit 7 compares the second carrier wave immediately after time T1 with the threshold value of the intermediate phase, and the PWM signal generation unit 7 is high during the period when the duty ratio of the W phase that has become the intermediate phase exceeds the reference value 0.5. Outputs the voltage interval and outputs the low voltage interval after output. Therefore, as shown in FIG. 13, immediately after time T1, the cycle of the intermediate phase PWM signal pattern is reset, and the high voltage section and the low voltage section of the intermediate phase PWM signal pattern are switched.
  • the W-phase PWM signal pattern is the maximum-phase PWM signal pattern of the first carrier wave 10 kHz before time T1, and the intermediate-phase PWM signal pattern of the second carrier wave 5 kHz after time T1.
  • the W phase is switched from the maximum phase to the intermediate phase at time T1, the PWM signal pattern changes more continuously, and the torque change in the electric motor 10 becomes smaller.
  • FIG. 14 is a flowchart illustrating a method for controlling the power conversion apparatus 1.
  • the phase current reproduction unit 4 uses the current detection element 3 to say that “the switching element on the upper arm side of one phase among the three phases is on and the switching element on the lower arm side of the remaining two phases.
  • the first set of energized states where “is on” and “the switching elements on the lower arm side of one phase out of the three phases are on and the switching elements on the upper arm side of the remaining two phases are on” 2
  • the bus current value in the energized state of the set is detected.
  • step ST2 the phase current reproduction unit 4 determines the U phase, the V phase, and the W phase based on the two bus current values detected in step ST1 and the U phase, V phase, and W phase PWM signal patterns at that time. Reproduce the phase current of the W phase.
  • step ST ⁇ b> 3 the duty generation unit 5 uses the three-phase phase current reproduced by the phase current reproduction unit 4 and the rotor angle of the electric motor 10 detected by the rotor angle sensor 11 to use the U-phase, V-phase, and A duty ratio of a W-phase PWM signal pattern is generated.
  • step ST4 the determination unit 6 determines the magnitude relationship between the duty ratios of the three-phase PWM signal patterns generated by the duty generation unit 5 and classifies them into the maximum phase, the minimum phase, and the intermediate phase.
  • step ST5 the PWM signal generation unit 7 generates a PWM signal pattern of the maximum phase, the minimum phase, and the intermediate phase based on the three-phase duty ratio generated by the duty generation unit 5.
  • step ST6 the PWM signal generation unit 7 converts the maximum phase, minimum phase, and intermediate phase PWM signal patterns generated in step ST5 into U-phase, V-phase, and W-phase PWM signal patterns, and outputs them to the inverter circuit 2. Output.
  • a plurality of switching elements UH, UL, VH, VL, WH, and WL are turned on and off according to a three-phase PWM signal pattern, whereby a direct current is converted into a three-phase alternating current.
  • the current detection element 3 Based on the inverter circuit 2 for conversion to the current, the current detection element 3 connected to the DC side of the inverter circuit 2 and generating a signal corresponding to the current, the signal generated in the current detection element 3 and the three-phase PWM signal pattern
  • a phase current reproduction unit 4 that reproduces the phase current of the inverter circuit 2
  • a duty generation unit 5 that generates a duty ratio of a three-phase PWM signal pattern based on the phase current reproduced by the phase current reproduction unit 4, and a duty
  • the magnitude relationship of the duty ratio of the three-phase PWM signal pattern generated by the generation unit 5 is determined, and the maximum phase with the maximum duty ratio, the minimum phase with the minimum, and
  • the cycle of the intermediate-phase PWM signal pattern is set to the maximum phase or
  • the PWM signal generation unit 7 is configured to make the period of the minimum phase PWM signal pattern more than twice. In this power converter 1, when the phase current reproduction unit 4
  • the PWM signal generation unit 7 sets, for the maximum phase and the minimum phase, the interval with the shorter duration between the high voltage interval and the low voltage interval of the PWM signal pattern at the beginning of the cycle.
  • the arrangement may be such that, for the intermediate phase, a section having a longer duration among the high voltage section and the low voltage section of the PWM signal pattern is disposed at the beginning of the cycle.
  • the PWM signal generation unit 7 uses a value that is half of the sum of the maximum phase duty ratio and the minimum phase duty ratio as a reference value, and the intermediate phase duty ratio crosses the reference value.
  • the order of the high voltage section and the low voltage section may be reversed by shifting the phase of the intermediate phase PWM signal pattern by 180 degrees. This configuration does not disturb the intermediate phase PWM signal pattern.
  • the PWM signal generation unit 7 switches between the phase having the maximum duty ratio and the intermediate phase, or switching between the minimum phase and the intermediate phase.
  • the phase of the PWM signal pattern of the intermediate phase after the replacement may be changed.
  • the PWM signal generation unit 7 switches between a high voltage section and a low voltage section of an intermediate phase PWM signal pattern at the time of switching.
  • the PWM signal generation unit 7 inverts the PWM signal pattern of either the maximum phase or the minimum phase to obtain the PWM signal pattern of either the maximum phase or the minimum phase. It may be a configuration. With this configuration, the processing of the PWM signal generation unit 7 becomes simpler, so the power conversion device 1 can be configured using an inexpensive low-function microcomputer.
  • FIG. 15 is a diagram showing normally used voltage vectors V0 to V7.
  • the state where the switching element on the upper arm side of the U-phase, V-phase or W-phase is on corresponds to “1”, and the off-state corresponds to “0”.
  • voltage vectors V0, Va to Vf, V7 as shown in FIG. 16 corresponding to the maximum phase, intermediate phase, and minimum phase are newly introduced.
  • the maximum phase is the U phase
  • the intermediate phase is the V phase
  • the minimum phase is the W phase
  • V1 is Va
  • V2 is Vb
  • V3 is Vc
  • V4 is Vd
  • V5 is Ve
  • V6 is Vf
  • the inverse vector shown in FIGS. 15 and 16 is a voltage vector in the reverse direction of each voltage vector.
  • the relationship between the standardized time and the voltage command value is defined as follows.
  • the standardized times are tmax, tmid, and tmin defined using the time standardized to “1” for one cycle of the carrier wave.
  • tmax is the time of the high voltage interval in the maximum phase PWM signal pattern.
  • tmid is the time of the high voltage interval in the PWM signal pattern of the intermediate phase.
  • tmin is the time of the high voltage interval in the PWM signal pattern of the minimum phase.
  • vmax is a voltage command value of the maximum phase.
  • vmid is an intermediate phase voltage command value.
  • vmin is a voltage command value of the minimum phase.
  • the maximum phase, intermediate phase, and minimum phase PWM signal patterns in the first embodiment are shown in FIG. 17 when the duty ratio of the intermediate phase is 0.5 or more and less than 0.5. It is expressed as 18.
  • the duty ratio of the intermediate phase approaches 0.5, so that the bus current detection time can be secured.
  • the duty ratio of the intermediate phase is close to 0 or 1, the bus current detection time becomes shorter, and detection in a stable state becomes difficult.
  • the power conversion device 1 is required to detect the bus current corresponding to the phase current of the maximum phase because tmid is close to 1 and the time of the low voltage section of the PWM signal pattern of the intermediate phase is shortened.
  • the cycle of the intermediate phase PWM signal pattern is three times or more of the cycle of the maximum phase PWM signal pattern or the cycle of the minimum phase PWM signal pattern, whichever is shorter
  • the bus current detection time is lengthened.
  • the power converter device 1 which concerns on Embodiment 2 is the same structure on the drawing as the power converter device 1 of Embodiment 1 shown in FIG. 1, FIG. 1 is used.
  • FIG. 19 is a graph showing PWM signal patterns of the maximum phase, the intermediate phase, and the minimum phase in the power conversion device 1 according to Embodiment 2 of the present invention, and is an example when the duty ratio of the intermediate phase is close to 1.
  • the PWM signal generation unit 7 compares the predetermined upper limit value and lower limit value with the duty ratio of the intermediate phase. When the duty ratio of the intermediate phase is greater than or equal to the upper limit value, the PWM signal generation unit 7 is close to 1, and the time of the low voltage section in the PWM signal pattern of the intermediate phase is shortened, which is necessary for detecting the phase current of the maximum phase. It is determined that the time of the voltage vector Vd cannot be secured sufficiently, and a PWM signal pattern as shown in FIG. 19 is generated.
  • the PWM signal generation unit 7 repeats the output of the voltage vectors ⁇ Vd and Vf N times with the intermediate phase PWM signal pattern fixed to the high voltage side, and then the period of (N + 1) (t ⁇ tmid),
  • the voltage vector Vd is output by setting the intermediate phase PWM signal pattern to the low voltage side. Accordingly, not only the time of the voltage vector Vf for detecting the bus current corresponding to the phase current of the minimum phase but also the time of the voltage vector Vd for detecting the bus current corresponding to the phase current of the maximum phase is lengthened. .
  • the PWM signal generation unit 7 When the duty ratio of the intermediate phase is less than the lower limit value, the PWM signal generation unit 7 is close to 0 and the time of the high voltage section in the PWM signal pattern of the intermediate phase is shortened, which is necessary for detecting the phase current of the minimum phase. It is determined that sufficient time for the voltage vector Vf cannot be secured. In this case, the PWM signal generation unit 7 repeats the output of the voltage vectors ⁇ Vf and Vd N times with the intermediate phase PWM signal pattern fixed to the low voltage side, and then the period of (N + 1) (t ⁇ tmid) The voltage vector Vf is output by setting the intermediate phase PWM signal pattern to the high voltage side. Accordingly, not only the time of the voltage vector Vd for detecting the bus current corresponding to the phase current of the maximum phase but also the time of the voltage vector Vf for detecting the bus current corresponding to the phase current of the minimum phase becomes longer. .
  • the PWM signal generation unit 7 sets the cycle of the intermediate phase PWM signal pattern to the maximum phase or minimum phase PWM signal pattern as in the first embodiment. 2 times the period.
  • the PWM signal generation unit 7 of the power conversion device 1 when the duty ratio of the PWM signal pattern of the intermediate phase is equal to or higher than the predetermined upper limit value or less than the lower limit value, the PWM signal generation unit 7 of the power conversion device 1 according to the second embodiment
  • the period of the PWM signal pattern is set to be three times or more the period of the PWM signal pattern of the maximum phase or the minimum phase. With this configuration, the bus current detection time can be ensured even when the duty ratio of the intermediate phase is close to 0 or 1.
  • Embodiment 3 As described in the first embodiment, the phase current reproduction unit 4 alternately reproduces the maximum phase current and the minimum phase current by detecting the bus current continuously for two periods. However, if the bus current cannot be detected in one of the two periods because the duty ratio of the intermediate phase is close to 1 or 0 and the bus current detection time is short, only the phase current of one phase can be reproduced. Therefore, when the phase current reproduction unit 4 of the third embodiment can reproduce only one phase current continuously for two cycles or more, the phase current value of one phase that can be reproduced is A, and the two phases that cannot be reproduced. Let B and C be the phase current values.
  • the asymptote of the phase current values B and C is defined by the following equation. i is the number of repetitions of the cycle, and Ie is a coefficient determined based on the characteristics of the electric motor 10, the carrier cycle, and the like.
  • B i B i-1 + (1 / Ie) (A i / 2-B i-1 )
  • C i C i-1 + (1 / Ie) (A i / 2-C i-1 )
  • the phase current reproduction unit 4 of the power conversion device 1 according to Embodiment 3 can reproduce only the single-phase phase current continuously for two cycles or more even when the maximum phase, the minimum phase, and the intermediate phase are reproduced.
  • the phase current for the three phases can be reproduced.
  • Embodiment 4 FIG.
  • the PWM signal operation method of the first embodiment can be easily implemented, and the phase current can be reproduced in a wide range of the modulation rate.
  • a reverse voltage is applied by switching from the voltage vector Vd to the reverse voltage vector ⁇ Vd, or from the voltage vector Vf to the reverse voltage vector ⁇ Vf as shown in FIGS.
  • a useless electric current flows between the power converter device 1 and the DC bus, and heat generation, radio noise, and vibration are generated.
  • it is effective to increase the time of the zero voltage vectors V0 and V7.
  • the maximum phase PWM signal pattern and the minimum phase PWM signal pattern are maximized in the time when the high voltage section and the low voltage section match, and the intermediate phase PWM signal pattern is also the maximum phase and minimum phase PWM signal. It is preferable that the time corresponding to the high voltage section and the low voltage section of the signal pattern is long.
  • the torque of the electric motor 10 is determined by the phase current.
  • the phase current is determined by the voltage difference between the U phase, the V phase, and the W phase.
  • the carrier period is sufficiently short with respect to the change time of the bus current, and the phase voltage is proportional only to the duty ratio. Therefore, if the PWM signal pattern for reproducing the phase current from the bus current is maintained at (tmax-tmid) and (tmid-tmin), the phase of the PWM signal pattern of each phase and the magnitude of the duty ratio are It may be changed. Therefore, in the fourth embodiment, the PWM signal generation unit 7 operates the PWM signal patterns of the maximum phase, the intermediate phase, and the minimum phase according to the following rules (1) to (3).
  • FIG. 1 is used since the power converter device 1 which concerns on Embodiment 4 is the same structure on the drawing as the power converter device 1 of Embodiment 1 shown in FIG. 1, FIG. 1 is used.
  • the following rules (4) and (5) may be added to the rules (1) to (3).
  • Rule (4) The carrier wave used by the PWM signal generator 7 is of one type and has a constant period.
  • Rule (5) The bus current detection timing is equally spaced.
  • Rule (6) Increase the bus current detection time.
  • Rule (7) The number of times of switching of the switching elements of the inverter circuit 2 is reduced.
  • Rule (8) Reduce the current going to the DC power supply.
  • FIG. 20 An example in which the time of the zero voltage vector in the PWM signal pattern is maximized by the above rule is shown in FIG.
  • the example in FIG. 20 is a reference example for helping understanding of the above rules, and is not a PWM signal pattern actually generated by the PWM signal generation unit 7 of the fourth embodiment. Only in FIG. 20, the periods of the PWM signal patterns of the maximum phase, the intermediate phase, and the minimum phase are the same. In the example of FIG. 20, the high voltage period of the PWM signal pattern of the maximum phase, the intermediate phase, and the minimum phase starts at the same time, thereby maximizing the time during which all three phases are high voltage.
  • the time during which the three phases are low is maximized.
  • the zero voltage vector V7 is obtained during the first tmin of the cycle
  • the zero voltage vector V0 is obtained during the last (1-tmax) of the cycle.
  • FIG. 21 is a graph showing PWM signal patterns of the maximum phase, the intermediate phase, and the minimum phase generated by the PWM signal generation unit 7 of the fourth embodiment according to the above rules.
  • the PWM signal generation unit 7 changes the PWM signal pattern shown in FIG. 17 to the PWM signal pattern shown in FIG.
  • the duty ratio of the intermediate phase is 0.5 or more
  • the cycle of the PWM signal pattern of the intermediate phase is twice the cycle of the PWM signal pattern of the minimum phase.
  • the PWM signal generator 7 is fixed to the high voltage side by changing the phase of the maximum phase PWM signal pattern.
  • the PWM signal generation unit 7 determines tmid and tmin according to the above rules (1) to (3) while maintaining (tmax-tmid) and (tmid-tmin), and outputs the PWM signal pattern of the intermediate phase and the minimum phase. Generate. Further, the PWM signal generation unit 7 arranges tmid and tmin on the leading side of the cycle so that the time of the zero voltage vector V7 becomes long. However, since the cycle of the intermediate phase is twice the cycle of the minimum phase, the low voltage section of the PWM signal pattern of the intermediate phase appears once every two cycles of the minimum phase. Thereby, the waveform shown in FIG. 21 is generated. In the PWM signal pattern of FIG. 21, the voltage vectors Vf and Vd appear alternately for each carrier cycle, so that the bus current corresponding to the maximum phase current and the bus current corresponding to the minimum phase current can be detected alternately. .
  • the PWM signal generator 7 fixes the PWM signal pattern of the minimum phase to the low voltage side by changing the phase.
  • the PWM signal generation unit 7 determines tmax and tmid according to the above rules (1) to (3) while maintaining (tmax-tmid) and (tmid-tmin), and determines the PWM signal pattern of the maximum phase and the intermediate phase. Generate. Further, the PWM signal generation unit 7 arranges tmax and tmid on the end side of the cycle so that the time of the zero voltage vector V0 becomes longer.
  • the cycle of the intermediate phase is twice the cycle of the maximum phase, the high voltage section of the PWM signal pattern of the intermediate phase appears once every two cycles of the maximum phase. Thereby, even when the duty ratio of the intermediate phase is less than 0.5, the voltage vectors Vf and Vd appear alternately for each carrier cycle.
  • the PWM signal generation unit 7 of the power conversion device 1 fixes the maximum phase PWM signal pattern to the high voltage side or the minimum phase PWM signal pattern to the low voltage side. It is the structure to do. Thereby, it is possible to maximize the time of the zero voltage vector, and it is possible to prevent useless current from flowing between the inverter circuit 2 and the DC bus.
  • the PWM signal generation unit 7 operates the PWM signal pattern so that the time of the zero voltage vector V7 becomes longer when the duty ratio of the intermediate phase is 0.5 or more, and is less than 0.5. In some cases, the PWM signal pattern was manipulated so that the time of the zero voltage vector V0 was long. On the other hand, in the fifth embodiment, the PWM signal generation unit 7 operates the PWM signal pattern so that the zero voltage vectors V7 and V0 are switched every other period of the carrier wave. In addition, since the power converter device 1 which concerns on Embodiment 5 is the same structure on the drawing as the power converter device 1 of Embodiment 1 shown in FIG. 1, FIG. 1 is used.
  • FIG. 22 is a graph showing PWM signal patterns of the maximum phase, the intermediate phase, and the maximum phase generated by the PWM signal generation unit 7 of the fifth embodiment.
  • the PWM signal generation unit 7 fixes the minimum phase PWM signal pattern on the low voltage side for the carrier periods P1 and P3, and maximizes the time of the zero voltage vector V0 according to the above rules (1) to (3). Manipulate phase and intermediate phase PWM signal patterns. Further, the PWM signal generation unit 7 fixes the maximum phase PWM signal pattern on the high voltage side for the carrier periods P2 and P4 so that the time of the zero voltage vector V7 becomes longer according to the rules (1) to (3).
  • the intermediate phase and minimum phase PWM signal patterns are manipulated.
  • the times of the zero voltage vectors V0 and V7 are the same, so half the total value of the maximum phase duty ratio and the minimum phase duty ratio is 0.5. .
  • a PWM signal pattern with a long bus current detection time is obtained.
  • the waveforms of the PWM signal pattern of the maximum phase, the intermediate phase, and the minimum phase are symmetrical with respect to the midpoint of the zero voltage vector V0 or V7. It becomes a waveform.
  • the PWM signal pattern has a symmetrical waveform, a current waveform with less distortion can be obtained.
  • the PWM signal generation unit 7 of the power conversion device 1 fixes the cycle of fixing the maximum phase PWM signal pattern to the high voltage side and the minimum phase PWM signal pattern to the low voltage side. It is the structure which repeats the period to fix. With this configuration, the waveforms of the PWM signal patterns of the maximum phase, the intermediate phase, and the minimum phase can be made symmetrical, and a current with less distortion can be output to 10.
  • Embodiment 6 FIG.
  • the power converter device 1 which concerns on Embodiment 6 is the same structure on the drawing as the power converter device 1 of Embodiment 1 shown in FIG. 1, FIG. 1 is used.
  • FIG. 23 is a graph illustrating PWM signal patterns of the maximum phase, the intermediate phase, and the minimum phase generated by the PWM signal generation unit 7 according to the sixth embodiment, where the duty ratio of the intermediate phase is 0.5 or more. It is an example.
  • the PWM signal generation unit 7 determines that the time of the voltage vector Vd in the second carrier cycle is short as shown in FIG. 23, the voltage vector Vf that has been output so far at the time T11 when the first carrier cycle ends.
  • the reverse voltage vector -Vd is output by setting the maximum phase PWM signal pattern to be maintained on the high voltage side to output the zero voltage vector V7 on the low voltage side. The time of this reverse voltage vector -Vd is assumed to be tdc.
  • the PWM signal generation unit 7 extends the time of the low voltage section of the PWM signal pattern of the intermediate phase and the minimum phase in the second carrier cycle by tdc. Thereby, the time of the voltage vector Vd is extended, and the detection time of the bus current corresponding to the phase current of the maximum phase becomes longer.
  • FIG. 24 is a graph showing PWM signal patterns of the maximum phase, the intermediate phase, and the minimum phase generated by the PWM signal generation unit 7 of the sixth embodiment, where the duty ratio of the intermediate phase is less than 0.5. It is an example.
  • the PWM signal generation unit 7 determines that the time of the voltage vector Vf in the second carrier cycle is short as shown in FIG. 24, the voltage vector Vd that has been output until then at the time T12 when the first carrier cycle ends.
  • the reverse voltage vector -Vf is output by setting the minimum phase PWM signal pattern to be maintained on the low voltage side to output the zero voltage vector V0 on the high voltage side. The time of this reverse voltage vector -Vf is assumed to be tfc.
  • the PWM signal generation unit 7 extends the time of the high voltage section of the PWM signal pattern of the maximum phase and the intermediate phase in the second carrier cycle by tfc. Thereby, the time of the voltage vector Vf is extended, and the detection time of the bus current corresponding to the phase current of the minimum phase becomes longer.
  • the PWM signal generation unit 7 determines that the time of the voltage vector Vd or Vf is short when the duty ratio of the intermediate phase is equal to or higher than the upper limit value or lower than the lower limit value as described in the second embodiment, for example. That's fine. tdc and tfc are, for example, times required for bus current detection, and are defined in advance in the PWM signal generation unit 7.
  • FIG. 25 is a graph showing the PWM signal patterns of the maximum phase, the intermediate phase, and the minimum phase generated by the PWM signal generation unit 7 of the sixth embodiment.
  • the PWM signal generation unit 7 when the modulation rate is low, both the time of the voltage vector Vd and the time of the voltage vector Vf are shortened.
  • the PWM signal generation unit 7 generates the reverse voltage vector -Vd by the method shown in FIG. 23 to lengthen the time of the voltage vector Vd for detecting the bus current, as shown in FIG.
  • the reverse voltage vector -Vf is generated by the method to increase the time of the voltage vector Vf for detecting the bus current.
  • the PWM signal generation unit 7 of the power conversion device 1 when the PWM signal generation unit 7 of the power conversion device 1 according to the sixth embodiment generates a PWM signal pattern using a sawtooth wave carrier, the PWM of the maximum phase at the time T11 when the carrier cycle ends.
  • the signal pattern is set to a low voltage section for a predetermined time tdc, and the low voltage sections of the intermediate phase and minimum phase PWM signal patterns in the period immediately after the time T11 are extended by a predetermined time tdc.
  • the PWM signal pattern of the minimum phase is determined in advance at time T12 when the carrier cycle ends.
  • the high voltage section is set for the time tfc, and the high voltage sections of the maximum-phase and intermediate-phase PWM signal patterns in the period immediately after the time point T12 are extended by a predetermined time tfc.
  • FIG. 26, FIG. 27 and FIG. 28 are graphs showing the PWM signal patterns of the maximum phase, intermediate phase and minimum phase generated by the PWM signal generation unit 7 of the sixth embodiment, and an example when a triangular wave carrier is used. It is.
  • the phase current reproduction unit 4 detects the bus current just before the top or valley bottom of the triangular wave carrier, that is, immediately before the time points T11 and T12 when the change direction of the value of the triangular wave carrier is reversed.
  • the PWM signal generation unit 7 reduces the maximum-phase PWM signal pattern by time tdc at time T11 when the change direction of the triangular wave carrier value is reversed.
  • the voltage period the low voltage period of the PWM signal pattern of the intermediate phase and the minimum phase in the period immediately after the time point T11 is extended by a predetermined time tdc.
  • the PWM signal generation unit 7 displays the PWM signal pattern of the minimum phase in the period immediately after time T12 when the change direction of the triangular wave carrier value is reversed.
  • the high voltage section is set for a predetermined time tfc, and the high voltage sections of the maximum phase and intermediate phase PWM signal patterns in the period immediately after the time T12 are extended by the predetermined time tfc. Further, when the modulation rate is low and the time of the voltage vector Vd and the time of the voltage vector Vf are both short, the PWM signal generation unit 7 is shown in FIG. 28 by combining the methods described in FIGS. A PWM signal pattern may be generated. With the above configuration, even when a triangular wave carrier is used, the bus current detection time can be ensured as in the case of using a sawtooth wave carrier.
  • Embodiment 7 FIG.
  • the power conversion device 1 according to the seventh embodiment has the same configuration as the power conversion device 1 according to the first embodiment shown in FIG.
  • FIG. 29 is a graph showing PWM signal patterns of the maximum phase, intermediate phase, and minimum phase generated by the PWM signal generation unit 7 of the seventh embodiment, and the duty ratio of the intermediate phase is a reference value of 0.5 or more.
  • the waveforms before operation of the maximum phase, intermediate phase, and minimum phase PWM signal patterns shown in FIG. 29 are the same as the waveforms of the maximum phase, intermediate phase, and minimum phase PWM signal patterns in the carrier periods P1 and P2 shown in FIG.
  • the PWM signal generator 7 outputs the voltage vector Vd only once every two carrier waves. Manipulate the phase PWM signal pattern.
  • the PWM signal generation unit 7 sets the start position of the high voltage interval of the intermediate phase PWM signal pattern shown in FIG. 22 as the maximum phase PWM signal pattern in the period excluding the zero voltage vectors V0 and V7.
  • the PWM signal pattern in the high voltage section and the minimum phase is shifted to time T21 when it becomes the low voltage section.
  • the PWM signal generation unit 7 shifts the end position of the high voltage section by the amount by which the start position of the high voltage section of the intermediate phase PWM signal pattern is shifted.
  • the time of voltage vector Vd in FIG. 29 is twice the time of voltage vector Vd of carrier cycle P2 in FIG. 22, and the detection time of the bus current corresponding to the phase current of the maximum phase is lengthened.
  • FIG. 30 is a graph showing the PWM signal patterns of the maximum phase, the intermediate phase, and the minimum phase generated by the PWM signal generation unit 7 of the seventh embodiment, and the duty ratio of the intermediate phase is less than the reference value 0.5.
  • the waveforms of the maximum phase, intermediate phase, and minimum phase PWM signal patterns shown in FIG. 30 before operation are the same as the waveforms of the maximum phase, intermediate phase, and minimum phase PWM signal patterns in the carrier periods P2 and P3 shown in FIG.
  • the PWM signal generator 7 outputs the voltage vector Vf only once every two carrier waves in order to increase the time of the voltage vector Vf for detecting the bus current corresponding to the phase current of the minimum phase. Manipulate the phase PWM signal pattern.
  • the PWM signal generation unit 7 determines the start position of the low voltage interval of the intermediate phase PWM signal pattern shown in FIG. 22 as the maximum phase PWM signal pattern in the period excluding the zero voltage vectors V0 and V7.
  • the PWM signal pattern in the high voltage section and the minimum phase is shifted to time T22 when it becomes the low voltage section. Further, the PWM signal generation unit 7 shifts the end position of the low voltage section by the amount by which the start position of the low voltage section of the intermediate phase PWM signal pattern is shifted.
  • the time of voltage vector Vf in FIG. 30 is twice the time of voltage vector Vf of carrier period P3 in FIG. 22, and the detection time of the bus current corresponding to the phase current of the minimum phase becomes longer.
  • the PWM signal generation unit 7 of the power conversion device 1 uses the half value of the total value of the maximum phase duty ratio and the minimum phase duty ratio as the reference value, and the intermediate phase duty
  • the maximum phase PWM signal pattern in the period excluding the zero voltage vector where the output voltage of the inverter circuit 2 is zero is indicated as the start position of the high voltage interval of the intermediate phase PWM signal pattern.
  • the configuration is such that the PWM signal pattern in the high voltage section and the minimum phase is shifted to time T21 when the low voltage section is reached, and the end position is also shifted by the amount by which the start position is shifted.
  • the PWM signal generation unit 7 excludes the start position of the low voltage section of the PWM signal pattern of the intermediate phase from the zero voltage vector where the output voltage of the inverter circuit becomes zero when the duty ratio of the intermediate phase is less than the reference value. In this period, the maximum phase PWM signal pattern is shifted to a time T22 in which the minimum phase PWM signal pattern is in the high voltage section and the minimum phase PWM signal pattern is in the low voltage section, and the end position is shifted by the shift of the start position. With this configuration, it is possible to lengthen the bus current detection time as compared with the fifth embodiment. Furthermore, since no voltage vector other than voltage vectors Vd, Vf, V0, and V7 is output, useless current does not flow to the bus.
  • Embodiment 8 FIG. Although the reverse voltage vector is not output in the PWM signal operation method of the seventh embodiment, the bus current detection time cannot be longer than twice the bus current detection time by the PWM signal operation method of the fifth embodiment. When it is necessary to further increase the bus current detection time because the response of the current detection circuit used for the phase current reproduction unit 4 is slow, the bus current detection time is set to 2 by the PWM signal operation method of the eighth embodiment. It is possible to make it longer than twice. In addition, since the power converter device 1 which concerns on Embodiment 8 is the same structure on the drawing as the power converter device 1 of Embodiment 1 shown in FIG. 1, FIG. 1 is used.
  • FIG. 31 is a graph showing PWM signal patterns of the maximum phase, intermediate phase, and minimum phase generated by the PWM signal generation unit 7 of the eighth embodiment, and the duty ratio of the intermediate phase is a reference value of 0.5 or more.
  • Waveforms before operation of the maximum phase, intermediate phase, and minimum phase PWM signal patterns shown in FIG. 31 are the same as the waveforms of the maximum phase, intermediate phase, and minimum phase PWM signal patterns shown in FIG.
  • the PWM signal generator 7 starts the position of the high voltage section of the PWM signal pattern in the intermediate phase in order to make the time of the voltage vector Vd for detecting the bus current corresponding to the phase current of the maximum phase longer than the time in FIG. Is shifted to the advance side from the time T21.
  • the PWM signal generation unit 7 shifts the end position of the high voltage section by the amount by which the start position of the high voltage section of the intermediate phase PWM signal pattern is shifted. Thereby, the time of voltage vector Vd in FIG. 31 becomes longer than the time of voltage vector Vd in FIG. 29, and the detection time of the bus current corresponding to the phase current of the maximum phase becomes further longer.
  • FIG. 32 is a graph showing PWM signal patterns of the maximum phase, the intermediate phase, and the minimum phase generated by the PWM signal generation unit 7 of Embodiment 8, and the duty ratio of the intermediate phase is less than the reference value 0.5.
  • the waveforms before operation of the maximum phase, intermediate phase, and minimum phase PWM signal patterns shown in FIG. 32 are the same as the waveforms of the maximum phase, intermediate phase, and minimum phase PWM signal patterns shown in FIG.
  • the PWM signal generator 7 starts the position of the low voltage section of the PWM signal pattern of the intermediate phase in order to make the time of the voltage vector Vf for detecting the bus current corresponding to the phase current of the minimum phase longer than the time in FIG. Is shifted to the advance side with respect to time T22.
  • the PWM signal generation unit 7 shifts the end position of the low voltage section by the amount by which the start position of the low voltage section of the intermediate phase PWM signal pattern is shifted. Thereby, the time of voltage vector Vf in FIG. 32 becomes longer than the time of voltage vector Vf in FIG. 30, and the detection time of the bus current corresponding to the phase current of the minimum phase becomes further longer.
  • the PWM signal generation unit 7 of the power conversion device 1 determines the start position of the high voltage section of the intermediate phase PWM signal pattern when the intermediate phase duty ratio is greater than or equal to the reference value.
  • the maximum phase PWM signal pattern in the period excluding the zero voltage vector is shifted to the advance side from the time T21 in which the minimum phase PWM signal pattern is in the high voltage section and the minimum phase PWM signal pattern is in the low voltage section.
  • the PWM signal generation unit 7 determines the start position of the low voltage section of the PWM signal pattern of the intermediate phase as the maximum phase PWM in the period excluding the zero voltage vector.
  • the signal pattern is shifted to the advance side from time T22 when the PWM signal pattern in the high voltage section and the minimum phase PWM signal pattern is in the low voltage section.
  • the voltage vector Vb or Ve is generated by the operation of the intermediate phase PWM signal pattern.
  • the current flowing back through the bus can be reduced.
  • Embodiment 9 FIG.
  • the bus current detection time is extended by generating the voltage vector Vb or Ve.
  • the cycle of the intermediate phase PWM signal pattern is set to be three times or more the cycle of the maximum phase or minimum phase PWM signal pattern.
  • the bus current detection time at the end of the period of the PWM signal pattern is lengthened.
  • FIG. 1 since the power converter device 1 which concerns on Embodiment 9 is the same structure on the drawing as the power converter device 1 of Embodiment 1 shown in FIG. 1, FIG. 1 is used.
  • FIG. 33 is a graph showing the PWM signal patterns of the maximum phase, the intermediate phase, and the minimum phase generated by the PWM signal generation unit 7 of the ninth embodiment, and is an example when the duty ratio of the intermediate phase is close to 1. .
  • the PWM signal generation unit 7 compares the predetermined upper limit value and lower limit value with the duty ratio of the intermediate phase. When the duty ratio of the intermediate phase is greater than or equal to the upper limit value, the PWM signal generation unit 7 determines that the time of the voltage vector Vd necessary for detecting the phase current of the maximum phase cannot be sufficiently secured, and the PWM signal as shown in FIG. Generate a signal pattern.
  • FIG. 33 is a graph showing the PWM signal patterns of the maximum phase, the intermediate phase, and the minimum phase generated by the PWM signal generation unit 7 of the ninth embodiment, and is an example when the duty ratio of the intermediate phase is close to 1. .
  • the PWM signal generation unit 7 compares the predetermined upper limit value and lower limit value with the duty ratio of the intermediate phase. When the duty ratio of the
  • the PWM signal generation unit 7 maximizes the time of the zero voltage vector by the PWM signal operation method described in the seventh embodiment to obtain a PWM signal pattern of the carrier cycle P11 shown in FIG.
  • the waveform of the PWM signal pattern of the carrier cycle P11 shown in FIG. 33 is the same as the waveform of the PWM signal pattern of the first carrier cycle shown in FIG.
  • the PWM signal generation unit 7 outputs a PWM signal pattern of the carrier cycle P12 composed of the voltage vectors V7 and Vf n-1 times.
  • the PWM signal generation unit 7 multiplies the voltage vector Vd in the PWM signal pattern of the second carrier cycle shown in FIG. 29 to obtain a PWM signal pattern of the carrier cycle P13 shown in FIG. In this way, the time of the voltage vector Vd can be extended without changing the duty ratio, and the current flowing back to the bus can be reduced by eliminating the generation of an extra voltage vector.
  • the PWM signal generator 7 determines that the time of the voltage vector Vf necessary for detecting the phase current of the minimum phase cannot be sufficiently secured when the duty ratio of the intermediate phase is less than the lower limit value. In that case, the PWM signal generation unit 7 maximizes the time of the zero voltage vector by the PWM signal operation method described in the seventh embodiment, and outputs the same waveform as the PWM signal pattern of the first carrier cycle shown in FIG. To do. Next, the PWM signal generation unit 7 outputs the PWM signal pattern of the carrier cycle composed of the voltage vectors V0 and Vd n-1 times. Finally, the PWM signal generation unit 7 outputs a waveform obtained by multiplying the voltage vector Vf in the PWM signal pattern of the second carrier cycle shown in FIG. 30 by n times. In this way, the time of the voltage vector Vf can be extended without changing the duty ratio, and the current flowing back to the bus can be reduced by eliminating the generation of an extra voltage vector.
  • the PWM signal generation unit 7 may use either of the zero voltage vectors V0 and V7.
  • the number of switchings is obtained by using the zero voltage vector V0 after the voltage vector Vd for detecting the bus current corresponding to the phase current of the maximum phase. Can be reduced.
  • the duty ratio of the intermediate phase is less than the lower limit value, the number of times of switching can be reduced by using the zero voltage vector V7 after the voltage vector Vf for detecting the bus current corresponding to the phase current of the minimum phase.
  • the PWM signal generation unit 7 may use either of the zero voltage vectors V0 and V7.
  • the PWM signal generation unit 7 of the power conversion device 1 according to the ninth embodiment is similar to the first embodiment in that the duty ratio of the intermediate-phase PWM signal pattern is equal to or higher than a predetermined upper limit value or When it is less than the lower limit value, the period of the PWM signal pattern of the intermediate phase is set to be three times or more the period of the PWM signal pattern of the maximum phase or the minimum phase. With this configuration, the bus current detection time can be ensured even when the duty ratio of the intermediate phase is close to 0 or 1 in the PWM signal operation method after the fourth embodiment.
  • the power conversion device can secure a bus current detection time by an easy operation of a PWM signal pattern, and can use an inexpensive low-function microcomputer. It is suitable for use in an electric motor that drives an actuator.

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Abstract

A determination unit (6) of a power conversion device (1) determines a magnitude relation among the duty ratios of U-phase, V-phase, and W-phase and categorizes the phases into a maximum phase, a minimum phase, and an intermediate phase. A PWM signal generation unit (7) makes the PWM signal pattern cycle of the intermediate phase twice the PWM signal pattern cycle of the maximum phase and the minimum phase. A phase current reproduction unit (4) uses a current detection element (3) connected to the DC side of an inverter circuit (2) to detect bus-line current in each PWM signal pattern cycle of the maximum phase and the minimum phase.

Description

電力変換装置およびその制御方法Power converter and control method thereof
　この発明は、直流の入力を交流に変換して電動機を駆動する電力変換装置、およびこの電力変換装置の制御方法に関するものである。 The present invention relates to a power conversion device that drives a motor by converting a direct current input into alternating current, and a control method for the power conversion device.
　多相電力変換装置を用いて電動機を駆動するにあたり、低価格化を目的として、複数の高価な絶縁型電流検出器を使用して電動機に通電される各相の相電流を検出する代わりに、直流電源とインバータ回路のブリッジとの間の直流母線電流を測定して各相の相電流を再現する方法が考案されてきた。例えば特許文献１では、３相電力変換装置でそれまでもっぱら回路保護に使用されていた、シャント抵抗または直流変換器（ＤＣ－ＣＴ）が検出する母線電流をサンプルホールドし、サンプルホールドした母線電流と電動機に対する通電パターンとの組み合わせで相電流を再現する基本的な方法が述べられている。 When driving a motor using a multiphase power converter, instead of detecting the phase current of each phase that is energized to the motor using a plurality of expensive insulated current detectors, for the purpose of reducing the price, Methods have been devised to measure the DC bus current between the DC power supply and the inverter circuit bridge to reproduce the phase current of each phase. For example, in Patent Document 1, a bus current detected by a shunt resistor or a DC converter (DC-CT), which has been used exclusively for circuit protection in a three-phase power converter until now, is sampled and held. A basic method for reproducing a phase current in combination with an energization pattern for an electric motor is described.
特開平２－１９７２９５号公報Japanese Patent Laid-Open No. 2-197295
　従来、母線電流から相電流を再現する場合、シャント抵抗または直流変換器の出力が安定するまでに時間を要するので、母線電流検出時に電動機に対する通電パターンをある一定時間以上維持する必要があった。つまり、母線電流検出時間を確保するために通電パターンを操作する必要があるという課題があった。 Conventionally, when the phase current is reproduced from the bus current, it takes time until the output of the shunt resistor or the DC converter is stabilized. Therefore, when the bus current is detected, it is necessary to maintain the energization pattern for the motor for a certain time or more. That is, there is a problem that it is necessary to operate the energization pattern in order to secure the bus current detection time.
　この発明は、上記のような課題を解決するためになされたもので、母線電流検出時間の確保を容易にすることを目的とする。 The present invention has been made to solve the above-described problems, and it is an object of the present invention to make it easy to ensure the bus current detection time.
　この発明に係る電力変換装置は、複数のスイッチング素子が３相のＰＷＭ（Ｐｕｌｓｅ　Ｗｉｄｔｈ　Ｍｏｄｕｌａｔｉｏｎ）信号パターンに従いオンオフすることで、直流を３相交流に変換するインバータ回路と、インバータ回路の直流側に接続され、電流に対応する信号を発生する電流検出素子と、電流検出素子に発生した信号と３相のＰＷＭ信号パターンとに基づいてインバータ回路の相電流を再現する相電流再現部と、相電流再現部により再現された相電流に基づいて３相のＰＷＭ信号パターンのデューティ比を生成するデューティ生成部と、デューティ生成部により生成された３相のＰＷＭ信号パターンのデューティ比の大小関係を判定し、デューティ比が最大となる最大相、最小となる最小相および中間となる中間相に分類する判定部と、デューティ生成部により生成されたデューティ比に基づいて３相のＰＷＭ信号パターンを生成する際、中間相のＰＷＭ信号パターンの周期を、最大相または最小相のＰＷＭ信号パターンの周期の２倍以上にするＰＷＭ信号生成部とを備えるものである。 In the power conversion device according to the present invention, a plurality of switching elements are turned on and off according to a three-phase PWM (Pulse Width Modulation) signal pattern, so that an inverter circuit that converts direct current into three-phase alternating current is connected to the direct current side of the inverter circuit A current detection element that generates a signal corresponding to the current, a phase current reproduction unit that reproduces the phase current of the inverter circuit based on the signal generated in the current detection element and the three-phase PWM signal pattern, and the phase current reproduction A duty generation unit that generates a duty ratio of a three-phase PWM signal pattern based on the phase current reproduced by the unit, and a magnitude relationship between the duty ratios of the three-phase PWM signal pattern generated by the duty generation unit; Classify into maximum phase with maximum duty ratio, minimum phase with minimum duty, and intermediate phase with intermediate duty When generating a three-phase PWM signal pattern based on the duty ratio generated by the determination unit and the duty generation unit, the cycle of the intermediate-phase PWM signal pattern is 2 of the cycle of the maximum-phase or minimum-phase PWM signal pattern. And a PWM signal generation unit for doubling or more.
　この発明によれば、３相のＰＷＭ信号パターンを生成する際、中間相のＰＷＭ信号パターンの周期を、最大相または最小相のＰＷＭ信号パターンの周期の２倍以上にするようにしたので、母線電流検出時間を容易に確保することができる。 According to the present invention, when generating the three-phase PWM signal pattern, the cycle of the intermediate phase PWM signal pattern is set to be twice or more the cycle of the maximum phase or minimum phase PWM signal pattern. Current detection time can be easily secured.
この発明の実施の形態１に係る電力変換装置の構成例を示すブロック図である。It is a block diagram which shows the structural example of the power converter device which concerns on Embodiment 1 of this invention. 実施の形態１に係る電力変換装置のインバータ回路の構成例を示す回路図である。FIG. 3 is a circuit diagram illustrating a configuration example of an inverter circuit of the power conversion device according to the first embodiment. 図３Ａおよび図３Ｂは、実施の形態１に係る電力変換装置のハードウェア構成例を示す図である。3A and 3B are diagrams illustrating a hardware configuration example of the power conversion device according to the first embodiment. デューティ生成部により生成されたＵ相、Ｖ相およびＷ相のＰＷＭ信号パターンのデューティ比を示すグラフである。It is a graph which shows the duty ratio of the PWM signal pattern of the U phase, V phase, and W phase which were produced | generated by the duty production | generation part. 図４に示したデューティ比の振幅の中心を０．５に補正したグラフである。5 is a graph in which the center of the amplitude of the duty ratio shown in FIG. 4 is corrected to 0.5. 図５に示したＵ相、Ｖ相およびＷ相のＰＷＭ信号パターンのデューティ比を最大相、最小相および中間相に分類したグラフである。6 is a graph in which the duty ratios of the U-phase, V-phase, and W-phase PWM signal patterns shown in FIG. 5 are classified into a maximum phase, a minimum phase, and an intermediate phase. 中間相のデューティ比が基準値０．５以上である場合の波形を示すグラフである。It is a graph which shows a waveform in case the duty ratio of an intermediate phase is the standard value 0.5 or more. 中間相のデューティ比が基準値０．５未満である場合の波形を示すグラフである。It is a graph which shows a waveform in case the duty ratio of an intermediate phase is less than the reference value 0.5. 中間相のデューティ比が基準値０．５以上の場合に第１キャリア波と比較される中間層の閾値を示すグラフである。It is a graph which shows the threshold value of the intermediate | middle layer compared with a 1st carrier wave when the duty ratio of an intermediate | middle phase is 0.5 or more of reference values. 中間相のデューティ比が基準値０．５未満の場合に第１キャリア波と比較される中間層の閾値を示すグラフである。It is a graph which shows the threshold value of the intermediate | middle layer compared with a 1st carrier wave when the duty ratio of an intermediate | middle phase is less than the reference value 0.5. 中間相のデューティ比および中間相の閾値の波形を示すグラフである。It is a graph which shows the waveform of the duty ratio of an intermediate phase, and the threshold value of an intermediate phase. 中間相のデューティ比が基準値０．５をまたぐ時刻Ｔ２前後のＰＷＭ信号パターンを示すグラフである。It is a graph which shows the PWM signal pattern before and behind time T2 when the duty ratio of an intermediate phase crosses the reference value 0.5. 最大相がＷ相からＵ相に入れ替わる時刻Ｔ１前後のＰＷＭ信号パターンを示すグラフである。It is a graph which shows the PWM signal pattern before and after time T1 when the maximum phase is switched from the W phase to the U phase. 実施の形態１に係る電力変換装置の制御方法を示すフローチャートである。3 is a flowchart illustrating a method for controlling the power conversion device according to the first embodiment. 従来の電力変換装置の電圧ベクトルを示す図である。It is a figure which shows the voltage vector of the conventional power converter device. この発明に係る電力変換装置の電圧ベクトルを示す図である。It is a figure which shows the voltage vector of the power converter device which concerns on this invention. 実施の形態１における最大相、中間相および最小相のＰＷＭ信号パターンの、中間相のデューティ比が０．５以上である場合の例を示すグラフである。5 is a graph showing an example in which the duty ratio of the intermediate phase of the maximum phase, intermediate phase, and minimum phase PWM signal patterns in the first embodiment is 0.5 or more. 実施の形態１における最大相、中間相および最小相のＰＷＭ信号パターンの、中間相のデューティ比が０．５未満である場合の例を示すグラフである。6 is a graph illustrating an example in which the duty ratio of the intermediate phase of the PWM signal pattern of the maximum phase, the intermediate phase, and the minimum phase in the first embodiment is less than 0.5. この発明の実施の形態２における最大相、中間相および最小相のＰＷＭ信号パターンの、中間相のデューティ比が１に近い場合の例を示すグラフである。It is a graph which shows the example in case the duty ratio of an intermediate phase is close to 1 of the PWM signal pattern of the maximum phase, intermediate phase, and minimum phase in Embodiment 2 of this invention. この発明の実施の形態４におけるＰＷＭ信号操作の規則の理解を助けるための参考例であり、ＰＷＭ信号パターンにおけるゼロ電圧ベクトルの時間を最大にした例を示すグラフである。It is a reference example for assisting the understanding of the rule of the PWM signal operation in Embodiment 4 of this invention, and is a graph which shows the example which maximized the time of the zero voltage vector in a PWM signal pattern. 実施の形態４のＰＷＭ信号生成部により生成された最大相、中間相および最小相のＰＷＭ信号パターンを示すグラフである。10 is a graph showing PWM signal patterns of maximum phase, intermediate phase, and minimum phase generated by the PWM signal generation unit of the fourth embodiment. この発明の実施の形態５に係る電力変換装置におけるＰＷＭ信号生成部により生成された最大相、中間相および最小相のＰＷＭ信号パターンを示すグラフである。It is a graph which shows the PWM signal pattern of the maximum phase, intermediate | middle phase, and minimum phase which were produced | generated by the PWM signal generation part in the power converter device which concerns on Embodiment 5 of this invention. この発明の実施の形態６に係る電力変換装置におけるＰＷＭ信号生成部により生成された最大相、中間相および最小相のＰＷＭ信号パターンを示すグラフである。It is a graph which shows the PWM signal pattern of the maximum phase, intermediate | middle phase, and minimum phase which were produced | generated by the PWM signal generation part in the power converter device which concerns on Embodiment 6 of this invention. 実施の形態６に係る電力変換装置におけるＰＷＭ信号生成部により生成された最大相、中間相および最小相のＰＷＭ信号パターンを示すグラフである。14 is a graph showing PWM signal patterns of maximum phase, intermediate phase, and minimum phase generated by a PWM signal generation unit in the power conversion device according to the sixth embodiment. 実施の形態６に係る電力変換装置におけるＰＷＭ信号生成部により生成された最大相、中間相および最小相のＰＷＭ信号パターンを示すグラフである。14 is a graph showing PWM signal patterns of maximum phase, intermediate phase, and minimum phase generated by a PWM signal generation unit in the power conversion device according to the sixth embodiment. 実施の形態６に係る電力変換装置におけるＰＷＭ信号生成部により生成された最大相、中間相および最小相のＰＷＭ信号パターンを示すグラフであり、三角波キャリアを用いた場合の例である。It is a graph which shows the PWM signal pattern of the maximum phase, intermediate | middle phase, and minimum phase which were produced | generated by the PWM signal generation part in the power converter device which concerns on Embodiment 6, and is an example at the time of using a triangular wave carrier. 実施の形態６に係る電力変換装置におけるＰＷＭ信号生成部により生成された最大相、中間相および最小相のＰＷＭ信号パターンを示すグラフであり、三角波キャリアを用いた場合の例である。It is a graph which shows the PWM signal pattern of the maximum phase, intermediate | middle phase, and minimum phase which were produced | generated by the PWM signal generation part in the power converter device which concerns on Embodiment 6, and is an example at the time of using a triangular wave carrier. 実施の形態６に係る電力変換装置におけるＰＷＭ信号生成部により生成された最大相、中間相および最小相のＰＷＭ信号パターンを示すグラフであり、三角波キャリアを用いた場合の例である。It is a graph which shows the PWM signal pattern of the maximum phase, intermediate | middle phase, and minimum phase which were produced | generated by the PWM signal generation part in the power converter device which concerns on Embodiment 6, and is an example at the time of using a triangular wave carrier. この発明の実施の形態７に係る電力変換装置におけるＰＷＭ信号生成部により生成された最大相、中間相および最小相のＰＷＭ信号パターンを示すグラフである。It is a graph which shows the PWM signal pattern of the maximum phase, intermediate | middle phase, and minimum phase which were produced | generated by the PWM signal generation part in the power converter device which concerns on Embodiment 7 of this invention. 実施の形態７に係る電力変換装置におけるＰＷＭ信号生成部により生成された最大相、中間相および最小相のＰＷＭ信号パターンを示すグラフである。18 is a graph showing PWM signal patterns of maximum phase, intermediate phase, and minimum phase generated by a PWM signal generation unit in the power conversion device according to the seventh embodiment. この発明の実施の形態８に係る電力変換装置におけるＰＷＭ信号生成部により生成された最大相、中間相および最小相のＰＷＭ信号パターンを示すグラフである。It is a graph which shows the PWM signal pattern of the maximum phase, intermediate | middle phase, and minimum phase which were produced | generated by the PWM signal generation part in the power converter device which concerns on Embodiment 8 of this invention. 実施の形態８に係る電力変換装置におけるＰＷＭ信号生成部により生成された最大相、中間相および最小相のＰＷＭ信号パターンを示すグラフである。10 is a graph showing PWM signal patterns of a maximum phase, an intermediate phase, and a minimum phase generated by a PWM signal generation unit in a power conversion device according to an eighth embodiment. この発明の実施の形態９に係る電力変換装置におけるＰＷＭ信号生成部により生成された最大相、中間相および最小相のＰＷＭ信号パターンを示すグラフである。It is a graph which shows the PWM signal pattern of the maximum phase, intermediate | middle phase, and minimum phase which were produced | generated by the PWM signal generation part in the power converter device which concerns on Embodiment 9 of this invention.
　以下、この発明をより詳細に説明するために、この発明を実施するための形態について、添付の図面に従って説明する。
実施の形態１．
　図１は、この発明の実施の形態１に係る電力変換装置１の構成例を示すブロック図である。電力変換装置１は、直流をＵ相、Ｖ相およびＷ相の３相交流に変換して電動機１０へ出力し、電動機１０を駆動するものである。電動機１０は、例えば永久磁石を用いた同期モータである。この電動機１０は、ロータの角度を検出するロータ角度センサ１１を備えている。ロータ角度センサ１１は、電動機１０のロータ角度を検出し、電力変換装置１へ出力する。 Hereinafter, in order to explain the present invention in more detail, modes for carrying out the present invention will be described with reference to the accompanying drawings.
Embodiment 1 FIG.
FIG. 1 is a block diagram showing a configuration example of a power conversion device 1 according to Embodiment 1 of the present invention. The power conversion device 1 converts a direct current into a three-phase alternating current of U phase, V phase, and W phase and outputs it to the electric motor 10 to drive the electric motor 10. The electric motor 10 is a synchronous motor using a permanent magnet, for example. The electric motor 10 includes a rotor angle sensor 11 that detects the angle of the rotor. The rotor angle sensor 11 detects the rotor angle of the electric motor 10 and outputs it to the power conversion device 1.
　図示された電力変換装置１は、複数のスイッチング素子がＵ相、Ｖ相およびＷ相の３相のＰＷＭ信号パターンに従いオンオフすることで直流を３相交流に変換するインバータ回路２と、インバータ回路２の直流側に接続されて電流に対応する信号を発生する電流検出素子３と、電流検出素子３に発生した信号と３相のＰＷＭ信号パターンとに基づいてインバータ回路２の相電流を再現する相電流再現部４と、相電流再現部４により再現された相電流に基づいて３相のＰＷＭ信号パターンのデューティ比を生成するデューティ生成部５と、デューティ生成部５により生成された３相のＰＷＭ信号パターンのデューティ比の大小関係を判定してデューティ比が最大となる最大相、最小となる最小相および中間となる中間相に分類する判定部６と、デューティ生成部５により生成されたデューティ比に基づいて３相のＰＷＭ信号パターンを生成する際に中間相のＰＷＭ信号パターンの周期を、最大相または最小相のＰＷＭ信号パターンの周期の２倍以上にするＰＷＭ信号生成部７とを備えている。 The illustrated power conversion apparatus 1 includes an inverter circuit 2 that converts a direct current into a three-phase alternating current by turning on and off a plurality of switching elements according to a three-phase PWM signal pattern of a U phase, a V phase, and a W phase, and an inverter circuit 2 Current detecting element 3 that is connected to the DC side of the signal generating a signal corresponding to the current, and a phase that reproduces the phase current of the inverter circuit 2 based on the signal generated in the current detecting element 3 and the three-phase PWM signal pattern. A current reproduction unit 4; a duty generation unit 5 that generates a duty ratio of a three-phase PWM signal pattern based on the phase current reproduced by the phase current reproduction unit 4; and a three-phase PWM generated by the duty generation unit 5 A determination unit 6 that determines the magnitude relationship of the duty ratios of the signal patterns and classifies the maximum phase, the minimum phase that is the minimum, and the intermediate phase that is the middle, with the maximum duty ratio; When generating a three-phase PWM signal pattern based on the duty ratio generated by the duty generation unit 5, the period of the intermediate phase PWM signal pattern is set to be twice or more the period of the maximum phase or minimum phase PWM signal pattern. And a PWM signal generation unit 7 for performing the above operation.
　図２は、実施の形態１に係る電力変換装置１のインバータ回路２の構成例を示す回路図である。インバータ回路２は、Ｕ相、Ｖ相およびＷ相の３相からなる。各相には、上アーム側のスイッチング素子ＵＨ，ＶＨ，ＷＨと、下アーム側のスイッチング素子ＵＬ，ＶＬ，ＷＬが設置されている。スイッチング素子ＵＨ，ＵＬ，ＶＨ，ＶＬ，ＷＨ，ＷＬは、ＰＷＭ信号生成部７からのＰＷＭ信号パターンに従ってオンオフし、電動機１０を駆動するための３相交流電流を生成する。 FIG. 2 is a circuit diagram illustrating a configuration example of the inverter circuit 2 of the power conversion device 1 according to the first embodiment. The inverter circuit 2 includes three phases, a U phase, a V phase, and a W phase. In each phase, switching elements UH, VH, WH on the upper arm side and switching elements UL, VL, WL on the lower arm side are installed. The switching elements UH, UL, VH, VL, WH, WL are turned on / off according to the PWM signal pattern from the PWM signal generation unit 7 to generate a three-phase alternating current for driving the electric motor 10.
　インバータ回路２の直流側には、母線電流に対応した信号を発生する電流検出素子３が接続されている。電流検出素子３は、例えばシャント抵抗または直流変換器である。 A current detection element 3 that generates a signal corresponding to the bus current is connected to the DC side of the inverter circuit 2. The current detection element 3 is, for example, a shunt resistor or a DC converter.
　電力変換装置１における相電流再現部４、デューティ生成部５、判定部６およびＰＷＭ信号生成部７は、図３Ａに示すように専用のハードウェアである処理回路１００であってもよいし、図３Ｂに示すようにメモリ１０２に格納されているプログラムを実行するプロセッサ１０１であってもよい。 The phase current reproduction unit 4, the duty generation unit 5, the determination unit 6, and the PWM signal generation unit 7 in the power conversion device 1 may be a processing circuit 100 that is dedicated hardware as illustrated in FIG. The processor 101 may execute a program stored in the memory 102 as illustrated in 3B.
　図３Ａに示すように、相電流再現部４、デューティ生成部５、判定部６およびＰＷＭ信号生成部７が専用のハードウェアである場合、処理回路１００は、例えば単一回路、複合回路、プログラム化したプロセッサ、並列プログラム化したプロセッサ、ＡＳＩＣ（Ａｐｐｌｉｃａｔｉｏｎ－Ｓｐｅｃｉｆｉｃ　Ｉｎｔｅｇｒａｔｅｄ　Ｃｉｒｃｕｉｔ）、ＦＰＧＡ（Ｆｉｅｌｄ－Ｐｒｏｇｒａｍｍａｂｌｅ　Ｇａｔｅ　Ａｒｒａｙ）、またはこれらを組み合わせたものが該当する。相電流再現部４、デューティ生成部５、判定部６およびＰＷＭ信号生成部７の機能を複数の処理回路１１で実現してもよいし、各部の機能をまとめて１つの処理回路１００で実現してもよい。 As illustrated in FIG. 3A, when the phase current reproduction unit 4, the duty generation unit 5, the determination unit 6, and the PWM signal generation unit 7 are dedicated hardware, the processing circuit 100 is, for example, a single circuit, a composite circuit, a program An integrated processor, a parallel-programmed processor, an ASIC (Application-Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array), or a combination of these. The functions of the phase current reproduction unit 4, the duty generation unit 5, the determination unit 6, and the PWM signal generation unit 7 may be realized by a plurality of processing circuits 11, or the functions of the respective units are realized by a single processing circuit 100. May be.
　図３Ｂに示すように、相電流再現部４、デューティ生成部５、判定部６およびＰＷＭ信号生成部７がプロセッサ１０１である場合、各部の機能は、ソフトウェア、ファームウェア、またはソフトウェアとファームウェアとの組み合わせにより実現される。ソフトウェアまたはファームウェアはプログラムとして記述され、メモリ１０２に格納される。プロセッサ１０１は、メモリ１０２に格納されているプログラムを読み出して実行することにより、各部の機能を実現する。即ち、電力変換装置１は、プロセッサ１０１により実行されるときに、電流検出素子３に発生した信号と３相のＰＷＭ信号パターンとに基づいてインバータ回路２の相電流を再現するステップと、再現された相電流に基づいて３相のＰＷＭ信号パターンのデューティ比を生成するステップと、生成された３相のＰＷＭ信号パターンのデューティ比の大小関係を判定してデューティ比が最大となる最大相、最小となる最小相および中間となる中間相に分類するステップと、生成されたデューティ比に基づいて３相のＰＷＭ信号パターンを生成する際に中間相のＰＷＭ信号パターンの周期を最大相または最小相のＰＷＭ信号パターンの周期の２倍以上にするステップが結果的に実行されることになるプログラムを格納するためのメモリ１０２を備える。また、このプログラムは、相電流再現部４、デューティ生成部５、判定部６およびＰＷＭ信号生成部７の手順または方法をコンピュータに実行させるものであるともいえる。 As shown in FIG. 3B, when the phase current reproduction unit 4, the duty generation unit 5, the determination unit 6, and the PWM signal generation unit 7 are the processor 101, the function of each unit is software, firmware, or a combination of software and firmware. It is realized by. Software or firmware is described as a program and stored in the memory 102. The processor 101 reads out and executes a program stored in the memory 102, thereby realizing the function of each unit. That is, the power conversion device 1 is reproduced with the step of reproducing the phase current of the inverter circuit 2 based on the signal generated in the current detection element 3 and the three-phase PWM signal pattern when executed by the processor 101. The step of generating the duty ratio of the three-phase PWM signal pattern based on the phase current and the maximum phase and the minimum of which the duty ratio is maximized by determining the magnitude relationship between the duty ratio of the generated three-phase PWM signal pattern And when generating a three-phase PWM signal pattern based on the generated duty ratio, the period of the intermediate phase PWM signal pattern is set to the maximum phase or the minimum phase. A memory 102 is provided for storing a program that results in the step of making the period of the PWM signal pattern more than twice as long. That. It can also be said that this program causes the computer to execute the procedures or methods of the phase current reproduction unit 4, the duty generation unit 5, the determination unit 6, and the PWM signal generation unit 7.
　ここで、プロセッサ１０１とは、例えば、ＣＰＵ（Ｃｅｎｔｒａｌ　Ｐｒｏｃｅｓｓｉｎｇ　Ｕｎｉｔ）、処理装置、演算装置、マイクロプロセッサ、マイクロコンピュータ（以下、マイコンと称す）、またはＤＳＰ（Ｄｉｇｉｔａｌ　Ｓｉｇｎａｌ　Ｐｒｏｃｅｓｓｏｒ）などのことである。
　メモリ１０２は、例えば、ＲＡＭ（Ｒａｎｄｏｍ　Ａｃｃｅｓｓ　Ｍｅｍｏｒｙ）、ＲＯＭ（Ｒｅａｄ　Ｏｎｌｙ　Ｍｅｍｏｒｙ）、ＥＰＲＯＭ（Ｅｒａｓａｂｌｅ　Ｐｒｏｇｒａｍｍａｂｌｅ　ＲＯＭ）、ＥＥＰＲＯＭ（Ｅｌｅｃｔｒｉｃａｌｌｙ　ＥＰＲＯＭ）、フラッシュメモリ、ＳＳＤ（Ｓｏｌｉｄ　Ｓｔａｔｅ　Ｄｒｉｖｅ）等の不揮発性または揮発性の半導体メモリであってもよいし、ハードディスク、フレキシブルディスク等の磁気ディスクであってもよいし、ＣＤ（Ｃｏｍｐａｃｔ　Ｄｉｓｃ）、ＤＶＤ（Ｄｉｇｉｔａｌ　Ｖｅｒｓａｔｉｌｅ　Ｄｉｓｃ）等の光ディスクであってもよい。 Here, the processor 101 is, for example, a CPU (Central Processing Unit), a processing device, an arithmetic device, a microprocessor, a microcomputer (hereinafter referred to as a microcomputer), or a DSP (Digital Signal Processor).
The memory 102 is, for example, a RAM (Random Access Memory), a ROM (Read Only Memory), an EPROM (Erasable Programmable ROM), an EEPROM (Electrically EPROM), a flash memory, an SSD (Solid State Nonvolatile) or the like. It may be a semiconductor memory, a magnetic disk such as a hard disk or a flexible disk, or an optical disk such as a CD (Compact Disc) or a DVD (Digital Versatile Disc).
　なお、相電流再現部４、デューティ生成部５、判定部６およびＰＷＭ信号生成部７の各機能について、一部を専用のハードウェアで実現し、一部をソフトウェアまたはファームウェアで実現するようにしてもよい。このように、電力変換装置１における処理回路１００は、ハードウェア、ソフトウェア、ファームウェア、またはこれらの組み合わせによって、上述の各機能を実現することができる。 In addition, about each function of the phase current reproduction part 4, the duty generation part 5, the determination part 6, and the PWM signal generation part 7, a part is implement | achieved by exclusive hardware and a part is implement | achieved by software or firmware. Also good. As described above, the processing circuit 100 in the power conversion device 1 can realize the above-described functions by hardware, software, firmware, or a combination thereof.
　相電流再現部４は、電流検出素子３であるシャント抵抗の両端の電圧を検出し、検出した電圧を母線電流値に変換する。そして、相電流再現部４は、電流検出素子３を用いて検出した母線電流値と、ＰＷＭ信号生成部７により生成された３相のＰＷＭ信号パターンとに基づいて、後述する方法により３相の相電流を再現し、デューティ生成部５へ出力する。 The phase current reproduction unit 4 detects the voltage across the shunt resistor, which is the current detection element 3, and converts the detected voltage into a bus current value. Then, the phase current reproduction unit 4 uses a method described later on the basis of the bus current value detected using the current detection element 3 and the three-phase PWM signal pattern generated by the PWM signal generation unit 7. The phase current is reproduced and output to the duty generation unit 5.
　デューティ生成部５は、相電流再現部４により再現された３相の相電流と、ロータ角度センサ１１により検出された電動機１０のロータ角度とを用いたベクトル制御を行い、３相のＰＷＭ信号パターンのデューティ比を生成する。デューティ生成部５によるデューティ比の生成方法としては、例えば特許第５３００９４４号公報に記載された方法など、周知の技術を用いることが可能である。デューティ生成部５は、生成した３相のＰＷＭ信号パターンのデューティ比を、判定部６へ出力する。 The duty generation unit 5 performs vector control using the three-phase phase current reproduced by the phase current reproduction unit 4 and the rotor angle of the electric motor 10 detected by the rotor angle sensor 11, and a three-phase PWM signal pattern The duty ratio is generated. As a method for generating a duty ratio by the duty generation unit 5, a known technique such as a method described in Japanese Patent No. 5300944 can be used. The duty generation unit 5 outputs the duty ratio of the generated three-phase PWM signal pattern to the determination unit 6.
　図４は、デューティ生成部５により生成されたＵ相、Ｖ相およびＷ相のＰＷＭ信号パターンのデューティ比を示すグラフである。ここでは、デューティ生成部５は、Ｕ相の上アーム側のスイッチング素子ＵＨ、Ｖ相の上アーム側のスイッチング素子ＶＨ、およびＷ相の上アーム側のスイッチング素子ＷＨを駆動するために、１２０度ずつ位相がずれた正弦波状のデューティ比を生成する。なお、図４において破線で囲んだ部分で波形が不連続になっているのは、デューティ生成部５のベクトル制御においてｄｑ軸電流を４ｍｓごとにフィードバック制御しているためである。 FIG. 4 is a graph showing the duty ratio of the U-phase, V-phase, and W-phase PWM signal patterns generated by the duty generator 5. Here, the duty generation unit 5 drives the switching element UH on the U-phase upper arm side, the switching element VH on the V-phase upper arm side, and the switching element WH on the W-phase upper arm side, A sinusoidal duty ratio with a phase shift is generated. The reason why the waveform is discontinuous in the portion surrounded by the broken line in FIG. 4 is that the dq axis current is feedback-controlled every 4 ms in the vector control of the duty generator 5.
　また、デューティ生成部５は、Ｕ相、Ｖ相およびＷ相のＰＷＭ信号のデューティ比の振幅の中心が０．５になるように、各相のデューティ比をオフセット補正してもよい。デューティ生成部５は、各相のデューティ比を、振幅の中心が０．５になるようオフセット補正した後、判定部６へ出力する。 Further, the duty generation unit 5 may perform offset correction on the duty ratio of each phase so that the center of the amplitude of the duty ratio of the U-phase, V-phase, and W-phase PWM signals is 0.5. The duty generation unit 5 offsets the duty ratio of each phase so that the center of the amplitude becomes 0.5, and then outputs the duty ratio to the determination unit 6.
　図５は、図４に示したデューティ比の振幅の中心を０．５に補正したグラフである。デューティ比の振幅の中心が０．５になるよう補正することで、電圧の利用率が改善する。 FIG. 5 is a graph in which the center of the amplitude of the duty ratio shown in FIG. 4 is corrected to 0.5. By correcting so that the center of the amplitude of the duty ratio becomes 0.5, the voltage utilization rate is improved.
　判定部６は、デューティ生成部５により生成されたＵ相、Ｖ相およびＷ相のＰＷＭ信号パターンのデューティ比の大小関係を判定し、デューティ比が最大となる最大相、最小となる最小相、および中間となる中間相に分類する。判定部６は、３相のＰＷＭ信号パターンのデューティ比と大小関係の判定結果とを、ＰＷＭ信号生成部７へ出力する。 The determination unit 6 determines the magnitude relationship between the duty ratios of the U-phase, V-phase, and W-phase PWM signal patterns generated by the duty generation unit 5, and the maximum phase with the maximum duty ratio, the minimum phase with the minimum, And the intermediate phase which is intermediate. The determination unit 6 outputs the duty ratio of the three-phase PWM signal pattern and the determination result of the magnitude relationship to the PWM signal generation unit 7.
　図６は、図５に示したＵ相、Ｖ相およびＷ相のＰＷＭ信号パターンのデューティ比を最大相、最小相および中間相に分類したグラフである。判定部６は、デューティ生成部５により生成されたＵ相、Ｖ相およびＷ相のＰＷＭ信号パターンのデューティ比を、キャリア周期にあわせてサンプリングする。そして、判定部６は、あるタイミングでサンプリングした３相分のデューティ比のうちの最も値が大きいデューティ比をもつ相を最大相に分類し、最も値が小さいデューティ比をもつ相を最小相に分類し、その中間の値となるデューティ比をもつ相を中間相に分類する。図６において、時刻Ｔ１では、最大相がＷ相からＵ相に入れ替わる。時刻Ｔ２では、中間相であるＷ相のデューティ比が０．５を下回る。時刻Ｔ３では、最小相がＶ相からＷ相に入れ替わる。時刻Ｔ４では、中間相であるＶ相のデューティ比が０．５を上回る。図６の時刻Ｔ１～Ｔ５は、図５の時刻Ｔ１～Ｔ５と同じ時刻である。
　このように、図５に示したＵ相、Ｖ相およびＷ相のデューティ比を、図６のように最大相、最小相および中間相のデューティ比に分類すると、最大相と最小相の波形はデューティ比０．５の直線を対象軸とした線対称になる。これは、図５においてデューティ生成部５が、Ｕ相、Ｖ相およびＷ相のデューティ比を、振幅の中心が０．５になるよう補正したためである。 FIG. 6 is a graph in which the duty ratios of the U-phase, V-phase, and W-phase PWM signal patterns shown in FIG. 5 are classified into a maximum phase, a minimum phase, and an intermediate phase. The determination unit 6 samples the duty ratio of the U-phase, V-phase, and W-phase PWM signal patterns generated by the duty generation unit 5 in accordance with the carrier period. Then, the determination unit 6 classifies the phase having the largest duty ratio among the duty ratios of the three phases sampled at a certain timing as the maximum phase, and sets the phase having the smallest duty ratio as the minimum phase. Classify and classify a phase having a duty ratio that is an intermediate value as an intermediate phase. In FIG. 6, at time T1, the maximum phase is switched from the W phase to the U phase. At time T2, the duty ratio of the W phase, which is an intermediate phase, falls below 0.5. At time T3, the minimum phase is switched from the V phase to the W phase. At time T4, the duty ratio of the V phase that is the intermediate phase exceeds 0.5. Times T1 to T5 in FIG. 6 are the same as the times T1 to T5 in FIG.
Thus, when the duty ratios of the U phase, V phase and W phase shown in FIG. 5 are classified into the duty ratios of the maximum phase, the minimum phase and the intermediate phase as shown in FIG. 6, the waveforms of the maximum phase and the minimum phase are as follows. The line is symmetrical with respect to a straight line having a duty ratio of 0.5. This is because the duty generation unit 5 in FIG. 5 corrects the duty ratios of the U phase, the V phase, and the W phase so that the center of the amplitude becomes 0.5.
　ＰＷＭ信号生成部７は、予め定められた周期をもつキャリア波と判定部６から受け取った最大相、最小相および中間相のデューティ比とに基づいて、最大相、最小相および中間相のＰＷＭ信号パターンを生成する。その際、ＰＷＭ信号生成部７は、母線電流検出時間を確保できるように最大相、最小相および中間相のＰＷＭ信号パターンを操作した後、Ｕ相、Ｖ相およびＷ相のＰＷＭ信号パターンに変換し、インバータ回路２および相電流再現部４へ出力する。 The PWM signal generation unit 7 generates a PWM signal of the maximum phase, the minimum phase, and the intermediate phase based on the carrier wave having a predetermined period and the duty ratios of the maximum phase, the minimum phase, and the intermediate phase received from the determination unit 6. Generate a pattern. At that time, the PWM signal generation unit 7 operates the PWM signal pattern of the maximum phase, the minimum phase, and the intermediate phase so as to ensure the bus current detection time, and then converts the PWM signal pattern of the U phase, the V phase, and the W phase. And output to the inverter circuit 2 and the phase current reproduction unit 4.
　次に、相電流再現部４による相電流再現方法と、ＰＷＭ信号生成部７によるＰＷＭ信号操作方法を説明する。
　電動機１０の運転時には、インバータ回路２において対をなすスイッチング素子ＵＨとＵＬのいずれか一方のみオン、ＶＨとＶＬのいずれか一方のみオン、ＷＨとＷＬのいずれか一方のみオンになる。相電流を再現するために母線電流を検出する場合、通電の組み合わせとして２組の状態が考えられる。
　１組目の状態は「３相のうちのある１相の上アーム側のスイッチング素子がオンで、残りの２相の下アーム側のスイッチング素子がオン」である。このとき、上記ある１相の下アーム側のスイッチング素子はオフになり、上記残りの２相の上アーム側のスイッチング素子はオフになる。
　２組目の状態は「３相のうちのある１相の下アーム側のスイッチング素子がオンで、残りの２相の上アーム側のスイッチング素子がオン」である。このとき、上記ある１相の上アーム側のスイッチング素子はオフになり、上記残りの２相の下アーム側のスイッチング素子はオフになる。 Next, a phase current reproduction method by the phase current reproduction unit 4 and a PWM signal operation method by the PWM signal generation unit 7 will be described.
During operation of the electric motor 10, only one of the switching elements UH and UL paired in the inverter circuit 2 is turned on, only one of VH and VL is turned on, and only one of WH and WL is turned on. When the bus current is detected in order to reproduce the phase current, two states are conceivable as energization combinations.
The state of the first set is “the switching element on the upper arm side of one phase of the three phases is on, and the switching elements on the lower arm side of the remaining two phases are on”. At this time, the switching element on the lower arm side of a certain one phase is turned off, and the switching elements on the upper arm side of the remaining two phases are turned off.
The state of the second set is “the switching element on the lower arm side of one phase out of the three phases is on, and the switching element on the upper arm side of the remaining two phases is on”. At this time, the switching element on the upper arm side of a certain one phase is turned off, and the switching elements on the lower arm side of the remaining two phases are turned off.
　例えば、スイッチング素子ＵＨ，ＶＬ，ＷＬがオンした１組目の状態では、唯一上アーム側がオンになっているＵ相電流が母線電流に一致する。他方、スイッチング素子ＵＨ，ＶＨ，ＷＬがオンした２組目の状態では、唯一下アーム側がオンになっているＷ相電流が母線電流の逆方向電流になる。これにより、Ｕ相電流とＷ相電流が分かる。残りの１相の相電流は、（得られた２相の相電流の合計値）×（－１）として計算される。 For example, in the first set state in which the switching elements UH, VL, WL are turned on, the U-phase current with the upper arm side only turned on matches the bus current. On the other hand, in the second set state in which switching elements UH, VH, WL are turned on, only the W-phase current with the lower arm side turned on becomes the reverse current of the bus current. Thereby, the U-phase current and the W-phase current are known. The remaining one-phase phase current is calculated as (the total value of the obtained two-phase phase currents) × (−1).
　相電流再現部４は、以上の方法により、母線電流値から３相の相電流を再現することができる。しかし、３相のＰＷＭ信号パターンのデューティ比が近接すると、上記２組の状態が維持される時間、つまり母線電流検出時間が短くなってしまう。母線電流検出時間が短くなると、正確な値を検出できない。また、母線電流検出のタイミングを、スイッチング素子をオンオフするタイミングに合わせて変化させる必要がある。そうすると処理が複雑になる。 The phase current reproduction unit 4 can reproduce the three-phase phase current from the bus current value by the above method. However, when the duty ratios of the three-phase PWM signal patterns are close to each other, the time during which the two sets of states are maintained, that is, the bus current detection time is shortened. If the bus current detection time is shortened, an accurate value cannot be detected. In addition, it is necessary to change the bus current detection timing in accordance with the timing at which the switching element is turned on / off. This complicates the process.
　そこで、本実施の形態１では、以下の方法により、母線電流検出時間を容易に確保する。
　図７は、中間相のデューティ比が基準値０．５以上である場合の波形を示すグラフである。図８は、中間相のデューティ比が基準値０．５未満である場合の波形を示すグラフである。基準値の説明は後述する。図７と図８において、１番上の波形は上アーム側のスイッチング素子を駆動するための、最大相のＰＷＭ信号パターンである。ＰＷＭ信号が高電圧区間であるとき、このＰＷＭ信号を受け付けたスイッチング素子がオンになる。ＰＷＭ信号が低電圧区間であるとき、このＰＷＭ信号を受け付けたスイッチング素子がオフになる。上から２番目の波形は上アーム側のスイッチング素子を駆動するための、中間相のＰＷＭ信号パターンである。上から３番目の波形は上アーム側のスイッチング素子を駆動するための、最小相のＰＷＭ信号パターンである。上から４番目の波形は第１キャリア波、最大相の閾値、および最小相の閾値である。上から５番目の波形は第２キャリア波および中間相の閾値である。上から６番目の波形は実際の母線電流と電流検出素子３が検出する母線電流値、および母線電流検出のタイミングを示す。 Therefore, in the first embodiment, the bus current detection time is easily secured by the following method.
FIG. 7 is a graph showing a waveform when the duty ratio of the intermediate phase is a reference value of 0.5 or more. FIG. 8 is a graph showing a waveform when the duty ratio of the intermediate phase is less than the reference value 0.5. The reference value will be described later. 7 and 8, the top waveform is the maximum phase PWM signal pattern for driving the switching element on the upper arm side. When the PWM signal is in the high voltage section, the switching element that has received the PWM signal is turned on. When the PWM signal is in the low voltage section, the switching element that has received the PWM signal is turned off. The second waveform from the top is an intermediate phase PWM signal pattern for driving the switching element on the upper arm side. The third waveform from the top is a minimum phase PWM signal pattern for driving the switching element on the upper arm side. The fourth waveform from the top is the first carrier wave, the maximum phase threshold, and the minimum phase threshold. The fifth waveform from the top is the second carrier wave and the intermediate phase threshold. The sixth waveform from the top shows the actual bus current, the bus current value detected by the current detection element 3, and the bus current detection timing.
　ＰＷＭ信号生成部７は、予め定められた周期ののこぎり波状のキャリア波または三角波状のキャリア波を生成し、これを第１キャリア波とする。図７および図８において、第１キャリア波はのこぎり波状であり、キャリア周期は０．１ｍｓ、キャリア周波数は１０ｋＨｚである。そして、ＰＷＭ信号生成部７は、判定部６から受け取った最大相のデューティ比から最大相の閾値（１－デューティ比）を算出し、第１キャリア波と比較する。ＰＷＭ信号生成部７は、（１－デューティ比）＜（第１キャリア波）のときは最大相のＰＷＭ信号パターンを高電圧区間とし、それ以外のときは最大相のＰＷＭ信号パターンを低電圧区間とする。 The PWM signal generation unit 7 generates a sawtooth wave carrier wave or a triangular wave carrier wave having a predetermined period, and uses this as a first carrier wave. 7 and 8, the first carrier wave is a sawtooth wave, the carrier period is 0.1 ms, and the carrier frequency is 10 kHz. Then, the PWM signal generation unit 7 calculates the maximum phase threshold (1-duty ratio) from the maximum phase duty ratio received from the determination unit 6 and compares it with the first carrier wave. The PWM signal generation unit 7 sets the maximum phase PWM signal pattern as a high voltage interval when (1-duty ratio) <(first carrier wave), and sets the maximum phase PWM signal pattern as a low voltage interval otherwise. And
　また、ＰＷＭ信号生成部７は、判定部６から受け取った最小相のデューティ比を最小相の閾値とし、第１キャリア波と比較する。ＰＷＭ信号生成部７は、（デューティ比）＞（第１キャリア波）のときは最小相のＰＷＭ信号パターンを高電圧区間とし、それ以外のときは最小相のＰＷＭ信号パターンを低電圧区間とする。 Also, the PWM signal generation unit 7 uses the minimum phase duty ratio received from the determination unit 6 as the minimum phase threshold and compares it with the first carrier wave. The PWM signal generation unit 7 sets the minimum phase PWM signal pattern as a high voltage interval when (duty ratio)> (first carrier wave), and sets the minimum phase PWM signal pattern as a low voltage interval otherwise. .
　さらに、ＰＷＭ信号生成部７は、第１キャリア波を２倍の周期にした第２キャリア波を生成する。図７および図８の例では、第２キャリア波は、第１キャリア波に対し２周期ごとに１周期分間引いた波形になっている。ＰＷＭ信号生成部７は、判定部６から受け取った中間相のデューティ比から中間相の閾値を算出し、第２キャリア波と比較する。比較の際、ＰＷＭ信号生成部７は、最大相のデューティ比と最小相のデューティ比の合計値の半分の値である基準値０．５を境にして、中間相の閾値を変更する。 Furthermore, the PWM signal generation unit 7 generates a second carrier wave that is a double cycle of the first carrier wave. In the example of FIGS. 7 and 8, the second carrier wave has a waveform that is drawn for one period every two periods with respect to the first carrier wave. The PWM signal generation unit 7 calculates the threshold value of the intermediate phase from the duty ratio of the intermediate phase received from the determination unit 6 and compares it with the second carrier wave. At the time of comparison, the PWM signal generator 7 changes the threshold value of the intermediate phase with a reference value 0.5 as a boundary, which is a half value of the total value of the duty ratio of the maximum phase and the duty ratio of the minimum phase.
　中間相のデューティ比が０．５以上の場合、ＰＷＭ信号生成部７は、中間相の閾値｛２×（デューティ比）－１｝を算出し、｛２×（デューティ比）－１｝＞（第２キャリア波）のときは中間相のＰＷＭ信号パターンを高電圧区間とし、それ以外のときは中間相のＰＷＭ信号パターンを低電圧区間とする。
　一方、中間相のデューティ比が０．５未満の場合、ＰＷＭ信号生成部７は、中間相の閾値｛１－２×（デューティ比）｝を算出し、｛１－２×（デューティ比）｝＜（第２キャリア波）のときは中間相のＰＷＭ信号パターンを高電圧区間とし、それ以外のときは中間相のＰＷＭ信号パターンを低電圧区間とする。 When the duty ratio of the intermediate phase is 0.5 or more, the PWM signal generation unit 7 calculates the threshold value {2 × (duty ratio) −1} of the intermediate phase and {2 × (duty ratio) −1}> ( In the case of the second carrier wave), the intermediate phase PWM signal pattern is set as the high voltage section, and in other cases, the intermediate phase PWM signal pattern is set as the low voltage section.
On the other hand, when the duty ratio of the intermediate phase is less than 0.5, the PWM signal generation unit 7 calculates the threshold value of the intermediate phase {1-2 × (duty ratio)} and {1-2 × (duty ratio)} When (<second carrier wave), the intermediate phase PWM signal pattern is set as a high voltage interval, and otherwise, the intermediate phase PWM signal pattern is set as a low voltage interval.
　このようにすれば、図７および図８のように最大相と最小相のＰＷＭ信号パターンの周期の２倍の周期をもつ中間相のＰＷＭ信号パターンが生成される。また、最大相のＰＷＭ信号パターンのうちの継続期間が短い低電圧区間が先に出力され、継続時間が長い高電圧区間が後に出力される。最小相のＰＷＭ信号パターンのうちの継続期間が短い高電圧区間が先に出力され、継続時間が長い低電圧区間が後に出力される。中間相のデューティ比が０．５以上の場合、中間相のＰＷＭ信号パターンのうちの継続時間が長い高電圧区間が先に出力され、継続時間が短い低電圧区間が後に出力される。一方、中間相のデューティ比が０．５未満の場合、中間相のＰＷＭ信号パターンのうちの継続時間が長い低電圧区間が先に出力され、継続時間が短い高電圧区間が後に出力される。 In this way, an intermediate-phase PWM signal pattern having a period twice as long as the maximum-phase and minimum-phase PWM signal patterns is generated as shown in FIGS. In addition, a low voltage section having a short duration in the maximum phase PWM signal pattern is output first, and a high voltage section having a long duration is output later. Of the minimum phase PWM signal pattern, a high voltage interval with a short duration is output first, and a low voltage interval with a long duration is output later. When the duty ratio of the intermediate phase is 0.5 or more, a high voltage section having a long duration among the PWM signal patterns of the intermediate phase is output first, and a low voltage section having a short duration is output later. On the other hand, when the duty ratio of the intermediate phase is less than 0.5, the low voltage section having a long duration among the PWM signal patterns of the intermediate phase is output first, and the high voltage section having a short duration is output later.
　相電流再現部４は、第１キャリア波が０に戻る直前、つまり第１キャリア周期の終了直前で母線電流を検出すれば、最大相の相電流と最小相の相電流とを交互に検出できる。そして、相電流再現部４は、中間相の相電流＝｛－（最大相の相電流）－（最小相の相電流）｝を算出する。これにより、１つの電流検出素子３を用いて最大相、最小相および中間相の相電流を再現することができる。最後に相電流再現部４は、判定部６の判定結果に基づいて、最大相、最小相および中間相の相電流を、Ｕ相、Ｖ相およびＷ相の相電流に置き換える。 If the phase current reproducing unit 4 detects the bus current immediately before the first carrier wave returns to 0, that is, immediately before the end of the first carrier period, the phase current reproducing unit 4 can alternately detect the phase current of the maximum phase and the phase current of the minimum phase. . Then, the phase current reproduction unit 4 calculates the phase current of the intermediate phase = {− (maximum phase current) − (minimum phase current)}. Thereby, the phase current of the maximum phase, the minimum phase, and the intermediate phase can be reproduced using one current detection element 3. Finally, the phase current reproduction unit 4 replaces the phase currents of the maximum phase, the minimum phase, and the intermediate phase with the phase currents of the U phase, the V phase, and the W phase based on the determination result of the determination unit 6.
　上述の通り、相電流再現部４は、１回目の第１キャリア周期の終了直前で１組目の通電状態における母線電流を検出したのち、２回目の第１キャリア周期の終了直前で２組目の通電状態における母線電流を検出する必要がある。
　１回目の第１キャリア周期では、中間相のＰＷＭ信号パターンの高電圧区間と低電圧区間のうちの継続時間が長い方の区間が配置されている。そのため、最大相、最小相および中間相のうちのいずれか１相のＰＷＭ信号パターンが高電圧区間、かつ残り２相のＰＷＭ信号パターンが低電圧区間になる期間が、１回目の第１キャリア周期の０．５以上の期間維持される。よって、第１キャリア波が０に戻る直前の母線電流検出タイミングまでに、電流検出素子３の検出値が安定する。
　２回目の第１キャリア周期では、中間相のＰＷＭ信号パターンの高電圧区間と低電圧区間のうちの継続時間が短い方の区間が配置されている。しかしながら、中間相のＰＷＭ信号パターンの周期は、最大相および最小相のＰＷＭ信号パターンの周期の２倍になっているため、２組目の通電状態においても長い母線電流検出時間を確保できる。 As described above, the phase current reproducing unit 4 detects the bus current in the energized state of the first set immediately before the end of the first first carrier cycle, and then the second set immediately before the end of the second first carrier cycle. It is necessary to detect the bus current in the energized state.
In the first carrier cycle of the first time, a section having a longer duration between the high voltage section and the low voltage section of the intermediate phase PWM signal pattern is arranged. Therefore, the period when the PWM signal pattern of any one of the maximum phase, the minimum phase and the intermediate phase is in the high voltage section and the remaining two phase PWM signal patterns are in the low voltage section is the first first carrier cycle. Of 0.5 or more. Therefore, the detection value of the current detection element 3 is stabilized by the bus current detection timing immediately before the first carrier wave returns to zero.
In the second first carrier cycle, a section having a shorter duration between the high voltage section and the low voltage section of the intermediate phase PWM signal pattern is arranged. However, since the cycle of the intermediate phase PWM signal pattern is twice the cycle of the maximum phase and minimum phase PWM signal patterns, a long bus current detection time can be secured even in the second set of energized states.
　母線電流検出時間を十分に確保できることにより、相電流再現部４は、応答性が遅い電流検出回路でも使用可能となる。よって、電力変換装置１に使用するマイコンまたは回路部品の選択範囲が広がり、コストアップを抑えられる。さらに、母線電流検出タイミングは第１キャリア波が０に戻る直前のタイミングに固定されているため、処理が簡素であり、安価な低機能マイコンを用いて電力変換装置１を構成することが可能である。 By ensuring a sufficient bus current detection time, the phase current reproduction unit 4 can be used even in a current detection circuit with a slow response. Therefore, the selection range of the microcomputer or circuit component used for the power converter 1 is expanded, and the cost increase can be suppressed. Furthermore, since the bus current detection timing is fixed to the timing immediately before the first carrier wave returns to 0, the processing is simple and the power conversion device 1 can be configured using an inexpensive low-function microcomputer. is there.
　なお、図６に示したように、最大相と最小相はデューティ比０．５の直線を対象軸とした線対称になっている。そこで、ＰＷＭ信号生成部７は、最大相のＰＷＭ信号パターンを反転して最小相のＰＷＭ信号パターンとしてもよい。反対に、ＰＷＭ信号生成部７は、最小相のＰＷＭ信号パターンを反転して、最大相のＰＷＭ信号パターンとしてもよい。 Note that, as shown in FIG. 6, the maximum phase and the minimum phase are symmetrical with respect to a straight line having a duty ratio of 0.5. Therefore, the PWM signal generation unit 7 may reverse the maximum phase PWM signal pattern to obtain the minimum phase PWM signal pattern. Conversely, the PWM signal generation unit 7 may invert the minimum phase PWM signal pattern to obtain the maximum phase PWM signal pattern.
　また、図７および図８では、中間相のＰＷＭ信号パターンを生成するために第２キャリア波を使用したが、第２キャリア波を使用する代わりに、図９および図１０のように中間相の閾値を第１キャリア波の周期ごとに変更するようにしてもよい。図９は、中間相のデューティ比が０．５以上の場合に第１キャリア波と比較される中間層の閾値を示すグラフであり、比較の結果、図７に示す中間相のＰＷＭ信号パターンが生成される。図１０は、中間相のデューティ比が０．５未満の場合に第１キャリア波と比較される中間層の閾値を示すグラフであり、比較の結果、図８に示す中間相のＰＷＭ信号パターンが生成される。中間層の閾値をキャリア周期ごとに変更することにより、キャリア波は１つでよい。 7 and 8, the second carrier wave is used to generate the intermediate phase PWM signal pattern. Instead of using the second carrier wave, the intermediate phase of the intermediate phase as shown in FIGS. 9 and 10 is used. You may make it change a threshold value for every period of a 1st carrier wave. FIG. 9 is a graph showing the threshold value of the intermediate layer compared with the first carrier wave when the duty ratio of the intermediate phase is 0.5 or more. As a result of the comparison, the PWM signal pattern of the intermediate phase shown in FIG. Generated. FIG. 10 is a graph showing the threshold value of the intermediate layer compared with the first carrier wave when the duty ratio of the intermediate phase is less than 0.5. As a result of the comparison, the PWM signal pattern of the intermediate phase shown in FIG. Generated. By changing the threshold of the intermediate layer for each carrier period, one carrier wave is sufficient.
　また、図７および図８では、のこぎり波状のキャリア波を使用したが、三角波状のキャリア波を使用してもよい。三角波状のキャリア波を使用した場合、三角波の頂上または谷底に対して左右対称なＰＷＭ信号パターンを生成することができる。しかし、本実施の形態１以降では、ＰＷＭ信号パターンの高電圧区間と低電圧区間の幅を不規則に変更するので、三角波状のキャリア波を使用するメリットは少ない。一方、のこぎり波状のキャリア波は、パルスを単純な一方向にカウントし続けるタイマを使用して生成することができるため、ＰＷＭ信号生成部７を安価な低機能マイコンを用いて構成することが可能である。なお、ＰＷＭ信号生成部７は、アナログ回路またはデジタル回路によるのこぎり波状のキャリア波発生回路と、キャリア波と閾値との比較器と、キャリア波発生回路をリセットするリセット回路と、リセットのタイミングに同期して判定部６からのデューティ比をサンプルホールドするサンプルホールド回路などの専用のハードウェアを用いても容易に構成可能である。 In FIGS. 7 and 8, a sawtooth carrier wave is used, but a triangular carrier wave may be used. When a triangular carrier wave is used, a PWM signal pattern that is symmetrical with respect to the top or valley bottom of the triangular wave can be generated. However, in the first and subsequent embodiments, the width of the high voltage section and the low voltage section of the PWM signal pattern is irregularly changed, so that there are few merits of using a triangular wave carrier wave. On the other hand, the sawtooth wave carrier wave can be generated using a timer that keeps counting pulses in one simple direction, so that the PWM signal generator 7 can be configured using an inexpensive low-function microcomputer. It is. The PWM signal generation unit 7 is synchronized with a sawtooth wave carrier wave generation circuit using an analog circuit or a digital circuit, a carrier wave / threshold comparator, a reset circuit for resetting the carrier wave generation circuit, and a reset timing. Thus, the hardware can be easily configured using dedicated hardware such as a sample and hold circuit that samples and holds the duty ratio from the determination unit 6.
　また、ＰＷＭ信号生成部７は、最大相および最小相のデューティ比の合計値の半分の値である０．５を基準値とした場合、中間相のデューティ比がこの基準値０．５をまたぐときに、中間相のＰＷＭ信号パターンの位相を１８０度移動させることによって高電圧区間と低電圧区間の順番を逆にして出力する。この具体例を、図１１および図１２を用いて説明する。 Further, when the PWM signal generation unit 7 uses 0.5, which is half the total value of the duty ratios of the maximum phase and the minimum phase, as a reference value, the duty ratio of the intermediate phase crosses this reference value 0.5. When the phase of the intermediate phase PWM signal pattern is shifted by 180 degrees, the high voltage section and the low voltage section are output in reverse order. A specific example will be described with reference to FIGS. 11 and 12.
　図１１は、中間相のデューティ比と、中間相のデューティ比が０．５以上または０．５未満のときの中間相の閾値とを示すグラフである。図１１の時刻Ｔ１～Ｔ５は、図５および図６の時刻Ｔ１～Ｔ５と同じ時刻である。上述したように、中間相のデューティ比が０．５以上である場合の中間相の閾値は｛２×（デューティ比）－１｝であり、中間相のデューティ比が０．５未満である場合の中間相の閾値は｛１－２×（デューティ比）｝である。 FIG. 11 is a graph showing the duty ratio of the intermediate phase and the threshold value of the intermediate phase when the duty ratio of the intermediate phase is 0.5 or more or less than 0.5. Times T1 to T5 in FIG. 11 are the same as the times T1 to T5 in FIGS. As described above, when the duty ratio of the intermediate phase is 0.5 or more, the threshold value of the intermediate phase is {2 × (duty ratio) −1}, and the duty ratio of the intermediate phase is less than 0.5 The intermediate phase threshold value is {1-2 × (duty ratio)}.
　図１２は、中間相であるＷ相のデューティ比が基準値０．５を下回る時刻Ｔ２前後のＰＷＭ信号パターンを示すグラフである。１番上の波形は最大相であるＵ相のＰＷＭ信号パターンである。上から２番目の波形は中間相であるＷ相のＰＷＭ信号パターンであり、時刻Ｔ２でデューティ比が０．５以上になる。上から３番目の波形は最小相であるＶ相のＰＷＭ信号パターンである。ＰＷＭ信号生成部７は、最大相、中間相および最小相のＰＷＭ信号パターンを組み替えて、上から４番目～６番目に示すＰＷＭ信号パターンを生成する。上から４番目の波形はＵ相のＰＷＭ信号パターン、上から５番目の波形はＶ相のＰＷＭ信号パターン、上から６番目の波形はＷ相のＰＷＭ信号パターンである。 FIG. 12 is a graph showing PWM signal patterns before and after time T2 when the duty ratio of the W phase, which is an intermediate phase, falls below the reference value 0.5. The top waveform is a U-phase PWM signal pattern which is the maximum phase. The second waveform from the top is a W-phase PWM signal pattern that is an intermediate phase, and the duty ratio becomes 0.5 or more at time T2. The third waveform from the top is the V-phase PWM signal pattern which is the minimum phase. The PWM signal generation unit 7 generates the fourth to sixth PWM signal patterns from the top by rearranging the maximum phase, intermediate phase, and minimum phase PWM signal patterns. The fourth waveform from the top is the U-phase PWM signal pattern, the fifth waveform from the top is the V-phase PWM signal pattern, and the sixth waveform from the top is the W-phase PWM signal pattern.
　図１１において、ＰＷＭ信号生成部７は、中間相のデューティ比が基準値０．５以上になる時刻Ｔ２で、第２キャリア周期の位相を逆転させる。そのため、図１２に示すように、中間相であるＷ相の時刻Ｔ２直後のＰＷＭ信号パターンの位相が１８０度移動し、高電圧区間と低電圧区間の順番が逆になる。これにより、中間相のデューティ比が０．５をまたぐときに、中間相のＰＷＭ信号パターンが乱れない。 In FIG. 11, the PWM signal generator 7 reverses the phase of the second carrier period at time T2 when the duty ratio of the intermediate phase becomes equal to or higher than the reference value 0.5. Therefore, as shown in FIG. 12, the phase of the PWM signal pattern immediately after the time T2 of the W phase that is the intermediate phase is shifted by 180 degrees, and the order of the high voltage section and the low voltage section is reversed. Thereby, when the duty ratio of the intermediate phase exceeds 0.5, the PWM signal pattern of the intermediate phase is not disturbed.
　また、ＰＷＭ信号生成部７は、デューティ比が最大となる相と中間となる相との入れ替わりが発生した場合、または最小となる相と中間となる相との入れ替わりが発生した場合、入れ替わり後の中間相のＰＷＭ信号パターンの位相を変更してもよい。デューティ比が最大となる相と中間となる相との入れ替わりが発生した場合の例を、図１１および図１３を用いて説明する。 Further, the PWM signal generation unit 7 is configured to switch the phase between the phase having the maximum duty ratio and the intermediate phase, or the switching from the minimum phase to the intermediate phase. The phase of the intermediate phase PWM signal pattern may be changed. An example of the case where the phase having the maximum duty ratio and the intermediate phase are switched will be described with reference to FIGS. 11 and 13.
　図１３は、最大相がＷ相からＵ相に入れ替わる時刻Ｔ１前後のＰＷＭ信号パターンを示すグラフである。１番上の波形は最大相のＰＷＭ信号パターンであり、時刻Ｔ１で最大相がＷ相からＵ相に入れ替わる。上から２番目の波形は中間相のＰＷＭ信号パターンであり、時刻Ｔ１で中間相がＵ相からＷ相に入れ替わる。上から３番目の波形は最小相のＰＷＭ信号パターンであり、最小相はＶ相である。ＰＷＭ信号生成部７は、最大相、中間相および最小相のＰＷＭ信号パターンを組み替えて、上から４番目～６番目に示すＰＷＭ信号パターンを生成する。上から４番目の波形はＵ相のＰＷＭ信号パターン、上から５番目の波形はＶ相のＰＷＭ信号パターン、上から６番目の波形はＷ相のＰＷＭ信号パターンである。 FIG. 13 is a graph showing a PWM signal pattern around time T1 when the maximum phase is switched from the W phase to the U phase. The top waveform is the PWM signal pattern of the maximum phase, and the maximum phase is switched from the W phase to the U phase at time T1. The second waveform from the top is the PWM signal pattern of the intermediate phase, and the intermediate phase is switched from the U phase to the W phase at time T1. The third waveform from the top is the minimum phase PWM signal pattern, and the minimum phase is the V phase. The PWM signal generation unit 7 generates the fourth to sixth PWM signal patterns from the top by rearranging the maximum phase, intermediate phase, and minimum phase PWM signal patterns. The fourth waveform from the top is the U-phase PWM signal pattern, the fifth waveform from the top is the V-phase PWM signal pattern, and the sixth waveform from the top is the W-phase PWM signal pattern.
　図１１において、ＰＷＭ信号生成部７は、Ｗ相が最大相から中間相に入れ替わる時刻Ｔ１で、第２キャリア周期の位相順をリセットし、時刻Ｔ１直後に第２キャリア波を生成する。そして、ＰＷＭ信号生成部７は、時刻Ｔ１直後の第２キャリア波と中間相の閾値との比較により、中間相となったＷ相のデューティ比が基準値０．５を超えている期間において高電圧区間を出力し、出力後に低電圧区間を出力する。そのため、図１３に示すように、時刻Ｔ１直後に中間相のＰＷＭ信号パターンの周期がリセットされ、中間相のＰＷＭ信号パターンの高電圧区間と低電圧区間が切り替わる。Ｗ相のＰＷＭ信号パターンは、時刻Ｔ１より前は第１キャリア波１０ｋＨｚの最大相のＰＷＭ信号パターンとなり、時刻Ｔ１の後は第２キャリア波５ｋＨｚの中間相のＰＷＭ信号パターンとなる。Ｗ相が時刻Ｔ１で最大相から中間相に入れ替わるときに、ＰＷＭ信号パターンがより連続的に変化するようになり、電動機１０におけるトルクの変化が小さくなる。 In FIG. 11, the PWM signal generation unit 7 resets the phase order of the second carrier period at time T1 when the W phase is switched from the maximum phase to the intermediate phase, and generates the second carrier wave immediately after time T1. Then, the PWM signal generation unit 7 compares the second carrier wave immediately after time T1 with the threshold value of the intermediate phase, and the PWM signal generation unit 7 is high during the period when the duty ratio of the W phase that has become the intermediate phase exceeds the reference value 0.5. Outputs the voltage interval and outputs the low voltage interval after output. Therefore, as shown in FIG. 13, immediately after time T1, the cycle of the intermediate phase PWM signal pattern is reset, and the high voltage section and the low voltage section of the intermediate phase PWM signal pattern are switched. The W-phase PWM signal pattern is the maximum-phase PWM signal pattern of the first carrier wave 10 kHz before time T1, and the intermediate-phase PWM signal pattern of the second carrier wave 5 kHz after time T1. When the W phase is switched from the maximum phase to the intermediate phase at time T1, the PWM signal pattern changes more continuously, and the torque change in the electric motor 10 becomes smaller.
　図１４は、電力変換装置１の制御方法を示すフローチャートである。
　ステップＳＴ１において、相電流再現部４は、電流検出素子３を用いて、「３相のうちのある１相の上アーム側のスイッチング素子がオンで、残りの２相の下アーム側のスイッチング素子がオン」となる１組目の通電状態と、「３相のうちのある１相の下アーム側のスイッチング素子がオンで、残りの２相の上アーム側のスイッチング素子がオン」となる２組目の通電状態における母線電流値を検出する。 FIG. 14 is a flowchart illustrating a method for controlling the power conversion apparatus 1.
In step ST 1, the phase current reproduction unit 4 uses the current detection element 3 to say that “the switching element on the upper arm side of one phase among the three phases is on and the switching element on the lower arm side of the remaining two phases. And the first set of energized states where “is on” and “the switching elements on the lower arm side of one phase out of the three phases are on and the switching elements on the upper arm side of the remaining two phases are on” 2 The bus current value in the energized state of the set is detected.
　ステップＳＴ２において、相電流再現部４は、ステップＳＴ１で検出した２組の母線電流値と、そのときのＵ相、Ｖ相およびＷ相のＰＷＭ信号パターンとに基づいて、Ｕ相、Ｖ相およびＷ相の相電流を再現する。 In step ST2, the phase current reproduction unit 4 determines the U phase, the V phase, and the W phase based on the two bus current values detected in step ST1 and the U phase, V phase, and W phase PWM signal patterns at that time. Reproduce the phase current of the W phase.
　ステップＳＴ３において、デューティ生成部５は、相電流再現部４により再現された３相の相電流と、ロータ角度センサ１１により検出された電動機１０のロータ角度とを用いて、Ｕ相、Ｖ相およびＷ相のＰＷＭ信号パターンのデューティ比を生成する。 In step ST <b> 3, the duty generation unit 5 uses the three-phase phase current reproduced by the phase current reproduction unit 4 and the rotor angle of the electric motor 10 detected by the rotor angle sensor 11 to use the U-phase, V-phase, and A duty ratio of a W-phase PWM signal pattern is generated.
　ステップＳＴ４において、判定部６は、デューティ生成部５により生成された３相のＰＷＭ信号パターンのデューティ比の大小関係を判定し、最大相、最小相および中間相に分類する。 In step ST4, the determination unit 6 determines the magnitude relationship between the duty ratios of the three-phase PWM signal patterns generated by the duty generation unit 5 and classifies them into the maximum phase, the minimum phase, and the intermediate phase.
　ステップＳＴ５において、ＰＷＭ信号生成部７は、デューティ生成部５により生成された３相のデューティ比に基づいて最大相、最小相および中間相のＰＷＭ信号パターンを生成する。 In step ST5, the PWM signal generation unit 7 generates a PWM signal pattern of the maximum phase, the minimum phase, and the intermediate phase based on the three-phase duty ratio generated by the duty generation unit 5.
　ステップＳＴ６において、ＰＷＭ信号生成部７は、ステップＳＴ５で生成した最大相、最小相および中間相のＰＷＭ信号パターンを、Ｕ相、Ｖ相およびＷ相のＰＷＭ信号パターンに変換し、インバータ回路２へ出力する。 In step ST6, the PWM signal generation unit 7 converts the maximum phase, minimum phase, and intermediate phase PWM signal patterns generated in step ST5 into U-phase, V-phase, and W-phase PWM signal patterns, and outputs them to the inverter circuit 2. Output.
　以上のように、実施の形態１に係る電力変換装置１は、複数のスイッチング素子ＵＨ，ＵＬ，ＶＨ，ＶＬ，ＷＨ，ＷＬが３相のＰＷＭ信号パターンに従いオンオフすることで、直流を３相交流に変換するインバータ回路２と、インバータ回路２の直流側に接続され、電流に対応する信号を発生する電流検出素子３と、電流検出素子３に発生した信号と３相のＰＷＭ信号パターンとに基づいてインバータ回路２の相電流を再現する相電流再現部４と、相電流再現部４により再現された相電流に基づいて３相のＰＷＭ信号パターンのデューティ比を生成するデューティ生成部５と、デューティ生成部５により生成された３相のＰＷＭ信号パターンのデューティ比の大小関係を判定し、デューティ比が最大となる最大相、最小となる最小相および中間となる中間相に分類する判定部６と、デューティ生成部５により生成されたデューティ比に基づいて３相のＰＷＭ信号パターンを生成する際、中間相のＰＷＭ信号パターンの周期を、最大相または最小相のＰＷＭ信号パターンの周期の２倍以上にするＰＷＭ信号生成部７とを備える構成にした。この電力変換装置１において、相電流再現部４が最大相および最小相のＰＷＭ信号パターンの周期ごとに電流検出素子３を用いて母線電流を検出する構成にした場合、母線電流検出時間を容易に確保することができる。 As described above, in the power conversion device 1 according to the first embodiment, a plurality of switching elements UH, UL, VH, VL, WH, and WL are turned on and off according to a three-phase PWM signal pattern, whereby a direct current is converted into a three-phase alternating current. Based on the inverter circuit 2 for conversion to the current, the current detection element 3 connected to the DC side of the inverter circuit 2 and generating a signal corresponding to the current, the signal generated in the current detection element 3 and the three-phase PWM signal pattern A phase current reproduction unit 4 that reproduces the phase current of the inverter circuit 2, a duty generation unit 5 that generates a duty ratio of a three-phase PWM signal pattern based on the phase current reproduced by the phase current reproduction unit 4, and a duty The magnitude relationship of the duty ratio of the three-phase PWM signal pattern generated by the generation unit 5 is determined, and the maximum phase with the maximum duty ratio, the minimum phase with the minimum, and When the three-phase PWM signal pattern is generated based on the duty ratio generated by the determination unit 6 that classifies the intermediate phase and the duty generation unit 5, the cycle of the intermediate-phase PWM signal pattern is set to the maximum phase or The PWM signal generation unit 7 is configured to make the period of the minimum phase PWM signal pattern more than twice. In this power converter 1, when the phase current reproduction unit 4 is configured to detect the bus current using the current detection element 3 for each period of the maximum phase and minimum phase PWM signal patterns, the bus current detection time can be easily set. Can be secured.
　また、実施の形態１によれば、ＰＷＭ信号生成部７は、最大相および最小相について、ＰＷＭ信号パターンの高電圧区間と低電圧区間のうち、継続時間が短い方の区間を周期の先頭に配置し、中間相について、ＰＷＭ信号パターンの高電圧区間と低電圧区間のうち、継続時間が長い方の区間を周期の先頭に配置する構成であってもよい。最大相と最小相の長い方の区間をまとめることで、中間相のデューティ比が０．５以上である場合、最小相の相電流を第１キャリア周期の０．５以上の期間、検出できる。同様に、中間相のデューティ比が０．５未満である場合は、最大相の相電流を第１キャリア周期の０．５以上の期間、検出できる。 Further, according to the first embodiment, the PWM signal generation unit 7 sets, for the maximum phase and the minimum phase, the interval with the shorter duration between the high voltage interval and the low voltage interval of the PWM signal pattern at the beginning of the cycle. The arrangement may be such that, for the intermediate phase, a section having a longer duration among the high voltage section and the low voltage section of the PWM signal pattern is disposed at the beginning of the cycle. By combining the longer sections of the maximum phase and the minimum phase, when the duty ratio of the intermediate phase is 0.5 or more, the phase current of the minimum phase can be detected for a period of 0.5 or more of the first carrier period. Similarly, when the duty ratio of the intermediate phase is less than 0.5, the phase current of the maximum phase can be detected for a period of 0.5 or more of the first carrier period.
　また、実施の形態１によれば、ＰＷＭ信号生成部７は、最大相のデューティ比と最小相のデューティ比の合計値の半分の値を基準値とし、中間相のデューティ比が基準値をまたぐときに、中間相のＰＷＭ信号パターンの位相を１８０度移動させることによって高電圧区間と低電圧区間の順番を逆にする構成であってもよい。この構成により中間相のＰＷＭ信号パターンが乱れない。 Further, according to the first embodiment, the PWM signal generation unit 7 uses a value that is half of the sum of the maximum phase duty ratio and the minimum phase duty ratio as a reference value, and the intermediate phase duty ratio crosses the reference value. In some cases, the order of the high voltage section and the low voltage section may be reversed by shifting the phase of the intermediate phase PWM signal pattern by 180 degrees. This configuration does not disturb the intermediate phase PWM signal pattern.
　また、実施の形態１によれば、ＰＷＭ信号生成部７は、デューティ比が最大となる相と中間となる相との入れ替わり、または最小となる相と中間となる相との入れ替わりが発生した場合、入れ替わり後の中間相のＰＷＭ信号パターンの位相を変更する構成であってもよい。例えば、ＰＷＭ信号生成部７は、入れ替わり時、中間相のＰＷＭ信号パターンの高電圧区間と低電圧区間を切り替える。これにより、最大相または最小相が中間相に入れ替わるときに、ＰＷＭ信号パターンがより連続的に変化するようになり、電動機１０におけるトルクの変化が小さくなる。 Further, according to the first embodiment, the PWM signal generation unit 7 switches between the phase having the maximum duty ratio and the intermediate phase, or switching between the minimum phase and the intermediate phase. The phase of the PWM signal pattern of the intermediate phase after the replacement may be changed. For example, the PWM signal generation unit 7 switches between a high voltage section and a low voltage section of an intermediate phase PWM signal pattern at the time of switching. Thereby, when the maximum phase or the minimum phase is switched to the intermediate phase, the PWM signal pattern changes more continuously, and the torque change in the electric motor 10 becomes smaller.
　また、実施の形態１によれば、ＰＷＭ信号生成部７は、最大相または最小相のいずれか一方のＰＷＭ信号パターンを反転して、最大相または最小相のいずれか他方のＰＷＭ信号パターンとする構成であってもよい。この構成により、ＰＷＭ信号生成部７の処理がより簡素になるため、安価な低機能マイコンを用いて電力変換装置１を構成することが可能である。 Further, according to the first embodiment, the PWM signal generation unit 7 inverts the PWM signal pattern of either the maximum phase or the minimum phase to obtain the PWM signal pattern of either the maximum phase or the minimum phase. It may be a configuration. With this configuration, the processing of the PWM signal generation unit 7 becomes simpler, so the power conversion device 1 can be configured using an inexpensive low-function microcomputer.
実施の形態２．
　以降の説明のため、デューティ比の大きさ順に相を並べたときの電圧ベクトルを定義する。図１５は、通常用いられる電圧ベクトルＶ０～Ｖ７を示す図である。図１５において、Ｕ相、Ｖ相またはＷ相の上アーム側のスイッチング素子がオンしている状態が「１」に対応し、オフしている状態が「０」に対応している。 Embodiment 2. FIG.
For the following description, a voltage vector when the phases are arranged in order of the duty ratio is defined. FIG. 15 is a diagram showing normally used voltage vectors V0 to V7. In FIG. 15, the state where the switching element on the upper arm side of the U-phase, V-phase or W-phase is on corresponds to “1”, and the off-state corresponds to “0”.
　実施の形態２以降では新たに、最大相、中間相および最小相に対応した、図１６のような電圧ベクトルＶ０，Ｖａ～Ｖｆ，Ｖ７を導入する。最大相がＵ相、中間相がＶ相および最小相がＷ相である場合、Ｖ１はＶａ、Ｖ２はＶｂ、Ｖ３はＶｃ、Ｖ４はＶｄ、Ｖ５はＶｅ、Ｖ６はＶｆになり、Ｖ０とＶ７はそのまま使用される。図１５および図１６に示した逆ベクトルは、各電圧ベクトルの逆方向の電圧ベクトルである。 In the second and subsequent embodiments, voltage vectors V0, Va to Vf, V7 as shown in FIG. 16 corresponding to the maximum phase, intermediate phase, and minimum phase are newly introduced. When the maximum phase is the U phase, the intermediate phase is the V phase, and the minimum phase is the W phase, V1 is Va, V2 is Vb, V3 is Vc, V4 is Vd, V5 is Ve, V6 is Vf, and V0 and V7 Is used as is. The inverse vector shown in FIGS. 15 and 16 is a voltage vector in the reverse direction of each voltage vector.
　また、実施の形態２では、規格化時間と電圧指令値の関係を、以下のように定義する。
　規格化時間は、キャリア波１周期を「１」に規格化した時間を用いて定義されるｔｍａｘ，ｔｍｉｄ，ｔｍｉｎである。ｔｍａｘは、最大相のＰＷＭ信号パターンにおける高電圧区間の時間である。ｔｍｉｄは、中間相のＰＷＭ信号パターンにおける高電圧区間の時間である。ｔｍｉｎは、最小相のＰＷＭ信号パターンにおける高電圧区間の時間である。
　ｖｍａｘは、最大相の電圧指令値である。ｖｍｉｄは、中間相の電圧指令値である。ｖｍｉｎは、最小相の電圧指令値である。
　母線の電圧をｖｂとすると、ｔｍａｘ，ｔｍｉｄ，ｔｍｉｎは以下になる。
　ｔｍａｘ＝ｖｍａｘ／ｖｂ
　ｔｍｉｄ＝ｖｍｉｄ／ｖｂ
　ｔｍｉｎ＝ｖｍｉｎ／ｖｂ In the second embodiment, the relationship between the standardized time and the voltage command value is defined as follows.
The standardized times are tmax, tmid, and tmin defined using the time standardized to “1” for one cycle of the carrier wave. tmax is the time of the high voltage interval in the maximum phase PWM signal pattern. tmid is the time of the high voltage interval in the PWM signal pattern of the intermediate phase. tmin is the time of the high voltage interval in the PWM signal pattern of the minimum phase.
vmax is a voltage command value of the maximum phase. vmid is an intermediate phase voltage command value. vmin is a voltage command value of the minimum phase.
Assuming that the bus voltage is vb, tmax, tmid, and tmin are as follows.
tmax = vmax / vb
tmid = vmid / vb
tmin = vmin / vb
　このように定義すると、上記実施の形態１における最大相、中間相および最小相のＰＷＭ信号パターンは、中間相のデューティ比が０．５以上の場合に図１７、０．５未満の場合に図１８のように表される。図１７および図１８に示されたＰＷＭ信号パターンにおいて、パルス幅の変調率が低い場合、中間相のデューティ比が０．５に近づくため、母線電流検出時間が確保できる。一方、中間相のデューティ比が０または１に近くなると、母線電流検出時間が短くなっていき、安定状態での検出が困難になっていく。 When defined in this way, the maximum phase, intermediate phase, and minimum phase PWM signal patterns in the first embodiment are shown in FIG. 17 when the duty ratio of the intermediate phase is 0.5 or more and less than 0.5. It is expressed as 18. In the PWM signal patterns shown in FIGS. 17 and 18, when the modulation factor of the pulse width is low, the duty ratio of the intermediate phase approaches 0.5, so that the bus current detection time can be secured. On the other hand, when the duty ratio of the intermediate phase is close to 0 or 1, the bus current detection time becomes shorter, and detection in a stable state becomes difficult.
　そこで、実施の形態２に係る電力変換装置１は、ｔｍｉｄが１に近く中間相のＰＷＭ信号パターンの低電圧区間の時間が短くなり、最大相の相電流に相当する母線電流の検出に必要な電圧ベクトルＶｄの出力時間を確保できない場合に、中間相のＰＷＭ信号パターンの周期を、最大相のＰＷＭ信号パターンの周期または最小相のＰＷＭ信号パターンの周期のいずれか短い方の周期の３倍以上にして、母線電流検出時間を長くする。なお、実施の形態２に係る電力変換装置１は、図１に示した実施の形態１の電力変換装置１と図面上同一構成であるため、図１を援用する。 Therefore, the power conversion device 1 according to the second embodiment is required to detect the bus current corresponding to the phase current of the maximum phase because tmid is close to 1 and the time of the low voltage section of the PWM signal pattern of the intermediate phase is shortened. When the output time of the voltage vector Vd cannot be secured, the cycle of the intermediate phase PWM signal pattern is three times or more of the cycle of the maximum phase PWM signal pattern or the cycle of the minimum phase PWM signal pattern, whichever is shorter Thus, the bus current detection time is lengthened. In addition, since the power converter device 1 which concerns on Embodiment 2 is the same structure on the drawing as the power converter device 1 of Embodiment 1 shown in FIG. 1, FIG. 1 is used.
　図１９は、この発明の実施の形態２に係る電力変換装置１における最大相、中間相および最小相のＰＷＭ信号パターンを示すグラフであり、中間相のデューティ比が１に近い場合の例である。ＰＷＭ信号生成部７は、予め定められた上限値および下限値と、中間相のデューティ比とを比較する。ＰＷＭ信号生成部７は、中間相のデューティ比が上限値以上である場合、ｔｍｉｄが１に近く中間相のＰＷＭ信号パターンにおける低電圧区間の時間が短くなり、最大相の相電流検出に必要な電圧ベクトルＶｄの時間を十分に確保できないと判定して、図１９のようなＰＷＭ信号パターンを生成する。つまり、ＰＷＭ信号生成部７は、中間相のＰＷＭ信号パターンを高電圧側に固定したまま、電圧ベクトル－ＶｄとＶｆの出力をＮ回繰り返した後、（Ｎ＋１）（ｔ－ｔｍｉｄ）の期間、中間相のＰＷＭ信号パターンを低電圧側にすることによって電圧ベクトルＶｄを出力する。これにより、最小相の相電流に相当する母線電流を検出するための電圧ベクトルＶｆの時間だけでなく、最大相の相電流に相当する母線電流を検出するための電圧ベクトルＶｄの時間も長くなる。 FIG. 19 is a graph showing PWM signal patterns of the maximum phase, the intermediate phase, and the minimum phase in the power conversion device 1 according to Embodiment 2 of the present invention, and is an example when the duty ratio of the intermediate phase is close to 1. . The PWM signal generation unit 7 compares the predetermined upper limit value and lower limit value with the duty ratio of the intermediate phase. When the duty ratio of the intermediate phase is greater than or equal to the upper limit value, the PWM signal generation unit 7 is close to 1, and the time of the low voltage section in the PWM signal pattern of the intermediate phase is shortened, which is necessary for detecting the phase current of the maximum phase. It is determined that the time of the voltage vector Vd cannot be secured sufficiently, and a PWM signal pattern as shown in FIG. 19 is generated. That is, the PWM signal generation unit 7 repeats the output of the voltage vectors −Vd and Vf N times with the intermediate phase PWM signal pattern fixed to the high voltage side, and then the period of (N + 1) (t−tmid), The voltage vector Vd is output by setting the intermediate phase PWM signal pattern to the low voltage side. Accordingly, not only the time of the voltage vector Vf for detecting the bus current corresponding to the phase current of the minimum phase but also the time of the voltage vector Vd for detecting the bus current corresponding to the phase current of the maximum phase is lengthened. .
　ＰＷＭ信号生成部７は、中間相のデューティ比が下限値未満である場合、ｔｍｉｄが０に近く中間相のＰＷＭ信号パターンにおける高電圧区間の時間が短くなり、最小相の相電流検出に必要な電圧ベクトルＶｆの時間を十分に確保できないと判定する。その場合、ＰＷＭ信号生成部７は、中間相のＰＷＭ信号パターンを低電圧側に固定したまま、電圧ベクトル－ＶｆとＶｄの出力をＮ回繰り返した後、（Ｎ＋１）（ｔ－ｔｍｉｄ）の期間中間相のＰＷＭ信号パターンを高電圧側にすることによって電圧ベクトルＶｆを出力する。これにより、最大相の相電流に相当する母線電流を検出するための電圧ベクトルＶｄの時間だけでなく、最小相の相電流に相当する母線電流を検出するための電圧ベクトルＶｆの時間も長くなる。 When the duty ratio of the intermediate phase is less than the lower limit value, the PWM signal generation unit 7 is close to 0 and the time of the high voltage section in the PWM signal pattern of the intermediate phase is shortened, which is necessary for detecting the phase current of the minimum phase. It is determined that sufficient time for the voltage vector Vf cannot be secured. In this case, the PWM signal generation unit 7 repeats the output of the voltage vectors −Vf and Vd N times with the intermediate phase PWM signal pattern fixed to the low voltage side, and then the period of (N + 1) (t−tmid) The voltage vector Vf is output by setting the intermediate phase PWM signal pattern to the high voltage side. Accordingly, not only the time of the voltage vector Vd for detecting the bus current corresponding to the phase current of the maximum phase but also the time of the voltage vector Vf for detecting the bus current corresponding to the phase current of the minimum phase becomes longer. .
　ＰＷＭ信号生成部７は、中間相のデューティ比が上限値未満または下限値以上である場合、実施の形態１と同様に、中間相のＰＷＭ信号パターンの周期を最大相または最小相のＰＷＭ信号パターンの周期の２倍にする。 When the duty ratio of the intermediate phase is less than the upper limit value or more than the lower limit value, the PWM signal generation unit 7 sets the cycle of the intermediate phase PWM signal pattern to the maximum phase or minimum phase PWM signal pattern as in the first embodiment. 2 times the period.
　以上のように、実施の形態２に係る電力変換装置１のＰＷＭ信号生成部７は、中間相のＰＷＭ信号パターンのデューティ比が予め定められた上限値以上または下限値未満である場合、中間相のＰＷＭ信号パターンの周期を、最大相または最小相のＰＷＭ信号パターンの周期の３倍以上にする構成である。この構成により、中間相のデューティ比が０または１に近い場合であっても、母線電流検出時間を確保することができる。 As described above, when the duty ratio of the PWM signal pattern of the intermediate phase is equal to or higher than the predetermined upper limit value or less than the lower limit value, the PWM signal generation unit 7 of the power conversion device 1 according to the second embodiment The period of the PWM signal pattern is set to be three times or more the period of the PWM signal pattern of the maximum phase or the minimum phase. With this configuration, the bus current detection time can be ensured even when the duty ratio of the intermediate phase is close to 0 or 1.
実施の形態３．
　実施の形態１で説明したように、相電流再現部４は、２周期連続して母線電流を検出することによって、最大相の相電流と最小相の相電流とを交互に再現する。しかし、中間相のデューティ比が１または０に近く母線電流検出時間が短い等の理由により２周期のうちのどちらか一方で母線電流を検出できなかった場合、１相の相電流しか再現できない。そこで、実施の形態３の相電流再現部４は、２周期以上連続して１相の相電流しか再現できなかった場合、再現できた１相の相電流値をＡ、再現できなかった２相の相電流値をＢ，Ｃとする。そして、相電流再現部４は、式Ｂ＋Ｃ＝－Ａを用いて、再現できなかった２相の相電流値Ｂ，Ｃを推定する。その際、相電流再現部４は、相電流値Ｂ，Ｃを、－Ａ／２に漸近するように徐々に変化させていく。例えば、相電流値Ｂ，Ｃの漸近線は以下の式で定義される。ｉは周期の繰り返し回数であり、Ｉｅは電動機１０の特性およびキャリア周期等に基づいて決定された係数である。
　Ｂｉ＝Ｂｉ－１＋（１／Ｉｅ）（Ａｉ／２－Ｂｉ－１）
　Ｃｉ＝Ｃｉ－１＋（１／Ｉｅ）（Ａｉ／２－Ｃｉ－１） Embodiment 3 FIG.
As described in the first embodiment, the phase current reproduction unit 4 alternately reproduces the maximum phase current and the minimum phase current by detecting the bus current continuously for two periods. However, if the bus current cannot be detected in one of the two periods because the duty ratio of the intermediate phase is close to 1 or 0 and the bus current detection time is short, only the phase current of one phase can be reproduced. Therefore, when the phase current reproduction unit 4 of the third embodiment can reproduce only one phase current continuously for two cycles or more, the phase current value of one phase that can be reproduced is A, and the two phases that cannot be reproduced. Let B and C be the phase current values. Then, the phase current reproduction unit 4 estimates the two-phase phase current values B and C that could not be reproduced using the formula B + C = −A. At that time, the phase current reproduction unit 4 gradually changes the phase current values B and C so as to approach -A / 2. For example, the asymptote of the phase current values B and C is defined by the following equation. i is the number of repetitions of the cycle, and Ie is a coefficient determined based on the characteristics of the electric motor 10, the carrier cycle, and the like.
B i = B i-1 + (1 / Ie) (A i / 2-B i-1 )
C i = C i-1 + (1 / Ie) (A i / 2-C i-1 )
　以上のように、実施の形態３に係る電力変換装置１の相電流再現部４は、２周期以上連続して１相の相電流しか再現できなかった場合でも、最大相、最小相および中間相の３相分の相電流を再現することができる。 As described above, the phase current reproduction unit 4 of the power conversion device 1 according to Embodiment 3 can reproduce only the single-phase phase current continuously for two cycles or more even when the maximum phase, the minimum phase, and the intermediate phase are reproduced. The phase current for the three phases can be reproduced.
実施の形態４．
　実施の形態１のＰＷＭ信号操作方法は容易に実施でき、かつ変調率の広い範囲で相電流が再現できる。その一方で、図１７、図１８および図１９に示したように電圧ベクトルＶｄから逆電圧ベクトル－Ｖｄへ切り替わる、または電圧ベクトルＶｆから逆電圧ベクトル－Ｖｆへ切り替わることにより逆方向の電圧がかかる。これにより、電力変換装置１と直流母線との間に無駄な電流が流れ、発熱、ラジオノイズおよび振動が生じる。実施の形態１のＰＷＭ信号操作方法において逆電圧ベクトルへの切り替わりを減らすためには、ゼロ電圧ベクトルＶ０，Ｖ７の時間を増やすことが有効である。このためには、最大相のＰＷＭ信号パターンと最小相のＰＷＭ信号パターンとで高電圧区間と低電圧区間が一致する時間を最大にし、さらに中間相のＰＷＭ信号パターンも最大相および最小相のＰＷＭ信号パターンの高電圧区間と低電圧区間に一致する時間が長くなるようにするとよい。 Embodiment 4 FIG.
The PWM signal operation method of the first embodiment can be easily implemented, and the phase current can be reproduced in a wide range of the modulation rate. On the other hand, a reverse voltage is applied by switching from the voltage vector Vd to the reverse voltage vector −Vd, or from the voltage vector Vf to the reverse voltage vector −Vf as shown in FIGS. Thereby, a useless electric current flows between the power converter device 1 and the DC bus, and heat generation, radio noise, and vibration are generated. In order to reduce the switching to the reverse voltage vector in the PWM signal operation method of the first embodiment, it is effective to increase the time of the zero voltage vectors V0 and V7. For this purpose, the maximum phase PWM signal pattern and the minimum phase PWM signal pattern are maximized in the time when the high voltage section and the low voltage section match, and the intermediate phase PWM signal pattern is also the maximum phase and minimum phase PWM signal. It is preferable that the time corresponding to the high voltage section and the low voltage section of the signal pattern is long.
　電動機１０のトルクは相電流で決定される。相電流はＵ相、Ｖ相およびＷ相の間の電圧差で決定される。キャリア周期は母線電流の変化時間に対して十分短く、相電圧はデューティ比のみに比例する。よって、母線電流から相電流を再現するためのＰＷＭ信号パターンは、（ｔｍａｘ－ｔｍｉｄ）と（ｔｍｉｄ－ｔｍｉｎ）が維持されていれば、各相のＰＷＭ信号パターンの位相およびデューティ比の大きさが変更されてもよい。そこで、実施の形態４では、ＰＷＭ信号生成部７は、以下の規則（１）～（３）に従い、最大相、中間相および最小相のＰＷＭ信号パターンを操作する。なお、実施の形態４に係る電力変換装置１は、図１に示した実施の形態１の電力変換装置１と図面上同一構成であるため、図１を援用する。 The torque of the electric motor 10 is determined by the phase current. The phase current is determined by the voltage difference between the U phase, the V phase, and the W phase. The carrier period is sufficiently short with respect to the change time of the bus current, and the phase voltage is proportional only to the duty ratio. Therefore, if the PWM signal pattern for reproducing the phase current from the bus current is maintained at (tmax-tmid) and (tmid-tmin), the phase of the PWM signal pattern of each phase and the magnitude of the duty ratio are It may be changed. Therefore, in the fourth embodiment, the PWM signal generation unit 7 operates the PWM signal patterns of the maximum phase, the intermediate phase, and the minimum phase according to the following rules (1) to (3). In addition, since the power converter device 1 which concerns on Embodiment 4 is the same structure on the drawing as the power converter device 1 of Embodiment 1 shown in FIG. 1, FIG. 1 is used.
　規則（１）
　最大相、中間相および最小相において、ＰＷＭ信号パターンの高電圧区間の時間は以下の式により定義される。
　ｔｍａｘ＝（ｖｍａｘ－ｖｍｉｎ）／ｖｂ＋ｔｂａｓｅ
　ｔｍｉｄ＝（ｖｍｉｄ－ｖｍｉｎ）／ｖｂ＋ｔｂａｓｅ
　ｔｍｉｎ＝ｔｂａｓｅ
　ただし、ｔｂａｓｅは、ｔｍａｘがキャリア波１周期を規格化した「１」を超えない、０以上の任意の値である。
　規則（２）
　最大相、中間相および最小相のＰＷＭ信号パターンは、相ごとに位相が変更されてもよい。
　規則（３）
　最大相、中間相および最小相のＰＷＭ信号パターンは、高電圧区間が分割されてもよい。 Rule (1)
In the maximum phase, the intermediate phase, and the minimum phase, the time of the high voltage interval of the PWM signal pattern is defined by the following equation.
tmax = (vmax−vmin) / vb + tbase
tmid = (vmid−vmin) / vb + tbase
tmin = tbase
However, tbase is an arbitrary value of 0 or more that does not exceed “1” in which tmax standardizes one cycle of the carrier wave.
Rule (2)
The phase of the PWM signal pattern of the maximum phase, the intermediate phase, and the minimum phase may be changed for each phase.
Rule (3)
The maximum voltage, intermediate phase, and minimum phase PWM signal patterns may be divided into high voltage sections.
　また、ＰＷＭ信号生成部７においてＰＷＭ信号パターンを生成する手順を単純化するために、規則（１）～（３）に対して、以下の規則（４）、（５）を加えてもよい。 Further, in order to simplify the procedure of generating the PWM signal pattern in the PWM signal generation unit 7, the following rules (4) and (5) may be added to the rules (1) to (3).
　規則（４）
　ＰＷＭ信号生成部７が使用するキャリア波は１種類とし、かつ一定周期とする。
　規則（５）
　母線電流検出タイミングは等間隔とする。 Rule (4)
The carrier wave used by the PWM signal generator 7 is of one type and has a constant period.
Rule (5)
The bus current detection timing is equally spaced.
　さらに、以下の規則（６）～（８）を加えてもよい。 Furthermore, the following rules (6) to (8) may be added.
　規則（６）
　母線電流検出時間を長くする。
　規則（７）
　インバータ回路２のスイッチング素子のスイッチングの回数を少なくする。
　規則（８）
　直流電源に向かう電流を少なくする。 Rule (6)
Increase the bus current detection time.
Rule (7)
The number of times of switching of the switching elements of the inverter circuit 2 is reduced.
Rule (8)
Reduce the current going to the DC power supply.
　以上の規則により、ＰＷＭ信号パターンにおけるゼロ電圧ベクトルの時間を最大にした例を、図２０に示す。図２０の例は、上記規則の理解を助けるための参考例であり、実施の形態４のＰＷＭ信号生成部７が実際に生成するＰＷＭ信号パターンではない。この図２０のみ、最大相、中間相および最小相のＰＷＭ信号パターンの周期は同一である。
　図２０の例では、最大相、中間相および最小相のＰＷＭ信号パターンの高電圧区間が同時に開始することで、３相とも高電圧になる時間が最大化される。また、最大相、中間相および最小相のＰＷＭ信号パターンの低電圧区間を周期の終わり側に統一することで、３相とも低電圧になる時間が最大化される。このようにすると、周期最初のｔｍｉｎの間はゼロ電圧ベクトルＶ７になり、周期最後の（１－ｔｍａｘ）の間はゼロ電圧ベクトルＶ０になる。 An example in which the time of the zero voltage vector in the PWM signal pattern is maximized by the above rule is shown in FIG. The example in FIG. 20 is a reference example for helping understanding of the above rules, and is not a PWM signal pattern actually generated by the PWM signal generation unit 7 of the fourth embodiment. Only in FIG. 20, the periods of the PWM signal patterns of the maximum phase, the intermediate phase, and the minimum phase are the same.
In the example of FIG. 20, the high voltage period of the PWM signal pattern of the maximum phase, the intermediate phase, and the minimum phase starts at the same time, thereby maximizing the time during which all three phases are high voltage. Further, by unifying the low voltage sections of the PWM signal pattern of the maximum phase, the intermediate phase, and the minimum phase on the end side of the cycle, the time during which the three phases are low is maximized. In this way, the zero voltage vector V7 is obtained during the first tmin of the cycle, and the zero voltage vector V0 is obtained during the last (1-tmax) of the cycle.
　図２１は、実施の形態４のＰＷＭ信号生成部７が上記規則に従って生成した最大相、中間相および最小相のＰＷＭ信号パターンを示すグラフである。ここでは、ＰＷＭ信号生成部７が、先に示した図１７のＰＷＭ信号パターンを上記規則に従って操作することによって図２１のＰＷＭ信号パターンに変更する場合を説明する。図２１に示す波形は、中間相のデューティ比が０．５以上であり、かつ中間相のＰＷＭ信号パターンの周期が最小相のＰＷＭ信号パターンの周期の２倍である。 FIG. 21 is a graph showing PWM signal patterns of the maximum phase, the intermediate phase, and the minimum phase generated by the PWM signal generation unit 7 of the fourth embodiment according to the above rules. Here, a case will be described in which the PWM signal generation unit 7 changes the PWM signal pattern shown in FIG. 17 to the PWM signal pattern shown in FIG. In the waveform shown in FIG. 21, the duty ratio of the intermediate phase is 0.5 or more, and the cycle of the PWM signal pattern of the intermediate phase is twice the cycle of the PWM signal pattern of the minimum phase.
　ＰＷＭ信号生成部７は、最大相のＰＷＭ信号パターンの位相を変更することによって高電圧側に固定する。ＰＷＭ信号生成部７は、（ｔｍａｘ－ｔｍｉｄ）と（ｔｍｉｄ－ｔｍｉｎ）を維持しつつ、上記規則（１）～（３）に従ってｔｍｉｄとｔｍｉｎを決定し、中間相と最小相のＰＷＭ信号パターンを生成する。また、ＰＷＭ信号生成部７は、ゼロ電圧ベクトルＶ７の時間が長くなるように、ｔｍｉｄとｔｍｉｎを周期の先頭側に配置する。ただし、中間相の周期は最小相の周期の２倍であるため、中間相のＰＷＭ信号パターンの低電圧区間は、最小相の２周期に１度現れることになる。これにより、図２１に示す波形が生成される。図２１のＰＷＭ信号パターンは、キャリア周期ごとに電圧ベクトルＶｆとＶｄが交互に現れるので、最大相の相電流に相当する母線電流と最小相の相電流に相当する母線電流とを交互に検出できる。 The PWM signal generator 7 is fixed to the high voltage side by changing the phase of the maximum phase PWM signal pattern. The PWM signal generation unit 7 determines tmid and tmin according to the above rules (1) to (3) while maintaining (tmax-tmid) and (tmid-tmin), and outputs the PWM signal pattern of the intermediate phase and the minimum phase. Generate. Further, the PWM signal generation unit 7 arranges tmid and tmin on the leading side of the cycle so that the time of the zero voltage vector V7 becomes long. However, since the cycle of the intermediate phase is twice the cycle of the minimum phase, the low voltage section of the PWM signal pattern of the intermediate phase appears once every two cycles of the minimum phase. Thereby, the waveform shown in FIG. 21 is generated. In the PWM signal pattern of FIG. 21, the voltage vectors Vf and Vd appear alternately for each carrier cycle, so that the bus current corresponding to the maximum phase current and the bus current corresponding to the minimum phase current can be detected alternately. .
　中間相のデューティ比が０．５未満の場合、ＰＷＭ信号生成部７は、最小相のＰＷＭ信号パターンの位相を変更することによって低電圧側に固定する。ＰＷＭ信号生成部７は、（ｔｍａｘ－ｔｍｉｄ）と（ｔｍｉｄ－ｔｍｉｎ）を維持しつつ、上記規則（１）～（３）に従ってｔｍａｘとｔｍｉｄを決定し、最大相と中間相のＰＷＭ信号パターンを生成する。また、ＰＷＭ信号生成部７は、ゼロ電圧ベクトルＶ０の時間が長くなるように、ｔｍａｘとｔｍｉｄを周期の終了側に配置する。ただし、中間相の周期は最大相の周期の２倍であるため、中間相のＰＷＭ信号パターンの高電圧区間は、最大相の２周期に１度現れることになる。これにより、中間相のデューティ比が０．５未満の場合でもキャリア周期ごとに電圧ベクトルＶｆとＶｄが交互に現れるようになる。 When the duty ratio of the intermediate phase is less than 0.5, the PWM signal generator 7 fixes the PWM signal pattern of the minimum phase to the low voltage side by changing the phase. The PWM signal generation unit 7 determines tmax and tmid according to the above rules (1) to (3) while maintaining (tmax-tmid) and (tmid-tmin), and determines the PWM signal pattern of the maximum phase and the intermediate phase. Generate. Further, the PWM signal generation unit 7 arranges tmax and tmid on the end side of the cycle so that the time of the zero voltage vector V0 becomes longer. However, since the cycle of the intermediate phase is twice the cycle of the maximum phase, the high voltage section of the PWM signal pattern of the intermediate phase appears once every two cycles of the maximum phase. Thereby, even when the duty ratio of the intermediate phase is less than 0.5, the voltage vectors Vf and Vd appear alternately for each carrier cycle.
　以上のように、実施の形態４に係る電力変換装置１のＰＷＭ信号生成部７は、最大相のＰＷＭ信号パターンを高電圧側に固定する、または最小相のＰＷＭ信号パターンを低電圧側に固定する構成である。これにより、ゼロ電圧ベクトルの時間を最大化することが可能となり、インバータ回路２と直流母線との間に無駄な電流が流れることを防止できる。 As described above, the PWM signal generation unit 7 of the power conversion device 1 according to the fourth embodiment fixes the maximum phase PWM signal pattern to the high voltage side or the minimum phase PWM signal pattern to the low voltage side. It is the structure to do. Thereby, it is possible to maximize the time of the zero voltage vector, and it is possible to prevent useless current from flowing between the inverter circuit 2 and the DC bus.
実施の形態５．
　実施の形態４では、ＰＷＭ信号生成部７は、中間相のデューティ比が０．５以上である場合にゼロ電圧ベクトルＶ７の時間が長くなるようにＰＷＭ信号パターンを操作し、０．５未満である場合にゼロ電圧ベクトルＶ０の時間が長くなるようにＰＷＭ信号パターンを操作した。これに対し、実施の形態５では、ＰＷＭ信号生成部７は、キャリア波の１周期おきにゼロ電圧ベクトルＶ７とＶ０とが入れ替わるように、ＰＷＭ信号パターンを操作する。なお、実施の形態５に係る電力変換装置１は、図１に示した実施の形態１の電力変換装置１と図面上同一構成であるため、図１を援用する。 Embodiment 5 FIG.
In the fourth embodiment, the PWM signal generation unit 7 operates the PWM signal pattern so that the time of the zero voltage vector V7 becomes longer when the duty ratio of the intermediate phase is 0.5 or more, and is less than 0.5. In some cases, the PWM signal pattern was manipulated so that the time of the zero voltage vector V0 was long. On the other hand, in the fifth embodiment, the PWM signal generation unit 7 operates the PWM signal pattern so that the zero voltage vectors V7 and V0 are switched every other period of the carrier wave. In addition, since the power converter device 1 which concerns on Embodiment 5 is the same structure on the drawing as the power converter device 1 of Embodiment 1 shown in FIG. 1, FIG. 1 is used.
　図２２は、実施の形態５のＰＷＭ信号生成部７により生成された最大相、中間相および最大相のＰＷＭ信号パターンを示すグラフである。ＰＷＭ信号生成部７は、キャリア周期Ｐ１，Ｐ３について、最小相のＰＷＭ信号パターンを低電圧側に固定し、上記規則（１）～（３）に従ってゼロ電圧ベクトルＶ０の時間が長くなるように最大相および中間相のＰＷＭ信号パターンを操作する。また、ＰＷＭ信号生成部７は、キャリア周期Ｐ２，Ｐ４について、最大相のＰＷＭ信号パターンを高電圧側に固定し、上記規則（１）～（３）に従ってゼロ電圧ベクトルＶ７の時間が長くなるように中間相および最小相のＰＷＭ信号パターンを操作する。このようにして生成されたＰＷＭ信号パターンにおいて、ゼロ電圧ベクトルＶ０とＶ７の時間は同じになるので、最大相のデューティ比と最小相のデューティ比の合計値の半分の値は０．５になる。この状態で母線電流検出時間が長いＰＷＭ信号パターンが得られる。また、中間相のＰＷＭ信号パターンの位相を変化させたことで、最大相、中間相および最小相のＰＷＭ信号パターンの波形が、ゼロ電圧ベクトルＶ０またはＶ７の中点を対象軸にした左右対称な波形になる。左右対称な波形のＰＷＭ信号パターンのとき、歪みの少ない電流波形が得られる。 FIG. 22 is a graph showing PWM signal patterns of the maximum phase, the intermediate phase, and the maximum phase generated by the PWM signal generation unit 7 of the fifth embodiment. The PWM signal generation unit 7 fixes the minimum phase PWM signal pattern on the low voltage side for the carrier periods P1 and P3, and maximizes the time of the zero voltage vector V0 according to the above rules (1) to (3). Manipulate phase and intermediate phase PWM signal patterns. Further, the PWM signal generation unit 7 fixes the maximum phase PWM signal pattern on the high voltage side for the carrier periods P2 and P4 so that the time of the zero voltage vector V7 becomes longer according to the rules (1) to (3). The intermediate phase and minimum phase PWM signal patterns are manipulated. In the PWM signal pattern generated in this way, the times of the zero voltage vectors V0 and V7 are the same, so half the total value of the maximum phase duty ratio and the minimum phase duty ratio is 0.5. . In this state, a PWM signal pattern with a long bus current detection time is obtained. Further, by changing the phase of the PWM signal pattern of the intermediate phase, the waveforms of the PWM signal pattern of the maximum phase, the intermediate phase, and the minimum phase are symmetrical with respect to the midpoint of the zero voltage vector V0 or V7. It becomes a waveform. When the PWM signal pattern has a symmetrical waveform, a current waveform with less distortion can be obtained.
　以上のように、実施の形態５に係る電力変換装置１のＰＷＭ信号生成部７は、最大相のＰＷＭ信号パターンを高電圧側に固定する周期と、最小相のＰＷＭ信号パターンを低電圧側に固定する周期とを繰り返す構成である。この構成により、最大相、中間相および最小相のＰＷＭ信号パターンの波形を左右対称にすることが可能となり、歪みの少ない電流を１０へ出力することができる。 As described above, the PWM signal generation unit 7 of the power conversion device 1 according to the fifth embodiment fixes the cycle of fixing the maximum phase PWM signal pattern to the high voltage side and the minimum phase PWM signal pattern to the low voltage side. It is the structure which repeats the period to fix. With this configuration, the waveforms of the PWM signal patterns of the maximum phase, the intermediate phase, and the minimum phase can be made symmetrical, and a current with less distortion can be output to 10.
実施の形態６．
　実施の形態５のＰＷＭ信号操作方法では、中間相のＰＷＭ信号パターンのデューティ比が１または０に近い場合に電圧ベクトルＶｄまたはＶｆの時間が短くなり、母線電流検出時間を十分に確保できない場合がある。そこで、実施の形態６では、母線電流検出タイミングから外れた位置のゼロ電圧ベクトルＶ０またはＶ７において、母線電流検出時とは逆の電圧ベクトル－Ｖｄまたは－Ｖｆを出力することにより、母線電流検出時間を長くする。このとき、逆電圧ベクトルにより、力行時にも直流電源に向かう負の電流が母線に発生する。この負の電流が母線電流検出の妨げにならないように、上記の逆電圧ベクトル出力タイミングを母線電流検出タイミングから離すようにする。なお、実施の形態６に係る電力変換装置１は、図１に示した実施の形態１の電力変換装置１と図面上同一構成であるため、図１を援用する。 Embodiment 6 FIG.
In the PWM signal operation method of the fifth embodiment, when the duty ratio of the PWM signal pattern of the intermediate phase is close to 1 or 0, the time of the voltage vector Vd or Vf is shortened, and the bus current detection time may not be sufficiently secured. is there. Therefore, in the sixth embodiment, by outputting a voltage vector −Vd or −Vf opposite to that at the time of detecting the bus current at the zero voltage vector V0 or V7 at a position deviated from the bus current detection timing, Lengthen. At this time, due to the reverse voltage vector, a negative current toward the DC power source is generated in the bus even during powering. The reverse voltage vector output timing is separated from the bus current detection timing so that the negative current does not interfere with the bus current detection. In addition, since the power converter device 1 which concerns on Embodiment 6 is the same structure on the drawing as the power converter device 1 of Embodiment 1 shown in FIG. 1, FIG. 1 is used.
　図２３は、実施の形態６のＰＷＭ信号生成部７により生成された最大相、中間相および最小相のＰＷＭ信号パターンを示すグラフであり、中間相のデューティ比が０．５以上である場合の例である。ＰＷＭ信号生成部７は、図２３のように２回目のキャリア周期における電圧ベクトルＶｄの時間が短いと判定した場合、最初のキャリア周期が終了した時点Ｔ１１において、それまで出力していた電圧ベクトルＶｆの出力後に、本来ゼロ電圧ベクトルＶ７を出力するべく最大相のＰＷＭ信号パターンを高電圧側に維持すべきところを低電圧側にして、逆電圧ベクトル－Ｖｄを出力する。この逆電圧ベクトル－Ｖｄの時間をｔｄｃとする。ＰＷＭ信号生成部７は、２回目のキャリア周期における中間相と最小相のＰＷＭ信号パターンの低電圧区間の時間をｔｄｃだけ延長する。これにより、電圧ベクトルＶｄの時間が延長されて、最大相の相電流に相当する母線電流の検出時間が長くなる。 FIG. 23 is a graph illustrating PWM signal patterns of the maximum phase, the intermediate phase, and the minimum phase generated by the PWM signal generation unit 7 according to the sixth embodiment, where the duty ratio of the intermediate phase is 0.5 or more. It is an example. When the PWM signal generation unit 7 determines that the time of the voltage vector Vd in the second carrier cycle is short as shown in FIG. 23, the voltage vector Vf that has been output so far at the time T11 when the first carrier cycle ends. After the output, the reverse voltage vector -Vd is output by setting the maximum phase PWM signal pattern to be maintained on the high voltage side to output the zero voltage vector V7 on the low voltage side. The time of this reverse voltage vector -Vd is assumed to be tdc. The PWM signal generation unit 7 extends the time of the low voltage section of the PWM signal pattern of the intermediate phase and the minimum phase in the second carrier cycle by tdc. Thereby, the time of the voltage vector Vd is extended, and the detection time of the bus current corresponding to the phase current of the maximum phase becomes longer.
　図２４は、実施の形態６のＰＷＭ信号生成部７により生成された最大相、中間相および最小相のＰＷＭ信号パターンを示すグラフであり、中間相のデューティ比が０．５未満である場合の例である。ＰＷＭ信号生成部７は、図２４のように２回目のキャリア周期における電圧ベクトルＶｆの時間が短いと判定した場合、最初のキャリア周期が終了した時点Ｔ１２において、それまで出力していた電圧ベクトルＶｄの出力後に、本来ゼロ電圧ベクトルＶ０を出力するべく最小相のＰＷＭ信号パターンを低電圧側に維持すべきところを高電圧側にして、逆電圧ベクトル－Ｖｆを出力する。この逆電圧ベクトル－Ｖｆの時間をｔｆｃとする。ＰＷＭ信号生成部７は、２回目のキャリア周期における最大相と中間相のＰＷＭ信号パターンの高電圧区間の時間をｔｆｃだけ延長する。これにより、電圧ベクトルＶｆの時間が延長されて、最小相の相電流に相当する母線電流の検出時間が長くなる。 FIG. 24 is a graph showing PWM signal patterns of the maximum phase, the intermediate phase, and the minimum phase generated by the PWM signal generation unit 7 of the sixth embodiment, where the duty ratio of the intermediate phase is less than 0.5. It is an example. When the PWM signal generation unit 7 determines that the time of the voltage vector Vf in the second carrier cycle is short as shown in FIG. 24, the voltage vector Vd that has been output until then at the time T12 when the first carrier cycle ends. After the output, the reverse voltage vector -Vf is output by setting the minimum phase PWM signal pattern to be maintained on the low voltage side to output the zero voltage vector V0 on the high voltage side. The time of this reverse voltage vector -Vf is assumed to be tfc. The PWM signal generation unit 7 extends the time of the high voltage section of the PWM signal pattern of the maximum phase and the intermediate phase in the second carrier cycle by tfc. Thereby, the time of the voltage vector Vf is extended, and the detection time of the bus current corresponding to the phase current of the minimum phase becomes longer.
　なお、ＰＷＭ信号生成部７は、例えば、実施の形態２で説明したように中間相のデューティ比が上限値以上または下限値未満である場合に、電圧ベクトルＶｄまたはＶｆの時間が短いと判定すればよい。ｔｄｃおよびｔｆｃは、例えば母線電流検出に必要な時間であり、ＰＷＭ信号生成部７に予め定義されている。 The PWM signal generation unit 7 determines that the time of the voltage vector Vd or Vf is short when the duty ratio of the intermediate phase is equal to or higher than the upper limit value or lower than the lower limit value as described in the second embodiment, for example. That's fine. tdc and tfc are, for example, times required for bus current detection, and are defined in advance in the PWM signal generation unit 7.
　図２５は、実施の形態６のＰＷＭ信号生成部７により生成された最大相、中間相および最小相のＰＷＭ信号パターンを示すグラフである。実施の形態６では、実施の形態１とは異なり変調率が低い場合には、電圧ベクトルＶｄの時間と電圧ベクトルＶｆの時間がともに短くなる。このような場合には、ＰＷＭ信号生成部７は、図２３に示した方法で逆電圧ベクトル－Ｖｄを発して母線電流検出のための電圧ベクトルＶｄの時間を長くすると共に、図２４で示した方法で逆電圧ベクトル－Ｖｆを発して母線電流検出のための電圧ベクトルＶｆの時間を長くする。 FIG. 25 is a graph showing the PWM signal patterns of the maximum phase, the intermediate phase, and the minimum phase generated by the PWM signal generation unit 7 of the sixth embodiment. In the sixth embodiment, unlike the first embodiment, when the modulation rate is low, both the time of the voltage vector Vd and the time of the voltage vector Vf are shortened. In such a case, the PWM signal generation unit 7 generates the reverse voltage vector -Vd by the method shown in FIG. 23 to lengthen the time of the voltage vector Vd for detecting the bus current, as shown in FIG. The reverse voltage vector -Vf is generated by the method to increase the time of the voltage vector Vf for detecting the bus current.
　以上のように、実施の形態６に係る電力変換装置１のＰＷＭ信号生成部７は、のこぎり波キャリアを用いてＰＷＭ信号パターンを生成する場合、キャリア周期が終了する時点Ｔ１１において、最大相のＰＷＭ信号パターンを予め定められた時間ｔｄｃだけ低電圧区間にし、当該時点Ｔ１１直後の周期における中間相および最小相のＰＷＭ信号パターンの低電圧区間を予め定められた時間ｔｄｃだけ延長する構成である。この構成により、中間相のデューティ比が１に近い場合であっても、母線電流検出時間を確保することができる。 As described above, when the PWM signal generation unit 7 of the power conversion device 1 according to the sixth embodiment generates a PWM signal pattern using a sawtooth wave carrier, the PWM of the maximum phase at the time T11 when the carrier cycle ends. The signal pattern is set to a low voltage section for a predetermined time tdc, and the low voltage sections of the intermediate phase and minimum phase PWM signal patterns in the period immediately after the time T11 are extended by a predetermined time tdc. With this configuration, the bus current detection time can be secured even when the duty ratio of the intermediate phase is close to 1.
　また、実施の形態６によれば、ＰＷＭ信号生成部７は、のこぎり波キャリアを用いてＰＷＭ信号パターンを生成する場合、キャリア周期が終了する時点Ｔ１２において、最小相のＰＷＭ信号パターンを予め定められた時間ｔｆｃだけ高電圧区間にし、当該時点Ｔ１２直後の周期における最大相および中間相のＰＷＭ信号パターンの高電圧区間を予め定められた時間ｔｆｃだけ延長する構成である。この構成により、中間相のデューティ比が０に近い場合であっても、母線電流検出時間を確保することができる。 Further, according to the sixth embodiment, when the PWM signal generation unit 7 generates a PWM signal pattern using a sawtooth wave carrier, the PWM signal pattern of the minimum phase is determined in advance at time T12 when the carrier cycle ends. The high voltage section is set for the time tfc, and the high voltage sections of the maximum-phase and intermediate-phase PWM signal patterns in the period immediately after the time point T12 are extended by a predetermined time tfc. With this configuration, the bus current detection time can be ensured even when the duty ratio of the intermediate phase is close to zero.
　ここで、実施の形態６において、ＰＷＭ信号生成部７が三角波状のキャリア波を用いてＰＷＭ信号パターンを生成する場合の、ＰＷＭ信号操作方法例を説明する。
　図２６、図２７および図２８は、実施の形態６のＰＷＭ信号生成部７により生成された最大相、中間相および最小相のＰＷＭ信号パターンを示すグラフであり、三角波キャリアを用いた場合の例である。三角波キャリアを使用する場合、相電流再現部４は、三角波キャリアの頂上または谷底、つまり三角波キャリアの値の変化方向が反転する時点Ｔ１１，Ｔ１２の直前で、母線電流を検出する。図２６に示す中間相のデューティ比が０．５以上である場合、ＰＷＭ信号生成部７は、三角波キャリアの値の変化方向が反転する時点Ｔ１１において、最大相のＰＷＭ信号パターンを時間ｔｄｃだけ低電圧区間にし、当該時点Ｔ１１直後の周期における中間相および最小相のＰＷＭ信号パターンの低電圧区間を予め定められた時間ｔｄｃだけ延長する。一方、図２７に示す中間相のデューティ比が０．５未満である場合、ＰＷＭ信号生成部７は、三角波キャリアの値の変化方向が反転する時点Ｔ１２直後の周期における最小相のＰＷＭ信号パターンを予め定められた時間ｔｆｃだけ高電圧区間にし、当該時点Ｔ１２直後の周期における最大相および中間相のＰＷＭ信号パターンの高電圧区間を予め定められた時間ｔｆｃだけ延長する。また、変調率が低く電圧ベクトルＶｄの時間と電圧ベクトルＶｆの時間がともに短くなるような場合には、ＰＷＭ信号生成部７は、図２６と図２７において説明した方法を組み合わせて図２８に示すＰＷＭ信号パターンを生成すればよい。以上の構成により、三角波キャリアを使用する場合でも、のこぎり波キャリアを使用する場合と同様に母線電流検出時間を確保することができる。 Here, in Embodiment 6, an example of a PWM signal operation method when the PWM signal generation unit 7 generates a PWM signal pattern using a triangular carrier wave will be described.
FIG. 26, FIG. 27 and FIG. 28 are graphs showing the PWM signal patterns of the maximum phase, intermediate phase and minimum phase generated by the PWM signal generation unit 7 of the sixth embodiment, and an example when a triangular wave carrier is used. It is. When the triangular wave carrier is used, the phase current reproduction unit 4 detects the bus current just before the top or valley bottom of the triangular wave carrier, that is, immediately before the time points T11 and T12 when the change direction of the value of the triangular wave carrier is reversed. When the duty ratio of the intermediate phase shown in FIG. 26 is 0.5 or more, the PWM signal generation unit 7 reduces the maximum-phase PWM signal pattern by time tdc at time T11 when the change direction of the triangular wave carrier value is reversed. In the voltage period, the low voltage period of the PWM signal pattern of the intermediate phase and the minimum phase in the period immediately after the time point T11 is extended by a predetermined time tdc. On the other hand, when the duty ratio of the intermediate phase shown in FIG. 27 is less than 0.5, the PWM signal generation unit 7 displays the PWM signal pattern of the minimum phase in the period immediately after time T12 when the change direction of the triangular wave carrier value is reversed. The high voltage section is set for a predetermined time tfc, and the high voltage sections of the maximum phase and intermediate phase PWM signal patterns in the period immediately after the time T12 are extended by the predetermined time tfc. Further, when the modulation rate is low and the time of the voltage vector Vd and the time of the voltage vector Vf are both short, the PWM signal generation unit 7 is shown in FIG. 28 by combining the methods described in FIGS. A PWM signal pattern may be generated. With the above configuration, even when a triangular wave carrier is used, the bus current detection time can be ensured as in the case of using a sawtooth wave carrier.
実施の形態７．
　実施の形態７に係る電力変換装置１は、図１に示した実施の形態１の電力変換装置１と図面上同一構成であるため、図１を援用する。 Embodiment 7 FIG.
The power conversion device 1 according to the seventh embodiment has the same configuration as the power conversion device 1 according to the first embodiment shown in FIG.
　図２９は、実施の形態７のＰＷＭ信号生成部７により生成された最大相、中間相および最小相のＰＷＭ信号パターンを示すグラフであり、中間相のデューティ比が基準値０．５以上である場合の例である。図２９に示す最大相、中間相および最小相のＰＷＭ信号パターンの操作前の波形は、図２２に示したキャリア周期Ｐ１，Ｐ２における最大相、中間相および最小相のＰＷＭ信号パターンの波形と同じであるものとする。ＰＷＭ信号生成部７は、最大相の相電流に相当する母線電流を検出する電圧ベクトルＶｄの時間を長くするために、キャリア波の２回に１回のみ電圧ベクトルＶｄを出力するように、中間相のＰＷＭ信号パターンを操作する。その際、ＰＷＭ信号生成部７は、図２２に示した中間相のＰＷＭ信号パターンの高電圧区間の開始位置を、ゼロ電圧ベクトルＶ０，Ｖ７を除いた期間のうちの最大相のＰＷＭ信号パターンが高電圧区間かつ最小相のＰＷＭ信号パターンが低電圧区間になる時点Ｔ２１までずらす。さらに、ＰＷＭ信号生成部７は、中間相のＰＷＭ信号パターンの高電圧区間の開始位置をずらした分だけ、当該高電圧区間の終了位置もずらす。これにより、図２９における電圧ベクトルＶｄの時間は、図２２におけるキャリア周期Ｐ２の電圧ベクトルＶｄの時間の２倍になり、最大相の相電流に相当する母線電流の検出時間が長くなる。 FIG. 29 is a graph showing PWM signal patterns of the maximum phase, intermediate phase, and minimum phase generated by the PWM signal generation unit 7 of the seventh embodiment, and the duty ratio of the intermediate phase is a reference value of 0.5 or more. This is an example. The waveforms before operation of the maximum phase, intermediate phase, and minimum phase PWM signal patterns shown in FIG. 29 are the same as the waveforms of the maximum phase, intermediate phase, and minimum phase PWM signal patterns in the carrier periods P1 and P2 shown in FIG. Suppose that In order to increase the time of the voltage vector Vd for detecting the bus current corresponding to the phase current of the maximum phase, the PWM signal generator 7 outputs the voltage vector Vd only once every two carrier waves. Manipulate the phase PWM signal pattern. At that time, the PWM signal generation unit 7 sets the start position of the high voltage interval of the intermediate phase PWM signal pattern shown in FIG. 22 as the maximum phase PWM signal pattern in the period excluding the zero voltage vectors V0 and V7. The PWM signal pattern in the high voltage section and the minimum phase is shifted to time T21 when it becomes the low voltage section. Further, the PWM signal generation unit 7 shifts the end position of the high voltage section by the amount by which the start position of the high voltage section of the intermediate phase PWM signal pattern is shifted. Thus, the time of voltage vector Vd in FIG. 29 is twice the time of voltage vector Vd of carrier cycle P2 in FIG. 22, and the detection time of the bus current corresponding to the phase current of the maximum phase is lengthened.
　図３０は、実施の形態７のＰＷＭ信号生成部７により生成された最大相、中間相および最小相のＰＷＭ信号パターンを示すグラフであり、中間相のデューティ比が基準値０．５未満である場合の例である。図３０に示す最大相、中間相および最小相のＰＷＭ信号パターンの操作前の波形は、図２２に示したキャリア周期Ｐ２，Ｐ３における最大相、中間相および最小相のＰＷＭ信号パターンの波形と同じであるものとする。ＰＷＭ信号生成部７は、最小相の相電流に相当する母線電流を検出する電圧ベクトルＶｆの時間を長くするために、キャリア波の２回に１回のみ電圧ベクトルＶｆを出力するように、中間相のＰＷＭ信号パターンを操作する。その際、ＰＷＭ信号生成部７は、図２２に示した中間相のＰＷＭ信号パターンの低電圧区間の開始位置を、ゼロ電圧ベクトルＶ０，Ｖ７を除いた期間のうちの最大相のＰＷＭ信号パターンが高電圧区間かつ最小相のＰＷＭ信号パターンが低電圧区間になる時点Ｔ２２までずらす。さらに、ＰＷＭ信号生成部７は、中間相のＰＷＭ信号パターンの低電圧区間の開始位置をずらした分だけ、当該低電圧区間の終了位置もずらす。これにより、図３０における電圧ベクトルＶｆの時間は、図２２におけるキャリア周期Ｐ３の電圧ベクトルＶｆの時間の２倍になり、最小相の相電流に相当する母線電流の検出時間が長くなる。 FIG. 30 is a graph showing the PWM signal patterns of the maximum phase, the intermediate phase, and the minimum phase generated by the PWM signal generation unit 7 of the seventh embodiment, and the duty ratio of the intermediate phase is less than the reference value 0.5. This is an example. The waveforms of the maximum phase, intermediate phase, and minimum phase PWM signal patterns shown in FIG. 30 before operation are the same as the waveforms of the maximum phase, intermediate phase, and minimum phase PWM signal patterns in the carrier periods P2 and P3 shown in FIG. Suppose that The PWM signal generator 7 outputs the voltage vector Vf only once every two carrier waves in order to increase the time of the voltage vector Vf for detecting the bus current corresponding to the phase current of the minimum phase. Manipulate the phase PWM signal pattern. At that time, the PWM signal generation unit 7 determines the start position of the low voltage interval of the intermediate phase PWM signal pattern shown in FIG. 22 as the maximum phase PWM signal pattern in the period excluding the zero voltage vectors V0 and V7. The PWM signal pattern in the high voltage section and the minimum phase is shifted to time T22 when it becomes the low voltage section. Further, the PWM signal generation unit 7 shifts the end position of the low voltage section by the amount by which the start position of the low voltage section of the intermediate phase PWM signal pattern is shifted. Thereby, the time of voltage vector Vf in FIG. 30 is twice the time of voltage vector Vf of carrier period P3 in FIG. 22, and the detection time of the bus current corresponding to the phase current of the minimum phase becomes longer.
　以上のように、実施の形態７に係る電力変換装置１のＰＷＭ信号生成部７は、最大相のデューティ比と最小相のデューティ比の合計値の半分の値を基準値とし、中間相のデューティ比が基準値以上の場合、中間相のＰＷＭ信号パターンの高電圧区間の開始位置を、インバータ回路２の出力電圧がゼロになるゼロ電圧ベクトルを除いた期間のうちの最大相のＰＷＭ信号パターンが高電圧区間かつ最小相のＰＷＭ信号パターンが低電圧区間になる時点Ｔ２１までずらし、開始位置をずらした分だけ終了位置もずらす構成である。また、ＰＷＭ信号生成部７は、中間相のデューティ比が基準値未満の場合、中間相のＰＷＭ信号パターンの低電圧区間の開始位置を、インバータ回路の出力電圧がゼロになるゼロ電圧ベクトルを除いた期間のうちの最大相のＰＷＭ信号パターンが高電圧区間かつ最小相のＰＷＭ信号パターンが低電圧区間になる時点Ｔ２２までずらし、開始位置をずらした分だけ終了位置もずらす構成である。この構成により、実施の形態５に比べて、母線電流検出時間を長くすることができる。さらに、電圧ベクトルＶｄ，Ｖｆ，Ｖ０，Ｖ７以外の電圧ベクトルを出力しないので、無駄な電流が母線に流れない。 As described above, the PWM signal generation unit 7 of the power conversion device 1 according to the seventh embodiment uses the half value of the total value of the maximum phase duty ratio and the minimum phase duty ratio as the reference value, and the intermediate phase duty When the ratio is equal to or higher than the reference value, the maximum phase PWM signal pattern in the period excluding the zero voltage vector where the output voltage of the inverter circuit 2 is zero is indicated as the start position of the high voltage interval of the intermediate phase PWM signal pattern. The configuration is such that the PWM signal pattern in the high voltage section and the minimum phase is shifted to time T21 when the low voltage section is reached, and the end position is also shifted by the amount by which the start position is shifted. Further, the PWM signal generation unit 7 excludes the start position of the low voltage section of the PWM signal pattern of the intermediate phase from the zero voltage vector where the output voltage of the inverter circuit becomes zero when the duty ratio of the intermediate phase is less than the reference value. In this period, the maximum phase PWM signal pattern is shifted to a time T22 in which the minimum phase PWM signal pattern is in the high voltage section and the minimum phase PWM signal pattern is in the low voltage section, and the end position is shifted by the shift of the start position. With this configuration, it is possible to lengthen the bus current detection time as compared with the fifth embodiment. Furthermore, since no voltage vector other than voltage vectors Vd, Vf, V0, and V7 is output, useless current does not flow to the bus.
実施の形態８．
　実施の形態７のＰＷＭ信号操作方法では、逆電圧ベクトルは出力しないものの、母線電流検出時間を実施の形態５のＰＷＭ信号操作方法による母線電流検出時間と比べて２倍より長くすることはできない。相電流再現部４に使用する電流検出回路の応答性が遅い等の理由により、母線電流検出時間をさらに長くする必要がある場合、実施の形態８のＰＷＭ信号操作方法によって母線電流検出時間を２倍より長くすることが可能である。なお、実施の形態８に係る電力変換装置１は、図１に示した実施の形態１の電力変換装置１と図面上同一構成であるため、図１を援用する。 Embodiment 8 FIG.
Although the reverse voltage vector is not output in the PWM signal operation method of the seventh embodiment, the bus current detection time cannot be longer than twice the bus current detection time by the PWM signal operation method of the fifth embodiment. When it is necessary to further increase the bus current detection time because the response of the current detection circuit used for the phase current reproduction unit 4 is slow, the bus current detection time is set to 2 by the PWM signal operation method of the eighth embodiment. It is possible to make it longer than twice. In addition, since the power converter device 1 which concerns on Embodiment 8 is the same structure on the drawing as the power converter device 1 of Embodiment 1 shown in FIG. 1, FIG. 1 is used.
　図３１は、実施の形態８のＰＷＭ信号生成部７により生成された最大相、中間相および最小相のＰＷＭ信号パターンを示すグラフであり、中間相のデューティ比が基準値０．５以上である場合の例である。図３１に示す最大相、中間相および最小相のＰＷＭ信号パターンの操作前の波形は、図２９に示した最大相、中間相および最小相のＰＷＭ信号パターンの波形と同じであるものとする。ＰＷＭ信号生成部７は、最大相の相電流に相当する母線電流を検出する電圧ベクトルＶｄの時間を図２９における当該時間より長くするために、中間相のＰＷＭ信号パターンの高電圧区間の開始位置を、時点Ｔ２１よりも進角側にずらす。さらに、ＰＷＭ信号生成部７は、中間相のＰＷＭ信号パターンの高電圧区間の開始位置をずらした分だけ、当該高電圧区間の終了位置もずらす。これにより、図３１における電圧ベクトルＶｄの時間は、図２９における電圧ベクトルＶｄの時間より長くなり、最大相の相電流に相当する母線電流の検出時間がさらに長くなる。 FIG. 31 is a graph showing PWM signal patterns of the maximum phase, intermediate phase, and minimum phase generated by the PWM signal generation unit 7 of the eighth embodiment, and the duty ratio of the intermediate phase is a reference value of 0.5 or more. This is an example. Waveforms before operation of the maximum phase, intermediate phase, and minimum phase PWM signal patterns shown in FIG. 31 are the same as the waveforms of the maximum phase, intermediate phase, and minimum phase PWM signal patterns shown in FIG. The PWM signal generator 7 starts the position of the high voltage section of the PWM signal pattern in the intermediate phase in order to make the time of the voltage vector Vd for detecting the bus current corresponding to the phase current of the maximum phase longer than the time in FIG. Is shifted to the advance side from the time T21. Further, the PWM signal generation unit 7 shifts the end position of the high voltage section by the amount by which the start position of the high voltage section of the intermediate phase PWM signal pattern is shifted. Thereby, the time of voltage vector Vd in FIG. 31 becomes longer than the time of voltage vector Vd in FIG. 29, and the detection time of the bus current corresponding to the phase current of the maximum phase becomes further longer.
　図３２は、実施の形態８のＰＷＭ信号生成部７により生成された最大相、中間相および最小相のＰＷＭ信号パターンを示すグラフであり、中間相のデューティ比が基準値０．５未満である場合の例である。図３２に示す最大相、中間相および最小相のＰＷＭ信号パターンの操作前の波形は、図３０に示した最大相、中間相および最小相のＰＷＭ信号パターンの波形と同じであるものとする。ＰＷＭ信号生成部７は、最小相の相電流に相当する母線電流を検出する電圧ベクトルＶｆの時間を図３０における当該時間より長くするために、中間相のＰＷＭ信号パターンの低電圧区間の開始位置を、時点Ｔ２２よりも進角側にずらす。さらに、ＰＷＭ信号生成部７は、中間相のＰＷＭ信号パターンの低電圧区間の開始位置をずらした分だけ、当該低電圧区間の終了位置もずらす。これにより、図３２における電圧ベクトルＶｆの時間は、図３０における電圧ベクトルＶｆの時間より長くなり、最小相の相電流に相当する母線電流の検出時間がさらに長くなる。 FIG. 32 is a graph showing PWM signal patterns of the maximum phase, the intermediate phase, and the minimum phase generated by the PWM signal generation unit 7 of Embodiment 8, and the duty ratio of the intermediate phase is less than the reference value 0.5. This is an example. The waveforms before operation of the maximum phase, intermediate phase, and minimum phase PWM signal patterns shown in FIG. 32 are the same as the waveforms of the maximum phase, intermediate phase, and minimum phase PWM signal patterns shown in FIG. The PWM signal generator 7 starts the position of the low voltage section of the PWM signal pattern of the intermediate phase in order to make the time of the voltage vector Vf for detecting the bus current corresponding to the phase current of the minimum phase longer than the time in FIG. Is shifted to the advance side with respect to time T22. Further, the PWM signal generation unit 7 shifts the end position of the low voltage section by the amount by which the start position of the low voltage section of the intermediate phase PWM signal pattern is shifted. Thereby, the time of voltage vector Vf in FIG. 32 becomes longer than the time of voltage vector Vf in FIG. 30, and the detection time of the bus current corresponding to the phase current of the minimum phase becomes further longer.
　以上のように、実施の形態８に係る電力変換装置１のＰＷＭ信号生成部７は、中間相のデューティ比が基準値以上の場合、中間相のＰＷＭ信号パターンの高電圧区間の開始位置を、ゼロ電圧ベクトルを除いた期間のうちの最大相のＰＷＭ信号パターンが高電圧区間かつ最小相のＰＷＭ信号パターンが低電圧区間になる時点Ｔ２１よりも進角側にずらす構成である。また、ＰＷＭ信号生成部７は、中間相のデューティ比が基準値未満の場合、中間相のＰＷＭ信号パターンの低電圧区間の開始位置を、ゼロ電圧ベクトルを除いた期間のうちの最大相のＰＷＭ信号パターンが高電圧区間かつ最小相のＰＷＭ信号パターンが低電圧区間になる時点Ｔ２２よりも進角側にずらす構成である。この構成により、実施の形態５，７に比べて、母線電流検出時間を長くすることができる。さらに、中間相のＰＷＭ信号パターンの操作により電圧ベクトルＶｂまたはＶｅが発生するが、逆電圧ベクトルではないので母線を逆流する電流は少なくてすむ。 As described above, the PWM signal generation unit 7 of the power conversion device 1 according to the eighth embodiment determines the start position of the high voltage section of the intermediate phase PWM signal pattern when the intermediate phase duty ratio is greater than or equal to the reference value. In this configuration, the maximum phase PWM signal pattern in the period excluding the zero voltage vector is shifted to the advance side from the time T21 in which the minimum phase PWM signal pattern is in the high voltage section and the minimum phase PWM signal pattern is in the low voltage section. Further, when the duty ratio of the intermediate phase is less than the reference value, the PWM signal generation unit 7 determines the start position of the low voltage section of the PWM signal pattern of the intermediate phase as the maximum phase PWM in the period excluding the zero voltage vector. In this configuration, the signal pattern is shifted to the advance side from time T22 when the PWM signal pattern in the high voltage section and the minimum phase PWM signal pattern is in the low voltage section. With this configuration, it is possible to lengthen the bus current detection time as compared with the fifth and seventh embodiments. Further, the voltage vector Vb or Ve is generated by the operation of the intermediate phase PWM signal pattern. However, since it is not the reverse voltage vector, the current flowing back through the bus can be reduced.
実施の形態９．
　実施の形態８のＰＷＭ信号操作方法では、電圧ベクトルＶｂまたはＶｅを発することで母線電流検出時間を長くした。これに対し、実施の形態９では、実施の形態２と同様に中間相のＰＷＭ信号パターンの周期を、最大相または最小相のＰＷＭ信号パターンの周期の３倍以上にすることによって、中間相のＰＷＭ信号パターンの周期最後における母線電流検出時間を長くする。なお、実施の形態９に係る電力変換装置１は、図１に示した実施の形態１の電力変換装置１と図面上同一構成であるため、図１を援用する。 Embodiment 9 FIG.
In the PWM signal operation method of the eighth embodiment, the bus current detection time is extended by generating the voltage vector Vb or Ve. In contrast, in the ninth embodiment, as in the second embodiment, the cycle of the intermediate phase PWM signal pattern is set to be three times or more the cycle of the maximum phase or minimum phase PWM signal pattern. The bus current detection time at the end of the period of the PWM signal pattern is lengthened. In addition, since the power converter device 1 which concerns on Embodiment 9 is the same structure on the drawing as the power converter device 1 of Embodiment 1 shown in FIG. 1, FIG. 1 is used.
　図３３は、実施の形態９のＰＷＭ信号生成部７により生成された最大相、中間相および最小相のＰＷＭ信号パターンを示すグラフであり、中間相のデューティ比が１に近い場合の例である。ＰＷＭ信号生成部７は、予め定められた上限値および下限値と、中間相のデューティ比とを比較する。ＰＷＭ信号生成部７は、中間相のデューティ比が上限値以上である場合、最大相の相電流検出に必要な電圧ベクトルＶｄの時間を十分に確保できないと判定して、図３３のようなＰＷＭ信号パターンを生成する。図３３の例は、中間相のＰＷＭ信号パターンの周期が、最小相のＰＷＭ信号パターンの周期のｎ＝３倍になっている。まず、ＰＷＭ信号生成部７は、実施の形態７で説明したＰＷＭ信号操作方法によりゼロ電圧ベクトルの時間を最大化し、図３３に示すキャリア周期Ｐ１１のＰＷＭ信号パターンにする。図３３に示すキャリア周期Ｐ１１のＰＷＭ信号パターンの波形は、図２９に示した１回目のキャリア周期のＰＷＭ信号パターンの波形と同じである。次に、ＰＷＭ信号生成部７は、電圧ベクトルＶ７とＶｆからなるキャリア周期Ｐ１２のＰＷＭ信号パターンを、ｎ－１回出力する。最後に、ＰＷＭ信号生成部７は、図２９に示した２回目のキャリア周期のＰＷＭ信号パターンにおける電圧ベクトルＶｄをｎ倍し、図３３に示すキャリア周期Ｐ１３のＰＷＭ信号パターンにする。このようにすると、デューティ比を変化させずに電圧ベクトルＶｄの時間を延長することができると共に、余分な電圧ベクトルの発生をなくすことで母線に逆流する電流を減らせる。 FIG. 33 is a graph showing the PWM signal patterns of the maximum phase, the intermediate phase, and the minimum phase generated by the PWM signal generation unit 7 of the ninth embodiment, and is an example when the duty ratio of the intermediate phase is close to 1. . The PWM signal generation unit 7 compares the predetermined upper limit value and lower limit value with the duty ratio of the intermediate phase. When the duty ratio of the intermediate phase is greater than or equal to the upper limit value, the PWM signal generation unit 7 determines that the time of the voltage vector Vd necessary for detecting the phase current of the maximum phase cannot be sufficiently secured, and the PWM signal as shown in FIG. Generate a signal pattern. In the example of FIG. 33, the period of the PWM signal pattern of the intermediate phase is n = 3 times the period of the PWM signal pattern of the minimum phase. First, the PWM signal generation unit 7 maximizes the time of the zero voltage vector by the PWM signal operation method described in the seventh embodiment to obtain a PWM signal pattern of the carrier cycle P11 shown in FIG. The waveform of the PWM signal pattern of the carrier cycle P11 shown in FIG. 33 is the same as the waveform of the PWM signal pattern of the first carrier cycle shown in FIG. Next, the PWM signal generation unit 7 outputs a PWM signal pattern of the carrier cycle P12 composed of the voltage vectors V7 and Vf n-1 times. Finally, the PWM signal generation unit 7 multiplies the voltage vector Vd in the PWM signal pattern of the second carrier cycle shown in FIG. 29 to obtain a PWM signal pattern of the carrier cycle P13 shown in FIG. In this way, the time of the voltage vector Vd can be extended without changing the duty ratio, and the current flowing back to the bus can be reduced by eliminating the generation of an extra voltage vector.
　ＰＷＭ信号生成部７は、中間相のデューティ比が下限値未満である場合、最小相の相電流検出に必要な電圧ベクトルＶｆの時間を十分に確保できないと判定する。その場合、ＰＷＭ信号生成部７は、実施の形態７で説明したＰＷＭ信号操作方法によりゼロ電圧ベクトルの時間を最大化し、図３０に示した１回目のキャリア周期のＰＷＭ信号パターンと同じ波形を出力する。次に、ＰＷＭ信号生成部７は、電圧ベクトルＶ０とＶｄからなるキャリア周期のＰＷＭ信号パターンをｎ－１回出力する。最後に、ＰＷＭ信号生成部７は、図３０に示した２回目のキャリア周期のＰＷＭ信号パターンにおける電圧ベクトルＶｆをｎ倍した波形を出力する。このようにすると、デューティ比を変化させずに電圧ベクトルＶｆの時間を延長することができると共に、余分な電圧ベクトルの発生をなくすことで母線に逆流する電流を減らせる。 The PWM signal generator 7 determines that the time of the voltage vector Vf necessary for detecting the phase current of the minimum phase cannot be sufficiently secured when the duty ratio of the intermediate phase is less than the lower limit value. In that case, the PWM signal generation unit 7 maximizes the time of the zero voltage vector by the PWM signal operation method described in the seventh embodiment, and outputs the same waveform as the PWM signal pattern of the first carrier cycle shown in FIG. To do. Next, the PWM signal generation unit 7 outputs the PWM signal pattern of the carrier cycle composed of the voltage vectors V0 and Vd n-1 times. Finally, the PWM signal generation unit 7 outputs a waveform obtained by multiplying the voltage vector Vf in the PWM signal pattern of the second carrier cycle shown in FIG. 30 by n times. In this way, the time of the voltage vector Vf can be extended without changing the duty ratio, and the current flowing back to the bus can be reduced by eliminating the generation of an extra voltage vector.
　なお、ＰＷＭ信号生成部７は、ゼロ電圧ベクトルＶ０とＶ７のどちらを用いてもよい。例えば中間相のデューティ比が上限値以上である場合を示した図３３において、最大相の相電流に相当する母線電流を検出する電圧ベクトルＶｄの後、ゼロ電圧ベクトルＶ０を用いることにより、スイッチング回数を削減できる。同様に、中間相のデューティ比が下限値未満である場合において、最小相の相電流に相当する母線電流を検出する電圧ベクトルＶｆの後、ゼロ電圧ベクトルＶ７を用いることにより、スイッチング回数を削減できる。
　実施の形態６～８のＰＷＭ信号操作方法においても、ＰＷＭ信号生成部７は、ゼロ電圧ベクトルＶ０とＶ７のどちらを用いてもよい。 Note that the PWM signal generation unit 7 may use either of the zero voltage vectors V0 and V7. For example, in FIG. 33 showing the case where the duty ratio of the intermediate phase is equal to or higher than the upper limit value, the number of switchings is obtained by using the zero voltage vector V0 after the voltage vector Vd for detecting the bus current corresponding to the phase current of the maximum phase. Can be reduced. Similarly, when the duty ratio of the intermediate phase is less than the lower limit value, the number of times of switching can be reduced by using the zero voltage vector V7 after the voltage vector Vf for detecting the bus current corresponding to the phase current of the minimum phase. .
Also in the PWM signal operation methods of the sixth to eighth embodiments, the PWM signal generation unit 7 may use either of the zero voltage vectors V0 and V7.
　以上のように、実施の形態９に係る電力変換装置１のＰＷＭ信号生成部７は、上記実施の形態１と同様に、中間相のＰＷＭ信号パターンのデューティ比が予め定められた上限値以上または下限値未満である場合、中間相のＰＷＭ信号パターンの周期を、最大相または最小相のＰＷＭ信号パターンの周期の３倍以上にする構成である。この構成により、実施の形態４以降のＰＷＭ信号操作方法において中間相のデューティ比が０または１に近い場合であっても、母線電流検出時間を確保することができる。 As described above, the PWM signal generation unit 7 of the power conversion device 1 according to the ninth embodiment is similar to the first embodiment in that the duty ratio of the intermediate-phase PWM signal pattern is equal to or higher than a predetermined upper limit value or When it is less than the lower limit value, the period of the PWM signal pattern of the intermediate phase is set to be three times or more the period of the PWM signal pattern of the maximum phase or the minimum phase. With this configuration, the bus current detection time can be ensured even when the duty ratio of the intermediate phase is close to 0 or 1 in the PWM signal operation method after the fourth embodiment.
　なお、本発明はその発明の範囲内において、各実施の形態の自由な組み合わせ、各実施の形態の任意の構成要素の変形、または各実施の形態の任意の構成要素の省略が可能である。 In the present invention, within the scope of the invention, free combinations of the respective embodiments, modification of arbitrary components of the respective embodiments, or omission of arbitrary components of the respective embodiments are possible.
　この発明に係る電力変換装置は、ＰＷＭ信号パターンの容易な操作によって母線電流検出時間を確保できるようになり、安価な低機能マイコンを使用することが可能となるので、例えば車両に搭載されているアクチュエータを駆動する電動機などに用いるのに適している。 The power conversion device according to the present invention can secure a bus current detection time by an easy operation of a PWM signal pattern, and can use an inexpensive low-function microcomputer. It is suitable for use in an electric motor that drives an actuator.
　１　電力変換装置、２　インバータ回路、３　電流検出素子、４　相電流再現部、５　デューティ生成部、６　判定部、７　ＰＷＭ信号生成部、１０　電動機、１１　ロータ角度センサ、１００　処理回路、１０１　プロセッサ、１０２　メモリ。 1 power converter, 2 inverter circuit, 3 current detection element, 4 phase current reproduction unit, 5 duty generation unit, 6 determination unit, 7 PWM signal generation unit, 10 motor, 11 rotor angle sensor, 100 processing circuit, 101 processor, 102 Memory.

Claims (17)

  1. 　複数のスイッチング素子が３相のＰＷＭ信号パターンに従いオンオフすることで、直流を３相交流に変換するインバータ回路と、
    　前記インバータ回路の直流側に接続され、電流に対応する信号を発生する電流検出素子と、
    　前記電流検出素子に発生した信号と前記３相のＰＷＭ信号パターンとに基づいて前記インバータ回路の相電流を再現する相電流再現部と、
    　前記相電流再現部により再現された相電流に基づいて前記３相のＰＷＭ信号パターンのデューティ比を生成するデューティ生成部と、
    　前記デューティ生成部により生成された前記３相のＰＷＭ信号パターンのデューティ比の大小関係を判定し、デューティ比が最大となる最大相、最小となる最小相および中間となる中間相に分類する判定部と、
    　前記デューティ生成部により生成されたデューティ比に基づいて前記３相のＰＷＭ信号パターンを生成する際、前記中間相のＰＷＭ信号パターンの周期を、前記最大相または前記最小相のＰＷＭ信号パターンの周期の２倍以上にするＰＷＭ信号生成部とを備える電力変換装置。     An inverter circuit that converts direct current into three-phase alternating current by turning on and off a plurality of switching elements according to a three-phase PWM signal pattern;
    A current detecting element connected to the DC side of the inverter circuit and generating a signal corresponding to the current;
    A phase current reproduction unit that reproduces the phase current of the inverter circuit based on the signal generated in the current detection element and the three-phase PWM signal pattern;
    A duty generation unit configured to generate a duty ratio of the three-phase PWM signal pattern based on the phase current reproduced by the phase current reproduction unit;
    A determination unit that determines the magnitude relationship between the duty ratios of the three-phase PWM signal patterns generated by the duty generation unit, and classifies the maximum phase, the minimum phase that is the minimum, and the intermediate phase that is the minimum When,
    When generating the three-phase PWM signal pattern based on the duty ratio generated by the duty generation unit, the period of the intermediate phase PWM signal pattern is set to the period of the maximum phase or the minimum phase PWM signal pattern. A power conversion device comprising: a PWM signal generation unit that doubles or more.
  2. 　前記ＰＷＭ信号生成部は、
    　前記中間相のＰＷＭ信号パターンのデューティ比が予め定められた上限値未満または下限値以上である場合、前記中間相のＰＷＭ信号パターンの周期を、前記最大相または前記最小相のＰＷＭ信号パターンの周期の２倍にし、
    　前記中間相のＰＷＭ信号パターンのデューティ比が予め定められた上限値以上または下限値未満である場合、前記中間相のＰＷＭ信号パターンの周期を、前記最大相または前記最小相のＰＷＭ信号パターンの周期の３倍以上にすることを特徴とする請求項１記載の電力変換装置。     The PWM signal generator is
    When the duty ratio of the intermediate phase PWM signal pattern is less than a predetermined upper limit value or more than a lower limit value, the cycle of the intermediate phase PWM signal pattern is set to the cycle of the maximum phase or the minimum phase PWM signal pattern. 2 times,
    When the duty ratio of the intermediate phase PWM signal pattern is equal to or higher than a predetermined upper limit value or less than the lower limit value, the cycle of the intermediate phase PWM signal pattern is set to the cycle of the maximum phase or the minimum phase PWM signal pattern. The power conversion device according to claim 1, wherein the power conversion device is set to be three times or more.
  3. 　前記ＰＷＭ信号生成部は、
    　前記最大相および前記最小相について、ＰＷＭ信号パターンの高電圧区間と低電圧区間のうち、継続時間が短い方の区間を周期の先頭に配置し、
    　前記中間相について、ＰＷＭ信号パターンの高電圧区間と低電圧区間のうち、継続時間が長い方の区間を周期の先頭に配置することを特徴とする請求項１記載の電力変換装置。     The PWM signal generator is
    For the maximum phase and the minimum phase, between the high voltage section and the low voltage section of the PWM signal pattern, the section with the shorter duration is placed at the beginning of the cycle,
    2. The power conversion device according to claim 1, wherein, for the intermediate phase, a section having a longer duration among a high voltage section and a low voltage section of the PWM signal pattern is arranged at the head of the cycle.
  4. 　前記ＰＷＭ信号生成部は、前記最大相のデューティ比と前記最小相のデューティ比の合計値の半分の値を基準値とし、前記中間相のデューティ比が前記基準値をまたぐときに、前記中間相のＰＷＭ信号パターンの位相を１８０度移動させることによって高電圧区間と低電圧区間の順番を逆にすることを特徴とする請求項３記載の電力変換装置。 The PWM signal generation unit uses a value that is half the total value of the duty ratio of the maximum phase and the duty ratio of the minimum phase as a reference value, and when the duty ratio of the intermediate phase crosses the reference value, the intermediate phase The power converter according to claim 3, wherein the order of the high voltage section and the low voltage section is reversed by shifting the phase of the PWM signal pattern by 180 degrees.
  5. 　前記ＰＷＭ信号生成部は、デューティ比が最大となる相と中間となる相との入れ替わり、または最小となる相と中間となる相との入れ替わりが発生した場合、入れ替わり後の中間相のＰＷＭ信号パターンの位相を変更することを特徴とする請求項３記載の電力変換装置。 The PWM signal generation unit generates a PWM signal pattern of the intermediate phase after the switching when the switching between the phase having the maximum duty ratio and the intermediate phase, or the switching between the minimum phase and the intermediate phase occurs. The power converter according to claim 3, wherein the phase of the power converter is changed.
  6. 　前記ＰＷＭ信号生成部は、デューティ比が最大となる相と中間となる相との入れ替わり、または最小となる相と中間となる相との入れ替わりが発生した場合、入れ替わり時に中間相のＰＷＭ信号パターンの高電圧区間と低電圧区間を切り替えることを特徴とする請求項５記載の電力変換装置。 When the PWM signal generation unit switches between the phase having the maximum duty ratio and the intermediate phase, or when switching between the minimum phase and the intermediate phase occurs, the PWM signal pattern of the intermediate phase at the time of replacement is generated. The power converter according to claim 5, wherein the high voltage section and the low voltage section are switched.
  7. 　前記ＰＷＭ信号生成部は、前記最大相または前記最小相のいずれか一方のＰＷＭ信号パターンを反転して、前記最大相または前記最小相のいずれか他方のＰＷＭ信号パターンとすることを特徴とする請求項３記載の電力変換装置。 The PWM signal generation unit inverts the PWM signal pattern of either the maximum phase or the minimum phase to obtain the PWM signal pattern of the other of the maximum phase or the minimum phase. Item 4. The power conversion device according to Item 3.
  8. 　前記相電流再現部は、２周期以上連続して１相の相電流しか再現できなかった場合、再現できた１相の相電流値をＡ、再現できなかった２相の相電流値をＢ，Ｃとした式Ｂ＋Ｃ＝－ＡによりＢとＣの相電流値を推定し、さらにＢとＣの相電流値を－Ａ／２に漸近するように変化させることを特徴とする請求項１記載の電力変換装置。 When only one phase current can be reproduced continuously for two or more cycles, the phase current reproduction unit represents a phase current value of one phase that can be reproduced as A, a phase current value of two phases that could not be reproduced as B, 2. The phase current value of B and C is estimated by an expression B + C = −A where C is set, and the phase current value of B and C is further changed to be asymptotic to −A / 2. Power conversion device.
  9. 　前記ＰＷＭ信号生成部は、前記最大相のＰＷＭ信号パターンを高電圧側に固定する、または前記最小相のＰＷＭ信号パターンを低電圧側に固定することを特徴とする請求項１記載の電力変換装置。 2. The power converter according to claim 1, wherein the PWM signal generation unit fixes the PWM signal pattern of the maximum phase on a high voltage side or fixes the PWM signal pattern of the minimum phase on a low voltage side. .
  10. 　前記ＰＷＭ信号生成部は、前記最大相のＰＷＭ信号パターンを高電圧側に固定する周期と、前記最小相のＰＷＭ信号パターンを低電圧側に固定する周期とを繰り返すことを特徴とする請求項９記載の電力変換装置。 10. The PWM signal generation unit repeats a cycle of fixing the maximum phase PWM signal pattern to a high voltage side and a cycle of fixing the minimum phase PWM signal pattern to a low voltage side. The power converter described.
  11. 　前記ＰＷＭ信号生成部は、のこぎり波キャリアを用いてＰＷＭ信号パターンを生成する場合はキャリア周期が終了する時点、または三角波キャリアを用いてＰＷＭ信号パターンを生成する場合は当該三角波キャリアの値の変化方向が反転する時点において、前記最大相のＰＷＭ信号パターンを予め定められた時間だけ低電圧区間にし、当該時点直後の周期における前記中間相および前記最小相のＰＷＭ信号パターンの低電圧区間を前記予め定められた時間だけ延長することを特徴とする請求項９記載の電力変換装置。 When the PWM signal pattern is generated using a sawtooth wave carrier, the PWM signal generation unit ends the carrier cycle, or when the PWM signal pattern is generated using a triangular wave carrier, the change direction of the value of the triangular wave carrier At the time of inversion, the maximum phase PWM signal pattern is set to a low voltage section for a predetermined time, and the low voltage sections of the intermediate phase and the minimum phase PWM signal pattern in the period immediately after the time are set in advance. The power conversion device according to claim 9, wherein the power conversion device extends for a predetermined time.
  12. 　前記ＰＷＭ信号生成部は、のこぎり波キャリアを用いてＰＷＭ信号パターンを生成する場合はキャリア周期が終了する時点、または三角波キャリアを用いてＰＷＭ信号パターンを生成する場合は当該三角波キャリアの値の変化方向が反転する時点において、前記最小相のＰＷＭ信号パターンを予め定められた時間だけ高電圧区間にし、当該時点直後の周期における前記最大相および前記中間相のＰＷＭ信号パターンの高電圧区間を前記予め定められた時間だけ延長することを特徴とする請求項９記載の電力変換装置。 When the PWM signal pattern is generated using a sawtooth wave carrier, the PWM signal generation unit ends the carrier cycle, or when the PWM signal pattern is generated using a triangular wave carrier, the change direction of the value of the triangular wave carrier At the time of inversion, the PWM signal pattern of the minimum phase is set to a high voltage section for a predetermined time, and the high voltage section of the PWM signal pattern of the maximum phase and the intermediate phase in the period immediately after the time is set in advance. The power conversion device according to claim 9, wherein the power conversion device extends for a predetermined time.
  13. 　前記ＰＷＭ信号生成部は、前記最大相のデューティ比と前記最小相のデューティ比の合計値の半分の値を基準値とし、前記中間相のデューティ比が前記基準値以上の場合、前記中間相のＰＷＭ信号パターンの高電圧区間の開始位置を、前記インバータ回路の出力電圧がゼロになるゼロ電圧ベクトルを除いた期間のうちの前記最大相のＰＷＭ信号パターンが高電圧区間かつ前記最小相のＰＷＭ信号パターンが低電圧区間になる時点までずらし、開始位置をずらした分だけ終了位置もずらすことを特徴とする請求項９記載の電力変換装置。 The PWM signal generation unit uses a value that is half the total value of the duty ratio of the maximum phase and the duty ratio of the minimum phase as a reference value, and when the duty ratio of the intermediate phase is equal to or greater than the reference value, The maximum phase PWM signal pattern of the start position of the high voltage interval of the PWM signal pattern except the zero voltage vector in which the output voltage of the inverter circuit becomes zero is the high voltage interval and the minimum phase PWM signal. The power conversion device according to claim 9, wherein the pattern is shifted to a time when the pattern becomes a low voltage section, and the end position is also shifted by the amount by which the start position is shifted.
  14. 　前記ＰＷＭ信号生成部は、前記最大相のデューティ比と前記最小相のデューティ比の合計値の半分の値を基準値とし、前記中間相のデューティ比が前記基準値未満の場合、前記中間相のＰＷＭ信号パターンの低電圧区間の開始位置を、前記インバータ回路の出力電圧がゼロになるゼロ電圧ベクトルを除いた期間のうちの前記最大相のＰＷＭ信号パターンが高電圧区間かつ前記最小相のＰＷＭ信号パターンが低電圧区間になる時点までずらし、開始位置をずらした分だけ終了位置もずらすことを特徴とする請求項９記載の電力変換装置。 The PWM signal generation unit uses a value that is half of the total value of the duty ratio of the maximum phase and the duty ratio of the minimum phase as a reference value, and when the duty ratio of the intermediate phase is less than the reference value, The PWM signal pattern of the maximum phase in the period excluding the zero voltage vector where the output voltage of the inverter circuit becomes zero is the start position of the low voltage section of the PWM signal pattern is the high voltage section and the PWM signal of the minimum phase The power conversion device according to claim 9, wherein the pattern is shifted to a time when the pattern becomes a low voltage section, and the end position is also shifted by the amount by which the start position is shifted.
  15. 　前記ＰＷＭ信号生成部は、前記中間相のＰＷＭ信号パターンの高電圧区間の開始位置を、前記ゼロ電圧ベクトルを除いた期間のうちの前記最大相のＰＷＭ信号パターンが高電圧区間かつ前記最小相のＰＷＭ信号パターンが低電圧区間になる前記時点よりも進角側にずらすことを特徴とする請求項１３記載の電力変換装置。 The PWM signal generation unit determines the start position of the high voltage interval of the intermediate phase PWM signal pattern, and the maximum phase PWM signal pattern of the period excluding the zero voltage vector is the high voltage interval and the minimum phase. The power conversion device according to claim 13, wherein the PWM signal pattern is shifted to an advance side from the time point when the PWM signal pattern is in a low voltage section.
  16. 　前記ＰＷＭ信号生成部は、前記中間相のＰＷＭ信号パターンの低電圧区間の開始位置を、前記ゼロ電圧ベクトルを除いた期間のうちの前記最大相のＰＷＭ信号パターンが高電圧区間かつ前記最小相のＰＷＭ信号パターンが低電圧区間になる前記時点よりも進角側にずらすことを特徴とする請求項１４記載の電力変換装置。 The PWM signal generation unit determines the start position of the low-voltage section of the intermediate-phase PWM signal pattern, and the maximum-phase PWM signal pattern of the period excluding the zero voltage vector is the high-voltage section and the minimum-phase section. The power conversion device according to claim 14, wherein the PWM signal pattern is shifted to an advance side from the time point when the PWM signal pattern is in a low voltage section.
  17. 　複数のスイッチング素子が３相のＰＷＭ信号パターンに従いオンオフすることで、直流を３相交流に変換するインバータ回路と、前記インバータ回路の直流側に接続され、電流に対応する信号を発生する電流検出素子とを備える電力変換装置の制御方法であって、
    　相電流再現部が、前記電流検出素子に発生した信号と前記３相のＰＷＭ信号パターンとに基づいて前記インバータ回路の相電流を再現するステップと、
    　デューティ生成部が、前記相電流再現部により再現された相電流に基づいて前記３相のＰＷＭ信号パターンのデューティ比を生成するステップと、
    　判定部が、前記デューティ生成部により生成された前記３相のＰＷＭ信号パターンのデューティ比の大小関係を判定し、デューティ比が最大となる最大相、最小となる最小相および中間となる中間相に分類するステップと、
    　ＰＷＭ信号生成部が、前記デューティ生成部により生成されたデューティ比に基づいて前記３相のＰＷＭ信号パターンを生成する際、前記中間相のＰＷＭ信号パターンの周期を、前記最大相または前記最小相のＰＷＭ信号パターンの周期の２倍以上にするステップとを備える電力変換装置の制御方法。     An inverter circuit that converts direct current into three-phase alternating current by turning on and off a plurality of switching elements according to a three-phase PWM signal pattern, and a current detection element that is connected to the direct current side of the inverter circuit and generates a signal corresponding to current A method for controlling a power conversion device comprising:
    A step of reproducing a phase current of the inverter circuit based on a signal generated in the current detection element and the three-phase PWM signal pattern;
    A step of generating a duty ratio of the three-phase PWM signal pattern based on the phase current reproduced by the phase current reproduction unit;
    The determination unit determines the magnitude relationship between the duty ratios of the three-phase PWM signal patterns generated by the duty generation unit, and determines the maximum phase with the maximum duty ratio, the minimum phase with the minimum, and the intermediate phase with the middle. A step of classification;
    When the PWM signal generation unit generates the three-phase PWM signal pattern based on the duty ratio generated by the duty generation unit, the period of the intermediate phase PWM signal pattern is set to the maximum phase or the minimum phase. A method for controlling the power converter, comprising a step of setting the period of the PWM signal pattern to twice or more.
PCT/JP2016/061896 2016-04-13 2016-04-13 Power conversion device and method for controlling same WO2017179150A1 (en)

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