WO2017174608A1 - Semiconductor chip with moisture protection layer - Google Patents

Semiconductor chip with moisture protection layer Download PDF

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Publication number
WO2017174608A1
WO2017174608A1 PCT/EP2017/058033 EP2017058033W WO2017174608A1 WO 2017174608 A1 WO2017174608 A1 WO 2017174608A1 EP 2017058033 W EP2017058033 W EP 2017058033W WO 2017174608 A1 WO2017174608 A1 WO 2017174608A1
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WO
WIPO (PCT)
Prior art keywords
layer
semiconductor
semiconductor chip
protection layer
metallization
Prior art date
Application number
PCT/EP2017/058033
Other languages
French (fr)
Inventor
Charalampos PAPADOPOULOS
David GUILLON
Original Assignee
Abb Schweiz Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Abb Schweiz Ag filed Critical Abb Schweiz Ag
Publication of WO2017174608A1 publication Critical patent/WO2017174608A1/en

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    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1027—IV
    • H01L2924/10272—Silicon Carbide [SiC]
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]

Definitions

  • the invention relates to a method for manufacturing semiconductor chips, to a semiconductor chip and to a semiconductor module.
  • a high electric field in the passivation materials may cause a degradation of the materials, because it may cause a chemical reaction of the materials with the moisture.
  • sparking events may happen due to a field distribution change.
  • a passivation layer may comprise a polyimide covering a layer of SiN.
  • the SiN may react with moisture, which is soaked into the polyimide, and is getting oxidized. This may create a less dense SiN layer with porous structure, which then has a degraded capability of filtering the electric field towards the gel, which covers the polyimide, and may cause cracks.
  • the passivation layer with polyimide covers a layer of aluminum, but has cracks, humidity may penetrate towards the aluminum.
  • the electric field may cause the aluminum to corrode to an aluminum oxide, which is growing in mass and may cause further, larger cracks.
  • the termination when the polyimide covers a termination layer at a border of the semiconductor chip, which is responsible for blocking currents outside the effective area, the termination may be damaged and due to the defects, a leakage current may rise.
  • the leakage current also may locally create heat, which may cause that the adhesion of the polyimide on the termination layer is not given anymore and parts of the termination layer may be shorted with moisture ions, getting into the gap between the polyimide and the termination layer. In summary, this results in a degraded blocking capability of the termination layer.
  • DE 10 2009 001 028 B4 shows a method, in which a protection layer is destroyed for bonding a bond wire to a semiconductor body.
  • DE 10 2007 035 608 Al and DE 10 2009 033 594 Al show a semiconductor module with a protection layer that is deposited onto the module after the connection of bond wires.
  • US 5 854 141 A relates to an inorganic seal for a chip.
  • a passivation layer is shown, which includes a metallization ring.
  • the passivation layer is covered with a layer of an inorganic insulator, a layer of organic polyimide and a layer of inorganic material. This structure is used for delamination protection.
  • US 5 284 801 A relates to a method of moisture protection in a semiconductor device with a chip, a metallization, a passivation layer and a protection layer, which is moisture resistant.
  • US 2014/110838 Al shows a metallization structure, which is protected by a layer that may be made by atomic layer deposition and of aluminum oxide. It is mentioned that wire bonding may be done by breaking through the layer.
  • US 2010/314 629 Al shows a semiconductor device with a termination end-portion with an inorganic protection film.
  • a semiconductor chip may comprise a semiconductor substrate (such as Si. SiC or GaN), in which one or more semiconductor elements are provided (such as diodes, transistors, thyristors, IGBTs, etc.).
  • a semiconductor chip also may comprise conducting and nonconducting layers on the semiconductor substrate, such as electrodes, protection and/or isolation layers.
  • the semiconductor chips may be power semiconductor chips adapted for processing voltages of more than 100 V and/or current of more than 10 A.
  • the method comprises: providing a wafer for a plurality of semiconductor chips, the wafer comprising for each semiconductor chip: a semiconductor substrate comprising a semiconductor element, which semiconductor substrate is covered by a metallization layer providing an electrode area of the semiconductor chip, comprising a termination layer on the semiconductor substrate at a border of the semiconductor chip and comprises an electrically non-conducting passivation layer at least partially covering the termination layer and partially covering the semiconductor substrate and/or the metallization layer.
  • the wafer (which usually has a disc-shaped body) may be manufactured in many steps, in which the semiconductor elements are doped into the semiconductor substrate and the metallization layer and passivation layer are coated onto the semiconductor substrate. It has to be noted that covering may mean that the one layer is directly provided above the other layer or the substrate or that other layers are provided in between.
  • the one or more metallization layer may provide electrodes for electrically connecting external conductors to the semiconductor element.
  • the passivation layer may be electrically non-conducting and/or may comprise one or more layers of dielectric and/or electrically non- conducting material, for example a plastics layer.
  • the method comprises: depositing a protection layer by at least one of atomic layer deposition and laser deposition above the passivation layer and the metallization layer of the semiconductor chips; and, after the depositing of the protection layer, sawing the wafer into the semiconductor chips.
  • the protection layer may be provided directly over the passivation layer and/or the metallization layer.
  • the protection layer may be a rather thin layer (thinner than the passivation layer) and/or may be made of a material, which has a lower permeability with respect to moisture than the passivation layer.
  • Moisture may be or may comprise water that may condense from air surrounding the semiconductor chip and/or that may penetrate into the passivation layer.
  • the passivation layer may be prevented from acquiring moisture and/or the degrading processes described above may be prevented.
  • chemical reactions based on the moisture and/or a lowered electrical resistivity of the passivation layer based on moisture may be reduced.
  • the protection layer may act as a moisture barrier and thus may result in a hermetically sealed semiconductor chip, which may have a long reliability and shows nearly no higher degrading in the presence of moisture.
  • the performance of the semiconductor chip and/or a semiconductor chip, in which the semiconductor chip is arranged, may have a high performance in terms of reliability in humidity, especially with respect to high voltages and high electric fields.
  • the protection layer may be deposited nearly above the whole surface of the wafer for sealing critical regions. Since the wafer is sawn into separate semiconductor chips, only one deposition process may have to be performed for a plurality of chips, which may help to save manufacturing time.
  • the protection layer is made from a metal compound.
  • metal compounds for example based on Al, Zr, Hf, and/or Ti have to be shown that they have a low permeability with respect to moisture.
  • These metal compounds may be metal oxides, such as A1203, ZrO, Hf02 and/or Ti02. However, also other compounds such as TiN may be used.
  • the protection layer is atomic layer deposited or the protection layer is laser deposited. Both deposition methods may be suitable for generating thin layers of the above mentioned materials.
  • the metal mentioned above may be provided as a hot gas, and the wafer may be exposed alternating to this gas and other gaseous compounds.
  • the metal and other compounds for the protection layer may be heated together with a side of the wafer by a laser, which results in the deposition of the protection layer on the heated side.
  • the protection layer has a thickness of less than 1000 nm, for example less than 500 nm or less than 300 nm.
  • the protection layer may have a thickness of about 100 nm.
  • Such thin layers may be generated with the above mentioned deposition processes.
  • the passivation layer comprises an organic material.
  • the passivation layer may be a layer above a termination layer for protecting a border of the semiconductor chip from leakage currents.
  • the passivation layer also may be a layer above a gate runner (a metallization layer interconnected with a gate electrode), which protects the gate runner.
  • the passivation layer also may comprise one or more layers of different material.
  • one of the layers may be an SiN layer and/or one layer may be a plastics layer.
  • An organic material may be a plastics material based on C (carbon).
  • the passivation layer may comprise a layer of a polymer material, such as polyimide.
  • the protection layer may seal layers of inorganic material (such as the metallization layer) but also layers of organic materials (such as a polyimide layer).
  • both sides (and for example the complete surface) of the wafer are deposited with the protection layer.
  • the deposition process may be very unspecific about the area, in which the material is deposited.
  • the wafer comprises for each semiconductor chip a first metallization layer on a first side and a second metallization layer on a second, opposite side.
  • the first metallization layer may provide a source (or collector) electrode and the second metallization layer may provide a drain (or emitter) electrode.
  • the semiconductor chip later may be attached to a metallization layer of a semiconductor module.
  • the method further comprises: after depositing the protection layer and before sawing, attaching the wafer to an adhesive tape, the tape having an adhesive surface with a higher adhesion to the protection layer as the protection layer to the second metallization layer on the semiconductor chip; and, after sawing, picking a semiconductor chip from the tape, such that the protection layer remains on the adhesive tape.
  • the wafer is attached to a tape, which is later used for handling the chips.
  • This tape may be used for removing an unwanted part of the protection layer from the second metallization layer.
  • the material of the protection layer, the metallization layer and the adhesive of the tape may be chosen in such a way, that the protection layer remains on the tape, when the semiconductor chip is diced. No etching is needed to remove the surplus parts of the protection layer.
  • the protection layer is made from A1203 and the second metallization layer is made from Ag. These materials have a rather low adhesion with each other, such that ordinary adhesive tapes may be used for removing the protection layer from the second metallization layer.
  • the method further comprises: before depositing the protection layer (and before sawing), attaching the wafer to an adhesive tape, protecting a second side of the semiconductor chip to be coated with the protection layer. It also may be possible to use the tape to prevent a deposition of the backside of the waver, i.e. the second metallization layer. However, in this case, the tape may have to be adapted to withstand the conditions near a deposition process.
  • the method further comprises: ultrasonic welding a bond wire to the metallization layer, such that during the welding, the part of the protection layer between the bond wire and the metallization layer is removed and the bond wire is bonded to the metallization layer.
  • an end of the bond wire is vibrated and pressed against the semiconductor chip.
  • the vibrations in combination with the pressing force may cause the protection layer beneath the end of the bond wire to be mechanically destroyed.
  • No etching process is needed before attaching a bond wire to the (first) metallization layer.
  • the bonding may be performed through the deposited protection layer. Furthermore, only under the end of the bond wire the protection layer is removed, the remaining parts of the protection layer may remain intact.
  • a further aspect of the invention relates to a semiconductor chip.
  • This semiconductor chip may have been manufactured by the method as described in the above and in the following.
  • the semiconductor chip comprises: a semiconductor substrate comprising a semiconductor element; a metallization layer on the semiconductor substrate, the metallization layer providing an electrode area of the semiconductor chip; an electrically non-conducting passivation layer, partially covering the semiconductor substrate and/or the metallization layer; a termination layer on the semiconductor substrate at a border of the semiconductor chip, wherein the passivation layer is at least partially covering the termination layer; and a protection layer deposited above the passivation layer and the metallization layer, which protection layer may have a lesser permeability with respect to moisture compared to the passivation layer.
  • the protection layer may have been deposited by at least one of atomic layer deposition and laser deposition before the semiconductor chip has been sawen from a wafer.
  • the order of the sawing step and the deposition step may be recognized at an edge of the semiconductor chip.
  • the protection layer may have a sharp rim, may show traces of the sawing tool and/or may have the same thickness at the border as remote from the border.
  • the protection layer may reach around the edge of the semiconductor chip, the protection layer may have a rounded rim, the protection layer may become thinner at the border of the semiconductor chip. Furthermore, no traces of a sawing tool may be present and the protection may be extreme flat (as everywhere, where its surface has been formed by deposition).
  • the metallization layer provides an electrode layer of the semiconductor chip.
  • the metallization layer may provide an electrode for electrically connecting the semiconductor elements with conductors, such as bond wires.
  • the semiconductor chip comprises a first metallization layer on a first side of the semiconductor substrate, wherein the passivation layer and the protection layer are arranged on the first side; and a second metallization layer on a second, opposite side of the semiconductor substrate.
  • the protection layer may have been deposited on both sides but may have been removed from the second side. In this case it may be possible that rests of the protection layer may be found on the second side.
  • the protection layer is made of A1203 and the second metallization layer is made of an Ag, the protection layer on the second side may have been removed with an adhesive tape.
  • the semiconductor chip comprises a termination layer on the semiconductor substrate at a border of the semiconductor chip, wherein the passivation layer is at least partially covering the termination layer.
  • Many power semiconductor chips comprise a termination for preventing a leakage current through the border of the semiconductor chip.
  • This termination may comprise a passivation layer (for example with polyimide) that may be protected with the protection layer.
  • the protection layer may seal the termination from moisture or contamination.
  • a further aspect of the invention relates to a semiconductor substrate and/or module.
  • a semiconductor module may be a device comprising one or more semiconductor chips (for example, as described in the above and in the following), which are mechanically supported and electrically connected with further components of the semiconductor module.
  • the semiconductor module comprises: a base substrate with a metallization layer; a semiconductor chip as described in the above and in the following attached to the base substrate (for example bonded to the metallization layer of the base substrate); and at least one bond wire bonded to the metallization layer of the base substrate.
  • the bond wire is bonded to the metallization layer of the semiconductor chip through the protection layer by ultrasonic welding.
  • Fig. 1 schematically shows a wafer at the beginning of a method for manufacturing semiconductor chips according to an embodiment of the invention.
  • Fig. 2 schematically shows a wafer after a method step of a method for manufacturing semiconductor chips according to an embodiment of the invention.
  • Fig. 3 schematically shows a wafer after a further method step of a method for manufacturing semiconductor chips according to an embodiment of the invention.
  • Fig. 4 schematically shows a wafer after a further method step of a method for manufacturing semiconductor chips according to an embodiment of the invention.
  • Fig. 5 schematically shows a wafer after a further method step of a method for manufacturing semiconductor chips according to an embodiment of the invention.
  • Fig. 6 shows a semiconductor module with a semiconductor chip according to an embodiment of the invention.
  • Fig. 1 shows a wafer 10, which is based on a semiconductor substrate 12 such as Si or SiC. Later, the wafer 10 will be cut into separate semiconductor chips.
  • the semiconductor substrate 12 comprises a semiconductor element 14, which, for example, has been formed by doping the semiconductor substrate 12 in a plurality of steps.
  • the semiconductor substrate 12 is covered by a topside first metallization layer 16 providing a first electrode area of the semiconductor chip and by a bottom side, second metallization layer 18 providing a second electrode area of the semiconductor chip (when the chip has been cut from the wafer 10).
  • the metallization layers 16, 18 may be made of Cu, Ag, Al, etc.
  • the wafer 10 (and each chip) comprises one or more electrically non- conducting passivation layers 20 partially covering the semiconductor substrate 12 and/or a metallization layer 16 (there may be further metallization layers, such as a gate runner).
  • the passivation layer 20 partially covers a termination layer 22, which is arranged at a (later) border of the semiconductor chip.
  • the termination layer 22 may be provided for blocking leakage currents at the border of the chip.
  • the passivation layer 20 at least partially covers a gate runner, which may be provided as a part of a metallization layer 16 on the topside of the wafer 10 (or later chip) and/or which may distribute a current from a gate area across the topside of the chip.
  • the non-conducting passivation layer 20 may comprise several layers, such as a layer of inorganic material such as SiN and/or a layer of organic material, such as polyimide 24.
  • Fig. 2 shows the wafer 10 after depositing a protection layer 26 all over the complete surface of the wafer 10. It also may be possible that only a part of the complete surface of the wafer 10, such that only the topside (and parts of the edges) are provided with the protection layer 26. For example, the deposition of the protection layer 26 may be performed after electrical testing of the semiconductor elements 14.
  • the protection layer 26 may be generated with atomic layer deposition (ALD) or laser depositions of materials adapted for at least partially blocking moisture and for withstanding the electrical conditions when the chip is operating (such as high dielectric strength, high dielectric constant with high density, etc.). As shown in Fig, 2, the protection layer may be adapted for sealing the termination layer 22 and the passivation layer 20 from moisture. Suitable materials for the protection layer 26 may be metal compounds, such as metal oxides. Examples for these materials are A1203, ZrO, Hf02, TiN, Ti02.
  • the whole wafer 10 may be coated and may be sealed on the topside and backside.
  • laser deposition only the topside may be coated, since with laser deposition, the direction of coating may be controlled.
  • Fig. 3 shows the wafer 10 after it has been attached to a tape 28. It may be possible that the wafer 10 is attached to the tape 28 before the deposition of the protection layer 28. In this case, the tape 28 may prevent the coating of the bottom side of the wafer 10.
  • Fig. 4 shows the wafer 10, after it has been sawn into separate chips 30. The chips 30 may be sawn after the protection layer 26 has been deposited. As shown in Fig. 4, the separation of the chips 30 from each other causes that the protection layer 26 (and the termination layer 22) may be cut with the sawing tool, resulting in sharp rims. At the sawing surfaces, the chips 30 are not covered by the protection layer 26.
  • Fig. 5 shows the semiconductor chips 30 on the tape 28 during dicing.
  • the tape 28 may be used to remove a part of the protection layer 26 from the chip 30, which is covering the bottom side and/or the metallization layer 18 of the chip 30.
  • the metallization layer 18 may be used for soldering the chip 30 to a further substrate and therefore may have to be clean enough for this process step.
  • the part of the protection layer 26 covering the metallization layer 18 may be removed from the chip 30 during the picking of the chip 30. This may be achieved, when the protection layer 26 has a worse adhesion to the metallization layer 18 as to the tape 28. Then, after dicing, the deposited material of the protection layer 26 on the bottom side of the chip 30 will stick on the tape 28 during picking. For example, this may be the case for a protection layer made of A1203 and a metallization layer 18 made of Ag.
  • Fig. 6 shows a semiconductor module 32 onto which a semiconductor chip 30, which was manufactured as shown in Fig. 1 to 5, is bonded.
  • the semiconductor module 32 comprises a substrate 34 with a metallization layer 36 to which the semiconductor chip 30 is bonded (for example soldered) and one or more bond wires 38 interconnecting the electrode area provided by the metallization layer 16 of the chip 30 with a (further part) of the metallization layer 36 of the semiconductor module 32.
  • the parts of the bond wires 38 bonded to the metallization layer 16 have been bonded by ultrasonic welding.
  • the part of the protection layer 26 between the part of the bond wire 38 and the metallization layer 16 has been removed by the vibrations present during ultrasonic welding. It is not needed to etch a window into the protection layer 26 to open the electrode area, since during the ultrasonic welding of the bond wire 38, the friction between both surfaces of the wire bond 38 and the protection layer 26 may disperse material from the protection layer 26.
  • the etching step may be skipped, although the chip 30 is hermetically sealed on the topside, except on the edges, where it has been sawn.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

A method for manufacturing semiconductor chips (30) comprises: providing a wafer (10) for a plurality of semiconductor chips (30), the wafer (10) comprising for each semiconductor chip (30): a semiconductor substrate (12) comprising a semiconductor element (14), which semiconductor substrate (12) is covered by a metallization layer (16) providing an electrode area of the semiconductor chip (30) and comprising an electrically non-conducting passivation layer (20) partially covering at least one of the semiconductor substrate (12) and the metallization layer (16); depositing a protection layer (26) above the passivation layer (20) and the metallization layer (16) of the semiconductor chips, wherein the protection layer has a lower permeability with respect to moisture than the passivation layer (20); and, after the depositing of the protection layer (26), sawing the wafer (10) into the semiconductor chips (30).

Description

Semiconductor chip with moisture protection layer
FIELD OF THE INVENTION
The invention relates to a method for manufacturing semiconductor chips, to a semiconductor chip and to a semiconductor module.
BACKGROUND OF THE INVENTION
The reliability of power electronic devices with respect to moisture is an important issue. High voltages in combination with moisture may accelerate a degradation of the passivation materials on the semiconductor chips employed in the power electronics device.
In particular, a high electric field in the passivation materials may cause a degradation of the materials, because it may cause a chemical reaction of the materials with the moisture. Furthermore, sparking events may happen due to a field distribution change.
For example, a passivation layer may comprise a polyimide covering a layer of SiN. The SiN may react with moisture, which is soaked into the polyimide, and is getting oxidized. This may create a less dense SiN layer with porous structure, which then has a degraded capability of filtering the electric field towards the gel, which covers the polyimide, and may cause cracks.
As a further example, if the passivation layer with polyimide covers a layer of aluminum, but has cracks, humidity may penetrate towards the aluminum. The electric field may cause the aluminum to corrode to an aluminum oxide, which is growing in mass and may cause further, larger cracks.
For example, when the polyimide covers a termination layer at a border of the semiconductor chip, which is responsible for blocking currents outside the effective area, the termination may be damaged and due to the defects, a leakage current may rise. The leakage current also may locally create heat, which may cause that the adhesion of the polyimide on the termination layer is not given anymore and parts of the termination layer may be shorted with moisture ions, getting into the gap between the polyimide and the termination layer. In summary, this results in a degraded blocking capability of the termination layer. DE 10 2009 001 028 B4 shows a method, in which a protection layer is destroyed for bonding a bond wire to a semiconductor body.
DE 10 2007 035 608 Al and DE 10 2009 033 594 Al show a semiconductor module with a protection layer that is deposited onto the module after the connection of bond wires.
US 5 854 141 A relates to an inorganic seal for a chip. A passivation layer is shown, which includes a metallization ring. The passivation layer is covered with a layer of an inorganic insulator, a layer of organic polyimide and a layer of inorganic material. This structure is used for delamination protection.
US 5 284 801 A relates to a method of moisture protection in a semiconductor device with a chip, a metallization, a passivation layer and a protection layer, which is moisture resistant.
US 2014/110838 Al shows a metallization structure, which is protected by a layer that may be made by atomic layer deposition and of aluminum oxide. It is mentioned that wire bonding may be done by breaking through the layer.
US 2010/314 629 Al shows a semiconductor device with a termination end-portion with an inorganic protection film.
DESCRIPTION OF THE INVENTION
It is an objective of the invention to protect semiconductor chips better from moisture. This objective is achieved by the subject-matter of the independent claims. Further exemplary embodiments are evident from the dependent claims and the following description.
An aspect of the invention relates to a method for manufacturing semiconductor chips. A semiconductor chip may comprise a semiconductor substrate (such as Si. SiC or GaN), in which one or more semiconductor elements are provided (such as diodes, transistors, thyristors, IGBTs, etc.). A semiconductor chip also may comprise conducting and nonconducting layers on the semiconductor substrate, such as electrodes, protection and/or isolation layers.
The semiconductor chips may be power semiconductor chips adapted for processing voltages of more than 100 V and/or current of more than 10 A.
According to an embodiment of the invention, the method comprises: providing a wafer for a plurality of semiconductor chips, the wafer comprising for each semiconductor chip: a semiconductor substrate comprising a semiconductor element, which semiconductor substrate is covered by a metallization layer providing an electrode area of the semiconductor chip, comprising a termination layer on the semiconductor substrate at a border of the semiconductor chip and comprises an electrically non-conducting passivation layer at least partially covering the termination layer and partially covering the semiconductor substrate and/or the metallization layer. The wafer (which usually has a disc-shaped body) may be manufactured in many steps, in which the semiconductor elements are doped into the semiconductor substrate and the metallization layer and passivation layer are coated onto the semiconductor substrate. It has to be noted that covering may mean that the one layer is directly provided above the other layer or the substrate or that other layers are provided in between.
The one or more metallization layer may provide electrodes for electrically connecting external conductors to the semiconductor element. The passivation layer may be electrically non-conducting and/or may comprise one or more layers of dielectric and/or electrically non- conducting material, for example a plastics layer.
According to an embodiment of the invention, the method comprises: depositing a protection layer by at least one of atomic layer deposition and laser deposition above the passivation layer and the metallization layer of the semiconductor chips; and, after the depositing of the protection layer, sawing the wafer into the semiconductor chips. The protection layer may be provided directly over the passivation layer and/or the metallization layer.
The protection layer may be a rather thin layer (thinner than the passivation layer) and/or may be made of a material, which has a lower permeability with respect to moisture than the passivation layer. Moisture may be or may comprise water that may condense from air surrounding the semiconductor chip and/or that may penetrate into the passivation layer.
In such a way, the passivation layer may be prevented from acquiring moisture and/or the degrading processes described above may be prevented. In particular, chemical reactions based on the moisture and/or a lowered electrical resistivity of the passivation layer based on moisture may be reduced.
The protection layer may act as a moisture barrier and thus may result in a hermetically sealed semiconductor chip, which may have a long reliability and shows nearly no higher degrading in the presence of moisture. The performance of the semiconductor chip and/or a semiconductor chip, in which the semiconductor chip is arranged, may have a high performance in terms of reliability in humidity, especially with respect to high voltages and high electric fields.
The protection layer may be deposited nearly above the whole surface of the wafer for sealing critical regions. Since the wafer is sawn into separate semiconductor chips, only one deposition process may have to be performed for a plurality of chips, which may help to save manufacturing time.
According to an embodiment of the invention, the protection layer is made from a metal compound. In particular, specific metal compounds, for example based on Al, Zr, Hf, and/or Ti have to be shown that they have a low permeability with respect to moisture. These metal compounds may be metal oxides, such as A1203, ZrO, Hf02 and/or Ti02. However, also other compounds such as TiN may be used.
According to an embodiment of the invention, the protection layer is atomic layer deposited or the protection layer is laser deposited. Both deposition methods may be suitable for generating thin layers of the above mentioned materials. In atomic layer deposition, the metal mentioned above may be provided as a hot gas, and the wafer may be exposed alternating to this gas and other gaseous compounds. In laser deposition, the metal and other compounds for the protection layer may be heated together with a side of the wafer by a laser, which results in the deposition of the protection layer on the heated side.
According to an embodiment of the invention, the protection layer has a thickness of less than 1000 nm, for example less than 500 nm or less than 300 nm. For example, the protection layer may have a thickness of about 100 nm. Such thin layers may be generated with the above mentioned deposition processes.
According to an embodiment of the invention, the passivation layer comprises an organic material. For example, the passivation layer may be a layer above a termination layer for protecting a border of the semiconductor chip from leakage currents. The passivation layer also may be a layer above a gate runner (a metallization layer interconnected with a gate electrode), which protects the gate runner.
The passivation layer also may comprise one or more layers of different material. For example, one of the layers may be an SiN layer and/or one layer may be a plastics layer. An organic material may be a plastics material based on C (carbon).
For example, the passivation layer may comprise a layer of a polymer material, such as polyimide. In particular, the protection layer may seal layers of inorganic material (such as the metallization layer) but also layers of organic materials (such as a polyimide layer).
According to an embodiment of the invention, both sides (and for example the complete surface) of the wafer are deposited with the protection layer. The deposition process may be very unspecific about the area, in which the material is deposited.
According to an embodiment of the invention, the wafer comprises for each semiconductor chip a first metallization layer on a first side and a second metallization layer on a second, opposite side. The first metallization layer, for example, may provide a source (or collector) electrode and the second metallization layer may provide a drain (or emitter) electrode. With the second metallization layer, the semiconductor chip later may be attached to a metallization layer of a semiconductor module.
According to an embodiment of the invention, the method further comprises: after depositing the protection layer and before sawing, attaching the wafer to an adhesive tape, the tape having an adhesive surface with a higher adhesion to the protection layer as the protection layer to the second metallization layer on the semiconductor chip; and, after sawing, picking a semiconductor chip from the tape, such that the protection layer remains on the adhesive tape.
Usually, before the semiconductor chips are separated, the wafer is attached to a tape, which is later used for handling the chips. This tape may be used for removing an unwanted part of the protection layer from the second metallization layer. In this case, the material of the protection layer, the metallization layer and the adhesive of the tape may be chosen in such a way, that the protection layer remains on the tape, when the semiconductor chip is diced. No etching is needed to remove the surplus parts of the protection layer.
According to an embodiment of the invention, the protection layer is made from A1203 and the second metallization layer is made from Ag. These materials have a rather low adhesion with each other, such that ordinary adhesive tapes may be used for removing the protection layer from the second metallization layer.
According to an embodiment of the invention, the method further comprises: before depositing the protection layer (and before sawing), attaching the wafer to an adhesive tape, protecting a second side of the semiconductor chip to be coated with the protection layer. It also may be possible to use the tape to prevent a deposition of the backside of the waver, i.e. the second metallization layer. However, in this case, the tape may have to be adapted to withstand the conditions near a deposition process. According to an embodiment of the invention, the method further comprises: ultrasonic welding a bond wire to the metallization layer, such that during the welding, the part of the protection layer between the bond wire and the metallization layer is removed and the bond wire is bonded to the metallization layer. In ultrasonic welding, an end of the bond wire is vibrated and pressed against the semiconductor chip. The vibrations in combination with the pressing force may cause the protection layer beneath the end of the bond wire to be mechanically destroyed. No etching process is needed before attaching a bond wire to the (first) metallization layer. The bonding may be performed through the deposited protection layer. Furthermore, only under the end of the bond wire the protection layer is removed, the remaining parts of the protection layer may remain intact.
Furthermore, a backend polyimide process on bond wires could be skipped, which is being used for Al reconstruction during cycling due to ceramic sealing. In that case the Aluminum is sealed from the environment and has no place to move.
A further aspect of the invention relates to a semiconductor chip. This semiconductor chip may have been manufactured by the method as described in the above and in the following.
According to an embodiment of the invention, the semiconductor chip comprises: a semiconductor substrate comprising a semiconductor element; a metallization layer on the semiconductor substrate, the metallization layer providing an electrode area of the semiconductor chip; an electrically non-conducting passivation layer, partially covering the semiconductor substrate and/or the metallization layer; a termination layer on the semiconductor substrate at a border of the semiconductor chip, wherein the passivation layer is at least partially covering the termination layer; and a protection layer deposited above the passivation layer and the metallization layer, which protection layer may have a lesser permeability with respect to moisture compared to the passivation layer.
Furthermore, the protection layer may have been deposited by at least one of atomic layer deposition and laser deposition before the semiconductor chip has been sawen from a wafer. The order of the sawing step and the deposition step may be recognized at an edge of the semiconductor chip. In the case of sawing after deposition, the protection layer may have a sharp rim, may show traces of the sawing tool and/or may have the same thickness at the border as remote from the border.
In the case, the deposition is after the sawing, the protection layer may reach around the edge of the semiconductor chip, the protection layer may have a rounded rim, the protection layer may become thinner at the border of the semiconductor chip. Furthermore, no traces of a sawing tool may be present and the protection may be extreme flat (as everywhere, where its surface has been formed by deposition).
According to an embodiment of the invention, the metallization layer provides an electrode layer of the semiconductor chip. As already mentioned, the metallization layer may provide an electrode for electrically connecting the semiconductor elements with conductors, such as bond wires.
According to an embodiment of the invention, the semiconductor chip comprises a first metallization layer on a first side of the semiconductor substrate, wherein the passivation layer and the protection layer are arranged on the first side; and a second metallization layer on a second, opposite side of the semiconductor substrate. For example, the protection layer may have been deposited on both sides but may have been removed from the second side. In this case it may be possible that rests of the protection layer may be found on the second side. When the protection layer is made of A1203 and the second metallization layer is made of an Ag, the protection layer on the second side may have been removed with an adhesive tape.
According to an embodiment of the invention, the semiconductor chip comprises a termination layer on the semiconductor substrate at a border of the semiconductor chip, wherein the passivation layer is at least partially covering the termination layer. Many power semiconductor chips comprise a termination for preventing a leakage current through the border of the semiconductor chip. This termination may comprise a passivation layer (for example with polyimide) that may be protected with the protection layer. The protection layer may seal the termination from moisture or contamination.
A further aspect of the invention relates to a semiconductor substrate and/or module. A semiconductor module may be a device comprising one or more semiconductor chips (for example, as described in the above and in the following), which are mechanically supported and electrically connected with further components of the semiconductor module.
According to an embodiment of the invention, the semiconductor module comprises: a base substrate with a metallization layer; a semiconductor chip as described in the above and in the following attached to the base substrate (for example bonded to the metallization layer of the base substrate); and at least one bond wire bonded to the metallization layer of the base substrate. The bond wire is bonded to the metallization layer of the semiconductor chip through the protection layer by ultrasonic welding. It has to be understood that features of the method as described in the above and in the following may be features of the semiconductor chip and/or the semiconductor substrate and /or module as described in the above and in the following, and vice versa.
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.
BRIEF DESCRIPTION OF THE DRAWINGS
The subject-matter of the invention will be explained in more detail in the following text with reference to exemplary embodiments which are illustrated in the attached drawings. Fig. 1 schematically shows a wafer at the beginning of a method for manufacturing semiconductor chips according to an embodiment of the invention.
Fig. 2 schematically shows a wafer after a method step of a method for manufacturing semiconductor chips according to an embodiment of the invention.
Fig. 3 schematically shows a wafer after a further method step of a method for manufacturing semiconductor chips according to an embodiment of the invention.
Fig. 4 schematically shows a wafer after a further method step of a method for manufacturing semiconductor chips according to an embodiment of the invention.
Fig. 5 schematically shows a wafer after a further method step of a method for manufacturing semiconductor chips according to an embodiment of the invention.
Fig. 6 shows a semiconductor module with a semiconductor chip according to an embodiment of the invention.
The reference symbols used in the drawings, and their meanings, are listed in summary form in the list of reference symbols. In principle, identical parts are provided with the same reference symbols in the figures.
DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS
Fig. 1 shows a wafer 10, which is based on a semiconductor substrate 12 such as Si or SiC. Later, the wafer 10 will be cut into separate semiconductor chips. For each chip, the semiconductor substrate 12 comprises a semiconductor element 14, which, for example, has been formed by doping the semiconductor substrate 12 in a plurality of steps. The semiconductor substrate 12 is covered by a topside first metallization layer 16 providing a first electrode area of the semiconductor chip and by a bottom side, second metallization layer 18 providing a second electrode area of the semiconductor chip (when the chip has been cut from the wafer 10).
The metallization layers 16, 18 may be made of Cu, Ag, Al, etc.
On the topside, the wafer 10 (and each chip) comprises one or more electrically non- conducting passivation layers 20 partially covering the semiconductor substrate 12 and/or a metallization layer 16 (there may be further metallization layers, such as a gate runner).
In Fig. 1, the passivation layer 20 partially covers a termination layer 22, which is arranged at a (later) border of the semiconductor chip. The termination layer 22 may be provided for blocking leakage currents at the border of the chip. It also may be possible that the passivation layer 20 at least partially covers a gate runner, which may be provided as a part of a metallization layer 16 on the topside of the wafer 10 (or later chip) and/or which may distribute a current from a gate area across the topside of the chip.
The non-conducting passivation layer 20 may comprise several layers, such as a layer of inorganic material such as SiN and/or a layer of organic material, such as polyimide 24. Fig. 2 shows the wafer 10 after depositing a protection layer 26 all over the complete surface of the wafer 10. It also may be possible that only a part of the complete surface of the wafer 10, such that only the topside (and parts of the edges) are provided with the protection layer 26. For example, the deposition of the protection layer 26 may be performed after electrical testing of the semiconductor elements 14.
The protection layer 26 may be generated with atomic layer deposition (ALD) or laser depositions of materials adapted for at least partially blocking moisture and for withstanding the electrical conditions when the chip is operating (such as high dielectric strength, high dielectric constant with high density, etc.). As shown in Fig, 2, the protection layer may be adapted for sealing the termination layer 22 and the passivation layer 20 from moisture. Suitable materials for the protection layer 26 may be metal compounds, such as metal oxides. Examples for these materials are A1203, ZrO, Hf02, TiN, Ti02.
With atomic laser deposition, the whole wafer 10 may be coated and may be sealed on the topside and backside. With laser deposition, only the topside may be coated, since with laser deposition, the direction of coating may be controlled.
Fig. 3 shows the wafer 10 after it has been attached to a tape 28. It may be possible that the wafer 10 is attached to the tape 28 before the deposition of the protection layer 28. In this case, the tape 28 may prevent the coating of the bottom side of the wafer 10. Fig. 4 shows the wafer 10, after it has been sawn into separate chips 30. The chips 30 may be sawn after the protection layer 26 has been deposited. As shown in Fig. 4, the separation of the chips 30 from each other causes that the protection layer 26 (and the termination layer 22) may be cut with the sawing tool, resulting in sharp rims. At the sawing surfaces, the chips 30 are not covered by the protection layer 26.
Fig. 5 shows the semiconductor chips 30 on the tape 28 during dicing.
When the protection layer 26 is deposited before the wafer 10 is attached to the tape 28 (for example via atomic laser deposition), the tape 28 may be used to remove a part of the protection layer 26 from the chip 30, which is covering the bottom side and/or the metallization layer 18 of the chip 30.
The metallization layer 18 may be used for soldering the chip 30 to a further substrate and therefore may have to be clean enough for this process step.
When the protection layer 26 sticks better to the tape 28 as to the metallization layer 18, the part of the protection layer 26 covering the metallization layer 18 may be removed from the chip 30 during the picking of the chip 30. This may be achieved, when the protection layer 26 has a worse adhesion to the metallization layer 18 as to the tape 28. Then, after dicing, the deposited material of the protection layer 26 on the bottom side of the chip 30 will stick on the tape 28 during picking. For example, this may be the case for a protection layer made of A1203 and a metallization layer 18 made of Ag.
Fig. 6 shows a semiconductor module 32 onto which a semiconductor chip 30, which was manufactured as shown in Fig. 1 to 5, is bonded.
The semiconductor module 32 comprises a substrate 34 with a metallization layer 36 to which the semiconductor chip 30 is bonded (for example soldered) and one or more bond wires 38 interconnecting the electrode area provided by the metallization layer 16 of the chip 30 with a (further part) of the metallization layer 36 of the semiconductor module 32.
The parts of the bond wires 38 bonded to the metallization layer 16 have been bonded by ultrasonic welding. During the welding, the part of the protection layer 26 between the part of the bond wire 38 and the metallization layer 16 has been removed by the vibrations present during ultrasonic welding. It is not needed to etch a window into the protection layer 26 to open the electrode area, since during the ultrasonic welding of the bond wire 38, the friction between both surfaces of the wire bond 38 and the protection layer 26 may disperse material from the protection layer 26. In summary, while bonding through the protection layer 28, the etching step may be skipped, although the chip 30 is hermetically sealed on the topside, except on the edges, where it has been sawn.
While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art and practising the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. A single processor or controller or other unit may fulfil the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope.
LIST OF REFERENCE SYMBOLS
10 wafer
12 semiconductor substrate
14 semiconductor element
16 first metallization layer
18 second metallization layer
20 passivation layer
22 termination layer
24 polyimide
26 protection layer
28 tape
30 chip
32 semiconductor module
34 substrate
36 metallization layer
38 bond wire

Claims

A method for manufacturing semiconductor chips (30), the method comprising: providing a wafer (10) for a plurality of semiconductor chips (30), the wafer (10) comprising for each semiconductor chip (30): a semiconductor substrate (12) comprising a semiconductor element (14), which semiconductor substrate (12) is covered by a metallization layer (16) providing an electrode area of the semiconductor chip (30), comprising a termination layer (22) on the semiconductor substrate (12) at a border of the semiconductor chip (30) and comprising an electrically non-conducting passivation layer (20) at least partially covering the termination layer (22) and partially covering at least one of the semiconductor substrate (12) and the metallization layer (16);
depositing a protection layer (26) by at least one of atomic layer deposition and laser deposition above the passivation layer (20) and the metallization layer (16) of the semiconductor chips, wherein the protection layer has a lower permeability with respect to moisture than the passivation layer (20);
after the depositing of the protection layer (26), sawing the wafer (10) into the semiconductor chips (30).
The method of claim 1 ,
wherein the protection layer (26) is made from a metal compound; and/or wherein the protection layer (26) is made from a metal oxide; and/or
wherein the protection layer (26) is made from at least one of A1203, ZrO, Hf02, TiN, Ti02.
The method of one of the previous claims,
wherein the protection layer (26) has a thickness of less than 1000 nm.
4. The method of one of the previous claims,
wherein the passivation layer (20) comprises organic material, a polymer material and/or a polyimide (24).
The method of one of the previous claims,
wherein both sides of the wafer (10) are deposited with the protection layer (26).
The method of one of the previous claims,
wherein the wafer (10) comprises for each semiconductor chip (30): a first metallization layer (16) on a first side and a second metallization layer (18) on a second, opposite side;
the method further comprising:
after depositing the protection layer (26) and before sawing, attaching the wafer (10) to an adhesive tape (28), the tape (28) having an adhesive surface with a higher adhesion to the protection layer (26) as the protection layer (26) to the second metallization layer (18) on the semiconductor chip (30);
after sawing, picking a semiconductor chip (30) from the tape (28), such that at least the protection layer (26) over the second metallization layer (18) remains on the adhesive tape (28).
The method of claim 6,
wherein the protection layer (28) is made from A1203 and the second metallization layer (18) is made from Ag.
The method of one of claims 1 to 4, further comprising:
before depositing the protection layer (26), attaching the wafer (10) to an adhesive tape, which protects a second side of the semiconductor chip (30) to be coated with the protection layer (26).
The method of one of the previous claims, further comprising:
ultrasonic welding a bond wire (38) to the metallization layer (16), such that during the welding, the part of the protection layer (26) between the bond wire and the metallization layer (16) is removed and the bond wire (38) is bonded to the metallization layer (16).
10. A semiconductor chip (30), comprising:
a semiconductor substrate (12) comprising a semiconductor element (14);
a metallization layer (16) on the semiconductor substrate (12), the metallization layer (16) providing an electrode area of the semiconductor chip (30);
an electrically non-conducting passivation layer (20), partially covering the semiconductor substrate (12) and/or the metallization layer (16);
a termination layer (22) on the semiconductor substrate (12) at a border of the semiconductor chip (30),
wherein the passivation layer (20) is at least partially covering the termination layer (22);
a protection layer (26) deposited above the passivation layer (20) and the metallization layer (16) and having a lower permeability with respect to moisture than the passivation layer (20);
wherein the protection layer (26) has been deposited by at least one of atomic layer deposition and laser deposition before the semiconductor chip (30) has been sawed from a wafer (10).
11. The semiconductor chip (30) of claim 10,
wherein the metallization layer (16) provides an electrode layer of the semiconductor chip (30).
12. The semiconductor chip (30) of claim 10 or 11, further comprising:
a first metallization layer (16) on a first side of the semiconductor substrate (12), wherein the passivation layer (20) and the protection layer (26) are arranged on the first side;
a second metallization layer (18) on a second, opposite side of the semiconductor substrate (12), which second metallization layer is made of Ag.
13. A semiconductor module (32), comprising:
a base substrate (34) with a metallization layer (36); a semiconductor chip (30) according to one of claims 10 to 12 attached to the base substrate (34);
at least one bond wire (38) bonded to the metallization layer (36) of the base substrate (34);
wherein the bond wire (38) is bonded to the metallization layer (36) of the semiconductor chip (30) through the protection layer (26) by ultrasonic welding.
PCT/EP2017/058033 2016-04-06 2017-04-04 Semiconductor chip with moisture protection layer WO2017174608A1 (en)

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EP16164088.3 2016-04-06

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