WO2017166109A1 - 一种低噪声放大器 - Google Patents

一种低噪声放大器 Download PDF

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Publication number
WO2017166109A1
WO2017166109A1 PCT/CN2016/077832 CN2016077832W WO2017166109A1 WO 2017166109 A1 WO2017166109 A1 WO 2017166109A1 CN 2016077832 W CN2016077832 W CN 2016077832W WO 2017166109 A1 WO2017166109 A1 WO 2017166109A1
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transistor
coupled
gate
output node
noise
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PCT/CN2016/077832
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English (en)
French (fr)
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张科峰
刘览琦
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武汉芯泰科技有限公司
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Priority to PCT/CN2016/077832 priority Critical patent/WO2017166109A1/zh
Publication of WO2017166109A1 publication Critical patent/WO2017166109A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements

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  • the present invention relates to the field of wireless communication transceiver technologies, and in particular, to a low noise amplifier.
  • the processed first-stage amplifier (low-noise amplifier, English abbreviated LNA) needs to have characteristics such as wideband, high gain, high linearity, low noise, and impedance matching.
  • the LNA is required to output a differential signal.
  • the LNA is the first stage in which the chip is connected to the antenna, which acts to amplify the antenna signal.
  • the useful signal in the communication band is amplified by the low noise amplifier, and the noise generated by the wireless spatial channel is suppressed by the gain of the amplifier, and the added noise of the amplifier itself is very small, so that the useful signal is amplified without affecting Its quality.
  • the various types of interference from the wireless spatial channel will produce signal intermodulation, which will be suppressed by the good linear performance of the amplifier.
  • the LNAs currently on the market are mainly divided into two categories: one is the differential input differential output type LNA.
  • this structure When this structure is matched with the antenna, it needs to connect a single-ended to differential transformer, which is improved in disguise. Cost; the other is a single-ended input, differential output LNA, this LNA needs no external transformer, and the noise-cancellation structure can eliminate the noise of one transistor at the input (the main source of noise), but this structure There is often a problem that the output impedance differential end is unbalanced.
  • the LNAs currently on the market are mainly divided into the following two categories: one is the use of off-chip inductors for impedance matching, but this scheme adds off-chip passive components, and often makes the LNA work in a narrow band.
  • the other is to use the source input impedance characteristics of the transistor to form a common gate tube matching.
  • This matching can achieve good results in the frequency band of several GHz, but due to the crystal
  • the transconductance requirements of the body tube are strict, which greatly limits the gain performance of the LNA.
  • the technical problem to be solved by the present invention is to provide a low noise amplifier for the compromise between the characteristics of impedance matching, low noise, high linearity, impedance balance, and high gain of the LNA in the background art.
  • the technical solution adopted by the present invention to solve the technical problem thereof is to construct a low noise amplifier, including:
  • a matching amplifier stage circuit comprising: an input node, a first transistor, a second transistor, a first output node, and a second output node; a source of the first transistor coupled to the input node, a drain coupled to the An output node to convert a noise current at the input node to a first noise voltage of the first output node; a gate of the second transistor coupled to a source stage of the first transistor, a drain thereof Coupled to the second output node to convert a noise current at the input node to a second noise voltage of the second output node; summing the second noise voltage with the first noise voltage to Eliminating the noise of the first transistor;
  • a gain boosting stage circuit comprising: a first pair of transistors and a second pair of transistors coupled to the first pair of transistors; the first pair of transistors being coupled to the first output node and the second output node, respectively
  • the current polarity of the first pair of transistors and the second pair of transistors is determined to suppress noise of the second transistor.
  • the first pair of transistors includes:
  • a third transistor having a gate coupled to the first output node
  • a fourth transistor having a gate coupled to the second output node.
  • the second pair of transistors includes:
  • a fifth transistor having a gate coupled to a gate of the third transistor, a second derivative of a transconductance of the fifth transistor being opposite to a second derivative of a transconductance of the third transistor;
  • a sixth transistor having a gate coupled to a gate of the fourth transistor, a second derivative of a transconductance of the sixth transistor being opposite a second derivative of a transconductance of the fourth transistor.
  • the gain boosting stage circuit further includes a first capacitor and a second capacitor; the first capacitor is coupled to a gate of the third transistor and a gate of the fifth transistor Extreme The second capacitor is coupled between a gate of the fourth transistor and a gate of the sixth transistor.
  • the gain boosting stage circuit further includes a first resistor and a second resistor; the first resistor is coupled to a drain of the third transistor, and the second resistor is coupled to The drain of the fourth transistor.
  • the first transistor is a common gate transistor and the second transistor is a common source transistor.
  • the matched amplification stage circuit further includes:
  • a common gate resistor coupled to a drain of the first transistor
  • the matched amplifier stage circuit further includes an input capacitor coupled between the source stage of the first transistor and the gate of the second transistor.
  • the matched amplifier stage circuit further includes an off-chip inductor coupled to the source stage of the first transistor.
  • the low noise amplifier disclosed above has the following beneficial effects: by adopting a noise canceling structure in the matching amplifier stage of the preceding stage, the broadband impedance matching is realized while ensuring the minimization of the first stage noise, thereby improving the noise of the overall LNA. Performance; in the gain-enhancing stage of the latter stage, a multi-transistor multiplexing structure is adopted. Since it is a symmetrical structure, the output impedance of the differential terminal is balanced. This structure eliminates the nonlinearity caused by gain boost while increasing the overall gain. At the same time, since the weak inversion transistor is in the latter stage of the LNA, the noise introduced is negligible. On the whole, such a technical solution effectively improves the noise performance and gain performance of the LNA circuit without deteriorating its linear performance.
  • FIG. 1 is a functional block diagram of a low noise amplifier provided by the present invention
  • FIG. 2 is a schematic structural diagram of a low noise amplifier provided by the present invention.
  • FIG. 3 is a schematic diagram of the principle of eliminating the second derivative of the transconductance provided by the present invention.
  • FIG. 1 is a functional block diagram of a low noise amplifier provided by the present invention.
  • the low noise amplifier comprises two stages, a matching amplification stage and a gain improvement stage.
  • the matching amplifier stage adopts the common gate input matching and noise cancellation structure, which realizes broadband matching of LNA, single-ended to differential conversion and extremely low noise performance.
  • the gain boosting stage provides a positive gain, which improves the overall LNA gain, and solves the problem that the matching amplifier stage has low gain due to common-gate matching.
  • the gain boost stage two NMOS transistors operating in the weak inversion region are used, and their increased third-order nonlinear current polarity is opposite to that of the amplifier transistor of the stage, thereby canceling each other, thereby eliminating the non- Linearity issues, so this stage provides both gain and excellent linear performance.
  • FIG. 2 is a schematic structural diagram of a low noise amplifier 100 according to the present invention.
  • the low noise amplifier 100 includes a matching amplifier stage circuit 1 and a gain boost stage circuit 2.
  • the matching amplifier circuit 1 First, the matching amplifier circuit 1
  • the matching amplifier stage circuit 1 includes an input node 10, a first transistor 11, a second transistor 12, a first output node 13, and a second output node 14; a source stage of the first transistor 11 is coupled to the input node 10 (ie An antenna impedance) having a drain coupled to the first output node 13 to convert a noise current at the input node 10 to a first noise voltage of the first output node 13; A gate coupled to a source stage of the first transistor 11 and a drain coupled to the second output node 14 to convert a noise current at the input node 10 to a second of the second output node 14 a noise voltage; forming a differential signal with the first noise voltage by the second noise voltage to cancel noise of the first transistor 11; specifically, the first transistor 11 is a common gate transistor (M1), the second The transistor 12 is a common source transistor (M2).
  • the matched amplifier stage circuit 1 further includes an input capacitor 17, an off-chip inductor 18, a common gate resistor 15 (R CG ), and a common source resistor 16 (R CS ).
  • a common gate resistor 15 is coupled to the drain of the first transistor 11; a common source resistor 16 is coupled to the drain of the second transistor 12.
  • the input capacitor 17 is coupled between a source stage of the first transistor 11 and a gate of the second transistor 12.
  • the off-chip inductor 18 is coupled to a source stage of the first transistor 11.
  • the parameters in the matching amplifier stage circuit 1 are as follows:
  • g m,CS input transconductance of the common source transistor M2;
  • V n,in the equivalent of the noise voltage generated by M1 at its source
  • V n, CG the equivalent noise voltage of M1 at the output (drain);
  • V n,CS the equivalent noise voltage of M2 at the output (drain);
  • a v, CG M1 amplification gain of the signal
  • a v, CS M2 amplification gain of the signal.
  • the matching amplifier stage is formed by combining a common gate input transistor M1 and a common source input transistor M2.
  • the input impedance of the common-gate input transistor can be regarded as the reciprocal of its transconductance, that is, 1/g m, CG , and the apparent antenna impedance is R S , so that only the two are equal, impedance matching can be achieved over a relatively wide frequency range. , which is
  • the principle of converting a single-ended signal to a differential signal is as follows: First, for a signal input from the antenna impedance R S to the source of M1, the signal is considered to be a small signal current i in , and the small signal current will pass through M1. The load of M1 flows through R CG . According to Kirchhoff's current law, the input small signal current is calculated as:
  • the low noise principle is to use the common source transistor M2 to amplify the noise Vn at the source end of the M1 to generate noise having the same phase and the same amplitude as the M1 drain terminal, that is, the R CG , so that the noise can cancel each other out in the output differential signal.
  • M1 is a transistor in the first stage, it amplifies the signal, so this part of the noise is eliminated, which will greatly benefit the low noise design of the LNA. This process needs to meet some conditions.
  • the noise current generated by M1 flows from R CG to R S at the antenna end. This noise current will generate noise voltage at the source and drain of M1, respectively.
  • V n,in 1/2 ⁇ i n ⁇ R s ;
  • V n, CG -1/2 ⁇ i n ⁇ R CG .
  • V n,in is amplified via the gate of M2. According to equation (3), this noise voltage is amplified as:
  • Equations (2), (3), and (4) can be converted into:
  • the noise voltage generated by M1 is in phase and amplitude is one. Since the differential signal is subtracted from the signal at both ends, in differential signal transmission, this noise is cancelled out during the subtraction due to the phase amplitude, and the noise of M1 is completely eliminated. It is worth noting that since M1 and M2 are the amplifying transistors in the first stage, their noise has the greatest influence on the LNA. Eliminating the noise of M1 will greatly optimize the noise performance of the LNA.
  • the noise of M2 cannot be eliminated by this structure, but since the work of impedance matching is mainly done by M1, the size of M2 does not necessarily need to maintain a specific transconductance, so it is possible to increase the size of M2 ( That is, the transconductance is increased to suppress the noise of M2.
  • the load resistance R CS of M2 which causes the output impedance imbalance of the matching amplifier stage, which is solved by the second stage gain boost stage.
  • the gain boost stage circuit 2 includes a first pair of transistors 21 and a second pair of transistors 22 coupled to the first pair of transistors 21; the first pair of transistors 21 are coupled to the first output node 13 and the second, respectively
  • the output node 14 suppresses the noise of the second transistor 12 by setting the current polarity of the first pair of transistors 21 and the second pair of transistors 22.
  • the first pair of transistors 21 includes a third transistor 211 (M3) and a fourth transistor 212 (M4).
  • a gate of the third transistor 211 is coupled to the first output node 13; a gate of the fourth transistor 212 is coupled to the second output node 14.
  • the second pair of transistors 22 includes a fifth transistor 221 (M5) and a sixth transistor 222 (M6).
  • a gate of the fifth transistor 221 is coupled to a gate of the third transistor 211, a second derivative of the transconductance of the fifth transistor 221 is opposite to a second derivative of the transconductance of the third transistor 211;
  • the gate of the six transistor 222 is coupled to the gate of the fourth transistor 212, and the second derivative of the transconductance of the sixth transistor 222 is opposite to the second derivative of the transconductance of the fourth transistor 212.
  • the gain boosting stage circuit 2 further includes a first resistor 25 (Rout), a second resistor 26 (Rout), a first capacitor 23 and a second capacitor 24; the first capacitor 23 is coupled to the third transistor 211 Between the gate and the gate of the fifth transistor 221, the second capacitor 24 is coupled between the gate of the fourth transistor 212 and the gate of the sixth transistor 222.
  • the first resistor 25 is coupled to a drain of the third transistor 211, and the second resistor 26 is coupled to a drain of the fourth transistor 212.
  • the parameters in the gain boost stage circuit 2 are as follows:
  • g m ′′ the second derivative of the transconductance of the transistor.
  • IIP 3 Input Third Intercept Point inputs the third-order intercept point to characterize the linear performance of the circuit. The bigger the better.
  • M2 in Fig. 2 can change the size boost transconductance to suppress noise, its gain is still limited by M1 because it has to be kept the same size as M1. M1 needs to meet the impedance matching
  • the technique seeks an increase in gain at the gain boost stage and solves the problem of unbalanced output impedance of the matched amplifier stage.
  • the present invention introduces a multi-transistor multiplexing technique (MGTR) in the gain boosting stage, and uses an additional weak inversion transistor to eliminate the nonlinear current of the amplifying transistor.
  • MGTR multi-transistor multiplexing technique
  • M3 and M4 are amplifying transistors operating in the saturation region, while M5 and M6 are additional transistors operating in the weak inversion region (weak signal amplification).
  • the calculation of the third-order intercept point IIP 3 is:
  • M5 operate in the weak inversion region by introducing and M6 , a positive g m ", and the transistors M3 and M4 amplifying negative g m" cancel each other, eliminating third-order nonlinearity, such that the formula (6) radical in the denominator close to zero, greatly improved
  • the indicator level of IIP 3 is shown in Figure 3.
  • the input voltage is scanned for M3 to M6, and the second derivative transconductance g m "" at different input voltages is measured.
  • the figure shows the g m of the amplifying transistors M3 and M4 operating in the saturation region. "It is a negative value, and transistors M5 and M6 operating in the weak inversion region generate a positive value of g m ".
  • the combined equivalent g m " is close to 0 in the small signal range. (The curve in the figure near the middle portion), whereby, according to equation (6), the structure can increase the maximum IIP 3 value.
  • This structure also solves the problem of gain design. Since M3 and M4 work in the saturation region, the signal amplification is performed, and the gain of the signal is:
  • This gain can effectively compensate for the gain limitation of the previous matching amplifier stage due to the common-gate matching structure.
  • the technical solution creatively combines the noise canceling structure and the multi-transistor multiplexing structure. Potential. Because in the radio frequency wireless communication module, there is such a law: 1. The more the module in the former stage, the greater the influence of noise on the overall communication link, and the less the degree of influence on the linear performance of the link; In the latter stage, the linearity performance has greater influence on the overall communication link, and the impact on the noise performance of the link is smaller. 3. The gain improvement leads to the optimization of noise performance and the deterioration of linear performance.
  • the noise canceling structure is adopted, and the broadband impedance matching is realized while minimizing the noise of the first stage, thereby improving the noise performance of the overall LNA; in the gain boosting stage of the latter stage, A multi-transistor multiplexing structure, since it is a symmetrical structure, the output impedance of the differential terminal is balanced. This structure eliminates the nonlinearity caused by gain boost while increasing the overall gain. At the same time, since the weak inversion transistor is in the latter stage of the LNA, the noise introduced is negligible. On the whole, such a technical solution effectively improves the noise performance and gain performance of the LNA circuit without deteriorating its linear performance.
  • the technical solution solves the design challenges of impedance matching, impedance balance, noise performance, gain performance, and linear performance of the LNA circuit.
  • the prior art proposed in the background art employs a low gain design or a compensating design as in the first scheme when improving the linear performance of the LNA.
  • the technical solution introduces two PMOS transistors operating in the weak inversion region in the first stage, the noise generated by them will have a huge impact on the LNA.
  • the prior art proposed in the background art employs a noise canceling technique when improving the noise performance of the LNA.
  • This technique can achieve broadband matching at the same time, but its negative effect is that the gain design is pinched by the antenna impedance, which makes it difficult for the LNA to achieve higher gain, and in order to achieve output differential impedance balance, a buffer stage must be introduced. If you add a gain at the buffer level, it will have a large amount of nonlinear effects because the stage is at the back stage. If a structure with no gain or negative gain is used at the buffer level, it does not help to increase the inherently low circuit gain.
  • the scheme adopts a similar structure of the prior art sound canceling technology to ensure that the first stage having the greatest influence on noise can have the minimum noise and achieve broadband matching.
  • the second stage of the LNA a multi-transistor multiplexing structure is introduced, and output impedance balance, high gain, high linearity, etc. are achieved, and the noise of the introduced transistor is negligible due to the noise level in the second stage. .
  • the one or more operations may constitute computer readable instructions stored on one or more computer readable media, which are executed by an electronic device The line time will cause the computing device to perform the operation.
  • the order in which some or all of the operations are described should not be construed as implying that the operations must be sequential. Those skilled in the art will appreciate alternative rankings that have the benefit of this specification. Moreover, it should be understood that not all operations must be present in every embodiment provided herein.
  • the word "preferred” as used herein is intended to serve as an example, instance, or illustration. Any aspect or design described herein as “preferred” need not be construed as being more advantageous than other aspects or designs. Instead, the use of the word “preferred” is intended to present a concept in a specific manner.
  • the term “or” as used in this application is intended to mean an “or” or “an” That is, unless otherwise specified or clear from the context, "X employs A or B” means naturally including any one of the permutations. That is, if X uses A; X uses B; or X uses both A and B, then "X uses A or B" is satisfied in any of the foregoing examples.
  • Each functional unit in the embodiment of the present invention may be integrated into one processing module, or each unit may exist physically separately, or two or more units may be integrated into one module.
  • the above integrated modules can be implemented in the form of hardware or in the form of software functional modules.
  • the integrated modules, if implemented in the form of software functional modules and sold or used as stand-alone products, may also be stored in a computer readable storage medium.
  • the above mentioned storage medium may be a read only memory, a magnetic disk or an optical disk or the like.

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Abstract

一种低噪声放大器，包括：匹配放大级电路（1），包括第一晶体管（11）、第二晶体管（12）、第一输出节点（13）及第二输出节点（14）；第一晶体管（11）的源级耦合至天线阻抗（10），其漏极耦合至第一输出节点（13）；第二晶体管（12）的栅极耦合至第一晶体管（11）的源级，其漏极耦合至第二输出节点（14）；增益提升级电路（2），包括第一对晶体管（21）及耦合至第一对晶体管（21）的第二对晶体管（22）；第一对晶体管（21）分别耦合至第一输出节点（13）及第二输出节点（14）。所述低噪声放大器有益效果为：实现宽带阻抗匹配的同时确保了第一级噪声的最小化，从而提升整体LNA的噪声性能，实现差分端的输出阻抗平衡，消除了增益提升带来的非线性。

Description

一种低噪声放大器 技术领域
本发明涉及无线通信收发器技术领域，尤其涉及一种低噪声放大器。
背景技术
随着技术的发展，集成无线通信芯片被大量应用于作战***、大规模应急通信***、导航定位、物联网、传感器网络、数字电视广播、公共安全、智能楼宇家居、无线电台、移动终端、玩具电子等多个行业，相应也衍生出了多样的通信协议标准。为了顺应市场的需求，当前无线通信领域最热门的研究就是设计一款兼容多协议的收发器芯片，以满足用户日益增长的语音、视频、数据浏览等需求，这就要求作为无线通信收发器信号处理的第一级放大器(低噪声放大器，英文简写LNA)需要兼具有宽带、高增益、高线性度、低噪声、阻抗匹配等特性指标。同时，为使信号更好的处理，要求LNA可以输出差分信号。
LNA是芯片与天线相连的第一级，它起到了对天线信号进行放大的作用。在这个过程中，通信频带内的有用信号被低噪声放大器放大，而由无线空间信道产生的噪声被放大器的增益抑制，同时放大器本身附加的噪声非常小，使得有用信号被放大的同时并不影响其质量。无线空间信道传来的各类干扰将产生信号交调量，这部分干扰将由放大器良好的线性性能抑制。
从结构上来看，目前市场上的LNA主要分为两类：一类是差分输入差分输出型的LNA，这种结构在与天线进行匹配时，需要外接一个单端转差分的变压器，变相提升了成本；另一类是单端输入、差分输出的LNA，这种LNA需要不需要外置的变压器，同时采用噪声消除的结构可以消除输入端的一个晶体管的噪声(主要噪声来源)，但是这种结构往往存在输出阻抗差分端不平衡的问题。
从匹配方式看，目前市场上的LNA主要分为以下两类：一类是采用片外电感电容进行阻抗匹配，但这种方案增加了片外无源器件，且往往使LNA的工作在窄带，应用于单频点的无线通信；另一类是利用晶体管的源极输入阻抗特性，形成共栅极管匹配，这种匹配可以在数GHz的频带内达到良好的效果，但由于对晶 体管的跨导要求严格，极大的限制了LNA的增益性能。
技术问题
本发明要解决的技术问题在于，针对背景技术中LNA的阻抗匹配、低噪声、高线性度、阻抗平衡、高增益等特性间的折中难题，提供一种低噪声放大器。
问题的解决方案
技术解决方案
本发明解决其技术问题所采用的技术方案是：构造一种低噪声放大器，包括：
匹配放大级电路，包括输入节点、第一晶体管、第二晶体管、第一输出节点及第二输出节点；所述第一晶体管的源级耦合至所述输入节点，其漏极耦合至所述第一输出节点，以将所述输入节点处的噪声电流转换为所述第一输出节点的第一噪声电压；所述第二晶体管的栅极耦合至所述第一晶体管的源级，其漏极耦合至所述第二输出节点，以将所述输入节点处的噪声电流转换为所述第二输出节点的第二噪声电压；通过所述第二噪声电压与所述第一噪声电压求和以消去第一晶体管的噪声；以及
增益提升级电路，包括第一对晶体管及耦合至所述第一对晶体管的第二对晶体管；所述第一对晶体管分别耦合至所述第一输出节点及所述第二输出节点，通过设定所述第一对晶体管与所述第二对晶体管的电流极性以抑制所述第二晶体管的噪声。
在本发明所述的低噪声放大器中，所述第一对晶体管包括：
第三晶体管，其栅极耦合至所述第一输出节点；以及
第四晶体管，其栅极耦合至所述第二输出节点。
在本发明所述的低噪声放大器中，所述第二对晶体管包括：
第五晶体管，其栅极耦合至所述第三晶体管的栅极，所述第五晶体管的跨导的二阶导数与所述第三晶体管的跨导的二阶导数符号相反；以及
第六晶体管，其栅极耦合至所述第四晶体管的栅极，所述第六晶体管的跨导的二阶导数与所述第四晶体管的跨导的二阶导数符号相反。
在本发明所述的低噪声放大器中，所述增益提升级电路还包括第一电容及第二电容；所述第一电容耦合至所述第三晶体管的栅极与所述第五晶体管的栅极之 间，所述第二电容耦合至所述第四晶体管的栅极与所述第六晶体管的栅极之间。
在本发明所述的低噪声放大器中，所述增益提升级电路还包括第一电阻及第二电阻；所述第一电阻耦合至所述第三晶体管的漏极，所述第二电阻耦合至所述第四晶体管的漏极。
在本发明所述的低噪声放大器中，所述第一晶体管为共栅晶体管，所述第二晶体管为共源晶体管。
在本发明所述的低噪声放大器中，所述匹配放大级电路还包括：
共栅电阻，其耦合至所述第一晶体管的漏极；以及
共源电阻，其耦合至所述第二晶体管的漏极。
在本发明所述的低噪声放大器中，所述匹配放大级电路还包括输入电容，所述输入电容耦合至所述第一晶体管的源级及所述第二晶体管的栅极之间。
在本发明所述的低噪声放大器中，所述匹配放大级电路还包括片外电感，所述片外电感耦合至所述第一晶体管的源级。
发明的有益效果
有益效果
上述公开的一种低噪声放大器具有以下有益效果：通过在靠前级的匹配放大级采用噪声消除结构，在实现宽带阻抗匹配的同时确保了第一级噪声的最小化，从而提升整体LNA的噪声性能；在靠后级的增益提升级，采用了多晶体管复用结构，由于其是一种对称性结构，其差分端的输出阻抗是平衡的。这种结构在提升整体增益的同时，消除了增益提升带来的非线性。与此同时，由于弱反型的晶体管处于LNA的后一级，其引入的噪声是可以忽略不计的。从整体上看，这样的技术方案有效的提升了LNA电路的噪声性能、增益性能，同时并没有恶化其线性性能。
对附图的简要说明
附图说明
图1为本发明提供的一种低噪声放大器的功能框图；
图2为本发明提供的一种低噪声放大器的结构示意图；
图3为本发明提供的跨导的二阶导数的消除原理示意图。
发明实施例
本发明的实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本发明，并不用于限定本发明。
本发明提供的本发明提供了一种组合了噪声消除技术与多场效应复用技术(Multi-gated Transistor，MGTR)的LNA，在一种噪声消除结构的后级采用了MGTR形式的缓冲器，解决了LNA的阻抗匹配、低噪声、高线性度、阻抗平衡、高增益等特性间的折中难题。参见图1，图1为本发明提供的一种低噪声放大器的功能框图。该低噪声放大器包括两级，分别是匹配放大级与增益提升级。其中，匹配放大级采用了共栅输入匹配与噪声消除结构，实现了LNA的宽带匹配、单端到差分的转换与极低噪声性能。其引入的输出阻抗不平衡的问题由第二级增益提升级解决，同时增益提升级提供正的增益，使整体LNA增益得到提升，解决了匹配放大级因共栅匹配带来的增益低的问题。再者，在增益提升级采用了两个工作在弱反型区的NMOS晶体管，他们提升的三阶非线性电流极性与该级的放大晶体管相反，互相抵消，从而消除放大晶体管带来的非线性问题，因此该级同时提供了增益与优良的线性性能。
参见图2，图2为本发明提供的一种低噪声放大器100的结构示意图，该低噪声放大器100包括匹配放大级电路1及增益提升级电路2。
一、匹配放大级电路1
匹配放大级电路1包括输入节点10、第一晶体管11、第二晶体管12、第一输出节点13及第二输出节点14；所述第一晶体管11的源级耦合至所述输入节点10(即天线阻抗)，其漏极耦合至所述第一输出节点13，以将所述输入节点10处的噪声电流转换为所述第一输出节点13的第一噪声电压；所述第二晶体管12的栅极耦合至所述第一晶体管11的源级，其漏极耦合至所述第二输出节点14，以将所述输入节点10处的噪声电流转换为所述第二输出节点14的第二噪声电压；通过所述第二噪声电压与所述第一噪声电压形成差分信号以消去第一晶体管11的 噪声；具体的，所述第一晶体管11为共栅晶体管(M1)，所述第二晶体管12为共源晶体管(M2)。所述匹配放大级电路1还包括输入电容17、片外电感18、共栅电阻15(RCG)及共源电阻16(RCS)。共栅电阻15耦合至所述第一晶体管11的漏极；共源电阻16耦合至所述第二晶体管12的漏极。所述输入电容17耦合至所述第一晶体管11的源级及所述第二晶体管12的栅极之间。所述片外电感18耦合至所述第一晶体管11的源级。
匹配放大级电路1中的参数如下：
iin：由天线信号等效的输入小信号电流；
gm，CG：输入共栅晶体管M1的跨导；
gm，CS：输入共源晶体管M2的跨导；
Vn，in：由M1产生的噪声电压在其源极的等效；
Vn，CG：M1在输出端(漏极)的等效噪声电压；
Vn，CS：M2在输出端(漏极)的等效噪声电压；
Av，CG：M1对信号的放大增益；
Av，CS：M2对信号的放大增益。
匹配放大级由共栅输入晶体管M1与共源输入晶体管M2组合而成。共栅输入晶体管的输入阻抗可视为其跨导的倒数，即1/gm，CG，视天线阻抗为RS，则只需二者相等，就可以在相当宽的频率范围内实现阻抗匹配，即
RS＝Rin＝1/gm，CG。
其单端信号转为差分信号的原理如下：首先，对于从天线阻抗RS输入到M1的源极的信号，可认为该信号是一个小信号电流iin，该小信号电流将经过M1，在M1的负载RCG上流过，根据基尔霍夫电流定律，对于输入小信号电流计算为：
iin＝Vout，CG/RCG＝Vin·Av，CG/RCG         (1)
这意味着共栅晶体管M1的输入阻抗可以表示为：
Rin＝Vin/iin＝RCG/Av，CG＝1/gm，CG＝RS          (2)
从(2)式可以得出，M1所提供的增益Av，CG为Av，CG＝gm，CG·RCG。而对于M2，其是标准的共源输入放大晶体管，因此其增益等于跨导与负载的相乘，同时对信号 的相位产生反转，即为Av，CS＝-gm，CS·RCS。综合起来，则有：
Av，CG＝-Av，CS＝gm，CG·RCG＝gm，CS·RCS         (3)
从(3)式可以看到，对于同一个天线信号，M1与M2对其的放大增益大小相同，但极性相反，因此在M1与M2的漏输出就形成了幅度相同而相位相差180°的差分信号，从而完成了单端信号至差分信号的转变过程。
其低噪声原理是利用共源晶体管M2将M1源端的噪声Vn放大，产生与M1漏端也就是RCG处相位相同且幅度相同的噪声，从而在输出的差分信号中，这个噪声可以互相抵消，这样，从整体上看，M1产生的噪声就被消除了。由于M1是处于第一级的晶体管，对信号有放大作用，因此这部分噪声被消除将极大的有利于LNA的低噪声设计。这个过程需要满足一些条件，首先，由M1产生的噪声电流从RCG流至天线端的RS，这个噪声电流将在M1的源极和漏极分别产生噪声电压
Vn，in＝1/2·in·Rs；
Vn，CG＝-1/2·in·RCG。
同时，Vn，in经由M2的栅极被放大，根据式(3)，这个噪声电压被放大为：
Vn，CS＝Vn，in·Av，CS＝α·in·Rs·(-gm，CS·RCS)         (4)
由式(2)、(3)，式(4)可以被换算为：
Vn，CS＝-α·in·RCG＝Vn，CG          (5)
可以看到，在M1与M2的漏端，由M1产生的噪声电压是同相位且幅度一至的。由于差分信号是两端信号相减得来，因此在差分信号传输中，这个噪声在相减的过程中由于相位幅度一至而被抵消了，从而M1的噪声被完全消除。值得注意的是，由于M1与M2是处在第一级的放大晶体管，它们的噪声对LNA而言影响是最大的，消除掉M1的噪声会使LNA的噪声性能得到极大的优化。
另一方面，M2的噪声并不能通过这个结构来消除，但由于阻抗匹配的工作主要由M1完成，因此M2的尺寸并不一定需要其保持特定的跨导，所以可以通过加大M2的尺寸(即提高了跨导)来抑制M2的噪声。为了满足(3)式，相应需要减小M2的负载电阻RCS，这样造成了匹配放大级的输出阻抗不平衡，这个问题由第二级增益提升级解决。
二、增益提升级电路2
增益提升级电路2包括第一对晶体管21及耦合至所述第一对晶体管21的第二对晶体管22；所述第一对晶体管21分别耦合至所述第一输出节点13及所述第二输出节点14，通过设定所述第一对晶体管21与所述第二对晶体管22的电流极性以抑制所述第二晶体管12的噪声。具体的，所述第一对晶体管21包括第三晶体管211(M3)及第四晶体管212(M4)。第三晶体管211的栅极耦合至所述第一输出节点13；第四晶体管212的栅极耦合至所述第二输出节点14。所述第二对晶体管22包括第五晶体管221(M5)及第六晶体管222(M6)。第五晶体管221的栅极耦合至所述第三晶体管211的栅极，所述第五晶体管221的跨导的二阶导数与所述第三晶体管211的跨导的二阶导数符号相反；第六晶体管222的栅极耦合至所述第四晶体管212的栅极，所述第六晶体管222的跨导的二阶导数与所述第四晶体管212的跨导的二阶导数符号相反。所述增益提升级电路2还包括第一电阻25(Rout)、第二电阻26(Rout)、第一电容23及第二电容24；所述第一电容23耦合至所述第三晶体管211的栅极与所述第五晶体管221的栅极之间，所述第二电容24耦合至所述第四晶体管212的栅极与所述第六晶体管222的栅极之间。所述第一电阻25耦合至所述第三晶体管211的漏极，所述第二电阻26耦合至所述第四晶体管212的漏极。
增益提升级电路2中的参数如下：
gm：晶体管的跨导；
gm″：晶体管跨导的二阶导数。
IIP3：Input Third Intercept Point输入三阶交调点，表征电路线性性能，越大越好。
在匹配放大级，虽然图2中的M2可以改变尺寸提升跨导来抑制噪声，但其增益由于要保持与M1大小一致，因此仍受到M1的限制。而M1为了实现阻抗匹配需要满足
Rs＝Rin＝1/gm，CG，
也就限制了其跨导gm，CG的值，从而对增益有很大的限制。如果过于通过提升其负载电阻RCG来寻求增益的提升，则又会因为电源电压的限制导致输出动态范围下降，甚至导致M1因漏端电压不足难以正常工作。因此，在匹配放大级是难以 做到高增益性能的。
本技术在增益提升级寻求了增益的提升，同时解决了匹配放大级输出阻抗不平衡的问题。而不同于一般的技术，在增益提升时带来严重的非线性问题，本发明在增益提升级引入了多晶体管复用技术(MGTR)，使用额外的弱反型晶体管消除放大晶体管的非线性电流，从而去除因增益提升带来的非线性问题。
M3及M4为工作在饱和区的放大晶体管，而M5与M6为工作在弱反型区的附加晶体管(对信号放大功能微弱)。对于一个晶体管而言，其三阶交调点IIP3的计算为：
Figure PCTCN2016077832-appb-000001
从式(6)可以看出，为了使IIP3尽可能取得最大值，晶体管的二阶导数跨导gm″需要接近于0。然而，对于一个工作在饱和区(从而取得优良的放大效果)的晶体管而言，其gm″为负值，从而产生三阶非线性，导致IIP3指标下降。与工作在饱和区的晶体管不同的是，工作在弱反型区的晶体管的gm″为正值。在本发明所使用的增益提升级中，通过引入工作于弱反型区的M5及M6，提供了正向的gm″，与放大晶体管M3及M4的负向gm″互相抵消，消除了三阶非线性，使得式(6)根式内的分母趋近于0，极大的提升了IIP3的指标水平，其原理如图3所示。
如图3所示，对M3～M6进行输入电压扫描，测量其在不同输入电压情况下的二阶导数跨导gm″。图中显示，工作在饱和区的放大晶体管M3及M4的gm″为负值，而工作在弱反型区的晶体管M5及M6则产生了一个正值的gm″，二者共同作用后，组合起来的等效gm″在小信号范围内贴近于0(图中靠近正中间部分的曲线)，由此，根据式(6)，本结构可以提升极大的IIP3值。本结构同时解决了增益设计的难题，由于M3及M4工作于饱和区，起到信号的放大作用，其对信号的增益为：
Av＝-gm·Rout               (7)
这个增益可以有效的弥补前面的匹配放大级因共栅匹配结构而产生的增益限制的问题。
综上所述，本技术方案创造性地结合了噪声消除结构与多晶体管复用结构的优 势。因为在射频无线通信模块中，存在这样的定律：1、越是靠前级的模块，其噪声对整体通信链路影响越大，而对链路的线性性能影响程度越小；2、越是靠后级的模块，其线性性能对整体通信链路影响越大，而对链路的噪声性能影响程度越小；3、增益的提升带来噪声性能的优化与线性性能的恶化。所以在靠前级的匹配放大级，采用噪声消除结构，在实现宽带阻抗匹配的同时确保了第一级噪声的最小化，从而提升整体LNA的噪声性能；在靠后级的增益提升级，采用了多晶体管复用结构，由于其是一种对称性结构，其差分端的输出阻抗是平衡的。这种结构在提升整体增益的同时，消除了增益提升带来的非线性。与此同时，由于弱反型的晶体管处于LNA的后一级，其引入的噪声是可以忽略不计的。从整体上看，这样的技术方案有效的提升了LNA电路的噪声性能、增益性能，同时并没有恶化其线性性能。
总而言之，本技术方案同时解决了LNA电路的阻抗匹配、阻抗平衡、噪声性能、增益性能、线性性能的设计难题。
针对背景技术中提出的现有技术在提升LNA的线性性能时采用低增益设计或者如技术方案一中的补偿性设计。但由于该技术方案在第一级就引入了两个工作在弱反型区的PMOS晶体管，它们产生的噪声将对LNA产生巨大的影响。
针对背景技术中提出的现有技术在提升LNA的噪声性能时采用噪声消除技术。这种技术同时可以实现宽带匹配，但其负面影响是增益设计受到天线阻抗的牵制，导致LNA很难达到较高的增益，而且为了达到输出差分阻抗平衡，必须引入缓冲级。如果在缓冲级添加增益，则会因为该级处于靠后级，产生大量非线性的影响。而如果在缓冲级使用无增益或负增益的结构，则无助于提升本来就不高的电路增益。
本方案在LNA的第一级采用现有技术中声消除技术类似的结构，确保对噪声影响最大的第一级能拥有最小的噪声，同时实现了宽带匹配。而在LNA的第二级，引入多晶体管复用结构，同时实现了输出阻抗平衡、高增益、高线性度等性能，同时引入的晶体管的噪声由于处在第二级，对整体噪声影响可以忽略。
本文提供了实施例的各种操作。在一个实施例中，所述的一个或多个操作可以构成一个或多个计算机可读介质上存储的计算机可读指令，其在被电子设备执 行时将使得计算设备执行所述操作。描述一些或所有操作的顺序不应当被解释为暗示这些操作必需是顺序相关的。本领域技术人员将理解具有本说明书的益处的可替代的排序。而且，应当理解，不是所有操作必需在本文所提供的每个实施例中存在。
而且，本文所使用的词语“优选的”意指用作实例、示例或例证。本文描述为“优选的”任意方面或设计不必被解释为比其他方面或设计更有利。相反，词语“优选的”的使用旨在以具体方式提出概念。如本申请中所使用的术语“或”旨在意指包含的“或”而非排除的“或”。即，除非另外指定或从上下文中清楚，“X使用A或B”意指自然包括排列的任意一个。即，如果X使用A；X使用B；或X使用A和B二者，则“X使用A或B”在前述任一示例中得到满足。
而且，尽管已经相对于一个或多个实现方式示出并描述了本公开，但是本领域技术人员基于对本说明书和附图的阅读和理解将会想到等价变型和修改。本公开包括所有这样的修改和变型，并且仅由所附权利要求的范围限制。特别地关于由上述组件(例如元件、资源等)执行的各种功能，用于描述这样的组件的术语旨在对应于执行所述组件的指定功能(例如其在功能上是等价的)的任意组件(除非另外指示)，即使在结构上与执行本文所示的本公开的示范性实现方式中的功能的公开结构不等同。此外，尽管本公开的特定特征已经相对于若干实现方式中的仅一个被公开，但是这种特征可以与如可以对给定或特定应用而言是期望和有利的其他实现方式的一个或多个其他特征组合。而且，就术语“包括”、“具有”、“含有”或其变形被用在具体实施方式或权利要求中而言，这样的术语旨在以与术语“包含”相似的方式包括。
本发明实施例中的各功能单元可以集成在一个处理模块中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。所述集成的模块如果以软件功能模块的形式实现并作为独立的产品销售或使用时，也可以存储在一个计算机可读取存储介质中。上述提到的存储介质可以是只读存储器，磁盘或光盘等。上述的各装置或***，可以执行相应方法实施例中的方法。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (9)

  1. 一种低噪声放大器，其特征在于，包括：
    匹配放大级电路，包括输入节点、第一晶体管、第二晶体管、第一输出节点及第二输出节点；所述第一晶体管的源级耦合至所述输入节点，其漏极耦合至所述第一输出节点，以将所述输入节点处的噪声电流转换为所述第一输出节点的第一噪声电压；所述第二晶体管的栅极耦合至所述第一晶体管的源级，其漏极耦合至所述第二输出节点，以将所述输入节点处的噪声电流转换为所述第二输出节点的第二噪声电压；通过所述第二噪声电压与所述第一噪声电压求和以消去第一晶体管的噪声；以及
    增益提升级电路，包括第一对晶体管及耦合至所述第一对晶体管的第二对晶体管；所述第一对晶体管分别耦合至所述第一输出节点及所述第二输出节点，通过设定所述第一对晶体管与所述第二对晶体管的电流极性以抑制所述第二晶体管的噪声。
  2. 根据权利要求1所述的低噪声放大器，其特征在于，所述第一对晶体管包括：
    第三晶体管，其栅极耦合至所述第一输出节点；以及
    第四晶体管，其栅极耦合至所述第二输出节点。
  3. 根据权利要求2所述的低噪声放大器，其特征在于，所述第二对晶体管包括：
    第五晶体管，其栅极耦合至所述第三晶体管的栅极，所述第五晶体管的跨导的二阶导数与所述第三晶体管的跨导的二阶导数符号相反；以及
    第六晶体管，其栅极耦合至所述第四晶体管的栅极，所述第六晶体管的跨导的二阶导数与所述第四晶体管的跨导的二阶导数符号相反。
  4. 根据权利要求3所述的低噪声放大器，其特征在于，所述增益提升级电路还包括第一电容及第二电容；所述第一电容耦合至所述第 三晶体管的栅极与所述第五晶体管的栅极之间，所述第二电容耦合至所述第四晶体管的栅极与所述第六晶体管的栅极之间。
  5. 根据权利要求3所述的低噪声放大器，其特征在于，所述增益提升级电路还包括第一电阻及第二电阻；所述第一电阻耦合至所述第三晶体管的漏极，所述第二电阻耦合至所述第四晶体管的漏极。
  6. 根据权利要求1所述的低噪声放大器，其特征在于，所述第一晶体管为共栅晶体管，所述第二晶体管为共源晶体管。
  7. 根据权利要求1或6所述的低噪声放大器，其特征在于，所述匹配放大级电路还包括：
    共栅电阻，其耦合至所述第一晶体管的漏极；以及
    共源电阻，其耦合至所述第二晶体管的漏极。
  8. 根据权利要求1所述的低噪声放大器，其特征在于，所述匹配放大级电路还包括输入电容，所述输入电容耦合至所述第一晶体管的源级及所述第二晶体管的栅极之间。
  9. 根据权利要求1所述的低噪声放大器，其特征在于，所述匹配放大级电路还包括片外电感，所述片外电感耦合至所述第一晶体管的源级。
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