WO2017156705A1 - Prédiction affine pour le codage vidéo - Google Patents

Prédiction affine pour le codage vidéo Download PDF

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Publication number
WO2017156705A1
WO2017156705A1 PCT/CN2016/076360 CN2016076360W WO2017156705A1 WO 2017156705 A1 WO2017156705 A1 WO 2017156705A1 CN 2016076360 W CN2016076360 W CN 2016076360W WO 2017156705 A1 WO2017156705 A1 WO 2017156705A1
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WIPO (PCT)
Prior art keywords
block
affine
mvs
neighboring
amvr
Prior art date
Application number
PCT/CN2016/076360
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English (en)
Inventor
Tzu-Der Chuang
Ching-Yeh Chen
Han HUANG
Xiaozhong Xu
Shan Liu
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Mediatek Inc.
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Filing date
Publication date
Application filed by Mediatek Inc. filed Critical Mediatek Inc.
Priority to PCT/CN2016/076360 priority Critical patent/WO2017156705A1/fr
Priority to EP17765801.0A priority patent/EP3414900A4/fr
Priority to CN202110949285.3A priority patent/CN113612994B/zh
Priority to RU2018134794A priority patent/RU2696551C1/ru
Priority to CN201780017425.5A priority patent/CN108781284B/zh
Priority to SG11201806865YA priority patent/SG11201806865YA/en
Priority to PCT/CN2017/076420 priority patent/WO2017157259A1/fr
Priority to US16/083,662 priority patent/US10638152B2/en
Priority to TW106108289A priority patent/TWI617185B/zh
Publication of WO2017156705A1 publication Critical patent/WO2017156705A1/fr
Priority to US16/827,881 priority patent/US11375226B2/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
    • H04N19/503—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving temporal prediction
    • H04N19/51—Motion estimation or motion compensation
    • H04N19/513—Processing of motion vectors
    • H04N19/517—Processing of motion vectors by encoding
    • H04N19/52—Processing of motion vectors by encoding by predictive encoding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
    • H04N19/503—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving temporal prediction
    • H04N19/51—Motion estimation or motion compensation
    • H04N19/537—Motion estimation other than block-based

Definitions

  • the invention relates generally to video processing.
  • the present invention relates to methods for affine prediction in video coding and its extensions, 3D video coding, scalable video coding, screen content coding et al.
  • Acronym CE Core Experiments
  • CTB Long coding unit
  • HEVC High Efficiency Video Coding
  • IntraBC Intra picture Block Copy
  • the affine model can be shown in Fig .
  • the transformed block is a rectangular block.
  • the motion vector field of each point in this moving block can be described by the following equation.
  • (v0x, v0y) is the control point motion vector on top left corner
  • (v1x, v1y) is another control point motion vector on above right corner of the block.
  • an affine_flag is signalled to indicate whether the affine inter mode is applied or not. If the current CU is in affine inter mode, a candidate MVP pair list is built using the neighbour valid reconstructed blocks. As shown in Fig , the v0 is selected from the motion vectors of the block A0, A1 or A2, and the v1 is selected from the motion vectors of the block B0 and B1. The index of candidate MVP pair is signalled in the bit stream. The MV difference (MVD) of the two control points are coded in the bitstream.
  • MVD MV difference
  • an affine merge mode is also proposed. If current is a merge PU, the neighboring five blocks (C0, B0, B1, C1, and A0 blocks in Fig.2) are checked whether one of them is affine inter mode or affine merge mode. If yes, an affine_flag is signaled to indicate whether the current PU is affine mode.
  • the current PU When the current PU is applied in affine merge mode, it gets the first block coded with affine mode from the valid neighbour reconstructed blocks. The selection order for the candidate block is from left, above, above right, left bottom to above left (C0 ⁇ B0 ⁇ B1 ⁇ C1 ⁇ A0) as shown in Fig 2.
  • the affine parameter of the first affine coded block is used to derive the v0 and v1 for the current PU.
  • the decoded MVs of each PU are downsampled with a 16:1 ratio and stored in the temporal MV buffer for the MVP derivation for the following frames.
  • the top-left 4x4 MV is stored in the temporal MV buffer and the stored MV represents the MV of the whole 16x16 block.
  • Fig.1 is a diagram illustrating four parameter affine motion model.
  • Fig.2 is a diagram illustrating MVP derivation for affine inter mode.
  • Fig.3 is a diagram illustrating example of required MVs of the neighboring blocks in affine parameter derivation.
  • Fig.4 is a diagram illustrating the concept of storing two rows and two columns. DETAILED DESCRIPTION OF THE INVENTION
  • the neighboring block is affine coded block (includes affine inter mode block and affine merge mode block)
  • the MV of bottom-left NxN block is also used.
  • the block B and block E are the affine coded blocks.
  • the MVs of VB0, VB1 (and sometimes VB2 if a third control point is needed), VE0, and VE1 (and sometimes VE2 if a third control point is needed) are required.
  • MVs of the neighboring 4x4 block row and 4x4 block column of the current CU/CTU and the MVs of current CTU are stored.
  • Other MVs are downsampled stored in temporal MV buffer for the following frames or discarded. It requires additional MV buffers to stores the MVs of neighboring blocks for affine parameter derivation.
  • M M MV rows and K MV columns.
  • Fig.4(a) to derive the affine parameters of block B, E, and A, the VB0’and VB1’ are used instead of VB0 and VB1.
  • the VE0’, VE1’and VE2’ are used instead of VE0, VE1 and VE2.
  • the VA0’and are used instead of VA0 and VA2.
  • the VB1’and VB2’ are used instead of VB0 ,VB1 and VB2.
  • the VE0’, VE1’ and VE2’ are used instead of VE0, VE1 and VE2.
  • the VA0’ and VA2’ are used instead of VA0 and VA2.
  • other positions in the two row blocks and two column blocks can be used for affine parameter derivation. Without loss of generality, only the method in Fig.2(a) is described in the following.
  • the derived 3 control points affine MVP from block B can be modified as follow:
  • VB0’, VB1’, and VB2 can be replaced by the corresponding MVs of any other selected reference/neighboring PU
  • (posCurPU_X, posCurPU_Y) are the pixel position of the top-left sample of the current PU relative to the top-left sample of the picture
  • (posRefPU_X, posRefPU_Y) are the pixel position of the top-left sample of the reference/neighboring PU relative to the top-left sample of the picture
  • (posB0’_X, posB0’_Y) are the pixel position of the top-left sample of the B0 block relative to the top- left sample of the picture.
  • the derived MVs are (v0x, v0y) plus the position dependent offset MV.
  • the horizontal direction offset MV is ((v1x– v0x)*N/w, (v1y– v0y)*N/w) and the vertical direction offset MV is (–(v1y– v0y)*N/w, (v1x– v0x)*N/w).
  • the top-left, top-right, and the bottom-left MVs are v0, v1, and v2, the MVs of each pixel can be as follow.
  • the horizontal direction offset MV is ((v1x– v0x)*N/w, (v1y– v0y)*N/w) and the vertical direction offset MV is ((v2x– v0x)*N/h, (v2y– v0y)*N/h).
  • the derived MV is (vx, vy) in (6).
  • w and h are the width and height of the affine code block.
  • the denominator can be decreased by N.
  • the equation (2) can be rewritten as follow.
  • the horizontal and vertical direction offset MVs for an MxM block.
  • M can be equal to 8.
  • the ((v1x– v0x)*N/w, (v1y– v0y)*N/w) and ((v2x– v0x)*N/h, (v2y– v0y)*N/h) are stored.
  • the affine parameter of the affine merge candidate can be also derived.
  • the top-left MV of the neighboring block can be also stored with the offset MVs.
  • the offset MV can be multiplied by a scale number.
  • the scale number can be predefined or set equal to CTU size.
  • CTU size For example, the ((v1x– v0x)*S/w, (v1y– v0y)*S/w) and ((v2x– v0x)*S/h, (v2y– v0y)*S/h) are stored.
  • the S can be equal to CTU_size or CTU_size/4.
  • the adaptive MV resolution was proposed to reduce the MVD overhead.
  • An AMVR_flag is signaled for a CU or a PU. If the AMVR_flag is true, the MVD is in integer pixel resolution. For affine merge mode, the derived motion vectors for all control points can be in fractional resolution. No AMVR_flag will be signaled.
  • M is the number of control points for the affine AMVP coded PU
  • the number M can be 0, 1, 2, 3, 4.
  • affine prediction it is proposed to combine the affine prediction with AMVR. If a PU or a CU is coded in affine AMVP mode and the AMVR_flag is true, all the MVDs of control points are in integer pixel resolution. All the MVPs of the control points (if associated with a MVD) can be also rounded to integer pixel resolution. For those control points without an associated MVD (infer the MVD to be zero, a predicted or derived MV is used directly), the predicted or derived MV can still be in fractional pixel resolution.
  • the MVD can be signaled before the AMVR_flag.
  • AMVR_flag For affine AMVP mode, if there is at least one non-zero MVD for the control point(s), then the resolution of the decoded MV(s) should be determined by using the AMVR_flag. If the MVDs for all the control points are zero, the MVP of all control points can remain in fractional pixel resolution. In this case, the AMVR_flag is not necessary to be signaled.
  • the affine inter mode is restricted to uni-prediction. For example, if affine_flag is true, the interDir can be only 0 or 1 (L0 uni-prediction or L1 uni-prediction). However, in the case of AMVR_flag is true, the MVD overhead is relatively small. So it is proposed to allow the bi-prediction for affine inter mode when AMVR_flag is true.
  • an embodiment of the present invention can be a circuit integrated into a video compression chip or program codes integrated into video compression software to perform the processing described herein.
  • An embodiment of the present invention may also be program codes to be executed on a Digital Signal Processor (DSP) to perform the processing described herein.
  • DSP Digital Signal Processor
  • the invention may also involve a number of functions to be performed by a computer processor, a digital signal processor, a microprocessor, or field programmable gate array (FPGA).
  • processors can be configured to perform particular tasks according to the invention, by executing machine-readable software code or firmware code that defines the particular methods embodied by the invention.
  • the software code or firmware codes may be developed in different programming languages and different format or style.
  • the software code may also be compiled for different target platform.
  • different code formats, styles and languages of software codes and other means of configuring code to perform the tasks in accordance with the invention will not depart from the spirit and scope of the invention.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)

Abstract

L'invention concerne des procédés de prédiction affine. D'abord, l'invention concerne des procédés de dérivation de MVP affine. L'invention concerne également des procédés de résolution adaptative et de prédiction affine.
PCT/CN2016/076360 2016-03-15 2016-03-15 Prédiction affine pour le codage vidéo WO2017156705A1 (fr)

Priority Applications (10)

Application Number Priority Date Filing Date Title
PCT/CN2016/076360 WO2017156705A1 (fr) 2016-03-15 2016-03-15 Prédiction affine pour le codage vidéo
EP17765801.0A EP3414900A4 (fr) 2016-03-15 2017-03-13 Procédé et appareil de codage vidéo avec compensation de mouvement affine
CN202110949285.3A CN113612994B (zh) 2016-03-15 2017-03-13 具有仿射运动补偿的视频编解码的方法
RU2018134794A RU2696551C1 (ru) 2016-03-15 2017-03-13 Способ и устройство для кодирования видео с компенсацией аффинного движения
CN201780017425.5A CN108781284B (zh) 2016-03-15 2017-03-13 具有仿射运动补偿的视频编解码的方法及装置
SG11201806865YA SG11201806865YA (en) 2016-03-15 2017-03-13 Method and apparatus of video coding with affine motion compensation
PCT/CN2017/076420 WO2017157259A1 (fr) 2016-03-15 2017-03-13 Procédé et appareil de codage vidéo avec compensation de mouvement affine
US16/083,662 US10638152B2 (en) 2016-03-15 2017-03-13 Method and apparatus of video coding with affine motion compensation
TW106108289A TWI617185B (zh) 2016-03-15 2017-03-14 具有仿射運動補償的視訊編碼的方法以及裝置
US16/827,881 US11375226B2 (en) 2016-03-15 2020-03-24 Method and apparatus of video coding with affine motion compensation

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WO2019203504A1 (fr) * 2018-04-15 2019-10-24 엘지전자 주식회사 Procédé et appareil pour réduire un espace de stockage pour des informations de mouvement dans un système de traitement vidéo
CN110719483A (zh) * 2018-07-13 2020-01-21 腾讯美国有限责任公司 视频解码方法和装置、计算机设备及存储介质
CN110730351A (zh) * 2018-07-17 2020-01-24 腾讯美国有限责任公司 视频解码的方法和装置、存储介质
WO2020032609A1 (fr) * 2018-08-09 2020-02-13 엘지전자 주식회사 Procédé et dispositif de décodage d'image basé sur une prédiction de mouvement affine à l'aide d'une liste de candidats de fusion affine dans un système de codage d'image
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