WO2017149580A1 - Dispositif à semi-conducteur au carbure de silicium et procédé de fabrication de dispositif à semi-conducteur au carbure de silicium - Google Patents

Dispositif à semi-conducteur au carbure de silicium et procédé de fabrication de dispositif à semi-conducteur au carbure de silicium Download PDF

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WO2017149580A1
WO2017149580A1 PCT/JP2016/055967 JP2016055967W WO2017149580A1 WO 2017149580 A1 WO2017149580 A1 WO 2017149580A1 JP 2016055967 W JP2016055967 W JP 2016055967W WO 2017149580 A1 WO2017149580 A1 WO 2017149580A1
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silicon carbide
semiconductor device
type
carbide semiconductor
region
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PCT/JP2016/055967
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English (en)
Japanese (ja)
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渊 卜
広行 吉元
島　明生
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株式会社日立製作所
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Priority to JP2018502857A priority Critical patent/JP6411695B2/ja
Priority to PCT/JP2016/055967 priority patent/WO2017149580A1/fr
Publication of WO2017149580A1 publication Critical patent/WO2017149580A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/744—Gate-turn-off devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/868—PIN diodes

Definitions

  • the present invention relates to a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device, and more particularly, to a silicon carbide bipolar element having a mesa structure and a method for manufacturing the same.
  • a power converter having excellent energy efficiency and low CO 2 emission has become important.
  • Many of the power conversion devices are configured by a power module in which an insulated gate bipolar transistor (IGBT) as a switching element and a PiN diode (PND) as a rectifying element are connected in parallel. For this reason, the loss reduction of the semiconductor element is directly linked to energy saving of the power converter.
  • IGBT insulated gate bipolar transistor
  • PND PiN diode
  • SiC 4H type silicon carbide
  • the current silicon carbide bipolar device has a problem of deterioration of energization in which the voltage increases when current flows in the forward direction.
  • BPD Basal Plane Dislocation
  • the BPD expands due to recombination of electrons and holes. This is because of the increase.
  • BPD is likely to occur on the mesa wall in the mesa processing process of the bipolar element.
  • an n-type layer is formed by forming a p-type layer or a high-resistance amorphous layer on a mesa wall portion or a mesa peripheral portion.
  • An energization deterioration preventing layer is provided that spatially separates the pn junction interface between the drift layer and the p-type charge injection layer and the surface of the mesa wall portion or the mesa peripheral portion.
  • an object of the present invention is to provide an excellent effect of preventing current deterioration in a silicon carbide bipolar device having a mesa structure.
  • the first region where the concentration of the p-type impurity is higher than the concentration of the n-type impurity formed inside the mesa structure, and the n-type impurity concentration than the concentration of the p-type impurity along the side surface of the mesa structure.
  • FIG. 1 is a top view of an n-type SiC-PND according to Embodiment 1 of the present invention. It is sectional drawing of n-type SiC-PND which concerns on Example 1 of this invention.
  • FIG. 6 is a cross sectional view of a process for manufacturing the silicon carbide semiconductor device of Example 1;
  • FIG. 6 is a cross sectional view of a process for manufacturing the silicon carbide semiconductor device of Example 1;
  • FIG. 6 is a cross sectional view of a process for manufacturing the silicon carbide semiconductor device of Example 1;
  • FIG. 6 is a cross sectional view of a process for manufacturing the silicon carbide semiconductor device of Example 1;
  • FIG. 6 is a cross sectional view of a silicon carbide semiconductor device of Example 2.
  • FIG. 6 is a cross sectional view of a silicon carbide semiconductor device of Example 3.
  • FIG. It is a top view of n-type SiC-PND according to Example 4 of the present invention. It is a top view of n-type SiC-PND according to Example 4 of the present invention.
  • FIG. 7 is a main part sectional view of a silicon carbide semiconductor device of Example 4;
  • FIG. 7 is a main part sectional view of a silicon carbide semiconductor device of Example 4;
  • It is sectional drawing of GTO which concerns on Example 5 of this invention. It is a figure which shows the example of application of the silicon carbide semiconductor device of this invention.
  • SiC-PND silicon carbide PiN diode
  • SiC-GTO silicon carbide gate turn-off thyristor
  • FIG. 1 is a top view of the n-type SiC-PND 100 of this embodiment.
  • FIG. 2 is a cross-sectional view of the SiC-PND 100 of the present embodiment at a location corresponding to the broken line A-A ′ in FIG. 1.
  • the n-type SiC-PND 100 of this embodiment is a silicon carbide semiconductor layer having an impurity concentration lower than that of the n-type bulk 4H-SiC substrate 101 on the n-type bulk 4H-SiC substrate 101.
  • An n-type drift layer 102 is formed.
  • a hole injection layer 103 which is a silicon carbide layer is formed on the n-type drift layer 102.
  • the n-type bulk 4H—SiC substrate 101 is an n-type single crystal SiC layer containing nitrogen (N), phosphorus (P) or the like as an impurity, and can be manufactured by, for example, a sublimation method.
  • the impurity concentration of the n-type bulk 4H—SiC substrate 101 is, for example, not less than 1 ⁇ 10 16 cm ⁇ 3 and less than 2 ⁇ 10 20 cm ⁇ 3 .
  • the thickness of the n-type bulk 4H—SiC substrate 101 is, for example, not less than 100 ⁇ m and less than 1000 ⁇ m.
  • the n-type drift layer 102 can be formed by, for example, an epitaxial growth method.
  • the concentration of impurities such as nitrogen (N) and phosphorus (P) contained in the n-type drift layer 102 is, for example, 1 ⁇ 10 13 cm ⁇ 3 or more and less than 1 ⁇ 10 18 cm ⁇ 3 .
  • the hole injection layer 103 is a silicon carbide layer containing p-type impurities such as aluminum (Al) and boron (B).
  • the concentration of the p-type impurity in the hole injection layer 103 is, for example, 1 ⁇ 10 17 cm ⁇ 3 or more and less than 1 ⁇ 10 21 cm ⁇ 3 .
  • the concentration of the p-type impurity is higher than the concentration of the n-type impurity.
  • the hole injection layer 103 is a p-type semiconductor layer and is in pn junction with the n-type drift layer 102.
  • the hole injection layer 103 can be formed by, for example, an epitaxial growth method.
  • a p-type impurity can be selectively introduced into the hole injection layer 103.
  • the hole injection layer 103 can also be formed by ion implantation of p-type impurities into the n-type semiconductor layer.
  • the thickness of the hole injection layer 103 is, for example, not less than 0.5 ⁇ m and less than 30 ⁇ m.
  • the hole injection layer 103 and the energization path from the hole injection layer 103 to the n-type drift layer 102 are provided in the mesa structure.
  • a p-type electric field relaxation layer 104 is formed around the mesa structure including under the side surface of the mesa structure.
  • the p-type field relaxation layer 104 is in contact with the hole injection layer 103.
  • the p-type field relaxation layer 104 can be formed by implanting p-type impurity ions, and the impurity concentration is, for example, 1 ⁇ 10 14 cm ⁇ 3 or more and less than 5 ⁇ 10 18 cm ⁇ 3 .
  • the side portion of the mesa structure is referred to as a mesa wall portion 108, and a partial region on the surface of the p-type field relaxation layer 104 from the lower end portion of the mesa wall portion 108 is referred to as a mesa lower end peripheral portion 109.
  • a part of the surface of the hole injection region 103 from the upper end of the region is called a mesa upper end peripheral portion 111.
  • the width W n1 of the mesa lower end peripheral portion 109 is not less than 1 nm and less than 100 ⁇ m, and can be set to 10 ⁇ m, for example.
  • the width W n2 of the mesa upper end peripheral portion 111 is 1 nm or more and less than 100 ⁇ m, and can be set to 5 ⁇ m, for example.
  • the n-type SiC-PND 100 includes an n-type current prevention layer 110 along the mesa upper end peripheral portion 111, the mesa wall portion 108, and the mesa lower end peripheral portion 109.
  • the n-type impurity concentration is higher than the p-type impurity concentration.
  • the thickness T n of the n-type current prevention layer 110 is not less than 1 nm and less than 2 ⁇ m, and can be, for example, 100 nm.
  • the n-type current blocking layer 110 can be formed by counter doping with n-type impurities.
  • the n-type current prevention layer 110 is an n-type semiconductor layer, it is pn-junction with the hole injection layer 103 and the p-type field relaxation layer 104 of the p-type semiconductor layer. Since the n-type current prevention layer 110 is formed along the mesa upper end peripheral part 111, the mesa wall part 108, and the mesa lower end peripheral part 109, generation of holes can be prevented in the entire periphery of the mesa wall part 108. .
  • an anode electrode 106 is provided in contact with the hole injection layer 103.
  • a cathode electrode 107 is provided on the back surface of the n-type bulk 4H—SiC substrate 101.
  • a passivation film 105 is provided on the surface of the n-type SiC-PND 100 except where the anode electrode 106 is provided.
  • the passivation film 105 can be formed of SiO 2 or silicon nitride.
  • FIG. 3A An n-type silicon carbide layer that becomes an n-type drift layer 102 having a lower impurity concentration than the n-type bulk 4H—SiC substrate 101 is formed on the n-type bulk 4H—SiC substrate 101.
  • a silicon carbide wafer is prepared, and a p-type silicon carbide layer to be the hole injection layer 103 is formed on the n-type semiconductor layer.
  • FIG. 3B a mesa structure is formed on the prepared silicon carbide wafer by removing the p-type silicon carbide layer and the n-type silicon carbide layer in the surrounding portions by dry etching.
  • the p-type electric field relaxation layer 104 is formed to extend below the hole injection layer 103 so as to be in contact with the hole injection layer 103.
  • nitrogen as an n-type impurity is ionized by a mask process on the mesa wall portion 108 and the peripheral portion of the mesa upper end peripheral portion 111 and the mesa lower end peripheral portion 109.
  • an n-type current prevention layer 110 that is an n-type semiconductor layer is formed.
  • the p-type electric field relaxation layer 104 is formed to extend below the hole injection layer 103 so as to be in contact with the hole injection layer 103, ion implantation is also performed from the mesa wall portion 108.
  • a portion having a p-type impurity concentration that is the sum of the p-type impurity concentration of the hole injection layer 103 and the p-type impurity concentration of the p-type field relaxation layer 104 is formed.
  • an n-type impurity having a concentration higher than the sum of the p-type impurity concentration of the hole injection layer 103 and the p-type impurity concentration of the p-type field relaxation layer 104 is added. inject.
  • the n-type impurity concentration of the n-type current blocking layer 110 is higher than the n-type impurity concentration of the n-type drift layer 102.
  • the anode electrode 106, the passivation film 105, and the cathode electrode 107 are formed to obtain the structure shown in FIG.
  • FIG. 4 The effect of the present invention is shown in FIG.
  • the time-dependent change of the forward voltage due to the energization of the SiC-PND with the n-type current prevention layer 110 is shown by a solid line, and as a comparative example, the energization of the SiC-PND without the n-type current prevention layer 110 is shown.
  • the change over time in the forward voltage is shown by broken lines. From FIG.
  • the forward voltage increases by energization, whereas when the n-type current prevention layer 110 is provided, the mesa wall portion In the vicinity of 108, no holes are generated due to the n-type current blocking layer 110, so that the expansion of the BPD is suppressed and the forward voltage hardly increases.
  • the present invention it is possible to obtain an excellent effect of preventing energization deterioration and to provide a highly reliable silicon carbide semiconductor device.
  • FIG. 5 shows a semiconductor device of this example.
  • the difference from the n-type SiC-PND 100 of the first embodiment of the semiconductor device shown in FIG. 5 is that a p-type resistance reduction layer 501 is formed under the anode electrode 106.
  • the impurity concentration of the p-type resistance reduction layer 501 is higher than the impurity concentration of the hole injection layer 103, and is, for example, 1 ⁇ 10 17 cm ⁇ 3 or more and less than 1 ⁇ 10 22 cm ⁇ 3 .
  • the p-type resistance reduction layer 501 can be formed by ion implantation of, for example, aluminum as a p-type impurity.
  • the outer peripheral portion of the p-type resistance reduction layer 501 may overlap with the n-type current prevention layer 110, but may be separated. By forming the p-type resistance reduction layer 501 having a high concentration of p-type impurities, the contact resistance of the anode electrode 106 can be reduced.
  • FIG. 6 shows a semiconductor device of this example.
  • the difference from the n-type SiC-PND 100 of the first embodiment of the semiconductor device shown in FIG. 6 is that an n-type BPD reduction layer 601 is formed between the n-type bulk 4H-SiC substrate 101 and the n-type drift layer 102. It is a point.
  • the thickness of the n-type BPD reduction layer 601 is, for example, not less than 0.5 ⁇ m and less than 50 ⁇ m, and the impurity concentration is, for example, not less than 1 ⁇ 10 15 cm ⁇ 3 and less than 1 ⁇ 10 20 cm ⁇ 3 .
  • n-type BPD reduction layer 601 a part of the BPD existing in the n-type bulk substrate 1 is changed to TED (Threading Edge Dislocation), and the BPD in the n-type drift layer 102 and the hole injection layer 103 is greatly reduced. can do.
  • 7A and 7B are top views of the silicon carbide semiconductor device of this example.
  • FIG. 7A shows an example of a FLR (Field Limiting Ring) structure.
  • FIG. 8A shows a cross-sectional view of the main part at a location corresponding to the broken line B-B ′ in FIG.
  • a p-type semiconductor region 701a, a p-type semiconductor region 701b, and a p-type semiconductor region 701c are provided in a ring shape outside the p-type field relaxation layer 104, and an FLR structure is formed. Is formed. Since the p-type electric field relaxation layer 104 is surrounded by the FLR structure, the electric field can be more effectively relaxed.
  • FIG. 7B is an example of a JTE (Junction Termination Extension) structure.
  • FIG. 8B is a cross-sectional view of the main part at a location corresponding to the broken line C-C ′ in FIG.
  • a p-type semiconductor region 701d having a lower p-type impurity concentration than the p-type field relaxation layer 104
  • a p-type semiconductor region 701d having a lower p-type impurity concentration than the p-type field relaxation layer 104
  • a p-type semiconductor region 701e having a low impurity concentration and a p-type semiconductor region 701f having a lower p-type impurity concentration than the p-type semiconductor region 701d are provided, and a JTE structure is formed. Since the p-type electric field relaxation layer 104 is connected to the JTE structure, the electric field can be more effectively relaxed.
  • FIG. 9 shows a cross-sectional structure of the SiC-GTO of this example.
  • a p-type field stop layer 1001 is formed on an n-type bulk 4H-SiC substrate 101.
  • a p-type drift layer 1002 is formed on the p-type field stop layer 1001.
  • An n-type conductive layer 1003 is formed on the p-type drift layer 1002.
  • a hole injection layer 103 is formed on the n-type conductive layer 1003.
  • An n-type conductive layer 1004 is formed on the outer periphery of the mesa structure of the n-type conductive layer 1003.
  • a gate electrode 1005 is formed on the n-type conductive layer 1004.
  • the n-type bulk 4H—SiC substrate 101 is an n-type single crystal SiC layer containing nitrogen (N), phosphorus (P), or the like formed by, for example, a sublimation method.
  • the thickness of the n-type bulk 4H—SiC substrate 101 is, for example, not less than 100 ⁇ m and less than 1000 ⁇ m.
  • the impurity concentration of the n-type bulk 4H—SiC substrate 101 is, for example, not less than 1 ⁇ 10 16 cm ⁇ 3 and less than 2 ⁇ 10 20 cm ⁇ 3 .
  • the p-type field stop layer 1001 is a layer containing a p-type impurity such as aluminum (Al) or boron (B) formed by an epitaxial growth method, for example.
  • the concentration of the p-type impurity in the p-type field stop layer 1001 is, for example, 1 ⁇ 10 15 cm ⁇ 3 or more and less than 1 ⁇ 10 19 cm ⁇ 3 .
  • the p-type drift layer 1002 can be formed by, for example, an epitaxial growth method.
  • the concentration of the p-type impurity in the p-type drift layer 1002 is, for example, 1 ⁇ 10 12 cm ⁇ 3 or more and less than 1 ⁇ 10 18 cm ⁇ 3 .
  • the n-type conductive layer 1003 can be formed by, for example, an epitaxial growth method.
  • the n-type impurity concentration of the n-type conductive layer 1003 is, for example, not less than 1 ⁇ 10 15 cm ⁇ 3 and less than 1 ⁇ 10 19 cm ⁇ 3 .
  • the hole injection layer 103 can be formed by, for example, an epitaxial growth method.
  • the thickness of the hole injection layer 103 is, for example, 0.5 ⁇ m or more and less than 30 ⁇ m, and the impurity concentration is, for example, 1 ⁇ 10 17 cm ⁇ 3 or more and less than 1 ⁇ 10 21 cm ⁇ 3 .
  • the n-type conductive layer 1004 can be formed by ion implantation of n-type impurities, for example.
  • the energization path from the hole injection layer 103 to the n-type conductive layer 1003 is inside the mesa structure.
  • an anode electrode 106 is provided in contact with the hole injection layer 103.
  • a cathode electrode 107 is provided on the back surface of the n-type bulk 4H—SiC substrate 101.
  • an n-type current prevention layer 110 is provided along the mesa upper end peripheral portion 111, the mesa wall portion 108, and the mesa lower end peripheral portion 109.
  • the n-type impurity concentration is higher than the p-type impurity concentration.
  • the thickness of the n-type current prevention layer 110 is not less than 1 nm and less than 2 ⁇ m, and can be, for example, 100 nm.
  • the n-type current blocking layer 110 can be formed by counter doping with n-type impurities.
  • FIG. 10 shows an application example of the silicon carbide semiconductor device shown in the first to fourth embodiments.
  • the power conversion device of this embodiment can be used for, for example, a railway vehicle.
  • FIG. 10 is a block diagram showing an example of a three-phase motor system applied to a railway vehicle. Electric power is supplied to the railway vehicle from the overhead line RT via the panda graph PG.
  • the high-voltage AC voltage of the overhead line RT is, for example, 25 kV or 15 kV.
  • This high-voltage AC voltage is stepped down to an AC voltage of, for example, 3.3 kV by the insulated main transformer MTR.
  • the stepped-down AC voltage is forward converted to a DC voltage of 3.3 kV by the converter AC / DC.
  • the DC voltage is converted into an AC voltage by the inverter DC / AC via the capacitor CL, and a desired three-phase AC voltage is output to the three-phase motor M3, thereby driving the three-phase motor M3.
  • Reference sign WHL indicates a wheel.
  • the n-type SiC-PND 100 of Examples 1 to 4 can be applied to the free-wheeling diode FRD connected in parallel to the IGBT of the converter AC / DC constituting the three-phase motor system of the railway vehicle in FIG.
  • the leakage current is reduced, so that it is possible to provide a highly efficient power converter with low loss.
  • the floor of the railway vehicle can be reduced by downsizing the underfloor parts including the three-phase motor system.
  • a storage battery SB can be newly installed in a part of the railway vehicle. Therefore, when the vehicle is decelerated, power is transferred to the overhead line RT via the wheels WHL. In addition to returning, it is also possible to store power in the storage battery SB. As a result, the regeneration efficiency of the railway vehicle can be improved. In other words, the life cycle cost of the railway system can be reduced.
  • n-type SiC-PND 100: n-type SiC-PND, 101: n-type bulk 4H-SiC substrate, 102: n-type drift layer, 103: hole injection layer, 104: p-type field relaxation layer, 105: passivation film, 106: anode electrode, 107 : Cathode electrode, 108: mesa wall portion, 109 mesa lower end peripheral portion, 110: n-type current prevention layer, 111: mesa upper end peripheral portion.

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  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

Le but de la présente invention est d'assurer d'excellents effets de prévention de détérioration de la conduction dans un élément bipolaire au carbure de silicium ayant une structure mésa. La présente invention résout le problème susmentionné par formation : d'une première zone dans laquelle la concentration d'une impureté du type p est supérieure à celle d'une impureté du type n, ladite première zone étant formée à l'intérieur d'une structure mésa ; et d'une seconde zone dans laquelle la concentration de l'impureté du type n est supérieure à celle de l'impureté du type p, ladite seconde zone étant située le long des surfaces latérales de la structure mésa.
PCT/JP2016/055967 2016-02-29 2016-02-29 Dispositif à semi-conducteur au carbure de silicium et procédé de fabrication de dispositif à semi-conducteur au carbure de silicium WO2017149580A1 (fr)

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JP2018502857A JP6411695B2 (ja) 2016-02-29 2016-02-29 炭化珪素半導体装置および炭化珪素半導体装置の製造方法
PCT/JP2016/055967 WO2017149580A1 (fr) 2016-02-29 2016-02-29 Dispositif à semi-conducteur au carbure de silicium et procédé de fabrication de dispositif à semi-conducteur au carbure de silicium

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002535840A (ja) * 1999-01-12 2002-10-22 オイペツク オイロペーイツシエ ゲゼルシヤフト フユール ライスツングスハルプライター エムベーハー ウント コンパニイ コマンデイートゲゼルシヤフト メサ形縁端部を備えるパワー半導体素子
JP2007165604A (ja) * 2005-12-14 2007-06-28 Kansai Electric Power Co Inc:The 炭化珪素バイポーラ型半導体装置
JP2014045167A (ja) * 2012-07-31 2014-03-13 Toshiba Corp 半導体装置及びその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002535840A (ja) * 1999-01-12 2002-10-22 オイペツク オイロペーイツシエ ゲゼルシヤフト フユール ライスツングスハルプライター エムベーハー ウント コンパニイ コマンデイートゲゼルシヤフト メサ形縁端部を備えるパワー半導体素子
JP2007165604A (ja) * 2005-12-14 2007-06-28 Kansai Electric Power Co Inc:The 炭化珪素バイポーラ型半導体装置
JP2014045167A (ja) * 2012-07-31 2014-03-13 Toshiba Corp 半導体装置及びその製造方法

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