WO2017126641A1 - Bonded body, power module substrate, bonded body manufacturing method, and power module substrate manufacturing method - Google Patents

Bonded body, power module substrate, bonded body manufacturing method, and power module substrate manufacturing method Download PDF

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Publication number
WO2017126641A1
WO2017126641A1 PCT/JP2017/001840 JP2017001840W WO2017126641A1 WO 2017126641 A1 WO2017126641 A1 WO 2017126641A1 JP 2017001840 W JP2017001840 W JP 2017001840W WO 2017126641 A1 WO2017126641 A1 WO 2017126641A1
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Prior art keywords
layer
intermetallic compound
ceramic substrate
compound layer
power module
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PCT/JP2017/001840
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French (fr)
Japanese (ja)
Inventor
伸幸 寺▲崎▼
長友　義幸
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三菱マテリアル株式会社
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Priority claimed from JP2017000381A external-priority patent/JP6819299B2/en
Application filed by 三菱マテリアル株式会社 filed Critical 三菱マテリアル株式会社
Priority to US16/070,332 priority Critical patent/US11062974B2/en
Priority to CN201780015160.5A priority patent/CN109075135B/en
Priority to EP17741518.9A priority patent/EP3407380B1/en
Priority to KR1020187023493A priority patent/KR102419486B1/en
Publication of WO2017126641A1 publication Critical patent/WO2017126641A1/en

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Definitions

  • the present invention relates to a joined body in which a ceramic member and a Cu member are joined, and a power module substrate in which a Cu plate made of Cu or a Cu alloy is joined to a ceramic substrate.
  • Semiconductor devices such as LEDs and power modules have a structure in which a semiconductor element is bonded on a circuit layer made of a conductive material.
  • a power semiconductor element for high power control used for controlling an electric vehicle such as wind power generation or an electric vehicle
  • a large amount of heat is generated. Therefore, as a substrate on which the power semiconductor element is mounted, for example, AlN (aluminum nitride) 2.
  • a power module substrate in which a metal plate having excellent conductivity is bonded as a circuit layer to one surface of a ceramic substrate made of has been widely used.
  • a metal plate may be joined as a metal layer to the other surface of the ceramic substrate.
  • the power module substrate shown in Patent Document 1 has a structure in which a circuit layer is formed by bonding a Cu plate (Cu member) to one surface of a ceramic substrate (ceramic member).
  • a Cu plate is disposed on one surface of a ceramic substrate with a Cu—Mg—Ti brazing material interposed therebetween, and heat treatment is performed to bond the Cu plate.
  • an intermetallic compound containing Cu, Mg, or Ti is present in the vicinity of the ceramic substrate. It is formed.
  • the intermetallic compound formed in the vicinity of the ceramic substrate is hard, the thermal stress generated in the ceramic substrate when a thermal cycle is applied to the power module substrate increases, and cracks are likely to occur in the ceramic substrate. there were.
  • the bonding rate between the ceramic substrate and the circuit layer may be reduced, and it may not be possible to bond well. there were.
  • Patent Documents 2 and 3 propose a power module substrate in which a ceramic substrate and a circuit layer are bonded using a Cu—P—Sn brazing material and a Ti material.
  • a Cu—Sn layer is formed on the ceramic substrate side, and a hard intermetallic compound layer is not provided in the vicinity of the ceramic substrate. In this case, thermal stress generated in the ceramic substrate can be reduced, and cracks can be prevented from occurring in the ceramic substrate.
  • the heat generation temperature of the semiconductor elements mounted on the power module substrate tends to increase, and the power module substrate is required to dissipate heat more efficiently than before.
  • a Ti layer is formed between the ceramic substrate and the circuit layer made of Cu or Cu alloy, and the thickness of the Ti layer is 1 ⁇ m or more and 15 ⁇ m. It is formed relatively thick as follows. For this reason, the thermal resistance in the stacking direction is increased, and there is a possibility that heat cannot be efficiently radiated.
  • a Cu—Sn layer and an intermetallic compound layer containing P and Ti are formed between the ceramic substrate and the circuit layer made of Cu or Cu alloy.
  • the use environment temperature is high, cracks are generated starting from the intermetallic compound layer containing P and Ti, which may result in insufficient bonding.
  • the present invention has been made in view of the above-described circumstances, and is a bonded body in which a ceramic member and a Cu member are bonded satisfactorily and the heat resistance in the stacking direction is low and can be efficiently radiated.
  • An object of the present invention is to provide a power module substrate, a method for manufacturing the joined body, and a method for manufacturing the power module substrate.
  • a joined body is a joined body of a ceramic member made of ceramics and a Cu member made of Cu or a Cu alloy, and the ceramic member and the Cu member A Cu—Sn layer in which Sn is solid-solved in Cu, a first intermetallic compound layer containing Cu and Ti, located on the Cu member side, and located on the ceramic member side, A second intermetallic compound layer containing P and Ti is formed between the first intermetallic compound layer and the Cu—Sn layer.
  • the first intermetallic compound layer containing Cu and Ti is formed on the Cu member side, so the Cu member and the second intermetallic compound layer are Can be reliably bonded, and the bonding strength between the Cu member and the ceramic member can be ensured even when the use environment temperature increases. Further, since the Ti layer is not formed or is very thin, the thermal resistance in the stacking direction can be kept low, and heat can be efficiently radiated.
  • a Ti layer is formed between the first intermetallic compound layer and the second intermetallic compound layer, and the thickness of the Ti layer is 0. It may be 5 ⁇ m or less.
  • a Ti layer is formed between the first intermetallic compound layer and the second intermetallic compound layer, and since the thickness of the Ti layer is 0.5 ⁇ m or less, the stacking direction The heat resistance in can be kept low, and heat can be radiated efficiently.
  • the thickness of the first intermetallic compound layer is in a range of 0.2 ⁇ m to 6 ⁇ m.
  • the thickness of the first intermetallic compound layer containing Cu and Ti is 0.2 ⁇ m or more, the bonding strength between the Cu member and the ceramic member can be reliably improved.
  • the thickness of the first intermetallic compound layer is 6 ⁇ m or less, the occurrence of cracks in the first intermetallic compound layer can be suppressed.
  • the thickness of the second intermetallic compound layer is in the range of 0.5 ⁇ m to 4 ⁇ m.
  • the thickness of the 2nd intermetallic compound layer containing P and Ti is 0.5 micrometer or more, the joint strength of Cu member and a ceramic member can be improved reliably.
  • the thickness of the second intermetallic compound layer is 4 ⁇ m or less, occurrence of cracks in the second intermetallic compound layer can be suppressed.
  • a power module substrate includes the above-described joined body, the ceramic substrate including the ceramic member, and the circuit layer including the Cu member formed on one surface of the ceramic substrate.
  • a first intermetallic compound layer, and a second intermetallic compound layer that is located between the first intermetallic compound layer and the Cu-Sn layer and contains P and Ti is formed. It is a feature.
  • the circuit layer and the second intermetallic compound layer are Bonding can be ensured, and the bonding strength between the circuit layer and the ceramic substrate can be ensured even when the operating environment temperature increases.
  • the Ti layer is not formed, or even if the Ti layer is formed, its thickness is as thin as 0.5 ⁇ m or less, so the thermal resistance in the stacking direction can be kept low, and it is mounted on the circuit layer. It is possible to efficiently dissipate heat from the semiconductor element.
  • a metal layer made of Al or an Al alloy may be formed on the other surface of the ceramic substrate.
  • the metal layer made of Al or Al alloy having relatively small deformation resistance is formed on the other surface of the ceramic substrate, the metal layer is preferentially applied when stress is applied to the power module substrate. The stress acting on the ceramic substrate can be reduced and cracking of the ceramic substrate can be suppressed.
  • a power module substrate includes the above-described joined body, the ceramic substrate including the ceramic member, a circuit layer formed on one surface of the ceramic substrate, and the ceramic substrate. And a metal layer made of the Cu member formed on the other surface, and located at the ceramic substrate side at a bonding interface between the ceramic substrate and the metal layer, and Sn is a solid solution in Cu A Sn layer, a first intermetallic compound layer that is located on the metal layer side and includes Cu and Ti, and is located between the first intermetallic compound layer and the Cu-Sn layer, and includes P and Ti. And a second intermetallic compound layer to be contained.
  • the metal layer and the second intermetallic compound layer are Bonding can be ensured, and the bonding strength between the metal layer and the ceramic substrate can be ensured even when the use environment temperature increases.
  • the Ti layer is not formed, or even if the Ti layer is formed, its thickness is as thin as 0.5 ⁇ m or less, so the thermal resistance in the stacking direction can be kept low, and it is mounted on the circuit layer. It is possible to efficiently dissipate heat from the semiconductor element.
  • a method of manufacturing a joined body according to one aspect of the present invention is a method of manufacturing a joined body of a ceramic member made of ceramic and a Cu member made of Cu or a Cu alloy, and includes a Cu—P—Sn-based brazing material and a Ti material.
  • Second heat treatment step for forming a compound layer It is characterized in that it comprises a.
  • the Cu—P—Sn brazing material is heated at a temperature lower than the melting start temperature of the Cu—P—Sn brazing material to cause the Cu member and the Ti material to react with each other. Since the first heat treatment step for forming the first intermetallic compound layer containing Ti and Ti is provided, the first intermetallic compound layer is surely formed, and the Cu member and the Ti material are reliably bonded. Can do. In this first heat treatment step, a part of the Ti material is left.
  • the Cu—P—Sn brazing material is heated at a temperature equal to or higher than the melting start temperature, and a Cu—Sn layer in which Sn is dissolved in Cu, and the first intermetallic compound Since the second heat treatment step of forming a second intermetallic compound layer containing P and Ti is provided between the layer and the Cu—Sn layer, the Ti of the Ti material is converted into Cu—P—. By reacting with the Sn-based brazing material, the second intermetallic compound layer can be formed, and the Cu member and the ceramic member can be reliably bonded. In the second heat treatment step, all of the Ti material may be reacted, or a part of the Ti material may be left to form a Ti layer having a thickness of 0.5 ⁇ m or less.
  • the heating temperature in the first heat treatment step is in a range of 580 ° C. or more and 670 ° C. or less, and the heating time is 30 minutes or more and 240 minutes or less. It is preferable to be within the range. In this case, since the heating temperature is 580 ° C. or more and the heating time is 30 minutes or more, the first intermetallic compound layer can be reliably formed. On the other hand, since the heating temperature is 670 ° C. or less and the heating time is 240 minutes or less, the first intermetallic compound layer is not formed thicker than necessary, and cracks occur in the first intermetallic compound layer. Can be suppressed.
  • the manufacturing method of the joined body which is 1 aspect of this invention is a manufacturing method of the joined body of the ceramic member which consists of ceramics, and Cu member which consists of Cu or Cu alloy, Comprising: Said Cu member and said Ti material A CuTi diffusion step in which Cu and Ti are diffused by heating in a laminated state to form a first intermetallic compound layer containing Cu and Ti between the Cu member and the Ti material; and a Cu-P-Sn system A laminating step of laminating the ceramic member, the Ti material on which the first intermetallic compound layer is formed, and the Cu member via a brazing material, and starting melting of the Cu—P—Sn based brazing material A second layer containing P and Ti, which is located between the Cu—Sn layer in which Sn is dissolved in Cu, the first intermetallic compound layer, and the Cu—Sn layer.
  • Heat treatment for forming an intermetallic compound layer Is characterized by comprising the steps, a.
  • the Cu member and the Ti material are heated in a stacked state to diffuse Cu and Ti, and Cu and Ti are contained between the Cu member and the Ti material. Since the CuTi diffusion step for forming the first intermetallic compound layer is provided, the first intermetallic compound layer can be reliably formed. In this CuTi diffusion step, a part of the Ti material is left. Further, in the CuTi diffusion process, since the Cu member and the Ti material are laminated and heated without laminating the brazing material, the heating conditions can be set relatively freely, and the first intermetallic compound layer is surely secured. And the thickness of the remaining Ti material can be adjusted with high accuracy.
  • the heating temperature in the CuTi diffusion step is in the range of 600 ° C. or more and 670 ° C. or less, and the heating time is in the range of 30 minutes or more and 360 minutes or less. It is preferable that In this case, since the heating temperature is 600 ° C. or more and the heating time is 30 minutes or more, the first intermetallic compound layer can be reliably formed. On the other hand, since the heating temperature is 670 ° C. or less and the heating time is 360 minutes or less, the first intermetallic compound layer is not formed thicker than necessary, and the first intermetallic compound layer is a starting point of cracking. Can be suppressed.
  • the load of the lamination direction may be in the range of 0.294 MPa or more and 1.96 MPa or less in the said CuTi diffusion process.
  • the load since the load is in the range of 0.294 MPa or more and 1.96 MPa or less, the first intermetallic compound layer can be reliably formed, and the bonding strength can be further increased.
  • it is 0.490 MPa or more and 1.47 MPa or less, and more preferably 1.18 MPa or more and 1.47 MPa or less.
  • a method for manufacturing a power module substrate according to an aspect of the present invention is a method for manufacturing a power module substrate in which a circuit layer made of Cu or a Cu alloy is disposed on one surface of a ceramic substrate, the ceramic substrate And the circuit layer are bonded by the above-described manufacturing method of the bonded body.
  • a Cu—Sn layer in which Sn is solid-solved in Cu at the bonding interface between the circuit layer and the ceramic substrate and Sn is dissolved in Cu, and the circuit layer side A first intermetallic compound layer containing Cu and Ti, a second intermetallic compound layer containing P and Ti, located between the first intermetallic compound layer and the Cu-Sn layer, , And the circuit layer and the ceramic substrate can be reliably bonded, and a power module substrate capable of efficiently dissipating heat with low thermal resistance in the stacking direction can be manufactured.
  • a circuit layer is disposed on one surface of the ceramic substrate, and a metal layer made of Cu or a Cu alloy is disposed on the other surface of the ceramic substrate.
  • a Cu—Sn layer in which Sn is solid-solved in Cu at the bonding interface between the metal layer and the ceramic substrate, and Sn is dissolved in Cu, and the circuit layer side A first intermetallic compound layer containing Cu and Ti, a second intermetallic compound layer containing P and Ti, located between the first intermetallic compound layer and the Cu-Sn layer, , And the metal layer and the ceramic substrate can be reliably bonded, and a power module substrate capable of efficiently dissipating heat with low thermal resistance in the stacking direction can be manufactured.
  • a circuit layer made of Cu or a Cu alloy is disposed on one surface of a ceramic substrate, and the other surface of the ceramic substrate is made of Al or an Al alloy.
  • a Cu—Sn layer in which Sn is solid-solved in Cu at the bonding interface between the circuit layer and the ceramic substrate and Sn is dissolved in Cu, and the circuit layer side A first intermetallic compound layer containing Cu and Ti, a second intermetallic compound layer containing P and Ti, located between the first intermetallic compound layer and the Cu-Sn layer, , And the circuit layer and the ceramic substrate can be reliably bonded, and a power module substrate capable of efficiently dissipating heat with low thermal resistance in the stacking direction can be manufactured.
  • circuit layer made of Cu or Cu alloy and the ceramic substrate can be bonded at a relatively low temperature, the circuit layer made of Cu or Cu alloy, the ceramic substrate, and the metal layer made of Al or Al alloy are bonded simultaneously. It is also possible to do.
  • the ceramic member and Cu member are joined favorably, and the joined body with low thermal resistance in the laminating direction, the power module substrate, the method for producing the joined body, and the production of the power module substrate A method can be provided.
  • the joined body according to the present embodiment is a power module substrate 10 in which a ceramic substrate 11 that is a ceramic member and a Cu plate 22 (circuit layer 12) that is a Cu member are joined.
  • the power module 1 provided with the board
  • the power module 1 includes a power module substrate 10 on which a circuit layer 12 is disposed, and a semiconductor element 3 bonded to one surface (upper surface in FIG. 1) of the circuit layer 12 via a bonding layer 2. ing.
  • the power module substrate 10 includes a ceramic substrate 11 and a circuit layer 12 disposed on one surface (the upper surface in FIG. 2) of the ceramic substrate 11.
  • the ceramic substrate 11 is made of ceramics such as AlN (aluminum nitride), Si 3 N 4 (silicon nitride), and Al 2 O 3 (alumina) having high insulating properties. In this embodiment, it is comprised with AlN (aluminum nitride) excellent in heat dissipation. Further, the thickness of the ceramic substrate 11 is set within a range of 0.2 to 1.5 mm, and in this embodiment is set to 0.635 mm.
  • the circuit layer 12 is formed by bonding a conductive metal plate of Cu or Cu alloy to one surface of the ceramic substrate 11.
  • the circuit layer 12 is formed by laminating a Cu—P—Sn brazing material 24 and a Cu plate 22 made of oxygen-free copper bonded with a Ti material 25 on one surface of the ceramic substrate 11. It is formed by processing and bonding a Cu plate 22 to the ceramic substrate 11 (see FIG. 5).
  • a Cu—P—Sn—Ni brazing material is used as the Cu—P—Sn brazing material 24.
  • the ceramic substrate 11 side has a structure in which Sn is diffused in Cu. Note that the thickness of the circuit layer 12 is set within a range of 0.1 mm or more and 1.0 mm or less, and is set to 0.3 mm in the present embodiment.
  • FIG. 3 shows a schematic explanatory diagram of the bonding interface between the ceramic substrate 11 and the circuit layer 12.
  • the bonding interface between the ceramic substrate 11 and the circuit layer 12 includes a Cu—Sn layer 14 located on the ceramic substrate 11 side, and a second layer containing Cu and Ti located on the circuit layer 12 side.
  • the Cu—Sn layer 14 is a layer in which Sn is dissolved in Cu.
  • the Cu—Sn layer 14 is a layer formed by incorporating P contained in the Cu—P—Sn brazing material 24 into the second intermetallic compound layer 17.
  • the first intermetallic compound layer 16 is a layer formed by mutual diffusion of Cu of the circuit layer 12 and Ti of the Ti material 25.
  • the diffusion of Cu and Ti is solid phase diffusion.
  • the first intermetallic compound layer 16 has one or more of a Cu 4 Ti phase, a Cu 3 Ti 2 phase, a Cu 4 Ti 3 phase, a CuTi phase, and a CuTi 2 phase.
  • the first intermetallic compound layer 16 has a Cu 4 Ti phase, a Cu 3 Ti 2 phase, a Cu 4 Ti 3 phase, a CuTi phase, and a CuTi 2 phase.
  • the thickness of the first intermetallic compound layer 16 is in the range of 0.2 ⁇ m to 6 ⁇ m.
  • the second intermetallic compound layer 17 is formed by combining P contained in the Cu—P—Sn brazing material 24 with Ti contained in the Ti material 25.
  • the second intermetallic compound layer 17 is composed of a P—Ni—Ti phase, a P—Ti phase, a Cu—Ni—Ti.
  • the phases are included, specifically, a P—Ni—Ti phase.
  • the thickness of the second intermetallic compound layer 17 is in the range of 0.5 ⁇ m to 4 ⁇ m.
  • the semiconductor element 3 is made of a semiconductor material such as Si.
  • the semiconductor element 3 and the circuit layer 12 are bonded via the bonding layer 2.
  • the bonding layer 2 is made of, for example, a Sn—Ag, Sn—In, or Sn—Ag—Cu solder material.
  • substrate 10 for power modules which concerns on this embodiment, and the power module 1 is demonstrated with reference to the flowchart of FIG. 4, and FIG.
  • the Cu plate 22 and the Ti material 25 to be the circuit layer 12 are laminated and placed in a vacuum heating furnace in a state of being pressurized in the lamination direction (pressure 1 to 35 kgf / cm 2 ).
  • the Cu plate 22 and the Ti material 25 are solid phase diffusion bonded to obtain a Cu—Ti bonded body 27. (CuTi diffusion step S01).
  • the thickness of the Ti material 25 is in the range of 0.4 ⁇ m to 5 ⁇ m.
  • the Ti material 25 is preferably formed by vapor deposition or sputtering when the thickness is 0.4 ⁇ m or more and less than 1 ⁇ m, and the foil material is preferably used when the thickness is 1 ⁇ m or more and 5 ⁇ m or less.
  • the lower limit of the thickness of the Ti material 25 is preferably 0.4 ⁇ m or more, and more preferably 0.5 ⁇ m or more.
  • the upper limit of the thickness of the Ti material 25 is preferably 1.5 ⁇ m or less, and more preferably 0.7 ⁇ m or less.
  • a Ti foil having a thickness of 1 ⁇ m and a purity of 99.8 mass% was used as the Ti material 25.
  • the Ti material 25 and the Cu plate 22 are joined by solid phase diffusion joining, and a laminated structure of the Cu plate 22 and the intermediate Ti layer 26 is formed.
  • an intermediate first intermetallic compound layer containing Cu and Ti is formed between the intermediate Ti layer 26 and the Cu plate 22.
  • the thickness of the intermediate Ti layer 26 is in the range of 0.1 ⁇ m to 3 ⁇ m. Note that the lower limit of the thickness of the intermediate Ti layer 26 is preferably 0.2 ⁇ m or more, and more preferably 0.4 ⁇ m or more.
  • the upper limit of the thickness of the intermediate Ti layer 26 is preferably 1.5 ⁇ m or less, and more preferably 1 ⁇ m or less. Furthermore, it is preferable that the thickness of the intermediate first intermetallic compound layer is 0.1 ⁇ m or more and 6 ⁇ m or less.
  • the pressure in the vacuum heating furnace is in the range of 10 ⁇ 6 Pa to 10 ⁇ 3 Pa
  • the heating temperature is in the range of 600 ° C. to 670 ° C.
  • the heating time is 30 minutes. It is set within the range of 360 minutes or less.
  • the intermediate first intermetallic compound layer can be sufficiently formed by setting the heating temperature to 600 ° C. or more and the heating time to 30 minutes or more. Moreover, it can suppress that an intermediate
  • the lower limit of the heating temperature is preferably 610 ° C. or higher, and more preferably 620 ° C. or higher.
  • the upper limit of the heating temperature is preferably 650 ° C. or less, more preferably 640 ° C. or less.
  • the lower limit of the heating time is preferably 15 minutes or more, and more preferably 60 minutes or more.
  • the upper limit of the heating time is preferably 120 minutes or less, and more preferably 90 minutes or less.
  • the pressure load in the stacking direction is 0.294 MPa to 1.96 MPa (3 kgf / cm 2 to 20 kgf / It is preferable to be within the range of cm 2 or less. More preferably, it is 0.490 MPa or more and 1.47 MPa or less, More preferably, it is good to set it in the range of 1.18 MPa or more and 1.47 MPa or less.
  • the Cu—P—Sn brazing material 24 and the Cu—Ti joined body 27 are sequentially laminated on one surface (the upper surface in FIG. 5) of the ceramic substrate 11 (lamination step S02).
  • the Cu—Ti joined body 27 is laminated so that the intermediate Ti layer 26 and the Cu—P—Sn brazing material 24 face each other.
  • the composition of the Cu—P—Sn brazing material 24 is Cu-7 mass% P-15 mass% Sn-10 mass% Ni, and its solidus temperature (melting start temperature) is 580 ° C. It is said that.
  • the Cu—P—Sn brazing material 24 is made of a foil material and has a thickness in the range of 5 ⁇ m to 150 ⁇ m.
  • the ceramic substrate 11, the Cu—P—Sn brazing material 24, and the Cu—Ti joined body 27 are charged in the stacking direction (pressure 1 to 35 kgf / cm 2 ) and placed in a vacuum heating furnace. And heated (heat treatment step S03).
  • the pressure in the vacuum heating furnace is in the range of 10 ⁇ 6 Pa to 10 ⁇ 3 Pa
  • the heating temperature is in the range of 600 ° C. to 700 ° C.
  • the heating time is set within a range of 15 minutes to 120 minutes.
  • the Cu—P—Sn brazing material 24 is melted to form a liquid phase, the intermediate Ti layer 26 is dissolved in this liquid phase, and the liquid phase is solidified.
  • the Cu plate 22 is joined.
  • P and Ni contained in the Cu—P—Sn-based brazing material 24 are combined with Ti in the intermediate Ti layer 26 to form the second intermetallic compound layer 17 and on the ceramic substrate 11 side.
  • a Cu—Sn layer 14 is formed.
  • the first intermetallic compound layer 16 is formed by leaving the intermediate first intermetallic compound layer.
  • the intermediate Ti layer 26 is a liquid phase of the Cu—P—Sn brazing material 24. All of it melts into the intermediate Ti layer 26 at the bonding interface between the ceramic substrate 11 and the circuit layer 12. As a result, the circuit layer 12 is formed on one surface of the ceramic substrate 11, and the power module substrate 10 according to this embodiment is manufactured.
  • the semiconductor element 3 is bonded to the upper surface of the circuit layer 12 of the power module substrate 10 via a solder material (semiconductor element bonding step S04). In this way, the power module 1 according to this embodiment is manufactured.
  • the bonding interface between the ceramic substrate 11 and the circuit layer 12 is located on the circuit layer 12 side and contains Cu and Ti. Since the first intermetallic compound layer 16 is formed, the circuit layer 12 and the second intermetallic compound layer 17 can be reliably bonded via the first intermetallic compound layer 16. Therefore, the bonding strength between the circuit layer 12 and the ceramic substrate 11 can be ensured even when the use environment temperature becomes high. Further, since the Ti layer is not formed at the bonding interface between the ceramic substrate 11 and the circuit layer 12, the thermal resistance in the stacking direction of the circuit layer 12 and the ceramic substrate 11 can be suppressed, and the circuit layer 12 is mounted on the circuit layer 12. The heat generated from the semiconductor element 3 can be efficiently radiated.
  • the thickness of the 1st intermetallic compound layer 16 since the thickness of the 1st intermetallic compound layer 16 shall be 0.2 micrometer or more, the joining strength of the circuit layer 12 and the ceramic substrate 11 can be improved reliably. On the other hand, since the thickness of the first intermetallic compound layer 16 is 6 ⁇ m or less, the occurrence of cracks in the first intermetallic compound layer 16 can be suppressed. In order to improve the bonding strength between the circuit layer 12 and the ceramic substrate 11 with certainty, the lower limit of the thickness of the first intermetallic compound layer 16 is preferably 0.5 ⁇ m or more, and preferably 1 ⁇ m or more. Is more preferable.
  • the thickness of the 1st intermetallic compound layer 16 may be thicker than the thickness of the intermediate first intermetallic compound layer due to the diffusion of Ti by heating in the heat treatment step S03.
  • the thickness of the second intermetallic compound layer 17 is 0.5 ⁇ m or more, the bonding strength between the circuit layer 12 and the ceramic substrate 11 can be reliably improved.
  • the thickness of the second intermetallic compound layer 17 is 4 ⁇ m or less, the occurrence of cracks in the second intermetallic compound layer 17 can be suppressed.
  • the lower limit of the thickness of the second intermetallic compound layer 17 is preferably 1 ⁇ m or more, and more preferably 2 ⁇ m or more. preferable.
  • the upper limit of the thickness of the 2nd intermetallic compound layer 17 into 3.5 micrometers or less, and to set it as 3 micrometers or less. Is more preferable.
  • the Cu plate 22 that becomes the circuit layer 12 and the Ti material 25 are stacked and pressed in the stacking direction (pressure 1 to 35 kgf / cm 2 ). Since there is a CuTi diffusion step S01 in which the Cu plate 22 and the Ti material 25 are placed in a vacuum heating furnace and heated to cause solid phase diffusion bonding to obtain a Cu—Ti joined body 27, the Cu plate 22 and intermediate Ti are provided. An intermediate first intermetallic compound layer containing Cu and Ti can be reliably formed between the layers 26.
  • the thickness of the intermediate Ti layer 26 is in the range of 0.1 ⁇ m or more and 3 ⁇ m or less, the intermediate Ti layer 26 and the Cu—P—Sn brazing material 24 Can be reacted. Further, in the CuTi diffusion step S01, the Cu plate 22 and the Ti material 25 are laminated and heated, and the Cu—P—Sn brazing material 24 is not laminated. It can be set freely.
  • the ceramic substrate 11, the Cu—P—Sn brazing material 24, and the Cu—Ti joined body 27 are pressurized in the stacking direction (pressure 1 to 35 kgf / cm 2).
  • the heat treatment step S03 is performed in which the heat treatment is performed by charging in a vacuum heating furnace, so that the second Ti can be reacted with the Cu—P—Sn brazing material 24 by reacting the Ti of the intermediate Ti layer 26 with the second heat treatment step 24.
  • the intermetallic compound layer 17 can be formed, and the circuit layer 12 and the ceramic substrate 11 can be reliably bonded.
  • the pressure applied is 1 kgf / cm 2 or more
  • the liquid phase of the ceramic substrate 11 and the Cu—P—Sn brazing material 24 can be brought into close contact, and the ceramic substrate 11 And the Cu—Sn layer 14 can be bonded satisfactorily.
  • the pressurized pressure is 35 kgf / cm 2 or less, the occurrence of cracks in the ceramic substrate 11 can be suppressed.
  • the pressure pressurized is set to 1 kgf / cm 2 or more 35 kgf / cm 2 within the following ranges.
  • FIG. 6 shows a power module 101 including the power module substrate 110 according to the second embodiment.
  • This power module 101 includes a power module substrate 110 on which a circuit layer 112 and a metal layer 113 are disposed, and a semiconductor element bonded to one surface (upper surface in FIG. 6) of the circuit layer 112 via a bonding layer 2. 3 and a heat sink 130 disposed on the other side of the metal layer 113 (lower side in FIG. 6).
  • the power module substrate 110 includes a ceramic substrate 11, a circuit layer 112 disposed on one surface of the ceramic substrate 11 (upper surface in FIG. 7), and the other surface of the ceramic substrate 11. And a metal layer 113 disposed on the lower surface in FIG.
  • the ceramic substrate 11 is made of AlN (aluminum nitride) with excellent heat dissipation.
  • the circuit layer 112 is formed by sequentially laminating a Cu—P—Sn-based brazing material 124, a Ti material 25, and a Cu plate 122 made of oxygen-free copper on one surface of the ceramic substrate 11, and performing a heat treatment. Then, it is formed by bonding a Cu plate 122 to the ceramic substrate 11 (see FIG. 10).
  • the thickness of the circuit layer 112 is set within a range of 0.1 mm or more and 1.0 mm or less, and is set to 0.3 mm in the present embodiment.
  • the metal layer 113 is formed by bonding a Cu or Cu alloy metal plate to the other surface of the ceramic substrate 11 via a Cu—P—Sn brazing material 124.
  • the metal layer 113 is formed by laminating a Cu-P-Sn-based brazing material 124, a Ti material 25, and a Cu plate 123 made of oxygen-free copper on the other surface of the ceramic substrate 11, and heat-treating the ceramic substrate.
  • 11 is formed by bonding a Cu plate 123 (see FIG. 10).
  • the thickness of the metal layer 113 is set within a range of 0.1 mm or more and 1.0 mm or less, and is set to 0.3 mm in the present embodiment.
  • a Cu—P—Sn—Ni brazing material is specifically used as the Cu—P—Sn brazing material 124.
  • FIG. 8 is a schematic explanatory diagram of the bonding interface between the ceramic substrate 11 and the circuit layer 112 (metal layer 113).
  • the Cu—Sn layer 14 located on the ceramic substrate 111 side and the circuit layer 112 (metal layer 113) side are provided.
  • a first intermetallic compound layer 16 located between Cu and Ti, and a second intermetallic compound layer located between the first intermetallic compound layer 16 and the Cu—Sn layer 14 and containing P and Ti. 17 are formed.
  • a Ti layer 15 is formed between the first intermetallic compound layer 16 and the second intermetallic compound layer 17, and the thickness of the Ti layer 15 is 0.5 ⁇ m or less.
  • the thickness of the first intermetallic compound layer 16 is in the range of 0.2 ⁇ m to 6 ⁇ m.
  • the thickness of the second intermetallic compound layer 17 is in the range of 0.5 ⁇ m to 4 ⁇ m.
  • the heat sink 130 dissipates heat from the power module substrate 110 described above.
  • the heat sink 130 is made of Cu or Cu alloy, and is made of phosphorous deoxidized copper in this embodiment.
  • the heat sink 130 is provided with a flow path 131 through which a cooling fluid flows.
  • the heat sink 130 and the metal layer 113 are joined by a solder layer 132 made of a solder material.
  • a Cu—P—Sn brazing material 124, a Ti material 25, and a Cu plate 122 to be a circuit layer 112 are sequentially laminated on one surface (the upper surface in FIG. 10) of the ceramic substrate 11.
  • the Cu—P—Sn brazing material 124, the Ti material 25, and the Cu plate 123 to be the metal layer 113 are sequentially laminated on the other surface (the lower surface in FIG. 10) of the ceramic substrate 11 (lamination step S101).
  • the Cu—P—Sn brazing material 124 is disposed on the ceramic substrate 11 side
  • the Ti material 25 is disposed on the Cu plates 122 and 123 side.
  • the composition of the Cu—P—Sn brazing material 124 is Cu—6.3 mass%, P—9.3 mass%, Sn—7 mass% Ni, and the solidus temperature (melting start temperature). ) Is 600 ° C.
  • the Cu—P—Sn brazing material 124 is made of a foil material and has a thickness in the range of 5 ⁇ m to 150 ⁇ m.
  • the thickness of the Ti material 25 is in the range of 0.4 ⁇ m to 5 ⁇ m.
  • the Ti material 25 is preferably formed by vapor deposition or sputtering when the thickness is 0.4 ⁇ m or more and less than 1 ⁇ m, and the foil material is preferably used when the thickness is 1 ⁇ m or more and 5 ⁇ m or less.
  • the lower limit of the thickness of the Ti material 25 is preferably 0.4 ⁇ m or more, and more preferably 0.5 ⁇ m or more.
  • the upper limit of the thickness of the Ti material 25 is preferably 1.5 ⁇ m or less, and more preferably 0.7 ⁇ m or less.
  • a Ti foil having a thickness of 1 ⁇ m and a purity of 99.8 mass% was used as the Ti material 25.
  • the Cu plate 122, the Ti material 25, the Cu—P—Sn brazing material 124, the ceramic substrate 11, the Cu—P—Sn based brazing material 124, the Ti material 25, and the Cu plate 123 are pressed in the stacking direction. (pressure 1 kgf / cm 2 or more 35 kgf / cm 2 or less) in a state, charged into a vacuum heating furnace, heating at a temperature below the melting initiation temperature of the Cu-P-Sn based brazing material 124 (first heat treatment Step S102).
  • the Ti material 25 and the Cu plate 122, and the Ti material 25 and the Cu plate 123 are joined by solid phase diffusion bonding, and between the Ti material 25 and the Cu plate 122 and between the Ti material 25 and the Cu plate 122.
  • a first intermetallic compound layer 16 containing Cu and Ti is formed between the plate 123 and the plate 123.
  • the pressure in the vacuum heating furnace is in the range of 10 ⁇ 6 Pa to 10 ⁇ 3 Pa
  • the heating temperature is in the range of 580 ° C. to 670 ° C.
  • the heating time is 30 minutes or more. It is set within the range of 240 minutes or less.
  • the heating temperature in the first heat treatment step S102 is set to the melting start temperature (solidus line) of the Cu—P—Sn brazing material 124. Temperature) is preferably ⁇ 10 ° C.
  • the first intermetallic compound layer 16 can be sufficiently formed by setting the heating temperature to 580 ° C. or more and the heating time to 30 minutes or more.
  • the lower limit of the heating temperature is preferably 610 ° C. or higher, and more preferably 620 ° C. or higher.
  • the upper limit of the heating temperature is preferably 650 ° C. or less, more preferably 640 ° C. or less.
  • the lower limit of the heating time is preferably 15 minutes or more, and more preferably 60 minutes or more.
  • the upper limit of the heating time is preferably 120 minutes or less, and more preferably 90 minutes or less.
  • pressure 123 in the stacking direction pressure 1 kgf / cm 2 or more 35 kgf / cm 2 or less
  • the pressure in the vacuum heating furnace is in the range of 10 ⁇ 6 Pa to 10 ⁇ 3 Pa
  • the heating temperature is in the range of 600 ° C. to 700 ° C.
  • the heating time is 15 minutes or more.
  • the second heat treatment step S103 in order to reliably melt the Cu—P—Sn brazing material 124, it is preferable to heat the Cu—P—Sn brazing material 124 at a solidus temperature of + 10 ° C. or higher. .
  • the Cu—P—Sn brazing material 124 is melted to form a liquid phase, the Ti material 25 is dissolved in the liquid phase, and the liquid phase is solidified.
  • Cu plate 122 and ceramic substrate 11 and Cu plate 123 are joined together.
  • P and Ni contained in the Cu—P—Sn based brazing material 124 are bonded to Ti of the Ti material 25 to form the second intermetallic compound layer 17, and on the ceramic substrate 11 side, Cu -The Sn layer 14 is formed.
  • a part of the Ti material 25 remains without being dissolved in the liquid phase of the Cu—P—Sn brazing material 124, and the first intermetallic compound layer 16 and the second intermetallic compound layer 17.
  • Ti layer 15 is formed between the two.
  • the circuit layer 112 is formed on one surface of the ceramic substrate 11 and the metal layer 113 is formed on the other surface, and the power module substrate 110 according to the present embodiment is manufactured.
  • the heat sink 130 is bonded to the lower surface of the metal layer 113 of the power module substrate 110 via a solder material (heat sink bonding step S104).
  • the semiconductor element 3 is bonded to the upper surface of the circuit layer 112 of the power module substrate 110 via a solder material (semiconductor element bonding step S105). In this way, the power module 101 according to this embodiment is manufactured.
  • the circuit layer 112 side at the bonding interface between the ceramic substrate 11 and the circuit layer 112 and at the bonding interface between the ceramic substrate 11 and the metal layer 113. Since the first intermetallic compound layer 16 containing Cu and Ti is formed on the metal layer 113 side, the circuit layer 112 and the second intermetallic compound are interposed via the first intermetallic compound layer 16. The layer 17 and the metal layer 113 and the second intermetallic compound layer 17 can be reliably bonded. Therefore, the bonding strength between the circuit layer 112 and the ceramic substrate 11 and the metal layer 113 and the ceramic substrate 11 can be ensured even when the use environment temperature becomes high.
  • the Ti layer 15 is formed at the bonding interface between the ceramic substrate 11 and the circuit layer 112 and the bonding interface between the ceramic substrate 11 and the metal layer 113, the thickness is 0.5 ⁇ m or less.
  • the thermal resistance in the stacking direction of the circuit layer 112, the ceramic substrate 11, and the metal layer 113 can be kept low, and the heat generated from the semiconductor element 3 mounted on the circuit layer 112 can be efficiently radiated.
  • the thickness of the first intermetallic compound layer 16 is 0.2 ⁇ m or more, the bonding strength between the circuit layer 112 and the ceramic substrate 11 and between the metal layer 113 and the ceramic substrate 11 is ensured. Can be improved. On the other hand, since the thickness of the first intermetallic compound layer 16 is 6 ⁇ m or less, the occurrence of cracks in the first intermetallic compound layer 16 can be suppressed.
  • the thickness of the second intermetallic compound layer 17 is 0.5 ⁇ m or more, the bonding strength between the circuit layer 112 and the ceramic substrate 11 and between the metal layer 113 and the ceramic substrate 11 is ensured. Can be improved. On the other hand, since the thickness of the second intermetallic compound layer 17 is 4 ⁇ m or less, the occurrence of cracks in the second intermetallic compound layer 17 can be suppressed.
  • the second intermetallic compound layer 17 can be formed by reacting the Ti of the Ti material 25 with the Cu—P—Sn brazing material 124, and the circuit layer 112, the ceramic substrate 11, and the metal layer can be formed. 113 and the ceramic substrate 11 can be reliably bonded.
  • the pressure applied is 1 kgf / cm 2 or more
  • the liquid phase of the ceramic substrate 11 and the Cu—P—Sn brazing material 124 can be brought into close contact with each other.
  • the substrate 11 and the Cu—Sn layer 14 can be bonded satisfactorily.
  • the pressurized pressure is 35 kgf / cm 2 or less, the occurrence of cracks in the ceramic substrate 11 can be suppressed.
  • the pressure pressurized is set to 1 kgf / cm 2 or more 35 kgf / cm 2 within the following ranges.
  • the circuit layer 112 is bonded to one surface of the ceramic substrate 11 and the metal layer 113 is bonded to the other surface at the same time.
  • the manufacturing process can be simplified and the manufacturing cost can be reduced.
  • FIG. 11 shows a power module 201 including a power module substrate 210 according to the third embodiment.
  • This power module 201 includes a power module substrate 210 on which a circuit layer 212 and a metal layer 213 are disposed, and a semiconductor element bonded to one surface (upper surface in FIG. 11) of the circuit layer 212 via a bonding layer 2. 3 and a heat sink 230 bonded to the other side (lower side in FIG. 11) of the power module substrate 210.
  • the power module substrate 210 includes a ceramic substrate 11, a circuit layer 212 disposed on one surface (the upper surface in FIG. 12) of the ceramic substrate 11, and the other surface of the ceramic substrate 11. And a metal layer 213 disposed on the lower surface in FIG.
  • the ceramic substrate 11 is made of AlN (aluminum nitride) with excellent heat dissipation.
  • the circuit layer 212 is formed by laminating a Cu-P-Sn-based brazing material 224, a Ti material 25, and a Cu plate 222 made of oxygen-free copper on one surface of the ceramic substrate 11, and heat-treating it. It is formed by bonding a Cu plate 222 to the ceramic substrate 11 (see FIG. 15).
  • the thickness of the circuit layer 212 is set within a range of 0.1 mm or more and 1.0 mm or less, and is set to 0.3 mm in the present embodiment.
  • a Cu—P—Sn—Ni brazing material is specifically used as the Cu—P—Sn brazing material 224.
  • the bonding interface between the ceramic substrate 11 and the circuit layer 212 includes a Cu—Sn layer 14 located on the ceramic substrate 11 side and a Cu—Ti layer located on the circuit layer 212 side. And a second intermetallic compound layer 17 that is located between the first intermetallic compound layer 16 and the Cu—Sn layer 14 and contains P and Ti is formed. .
  • a Ti layer 15 is formed between the first intermetallic compound layer 16 and the second intermetallic compound layer 17, and the thickness of the Ti layer 15 is 0.5 ⁇ m or less.
  • the metal layer 213 is formed by bonding an Al plate made of Al or an Al alloy to the other surface of the ceramic substrate 11.
  • the metal layer 213 is formed by bonding an Al plate 223 having a purity of 99.99 mass% or more to the other surface of the ceramic substrate 11 (see FIG. 15).
  • the thickness of the metal layer 213 is set within a range of 0.1 mm to 3.0 mm, and is set to 1.6 mm in the present embodiment.
  • the heat sink 230 is made of Al or an Al alloy, and is made of A6063 (Al alloy) in the present embodiment.
  • the heat sink 230 is provided with a flow path 231 through which a cooling fluid flows.
  • the heat sink 230 and the metal layer 213 are joined by an Al—Si brazing material.
  • a method for manufacturing the power module 201 according to the present embodiment will be described with reference to the flowchart of FIG. 14 and FIG.
  • a Cu plate 222 and a Ti material 25 to be the circuit layer 212 are laminated, and placed in a vacuum heating furnace in a state of being pressurized (pressure 1 to 35 kgf / cm 2 ) in the lamination direction.
  • pressure 1 to 35 kgf / cm 2 pressure 1 to 35 kgf / cm 2
  • the thickness of the Ti material 25 is in the range of 0.4 ⁇ m to 5 ⁇ m.
  • the Ti material 25 is preferably formed by vapor deposition or sputtering when the thickness is 0.4 ⁇ m or more and less than 1 ⁇ m, and the foil material is preferably used when the thickness is 1 ⁇ m or more and 5 ⁇ m or less.
  • the lower limit of the thickness of the Ti material 25 is preferably 0.4 ⁇ m or more, and more preferably 0.5 ⁇ m or more.
  • the upper limit of the thickness of the Ti material 25 is preferably 1.5 ⁇ m or less, and more preferably 0.7 ⁇ m or less.
  • a Ti foil having a thickness of 1.4 ⁇ m and a purity of 99.8 mass% is used as the Ti material 25.
  • the pressure in the vacuum heating furnace is in the range of 10 ⁇ 6 Pa to 10 ⁇ 3 Pa
  • the heating temperature is in the range of 600 ° C. to 670 ° C.
  • the heating time is 30 minutes. It is set within the range of 360 minutes or less.
  • the intermediate first intermetallic compound layer can be sufficiently formed by setting the heating temperature to 600 ° C. or more and the heating time to 30 minutes or more. Moreover, it can suppress that an intermediate
  • the lower limit of the heating temperature is preferably 610 ° C.
  • the upper limit of the heating temperature is preferably 650 ° C. or less, more preferably 640 ° C. or less.
  • the lower limit of the heating time is preferably 15 minutes or more, and more preferably 60 minutes or more.
  • the upper limit of the heating time is preferably 120 minutes or less, and more preferably 90 minutes or less.
  • the pressure load in the stacking direction is 0.294 MPa to 1.96 MPa (3 kgf / cm 2 to 20 kgf / It is preferable to be within the range of cm 2 or less. More preferably, it is 0.490 MPa or more and 1.47 MPa or less, More preferably, it is good to set it in the range of 1.18 MPa or more and 1.47 MPa or less.
  • the Ti material 25 and the Cu plate 222 are bonded by solid phase diffusion bonding, and a laminated structure of the Cu plate 222 and the intermediate Ti layer 26 is formed.
  • an intermediate first intermetallic compound layer containing Cu and Ti is formed between the intermediate Ti layer 26 and the Cu plate 222.
  • the thickness of the intermediate Ti layer 26 is in the range of 0.1 ⁇ m to 3 ⁇ m.
  • the lower limit of the thickness of the intermediate Ti layer 26 is preferably 0.2 ⁇ m or more, and more preferably 0.4 ⁇ m or more. Further, the upper limit of the thickness of the intermediate Ti layer 26 is preferably 1.5 ⁇ m or less, and more preferably 0.7 ⁇ m or less. Furthermore, it is preferable that the thickness of the intermediate first intermetallic compound layer is 0.1 ⁇ m or more and 6 ⁇ m or less.
  • a Cu—P—Sn brazing material 224, a Ti material 25, and a Cu plate 222 are sequentially laminated on one surface (the upper surface in FIG. 15) of the ceramic substrate 11, and the ceramic substrate.
  • an Al plate 223 to be the metal layer 213 is sequentially laminated on the other surface (lower surface in FIG. 14) with a bonding material 241 interposed therebetween.
  • the heat sink 230 is laminated below the Al plate 223 via the bonding material 242 (lamination step S202).
  • the Cu—Ti joined body 227 is laminated so that the intermediate Ti layer 26 and the Cu—P—Sn brazing material 224 face each other.
  • the composition of the Cu—P—Sn brazing material 224 is Cu-7 mass% P-15 mass% Sn-10 mass% Ni, and its melting start temperature (solidus temperature) is 580 ° C. It is said that.
  • the Cu—P—Sn brazing material 224 is made of a foil material and has a thickness in the range of 5 ⁇ m to 150 ⁇ m.
  • the bonding materials 241 and 242 are Al—Si brazing materials containing Si as a melting point lowering element.
  • Al—7.5 mass% Si brazing material is used. The material is used.
  • the ceramic substrate 11, the Cu—P—Sn brazing material 224, the Cu—Ti joined body 227, the joining material 241, the Al plate 223, the joining material 242 and the heat sink 230 are pressurized in the laminating direction (pressure 1 to 35 kgf). / Cm 2 ), the sample is charged into a vacuum heating furnace and heated (heat treatment step S203).
  • the pressure in the vacuum heating furnace is in the range of 10 ⁇ 6 Pa to 10 ⁇ 3 Pa
  • the heating temperature is in the range of 600 ° C. to 650 ° C.
  • the heating time is 30 minutes or more. It is set within the range of 240 minutes or less.
  • the Cu—P—Sn brazing material 224 is melted to form a liquid phase, and the intermediate Ti layer 26 is dissolved in this liquid phase, and the liquid phase is solidified.
  • the Cu plate 222 is joined.
  • P and Ni contained in the Cu—P—Sn-based brazing material 224 are combined with Ti of the intermediate Ti layer 26 to form the second intermetallic compound layer 17 and on the ceramic substrate 11 side.
  • a Cu—Sn layer 14 is formed.
  • the first intermetallic compound layer 16 is formed by leaving the intermediate first intermetallic compound layer.
  • the intermediate Ti layer 26 is in the range of 0.1 ⁇ m or more and 3 ⁇ m or less, the intermediate Ti layer 26 is in the liquid phase of the Cu—P—Sn-based brazing material 224. All is not melted and a part of it remains, and the Ti layer 15 is formed. However, since the thickness of the Ti layer 15 is as thin as 0.5 ⁇ m or less, the thermal resistance in the stacking direction of the circuit layer 212, the ceramic substrate 11, and the metal layer 213 can be kept low. Heat generated from the semiconductor element 3 mounted thereon can be efficiently radiated.
  • the thickness of the first intermetallic compound layer 16 may become thicker than the thickness of the intermediate first intermetallic compound layer due to the diffusion of Ti by heating in the heat treatment step S203. Further, the thickness of the Ti layer 15 may become thinner than the thickness of the intermediate Ti layer 26 due to the diffusion of Ti by heating in the heat treatment step S203.
  • the bonding material 241 is melted to form a liquid phase, and the liquid phase is solidified, so that the ceramic substrate 11 and the Al plate 223 are bonded via the bonding material 241. Further, in the heat treatment step S ⁇ b> 203, the bonding material 242 is melted to form a liquid phase, and the liquid phase is solidified, whereby the Al plate 223 and the heat sink 230 are bonded via the bonding material 242. Thereby, the substrate 210 for power modules which is this embodiment is manufactured.
  • the semiconductor element 3 is bonded to the upper surface of the circuit layer 212 of the power module substrate 210 via a solder material (semiconductor element bonding step S204). In this way, the power module 201 according to this embodiment is manufactured.
  • the power module substrate 210 according to the present embodiment configured as described above has the same effects as the power module substrates 10 and 110 described in the first and second embodiments. Further, in the power module substrate 210 according to the present embodiment, the metal layer 213 formed by bonding the Al plate 223 to the other surface of the ceramic substrate 11 is formed. It can be efficiently dissipated through the layer 213. Further, since Al has a relatively low deformation resistance, the thermal stress generated between the power module substrate 210 and the heat sink 230 is absorbed by the metal layer 213 when a cooling cycle is applied, and the ceramic substrate 11 is not cracked. Occurrence can be suppressed.
  • the circuit layer 212 is bonded to one surface of the ceramic substrate 11 and the metal layer 213 is simultaneously bonded to the other surface.
  • the manufacturing process can be simplified and the manufacturing cost can be reduced.
  • the power module is configured by mounting a semiconductor element on an insulating circuit board.
  • the present invention is not limited to this.
  • an LED module may be configured by mounting LED elements on a circuit layer of an insulated circuit board, or a thermoelectric module may be configured by mounting thermoelectric elements on a circuit layer of an insulated circuit board.
  • the case where the circuit layer is bonded to one surface of the ceramic substrate and the metal layer is simultaneously bonded to the other surface has been described. However, the circuit layer and the metal layer are separately provided. You may join.
  • the case where the circuit layer, the metal layer, and the heat sink are simultaneously bonded has been described. However, the circuit layer and the metal layer may be bonded to the ceramic substrate, and then the metal layer and the heat sink may be bonded. good.
  • the case where the metal layer is bonded to the other surface of the ceramic substrate via the Al—Si brazing material has been described, but the bonding is performed by a transient liquid phase bonding method (TLP), Ag paste, or the like. May be.
  • TLP transient liquid phase bonding method
  • the heat sink provided with the flow path has been described in the second embodiment and the third embodiment, a plate-like thing called a heat radiating plate or a pin-like fin may be used.
  • the power module substrate and the heat sink may be fixed by screwing or the like via grease.
  • the heat sink may not be bonded to the other surface side of the power module substrate.
  • the case where a Ti foil is used as the Ti material or the case where the Ti material is formed by vapor deposition or sputtering has been described.
  • Ti is formed on one surface of the Cu member. It is also possible to use a Cu member / Ti clad material in which is disposed.
  • the first intermetallic compound layer containing Cu and Ti may be formed by heating the Cu member / Ti clad material in advance, or in the Cu member / Ti clad material in the first heat treatment step. A first intermetallic compound layer may be formed.
  • a Ti material / brazing material clad material in which a Cu—P—Sn based brazing material is disposed on one surface of the Ti material, a Cu member, a Ti material, and a Cu—P—Sn based brazing material are laminated in this order.
  • Member / Ti material / brazing material clad can be used.
  • a Cu—P—Sn brazing material suitable for the method for producing a joined body of the present invention will be described in detail.
  • the P content of the Cu—P—Sn brazing material is preferably 3 mass% or more and 10 mass% or less.
  • P is an element having an effect of lowering the melting start temperature of the brazing material. Moreover, this P prevents oxidation of the brazing filler metal by covering the surface of the brazing filler metal with the P oxide generated by oxidation of P, and the surface of the molten brazing filler metal has good fluidity. It is an element having an effect of improving the wettability of the brazing material by covering. If the P content is less than 3 mass%, the effect of lowering the melting start temperature of the brazing material cannot be sufficiently obtained, the melting start temperature of the brazing material is increased, or the fluidity of the brazing material is insufficient.
  • the bondability with the layer may decrease.
  • the P content exceeds 10 mass%, a large amount of brittle intermetallic compounds are formed, and the bonding properties and bonding reliability between the ceramic substrate and the circuit layer may be reduced.
  • the content of P contained in the Cu—P—Sn brazing material is preferably in the range of 3 mass% to 10 mass%.
  • the Sn content of the Cu—P—Sn brazing material is preferably 0.5 mass% or more and 25 mass% or less.
  • Sn is an element having an effect of lowering the melting start temperature of the brazing material.
  • the Sn content is 0.5 mass% or more, the melting start temperature of the brazing material can be reliably lowered.
  • the Sn content is 25 mass% or less, the low temperature embrittlement of the brazing material can be suppressed, and the bonding reliability between the ceramic substrate and the circuit layer can be improved.
  • the Sn content in the Cu—P—Sn brazing material is preferably in the range of 0.5 mass% to 25 mass%.
  • the Cu—P—Sn brazing material may contain 2 mass% or more and 20 mass% or less of any one or more of Ni, Cr, Fe, and Mn.
  • Ni, Cr, Fe, and Mn are elements having an effect of suppressing the formation of an intermetallic compound containing P at the interface between the ceramic substrate and the brazing material.
  • the content of one or more of Ni, Cr, Fe, and Mn is 2 mass% or more, the formation of intermetallic compounds containing P at the bonding interface between the ceramic substrate and the brazing material is suppressed. This improves the bonding reliability between the ceramic substrate and the circuit layer.
  • the content of any one or more of Ni, Cr, Fe, and Mn is 20 mass% or less, an increase in the melting start temperature of the brazing material is suppressed, and the fluidity of the brazing material is lowered. This can suppress this and improve the bondability between the ceramic substrate and the circuit layer.
  • the content is within the range of 2 mass% or more and 20 mass% or less. It is preferable to do.
  • the above-described laminate was placed in a vacuum heating furnace (pressure: 10 ⁇ 4 Pa), and heated as a first heat treatment step at the temperature and time shown in Table 1 (column of heat treatment 1). Thereafter, as the second heat treatment step, the Cu plate is joined to one surface and the other surface of the ceramic substrate by heating at the temperature and time shown in Table 2 (column of heat treatment 2), and the circuit layer and metal A layer was formed to obtain a power module substrate.
  • the size of the Cu plate for the circuit layer is 44 mm ⁇ 25 mm for 90 ° peel strength test described later (however, it protrudes 5 mm from the end of the ceramic substrate), and 37 mm ⁇ 37 mm for the thermal resistance test, Each was produced.
  • the size of the Cu plate for the metal layer was 37 mm ⁇ 37 mm.
  • one surface of the ceramic substrate shown in Table 1 (40 mm ⁇ 40 mm, thickness 0.635 mm for AlN and Al 2 O 3 , thickness 0.32 mm for Si 3 N 4 ) and the other surface
  • a Cu—P—Sn-based brazing foil and a Cu—Ti joined body shown in Table 1 are sequentially laminated. And it heats with the temperature and time (column of the heat processing 2) of Table 2, and joins Cu board to the one side and the other side of a ceramic substrate, forms a circuit layer and a metal layer, The board
  • substrate for power modules was made.
  • the size of the Cu plate for the circuit layer and the metal layer was the same as described above.
  • a Cu plate was bonded to one surface and the other surface of the ceramic substrate to form a circuit layer and a metal layer to obtain a power module substrate.
  • the size of the Cu plate for the circuit layer and the metal layer was the same as the example of the present invention.
  • the power module substrate obtained as described above was evaluated for 90 ° peel strength between the circuit layer and the ceramic substrate and the thermal resistance in the stacking direction. Moreover, the thickness of the 1st intermetallic compound layer, Ti layer, and 2nd intermetallic compound layer was evaluated in the joining interface of a ceramic substrate and a circuit layer with respect to the obtained board
  • the thicknesses of the first intermetallic compound layer, the Ti layer and the second intermetallic compound layer are formed at the bonding interface from the EPMA at the Cu plate / ceramics substrate interface in a field of view of 10,000 times magnification (length 30 ⁇ m, width 40 ⁇ m).
  • the total area of the first intermetallic compound layer, the area of the Ti layer, and the total area of the second intermetallic compound layer are measured and divided by the width of the measurement visual field, and the average of the five visual fields is calculated between the first metal
  • the thicknesses of the compound layer, the Ti layer, and the second intermetallic compound layer were used.
  • the intermediate first intermetallic compound layer and the intermediate Ti layer have a 10,000 ⁇ field of view (length 30 ⁇ m, horizontal width) from the EPMA with respect to the Cu / Ti bonding interface of the Cu—Ti bonded body prepared by the heating method B described above. 40 ⁇ m), the total area of the intermediate first intermetallic compound layer formed at the bonding interface and the total area of the intermediate Ti layer are measured and divided by the width of the measurement visual field, and the average of the five visual fields is obtained.
  • the thickness of the intermediate first intermetallic compound layer and the intermediate Ti layer was used. Note that regions where the Ti concentration is in the range of 15 at% to 70 at% are regarded as the first intermetallic compound layer and the intermediate first intermetallic compound layer, and solid solutions are not included.
  • the second intermetallic compound layer includes at least P and Ti, and the P concentration is a region in the range of 28 at% to 52 at%. The evaluation results are shown in Tables 1 and 2.
  • Example 1 In Conventional Example 1 in which the Ti layer was formed thick, it was confirmed that although the 90 ° peel strength was high, the thermal resistance in the stacking direction was high. Further, in Conventional Example 2 in which no Ti layer was confirmed, it was confirmed that the first intermetallic compound layer was not formed and the 90 ° peel strength was low. On the other hand, in Examples 1 to 15 of the present invention, it was confirmed that a power module substrate having a high 90 ° peel strength and a low thermal resistance was obtained.
  • Example 2 Next, a more severe peel strength test was conducted.
  • a CuTi diffusion process a Cu plate (thickness: 0.3 mm) made of oxygen-free copper and a Ti material having a thickness of 3 mm are stacked, and the vacuum heating furnace is pressed in the stacking direction with the pressure shown in Table 3 The inside (pressure: 10 ⁇ 4 Pa) was charged and heated at the temperature and time shown in Table 3 (column of heat treatment 1) to obtain a Cu—Ti joined body.
  • Cu—Ti bonded bodies were prepared for the circuit layer and the metal layer, respectively.
  • one surface of the ceramic substrate described in Table 3 (40 mm ⁇ 40 mm, thickness 0.635 mm for AlN and Al 2 O 3 , thickness 0.32 mm for Si 3 N 4 ) and the other surface Cu-6.3 mass% P-9.3 mass% Sn-7.0 mass% Ni brazing material foil (melting point 600 ° C.) and Cu—Ti joined body were laminated in this order on the surface.
  • heat processing 2 it heated on condition of 650 degreeC for 60 minutes, the Cu board was joined to one side and the other side of a ceramic substrate, the circuit layer and the metal layer were formed, and the board
  • the size of the Cu plate for the circuit layer and the metal layer was the same as described above.
  • the 90 ° peel strength between the circuit layer and the ceramic substrate was evaluated under the following conditions.
  • the portion of the circuit layer that protrudes from the ceramic substrate is bent 90 °, the circuit layer is pulled in a direction perpendicular to the ceramic substrate, and the circuit layer is peeled off from the ceramic substrate.
  • the maximum tensile load was measured.
  • a value obtained by dividing the load by the joining length was defined as 90 ° peel strength, and is shown in Table 3.
  • the joining length in this example was the length of the long side of the circuit layer at the part where the circuit layer and the ceramic substrate were joined.
  • the power module substrate, the manufacturing method of the joined body, and the manufacturing method of the power module substrate, the ceramic member and the Cu member are satisfactorily bonded, and the thermal resistance in the stacking direction is reduced. It can be lowered.

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Abstract

This bonded body comprises a ceramic member formed from a ceramic and a Cu member formed from Cu or a Cu alloy. The following layers are formed on the bonding interface between the ceramic member and the Cu member: a Cu-Sn layer positioned on the Cu member side and comprising a solid solution of Sn in Cu, a first intermetallic compound layer positioned on the Cu member side and containing Cu and Ti, and a second intermetallic compound layer positioned between the first intermetallic compound layer and the Cu-Sn layer and containing P and Ti.

Description

接合体、パワーモジュール用基板、接合体の製造方法及びパワーモジュール用基板の製造方法BONDED BODY, POWER MODULE SUBSTRATE, BONDED BODY MANUFACTURING METHOD, AND POWER MODULE BOARD MANUFACTURING METHOD
　この発明は、セラミックス部材とＣｕ部材とが接合された接合体、及びセラミックス基板にＣｕ又はＣｕ合金からなるＣｕ板が接合されたパワーモジュール用基板に関する。
　本願は、２０１６年１月２２日に、日本に出願された特願２０１６－０１０６７５号、及び２０１７年１月５日に、日本に出願された特願２０１７－０００３８１号に基づき優先権を主張し、その内容をここに援用する。 The present invention relates to a joined body in which a ceramic member and a Cu member are joined, and a power module substrate in which a Cu plate made of Cu or a Cu alloy is joined to a ceramic substrate.
This application claims priority based on Japanese Patent Application No. 2016-010675 filed in Japan on January 22, 2016 and Japanese Patent Application No. 2017-000381 filed on Japan on January 5, 2017. , The contents of which are incorporated herein.
　ＬＥＤやパワーモジュール等の半導体装置においては、導電材料からなる回路層の上に半導体素子が接合された構造を備えている。
　風力発電、電気自動車等の電気車両などを制御するために用いられる大電力制御用のパワー半導体素子においては、発熱量が多いことから、これを搭載する基板としては、例えばＡｌＮ（窒化アルミニウム）などからなるセラミックス基板の一方の面に導電性の優れた金属板を回路層として接合したパワーモジュール用基板が、従来から広く用いられている。また、セラミックス基板の他方の面に、金属板を金属層として接合することもある。 Semiconductor devices such as LEDs and power modules have a structure in which a semiconductor element is bonded on a circuit layer made of a conductive material.
In a power semiconductor element for high power control used for controlling an electric vehicle such as wind power generation or an electric vehicle, a large amount of heat is generated. Therefore, as a substrate on which the power semiconductor element is mounted, for example, AlN (aluminum nitride) 2. Description of the Related Art Conventionally, a power module substrate in which a metal plate having excellent conductivity is bonded as a circuit layer to one surface of a ceramic substrate made of has been widely used. Moreover, a metal plate may be joined as a metal layer to the other surface of the ceramic substrate.
　例えば、特許文献１に示すパワーモジュール用基板においては、セラミックス基板（セラミックス部材）の一方の面に、Ｃｕ板（Ｃｕ部材）を接合することで回路層が形成された構造を備えている。このパワーモジュール用基板は、セラミックス基板の一方の面に、Ｃｕ－Ｍｇ－Ｔｉろう材を介在させてＣｕ板を配置し、加熱処理を行うことによりＣｕ板が接合されている。
　ところで、特許文献１に開示されたようにＣｕ－Ｍｇ－Ｔｉろう材を介してセラミックス基板とＣｕ板とを接合すると、セラミックス基板の近傍には、Ｃｕ、Ｍｇ、又はＴｉを含む金属間化合物が形成される。 For example, the power module substrate shown in Patent Document 1 has a structure in which a circuit layer is formed by bonding a Cu plate (Cu member) to one surface of a ceramic substrate (ceramic member). In this power module substrate, a Cu plate is disposed on one surface of a ceramic substrate with a Cu—Mg—Ti brazing material interposed therebetween, and heat treatment is performed to bond the Cu plate.
By the way, when the ceramic substrate and the Cu plate are joined via the Cu—Mg—Ti brazing material as disclosed in Patent Document 1, an intermetallic compound containing Cu, Mg, or Ti is present in the vicinity of the ceramic substrate. It is formed.
　このセラミックス基板近傍に形成される金属間化合物は、硬いため、パワーモジュール用基板に冷熱サイクルが負荷された際にセラミックス基板に発生する熱応力が大きくなり、セラミックス基板にクラックが生じ易くなる問題があった。
　また、セラミックス基板と回路層を接合する際に、セラミックス基板の近傍に硬い金属間化合物が形成されると、セラミックス基板と回路層との接合率が低下し、良好に接合することができないおそれがあった。 Since the intermetallic compound formed in the vicinity of the ceramic substrate is hard, the thermal stress generated in the ceramic substrate when a thermal cycle is applied to the power module substrate increases, and cracks are likely to occur in the ceramic substrate. there were.
In addition, when a hard intermetallic compound is formed in the vicinity of the ceramic substrate when bonding the ceramic substrate and the circuit layer, the bonding rate between the ceramic substrate and the circuit layer may be reduced, and it may not be possible to bond well. there were.
　そこで、例えば特許文献２，３には、セラミックス基板と回路層とを、Ｃｕ－Ｐ－Ｓｎ系ろう材及びＴｉ材を用いて接合したパワーモジュール用基板が提案されている。
　これら特許文献２，３に記載された発明においては、セラミックス基板側にＣｕ－Ｓｎ層が形成されており、セラミックス基板の近傍に硬い金属間化合物層が配設されないことから、冷熱サイクルを負荷した際にセラミックス基板に生じる熱応力を低減でき、セラミックス基板にクラックが発生することを抑制することが可能となる。 Thus, for example, Patent Documents 2 and 3 propose a power module substrate in which a ceramic substrate and a circuit layer are bonded using a Cu—P—Sn brazing material and a Ti material.
In the inventions described in these Patent Documents 2 and 3, a Cu—Sn layer is formed on the ceramic substrate side, and a hard intermetallic compound layer is not provided in the vicinity of the ceramic substrate. In this case, thermal stress generated in the ceramic substrate can be reduced, and cracks can be prevented from occurring in the ceramic substrate.
特許第４３７５７３０号公報Japanese Patent No. 4375730 特開２０１５－０４３３９２号公報Japanese Patent Laying-Open No. 2015-043392 特開２０１５－０６５４２３号公報Japanese Patent Laying-Open No. 2015-0654423
　ところで、最近では、パワーモジュール用基板に搭載される半導体素子の発熱温度が高くなる傾向にあり、パワーモジュール用基板においては、従来にも増して効率的に放熱することが求められている。
　ここで、特許文献２に記載されたパワーモジュール用基板においては、セラミックス基板とＣｕ又はＣｕ合金からなる回路層との間にＴｉ層が形成されており、このＴｉ層の厚さが１μｍ以上１５μｍ以下と比較的厚く形成されている。このため、積層方向の熱抵抗が高くなり、効率的に放熱することができなくなるおそれがあった。
　また、特許文献３に記載されたパワーモジュール用基板においては、セラミックス基板とＣｕ又はＣｕ合金からなる回路層との間に、Ｃｕ－Ｓｎ層とＰ及びＴｉを含有する金属間化合物層が形成されているが、使用環境温度が高くなるとＰ及びＴｉを含有する金属間化合物層を起点としてクラックが生じ、接合が不十分となるおそれがあった。 By the way, recently, the heat generation temperature of the semiconductor elements mounted on the power module substrate tends to increase, and the power module substrate is required to dissipate heat more efficiently than before.
Here, in the power module substrate described in Patent Document 2, a Ti layer is formed between the ceramic substrate and the circuit layer made of Cu or Cu alloy, and the thickness of the Ti layer is 1 μm or more and 15 μm. It is formed relatively thick as follows. For this reason, the thermal resistance in the stacking direction is increased, and there is a possibility that heat cannot be efficiently radiated.
In the power module substrate described in Patent Document 3, a Cu—Sn layer and an intermetallic compound layer containing P and Ti are formed between the ceramic substrate and the circuit layer made of Cu or Cu alloy. However, when the use environment temperature is high, cracks are generated starting from the intermetallic compound layer containing P and Ti, which may result in insufficient bonding.
　この発明は、前述した事情に鑑みてなされたものであって、セラミックス部材とＣｕ部材とが良好に接合され、かつ、積層方向の熱抵抗が低く効率的に放熱することが可能な接合体、パワーモジュール用基板、及び、この接合体の製造方法、パワーモジュール用基板の製造方法を提供することを目的とする。 The present invention has been made in view of the above-described circumstances, and is a bonded body in which a ceramic member and a Cu member are bonded satisfactorily and the heat resistance in the stacking direction is low and can be efficiently radiated. An object of the present invention is to provide a power module substrate, a method for manufacturing the joined body, and a method for manufacturing the power module substrate.
　前述の課題を解決するために、本発明の一態様である接合体は、セラミックスからなるセラミックス部材とＣｕ又はＣｕ合金からなるＣｕ部材との接合体であって、前記セラミックス部材と前記Ｃｕ部材との接合界面には、前記セラミックス部材側に位置し、ＳｎがＣｕ中に固溶したＣｕ－Ｓｎ層と、前記Ｃｕ部材側に位置し、ＣｕとＴｉを含有する第１金属間化合物層と、前記第１金属間化合物層と前記Ｃｕ－Ｓｎ層との間に位置し、ＰとＴｉを含有する第２金属間化合物層と、が形成されていることを特徴としている。 In order to solve the above-described problems, a joined body according to one aspect of the present invention is a joined body of a ceramic member made of ceramics and a Cu member made of Cu or a Cu alloy, and the ceramic member and the Cu member A Cu—Sn layer in which Sn is solid-solved in Cu, a first intermetallic compound layer containing Cu and Ti, located on the Cu member side, and located on the ceramic member side, A second intermetallic compound layer containing P and Ti is formed between the first intermetallic compound layer and the Cu—Sn layer.
　本発明の一態様である接合体によれば、前記Ｃｕ部材側に位置し、ＣｕとＴｉを含有する第１金属間化合物層が形成されているので、Ｃｕ部材と第２金属間化合物層とを確実に接合することができ、使用環境温度が高くなってもＣｕ部材とセラミックス部材との接合強度を確保することができる。また、Ｔｉ層が形成されていない、もしくは非常に薄いので、積層方向における熱抵抗を低く抑えることができ、効率的に放熱することができる。 According to the joined body which is one aspect of the present invention, the first intermetallic compound layer containing Cu and Ti is formed on the Cu member side, so the Cu member and the second intermetallic compound layer are Can be reliably bonded, and the bonding strength between the Cu member and the ceramic member can be ensured even when the use environment temperature increases. Further, since the Ti layer is not formed or is very thin, the thermal resistance in the stacking direction can be kept low, and heat can be efficiently radiated.
　ここで、本発明の一態様である接合体においては、前記第１金属間化合物層と前記第２金属間化合物層との間にＴｉ層が形成されており、このＴｉ層の厚さが０．５μｍ以下とされていてもよい。
　この場合、前記第１金属間化合物層と前記第２金属間化合物層との間にＴｉ層が形成されているが、このＴｉ層の厚さが０．５μｍ以下とされているので、積層方向における熱抵抗を低く抑えることができ、効率的に放熱することができる。 Here, in the joined body which is one embodiment of the present invention, a Ti layer is formed between the first intermetallic compound layer and the second intermetallic compound layer, and the thickness of the Ti layer is 0. It may be 5 μm or less.
In this case, a Ti layer is formed between the first intermetallic compound layer and the second intermetallic compound layer, and since the thickness of the Ti layer is 0.5 μm or less, the stacking direction The heat resistance in can be kept low, and heat can be radiated efficiently.
　また、本発明の一態様である接合体においては、前記第１金属間化合物層の厚さが０．２μｍ以上６μｍ以下の範囲内とされていることが好ましい。
　この場合、ＣｕとＴｉを含有する第１金属間化合物層の厚さが０．２μｍ以上とされているので、Ｃｕ部材とセラミックス部材との接合強度を確実に向上させることができる。一方、第１金属間化合物層の厚さが６μｍ以下とされているので、第１金属間化合物層における割れの発生を抑制することができる。 In the joined body that is one embodiment of the present invention, it is preferable that the thickness of the first intermetallic compound layer is in a range of 0.2 μm to 6 μm.
In this case, since the thickness of the first intermetallic compound layer containing Cu and Ti is 0.2 μm or more, the bonding strength between the Cu member and the ceramic member can be reliably improved. On the other hand, since the thickness of the first intermetallic compound layer is 6 μm or less, the occurrence of cracks in the first intermetallic compound layer can be suppressed.
　さらに、本発明の一態様である接合体においては、前記第２金属間化合物層の厚さが０．５μｍ以上４μｍ以下の範囲内とされていることが好ましい。
　この場合、ＰとＴｉを含有する第２金属間化合物層の厚さが０．５μｍ以上とされているので、Ｃｕ部材とセラミックス部材との接合強度を確実に向上させることができる。一方、第２金属間化合物層の厚さが４μｍ以下とされているので、第２金属間化合物層における割れの発生を抑制することができる。 Furthermore, in the joined body which is one embodiment of the present invention, it is preferable that the thickness of the second intermetallic compound layer is in the range of 0.5 μm to 4 μm.
In this case, since the thickness of the 2nd intermetallic compound layer containing P and Ti is 0.5 micrometer or more, the joint strength of Cu member and a ceramic member can be improved reliably. On the other hand, since the thickness of the second intermetallic compound layer is 4 μm or less, occurrence of cracks in the second intermetallic compound layer can be suppressed.
　本発明の一態様であるパワーモジュール用基板は、上述の接合体からなり、前記セラミックス部材からなるセラミックス基板と、このセラミックス基板の一方の面に形成された前記Ｃｕ部材からなる回路層と、を備え、前記セラミックス基板と前記回路層との接合界面には、前記セラミックス基板側に位置し、ＳｎがＣｕ中に固溶したＣｕ－Ｓｎ層と、前記回路層側に位置し、ＣｕとＴｉを有する第１金属間化合物層と、前記第１金属間化合物層と前記Ｃｕ－Ｓｎ層との間に位置し、ＰとＴｉを含有する第２金属間化合物層と、が形成されていることを特徴としている。 A power module substrate according to an aspect of the present invention includes the above-described joined body, the ceramic substrate including the ceramic member, and the circuit layer including the Cu member formed on one surface of the ceramic substrate. A bonding interface between the ceramic substrate and the circuit layer, located on the ceramic substrate side, and a Cu—Sn layer in which Sn is dissolved in Cu; and located on the circuit layer side, and Cu and Ti. A first intermetallic compound layer, and a second intermetallic compound layer that is located between the first intermetallic compound layer and the Cu-Sn layer and contains P and Ti is formed. It is a feature.
　本発明の一態様であるパワーモジュール用基板によれば、前記回路層側にＣｕとＴｉを含有する第１金属間化合物層が形成されているので、回路層と第２金属間化合物層とを確実に接合することができ、使用環境温度が高くなっても回路層とセラミックス基板との接合強度を確保することができる。また、Ｔｉ層が形成されていない、あるいは、Ｔｉ層が形成されていてもその厚さが０．５μｍ以下と薄いので、積層方向における熱抵抗を低く抑えることができ、回路層上に搭載された半導体素子からの熱を効率的に放熱することができる。 According to the power module substrate which is an aspect of the present invention, since the first intermetallic compound layer containing Cu and Ti is formed on the circuit layer side, the circuit layer and the second intermetallic compound layer are Bonding can be ensured, and the bonding strength between the circuit layer and the ceramic substrate can be ensured even when the operating environment temperature increases. Also, the Ti layer is not formed, or even if the Ti layer is formed, its thickness is as thin as 0.5 μm or less, so the thermal resistance in the stacking direction can be kept low, and it is mounted on the circuit layer. It is possible to efficiently dissipate heat from the semiconductor element.
　ここで、上述の本発明の一態様であるパワーモジュール用基板においては、前記セラミックス基板の他方の面に、Ａｌ又はＡｌ合金からなる金属層が形成されていてもよい。
　この場合、セラミックス基板の他方の面に、比較的変形抵抗の小さなＡｌ又はＡｌ合金からなる金属層が形成されているので、パワーモジュール用基板に応力が負荷された場合に金属層が優先的に変形し、セラミックス基板に作用する応力を低減することができ、セラミックス基板の割れを抑制することができる。 Here, in the power module substrate which is one embodiment of the present invention described above, a metal layer made of Al or an Al alloy may be formed on the other surface of the ceramic substrate.
In this case, since the metal layer made of Al or Al alloy having relatively small deformation resistance is formed on the other surface of the ceramic substrate, the metal layer is preferentially applied when stress is applied to the power module substrate. The stress acting on the ceramic substrate can be reduced and cracking of the ceramic substrate can be suppressed.
　また、本発明の一態様であるパワーモジュール用基板は、上述の接合体からなり、前記セラミックス部材からなるセラミックス基板と、このセラミックス基板の一方の面に形成された回路層と、前記セラミックス基板の他方の面に形成された前記Ｃｕ部材からなる金属層と、を備え、前記セラミックス基板と前記金属層との接合界面には、前記セラミックス基板側に位置し、ＳｎがＣｕ中に固溶したＣｕ－Ｓｎ層と、前記金属層側に位置し、ＣｕとＴｉを有する第１金属間化合物層と、前記第１金属間化合物層と前記Ｃｕ－Ｓｎ層との間に位置し、ＰとＴｉを含有する第２金属間化合物層と、が形成されていることを特徴としている。 Further, a power module substrate according to an aspect of the present invention includes the above-described joined body, the ceramic substrate including the ceramic member, a circuit layer formed on one surface of the ceramic substrate, and the ceramic substrate. And a metal layer made of the Cu member formed on the other surface, and located at the ceramic substrate side at a bonding interface between the ceramic substrate and the metal layer, and Sn is a solid solution in Cu A Sn layer, a first intermetallic compound layer that is located on the metal layer side and includes Cu and Ti, and is located between the first intermetallic compound layer and the Cu-Sn layer, and includes P and Ti. And a second intermetallic compound layer to be contained.
　本発明の一態様であるパワーモジュール用基板によれば、前記金属層側にＣｕとＴｉを含有する第１金属間化合物層が形成されているので、金属層と第２金属間化合物層とを確実に接合することができ、使用環境温度が高くなっても金属層とセラミックス基板との接合強度を確保することができる。また、Ｔｉ層が形成されていない、あるいは、Ｔｉ層が形成されていてもその厚さが０．５μｍ以下と薄いので、積層方向における熱抵抗を低く抑えることができ、回路層上に搭載された半導体素子からの熱を効率的に放熱することができる。 According to the power module substrate which is an aspect of the present invention, since the first intermetallic compound layer containing Cu and Ti is formed on the metal layer side, the metal layer and the second intermetallic compound layer are Bonding can be ensured, and the bonding strength between the metal layer and the ceramic substrate can be ensured even when the use environment temperature increases. Also, the Ti layer is not formed, or even if the Ti layer is formed, its thickness is as thin as 0.5 μm or less, so the thermal resistance in the stacking direction can be kept low, and it is mounted on the circuit layer. It is possible to efficiently dissipate heat from the semiconductor element.
　本発明の一態様である接合体の製造方法は、セラミックスからなるセラミックス部材とＣｕ又はＣｕ合金からなるＣｕ部材との接合体の製造方法であって、Ｃｕ－Ｐ－Ｓｎ系ろう材とＴｉ材とを介して、前記セラミックス部材と前記Ｃｕ部材とを積層する積層工程と、積層された状態で前記Ｃｕ－Ｐ－Ｓｎ系ろう材の溶融開始温度未満の温度で加熱し、前記Ｃｕ部材と前記Ｔｉ材とを反応させてＣｕとＴｉを有する第１金属間化合物層を形成する第１加熱処理工程と、前記第１加熱処理工程後に、前記Ｃｕ－Ｐ－Ｓｎ系ろう材の溶融開始温度以上の温度で加熱し、ＳｎがＣｕ中に固溶したＣｕ－Ｓｎ層と、前記第１金属間化合物層と前記Ｃｕ－Ｓｎ層との間に位置し、ＰとＴｉを含有する第２金属間化合物層とを形成する第２加熱処理工程と、を備えていることを特徴としている。 A method of manufacturing a joined body according to one aspect of the present invention is a method of manufacturing a joined body of a ceramic member made of ceramic and a Cu member made of Cu or a Cu alloy, and includes a Cu—P—Sn-based brazing material and a Ti material. And laminating the ceramic member and the Cu member, and heating at a temperature lower than the melting start temperature of the Cu—P—Sn brazing material in the laminated state, A first heat treatment step of reacting a Ti material to form a first intermetallic compound layer having Cu and Ti, and after the first heat treatment step, a melting start temperature of the Cu-P-Sn brazing material or higher Between the second metal containing P and Ti, which is located between the Cu—Sn layer in which Sn is dissolved in Cu, the first intermetallic compound layer, and the Cu—Sn layer. Second heat treatment step for forming a compound layer It is characterized in that it comprises a.
　この構成の接合体の製造方法によれば、積層された状態で前記Ｃｕ－Ｐ－Ｓｎ系ろう材の溶融開始温度未満の温度で加熱し、前記Ｃｕ部材と前記Ｔｉ材とを反応させてＣｕとＴｉを含有する第１金属間化合物層を形成する第１加熱処理工程を備えているので、第１金属間化合物層を確実に形成して、Ｃｕ部材とＴｉ材とを確実に接合することができる。なお、この第１加熱処理工程ではＴｉ材の一部を残存させる。
　さらに、前記第１加熱処理工程後に、前記Ｃｕ－Ｐ－Ｓｎ系ろう材の溶融開始温度以上の温度で加熱し、ＳｎがＣｕ中に固溶したＣｕ－Ｓｎ層と、前記第１金属間化合物層と前記Ｃｕ－Ｓｎ層との間に位置し、ＰとＴｉを含有する第２金属間化合物層とを形成する第２加熱処理工程を備えているので、Ｔｉ材のＴｉをＣｕ－Ｐ－Ｓｎ系ろう材と反応させることで、第２金属間化合物層を形成でき、Ｃｕ部材とセラミックス部材とを確実に接合することができる。なお、この第２加熱処理工程では、Ｔｉ材のすべてを反応させてもよいし、一部を残存させて厚さ０．５μｍ以下のＴｉ層を形成してもよい。 According to the method for manufacturing a bonded body having this configuration, the Cu—P—Sn brazing material is heated at a temperature lower than the melting start temperature of the Cu—P—Sn brazing material to cause the Cu member and the Ti material to react with each other. Since the first heat treatment step for forming the first intermetallic compound layer containing Ti and Ti is provided, the first intermetallic compound layer is surely formed, and the Cu member and the Ti material are reliably bonded. Can do. In this first heat treatment step, a part of the Ti material is left.
Further, after the first heat treatment step, the Cu—P—Sn brazing material is heated at a temperature equal to or higher than the melting start temperature, and a Cu—Sn layer in which Sn is dissolved in Cu, and the first intermetallic compound Since the second heat treatment step of forming a second intermetallic compound layer containing P and Ti is provided between the layer and the Cu—Sn layer, the Ti of the Ti material is converted into Cu—P—. By reacting with the Sn-based brazing material, the second intermetallic compound layer can be formed, and the Cu member and the ceramic member can be reliably bonded. In the second heat treatment step, all of the Ti material may be reacted, or a part of the Ti material may be left to form a Ti layer having a thickness of 0.5 μm or less.
　ここで、上述の本発明の一態様である接合体の製造方法においては、前記第１加熱処理工程における加熱温度が５８０℃以上６７０℃以下の範囲内、加熱時間が３０分以上２４０分以下の範囲内とされていることが好ましい。
　この場合、加熱温度が５８０℃以上及び加熱時間が３０分以上とされているので、前記第１金属間化合物層を確実に形成することができる。一方、加熱温度が６７０℃以下及び加熱時間が２４０分以下とされているので、前記第１金属間化合物層が必要以上に厚く形成されることがなく、第１金属間化合物層における割れの発生を抑制することができる。 Here, in the manufacturing method of the joined body according to one aspect of the present invention, the heating temperature in the first heat treatment step is in a range of 580 ° C. or more and 670 ° C. or less, and the heating time is 30 minutes or more and 240 minutes or less. It is preferable to be within the range.
In this case, since the heating temperature is 580 ° C. or more and the heating time is 30 minutes or more, the first intermetallic compound layer can be reliably formed. On the other hand, since the heating temperature is 670 ° C. or less and the heating time is 240 minutes or less, the first intermetallic compound layer is not formed thicker than necessary, and cracks occur in the first intermetallic compound layer. Can be suppressed.
　また、本発明の一態様である接合体の製造方法は、セラミックスからなるセラミックス部材とＣｕ又はＣｕ合金からなるＣｕ部材との接合体の製造方法であって、前記Ｃｕ部材と前記Ｔｉ材とを積層した状態で加熱してＣｕとＴｉを拡散させ、Ｃｕ部材と前記Ｔｉ材との間にＣｕとＴｉを含有する第１金属間化合物層を形成するＣｕＴｉ拡散工程と、Ｃｕ－Ｐ－Ｓｎ系ろう材を介して、前記セラミックス部材と、前記第１金属間化合物層が形成された前記Ｔｉ材及び前記Ｃｕ部材と、を積層する積層工程と、前記Ｃｕ－Ｐ－Ｓｎ系ろう材の溶融開始温度以上の温度で加熱し、ＳｎがＣｕ中に固溶したＣｕ－Ｓｎ層と、前記第１金属間化合物層と前記Ｃｕ－Ｓｎ層との間に位置し、ＰとＴｉを含有する第２金属間化合物層とを形成する加熱処理工程と、を備えていることを特徴としている。 Moreover, the manufacturing method of the joined body which is 1 aspect of this invention is a manufacturing method of the joined body of the ceramic member which consists of ceramics, and Cu member which consists of Cu or Cu alloy, Comprising: Said Cu member and said Ti material A CuTi diffusion step in which Cu and Ti are diffused by heating in a laminated state to form a first intermetallic compound layer containing Cu and Ti between the Cu member and the Ti material; and a Cu-P-Sn system A laminating step of laminating the ceramic member, the Ti material on which the first intermetallic compound layer is formed, and the Cu member via a brazing material, and starting melting of the Cu—P—Sn based brazing material A second layer containing P and Ti, which is located between the Cu—Sn layer in which Sn is dissolved in Cu, the first intermetallic compound layer, and the Cu—Sn layer. Heat treatment for forming an intermetallic compound layer Is characterized by comprising the steps, a.
　この構成の接合体の製造方法によれば、前記Ｃｕ部材と前記Ｔｉ材とを積層した状態で加熱してＣｕとＴｉを拡散させ、Ｃｕ部材と前記Ｔｉ材との間にＣｕとＴｉを含有する第１金属間化合物層を形成するＣｕＴｉ拡散工程を備えているので、第１金属間化合物層を確実に形成することができる。なお、このＣｕＴｉ拡散工程ではＴｉ材の一部を残存させる。
　また、ＣｕＴｉ拡散工程では、ろう材を積層することなくＣｕ部材とＴｉ材を積層して加熱しているので、加熱条件を比較的自由に設定することができ、第１金属間化合物層を確実に形成することができるとともに、残存させるＴｉ材の厚さを精度良く調整することができる。
　さらに、Ｃｕ－Ｐ－Ｓｎ系ろう材を介して、前記セラミックス部材と、前記第１金属間化合物層が形成された前記Ｔｉ材及び前記Ｃｕ部材と、を積層する積層工程、前記Ｃｕ－Ｐ－Ｓｎ系ろう材の溶融開始温度以上の温度で加熱し、ＳｎがＣｕ中に固溶したＣｕ－Ｓｎ層と、前記第１金属間化合物層と前記Ｃｕ－Ｓｎ層との間に位置し、ＰとＴｉを含有する第２金属間化合物層とを形成する加熱処理工程を備えているので、Ｔｉ材のＴｉをＣｕ－Ｐ－Ｓｎ系ろう材と反応させることで、第２金属間化合物層を形成でき、Ｃｕ部材とセラミックス部材とを確実に接合することができる。なお、この第２加熱処理工程では、Ｔｉ材のすべてを反応させてもよいし、一部を残存させて厚さ０．５μｍ以下のＴｉ層を形成してもよい。 According to the method for manufacturing a bonded body having this configuration, the Cu member and the Ti material are heated in a stacked state to diffuse Cu and Ti, and Cu and Ti are contained between the Cu member and the Ti material. Since the CuTi diffusion step for forming the first intermetallic compound layer is provided, the first intermetallic compound layer can be reliably formed. In this CuTi diffusion step, a part of the Ti material is left.
Further, in the CuTi diffusion process, since the Cu member and the Ti material are laminated and heated without laminating the brazing material, the heating conditions can be set relatively freely, and the first intermetallic compound layer is surely secured. And the thickness of the remaining Ti material can be adjusted with high accuracy.
Further, a laminating step of laminating the ceramic member, the Ti material on which the first intermetallic compound layer is formed, and the Cu member via a Cu—P—Sn brazing material, the Cu—P— Heated at a temperature equal to or higher than the melting start temperature of the Sn-based brazing material, Sn is located between the Cu—Sn layer in which Cu is solid-solved in Cu, the first intermetallic compound layer, and the Cu—Sn layer, and P And a second intermetallic compound layer containing Ti, the second intermetallic compound layer is formed by reacting Ti of the Ti material with the Cu—P—Sn brazing material. It can form and can join a Cu member and a ceramic member reliably. In the second heat treatment step, all of the Ti material may be reacted, or a part of the Ti material may be left to form a Ti layer having a thickness of 0.5 μm or less.
　ここで、上述の本発明の一態様である接合体の製造方法においては、前記ＣｕＴｉ拡散工程における加熱温度が６００℃以上６７０℃以下の範囲内、加熱時間が３０分以上３６０分以下の範囲内とされていることが好ましい。
　この場合、加熱温度が６００℃以上及び加熱時間が３０分以上とされているので、前記第１金属間化合物層を確実に形成することができる。一方、加熱温度が６７０℃以下及び加熱時間が３６０分以下とされているので、前記第１金属間化合物層が必要以上に厚く形成されることがなく、第１金属間化合物層が割れの起点となることを抑制できる。 Here, in the manufacturing method of the joined body which is one aspect of the present invention, the heating temperature in the CuTi diffusion step is in the range of 600 ° C. or more and 670 ° C. or less, and the heating time is in the range of 30 minutes or more and 360 minutes or less. It is preferable that
In this case, since the heating temperature is 600 ° C. or more and the heating time is 30 minutes or more, the first intermetallic compound layer can be reliably formed. On the other hand, since the heating temperature is 670 ° C. or less and the heating time is 360 minutes or less, the first intermetallic compound layer is not formed thicker than necessary, and the first intermetallic compound layer is a starting point of cracking. Can be suppressed.
　また、上述の本発明の接合体の製造方法においては、前記ＣｕＴｉ拡散工程において、積層方向の荷重が０．２９４ＭＰａ以上１．９６ＭＰａ以下の範囲内とされていてもよい。
　この場合、荷重が０．２９４ＭＰａ以上１．９６ＭＰａ以下の範囲内とされているので、前記第１金属間化合物層を確実に形成することができ、接合強度をさらに高くすることができる。好ましくは、０．４９０ＭＰａ以上１．４７ＭＰａ以下、より好ましくは、１．１８ＭＰａ以上１．４７ＭＰａ以下の範囲内とするとよい。 Moreover, in the manufacturing method of the above-mentioned joined body of this invention, the load of the lamination direction may be in the range of 0.294 MPa or more and 1.96 MPa or less in the said CuTi diffusion process.
In this case, since the load is in the range of 0.294 MPa or more and 1.96 MPa or less, the first intermetallic compound layer can be reliably formed, and the bonding strength can be further increased. Preferably, it is 0.490 MPa or more and 1.47 MPa or less, and more preferably 1.18 MPa or more and 1.47 MPa or less.
　本発明の一態様であるパワーモジュール用基板の製造方法は、セラミックス基板の一方の面にＣｕ又はＣｕ合金からなる回路層が配設されたパワーモジュール用基板の製造方法であって、前記セラミックス基板と前記回路層を、上述の接合体の製造方法によって接合することを特徴としている。 A method for manufacturing a power module substrate according to an aspect of the present invention is a method for manufacturing a power module substrate in which a circuit layer made of Cu or a Cu alloy is disposed on one surface of a ceramic substrate, the ceramic substrate And the circuit layer are bonded by the above-described manufacturing method of the bonded body.
　この構成のパワーモジュール用基板の製造方法によれば、回路層とセラミックス基板の接合界面に、前記セラミックス基板側に位置し、ＳｎがＣｕ中に固溶したＣｕ－Ｓｎ層と、前記回路層側に位置し、ＣｕとＴｉを有する第１金属間化合物層と、前記第１金属間化合物層と前記Ｃｕ－Ｓｎ層との間に位置し、ＰとＴｉを含有する第２金属間化合物層と、を形成することができ、回路層とセラミックス基板とを確実に接合することができるとともに、積層方向の熱抵抗が低く効率的に放熱することが可能なパワーモジュール用基板を製造することができる。 According to the method for manufacturing a power module substrate having this structure, a Cu—Sn layer in which Sn is solid-solved in Cu at the bonding interface between the circuit layer and the ceramic substrate and Sn is dissolved in Cu, and the circuit layer side A first intermetallic compound layer containing Cu and Ti, a second intermetallic compound layer containing P and Ti, located between the first intermetallic compound layer and the Cu-Sn layer, , And the circuit layer and the ceramic substrate can be reliably bonded, and a power module substrate capable of efficiently dissipating heat with low thermal resistance in the stacking direction can be manufactured. .
　本発明の一態様であるパワーモジュール用基板の製造方法は、セラミックス基板の一方の面に回路層が配設され、前記セラミックス基板の他方の面にＣｕ又はＣｕ合金からなる金属層が配設されたパワーモジュール用基板の製造方法であって、前記セラミックス基板と前記金属層を、上述の接合体の製造方法によって接合することを特徴としている。 In the method for manufacturing a power module substrate according to one aspect of the present invention, a circuit layer is disposed on one surface of the ceramic substrate, and a metal layer made of Cu or a Cu alloy is disposed on the other surface of the ceramic substrate. A method for manufacturing a power module substrate, wherein the ceramic substrate and the metal layer are bonded together by the method for manufacturing a bonded body described above.
　この構成のパワーモジュール用基板の製造方法によれば、金属層とセラミックス基板の接合界面に、前記セラミックス基板側に位置し、ＳｎがＣｕ中に固溶したＣｕ－Ｓｎ層と、前記回路層側に位置し、ＣｕとＴｉを有する第１金属間化合物層と、前記第１金属間化合物層と前記Ｃｕ－Ｓｎ層との間に位置し、ＰとＴｉを含有する第２金属間化合物層と、を形成することができ、金属層とセラミックス基板とを確実に接合することができるとともに、積層方向の熱抵抗が低く効率的に放熱することが可能なパワーモジュール用基板を製造することができる。 According to the method for manufacturing a power module substrate having this structure, a Cu—Sn layer in which Sn is solid-solved in Cu at the bonding interface between the metal layer and the ceramic substrate, and Sn is dissolved in Cu, and the circuit layer side A first intermetallic compound layer containing Cu and Ti, a second intermetallic compound layer containing P and Ti, located between the first intermetallic compound layer and the Cu-Sn layer, , And the metal layer and the ceramic substrate can be reliably bonded, and a power module substrate capable of efficiently dissipating heat with low thermal resistance in the stacking direction can be manufactured. .
　本発明の一態様であるパワーモジュール用基板の製造方法は、セラミックス基板の一方の面にＣｕ又はＣｕ合金からなる回路層が配設され、前記セラミックス基板の他方の面にＡｌ又はＡｌ合金からなる金属層が配設されたパワーモジュール用基板の製造方法であって、前記セラミックス基板と前記回路層を、上述の接合体の製造方法によって接合することを特徴としている。 In the power module substrate manufacturing method according to one aspect of the present invention, a circuit layer made of Cu or a Cu alloy is disposed on one surface of a ceramic substrate, and the other surface of the ceramic substrate is made of Al or an Al alloy. A method for manufacturing a power module substrate in which a metal layer is disposed, wherein the ceramic substrate and the circuit layer are bonded together by the above-described manufacturing method of a bonded body.
　この構成のパワーモジュール用基板の製造方法によれば、回路層とセラミックス基板の接合界面に、前記セラミックス基板側に位置し、ＳｎがＣｕ中に固溶したＣｕ－Ｓｎ層と、前記回路層側に位置し、ＣｕとＴｉを有する第１金属間化合物層と、前記第１金属間化合物層と前記Ｃｕ－Ｓｎ層との間に位置し、ＰとＴｉを含有する第２金属間化合物層と、を形成することができ、回路層とセラミックス基板とを確実に接合することができるとともに、積層方向の熱抵抗が低く効率的に放熱することが可能なパワーモジュール用基板を製造することができる。
　また、比較的低温でＣｕ又はＣｕ合金からなる回路層とセラミックス基板とを接合できるので、Ｃｕ又はＣｕ合金からなる回路層と、セラミックス基板と、Ａｌ又はＡｌ合金からなる金属層と、を同時に接合することも可能となる。 According to the method for manufacturing a power module substrate having this structure, a Cu—Sn layer in which Sn is solid-solved in Cu at the bonding interface between the circuit layer and the ceramic substrate and Sn is dissolved in Cu, and the circuit layer side A first intermetallic compound layer containing Cu and Ti, a second intermetallic compound layer containing P and Ti, located between the first intermetallic compound layer and the Cu-Sn layer, , And the circuit layer and the ceramic substrate can be reliably bonded, and a power module substrate capable of efficiently dissipating heat with low thermal resistance in the stacking direction can be manufactured. .
In addition, since the circuit layer made of Cu or Cu alloy and the ceramic substrate can be bonded at a relatively low temperature, the circuit layer made of Cu or Cu alloy, the ceramic substrate, and the metal layer made of Al or Al alloy are bonded simultaneously. It is also possible to do.
　本発明によれば、セラミックス部材とＣｕ部材とが良好に接合され、かつ、積層方向の熱抵抗が低い接合体、パワーモジュール用基板、及び、この接合体の製造方法、パワーモジュール用基板の製造方法を提供することができる。 ADVANTAGE OF THE INVENTION According to this invention, the ceramic member and Cu member are joined favorably, and the joined body with low thermal resistance in the laminating direction, the power module substrate, the method for producing the joined body, and the production of the power module substrate A method can be provided.
本発明の第一実施形態に係るパワーモジュール用基板を用いたパワーモジュールの概略説明図である。It is a schematic explanatory drawing of the power module using the board | substrate for power modules which concerns on 1st embodiment of this invention. 本発明の第一実施形態に係るパワーモジュール用基板の概略説明図である。It is a schematic explanatory drawing of the board | substrate for power modules which concerns on 1st embodiment of this invention. 図２に示すパワーモジュール用基板の回路層とセラミックス基板との接合界面における断面の概略説明図である。It is a schematic explanatory drawing of the cross section in the joining interface of the circuit layer and ceramic substrate of the board | substrate for power modules shown in FIG. 本発明の第一実施形態に係るパワーモジュール用基板の製造方法及びパワーモジュールの製造方法を説明するフロー図である。It is a flowchart explaining the manufacturing method of the board | substrate for power modules which concerns on 1st embodiment of this invention, and the manufacturing method of a power module. 本発明の第一実施形態に係るパワーモジュール用基板の製造方法及びパワーモジュールの製造方法の概略説明図である。It is a schematic explanatory drawing of the manufacturing method of the board | substrate for power modules which concerns on 1st embodiment of this invention, and the manufacturing method of a power module. 本発明の第二実施形態に係るパワーモジュール用基板を用いたパワーモジュールの概略説明図である。It is a schematic explanatory drawing of the power module using the board for power modules concerning a second embodiment of the present invention. 本発明の第二実施形態に係るパワーモジュール用基板の概略説明図である。It is a schematic explanatory drawing of the board | substrate for power modules which concerns on 2nd embodiment of this invention. 図７に示すパワーモジュール用基板の回路層及び金属層とセラミックス基板との接合界面における断面の概略図である。It is the schematic of the cross section in the joining interface of the circuit layer and metal layer of a power module board | substrate shown in FIG. 7, and a ceramic substrate. 本発明の第二実施形態に係るパワーモジュール用基板の製造方法及びパワーモジュールの製造方法を説明するフロー図である。It is a flowchart explaining the manufacturing method of the board | substrate for power modules which concerns on 2nd embodiment of this invention, and the manufacturing method of a power module. 本発明の第二実施形態に係るパワーモジュール用基板の製造方法及びパワーモジュールの製造方法の概略説明図である。It is a schematic explanatory drawing of the manufacturing method of the board | substrate for power modules which concerns on 2nd embodiment of this invention, and the manufacturing method of a power module. 本発明の第三実施形態に係るパワーモジュール用基板を用いたパワーモジュールの概略説明図である。It is a schematic explanatory drawing of the power module using the board for power modules concerning a third embodiment of the present invention. 本発明の第三実施形態に係るパワーモジュール用基板の概略説明図である。It is a schematic explanatory drawing of the board | substrate for power modules which concerns on 3rd embodiment of this invention. 図１２に示すパワーモジュール用基板の回路層とセラミックス基板との接合界面における断面の概略図である。It is the schematic of the cross section in the joining interface of the circuit layer and ceramic substrate of the board | substrate for power modules shown in FIG. 本発明の第三実施形態に係るパワーモジュール用基板の製造方法及びパワーモジュールの製造方法を説明するフロー図である。It is a flowchart explaining the manufacturing method of the board | substrate for power modules which concerns on 3rd embodiment of this invention, and the manufacturing method of a power module. 本発明の第三実施形態に係るパワーモジュール用基板の製造方法及びパワーモジュールの製造方法の概略説明図である。It is a schematic explanatory drawing of the manufacturing method of the board | substrate for power modules which concerns on 3rd embodiment of this invention, and the manufacturing method of a power module.
（第一実施形態）
　以下に、本発明の実施形態について添付した図面を参照して説明する。まず、本発明の第一実施形態について説明する。
　本実施形態に係る接合体は、セラミックス部材であるセラミックス基板１１と、Ｃｕ部材であるＣｕ板２２（回路層１２）とが接合されてなるパワーモジュール用基板１０である。図１に、本実施形態であるパワーモジュール用基板１０を備えたパワーモジュール１を示す。
　このパワーモジュール１は、回路層１２が配設されたパワーモジュール用基板１０と、回路層１２の一方の面（図１において上面）に接合層２を介して接合された半導体素子３とを備えている。 (First embodiment)
Embodiments of the present invention will be described below with reference to the accompanying drawings. First, a first embodiment of the present invention will be described.
The joined body according to the present embodiment is a power module substrate 10 in which a ceramic substrate 11 that is a ceramic member and a Cu plate 22 (circuit layer 12) that is a Cu member are joined. In FIG. 1, the power module 1 provided with the board | substrate 10 for power modules which is this embodiment is shown.
The power module 1 includes a power module substrate 10 on which a circuit layer 12 is disposed, and a semiconductor element 3 bonded to one surface (upper surface in FIG. 1) of the circuit layer 12 via a bonding layer 2. ing.
　パワーモジュール用基板１０は、図２に示すように、セラミックス基板１１と、このセラミックス基板１１の一方の面（図２において上面）に配設された回路層１２とを備えている。
　セラミックス基板１１は、絶縁性の高いＡｌＮ（窒化アルミニウム）、Ｓｉ３Ｎ４（窒化ケイ素）、Ａｌ２Ｏ３（アルミナ）等のセラミックスで構成されている。本実施形態では、放熱性の優れたＡｌＮ（窒化アルミニウム）で構成されている。また、セラミックス基板１１の厚さは、０．２～１．５ｍｍの範囲内に設定されており、本実施形態では、０．６３５ｍｍに設定されている。 As shown in FIG. 2, the power module substrate 10 includes a ceramic substrate 11 and a circuit layer 12 disposed on one surface (the upper surface in FIG. 2) of the ceramic substrate 11.
The ceramic substrate 11 is made of ceramics such as AlN (aluminum nitride), Si 3 N 4 (silicon nitride), and Al 2 O 3 (alumina) having high insulating properties. In this embodiment, it is comprised with AlN (aluminum nitride) excellent in heat dissipation. Further, the thickness of the ceramic substrate 11 is set within a range of 0.2 to 1.5 mm, and in this embodiment is set to 0.635 mm.
　回路層１２は、セラミックス基板１１の一方の面に、導電性を有するＣｕ又はＣｕ合金の金属板が接合されることにより形成されている。
　本実施形態において、回路層１２は、セラミックス基板１１の一方の面に、Ｃｕ－Ｐ－Ｓｎ系ろう材２４と、Ｔｉ材２５が接合された無酸素銅からなるＣｕ板２２を積層して加熱処理し、セラミックス基板１１にＣｕ板２２を接合することで形成されている（図５参照）。なお、本実施形態では、Ｃｕ－Ｐ－Ｓｎ系ろう材２４として、Ｃｕ－Ｐ－Ｓｎ－Ｎｉろう材を用いている。
　ここで、回路層１２においてセラミックス基板１１側は、ＳｎがＣｕ中に拡散した構造となっている。
　なお、回路層１２の厚さは０．１ｍｍ以上１．０ｍｍ以下の範囲内に設定されており、本実施形態では、０．３ｍｍに設定されている。 The circuit layer 12 is formed by bonding a conductive metal plate of Cu or Cu alloy to one surface of the ceramic substrate 11.
In this embodiment, the circuit layer 12 is formed by laminating a Cu—P—Sn brazing material 24 and a Cu plate 22 made of oxygen-free copper bonded with a Ti material 25 on one surface of the ceramic substrate 11. It is formed by processing and bonding a Cu plate 22 to the ceramic substrate 11 (see FIG. 5). In the present embodiment, a Cu—P—Sn—Ni brazing material is used as the Cu—P—Sn brazing material 24.
Here, in the circuit layer 12, the ceramic substrate 11 side has a structure in which Sn is diffused in Cu.
Note that the thickness of the circuit layer 12 is set within a range of 0.1 mm or more and 1.0 mm or less, and is set to 0.3 mm in the present embodiment.
　図３に、セラミックス基板１１と回路層１２との接合界面の概略説明図を示す。セラミックス基板１１と回路層１２との接合界面には、図３に示すように、セラミックス基板１１側に位置するＣｕ－Ｓｎ層１４と、回路層１２側に位置し、ＣｕとＴｉを含有する第１金属間化合物層１６と、第１金属間化合物層１６とＣｕ－Ｓｎ層１４との間に位置し、Ｐ及びＴｉを含有する第２金属間化合物層１７と、が形成されている。 FIG. 3 shows a schematic explanatory diagram of the bonding interface between the ceramic substrate 11 and the circuit layer 12. As shown in FIG. 3, the bonding interface between the ceramic substrate 11 and the circuit layer 12 includes a Cu—Sn layer 14 located on the ceramic substrate 11 side, and a second layer containing Cu and Ti located on the circuit layer 12 side. A first intermetallic compound layer 16, and a second intermetallic compound layer 17 containing P and Ti, which are located between the first intermetallic compound layer 16 and the Cu—Sn layer 14, are formed.
　Ｃｕ－Ｓｎ層１４は、ＳｎがＣｕ中に固溶した層である。このＣｕ－Ｓｎ層１４は、Ｃｕ－Ｐ－Ｓｎ系ろう材２４に含まれるＰが、第２金属間化合物層１７に取り込まれることにより形成される層である。 The Cu—Sn layer 14 is a layer in which Sn is dissolved in Cu. The Cu—Sn layer 14 is a layer formed by incorporating P contained in the Cu—P—Sn brazing material 24 into the second intermetallic compound layer 17.
　第１金属間化合物層１６は、回路層１２のＣｕとＴｉ材２５のＴｉとが相互拡散することによって形成される層である。ここで、ＣｕとＴｉとの拡散は、固相拡散とされている。
　具体的には、第１金属間化合物層１６は、Ｃｕ４Ｔｉ相、Ｃｕ３Ｔｉ２相、Ｃｕ４Ｔｉ３相、ＣｕＴｉ相、ＣｕＴｉ２相のいずれか１種以上を有する。本実施形態においては、第１金属間化合物層１６は、Ｃｕ４Ｔｉ相、Ｃｕ３Ｔｉ２相、Ｃｕ４Ｔｉ３相、ＣｕＴｉ相、ＣｕＴｉ２相を有している。
　また、本実施形態においては、この第１金属間化合物層１６の厚さは、０．２μｍ以上６μｍ以下の範囲内とされている。 The first intermetallic compound layer 16 is a layer formed by mutual diffusion of Cu of the circuit layer 12 and Ti of the Ti material 25. Here, the diffusion of Cu and Ti is solid phase diffusion.
Specifically, the first intermetallic compound layer 16 has one or more of a Cu 4 Ti phase, a Cu 3 Ti 2 phase, a Cu 4 Ti 3 phase, a CuTi phase, and a CuTi 2 phase. In the present embodiment, the first intermetallic compound layer 16 has a Cu 4 Ti phase, a Cu 3 Ti 2 phase, a Cu 4 Ti 3 phase, a CuTi phase, and a CuTi 2 phase.
In the present embodiment, the thickness of the first intermetallic compound layer 16 is in the range of 0.2 μm to 6 μm.
　第２金属間化合物層１７は、Ｃｕ－Ｐ－Ｓｎ系ろう材２４に含まれるＰが、Ｔｉ材２５に含まれるＴｉと結合することにより形成される。本実施形態では、Ｃｕ－Ｐ－Ｓｎ系ろう材２４がＮｉを含んでいることから、この第２金属間化合物層１７は、Ｐ－Ｎｉ－Ｔｉ相、Ｐ－Ｔｉ相、Ｃｕ－Ｎｉ－Ｔｉ相のいずれか１種以上を有しており、具体的には、Ｐ－Ｎｉ－Ｔｉ相とされている。
　また、本実施形態においては、この第２金属間化合物層１７の厚さは、０．５μｍ以上４μｍ以下の範囲内とされている。 The second intermetallic compound layer 17 is formed by combining P contained in the Cu—P—Sn brazing material 24 with Ti contained in the Ti material 25. In this embodiment, since the Cu—P—Sn brazing material 24 contains Ni, the second intermetallic compound layer 17 is composed of a P—Ni—Ti phase, a P—Ti phase, a Cu—Ni—Ti. One or more of the phases are included, specifically, a P—Ni—Ti phase.
In the present embodiment, the thickness of the second intermetallic compound layer 17 is in the range of 0.5 μm to 4 μm.
　半導体素子３は、Ｓｉ等の半導体材料で構成されている。この半導体素子３と回路層１２は、接合層２を介して接合されている。
　接合層２は、例えばＳｎ－Ａｇ系、Ｓｎ－Ｉｎ系、若しくはＳｎ－Ａｇ－Ｃｕ系のはんだ材とされている。 The semiconductor element 3 is made of a semiconductor material such as Si. The semiconductor element 3 and the circuit layer 12 are bonded via the bonding layer 2.
The bonding layer 2 is made of, for example, a Sn—Ag, Sn—In, or Sn—Ag—Cu solder material.
　以下に、本実施形態に係るパワーモジュール用基板１０、及びパワーモジュール１の製造方法について、図４のフロー図及び図５を参照して説明する。
　まず、図５に示すように、回路層１２となるＣｕ板２２とＴｉ材２５とを積層し、積層方向に加圧（圧力１～３５ｋｇｆ／ｃｍ２）した状態で真空加熱炉内に配置し加熱して、Ｃｕ板２２とＴｉ材２５とを固相拡散接合させ、Ｃｕ－Ｔｉ接合体２７を得る。（ＣｕＴｉ拡散工程Ｓ０１）。 Below, the manufacturing method of the board | substrate 10 for power modules which concerns on this embodiment, and the power module 1 is demonstrated with reference to the flowchart of FIG. 4, and FIG.
First, as shown in FIG. 5, the Cu plate 22 and the Ti material 25 to be the circuit layer 12 are laminated and placed in a vacuum heating furnace in a state of being pressurized in the lamination direction (pressure 1 to 35 kgf / cm 2 ). By heating, the Cu plate 22 and the Ti material 25 are solid phase diffusion bonded to obtain a Cu—Ti bonded body 27. (CuTi diffusion step S01).
　なお、Ｔｉ材２５の厚さは、０．４μｍ以上５μｍ以下の範囲内とされている。ここで、Ｔｉ材２５は、厚さが０．４μｍ以上１μｍ未満の場合には蒸着やスパッタによって成膜することが好ましく、厚さが１μｍ以上５μｍ以下の場合には箔材を用いることが好ましい。なお、Ｔｉ材２５の厚さの下限は０．４μｍ以上とすることが好ましく、０．５μｍ以上とすることがさらに好ましい。また、Ｔｉ材２５の厚さの上限は１．５μｍ以下とすることが好ましく、０．７μｍ以下とすることがさらに好ましい。本実施形態においては、Ｔｉ材２５として、厚さ１μｍ、純度９９．８ｍａｓｓ％のＴｉ箔を用いた。 Note that the thickness of the Ti material 25 is in the range of 0.4 μm to 5 μm. Here, the Ti material 25 is preferably formed by vapor deposition or sputtering when the thickness is 0.4 μm or more and less than 1 μm, and the foil material is preferably used when the thickness is 1 μm or more and 5 μm or less. . The lower limit of the thickness of the Ti material 25 is preferably 0.4 μm or more, and more preferably 0.5 μm or more. The upper limit of the thickness of the Ti material 25 is preferably 1.5 μm or less, and more preferably 0.7 μm or less. In the present embodiment, a Ti foil having a thickness of 1 μm and a purity of 99.8 mass% was used as the Ti material 25.
　このＣｕＴｉ拡散工程Ｓ０１によって得られるＣｕ－Ｔｉ接合体２７においては、Ｔｉ材２５とＣｕ板２２とが固相拡散接合によって接合され、Ｃｕ板２２と中間Ｔｉ層２６の積層構造となっている。ここで、中間Ｔｉ層２６とＣｕ板２２との間には、ＣｕとＴｉを含有する中間第１金属間化合物層が形成される。このとき、Ｔｉ材２５がすべて中間第１金属間化合物層の形成に消費されず、その一部が残存する。
　ここで、本実施形態では、中間Ｔｉ層２６の厚さは、０．１μｍ以上３μｍ以下の範囲内とされている。なお、中間Ｔｉ層２６の厚さの下限は０．２μｍ以上とすることが好ましく、０．４μｍ以上とすることがさらに好ましい。また、中間Ｔｉ層２６の厚さの上限は１．５μｍ以下とすることが好ましく、１μｍ以下とすることがさらに好ましい。
　さらに、中間第１金属間化合物層の厚さは、０．１μｍ以上６μｍ以下とすることが好ましい。 In the Cu—Ti joined body 27 obtained by the CuTi diffusion step S01, the Ti material 25 and the Cu plate 22 are joined by solid phase diffusion joining, and a laminated structure of the Cu plate 22 and the intermediate Ti layer 26 is formed. Here, an intermediate first intermetallic compound layer containing Cu and Ti is formed between the intermediate Ti layer 26 and the Cu plate 22. At this time, all of the Ti material 25 is not consumed for forming the intermediate first intermetallic compound layer, and a part thereof remains.
Here, in the present embodiment, the thickness of the intermediate Ti layer 26 is in the range of 0.1 μm to 3 μm. Note that the lower limit of the thickness of the intermediate Ti layer 26 is preferably 0.2 μm or more, and more preferably 0.4 μm or more. The upper limit of the thickness of the intermediate Ti layer 26 is preferably 1.5 μm or less, and more preferably 1 μm or less.
Furthermore, it is preferable that the thickness of the intermediate first intermetallic compound layer is 0.1 μm or more and 6 μm or less.
　また、ＣｕＴｉ拡散工程Ｓ０１においては、真空加熱炉内の圧力は１０－６Ｐａ以上１０－３Ｐａ以下の範囲内に、加熱温度は６００℃以上６７０℃以下の範囲内に、加熱時間は３０分以上３６０分以下の範囲内に設定している。
　ここで、ＣｕＴｉ拡散工程Ｓ０１において、加熱温度を６００℃以上及び加熱時間を３０分以上とすることで中間第１金属間化合物層を十分に形成することが可能となる。また、加熱温度を６７０℃以下及び加熱時間を３６０分以下とすることで中間第１金属間化合物層が必要以上に厚く形成されることを抑制できる。 In the CuTi diffusion step S01, the pressure in the vacuum heating furnace is in the range of 10 −6 Pa to 10 −3 Pa, the heating temperature is in the range of 600 ° C. to 670 ° C., and the heating time is 30 minutes. It is set within the range of 360 minutes or less.
Here, in the CuTi diffusion step S01, the intermediate first intermetallic compound layer can be sufficiently formed by setting the heating temperature to 600 ° C. or more and the heating time to 30 minutes or more. Moreover, it can suppress that an intermediate | middle 1st intermetallic compound layer is formed thickly more than necessary by heating temperature being 670 degrees C or less and heating time being 360 minutes or less.
　なお、加熱温度の下限は６１０℃以上とすることが好ましく６２０℃以上とすることがさらに好ましい。加熱温度の上限は６５０℃以下とすることが好ましく６４０℃以下とすることがさらに好ましい。また、加熱時間の下限は１５分以上とすることが好ましく６０分以上とすることがさらに好ましい。加熱時間の上限は１２０分以下とすることが好ましく９０分以下とすることがさらに好ましい。 The lower limit of the heating temperature is preferably 610 ° C. or higher, and more preferably 620 ° C. or higher. The upper limit of the heating temperature is preferably 650 ° C. or less, more preferably 640 ° C. or less. The lower limit of the heating time is preferably 15 minutes or more, and more preferably 60 minutes or more. The upper limit of the heating time is preferably 120 minutes or less, and more preferably 90 minutes or less.
　なお、Ｃｕ板２２とＴｉ材２５とをさらに強固に接合するためには、ＣｕＴｉ拡散工程Ｓ０１において、積層方向への加圧荷重を０．２９４ＭＰａ以上１．９６ＭＰａ以下（３ｋｇｆ／ｃｍ２以上２０ｋｇｆ／ｃｍ２以下）の範囲内とすることが好ましい。より好ましくは、０．４９０ＭＰａ以上１．４７ＭＰａ以下、さらに好ましくは、１．１８ＭＰａ以上１．４７ＭＰａ以下の範囲内とするとよい。 In addition, in order to join the Cu plate 22 and the Ti material 25 more firmly, in the CuTi diffusion step S01, the pressure load in the stacking direction is 0.294 MPa to 1.96 MPa (3 kgf / cm 2 to 20 kgf / It is preferable to be within the range of cm 2 or less. More preferably, it is 0.490 MPa or more and 1.47 MPa or less, More preferably, it is good to set it in the range of 1.18 MPa or more and 1.47 MPa or less.
　次に、セラミックス基板１１の一方の面（図５において上面）に、Ｃｕ－Ｐ－Ｓｎ系ろう材２４、Ｃｕ－Ｔｉ接合体２７を順に積層する（積層工程Ｓ０２）。ここで、Ｃｕ－Ｔｉ接合体２７は、中間Ｔｉ層２６とＣｕ－Ｐ－Ｓｎ系ろう材２４が対向するように積層される。
　本実施形態においては、Ｃｕ－Ｐ－Ｓｎ系ろう材２４の組成は、Ｃｕ－７ｍａｓｓ％Ｐ－１５ｍａｓｓ％Ｓｎ－１０ｍａｓｓ％Ｎｉとされており、その固相線温度（溶融開始温度）は５８０℃とされている。また、Ｃｕ－Ｐ－Ｓｎ系ろう材２４は箔材を用い、その厚さは、５μｍ以上１５０μｍ以下の範囲内とされている。 Next, the Cu—P—Sn brazing material 24 and the Cu—Ti joined body 27 are sequentially laminated on one surface (the upper surface in FIG. 5) of the ceramic substrate 11 (lamination step S02). Here, the Cu—Ti joined body 27 is laminated so that the intermediate Ti layer 26 and the Cu—P—Sn brazing material 24 face each other.
In this embodiment, the composition of the Cu—P—Sn brazing material 24 is Cu-7 mass% P-15 mass% Sn-10 mass% Ni, and its solidus temperature (melting start temperature) is 580 ° C. It is said that. The Cu—P—Sn brazing material 24 is made of a foil material and has a thickness in the range of 5 μm to 150 μm.
　次に、セラミックス基板１１、Ｃｕ－Ｐ－Ｓｎ系ろう材２４、Ｃｕ－Ｔｉ接合体２７を積層方向に加圧（圧力１～３５ｋｇｆ／ｃｍ２）した状態で、真空加熱炉内に装入して加熱する（加熱処理工程Ｓ０３）。
　ここで、本実施形態では、加熱処理工程Ｓ０３における条件として、真空加熱炉内の圧力は１０－６Ｐａ以上１０－３Ｐａ以下の範囲内に、加熱温度は６００℃以上７００℃以下の範囲内に、加熱時間は１５分以上１２０分以下の範囲内に設定している。 Next, the ceramic substrate 11, the Cu—P—Sn brazing material 24, and the Cu—Ti joined body 27 are charged in the stacking direction (pressure 1 to 35 kgf / cm 2 ) and placed in a vacuum heating furnace. And heated (heat treatment step S03).
Here, in the present embodiment, as the conditions in the heat treatment step S03, the pressure in the vacuum heating furnace is in the range of 10 −6 Pa to 10 −3 Pa, and the heating temperature is in the range of 600 ° C. to 700 ° C. In addition, the heating time is set within a range of 15 minutes to 120 minutes.
　この加熱処理工程Ｓ０３においては、Ｃｕ－Ｐ－Ｓｎ系ろう材２４が溶融して液相を形成し、この液相に中間Ｔｉ層２６が溶け込み、液相が凝固することにより、セラミックス基板１１とＣｕ板２２とが接合される。このとき、Ｃｕ－Ｐ－Ｓｎ系ろう材２４中に含まれるＰ及びＮｉは、中間Ｔｉ層２６のＴｉと結合し、第２金属間化合物層１７が形成されるとともに、セラミックス基板１１側にはＣｕ－Ｓｎ層１４が形成される。なお、第１金属間化合物層１６は、中間第１金属間化合物層が残存することによって形成される。 In this heat treatment step S03, the Cu—P—Sn brazing material 24 is melted to form a liquid phase, the intermediate Ti layer 26 is dissolved in this liquid phase, and the liquid phase is solidified. The Cu plate 22 is joined. At this time, P and Ni contained in the Cu—P—Sn-based brazing material 24 are combined with Ti in the intermediate Ti layer 26 to form the second intermetallic compound layer 17 and on the ceramic substrate 11 side. A Cu—Sn layer 14 is formed. The first intermetallic compound layer 16 is formed by leaving the intermediate first intermetallic compound layer.
　なお、本実施形態においては、中間Ｔｉ層２６の厚さが、０．１μｍ以上３μｍ以下の範囲内とされているので、この中間Ｔｉ層２６がＣｕ－Ｐ－Ｓｎ系ろう材２４の液相中にすべて溶け込み、セラミックス基板１１と回路層１２との接合界面において、中間Ｔｉ層２６が残存しない。
　これにより、セラミックス基板１１の一方の面に回路層１２が形成され、本実施形態であるパワーモジュール用基板１０が製造される。 In this embodiment, since the thickness of the intermediate Ti layer 26 is in the range of 0.1 μm or more and 3 μm or less, the intermediate Ti layer 26 is a liquid phase of the Cu—P—Sn brazing material 24. All of it melts into the intermediate Ti layer 26 at the bonding interface between the ceramic substrate 11 and the circuit layer 12.
As a result, the circuit layer 12 is formed on one surface of the ceramic substrate 11, and the power module substrate 10 according to this embodiment is manufactured.
　次に、パワーモジュール用基板１０の回路層１２の上面に、はんだ材を介して半導体素子３を接合する（半導体素子接合工程Ｓ０４）。
　このようにして、本実施形態に係るパワーモジュール１が製造される。 Next, the semiconductor element 3 is bonded to the upper surface of the circuit layer 12 of the power module substrate 10 via a solder material (semiconductor element bonding step S04).
In this way, the power module 1 according to this embodiment is manufactured.
　以上のような構成とされた本実施形態に係るパワーモジュール用基板１０によれば、セラミックス基板１１と回路層１２との接合界面において、回路層１２側に位置し、ＣｕとＴｉを含有する第１金属間化合物層１６が形成されているので、この第１金属間化合物層１６を介することで回路層１２と第２金属間化合物層１７とを確実に接合することができる。よって、使用環境温度が高くなっても回路層１２とセラミックス基板１１との接合強度を確保することができる。
　また、セラミックス基板１１と回路層１２との接合界面にＴｉ層が形成されていないので、回路層１２とセラミックス基板１１の積層方向における熱抵抗を低く抑えることが可能となり、回路層１２上に搭載された半導体素子３から発生する熱を効率的に放熱することができる。 According to the power module substrate 10 according to the present embodiment having the above-described configuration, the bonding interface between the ceramic substrate 11 and the circuit layer 12 is located on the circuit layer 12 side and contains Cu and Ti. Since the first intermetallic compound layer 16 is formed, the circuit layer 12 and the second intermetallic compound layer 17 can be reliably bonded via the first intermetallic compound layer 16. Therefore, the bonding strength between the circuit layer 12 and the ceramic substrate 11 can be ensured even when the use environment temperature becomes high.
Further, since the Ti layer is not formed at the bonding interface between the ceramic substrate 11 and the circuit layer 12, the thermal resistance in the stacking direction of the circuit layer 12 and the ceramic substrate 11 can be suppressed, and the circuit layer 12 is mounted on the circuit layer 12. The heat generated from the semiconductor element 3 can be efficiently radiated.
　また、本実施形態においては、第１金属間化合物層１６の厚さが０．２μｍ以上とされているので、回路層１２とセラミックス基板１１との接合強度を確実に向上させることができる。一方、第１金属間化合物層１６の厚さが６μｍ以下とされているので、この第１金属間化合物層１６における割れの発生を抑制することができる。
　なお、回路層１２とセラミックス基板１１との接合強度を確実に向上させるためには、第１金属間化合物層１６の厚さの下限を０．５μｍ以上とすることが好ましく、１μｍ以上とすることがさらに好ましい。また、第１金属間化合物層１６における割れの発生を確実に抑制するためには、第１金属間化合物層１６の厚さの上限を５μｍ以下とすることが好ましく、３μｍ以下とすることがさらに好ましい。なお、第１金属間化合物層１６の厚さは、加熱処理工程Ｓ０３における加熱によってＴｉの拡散が進み、中間第１金属間化合物層の厚さより厚くなる場合もある。 Moreover, in this embodiment, since the thickness of the 1st intermetallic compound layer 16 shall be 0.2 micrometer or more, the joining strength of the circuit layer 12 and the ceramic substrate 11 can be improved reliably. On the other hand, since the thickness of the first intermetallic compound layer 16 is 6 μm or less, the occurrence of cracks in the first intermetallic compound layer 16 can be suppressed.
In order to improve the bonding strength between the circuit layer 12 and the ceramic substrate 11 with certainty, the lower limit of the thickness of the first intermetallic compound layer 16 is preferably 0.5 μm or more, and preferably 1 μm or more. Is more preferable. Moreover, in order to suppress the generation | occurrence | production of the crack in the 1st intermetallic compound layer 16 reliably, it is preferable to make the upper limit of the thickness of the 1st intermetallic compound layer 16 into 5 micrometers or less, and also to set it as 3 micrometers or less. preferable. Note that the thickness of the first intermetallic compound layer 16 may be thicker than the thickness of the intermediate first intermetallic compound layer due to the diffusion of Ti by heating in the heat treatment step S03.
　さらに、本実施形態においては、第２金属間化合物層１７の厚さが０．５μｍ以上とされているので、回路層１２とセラミックス基板１１との接合強度を確実に向上させることができる。一方、第２金属間化合物層１７の厚さが４μｍ以下とされているので、この第２金属間化合物層１７における割れの発生を抑制することができる。
　なお、回路層１２とセラミックス基板１１との接合強度を確実に向上させるためには、第２金属間化合物層１７の厚さの下限を１μｍ以上とすることが好ましく、２μｍ以上とすることがさらに好ましい。また、第２金属間化合物層１７における割れの発生を確実に抑制するためには、第２金属間化合物層１７の厚さの上限を３．５μｍ以下とすることが好ましく、３μｍ以下とすることがさらに好ましい。 Furthermore, in this embodiment, since the thickness of the second intermetallic compound layer 17 is 0.5 μm or more, the bonding strength between the circuit layer 12 and the ceramic substrate 11 can be reliably improved. On the other hand, since the thickness of the second intermetallic compound layer 17 is 4 μm or less, the occurrence of cracks in the second intermetallic compound layer 17 can be suppressed.
In order to reliably improve the bonding strength between the circuit layer 12 and the ceramic substrate 11, the lower limit of the thickness of the second intermetallic compound layer 17 is preferably 1 μm or more, and more preferably 2 μm or more. preferable. Moreover, in order to suppress the generation | occurrence | production of the crack in the 2nd intermetallic compound layer 17 reliably, it is preferable to make the upper limit of the thickness of the 2nd intermetallic compound layer 17 into 3.5 micrometers or less, and to set it as 3 micrometers or less. Is more preferable.
　また、本実施形態のパワーモジュール用基板の製造方法においては、回路層１２となるＣｕ板２２とＴｉ材２５とを積層し、積層方向に加圧（圧力１～３５ｋｇｆ／ｃｍ２）した状態で真空加熱炉内に配置し加熱して、Ｃｕ板２２とＴｉ材２５とを固相拡散接合させ、Ｃｕ－Ｔｉ接合体２７を得るＣｕＴｉ拡散工程Ｓ０１を備えているので、Ｃｕ板２２と中間Ｔｉ層２６の間に、ＣｕとＴｉを含有する中間第１金属間化合物層を確実に形成することができる。 Further, in the method for manufacturing the power module substrate of the present embodiment, the Cu plate 22 that becomes the circuit layer 12 and the Ti material 25 are stacked and pressed in the stacking direction (pressure 1 to 35 kgf / cm 2 ). Since there is a CuTi diffusion step S01 in which the Cu plate 22 and the Ti material 25 are placed in a vacuum heating furnace and heated to cause solid phase diffusion bonding to obtain a Cu—Ti joined body 27, the Cu plate 22 and intermediate Ti are provided. An intermediate first intermetallic compound layer containing Cu and Ti can be reliably formed between the layers 26.
　また、中間Ｔｉ層２６の厚さが、０．１μｍ以上３μｍ以下の範囲内とされているので、後工程の加熱処理工程Ｓ０３において、中間Ｔｉ層２６とＣｕ－Ｐ－Ｓｎ系ろう材２４とを反応させることが可能となる。
　さらに、ＣｕＴｉ拡散工程Ｓ０１においては、Ｃｕ板２２とＴｉ材２５とを積層して加熱しており、Ｃｕ－Ｐ－Ｓｎ系ろう材２４を積層していないので、加熱温度及び加熱時間を比較的自由に設定することが可能となる。 In addition, since the thickness of the intermediate Ti layer 26 is in the range of 0.1 μm or more and 3 μm or less, the intermediate Ti layer 26 and the Cu—P—Sn brazing material 24 Can be reacted.
Further, in the CuTi diffusion step S01, the Cu plate 22 and the Ti material 25 are laminated and heated, and the Cu—P—Sn brazing material 24 is not laminated. It can be set freely.
　さらに、本実施形態のパワーモジュール用基板の製造方法においては、セラミックス基板１１、Ｃｕ－Ｐ－Ｓｎ系ろう材２４、Ｃｕ－Ｔｉ接合体２７を積層方向に加圧（圧力１～３５ｋｇｆ／ｃｍ２）した状態で、真空加熱炉内に装入して加熱する加熱処理工程Ｓ０３を備えているので、中間Ｔｉ層２６のＴｉをＣｕ－Ｐ－Ｓｎ系ろう材２４と反応させることで、第２金属間化合物層１７を形成でき、回路層１２とセラミックス基板１１とを確実に接合することができる。 Furthermore, in the method for manufacturing a power module substrate of the present embodiment, the ceramic substrate 11, the Cu—P—Sn brazing material 24, and the Cu—Ti joined body 27 are pressurized in the stacking direction (pressure 1 to 35 kgf / cm 2). In this state, the heat treatment step S03 is performed in which the heat treatment is performed by charging in a vacuum heating furnace, so that the second Ti can be reacted with the Cu—P—Sn brazing material 24 by reacting the Ti of the intermediate Ti layer 26 with the second heat treatment step 24. The intermetallic compound layer 17 can be formed, and the circuit layer 12 and the ceramic substrate 11 can be reliably bonded.
　ここで、加熱処理工程Ｓ０３において、加圧される圧力が１ｋｇｆ／ｃｍ２以上の場合、セラミックス基板１１とＣｕ－Ｐ－Ｓｎ系ろう材２４との液相を密着させることができ、セラミックス基板１１とＣｕ－Ｓｎ層１４とを良好に接合できる。また、加圧される圧力が３５ｋｇｆ／ｃｍ２以下の場合、セラミックス基板１１に割れが発生することを抑制できる。このような理由のため、本実施形態では、加圧される圧力は１ｋｇｆ／ｃｍ２以上３５ｋｇｆ／ｃｍ２以下の範囲内に設定されている。 Here, in the heat treatment step S03, when the pressure applied is 1 kgf / cm 2 or more, the liquid phase of the ceramic substrate 11 and the Cu—P—Sn brazing material 24 can be brought into close contact, and the ceramic substrate 11 And the Cu—Sn layer 14 can be bonded satisfactorily. Moreover, when the pressurized pressure is 35 kgf / cm 2 or less, the occurrence of cracks in the ceramic substrate 11 can be suppressed. For this reason, in the present embodiment, the pressure pressurized is set to 1 kgf / cm 2 or more 35 kgf / cm 2 within the following ranges.
（第二実施形態）
　次に、本発明の第二実施形態について説明する。なお、第一実施形態と同一の構成のものについては、同一の符号を付して記載し、詳細な説明を省略する。
　図６に、第二実施形態に係るパワーモジュール用基板１１０を備えたパワーモジュール１０１を示す。
　このパワーモジュール１０１は、回路層１１２及び金属層１１３が配設されたパワーモジュール用基板１１０と、回路層１１２の一方の面（図６において上面）に接合層２を介して接合された半導体素子３と、金属層１１３の他方側（図６において下側）に配置されたヒートシンク１３０と、を備えている。 (Second embodiment)
Next, a second embodiment of the present invention will be described. In addition, about the thing of the same structure as 1st embodiment, the same code | symbol is attached | subjected and described, and detailed description is abbreviate | omitted.
FIG. 6 shows a power module 101 including the power module substrate 110 according to the second embodiment.
This power module 101 includes a power module substrate 110 on which a circuit layer 112 and a metal layer 113 are disposed, and a semiconductor element bonded to one surface (upper surface in FIG. 6) of the circuit layer 112 via a bonding layer 2. 3 and a heat sink 130 disposed on the other side of the metal layer 113 (lower side in FIG. 6).
　パワーモジュール用基板１１０は、図７に示すように、セラミックス基板１１と、このセラミックス基板１１の一方の面（図７において上面）に配設された回路層１１２と、セラミックス基板１１の他方の面（図７において下面）に配設された金属層１１３と、を備えている。
　セラミックス基板１１は、第一実施形態と同様に、放熱性の優れたＡｌＮ（窒化アルミニウム）で構成されている。 As shown in FIG. 7, the power module substrate 110 includes a ceramic substrate 11, a circuit layer 112 disposed on one surface of the ceramic substrate 11 (upper surface in FIG. 7), and the other surface of the ceramic substrate 11. And a metal layer 113 disposed on the lower surface in FIG.
As in the first embodiment, the ceramic substrate 11 is made of AlN (aluminum nitride) with excellent heat dissipation.
　回路層１１２は、第一実施形態と同様に、セラミックス基板１１の一方の面にＣｕ－Ｐ－Ｓｎ系ろう材１２４、Ｔｉ材２５、無酸素銅からなるＣｕ板１２２を順に積層して加熱処理し、セラミックス基板１１にＣｕ板１２２を接合することで形成されている（図１０参照）。
　なお、回路層１１２の厚さは０．１ｍｍ以上１．０ｍｍ以下の範囲内に設定されており、本実施形態では、０．３ｍｍに設定されている。 As in the first embodiment, the circuit layer 112 is formed by sequentially laminating a Cu—P—Sn-based brazing material 124, a Ti material 25, and a Cu plate 122 made of oxygen-free copper on one surface of the ceramic substrate 11, and performing a heat treatment. Then, it is formed by bonding a Cu plate 122 to the ceramic substrate 11 (see FIG. 10).
The thickness of the circuit layer 112 is set within a range of 0.1 mm or more and 1.0 mm or less, and is set to 0.3 mm in the present embodiment.
　金属層１１３は、セラミックス基板１１の他方の面に、Ｃｕ又はＣｕ合金の金属板が、Ｃｕ－Ｐ－Ｓｎ系ろう材１２４を介して接合されることにより形成されている。本実施形態において、金属層１１３は、セラミックス基板１１の他方の面にＣｕ－Ｐ－Ｓｎ系ろう材１２４、Ｔｉ材２５、無酸素銅からなるＣｕ板１２３を積層して加熱処理し、セラミックス基板１１にＣｕ板１２３を接合することで形成されている（図１０参照）。
　この金属層１１３の厚さは０．１ｍｍ以上１．０ｍｍ以下の範囲内に設定されており、本実施形態では、０．３ｍｍに設定されている。
　ここで、本実施形態では、Ｃｕ－Ｐ－Ｓｎ系ろう材１２４として、具体的にはＣｕ－Ｐ－Ｓｎ－Ｎｉろう材を用いている。 The metal layer 113 is formed by bonding a Cu or Cu alloy metal plate to the other surface of the ceramic substrate 11 via a Cu—P—Sn brazing material 124. In the present embodiment, the metal layer 113 is formed by laminating a Cu-P-Sn-based brazing material 124, a Ti material 25, and a Cu plate 123 made of oxygen-free copper on the other surface of the ceramic substrate 11, and heat-treating the ceramic substrate. 11 is formed by bonding a Cu plate 123 (see FIG. 10).
The thickness of the metal layer 113 is set within a range of 0.1 mm or more and 1.0 mm or less, and is set to 0.3 mm in the present embodiment.
Here, in this embodiment, a Cu—P—Sn—Ni brazing material is specifically used as the Cu—P—Sn brazing material 124.
　図８に、セラミックス基板１１と回路層１１２（金属層１１３）との接合界面の概略説明図を示す。セラミックス基板１１と回路層１１２（金属層１１３）との接合界面には、図８に示すように、セラミックス基板１１１側に位置するＣｕ－Ｓｎ層１４と、回路層１１２（金属層１１３）側に位置し、ＣｕとＴｉを含有する第１金属間化合物層１６と、第１金属間化合物層１６とＣｕ－Ｓｎ層１４との間に位置し、Ｐ及びＴｉを含有する第２金属間化合物層１７と、が形成されている。 FIG. 8 is a schematic explanatory diagram of the bonding interface between the ceramic substrate 11 and the circuit layer 112 (metal layer 113). As shown in FIG. 8, at the bonding interface between the ceramic substrate 11 and the circuit layer 112 (metal layer 113), the Cu—Sn layer 14 located on the ceramic substrate 111 side and the circuit layer 112 (metal layer 113) side are provided. A first intermetallic compound layer 16 located between Cu and Ti, and a second intermetallic compound layer located between the first intermetallic compound layer 16 and the Cu—Sn layer 14 and containing P and Ti. 17 are formed.
　ここで、本実施形態では、第１金属間化合物層１６と第２金属間化合物層１７との間に、Ｔｉ層１５が形成されており、このＴｉ層１５の厚さが０．５μｍ以下とされている。
　また、本実施形態においては、第１金属間化合物層１６の厚さは、０．２μｍ以上６μｍ以下の範囲内とされている。
　さらに、本実施形態においては、第２金属間化合物層１７の厚さは、０．５μｍ以上４μｍ以下の範囲内とされている。 Here, in the present embodiment, a Ti layer 15 is formed between the first intermetallic compound layer 16 and the second intermetallic compound layer 17, and the thickness of the Ti layer 15 is 0.5 μm or less. Has been.
In the present embodiment, the thickness of the first intermetallic compound layer 16 is in the range of 0.2 μm to 6 μm.
Furthermore, in the present embodiment, the thickness of the second intermetallic compound layer 17 is in the range of 0.5 μm to 4 μm.
　ヒートシンク１３０は、前述のパワーモジュール用基板１１０からの熱を放散する。このヒートシンク１３０は、Ｃｕ又はＣｕ合金で構成されており、本実施形態ではりん脱酸銅で構成されている。このヒートシンク１３０には、冷却用の流体が流れるための流路１３１が設けられている。なお、本実施形態においては、ヒートシンク１３０と金属層１１３とが、はんだ材からなるはんだ層１３２によって接合されている。 The heat sink 130 dissipates heat from the power module substrate 110 described above. The heat sink 130 is made of Cu or Cu alloy, and is made of phosphorous deoxidized copper in this embodiment. The heat sink 130 is provided with a flow path 131 through which a cooling fluid flows. In the present embodiment, the heat sink 130 and the metal layer 113 are joined by a solder layer 132 made of a solder material.
　以下に、本実施形態に係るパワーモジュール１０１の製造方法について、図９のフロー図及び図１０を参照して説明する。
　まず、図１０に示すように、セラミックス基板１１の一方の面（図１０において上面）に、Ｃｕ－Ｐ－Ｓｎ系ろう材１２４、Ｔｉ材２５、及び回路層１１２となるＣｕ板１２２を順に積層するとともに、セラミックス基板１１の他方の面（図１０において下面）に、Ｃｕ－Ｐ－Ｓｎ系ろう材１２４、Ｔｉ材２５、及び金属層１１３となるＣｕ板１２３を順に積層する（積層工程Ｓ１０１）。すなわち、セラミックス基板１１とＣｕ板１２２及びＣｕ板１２３の間において、セラミックス基板１１側にＣｕ－Ｐ－Ｓｎ系ろう材１２４を配置し、Ｃｕ板１２２，１２３側にＴｉ材２５を配置している。 Below, the manufacturing method of the power module 101 which concerns on this embodiment is demonstrated with reference to the flowchart of FIG. 9, and FIG.
First, as shown in FIG. 10, a Cu—P—Sn brazing material 124, a Ti material 25, and a Cu plate 122 to be a circuit layer 112 are sequentially laminated on one surface (the upper surface in FIG. 10) of the ceramic substrate 11. At the same time, the Cu—P—Sn brazing material 124, the Ti material 25, and the Cu plate 123 to be the metal layer 113 are sequentially laminated on the other surface (the lower surface in FIG. 10) of the ceramic substrate 11 (lamination step S101). . That is, between the ceramic substrate 11 and the Cu plate 122 and Cu plate 123, the Cu—P—Sn brazing material 124 is disposed on the ceramic substrate 11 side, and the Ti material 25 is disposed on the Cu plates 122 and 123 side. .
　本実施形態においては、Ｃｕ－Ｐ－Ｓｎ系ろう材１２４の組成は、Ｃｕ－６．３ｍａｓｓ％Ｐ－９．３ｍａｓｓ％Ｓｎ－７ｍａｓｓ％Ｎｉとされており、その固相線温度（溶融開始温度）は６００℃とされている。また、Ｃｕ－Ｐ－Ｓｎ系ろう材１２４は箔材を用い、その厚さは、５μｍ以上１５０μｍ以下の範囲内とされている。 In the present embodiment, the composition of the Cu—P—Sn brazing material 124 is Cu—6.3 mass%, P—9.3 mass%, Sn—7 mass% Ni, and the solidus temperature (melting start temperature). ) Is 600 ° C. The Cu—P—Sn brazing material 124 is made of a foil material and has a thickness in the range of 5 μm to 150 μm.
　また、Ｔｉ材２５の厚さは、０．４μｍ以上５μｍ以下の範囲内とされている。ここで、Ｔｉ材２５は、厚さが０．４μｍ以上１μｍ未満の場合には蒸着やスパッタによって成膜することが好ましく、厚さが１μｍ以上５μｍ以下の場合には箔材を用いることが好ましい。なお、Ｔｉ材２５の厚さの下限は０．４μｍ以上とすることが好ましく０．５μｍ以上とすることがさらに好ましい。Ｔｉ材２５の厚さの上限は１．５μｍ以下とすることが好ましく、０．７μｍ以下とすることがさらに好ましい。本実施形態においては、Ｔｉ材２５として、厚さ１μｍ、純度９９．８ｍａｓｓ％のＴｉ箔を用いた。 Further, the thickness of the Ti material 25 is in the range of 0.4 μm to 5 μm. Here, the Ti material 25 is preferably formed by vapor deposition or sputtering when the thickness is 0.4 μm or more and less than 1 μm, and the foil material is preferably used when the thickness is 1 μm or more and 5 μm or less. . The lower limit of the thickness of the Ti material 25 is preferably 0.4 μm or more, and more preferably 0.5 μm or more. The upper limit of the thickness of the Ti material 25 is preferably 1.5 μm or less, and more preferably 0.7 μm or less. In the present embodiment, a Ti foil having a thickness of 1 μm and a purity of 99.8 mass% was used as the Ti material 25.
　次に、Ｃｕ板１２２、Ｔｉ材２５、Ｃｕ－Ｐ－Ｓｎ系ろう材１２４、セラミックス基板１１、Ｃｕ－Ｐ－Ｓｎ系ろう材１２４、Ｔｉ材２５、及びＣｕ板１２３を、積層方向に加圧（圧力１ｋｇｆ／ｃｍ２以上３５ｋｇｆ／ｃｍ２以下）した状態で、真空加熱炉内に装入し、Ｃｕ－Ｐ－Ｓｎ系ろう材１２４の溶融開始温度未満の温度で加熱する（第１加熱処理工程Ｓ１０２）。 Next, the Cu plate 122, the Ti material 25, the Cu—P—Sn brazing material 124, the ceramic substrate 11, the Cu—P—Sn based brazing material 124, the Ti material 25, and the Cu plate 123 are pressed in the stacking direction. (pressure 1 kgf / cm 2 or more 35 kgf / cm 2 or less) in a state, charged into a vacuum heating furnace, heating at a temperature below the melting initiation temperature of the Cu-P-Sn based brazing material 124 (first heat treatment Step S102).
　この第１加熱処理工程Ｓ１０２においては、Ｔｉ材２５とＣｕ板１２２及びＴｉ材２５とＣｕ板１２３が固相拡散接合によって接合され、Ｔｉ材２５とＣｕ板１２２との間及びＴｉ材２５とＣｕ板１２３との間にＣｕとＴｉを含有する第１金属間化合物層１６がそれぞれ形成される。 In the first heat treatment step S102, the Ti material 25 and the Cu plate 122, and the Ti material 25 and the Cu plate 123 are joined by solid phase diffusion bonding, and between the Ti material 25 and the Cu plate 122 and between the Ti material 25 and the Cu plate 122. A first intermetallic compound layer 16 containing Cu and Ti is formed between the plate 123 and the plate 123.
　ここで、本実施形態では、真空加熱炉内の圧力は１０－６Ｐａ以上１０－３Ｐａ以下の範囲内に、加熱温度は５８０℃以上６７０℃以下の範囲内に、加熱時間は３０分以上２４０分以下の範囲内に設定している。なお、Ｃｕ－Ｐ－Ｓｎ系ろう材１２４の溶融を確実に抑制するためには、第１加熱処理工程Ｓ１０２における加熱温度は、Ｃｕ－Ｐ－Ｓｎ系ろう材１２４の溶融開始温度（固相線温度）－１０℃とすることが好ましい。
　第１加熱処理工程Ｓ１０２において、加熱温度を５８０℃以上及び加熱時間を３０分以上とすることで第１金属間化合物層１６を十分に形成することが可能となる。また、加熱温度を６７０℃以下及び加熱時間を２４０分以下とすることで第１金属間化合物層１６が必要以上に厚く形成されることを抑制できる。
　なお、加熱温度の下限は６１０℃以上とすることが好ましく６２０℃以上とすることがさらに好ましい。加熱温度の上限は６５０℃以下とすることが好ましく６４０℃以下とすることがさらに好ましい。また、加熱時間の下限は１５分以上とすることが好ましく６０分以上とすることがさらに好ましい。加熱時間の上限は１２０分以下とすることが好ましく９０分以下とすることがさらに好ましい。 Here, in this embodiment, the pressure in the vacuum heating furnace is in the range of 10 −6 Pa to 10 −3 Pa, the heating temperature is in the range of 580 ° C. to 670 ° C., and the heating time is 30 minutes or more. It is set within the range of 240 minutes or less. In order to reliably suppress the melting of the Cu—P—Sn brazing material 124, the heating temperature in the first heat treatment step S102 is set to the melting start temperature (solidus line) of the Cu—P—Sn brazing material 124. Temperature) is preferably −10 ° C.
In the first heat treatment step S102, the first intermetallic compound layer 16 can be sufficiently formed by setting the heating temperature to 580 ° C. or more and the heating time to 30 minutes or more. Moreover, it can suppress that the 1st intermetallic compound layer 16 is formed more thickly than necessary by making heating temperature into 670 degrees C or less and heating time to 240 minutes or less.
The lower limit of the heating temperature is preferably 610 ° C. or higher, and more preferably 620 ° C. or higher. The upper limit of the heating temperature is preferably 650 ° C. or less, more preferably 640 ° C. or less. The lower limit of the heating time is preferably 15 minutes or more, and more preferably 60 minutes or more. The upper limit of the heating time is preferably 120 minutes or less, and more preferably 90 minutes or less.
　次に、第１加熱処理工程Ｓ１０２後に、Ｃｕ板１２２、Ｔｉ材２５、Ｃｕ－Ｐ－Ｓｎ系ろう材１２４、セラミックス基板１１、Ｃｕ－Ｐ－Ｓｎ系ろう材１２４、Ｔｉ材２５、及びＣｕ板１２３を積層方向に加圧（圧力１ｋｇｆ／ｃｍ２以上３５ｋｇｆ／ｃｍ２以下）した状態でＣｕ－Ｐ－Ｓｎ系ろう材１２４の溶融開始温度以上の温度で加熱する（第２加熱処理工程Ｓ１０３）。ここで、本実施形態では、真空加熱炉内の圧力は１０－６Ｐａ以上１０－３Ｐａ以下の範囲内に、加熱温度は６００℃以上７００℃以下の範囲内に、加熱時間は１５分以上１２０分以下の範囲内に設定している。ここで、第２加熱処理工程Ｓ１０３では、Ｃｕ－Ｐ－Ｓｎ系ろう材１２４を確実に溶融させるため、Ｃｕ－Ｐ－Ｓｎ系ろう材１２４の固相線温度＋１０℃以上で加熱することが好ましい。 Next, after the first heat treatment step S102, the Cu plate 122, the Ti material 25, the Cu—P—Sn brazing material 124, the ceramic substrate 11, the Cu—P—Sn based brazing material 124, the Ti material 25, and the Cu plate. pressure 123 in the stacking direction (pressure 1 kgf / cm 2 or more 35 kgf / cm 2 or less) in a state heated at the melting start temperature or higher of Cu-P-Sn based brazing material 124 (second heat treatment step S103) . Here, in this embodiment, the pressure in the vacuum heating furnace is in the range of 10 −6 Pa to 10 −3 Pa, the heating temperature is in the range of 600 ° C. to 700 ° C., and the heating time is 15 minutes or more. It is set within the range of 120 minutes or less. Here, in the second heat treatment step S103, in order to reliably melt the Cu—P—Sn brazing material 124, it is preferable to heat the Cu—P—Sn brazing material 124 at a solidus temperature of + 10 ° C. or higher. .
　この第２加熱処理工程Ｓ１０３においては、Ｃｕ－Ｐ－Ｓｎ系ろう材１２４が溶融して液相を形成し、この液相にＴｉ材２５が溶け込み、液相が凝固することにより、セラミックス基板１１とＣｕ板１２２及びセラミックス基板１１とＣｕ板１２３が接合される。このとき、Ｃｕ－Ｐ－Ｓｎ系ろう材１２４中に含まれるＰ及びＮｉは、Ｔｉ材２５のＴｉと結合し、第２金属間化合物層１７が形成されるとともに、セラミックス基板１１側にはＣｕ－Ｓｎ層１４が形成される。 In the second heat treatment step S103, the Cu—P—Sn brazing material 124 is melted to form a liquid phase, the Ti material 25 is dissolved in the liquid phase, and the liquid phase is solidified. Cu plate 122 and ceramic substrate 11 and Cu plate 123 are joined together. At this time, P and Ni contained in the Cu—P—Sn based brazing material 124 are bonded to Ti of the Ti material 25 to form the second intermetallic compound layer 17, and on the ceramic substrate 11 side, Cu -The Sn layer 14 is formed.
　なお、本実施形態においては、Ｔｉ材２５の一部がＣｕ－Ｐ－Ｓｎ系ろう材１２４の液相中に溶け込まずに残存し、第１金属間化合物層１６と第２金属間化合物層１７との間にＴｉ層１５が形成される。
　これにより、セラミックス基板１１の一方の面に回路層１１２が形成されるとともに、他方の面に金属層１１３が形成され、本実施形態であるパワーモジュール用基板１１０が製造される。 In the present embodiment, a part of the Ti material 25 remains without being dissolved in the liquid phase of the Cu—P—Sn brazing material 124, and the first intermetallic compound layer 16 and the second intermetallic compound layer 17. Ti layer 15 is formed between the two.
Thus, the circuit layer 112 is formed on one surface of the ceramic substrate 11 and the metal layer 113 is formed on the other surface, and the power module substrate 110 according to the present embodiment is manufactured.
　次いで、パワーモジュール用基板１１０の金属層１１３の下面に、はんだ材を介してヒートシンク１３０を接合する（ヒートシンク接合工程Ｓ１０４）。
　次に、パワーモジュール用基板１１０の回路層１１２の上面に、はんだ材を介して半導体素子３を接合する（半導体素子接合工程Ｓ１０５）。
　このようにして、本実施形態に係るパワーモジュール１０１が製造される。 Next, the heat sink 130 is bonded to the lower surface of the metal layer 113 of the power module substrate 110 via a solder material (heat sink bonding step S104).
Next, the semiconductor element 3 is bonded to the upper surface of the circuit layer 112 of the power module substrate 110 via a solder material (semiconductor element bonding step S105).
In this way, the power module 101 according to this embodiment is manufactured.
　以上のような構成とされた本実施形態に係るパワーモジュール用基板１１０においては、セラミックス基板１１と回路層１１２との接合界面及びセラミックス基板１１と金属層１１３との接合界面において、回路層１１２側及び金属層１１３側に位置し、ＣｕとＴｉを含有する第１金属間化合物層１６が形成されているので、この第１金属間化合物層１６を介することで回路層１１２と第２金属間化合物層１７及び金属層１１３と第２金属間化合物層１７とを確実に接合することができる。よって、使用環境温度が高くなっても回路層１１２とセラミックス基板１１及び金属層１１３とセラミックス基板１１との接合強度を確保することができる。 In the power module substrate 110 according to the present embodiment configured as described above, the circuit layer 112 side at the bonding interface between the ceramic substrate 11 and the circuit layer 112 and at the bonding interface between the ceramic substrate 11 and the metal layer 113. Since the first intermetallic compound layer 16 containing Cu and Ti is formed on the metal layer 113 side, the circuit layer 112 and the second intermetallic compound are interposed via the first intermetallic compound layer 16. The layer 17 and the metal layer 113 and the second intermetallic compound layer 17 can be reliably bonded. Therefore, the bonding strength between the circuit layer 112 and the ceramic substrate 11 and the metal layer 113 and the ceramic substrate 11 can be ensured even when the use environment temperature becomes high.
　また、セラミックス基板１１と回路層１１２との接合界面及びセラミックス基板１１と金属層１１３との接合界面に、Ｔｉ層１５が形成されているがその厚さが０．５μｍ以下とされているので、回路層１１２とセラミックス基板１１と金属層１１３の積層方向における熱抵抗を低く抑えることが可能となり、回路層１１２上に搭載された半導体素子３から発生する熱を効率的に放熱することができる。 In addition, although the Ti layer 15 is formed at the bonding interface between the ceramic substrate 11 and the circuit layer 112 and the bonding interface between the ceramic substrate 11 and the metal layer 113, the thickness is 0.5 μm or less. The thermal resistance in the stacking direction of the circuit layer 112, the ceramic substrate 11, and the metal layer 113 can be kept low, and the heat generated from the semiconductor element 3 mounted on the circuit layer 112 can be efficiently radiated.
　また、本実施形態においては、第１金属間化合物層１６の厚さが０．２μｍ以上とされているので、回路層１１２とセラミックス基板１１及び金属層１１３とセラミックス基板１１との接合強度を確実に向上させることができる。一方、第１金属間化合物層１６の厚さが６μｍ以下とされているので、この第１金属間化合物層１６における割れの発生を抑制することができる。 In this embodiment, since the thickness of the first intermetallic compound layer 16 is 0.2 μm or more, the bonding strength between the circuit layer 112 and the ceramic substrate 11 and between the metal layer 113 and the ceramic substrate 11 is ensured. Can be improved. On the other hand, since the thickness of the first intermetallic compound layer 16 is 6 μm or less, the occurrence of cracks in the first intermetallic compound layer 16 can be suppressed.
　さらに、本実施形態においては、第２金属間化合物層１７の厚さが０．５μｍ以上とされているので、回路層１１２とセラミックス基板１１及び金属層１１３とセラミックス基板１１との接合強度を確実に向上させることができる。一方、第２金属間化合物層１７の厚さが４μｍ以下とされているので、この第２金属間化合物層１７における割れの発生を抑制することができる。 Furthermore, in this embodiment, since the thickness of the second intermetallic compound layer 17 is 0.5 μm or more, the bonding strength between the circuit layer 112 and the ceramic substrate 11 and between the metal layer 113 and the ceramic substrate 11 is ensured. Can be improved. On the other hand, since the thickness of the second intermetallic compound layer 17 is 4 μm or less, the occurrence of cracks in the second intermetallic compound layer 17 can be suppressed.
　また、本実施形態のパワーモジュール用基板の製造方法においては、Ｃｕ板１２２、Ｔｉ材２５、Ｃｕ－Ｐ－Ｓｎ系ろう材１２４、セラミックス基板１１、Ｃｕ－Ｐ－Ｓｎ系ろう材１２４、Ｔｉ材２５、及びＣｕ板１２３を積層方向に加圧（圧力１ｋｇｆ／ｃｍ２以上３５ｋｇｆ／ｃｍ２以下）した状態で、真空加熱炉内に装入し、Ｃｕ－Ｐ－Ｓｎ系ろう材１２４の溶融開始温度未満の温度で加熱する第１加熱処理工程Ｓ１０２を備えているので、回路層１１２となるＣｕ板１２２とＴｉ材２５の間及び金属層１１３となるＣｕ板１２３とＴｉ材２５との間に、ＣｕとＴｉを含有する第１金属間化合物層１６を確実に形成することができる。 Further, in the method for manufacturing the power module substrate of the present embodiment, the Cu plate 122, the Ti material 25, the Cu—P—Sn brazing material 124, the ceramic substrate 11, the Cu—P—Sn based brazing material 124, the Ti material. 25, and the Cu plate 123 in the laminating direction to the pressure (pressure 1 kgf / cm 2 or more 35 kgf / cm 2 or less) condition, and charged in a vacuum heating furnace, the melting start of Cu-P-Sn based brazing material 124 Since the first heat treatment step S102 for heating at a temperature lower than the temperature is provided, between the Cu plate 122 that becomes the circuit layer 112 and the Ti material 25 and between the Cu plate 123 that becomes the metal layer 113 and the Ti material 25. The first intermetallic compound layer 16 containing Cu and Ti can be reliably formed.
　さらに、本実施形態のパワーモジュール用基板の製造方法においては、第１加熱処理工程Ｓ１０２後に、Ｃｕ－Ｐ－Ｓｎ系ろう材１２４の溶融開始温度以上の温度で加熱し、ＳｎがＣｕ中に固溶したＣｕ－Ｓｎ層１４と、第１金属間化合物層１６とＣｕ－Ｓｎ層１４との間に位置し、ＰとＴｉを含有する第２金属間化合物層１７とを形成する第２加熱処理工程Ｓ１０３を備えているので、Ｔｉ材２５のＴｉをＣｕ－Ｐ－Ｓｎ系ろう材１２４と反応させることで、第２金属間化合物層１７を形成でき、回路層１１２とセラミックス基板１１及び金属層１１３とセラミックス基板１１とを確実に接合することができる。 Furthermore, in the method for manufacturing a power module substrate of the present embodiment, after the first heat treatment step S102, heating is performed at a temperature equal to or higher than the melting start temperature of the Cu—P—Sn brazing material 124, and Sn is solidified in Cu. Second heat treatment for forming a melted Cu—Sn layer 14, and a second intermetallic compound layer 17 containing P and Ti, which is located between the first intermetallic compound layer 16 and the Cu—Sn layer 14. Since the step S103 is provided, the second intermetallic compound layer 17 can be formed by reacting the Ti of the Ti material 25 with the Cu—P—Sn brazing material 124, and the circuit layer 112, the ceramic substrate 11, and the metal layer can be formed. 113 and the ceramic substrate 11 can be reliably bonded.
　ここで、第２加熱処理工程Ｓ１０３において、加圧される圧力が１ｋｇｆ／ｃｍ２以上の場合、セラミックス基板１１とＣｕ－Ｐ－Ｓｎ系ろう材１２４との液相を密着させることができ、セラミックス基板１１とＣｕ－Ｓｎ層１４とを良好に接合できる。また、加圧される圧力が３５ｋｇｆ／ｃｍ２以下の場合、セラミックス基板１１に割れが発生することを抑制できる。このような理由のため、本実施形態では、加圧される圧力は１ｋｇｆ／ｃｍ２以上３５ｋｇｆ／ｃｍ２以下の範囲内に設定されている。 Here, in the second heat treatment step S103, when the pressure applied is 1 kgf / cm 2 or more, the liquid phase of the ceramic substrate 11 and the Cu—P—Sn brazing material 124 can be brought into close contact with each other. The substrate 11 and the Cu—Sn layer 14 can be bonded satisfactorily. Moreover, when the pressurized pressure is 35 kgf / cm 2 or less, the occurrence of cracks in the ceramic substrate 11 can be suppressed. For this reason, in the present embodiment, the pressure pressurized is set to 1 kgf / cm 2 or more 35 kgf / cm 2 within the following ranges.
　また、本実施形態に係るパワーモジュール用基板１１０の製造方法によれば、セラミックス基板１１の一方の面に回路層１１２を、他方の面に金属層１１３を同時に接合する構成とされているので、製造工程を簡略化し、製造コストを低減できる。 Further, according to the method for manufacturing the power module substrate 110 according to the present embodiment, the circuit layer 112 is bonded to one surface of the ceramic substrate 11 and the metal layer 113 is bonded to the other surface at the same time. The manufacturing process can be simplified and the manufacturing cost can be reduced.
（第三実施形態）
　次に、本発明の第三実施形態について説明する。なお、第一実施形態と同一の構成のものについては、同一の符号を付して記載し、詳細な説明を省略する。
　図１１に、第三実施形態に係るパワーモジュール用基板２１０を備えたパワーモジュール２０１を示す。
　このパワーモジュール２０１は、回路層２１２及び金属層２１３が配設されたパワーモジュール用基板２１０と、回路層２１２の一方の面（図１１において上面）に接合層２を介して接合された半導体素子３と、パワーモジュール用基板２１０の他方側（図１１において下側）に接合されたヒートシンク２３０と、を備えている。 (Third embodiment)
Next, a third embodiment of the present invention will be described. In addition, about the thing of the same structure as 1st embodiment, the same code | symbol is attached | subjected and described, and detailed description is abbreviate | omitted.
FIG. 11 shows a power module 201 including a power module substrate 210 according to the third embodiment.
This power module 201 includes a power module substrate 210 on which a circuit layer 212 and a metal layer 213 are disposed, and a semiconductor element bonded to one surface (upper surface in FIG. 11) of the circuit layer 212 via a bonding layer 2. 3 and a heat sink 230 bonded to the other side (lower side in FIG. 11) of the power module substrate 210.
　パワーモジュール用基板２１０は、図１２に示すように、セラミックス基板１１と、このセラミックス基板１１の一方の面（図１２において上面）に配設された回路層２１２と、セラミックス基板１１の他方の面（図１２において下面）に配設された金属層２１３と、を備えている。
　セラミックス基板１１は、第一実施形態と同様に、放熱性の優れたＡｌＮ（窒化アルミニウム）で構成されている。 As shown in FIG. 12, the power module substrate 210 includes a ceramic substrate 11, a circuit layer 212 disposed on one surface (the upper surface in FIG. 12) of the ceramic substrate 11, and the other surface of the ceramic substrate 11. And a metal layer 213 disposed on the lower surface in FIG.
As in the first embodiment, the ceramic substrate 11 is made of AlN (aluminum nitride) with excellent heat dissipation.
　回路層２１２は、第一実施形態と同様に、セラミックス基板１１の一方の面にＣｕ－Ｐ－Ｓｎ系ろう材２２４、Ｔｉ材２５、無酸素銅からなるＣｕ板２２２を積層して加熱処理し、セラミックス基板１１にＣｕ板２２２を接合することで形成されている（図１５参照）。
　なお、回路層２１２の厚さは０．１ｍｍ以上１．０ｍｍ以下の範囲内に設定されており、本実施形態では、０．３ｍｍに設定されている。
　ここで、本実施形態では、Ｃｕ－Ｐ－Ｓｎ系ろう材２２４として、具体的にはＣｕ－Ｐ－Ｓｎ－Ｎｉろう材を用いている。 As in the first embodiment, the circuit layer 212 is formed by laminating a Cu-P-Sn-based brazing material 224, a Ti material 25, and a Cu plate 222 made of oxygen-free copper on one surface of the ceramic substrate 11, and heat-treating it. It is formed by bonding a Cu plate 222 to the ceramic substrate 11 (see FIG. 15).
The thickness of the circuit layer 212 is set within a range of 0.1 mm or more and 1.0 mm or less, and is set to 0.3 mm in the present embodiment.
Here, in the present embodiment, a Cu—P—Sn—Ni brazing material is specifically used as the Cu—P—Sn brazing material 224.
　そして、セラミックス基板１１と回路層２１２との接合界面には、図１３に示すように、セラミックス基板１１側に位置するＣｕ－Ｓｎ層１４と、回路層２１２側に位置し、ＣｕとＴｉを含有する第１金属間化合物層１６と、第１金属間化合物層１６とＣｕ－Ｓｎ層１４との間に位置し、Ｐ及びＴｉを含有する第２金属間化合物層１７と、が形成されている。
　また、第１金属間化合物層１６と第２金属間化合物層１７との間に、Ｔｉ層１５が形成されており、このＴｉ層１５の厚さが０．５μｍ以下とされている。 As shown in FIG. 13, the bonding interface between the ceramic substrate 11 and the circuit layer 212 includes a Cu—Sn layer 14 located on the ceramic substrate 11 side and a Cu—Ti layer located on the circuit layer 212 side. And a second intermetallic compound layer 17 that is located between the first intermetallic compound layer 16 and the Cu—Sn layer 14 and contains P and Ti is formed. .
A Ti layer 15 is formed between the first intermetallic compound layer 16 and the second intermetallic compound layer 17, and the thickness of the Ti layer 15 is 0.5 μm or less.
　金属層２１３は、セラミックス基板１１の他方の面に、Ａｌ又はＡｌ合金からなるＡｌ板が接合されることにより形成されている。本実施形態において、金属層２１３は、セラミックス基板１１の他方の面に、純度９９．９９ｍａｓｓ％以上のＡｌ板２２３を接合することで形成されている（図１５参照）。
　この金属層２１３の厚さは０．１ｍｍ以上３．０ｍｍ以下の範囲内に設定されており、本実施形態では、１．６ｍｍに設定されている。 The metal layer 213 is formed by bonding an Al plate made of Al or an Al alloy to the other surface of the ceramic substrate 11. In the present embodiment, the metal layer 213 is formed by bonding an Al plate 223 having a purity of 99.99 mass% or more to the other surface of the ceramic substrate 11 (see FIG. 15).
The thickness of the metal layer 213 is set within a range of 0.1 mm to 3.0 mm, and is set to 1.6 mm in the present embodiment.
　ヒートシンク２３０は、Ａｌ又はＡｌ合金で構成されており、本実施形態ではＡ６０６３（Ａｌ合金）で構成されている。このヒートシンク２３０には、冷却用の流体が流れるための流路２３１が設けられている。なお、このヒートシンク２３０と金属層２１３とが、Ａｌ－Ｓｉ系ろう材によって接合されている。 The heat sink 230 is made of Al or an Al alloy, and is made of A6063 (Al alloy) in the present embodiment. The heat sink 230 is provided with a flow path 231 through which a cooling fluid flows. The heat sink 230 and the metal layer 213 are joined by an Al—Si brazing material.
　次に、本実施形態に係るパワーモジュール２０１の製造方法について、図１４のフロー図及び図１５を参照して説明する。
　まず、図１５に示すように、回路層２１２となるＣｕ板２２２とＴｉ材２５とを積層し、積層方向に加圧（圧力１～３５ｋｇｆ／ｃｍ２）した状態で真空加熱炉内に配置し加熱して、Ｃｕ板２２２とＴｉ材２５とを固相拡散接合させ、Ｃｕ－Ｔｉ接合体２２７を得る。（ＣｕＴｉ拡散工程Ｓ２０１）。 Next, a method for manufacturing the power module 201 according to the present embodiment will be described with reference to the flowchart of FIG. 14 and FIG.
First, as shown in FIG. 15, a Cu plate 222 and a Ti material 25 to be the circuit layer 212 are laminated, and placed in a vacuum heating furnace in a state of being pressurized (pressure 1 to 35 kgf / cm 2 ) in the lamination direction. By heating, the Cu plate 222 and the Ti material 25 are solid phase diffusion bonded to obtain a Cu—Ti bonded body 227. (CuTi diffusion step S201).
　なお、Ｔｉ材２５の厚さは、０．４μｍ以上５μｍ以下の範囲内とされている。ここで、Ｔｉ材２５は、厚さが０．４μｍ以上１μｍ未満の場合には蒸着やスパッタによって成膜することが好ましく、厚さが１μｍ以上５μｍ以下の場合には箔材を用いることが好ましい。なお、Ｔｉ材２５の厚さの下限は０．４μｍ以上とすることが好ましく、０．５μｍ以上とすることがさらに好ましい。また、Ｔｉ材２５の厚さの上限は１.５μｍ以下とすることが好ましく、０．７μｍ以下とすることがさらに好ましい。本実施形態においては、Ｔｉ材２５として、厚さ１．４μｍ、純度９９．８ｍａｓｓ％のＴｉ箔を用いた。 Note that the thickness of the Ti material 25 is in the range of 0.4 μm to 5 μm. Here, the Ti material 25 is preferably formed by vapor deposition or sputtering when the thickness is 0.4 μm or more and less than 1 μm, and the foil material is preferably used when the thickness is 1 μm or more and 5 μm or less. . The lower limit of the thickness of the Ti material 25 is preferably 0.4 μm or more, and more preferably 0.5 μm or more. Further, the upper limit of the thickness of the Ti material 25 is preferably 1.5 μm or less, and more preferably 0.7 μm or less. In the present embodiment, a Ti foil having a thickness of 1.4 μm and a purity of 99.8 mass% is used as the Ti material 25.
　また、ＣｕＴｉ拡散工程Ｓ２０１においては、真空加熱炉内の圧力は１０－６Ｐａ以上１０－３Ｐａ以下の範囲内に、加熱温度は６００℃以上６７０℃以下の範囲内に、加熱時間は３０分以上３６０分以下の範囲内に設定している。ここで、ＣｕＴｉ拡散工程Ｓ２０１において、加熱温度を６００℃以上及び加熱時間を３０分以上とすることで中間第１金属間化合物層を十分に形成することが可能となる。また、加熱温度を６５５℃以下及び加熱時間を３６０分以下とすることで中間第１金属間化合物層が必要以上に厚く形成されることを抑制できる。
　なお、加熱温度の下限は６１０℃以上とすることが好ましく６２０℃以上とすることがさらに好ましい。加熱温度の上限は６５０℃以下とすることが好ましく６４０℃以下とすることがさらに好ましい。また、加熱時間の下限は１５分以上とすることが好ましく６０分以上とすることがさらに好ましい。加熱時間の上限は１２０分以下とすることが好ましく９０分以下とすることがさらに好ましい。 In the CuTi diffusion step S201, the pressure in the vacuum heating furnace is in the range of 10 −6 Pa to 10 −3 Pa, the heating temperature is in the range of 600 ° C. to 670 ° C., and the heating time is 30 minutes. It is set within the range of 360 minutes or less. Here, in the CuTi diffusion step S201, the intermediate first intermetallic compound layer can be sufficiently formed by setting the heating temperature to 600 ° C. or more and the heating time to 30 minutes or more. Moreover, it can suppress that an intermediate | middle 1st intermetallic compound layer is formed thickly more than necessary by heating temperature being 655 degrees C or less and heating time being 360 minutes or less.
The lower limit of the heating temperature is preferably 610 ° C. or higher, and more preferably 620 ° C. or higher. The upper limit of the heating temperature is preferably 650 ° C. or less, more preferably 640 ° C. or less. The lower limit of the heating time is preferably 15 minutes or more, and more preferably 60 minutes or more. The upper limit of the heating time is preferably 120 minutes or less, and more preferably 90 minutes or less.
　なお、Ｃｕ板２２２とＴｉ材２５とをさらに強固に接合するためには、ＣｕＴｉ拡散工程Ｓ２０１において、積層方向への加圧荷重を０．２９４ＭＰａ以上１．９６ＭＰａ以下（３ｋｇｆ／ｃｍ２以上２０ｋｇｆ／ｃｍ２以下）の範囲内とすることが好ましい。より好ましくは、０．４９０ＭＰａ以上１．４７ＭＰａ以下、さらに好ましくは、１．１８ＭＰａ以上１．４７ＭＰａ以下の範囲内とするとよい。 In order to join the Cu plate 222 and the Ti material 25 more firmly, in the CuTi diffusion step S201, the pressure load in the stacking direction is 0.294 MPa to 1.96 MPa (3 kgf / cm 2 to 20 kgf / It is preferable to be within the range of cm 2 or less. More preferably, it is 0.490 MPa or more and 1.47 MPa or less, More preferably, it is good to set it in the range of 1.18 MPa or more and 1.47 MPa or less.
　このＣｕＴｉ拡散工程Ｓ２０１によって得られるＣｕ－Ｔｉ接合体２２７においては、Ｔｉ材２５とＣｕ板２２２とが固相拡散接合によって接合され、Ｃｕ板２２２と中間Ｔｉ層２６の積層構造となっている。ここで、中間Ｔｉ層２６とＣｕ板２２２との間には、ＣｕとＴｉを含有する中間第１金属間化合物層が形成される。このとき、Ｔｉ材２５がすべて中間第１金属間化合物層の形成に消費されず、その一部が残存する。
　ここで、本実施形態では、中間Ｔｉ層２６の厚さは、０．１μｍ以上３μｍ以下の範囲内とされている。なお、中間Ｔｉ層２６の厚さの下限は０．２μｍ以上とすることが好ましく、０．４μｍ以上とすることがさらに好ましい。また、中間Ｔｉ層２６の厚さの上限は１．５μｍ以下とすることが好ましく、０．７μｍ以下とすることがさらに好ましい。
　さらに、中間第１金属間化合物層の厚さは、０．１μｍ以上６μｍ以下とすることが好ましい。 In the Cu—Ti bonded body 227 obtained by the CuTi diffusion step S201, the Ti material 25 and the Cu plate 222 are bonded by solid phase diffusion bonding, and a laminated structure of the Cu plate 222 and the intermediate Ti layer 26 is formed. Here, an intermediate first intermetallic compound layer containing Cu and Ti is formed between the intermediate Ti layer 26 and the Cu plate 222. At this time, all of the Ti material 25 is not consumed for forming the intermediate first intermetallic compound layer, and a part thereof remains.
Here, in the present embodiment, the thickness of the intermediate Ti layer 26 is in the range of 0.1 μm to 3 μm. Note that the lower limit of the thickness of the intermediate Ti layer 26 is preferably 0.2 μm or more, and more preferably 0.4 μm or more. Further, the upper limit of the thickness of the intermediate Ti layer 26 is preferably 1.5 μm or less, and more preferably 0.7 μm or less.
Furthermore, it is preferable that the thickness of the intermediate first intermetallic compound layer is 0.1 μm or more and 6 μm or less.
　次に、図１５に示すように、セラミックス基板１１の一方の面（図１５において上面）に、Ｃｕ－Ｐ－Ｓｎ系ろう材２２４、Ｔｉ材２５及びＣｕ板２２２を順に積層するとともに、セラミックス基板１１の他方の面（図１４において下面）に、接合材２４１を介して金属層２１３となるＡｌ板２２３を順に積層する。そして、さらにＡｌ板２２３の下側に、接合材２４２を介してヒートシンク２３０を積層する（積層工程Ｓ２０２）。ここで、Ｃｕ－Ｔｉ接合体２２７は、中間Ｔｉ層２６とＣｕ－Ｐ－Ｓｎ系ろう材２２４が対向するように積層される。 Next, as shown in FIG. 15, a Cu—P—Sn brazing material 224, a Ti material 25, and a Cu plate 222 are sequentially laminated on one surface (the upper surface in FIG. 15) of the ceramic substrate 11, and the ceramic substrate. 11, an Al plate 223 to be the metal layer 213 is sequentially laminated on the other surface (lower surface in FIG. 14) with a bonding material 241 interposed therebetween. Further, the heat sink 230 is laminated below the Al plate 223 via the bonding material 242 (lamination step S202). Here, the Cu—Ti joined body 227 is laminated so that the intermediate Ti layer 26 and the Cu—P—Sn brazing material 224 face each other.
　本実施形態においては、Ｃｕ－Ｐ－Ｓｎ系ろう材２２４の組成は、Ｃｕ－７ｍａｓｓ％Ｐ－１５ｍａｓｓ％Ｓｎ－１０ｍａｓｓ％Ｎｉとされており、その溶融開始温度（固相線温度）は５８０℃とされている。また、Ｃｕ－Ｐ－Ｓｎ系ろう材２２４は箔材を用い、その厚さは、５μｍ以上１５０μｍ以下の範囲内とされている。
　また、接合材２４１、２４２としては、本実施形態では、融点降下元素であるＳｉを含有したＡｌ－Ｓｉ系ろう材とされており、第三実施形態においては、Ａｌ－７．５ｍａｓｓ％Ｓｉろう材を用いている。 In this embodiment, the composition of the Cu—P—Sn brazing material 224 is Cu-7 mass% P-15 mass% Sn-10 mass% Ni, and its melting start temperature (solidus temperature) is 580 ° C. It is said that. The Cu—P—Sn brazing material 224 is made of a foil material and has a thickness in the range of 5 μm to 150 μm.
In the present embodiment, the bonding materials 241 and 242 are Al—Si brazing materials containing Si as a melting point lowering element. In the third embodiment, Al—7.5 mass% Si brazing material is used. The material is used.
　次に、セラミックス基板１１、Ｃｕ－Ｐ－Ｓｎ系ろう材２２４、Ｃｕ－Ｔｉ接合体２２７、接合材２４１、Ａｌ板２２３、接合材２４２、及びヒートシンク２３０を積層方向に加圧（圧力１～３５ｋｇｆ／ｃｍ２）した状態で、真空加熱炉内に装入して加熱する（加熱処理工程Ｓ２０３）。ここで、本実施形態では、真空加熱炉内の圧力は１０－６Ｐａ以上１０－３Ｐａ以下の範囲内に、加熱温度は６００℃以上６５０℃以下の範囲内に、加熱時間は３０分以上２４０分以下の範囲内に設定している。 Next, the ceramic substrate 11, the Cu—P—Sn brazing material 224, the Cu—Ti joined body 227, the joining material 241, the Al plate 223, the joining material 242 and the heat sink 230 are pressurized in the laminating direction (pressure 1 to 35 kgf). / Cm 2 ), the sample is charged into a vacuum heating furnace and heated (heat treatment step S203). Here, in this embodiment, the pressure in the vacuum heating furnace is in the range of 10 −6 Pa to 10 −3 Pa, the heating temperature is in the range of 600 ° C. to 650 ° C., and the heating time is 30 minutes or more. It is set within the range of 240 minutes or less.
　この加熱処理工程Ｓ２０３においては、Ｃｕ－Ｐ－Ｓｎ系ろう材２２４が溶融して液相を形成し、この液相に中間Ｔｉ層２６が溶け込み、液相が凝固することにより、セラミックス基板１１とＣｕ板２２２とが接合される。このとき、Ｃｕ－Ｐ－Ｓｎ系ろう材２２４中に含まれるＰ及びＮｉは、中間Ｔｉ層２６のＴｉと結合し、第２金属間化合物層１７が形成されるとともに、セラミックス基板１１側にはＣｕ－Ｓｎ層１４が形成される。なお、第１金属間化合物層１６は、中間第１金属間化合物層が残存することによって形成される。
　本実施形態においては、中間Ｔｉ層２６の厚さが、０．１μｍ以上３μｍ以下の範囲内とされているので、この中間Ｔｉ層２６がＣｕ－Ｐ－Ｓｎ系ろう材２２４の液相中にすべてが溶け込まず、一部が残存し、Ｔｉ層１５が形成される。しかしながら、Ｔｉ層１５の厚さが０．５μｍ以下と薄く形成されていることから、回路層２１２とセラミックス基板１１と金属層２１３の積層方向における熱抵抗を低く抑えることが可能となり、回路層２１２上に搭載された半導体素子３から発生する熱を効率的に放熱することができる。
　なお、第１金属間化合物層１６の厚さは、加熱処理工程Ｓ２０３における加熱によってＴｉの拡散が進み、中間第１金属間化合物層の厚さより厚くなる場合もある。また、Ｔｉ層１５の厚さは、加熱処理工程Ｓ２０３における加熱によってＴｉの拡散が進み、中間Ｔｉ層２６の厚さよりも薄くなる場合もある。 In this heat treatment step S203, the Cu—P—Sn brazing material 224 is melted to form a liquid phase, and the intermediate Ti layer 26 is dissolved in this liquid phase, and the liquid phase is solidified. The Cu plate 222 is joined. At this time, P and Ni contained in the Cu—P—Sn-based brazing material 224 are combined with Ti of the intermediate Ti layer 26 to form the second intermetallic compound layer 17 and on the ceramic substrate 11 side. A Cu—Sn layer 14 is formed. The first intermetallic compound layer 16 is formed by leaving the intermediate first intermetallic compound layer.
In the present embodiment, since the thickness of the intermediate Ti layer 26 is in the range of 0.1 μm or more and 3 μm or less, the intermediate Ti layer 26 is in the liquid phase of the Cu—P—Sn-based brazing material 224. All is not melted and a part of it remains, and the Ti layer 15 is formed. However, since the thickness of the Ti layer 15 is as thin as 0.5 μm or less, the thermal resistance in the stacking direction of the circuit layer 212, the ceramic substrate 11, and the metal layer 213 can be kept low. Heat generated from the semiconductor element 3 mounted thereon can be efficiently radiated.
Note that the thickness of the first intermetallic compound layer 16 may become thicker than the thickness of the intermediate first intermetallic compound layer due to the diffusion of Ti by heating in the heat treatment step S203. Further, the thickness of the Ti layer 15 may become thinner than the thickness of the intermediate Ti layer 26 due to the diffusion of Ti by heating in the heat treatment step S203.
　また、加熱処理工程Ｓ２０３においては、接合材２４１が溶融して液相を形成し、この液相が凝固することにより、接合材２４１を介してセラミックス基板１１とＡｌ板２２３とが接合される。さらに、加熱処理工程Ｓ２０３においては、接合材２４２が溶融して液相を形成し、この液相が凝固することにより、接合材２４２を介してＡｌ板２２３とヒートシンク２３０とが接合される。
　これにより、本実施形態であるパワーモジュール用基板２１０が製造される。 In the heat treatment step S <b> 203, the bonding material 241 is melted to form a liquid phase, and the liquid phase is solidified, so that the ceramic substrate 11 and the Al plate 223 are bonded via the bonding material 241. Further, in the heat treatment step S <b> 203, the bonding material 242 is melted to form a liquid phase, and the liquid phase is solidified, whereby the Al plate 223 and the heat sink 230 are bonded via the bonding material 242.
Thereby, the substrate 210 for power modules which is this embodiment is manufactured.
　次に、パワーモジュール用基板２１０の回路層２１２の上面に、はんだ材を介して半導体素子３を接合する（半導体素子接合工程Ｓ２０４）。
　このようにして、本実施形態に係るパワーモジュール２０１が製造される。 Next, the semiconductor element 3 is bonded to the upper surface of the circuit layer 212 of the power module substrate 210 via a solder material (semiconductor element bonding step S204).
In this way, the power module 201 according to this embodiment is manufactured.
　以上のような構成とされた本実施形態に係るパワーモジュール用基板２１０においては、第一実施形態及び第二実施形態で説明したパワーモジュール用基板１０，１１０と同様の効果を奏する。
　また、本実施形態に係るパワーモジュール用基板２１０においては、セラミックス基板１１の他方の面にＡｌ板２２３が接合されてなる金属層２１３が形成されているので、半導体素子３からの熱を、金属層２１３を介して効率的に放散することができる。また、Ａｌは比較的変形抵抗が低いので、冷熱サイクルが負荷された際に、パワーモジュール用基板２１０とヒートシンク２３０との間に生じる熱応力を金属層２１３によって吸収し、セラミックス基板１１に割れが発生することを抑制できる。 The power module substrate 210 according to the present embodiment configured as described above has the same effects as the power module substrates 10 and 110 described in the first and second embodiments.
Further, in the power module substrate 210 according to the present embodiment, the metal layer 213 formed by bonding the Al plate 223 to the other surface of the ceramic substrate 11 is formed. It can be efficiently dissipated through the layer 213. Further, since Al has a relatively low deformation resistance, the thermal stress generated between the power module substrate 210 and the heat sink 230 is absorbed by the metal layer 213 when a cooling cycle is applied, and the ceramic substrate 11 is not cracked. Occurrence can be suppressed.
　また、本実施形態に係るパワーモジュール用基板２１０の製造方法によれば、セラミックス基板１１の一方の面に回路層２１２を、他方の面に金属層２１３を同時に接合する構成とされているので、製造工程を簡略化し、製造コストを低減できる。 Further, according to the method for manufacturing the power module substrate 210 according to the present embodiment, the circuit layer 212 is bonded to one surface of the ceramic substrate 11 and the metal layer 213 is simultaneously bonded to the other surface. The manufacturing process can be simplified and the manufacturing cost can be reduced.
　以上、本発明の実施形態について説明したが、本発明はこれに限定されることはなく、その発明の技術的思想を逸脱しない範囲で適宜変更可能である。
　例えば、本実施形態では、絶縁回路基板に半導体素子を搭載してパワーモジュールを構成するものとして説明したが、これに限定されることはない。例えば、絶縁回路基板の回路層にＬＥＤ素子を搭載してＬＥＤモジュールを構成してもよいし、絶縁回路基板の回路層に熱電素子を搭載して熱電モジュールを構成してもよい。 As mentioned above, although embodiment of this invention was described, this invention is not limited to this, It can change suitably in the range which does not deviate from the technical idea of the invention.
For example, in the present embodiment, the power module is configured by mounting a semiconductor element on an insulating circuit board. However, the present invention is not limited to this. For example, an LED module may be configured by mounting LED elements on a circuit layer of an insulated circuit board, or a thermoelectric module may be configured by mounting thermoelectric elements on a circuit layer of an insulated circuit board.
　また、第二実施形態及び第三実施形態においては、セラミックス基板の一方の面に回路層を、他方の面に金属層を同時に接合する場合について説明したが、回路層と金属層とを別々に接合しても良い。
　また、第三実施形態において、回路層、金属層、及びヒートシンクを同時に接合する場合について説明したが、回路層と金属層をセラミックス基板に接合した後に、金属層とヒートシンクとを接合する構成としても良い。
　また、第三実施形態において、セラミックス基板の他方の面にＡｌ－Ｓｉ系ろう材を介して金属層を接合する場合について説明したが、過渡液相接合法（ＴＬＰ）やＡｇペーストなどによって接合しても良い。 In the second embodiment and the third embodiment, the case where the circuit layer is bonded to one surface of the ceramic substrate and the metal layer is simultaneously bonded to the other surface has been described. However, the circuit layer and the metal layer are separately provided. You may join.
In the third embodiment, the case where the circuit layer, the metal layer, and the heat sink are simultaneously bonded has been described. However, the circuit layer and the metal layer may be bonded to the ceramic substrate, and then the metal layer and the heat sink may be bonded. good.
In the third embodiment, the case where the metal layer is bonded to the other surface of the ceramic substrate via the Al—Si brazing material has been described, but the bonding is performed by a transient liquid phase bonding method (TLP), Ag paste, or the like. May be.
　また、第二実施形態及び第三実施形態では、流路が設けられたヒートシンクを用いる場合について説明したが、放熱板と呼ばれる板状のものや、ピン状フィンを有するものとしてもよい。
　また、パワーモジュール用基板とヒートシンクとをはんだ材又はろう材で接合する場合について説明したが、パワーモジュール用基板とヒートシンクとの間にグリースを介してネジ止めなどによって固定する構成とされても良い。
　また、第二実施形態及び第三実施形態のパワーモジュール用基板において、パワーモジュール用基板の他方の面側にヒートシンクが接合されていなくても良い。 Moreover, although the case where the heat sink provided with the flow path is used has been described in the second embodiment and the third embodiment, a plate-like thing called a heat radiating plate or a pin-like fin may be used.
Moreover, although the case where the power module substrate and the heat sink are joined with the solder material or the brazing material has been described, the power module substrate and the heat sink may be fixed by screwing or the like via grease. .
In the power module substrates of the second and third embodiments, the heat sink may not be bonded to the other surface side of the power module substrate.
　なお、第一実施形態、第二実施形態及び第三実施形態では、Ｔｉ材としてＴｉ箔を用いる場合又は蒸着やスパッタでＴｉ材を形成する場合について説明したが、Ｃｕ部材の一方の面にＴｉを配設したＣｕ部材／Ｔｉクラッド材を用いることもできる。この場合、Ｃｕ部材／Ｔｉクラッド材を予め加熱することでＣｕとＴｉを含有する第１金属間化合物層を形成してもよいし、第１加熱処理工程でＣｕ部材／Ｔｉクラッド材の内部に第１金属間化合物層を形成してもよい。
　さらに、Ｔｉ材の一方の面にＣｕ－Ｐ－Ｓｎ系ろう材を配設したＴｉ材／ろう材クラッド材や、Ｃｕ部材、Ｔｉ材、Ｃｕ－Ｐ－Ｓｎ系ろう材の順に積層されたＣｕ部材／Ｔｉ材／ろう材クラッドを用いることができる。 In the first embodiment, the second embodiment, and the third embodiment, the case where a Ti foil is used as the Ti material or the case where the Ti material is formed by vapor deposition or sputtering has been described. However, Ti is formed on one surface of the Cu member. It is also possible to use a Cu member / Ti clad material in which is disposed. In this case, the first intermetallic compound layer containing Cu and Ti may be formed by heating the Cu member / Ti clad material in advance, or in the Cu member / Ti clad material in the first heat treatment step. A first intermetallic compound layer may be formed.
Furthermore, a Ti material / brazing material clad material in which a Cu—P—Sn based brazing material is disposed on one surface of the Ti material, a Cu member, a Ti material, and a Cu—P—Sn based brazing material are laminated in this order. Member / Ti material / brazing material clad can be used.
　また、上記実施形態では、Ｃｕ－Ｐ－Ｓｎ系ろう材の箔材を用いたものを例に挙げて説明したが、これに限定されることはなく、粉末やペーストを用いることもできる。
　さらに、上記実施形態ではＣｕ－Ｐ－Ｓｎ系ろう材として、Ｃｕ－Ｐ－Ｓｎ－Ｎｉろう材やＣｕ－Ｐ－Ｓｎろう材を用いるものとして説明したが、その他のＣｕ－Ｐ－Ｓｎ系ろう材を用いてもよい。以下に、本発明の接合体の製造方法に適したＣｕ－Ｐ－Ｓｎ系ろう材について詳しく説明する。 In the above-described embodiment, the description has been given by taking as an example the use of a Cu—P—Sn brazing foil material, but the present invention is not limited to this, and powders and pastes can also be used.
Further, in the above-described embodiment, the Cu—P—Sn brazing material has been described as using a Cu—P—Sn—Ni brazing material or a Cu—P—Sn brazing material. A material may be used. Hereinafter, a Cu—P—Sn brazing material suitable for the method for producing a joined body of the present invention will be described in detail.
　Ｃｕ－Ｐ－Ｓｎ系ろう材のＰの含有量は、３ｍａｓｓ％以上１０ｍａｓｓ％以下とされていることが好ましい。
　Ｐは、ろう材の溶融開始温度を低下させる作用効果を有する元素である。また、このＰは、Ｐが酸化することで発生するＰ酸化物により、ろう材表面を覆うことでろう材の酸化を防止するとともに、溶融したろう材の表面を流動性の良いＰ酸化物が覆うことでろう材の濡れ性を向上させる作用効果を有する元素である。
　Ｐの含有量が３ｍａｓｓ％未満では、ろう材の溶融開始温度を低下させる効果が十分に得られずろう材の溶融開始温度が上昇したり、ろう材の流動性が不足し、セラミックス基板と回路層との接合性が低下したりするおそれがある。また、Ｐの含有量が１０ｍａｓｓ％超では、脆い金属間化合物が多く形成され、セラミックス基板と回路層との接合性や接合信頼性が低下するおそれがある。
　このような理由からＣｕ－Ｐ－Ｓｎ系ろう材に含まれるＰの含有量は、３ｍａｓｓ％以上１０ｍａｓｓ％以下の範囲内とすることが好ましい。 The P content of the Cu—P—Sn brazing material is preferably 3 mass% or more and 10 mass% or less.
P is an element having an effect of lowering the melting start temperature of the brazing material. Moreover, this P prevents oxidation of the brazing filler metal by covering the surface of the brazing filler metal with the P oxide generated by oxidation of P, and the surface of the molten brazing filler metal has good fluidity. It is an element having an effect of improving the wettability of the brazing material by covering.
If the P content is less than 3 mass%, the effect of lowering the melting start temperature of the brazing material cannot be sufficiently obtained, the melting start temperature of the brazing material is increased, or the fluidity of the brazing material is insufficient. There is a possibility that the bondability with the layer may decrease. On the other hand, if the P content exceeds 10 mass%, a large amount of brittle intermetallic compounds are formed, and the bonding properties and bonding reliability between the ceramic substrate and the circuit layer may be reduced.
For these reasons, the content of P contained in the Cu—P—Sn brazing material is preferably in the range of 3 mass% to 10 mass%.
　また、Ｃｕ－Ｐ－Ｓｎ系ろう材のＳｎの含有量は、０．５ｍａｓｓ％以上２５ｍａｓｓ％以下とされていることが好ましい。
　Ｓｎは、ろう材の溶融開始温度を低下させる作用効果を有する元素である。Ｓｎの含有量が０．５ｍａｓｓ％以上では、ろう材の溶融開始温度を確実に低くすることができる。また、Ｓｎの含有量が２５ｍａｓｓ％以下では、ろう材の低温脆化を抑制することができ、セラミックス基板と回路層との接合信頼性を向上させることができる。
　このような理由からＣｕ－Ｐ－Ｓｎ系ろう材に含まれるＳｎの含有量は、０．５ｍａｓｓ％以上２５ｍａｓｓ％以下の範囲内とすることが好ましい。 In addition, the Sn content of the Cu—P—Sn brazing material is preferably 0.5 mass% or more and 25 mass% or less.
Sn is an element having an effect of lowering the melting start temperature of the brazing material. When the Sn content is 0.5 mass% or more, the melting start temperature of the brazing material can be reliably lowered. Further, when the Sn content is 25 mass% or less, the low temperature embrittlement of the brazing material can be suppressed, and the bonding reliability between the ceramic substrate and the circuit layer can be improved.
For these reasons, the Sn content in the Cu—P—Sn brazing material is preferably in the range of 0.5 mass% to 25 mass%.
　また、Ｃｕ－Ｐ－Ｓｎ系ろう材は、Ｎｉ、Ｃｒ、Ｆｅ、Ｍｎのうちいずれか１種または２種以上を２ｍａｓｓ％以上２０ｍａｓｓ％以下含有していても良い。
　Ｎｉ、Ｃｒ、Ｆｅ、Ｍｎは、セラミックス基板とろう材との界面にＰを含有する金属間化合物が形成されることを抑制する作用効果を有する元素である。
　Ｎｉ、Ｃｒ、Ｆｅ、Ｍｎのうちいずれか１種または２種以上の含有量が２ｍａｓｓ％以上では、セラミックス基板とろう材との接合界面にＰを含有する金属間化合物が形成されることを抑制することができ、セラミックス基板と回路層との接合信頼性が向上する。また、Ｎｉ、Ｃｒ、Ｆｅ、Ｍｎのうちいずれか１種または２種以上の含有量が２０ｍａｓｓ％以下では、ろう材の溶融開始温度が上昇することを抑制し、ろう材の流動性が低下することを抑え、セラミックス基板と回路層との接合性を向上させることができる。
　このような理由からＣｕ－Ｐ－Ｓｎ系ろう材にＮｉ、Ｃｒ、Ｆｅ、Ｍｎのうちいずれか１種または２種以上を含有させる場合、その含有量は２ｍａｓｓ％以上２０ｍａｓｓ％以下の範囲内とすることが好ましい。 Further, the Cu—P—Sn brazing material may contain 2 mass% or more and 20 mass% or less of any one or more of Ni, Cr, Fe, and Mn.
Ni, Cr, Fe, and Mn are elements having an effect of suppressing the formation of an intermetallic compound containing P at the interface between the ceramic substrate and the brazing material.
When the content of one or more of Ni, Cr, Fe, and Mn is 2 mass% or more, the formation of intermetallic compounds containing P at the bonding interface between the ceramic substrate and the brazing material is suppressed. This improves the bonding reliability between the ceramic substrate and the circuit layer. In addition, when the content of any one or more of Ni, Cr, Fe, and Mn is 20 mass% or less, an increase in the melting start temperature of the brazing material is suppressed, and the fluidity of the brazing material is lowered. This can suppress this and improve the bondability between the ceramic substrate and the circuit layer.
For these reasons, when one or more of Ni, Cr, Fe, and Mn is contained in the Cu—P—Sn brazing material, the content is within the range of 2 mass% or more and 20 mass% or less. It is preferable to do.
＜実施例１＞
　以下に、本発明の効果を確認すべく行った確認実験の結果について説明する。 <Example 1>
Below, the result of the confirmation experiment performed in order to confirm the effect of this invention is demonstrated.
（本発明例１～３、１２、１４～１５（加熱方式：Ａ））
　表１記載のセラミックス基板（４０ｍｍ×４０ｍｍ、ＡｌＮ及びＡｌ２Ｏ３の場合は厚さ０．６３５ｍｍ、Ｓｉ３Ｎ４の場合には厚さ０．３２ｍｍ）の一方の面及び他方の面に表１に示すＣｕ－Ｐ－Ｓｎ系ろう材箔、Ｔｉ材、無酸素銅からなるＣｕ板（厚さ：０．３ｍｍ）を順に積層し、積層方向に１５ｋｇｆ／ｃｍ２の荷重を付加した。
　そして、真空加熱炉内（圧力：１０－４Ｐａ）に前述した積層体を装入し、第１加熱処理工程として、表１記載の温度と時間（加熱処理１の欄）で加熱した。その後、第２加熱処理工程として、表２記載の温度と時間（加熱処理２の欄）で加熱することによって、セラミックス基板の一方の面及び他方の面にＣｕ板を接合し、回路層及び金属層を形成し、パワーモジュール用基板を得た。
　なお、回路層用のＣｕ板の大きさは、後述する９０°ピール強度試験用に４４ｍｍ×２５ｍｍ（但し、セラミックス基板の端部から５ｍｍ突出している）、熱抵抗試験用に３７ｍｍ×３７ｍｍとし、それぞれ作製した。金属層用のＣｕ板の大きさは、３７ｍｍ×３７ｍｍとした。 (Invention Examples 1 to 3, 12, 14 to 15 (heating method: A))
Displayed on one surface and the other surface of the ceramic substrate described in Table 1 (40 mm × 40 mm, thickness 0.635 mm for AlN and Al 2 O 3 , thickness 0.32 mm for Si 3 N 4 ) A Cu—P—Sn brazing foil shown in FIG. 1, a Ti material, and a Cu plate (thickness: 0.3 mm) made of oxygen-free copper were laminated in this order, and a load of 15 kgf / cm 2 was applied in the lamination direction.
Then, the above-described laminate was placed in a vacuum heating furnace (pressure: 10 −4 Pa), and heated as a first heat treatment step at the temperature and time shown in Table 1 (column of heat treatment 1). Thereafter, as the second heat treatment step, the Cu plate is joined to one surface and the other surface of the ceramic substrate by heating at the temperature and time shown in Table 2 (column of heat treatment 2), and the circuit layer and metal A layer was formed to obtain a power module substrate.
In addition, the size of the Cu plate for the circuit layer is 44 mm × 25 mm for 90 ° peel strength test described later (however, it protrudes 5 mm from the end of the ceramic substrate), and 37 mm × 37 mm for the thermal resistance test, Each was produced. The size of the Cu plate for the metal layer was 37 mm × 37 mm.
（本発明例４～１１、１３（加熱方式：Ｂ））
　まず、ＣｕＴｉ拡散工程として、無酸素銅からなるＣｕ板（厚さ：０．３ｍｍ）と表１記載のＴｉ材を積層し、積層方向に圧力１５ｋｇｆ／ｃｍ２で加圧した状態で真空加熱炉内（圧力：１０－４Ｐａ）に装入し、表１記載の温度と時間（加熱処理１の欄）で加熱し、Ｃｕ－Ｔｉ接合体を得た。なお、Ｃｕ－Ｔｉ接合体は回路層用と金属層用のそれぞれを用意した。
　次に、表１記載のセラミックス基板（４０ｍｍ×４０ｍｍ、ＡｌＮ及びＡｌ２Ｏ３の場合は厚さ０．６３５ｍｍ、Ｓｉ３Ｎ４の場合には厚さ０．３２ｍｍ）の一方の面及び他方の面に表１に示すＣｕ－Ｐ－Ｓｎ系ろう材箔、Ｃｕ－Ｔｉ接合体を順に積層する。
　そして、表２記載の温度と時間（加熱処理２の欄）で加熱し、セラミックス基板の一方の面及び他方の面にＣｕ板を接合し、回路層及び金属層を形成し、パワーモジュール用基板を作製した。回路層用及び金属層用のＣｕ板の大きさは、前述と同様とした。 (Invention Examples 4 to 11, 13 (heating method: B))
First, as a CuTi diffusion step, a Cu plate (thickness: 0.3 mm) made of oxygen-free copper and a Ti material shown in Table 1 are stacked, and a vacuum heating furnace is pressed in a pressure of 15 kgf / cm 2 in the stacking direction. The inside (pressure: 10 −4 Pa) was charged and heated at the temperature and time shown in Table 1 (column of heat treatment 1) to obtain a Cu—Ti joined body. Cu—Ti bonded bodies were prepared for the circuit layer and the metal layer, respectively.
Next, one surface of the ceramic substrate shown in Table 1 (40 mm × 40 mm, thickness 0.635 mm for AlN and Al 2 O 3 , thickness 0.32 mm for Si 3 N 4 ) and the other surface On the surface, a Cu—P—Sn-based brazing foil and a Cu—Ti joined body shown in Table 1 are sequentially laminated.
And it heats with the temperature and time (column of the heat processing 2) of Table 2, and joins Cu board to the one side and the other side of a ceramic substrate, forms a circuit layer and a metal layer, The board | substrate for power modules Was made. The size of the Cu plate for the circuit layer and the metal layer was the same as described above.
（従来例１，２）
　表１記載のセラミックス基板（４０ｍｍ×４０ｍｍ×０．６３５ｍｍｔ）の一方の面及び他方の面に表１に示すＣｕ－Ｐ－Ｓｎ系ろう材箔、Ｔｉ材、無酸素銅からなるＣｕ板（厚さ：０．３ｍｍ）を順に積層し、積層方向に１５ｋｇｆ／ｃｍ２の荷重を付加した。
　そして、真空加熱炉内（圧力：１０－４Ｐａ）に前述した積層体を装入し、第２加熱処理工程として、表２記載の温度と時間（加熱処理２の欄）で加熱することによって、セラミックス基板の一方の面及び他方の面にＣｕ板を接合し、回路層及び金属層を形成し、パワーモジュール用基板を得た。回路層用及び金属層用のＣｕ板の大きさは、本発明例と同様とした。 (Conventional examples 1 and 2)
A Cu plate (thickness) made of Cu—P—Sn-based brazing foil, Ti material and oxygen-free copper shown in Table 1 on one side and the other side of the ceramic substrate shown in Table 1 (40 mm × 40 mm × 0.635 mmt) The thickness was 0.3 mm) in order, and a load of 15 kgf / cm 2 was applied in the stacking direction.
Then, the above-mentioned laminated body was charged into the vacuum heating furnace (pressure: 10 −4 Pa), and heated as the second heat treatment step at the temperature and time shown in Table 2 (column of heat treatment 2). Then, a Cu plate was bonded to one surface and the other surface of the ceramic substrate to form a circuit layer and a metal layer to obtain a power module substrate. The size of the Cu plate for the circuit layer and the metal layer was the same as the example of the present invention.
　上述のようにして得られたパワーモジュール用基板に対して、回路層とセラミックス基板との９０°ピール強度、積層方向の熱抵抗を評価した。
　また、得られたパワーモジュール用基板に対して、セラミックス基板と回路層との接合界面において、第１金属間化合物層、Ｔｉ層、第２金属間化合物層の厚さを評価した。さらに、加熱処理１後の中間第１金属間化合物層、中間Ｔｉ層の厚さを評価した。 The power module substrate obtained as described above was evaluated for 90 ° peel strength between the circuit layer and the ceramic substrate and the thermal resistance in the stacking direction.
Moreover, the thickness of the 1st intermetallic compound layer, Ti layer, and 2nd intermetallic compound layer was evaluated in the joining interface of a ceramic substrate and a circuit layer with respect to the obtained board | substrate for power modules. Furthermore, the thickness of the intermediate first intermetallic compound layer and the intermediate Ti layer after the heat treatment 1 was evaluated.
（９０°ピール強度試験）
　各パワーモジュール用基板において、１５０℃で５００時間放置後、回路層のうちセラミックス基板から突出した部分を９０°折り曲げ、セラミックス基板と垂直方向に回路層を引っ張り、回路層がセラミックス基板から剥離するまでの最大の引っ張り荷重を測定した。この荷重を接合長さで割った値を９０°ピール強度とし、表２に記載した。本実施例での接合長さは、回路層とセラミックス基板とが接合した部分における、回路層の長辺の長さ（３９ｍｍ）とした。 (90 ° peel strength test)
After each power module substrate is left at 150 ° C. for 500 hours, the portion of the circuit layer protruding from the ceramic substrate is bent by 90 °, the circuit layer is pulled in a direction perpendicular to the ceramic substrate, and the circuit layer is peeled off from the ceramic substrate. The maximum tensile load was measured. A value obtained by dividing the load by the joining length was defined as 90 ° peel strength and shown in Table 2. The joining length in this example was the length (39 mm) of the long side of the circuit layer at the portion where the circuit layer and the ceramic substrate were joined.
（熱抵抗試験）
　ヒータチップ（１３ｍｍ×１０ｍｍ×０．２５ｍｍ）を回路層の表面に半田付けし、セラミックス基板を冷却器に積層した。次に、ヒータチップを１００Ｗの電力で加熱し、熱電対を用いてヒータチップの温度を実測した。また、冷却器を流通する冷却媒体（エチレングリコール：水＝９：１）の温度を実測した。そして、ヒータチップの温度と冷却媒体の温度差を電力で割った値を熱抵抗とし、本発明例１を１．００として相対評価した。評価結果を表２に示す。 (Thermal resistance test)
A heater chip (13 mm × 10 mm × 0.25 mm) was soldered to the surface of the circuit layer, and a ceramic substrate was laminated on the cooler. Next, the heater chip was heated with a power of 100 W, and the temperature of the heater chip was measured using a thermocouple. Further, the temperature of the cooling medium (ethylene glycol: water = 9: 1) flowing through the cooler was measured. And the value which divided the temperature difference of a heater chip | tip and the temperature of a cooling medium with electric power was made into thermal resistance, and the present invention example 1 was set as 1.00, and relative evaluation was carried out. The evaluation results are shown in Table 2.
（中間第１金属間化合物層、中間Ｔｉ層、第１金属間化合物層、Ｔｉ層及び第２金属間化合物層の厚さ）
　第１金属間化合物層、Ｔｉ層及び第２金属間化合物層の厚さは、Ｃｕ板／セラミックス基板界面のＥＰＭＡから、倍率１００００倍の視野（縦３０μｍ、横４０μｍ）において、接合界面に形成された第１金属間化合物層の総面積、Ｔｉ層の面積及び第２金属間化合物層の総面積を測定し、測定視野の幅の寸法で除して求め、５視野の平均を第１金属間化合物層、Ｔｉ層及び第２金属間化合物層の厚さとした。
　中間第１金属間化合物層及び中間Ｔｉ層は、前述した加熱方式Ｂにて作製したＣｕ－Ｔｉ接合体のＣｕとＴｉの接合界面に対し、ＥＰＭＡから、倍率１００００倍の視野（縦３０μｍ、横４０μｍ）において、接合界面に形成された中間第１金属間化合物層の総面積、中間Ｔｉ層の面積の総面積を測定し、測定視野の幅の寸法で除して求め、５視野の平均を中間第１金属間化合物層、中間Ｔｉ層の厚さとした。
　なお、Ｔｉ濃度が１５ａｔ％～７０ａｔ％の範囲内である領域を第１金属間化合物層及び中間第１金属間化合物層とみなし、固溶体は含めないものとする。
　また、第２金属間化合物層は、少なくともＰとＴｉを含み、Ｐ濃度が２８ａｔ％～５２ａｔ％の範囲内の領域とする。
　評価結果を表１及び表２に示す。 (Thickness of intermediate first intermetallic compound layer, intermediate Ti layer, first intermetallic compound layer, Ti layer and second intermetallic compound layer)
The thicknesses of the first intermetallic compound layer, the Ti layer and the second intermetallic compound layer are formed at the bonding interface from the EPMA at the Cu plate / ceramics substrate interface in a field of view of 10,000 times magnification (length 30 μm, width 40 μm). The total area of the first intermetallic compound layer, the area of the Ti layer, and the total area of the second intermetallic compound layer are measured and divided by the width of the measurement visual field, and the average of the five visual fields is calculated between the first metal The thicknesses of the compound layer, the Ti layer, and the second intermetallic compound layer were used.
The intermediate first intermetallic compound layer and the intermediate Ti layer have a 10,000 × field of view (length 30 μm, horizontal width) from the EPMA with respect to the Cu / Ti bonding interface of the Cu—Ti bonded body prepared by the heating method B described above. 40 μm), the total area of the intermediate first intermetallic compound layer formed at the bonding interface and the total area of the intermediate Ti layer are measured and divided by the width of the measurement visual field, and the average of the five visual fields is obtained. The thickness of the intermediate first intermetallic compound layer and the intermediate Ti layer was used.
Note that regions where the Ti concentration is in the range of 15 at% to 70 at% are regarded as the first intermetallic compound layer and the intermediate first intermetallic compound layer, and solid solutions are not included.
The second intermetallic compound layer includes at least P and Ti, and the P concentration is a region in the range of 28 at% to 52 at%.
The evaluation results are shown in Tables 1 and 2.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000002
Figure JPOXMLDOC01-appb-T000002
　Ｔｉ層が厚く形成された従来例１においては、９０°ピール強度は高いものの、積層方向の熱抵抗が高くなっていることが確認された。また、Ｔｉ層が確認されなかった従来例２では、第１金属間化合物層が形成されず、９０°ピール強度が低いことが確認された。
　これに対し、本発明例１～１５では、９０°ピール強度が高く、熱抵抗が低いパワーモジュール用基板が得られることが確認された。 In Conventional Example 1 in which the Ti layer was formed thick, it was confirmed that although the 90 ° peel strength was high, the thermal resistance in the stacking direction was high. Further, in Conventional Example 2 in which no Ti layer was confirmed, it was confirmed that the first intermetallic compound layer was not formed and the 90 ° peel strength was low.
On the other hand, in Examples 1 to 15 of the present invention, it was confirmed that a power module substrate having a high 90 ° peel strength and a low thermal resistance was obtained.
＜実施例２＞
　次に、さらに厳しいピール強度試験を実施した。
　まず、ＣｕＴｉ拡散工程として、無酸素銅からなるＣｕ板（厚さ：０．３ｍｍ）と厚さ３ｍｍのＴｉ材を積層し、表３に示す圧力で積層方向に加圧した状態で真空加熱炉内（圧力：１０－４Ｐａ）に装入し、表３記載の温度と時間（加熱処理１の欄）で加熱し、Ｃｕ－Ｔｉ接合体を得た。なお、Ｃｕ－Ｔｉ接合体は回路層用と金属層用のそれぞれを用意した。 <Example 2>
Next, a more severe peel strength test was conducted.
First, as a CuTi diffusion process, a Cu plate (thickness: 0.3 mm) made of oxygen-free copper and a Ti material having a thickness of 3 mm are stacked, and the vacuum heating furnace is pressed in the stacking direction with the pressure shown in Table 3 The inside (pressure: 10 −4 Pa) was charged and heated at the temperature and time shown in Table 3 (column of heat treatment 1) to obtain a Cu—Ti joined body. Cu—Ti bonded bodies were prepared for the circuit layer and the metal layer, respectively.
　次に、表３記載のセラミックス基板（４０ｍｍ×４０ｍｍ、ＡｌＮ及びＡｌ２Ｏ３の場合は厚さ０．６３５ｍｍ、Ｓｉ３Ｎ４の場合には厚さ０．３２ｍｍ）の一方の面及び他方の面にＣｕ－６．３ｍａｓｓ％Ｐ－９．３ｍａｓｓ％Ｓｎ－７．０ｍａｓｓ％Ｎｉろう材箔（融点６００℃）、Ｃｕ－Ｔｉ接合体を順に積層した。
　そして、加熱処理２として６５０℃で６０ｍｉｎの条件で加熱し、セラミックス基板の一方の面及び他方の面にＣｕ板を接合し、回路層及び金属層を形成し、パワーモジュール用基板を作製した。回路層用及び金属層用のＣｕ板の大きさは、前述と同様とした。 Next, one surface of the ceramic substrate described in Table 3 (40 mm × 40 mm, thickness 0.635 mm for AlN and Al 2 O 3 , thickness 0.32 mm for Si 3 N 4 ) and the other surface Cu-6.3 mass% P-9.3 mass% Sn-7.0 mass% Ni brazing material foil (melting point 600 ° C.) and Cu—Ti joined body were laminated in this order on the surface.
And as heat processing 2, it heated on condition of 650 degreeC for 60 minutes, the Cu board was joined to one side and the other side of a ceramic substrate, the circuit layer and the metal layer were formed, and the board | substrate for power modules was produced. The size of the Cu plate for the circuit layer and the metal layer was the same as described above.
　上述のようにして得られたパワーモジュール用基板に対して、回路層とセラミックス基板との９０°ピール強度を以下の条件で評価した。
　各パワーモジュール用基板において、１５０℃で１０００時間放置後、回路層のうちセラミックス基板から突出した部分を９０°折り曲げ、セラミックス基板と垂直方向に回路層を引っ張り、回路層がセラミックス基板から剥離するまでの最大の引っ張り荷重を測定した。この荷重を接合長さで割った値を９０°ピール強度とし、表３に記載した。本実施例での接合長さは、回路層とセラミックス基板とが接合した部分における、回路層の長辺の長さとした。 For the power module substrate obtained as described above, the 90 ° peel strength between the circuit layer and the ceramic substrate was evaluated under the following conditions.
In each power module substrate, after leaving at 150 ° C. for 1000 hours, the portion of the circuit layer that protrudes from the ceramic substrate is bent 90 °, the circuit layer is pulled in a direction perpendicular to the ceramic substrate, and the circuit layer is peeled off from the ceramic substrate. The maximum tensile load was measured. A value obtained by dividing the load by the joining length was defined as 90 ° peel strength, and is shown in Table 3. The joining length in this example was the length of the long side of the circuit layer at the part where the circuit layer and the ceramic substrate were joined.
Figure JPOXMLDOC01-appb-T000003
Figure JPOXMLDOC01-appb-T000003
　積層方向に圧力を高く、かつ、加熱時間を長く設定することにより、厳しい条件でのピール試験であっても、十分なピール強度を確保できることが確認された。 It was confirmed that a sufficient peel strength can be secured even in a peel test under severe conditions by setting a high pressure in the stacking direction and a long heating time.
　本発明の接合体、パワーモジュール用基板、及び、この接合体の製造方法、パワーモジュール用基板の製造方法よれば、セラミックス部材とＣｕ部材とが良好に接合され、かつ、積層方向の熱抵抗を低くすることが可能である。 According to the joined body of the present invention, the power module substrate, the manufacturing method of the joined body, and the manufacturing method of the power module substrate, the ceramic member and the Cu member are satisfactorily bonded, and the thermal resistance in the stacking direction is reduced. It can be lowered.
　１０、１１０、２１０　　パワーモジュール用基板（接合体）
　１１　　セラミックス基板（セラミックス部材）
　１２、１１２、２１２　　回路層（Ｃｕ部材）
　１４　Ｃｕ－Ｓｎ層
　１５　　Ｔｉ層
　１６　　第１金属間化合物層
　１７　　第２金属間化合物層
　２２、１２２、１２３、２２２　　Ｃｕ板（Ｃｕ部材）
　２４，１２４，２２４　　Ｃｕ－Ｐ－Ｓｎ系ろう材 10, 110, 210 Power module substrate (joint)
11 Ceramic substrate (ceramic member)
12, 112, 212 Circuit layer (Cu member)
14 Cu-Sn layer 15 Ti layer 16 First intermetallic compound layer 17 Second intermetallic compound layer 22, 122, 123, 222 Cu plate (Cu member)
24, 124, 224 Cu-P-Sn brazing material

Claims (15)

  1. 　セラミックスからなるセラミックス部材とＣｕ又はＣｕ合金からなるＣｕ部材との接合体であって、
    　前記セラミックス部材と前記Ｃｕ部材との接合界面には、
    　前記セラミックス部材側に位置し、ＳｎがＣｕ中に固溶したＣｕ－Ｓｎ層と、
    　前記Ｃｕ部材側に位置し、ＣｕとＴｉを含有する第１金属間化合物層と、
    　前記第１金属間化合物層と前記Ｃｕ－Ｓｎ層との間に位置し、ＰとＴｉを含有する第２金属間化合物層と、
    　が形成されていることを特徴とする接合体。     A joined body of a ceramic member made of ceramic and a Cu member made of Cu or a Cu alloy,
    In the bonding interface between the ceramic member and the Cu member,
    A Cu—Sn layer in which Sn is solid-solved in Cu, located on the ceramic member side;
    A first intermetallic compound layer located on the Cu member side and containing Cu and Ti;
    A second intermetallic compound layer located between the first intermetallic compound layer and the Cu-Sn layer and containing P and Ti;
    Is formed.
  2. 　前記第１金属間化合物層と前記第２金属間化合物層との間にＴｉ層が形成されており、このＴｉ層の厚さが０．５μｍ以下とされていることを特徴とする請求項１に記載の接合体。 2. A Ti layer is formed between the first intermetallic compound layer and the second intermetallic compound layer, and the thickness of the Ti layer is 0.5 μm or less. The joined body according to 1.
  3. 　前記第１金属間化合物層の厚さが０．２μｍ以上６μｍ以下の範囲内とされていることを特徴とする請求項１又は請求項２に記載の接合体。 The joined body according to claim 1 or 2, wherein a thickness of the first intermetallic compound layer is in a range of 0.2 µm to 6 µm.
  4. 　前記第２金属間化合物層の厚さが０．５μｍ以上４μｍ以下の範囲内とされていることを特徴とする請求項１から請求項３のいずれか一項に記載の接合体。 The joined body according to any one of claims 1 to 3, wherein a thickness of the second intermetallic compound layer is in a range of 0.5 µm to 4 µm.
  5. 　請求項１から請求項４のいずれか一項に記載の接合体からなり、
    　前記セラミックス部材からなるセラミックス基板と、このセラミックス基板の一方の面に形成された前記Ｃｕ部材からなる回路層と、を備え、
    　前記セラミックス基板と前記回路層との接合界面には、
    　前記セラミックス基板側に位置し、ＳｎがＣｕ中に固溶したＣｕ－Ｓｎ層と、
    　前記回路層側に位置し、ＣｕとＴｉを含有する第１金属間化合物層と、
    　前記第１金属間化合物層と前記Ｃｕ－Ｓｎ層との間に位置し、ＰとＴｉを含有する第２金属間化合物層と、
    　が形成されていることを特徴とするパワーモジュール用基板。     The joined body according to any one of claims 1 to 4,
    A ceramic substrate made of the ceramic member, and a circuit layer made of the Cu member formed on one surface of the ceramic substrate,
    In the bonding interface between the ceramic substrate and the circuit layer,
    A Cu—Sn layer in which Sn is dissolved in Cu, located on the ceramic substrate side;
    A first intermetallic compound layer located on the circuit layer side and containing Cu and Ti;
    A second intermetallic compound layer located between the first intermetallic compound layer and the Cu-Sn layer and containing P and Ti;
    A substrate for a power module, characterized in that is formed.
  6. 　前記セラミックス基板の他方の面に、Ａｌ又はＡｌ合金からなる金属層が形成されていることを特徴とする請求項５に記載のパワーモジュール用基板。 6. The power module substrate according to claim 5, wherein a metal layer made of Al or an Al alloy is formed on the other surface of the ceramic substrate.
  7. 　請求項１から請求項４のいずれか一項に記載の接合体からなり、
    　前記セラミックス部材からなるセラミックス基板と、このセラミックス基板の一方の面に形成された回路層と、前記セラミックス基板の他方の面に形成された前記Ｃｕ部材からなる金属層と、を備え、
    　前記セラミックス基板と前記金属層との接合界面には、
    　前記セラミックス基板側に位置し、ＳｎがＣｕ中に固溶したＣｕ－Ｓｎ層と、
    　前記金属層側に位置し、ＣｕとＴｉを含有する第１金属間化合物層と、
    　前記第１金属間化合物層と前記Ｃｕ－Ｓｎ層との間に位置し、ＰとＴｉを含有する第２金属間化合物層と、
    　が形成されていることを特徴とするパワーモジュール用基板。     The joined body according to any one of claims 1 to 4,
    A ceramic substrate made of the ceramic member, a circuit layer formed on one surface of the ceramic substrate, and a metal layer made of the Cu member formed on the other surface of the ceramic substrate,
    In the bonding interface between the ceramic substrate and the metal layer,
    A Cu—Sn layer in which Sn is dissolved in Cu, located on the ceramic substrate side;
    A first intermetallic compound layer located on the metal layer side and containing Cu and Ti;
    A second intermetallic compound layer located between the first intermetallic compound layer and the Cu-Sn layer and containing P and Ti;
    A substrate for a power module, characterized in that is formed.
  8. 　セラミックスからなるセラミックス部材とＣｕ又はＣｕ合金からなるＣｕ部材との接合体の製造方法であって、
    　Ｃｕ－Ｐ－Ｓｎ系ろう材とＴｉ材とを介して、前記セラミックス部材と前記Ｃｕ部材とを積層する積層工程と、
    　積層された状態で前記Ｃｕ－Ｐ－Ｓｎ系ろう材の溶融開始温度未満の温度で加熱し、前記Ｃｕ部材と前記Ｔｉ材とを反応させてＣｕとＴｉを含有する第１金属間化合物層を形成する第１加熱処理工程と、
    　前記第１加熱処理工程後に、前記Ｃｕ－Ｐ－Ｓｎ系ろう材の溶融開始温度以上の温度で加熱し、ＳｎがＣｕ中に固溶したＣｕ－Ｓｎ層と、前記第１金属間化合物層と前記Ｃｕ－Ｓｎ層との間に位置し、ＰとＴｉを含有する第２金属間化合物層とを形成する第２加熱処理工程と、
    　を備えていることを特徴とする接合体の製造方法。     A method for manufacturing a joined body of a ceramic member made of ceramics and a Cu member made of Cu or Cu alloy,
    A laminating step of laminating the ceramic member and the Cu member via a Cu—P—Sn brazing material and a Ti material;
    The first intermetallic compound layer containing Cu and Ti is heated by heating at a temperature lower than the melting start temperature of the Cu—P—Sn brazing material in a laminated state to react the Cu member with the Ti material. A first heat treatment step to be formed;
    After the first heat treatment step, the Cu—P—Sn brazing material is heated at a temperature equal to or higher than the melting start temperature, and a Cu—Sn layer in which Sn is dissolved in Cu, the first intermetallic compound layer, A second heat treatment step of forming a second intermetallic compound layer containing P and Ti, located between the Cu-Sn layer;
    The manufacturing method of the joined body characterized by the above-mentioned.
  9. 　前記第１加熱処理工程における加熱温度が５８０℃以上６７０℃以下の範囲内、加熱時間が３０分以上２４０分以下の範囲内とされていることを特徴とする請求項８に記載の接合体の製造方法。 9. The joined body according to claim 8, wherein a heating temperature in the first heat treatment step is in a range of 580 ° C. or more and 670 ° C. or less, and a heating time is in a range of 30 minutes or more and 240 minutes or less. Production method.
  10. 　セラミックスからなるセラミックス部材とＣｕ又はＣｕ合金からなるＣｕ部材との接合体の製造方法であって、
    　前記Ｃｕ部材と前記Ｔｉ材とを積層した状態で加熱してＣｕとＴｉを拡散させ、Ｃｕ部材と前記Ｔｉ材との間にＣｕとＴｉを含有する第１金属間化合物層を形成するＣｕＴｉ拡散工程と、
    　Ｃｕ－Ｐ－Ｓｎ系ろう材を介して、前記セラミックス部材と、前記第１金属間化合物層が形成された前記Ｔｉ材及び前記Ｃｕ部材と、を積層する積層工程と、
    　前記Ｃｕ－Ｐ－Ｓｎ系ろう材の溶融開始温度以上の温度で加熱し、ＳｎがＣｕ中に固溶したＣｕ－Ｓｎ層と、前記第１金属間化合物層と前記Ｃｕ－Ｓｎ層との間に位置し、ＰとＴｉを含有する第２金属間化合物層とを形成する加熱処理工程と、
    　を備えていることを特徴とする接合体の製造方法。     A method for manufacturing a joined body of a ceramic member made of ceramics and a Cu member made of Cu or Cu alloy,
    CuTi diffusion that forms a first intermetallic compound layer containing Cu and Ti between the Cu member and the Ti material by heating the Cu member and the Ti material in a stacked state to diffuse Cu and Ti. Process,
    A laminating step of laminating the ceramic member, the Ti material on which the first intermetallic compound layer is formed, and the Cu member via a Cu-P-Sn brazing material;
    Heated at a temperature equal to or higher than the melting start temperature of the Cu—P—Sn brazing material, and between the Cu—Sn layer in which Sn is dissolved in Cu, the first intermetallic compound layer, and the Cu—Sn layer And a heat treatment step of forming a second intermetallic compound layer containing P and Ti,
    The manufacturing method of the joined body characterized by the above-mentioned.
  11. 　前記ＣｕＴｉ拡散工程における加熱温度が６００℃以上６７０℃以下の範囲内、加熱時間が３０分以上３６０分以下の範囲内とされていることを特徴とする請求項１０に記載の接合体の製造方法。 11. The method for manufacturing a joined body according to claim 10, wherein a heating temperature in the CuTi diffusion step is in a range of 600 ° C. to 670 ° C. and a heating time is in a range of 30 minutes to 360 minutes. .
  12. 　前記ＣｕＴｉ拡散工程において、積層方向の荷重が０．２９４ＭＰａ以上１．９６ＭＰａ以下の範囲内とされていることを特徴とする請求項１０に記載の接合体の製造方法。 The method for manufacturing a joined body according to claim 10, wherein in the CuTi diffusion step, the load in the stacking direction is set in a range of 0.294 MPa to 1.96 MPa.
  13. 　セラミックス基板の一方の面にＣｕ又はＣｕ合金からなる回路層が配設されたパワーモジュール用基板の製造方法であって、
    　前記セラミックス基板と前記回路層を、請求項８から請求項１２のいずれか一項に記載の接合体の製造方法によって接合することを特徴とするパワーモジュール用基板の製造方法。     A method for manufacturing a power module substrate in which a circuit layer made of Cu or Cu alloy is disposed on one surface of a ceramic substrate,
    The method for manufacturing a power module substrate, wherein the ceramic substrate and the circuit layer are bonded by the method for manufacturing a bonded body according to any one of claims 8 to 12.
  14. 　セラミックス基板の一方の面に回路層が配設され、前記セラミックス基板の他方の面にＣｕ又はＣｕ合金からなる金属層が配設されたパワーモジュール用基板の製造方法であって、
    　前記セラミックス基板と前記金属層を、請求項８から請求項１２のいずれか一項に記載の接合体の製造方法によって接合することを特徴とするパワーモジュール用基板の製造方法。     A method for manufacturing a power module substrate, wherein a circuit layer is disposed on one surface of a ceramic substrate, and a metal layer made of Cu or Cu alloy is disposed on the other surface of the ceramic substrate,
    The method for manufacturing a power module substrate, wherein the ceramic substrate and the metal layer are bonded by the method for manufacturing a bonded body according to any one of claims 8 to 12.
  15. 　セラミックス基板の一方の面にＣｕ又はＣｕ合金からなる回路層が配設され、前記セラミックス基板の他方の面にＡｌ又はＡｌ合金からなる金属層が配設されたパワーモジュール用基板の製造方法であって、
    　前記セラミックス基板と前記回路層を、請求項８から請求項１２のいずれか一項に記載の接合体の製造方法によって接合することを特徴とするパワーモジュール用基板の製造方法。     A method for manufacturing a power module substrate, wherein a circuit layer made of Cu or Cu alloy is disposed on one surface of a ceramic substrate, and a metal layer made of Al or Al alloy is disposed on the other surface of the ceramic substrate. And
    The method for manufacturing a power module substrate, wherein the ceramic substrate and the circuit layer are bonded by the method for manufacturing a bonded body according to any one of claims 8 to 12.
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