WO2017119249A1 - Multilayer substrate and method for manufacturing multilayer substrate - Google Patents

Multilayer substrate and method for manufacturing multilayer substrate Download PDF

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Publication number
WO2017119249A1
WO2017119249A1 PCT/JP2016/087171 JP2016087171W WO2017119249A1 WO 2017119249 A1 WO2017119249 A1 WO 2017119249A1 JP 2016087171 W JP2016087171 W JP 2016087171W WO 2017119249 A1 WO2017119249 A1 WO 2017119249A1
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WO
WIPO (PCT)
Prior art keywords
multilayer substrate
insulator layer
resin
insulator
package component
Prior art date
Application number
PCT/JP2016/087171
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French (fr)
Japanese (ja)
Inventor
濱田　秀
茂 多胡
博史 品川
雅樹 川田
Original Assignee
株式会社村田製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 株式会社村田製作所 filed Critical 株式会社村田製作所
Priority to CN201690001339.6U priority Critical patent/CN208338048U/en
Publication of WO2017119249A1 publication Critical patent/WO2017119249A1/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits

Definitions

  • the present invention relates to a multilayer substrate and a method for manufacturing the multilayer substrate, and more particularly to a multilayer substrate including a base material on which an insulating layer made of a thermoplastic resin is laminated, and a method for manufacturing the multilayer substrate.
  • FIG. 26 is a cross-sectional structure diagram when the resin multilayer substrate 500 is manufactured.
  • the resin multilayer substrate 500 includes resin sheets 502a to 502d and components 503a and 503b. Through holes 514a and 514b are provided in the resin sheets 502b and 502c, respectively. Cavities 505a and 505b are formed by laminating such resin sheets 502b to 502d. Then, after the components 503a and 503b are accommodated in the cavities 505a and 505b, respectively, the resin sheet 502a is laminated on the resin sheet 502b. Thereby, the resin multilayer substrate 500 incorporating the components 503a and 503b is obtained.
  • an object of the present invention is to provide a multilayer substrate and a method for manufacturing the multilayer substrate that can improve the flatness of the main surface of the base material.
  • a multilayer substrate includes a base material formed by laminating a plurality of insulator layers made of a material including a first resin, which is a thermoplastic resin, in the stacking direction, and the base A package component embedded in a material, the package component having first and second planes positioned at both ends in the stacking direction and substantially perpendicular to the stacking direction.
  • the package component includes a first electronic component and a coating member made of a material containing a second resin and covering at least a part of the surface of the first electronic component.
  • the Young's modulus of the second resin is larger than the Young's modulus of the first resin at the softening point temperature of the first resin, and at least a part of the first plane and the second plane. At least a portion of It is constituted by coating member, and wherein.
  • At least a part of the surface of the first electronic component is covered with a coating member, so that it is positioned at both ends in the stacking direction and substantially in the stacking direction.
  • the coating member is made of a material containing a second resin, and the Young's modulus of the second resin is the first resin at the temperature of the heat treatment. Greater than Young's modulus It features a.
  • the flatness of the main surface of the substrate can be improved.
  • FIG. 1 is a cross-sectional structure diagram of an electronic device 10 including a multilayer substrate 20 according to an embodiment of the present invention.
  • FIG. 2A is a sectional view of the multilayer substrate 20.
  • FIG. 2B is an exploded view of the multilayer substrate 20.
  • FIG. 3A is a view of the electronic component 81 as viewed from above.
  • FIG. 3B is a view of the electronic component 81 as viewed from the front side.
  • FIG. 3C is a view of the package component 80 as viewed from above.
  • FIG. 3D is a view of the package component 80 as viewed from the front side.
  • FIG. 4A is a perspective view when the package component 80 is manufactured.
  • FIG. 4B is a perspective view when the package component 80 is manufactured.
  • FIG. 4A is a perspective view when the package component 80 is manufactured.
  • FIG. 4B is a perspective view when the package component 80 is manufactured.
  • FIG. 4C is a perspective view when the package component 80 is manufactured.
  • FIG. 4D is a perspective view when the package component 80 is manufactured.
  • FIG. 5A is a perspective view when the package component 80 is manufactured.
  • FIG. 5B is a perspective view when the package component 80 is manufactured.
  • FIG. 5C is a perspective view when the package component 80 is manufactured.
  • FIG. 5D is a perspective view when the package component 80 is manufactured.
  • FIG. 5E is a cross-sectional structure diagram when the multilayer substrate 20 is manufactured.
  • FIG. 6A is a cross-sectional structure diagram when the multilayer substrate 20 is manufactured.
  • FIG. 6B is a cross-sectional structure diagram when the multilayer substrate 20 is manufactured.
  • FIG. 7 is a cross-sectional structure diagram when the multilayer substrate 20 is manufactured.
  • FIG. 8 is a cross-sectional structure diagram of the multilayer substrate 20a.
  • FIG. 9A is a perspective view at the time of manufacturing the package component 80 and the insulator sheet 23.
  • FIG. 9B is a perspective view at the time of manufacturing the package component 80 and the insulator sheet 23.
  • FIG. 9C is a perspective view at the time of manufacturing the package component 80 and the insulator sheet 23.
  • FIG. 9D is a perspective view at the time of manufacturing the package component 80 and the insulator sheet 23.
  • FIG. 10 is a cross-sectional structure diagram when the multilayer substrate 20a is manufactured.
  • FIG. 11 is a cross-sectional structure diagram when the multilayer substrate 20a is manufactured.
  • FIG. 12 is a cross-sectional structure diagram of the multilayer substrates 20b and 20g.
  • FIG. 13 is a cross-sectional structure diagram when the multilayer substrates 20b and 20g are manufactured.
  • FIG. 14 is a cross-sectional structure diagram when the multilayer substrates 20b and 20g are manufactured.
  • FIG. 15 is a cross-sectional structure diagram of the multilayer substrates 20b and 20g during manufacturing.
  • FIG. 16 is a cross-sectional structure diagram of the multilayer substrates 20b and 20g during manufacturing.
  • FIG. 17 is a cross-sectional structure diagram of the multilayer substrate 20c.
  • FIG. 18 is a cross-sectional structure diagram when the multilayer substrate 20c is manufactured.
  • FIG. 19A is a cross-sectional structure diagram when the multilayer substrate 20c is manufactured.
  • FIG. 19B is a cross-sectional structure diagram when the multilayer substrate 20c is manufactured.
  • FIG. 20 is a cross-sectional structure diagram of the multilayer substrate 20d.
  • FIG. 21 is a sectional view of the multilayer substrate 20e.
  • FIG. 22 is a sectional view of the multilayer substrate 20f.
  • FIG. 23 is an external perspective view of the package component 80 of the multilayer board 20g.
  • FIG. 24A is a view of the package component 80 as viewed from above.
  • FIG. 24B is a cross-sectional structure diagram along AA in FIG. 24A.
  • 24C is a cross-sectional structure diagram taken along line BB in FIG. 24A.
  • FIG. 25 is an external perspective view of the package component 80 whose upper and lower surfaces are constituted by the external electrodes 84 a and 84 b and the coating member 86.
  • FIG. 26 is a cross-sectional structure diagram when the resin multilayer substrate 500 is manufactured.
  • FIG. 1 is a cross-sectional structure diagram of an electronic device 10 including a multilayer substrate 20 according to an embodiment of the present invention.
  • FIG. 2A is a sectional view of the multilayer substrate 20.
  • FIG. 2B is an exploded view of the multilayer substrate 20.
  • FIG. 3A is a view of the electronic component 81 as viewed from above.
  • FIG. 3B is a view of the electronic component 81 as viewed from the front side.
  • FIG. 3C is a view of the package component 80 as viewed from above.
  • 3D is a view of the package component 80 as viewed from the front side.
  • the via-hole conductors v100 and v102 are omitted.
  • the stacking direction of the multilayer substrate 20 is defined as the vertical direction.
  • 1, 2A, and 2B is defined as the front-rear direction (an example of the second orthogonal direction), and the left-right direction of the paper in FIGS. Example).
  • the up-down direction, the left-right direction, and the front-rear direction are orthogonal to each other.
  • the electronic device 10 is, for example, a mobile phone, a personal computer, a game machine, a wearable terminal, or the like.
  • FIG. 1 only modules and mother boards provided in the electronic device 10 are illustrated, and the casing of the electronic device 10 and other configurations are omitted.
  • the electronic device 10 includes a multilayer substrate 20, electronic components 60 and 70, and a mother substrate 100.
  • the multilayer substrate 20 is a plate-shaped resin substrate having a rectangular shape when viewed from above.
  • the long side extends in the left-right direction and the short side extends in the front-rear direction.
  • the multilayer substrate 20 includes a base material 22, external electrodes 24a to 24d, 26a and 26b, circuit conductor layers 28a to 28e, 29a to 29e, via-hole conductors v1 to v7, v11 to v17, v100, and v102.
  • the package part 80 is provided.
  • the external electrodes are provided in addition to the external electrodes 24a to 24d, 26a, and 26b, but the external electrodes other than the external electrodes 24a to 24d, 26a, and 26b are omitted in FIGS.
  • the circuit conductor layers are provided in addition to the circuit conductor layers 28a to 28e and 29a to 29e, but the circuit conductor layers other than the circuit conductor layers 28a to 28e and 29a to 29e are shown in FIGS. Omitted.
  • via-hole conductors are provided in addition to the via-hole conductors v1 to v7 and v11 to v17, but the via-hole conductors other than the via-hole conductors v1 to v7 and v11 to v17 are omitted in FIGS. 1 and 2A.
  • the base material 22 is a flexible plate-like member having a rectangular shape when viewed from above, as shown in FIG. 2A.
  • the base material 22 is a laminate in which insulator sheets 22a to 22g (an example of a plurality of insulator layers) are laminated in this order from the upper side to the lower side.
  • the base material 22 has two main surfaces.
  • the upper main surface of the base material 22 is referred to as a front surface
  • the lower main surface of the base material 22 is referred to as a back surface.
  • the back surface of the base material 22 is a mounting surface that faces the mother substrate 100 when the multilayer substrate 20 is mounted.
  • the insulator sheets 22a to 22g have a rectangular shape when viewed from above, and have the same shape as the base material 22.
  • the insulator sheets 22a to 22g are made of a material including a flexible thermoplastic resin (an example of a first resin) such as polyimide or liquid crystal polymer.
  • a flexible thermoplastic resin an example of a first resin
  • the upper main surface of the insulator sheets 22a to 22g is referred to as a front surface
  • the lower main surface of the insulator sheets 22a to 22g is referred to as a back surface.
  • through holes H1 to H3 having a rectangular shape when viewed from above are provided at the centers (near the intersections of the diagonal lines) of the insulator sheets 22b to 22d, respectively.
  • the through holes H1 to H3 are formed so as to connect the front and back surfaces of the insulator sheets 22b to 22d, respectively. Further, the outer edges of the through holes H1 to H3 overlap each other when viewed from above. Therefore, the through holes H1 to H3 are connected to one.
  • the upper opening of the through hole H1 is closed by the insulator sheet 22a.
  • the opening on the lower side of the through hole H3 is blocked by the insulator sheet 22e.
  • a rectangular parallelepiped space Sp in which the through holes H1 to H3 are connected is formed in the base material 22.
  • the package component 80 is built in the base material 22 and has a rectangular parallelepiped shape.
  • a surface positioned on the upper side is referred to as an upper surface (an example of the first plane)
  • a surface positioned on the lower side Is called the lower surface (an example of the second plane)
  • the front surface is called the front surface
  • the rear surface is called the rear surface
  • the right surface is called the right surface
  • the left surface is Called the left side.
  • the upper surface, the lower surface, the front surface, the rear surface, the right surface, and the left surface are substantially flat.
  • the upper surface and the lower surface are planes that are substantially perpendicular to the vertical direction.
  • the front surface, the rear surface, the right surface, and the left surface are planes that are substantially perpendicular to the upper surface and the lower surface and substantially parallel to the vertical direction.
  • the front surface, the rear surface, the right surface, and the left surface may be collectively referred to as a side surface.
  • chamfering is not performed on the joint portions of the upper surface, the lower surface, the front surface, the rear surface, the right surface, and the left surface, but the joint portions may be chamfered. It should be noted that being substantially flat and being substantially parallel or vertical means that it is allowed to slightly deviate from the plane or slightly deviate from parallel or vertical due to manufacturing variations.
  • the package component 80 is accommodated in the space Sp. Thereby, the package component 80 penetrates the insulator sheets 22b to 22d in the vertical direction. Furthermore, the back surface of the insulator sheet 22 a is in contact with the upper surface of the package component 80, and the surface of the insulator sheet 22 e (an example of the first insulator layer) is in contact with the lower surface of the package component 80. Further, the inner peripheral surfaces of the through holes H 1 to H 3 are in contact with the side surfaces of the package component 80. Further, the insulator sheets 22a to 22e are fixed to the package component 80. More specifically, as will be described later, the insulator sheets 22a to 22g are solidified after being softened in the thermocompression bonding process of the base material 22.
  • the insulating sheets 22a to 22g are softened, the insulating sheets 22a to 22e are formed in the gaps between the inner peripheral surface of the space Sp and the upper, lower, and side surfaces (hereinafter also referred to as surfaces) of the package component 50.
  • the gaps are filled, and the gaps are filled with the insulator sheets 22a to 22e.
  • the insulator sheets 22a to 22e are solidified, the inner peripheral surface of the space Sp and the surface of the package component 50 are fixed and are not easily separated.
  • the package component 80 includes an electronic component 81 (an example of a first electronic component) and a coating member 86, as shown in FIGS. 2A and 3A to 3D.
  • the electronic component 81 is, for example, a chip-type electronic component such as a capacitor or an inductor, and includes a main body 82 (an example of a first main body) and external electrodes 84 and 84b.
  • the main body 82 is a rectangular parallelepiped member made of a material such as ceramic, and includes circuit elements (not shown) such as capacitors and inductors therein.
  • the external electrode 84 a (an example of the first external electrode) is provided on the surface of the main body 82, and is provided on either the upper surface or the lower surface of the main body 82.
  • the external electrode 84a covers the entire left surface of the main body 82 (an example of a surface on one side in the first orthogonal direction) and is an area adjacent to the left surface, and has an upper surface (one side in the stacking direction).
  • the external electrode 84 b is provided on either the upper surface or the lower surface of the main body 82.
  • the external electrode 84b is provided on the surface of the main body 82.
  • the external electrode 84b covers the entire right surface of the main body 82 and is adjacent to the right surface, and includes an upper surface, a lower surface, a front surface, and a front surface. It covers a part of the rear surface.
  • the external electrodes 84a and 84b are formed, for example, by performing nickel plating and tin plating on a base electrode formed by applying a conductive paste mainly composed of silver or the like.
  • the coating member 86 is made of a material containing a thermosetting resin (an example of a second resin) such as an epoxy resin, and covers at least a part of the surface of the electronic component 81. Thereby, at least a part of the upper surface of the package component 80 and at least a part of the lower surface of the package component 80 are constituted by the coating member 86. In the present embodiment, the coating member 86 covers the entire surface of the electronic component 81. Therefore, the electronic component 81 is not exposed from the coating member 86. The entire upper surface of the package component 80 and the entire lower surface of the package component 80 are constituted by a coating member 86.
  • the lower surface of the coating member 86 (that is, the lower surface of the package component 80)
  • through holes for via-hole conductors v100 and v102 described later are provided on the lower surface of the coating member 86 (that is, the lower surface of the package component 80). Therefore, the lower surface of the coating member 86 (that is, the lower surface of the package component 80) is recessed in the through hole. However, since the through hole is small, the lower surface of the coating member 86 (that is, the lower surface of the package component 80) is interpreted as a plane for convenience.
  • the Young's modulus of a thermosetting resin such as an epoxy resin used for the coating member 86 at the softening point temperature of a thermoplastic resin such as polyimide or liquid crystal polymer used for the insulator sheets 22a to 22g is as follows. It is larger than the Young's modulus of thermoplastic resins such as polyimide and liquid crystal polymer used for 22g.
  • the softening point is the temperature at which the temperature of the resin rises and begins to deform.
  • the softening point of polyimide is 120 ° C., for example, and the softening point of liquid crystal polymer is 150 ° C., for example.
  • the softening point means a value measured according to the method described in JIS K7206.
  • the linear expansion coefficient of a thermosetting resin such as an epoxy resin used for the coating member 86 is equal to or higher than the linear expansion coefficient of the material (ceramic) of the main body 82, and polyimide or the like used for the insulator sheets 22a to 22g. It is below the linear expansion coefficient of thermoplastic resins, such as a liquid crystal polymer. More specifically, the linear expansion coefficient of the ceramic is, for example, about 7 ⁇ 10 ⁇ 6 / ° C., the linear expansion coefficient of the liquid crystal polymer is, for example, about 16 ⁇ 10 ⁇ 6 / ° C., and the linear expansion coefficient of the epoxy resin. Is, for example, about 10 ⁇ 10 ⁇ 6 / ° C. However, the linear expansion coefficient of the epoxy resin may be adjusted by the amount of filler added to the epoxy resin.
  • the external electrodes 24a to 24d are rectangular conductor layers and are provided on the surface of the insulator sheet 22a.
  • the external electrodes 24a to 24d are arranged in this order from the left side to the right side.
  • the external electrodes 26a and 26b are rectangular conductor layers, and are provided on the back surface of the insulator sheet 22g.
  • the external electrodes 26a and 26b are arranged in this order from the left side to the right side.
  • the circuit conductor layers 28a to 28e and 29a to 29e are conductor layers provided on the surfaces of the insulator sheets 22b to 22f, respectively, and constitute a part of the circuit in the multilayer substrate 20.
  • the circuit conductor layers 28a to 28e and 29a to 29e are linear wirings in FIG. 2, but may be capacitor conductors, ground conductors, or the like having a rectangular shape.
  • the circuit conductor layers 28 a to 28 e extend in the left-right direction on the left side with respect to the package component 80. However, the right end of the circuit conductor layer 28e overlaps with the package component 80 when viewed from above.
  • the circuit conductor layers 29 a to 29 e extend in the left-right direction on the right side with respect to the package component 80. However, the left end of the circuit conductor layer 29e overlaps with the package component 80 when viewed from above.
  • the material of the circuit conductor layers 28a to 28e, 29a to 29e and the external electrodes 24a to 24d, 26a, and 26b as described above is, for example, a metal foil made of copper.
  • the surface of the circuit conductor layers 28a to 28e, 29a to 29e and the external electrodes 24a to 24d, 26a and 26b is plated with zinc to reduce the surface roughness.
  • the surface roughness of the main surfaces of the circuit conductor layers 28a to 28e, 29a to 29e and the external electrodes 24a to 24d, 26a, and 26b that are in contact with the insulator sheets 22a to 22g is the circuit conductor layers 28a to 28e, 29a.
  • the surface roughness of the main surfaces not contacting the insulator sheets 22a to 22g is larger.
  • the circuit conductor layers 28a to 28e, 29a to 29e, the external electrodes 24a to 24d, 26a and 26b, and the insulator sheets 22a to 22g are made of the circuit conductor layers 28a to 28e, 29a to 29e and external electrodes 24a to 24d, 26a and 26b are physically fixed by entering into the irregularities, and are not chemically bonded. For this reason, there is almost no foreign matter such as a resin serving as an adhesive component at the boundary between the circuit conductor layers 28a to 28e, 29a to 29e, the external electrodes 24a to 24d, 26a and 26b, and the insulator sheets 22a to 22g. .
  • the via-hole conductors v1 to v7 are interlayer connection conductors that penetrate the insulating sheets 22a to 22g in the vertical direction, respectively.
  • Each of the via-hole conductors v1 to v6 has a shape that becomes thicker from the upper side to the lower side.
  • the via-hole conductor v7 has a shape that becomes thinner from the upper side to the lower side.
  • the via-hole conductor v1 connects the external electrode 24a and the circuit conductor layer 28a.
  • the via-hole conductor v2 connects the circuit conductor layer 28a and the circuit conductor layer 28b.
  • the via-hole conductor v3 connects the circuit conductor layer 28b and the circuit conductor layer 28c.
  • the via-hole conductor v4 connects the circuit conductor layer 28c and the circuit conductor layer 28d.
  • the via-hole conductor v5 connects the circuit conductor layer 28d and the circuit conductor layer 28e.
  • the via hole conductor v6 and the via hole conductor v7 are connected to each other to form a series of via hole conductors.
  • the via-hole conductors v6 and v7 connect the circuit conductor layer 28e and the external electrode 26a. Thereby, the external electrode 24a and the external electrode 26a are electrically connected.
  • Via-hole conductors v11 to v17 are interlayer connection conductors penetrating the insulating sheets 22a to 22g in the vertical direction, respectively.
  • Each of the via-hole conductors v11 to v16 has a shape that becomes thicker from the upper side to the lower side.
  • the via-hole conductor v17 has a shape that becomes thinner from the upper side to the lower side.
  • the via-hole conductor v11 connects the external electrode 24b and the circuit conductor layer 29a.
  • the via-hole conductor v12 connects the circuit conductor layer 29a and the circuit conductor layer 29b.
  • the via-hole conductor v13 connects the circuit conductor layer 29b and the circuit conductor layer 29c.
  • the via-hole conductor v14 connects the circuit conductor layer 29c and the circuit conductor layer 29d.
  • the via-hole conductor v15 connects the circuit conductor layer 29d and the circuit conductor layer 29e.
  • the via hole conductor v16 and the via hole conductor v17 constitute a series of via hole conductors by being connected to each other.
  • the via-hole conductors v16 and v17 connect the circuit conductor layer 29e and the external electrode 26b. Thereby, the external electrode 24d and the external electrode 26b are electrically connected.
  • the via-hole conductor v100 (an example of a connection conductor) penetrates the coating member 86 and the insulating sheet 22e in the vertical direction, and connects the external electrode 84a and the circuit conductor layer 28e. More specifically, the upper end of the via hole conductor v100 is connected to the external electrode 84a, and the lower end of the via hole conductor v100 is connected to the circuit conductor layer 28e.
  • the via-hole conductor v100 penetrates the coating member 86 existing between the external electrode 84a and the lower surface of the package component 80 in the vertical direction and penetrates the insulator sheet 22e in the vertical direction. Therefore, the via-hole conductor v100 passes through the lower surface of the package component 80.
  • the via-hole conductor v102 penetrates the coating member 86 and the insulating sheet 22e in the vertical direction, and connects the external electrode 84b and the circuit conductor layer 29e. More specifically, the upper end of the via hole conductor v102 is connected to the external electrode 84b, and the lower end of the via hole conductor v102 is connected to the circuit conductor layer 29e.
  • the via-hole conductor v102 penetrates the coating member 86 existing between the external electrode 84b and the lower surface of the package component 80 in the vertical direction and penetrates the insulator sheet 22e in the vertical direction. Therefore, the via-hole conductor v102 passes through the lower surface of the package component 80.
  • Via-hole conductors v1 to v7, v11 to v17, v100, and v102 are solidified conductive pastes mainly composed of metals such as copper, tin, and silver.
  • the material of the via-hole conductors v1 to v7 and v11 to v17 and the material of the via-hole conductors v100 and v102 are the same.
  • the electronic components 60 and 70 are electronic components mounted on the surface of the base material 22 and are, for example, semiconductor integrated circuits. However, the electronic components 60 and 70 may be chip-type electronic components such as capacitors and inductors.
  • the electronic component 60 includes a main body 60a and external electrodes 62a and 62b.
  • the main body 60a has a rectangular parallelepiped shape.
  • the external electrodes 62a and 62b are provided on the lower surface of the main body 60a, and are arranged in this order from the left side to the right side.
  • the external electrodes 62a and 62b are connected to the external electrodes 24a and 24b, for example, by solders 64a and 64b.
  • the electronic component 70 includes a main body 70a and external electrodes 72a and 72b.
  • the main body 70a has a rectangular parallelepiped shape.
  • the external electrodes 72a and 72b are provided on the lower surface of the main body 70a, and are arranged in this order from the left side to the right side.
  • the external electrodes 72a and 72b are connected to the external electrodes 24c and 24d by, for example, solders 74a and 74b.
  • the mother board 100 is a large circuit board used for a mobile phone or the like.
  • the mother substrate 100 is basically a hard substrate that does not have flexibility, but may have flexibility.
  • the mother substrate 100 includes a main body 102 and external electrodes 104a and 104b.
  • the main body 102 is a plate-shaped multilayer substrate having a rectangular shape when viewed from above.
  • An electric circuit is formed inside and on the surface of the main body 102.
  • the upper main surface of the main body 102 is referred to as a front surface
  • the lower main surface of the main body 102 is referred to as a back surface.
  • a surface mount type component, a shield case, or the like may be mounted on at least one of the front surface and the back surface of the mother substrate 100.
  • the external electrodes 104 a and 104 b are rectangular conductor layers and are provided on the surface of the main body 102.
  • the external electrodes 104a and 104b are arranged in this order from the left side to the right side.
  • the mother substrate 100 may further be provided with external electrodes (not shown) other than the external electrodes 104a and 104b.
  • the multilayer substrate 20 is mounted on the surface of the mother substrate 100. More specifically, the external electrodes 26a and 26b are mounted on the external electrodes 104a and 104b by solders 110a and 110b, respectively.
  • FIGS. 5A to 5D are perspective views when the package component 80 is manufactured. 4A to 4D and 5A to 5D that the electronic component 81 is indicated by a dotted line means that the electronic component 81 is present in the resin. 5E, FIG. 6A, FIG. 6B, and FIG. 7 are cross-sectional structure diagrams when the multilayer substrate 20 is manufactured.
  • a case where one multilayer substrate 20 is manufactured will be described as an example, but actually, a plurality of multilayer substrates 20 are manufactured simultaneously by laminating and cutting large-sized insulator sheets.
  • the manufacturing method of the package component 80 will be described with reference to FIGS. 4A to 4D and FIGS. 5A to 5D.
  • this step an example of the first step
  • the package component 80 is formed by covering the entire surface of the electronic component 81 with the coating member 86.
  • a plurality of electronic components 81 are arranged on a resin sheet 200 such as a PET film.
  • a resin sheet 200 such as a PET film.
  • the material containing the UV curable epoxy resin is irradiated with UV.
  • the resin layer 202 is formed.
  • the plurality of electronic components 81 are buried in the resin layer 202.
  • the upper surface of the resin layer 202 is polished with a grinder to adjust the vertical thickness of the resin layer 202 to an appropriate value, and the upper surface of the resin layer 202 is flattened.
  • the resin sheet 200 is peeled from the plurality of electronic components 81 and the resin layer 202. At this time, a part of the external electrodes 84 a and 84 b is exposed from the resin layer 202.
  • the resin sheet 201 is attached to the lower surfaces of the plurality of electronic components 81 and the resin layer 202.
  • a liquid material containing a UV curable epoxy resin is applied onto the resin layer 202, and then the material containing the UV curable epoxy resin is irradiated with UV.
  • the resin layer 203 is formed. Thereby, the plurality of electronic components 81 are buried in the resin layers 202 and 203 and are not exposed to the outside.
  • the resin layer 203 may be formed in advance, a plurality of electronic components 81 may be disposed on the resin layer 203, and the resin layer 202 may be formed on the resin layer 203.
  • the upper surface of the resin layer 203 is polished by a grinder to adjust the vertical thickness of the resin layers 202 and 203 to an appropriate value, and the upper surface of the resin layer 203 is flattened.
  • the resin layers 202 and 203 are cut with a dicer, and then the resin sheet 201 is peeled from the resin layer 203. Thereby, a plurality of package parts 80 are completed.
  • insulator sheets 22a to 22g made of a liquid crystal polymer are prepared.
  • a copper foil is formed on the entire main surface of one of the insulator sheets 22a to 22g. Specifically, copper foil is attached to the surfaces of the insulator sheets 22a to 22f. A copper foil is attached to the back surface of the insulator sheet 22g. Furthermore, the surface of the copper foils of the insulator sheets 22a to 22g is smoothed by, for example, applying zinc plating for rust prevention. In addition, metal foils other than copper foil may be used.
  • through holes H1 to H3 are formed in the insulating sheets 22b to 22d.
  • the through holes H1 to H3 are formed, for example, by irradiating a laser beam from the back surfaces of the insulator sheets 22b to 22d.
  • the through holes H1 to H3 may be formed by punching the insulating sheets 22b to 22d by punching.
  • the external electrodes 24a to 24d are formed on the surface of the insulator sheet 22a as shown in FIG. 2A.
  • a resist having the same shape as the external electrodes 24a to 24d shown in FIG. 3 is printed on the copper foil on the surface of the insulating sheet 22a.
  • the copper foil of the part which is not covered with the resist is removed by performing an etching process with respect to copper foil. Thereafter, the resist is removed by spraying a cleaning liquid (resist removing liquid).
  • a cleaning liquid resist removing liquid
  • circuit conductor layers 28a and 29a are formed on the surface of the insulator sheet 22b. Further, as shown in FIG. 2A, circuit conductor layers 28b and 29b are formed on the surface of the insulator sheet 22c. Further, as shown in FIG. 2A, circuit conductor layers 28c and 29c are formed on the surface of the insulator sheet 22d. Further, as shown in FIG. 2A, circuit conductor layers 28d and 29d are formed on the surface of the insulator sheet 22e. Further, as shown in FIG. 2A, circuit conductor layers 28e and 29e are formed on the surface of the insulator sheet 22f. As shown in FIG.
  • the external electrodes 26a and 26b are formed on the back surface of the insulating sheet 22g.
  • the process of forming the circuit conductor layers 28a to 28e, 29a to 29e and the external electrodes 26a and 26b is the same as the process of forming the external electrodes 24a and 24b, and the description thereof will be omitted.
  • the step of forming the through holes H1 to H3 may be performed after the step of forming the external electrodes 24a, 24b, 26a, 26b and the circuit conductor layers 28a to 28e, 29a to 29e.
  • a through hole is formed by irradiating a laser beam at a position where the via-hole conductors v1 to v4, v6, v7, v11 to v14, v16, and v17 are formed. Then, the through hole is filled with a conductive paste whose main component is a metal such as copper, tin or silver.
  • an insulator sheet 22e (an example of a first insulator layer) that contacts the lower surface of the package component 80, and an upper side (an example of one side in the stacking direction) of the insulator sheet 22e.
  • the insulating sheets 22a to 22e are stacked so as to incorporate the package component 80 in the insulating sheets 22a to 22d (an example of the third insulating layer) stacked on (4). That is, after the insulating sheets 22a to 22d are stacked, the package component 80 is inserted into the through holes H1 to H3 from the lower side, and the insulating sheet 22e is stacked on the lower side of the insulating sheet 22d.
  • the insulator sheets 22a to 22e are subjected to heat treatment and pressure treatment (thermocompression treatment), and the insulator sheets 22a to 22e are thermocompression bonded (hereinafter, this process is also referred to as a primary press).
  • the heat treatment is performed at a temperature not lower than the softening point of the thermoplastic resin constituting the insulating sheets 22a to 22g and at which the thermosetting resin constituting the coating member 86 is not decomposed (for example, 260 ° C. to 290 ° C.).
  • this heat treatment temperature it is sufficient that the thermosetting resin constituting the coating member 86 does not soften more greatly than the thermoplastic resin constituting the insulator sheets 22a to 22g.
  • Softening means that Young's modulus becomes small.
  • the Young's modulus of the resin that constitutes the coating member 86 only needs to be larger than the Young's modulus of the resin that constitutes the insulator sheets 22a to 22g under the same heat treatment temperature condition.
  • the insulator sheets 22a to 22e are softened and the conductive paste in the through holes is solidified.
  • the insulator sheets 22a to 22e are joined together, and the via-hole conductors v1 to v4 and v11 to v14 are formed.
  • thermoplastic resin of the insulator sheets 22a to 22e is softened by thermocompression, so that the thermoplastic resin flows into the gap formed between the inner peripheral surface of the space Sp and the surface of the package component 80. Thereafter, the insulator sheets 22a to 22e are cooled to solidify the thermoplastic resin, and the inner peripheral surface of the space Sp and the surface of the package component 80 are fixed.
  • a through hole is formed by irradiating a laser beam at a position where the via-hole conductors v5, v15, v100, and v102 are formed.
  • the through hole is provided so as to penetrate a part of the insulating sheet 22e and the coating member 86 and to expose a part of the external electrodes 84a and 84b of the package component 80.
  • the through hole is filled with a conductive paste mainly composed of a metal such as copper, tin, or silver.
  • insulator sheets 22f and 22g (an example of a fourth insulator layer) stacked on the lower side (an example of the other side in the stacking direction) of the insulator sheet 22e are insulators.
  • Laminate below the sheet 22e (an example of the second step and the sixth step).
  • the conductive paste (an example of a connection conductor) to be the via-hole conductors v100 and v102 and the circuit conductor layers 28e and 29e are connected.
  • the insulating sheets 22a to 22g are subjected to heat treatment and pressure treatment (thermocompression treatment), and the insulating sheets 22a to 22g are thermocompression bonded to form the base material 22 (hereinafter, this process is referred to as 2). Also called the next press, an example of the third step). At this time, heat treatment is performed at a temperature (for example, 260 ° C. to 290 ° C.) that is equal to or higher than the softening point of the thermoplastic resin that forms the insulating sheets 22a to 22g and that does not decompose the thermosetting resin that forms the coating member 86. I do. In the secondary press, the insulator sheets 22a to 22g are softened and the conductive paste in the through holes is solidified.
  • a temperature for example, 260 ° C. to 290 ° C.
  • the insulator sheets 22a to 22g are joined together, and the via-hole conductors v5 to v7, v15 to v17, v100, and v102 are formed (an example of the fifth step).
  • the via hole conductor v100 connects the external electrode 84a and the circuit conductor layer 28e, and the via hole conductor v102 connects the external electrode 84b and the circuit conductor layer 29e.
  • the multilayer substrate 20 is completed through the above steps.
  • the electronic components 60 and 70 are soldered to the base material 22 with solder 64a, 64b, 74a. It is mounted by 74b.
  • the multilayer substrate 20 is mounted on the mother substrate 100 with solders 110a and 110b. After that, the electronic device 10 is completed by mounting the mother substrate 100 on the housing.
  • the flatness of the upper surface and the lower surface of the base material 22 can be improved. More specifically, in the resin multilayer substrate 500 described in Patent Document 1, external electrodes (not shown) are provided on the upper and lower surfaces of the components 503a and 503b. Therefore, there are irregularities on the upper and lower surfaces of the components 503a and 503b. When such irregularities exist, large gaps are formed between the upper and lower surfaces of the components 503a and 503b and the resin sheets 502a and 502d. In the thermocompression bonding process, the resin sheets 502a and 502d in the vicinity of the components 503a and 503b soften and flow and flow into the gap. As a result, irregularities are formed on the upper and lower surfaces of the resin multilayer substrate 500 directly above and below the components 503a and 503b and in the vicinity thereof.
  • the coating member 86 is made of a material including a thermosetting resin and covers at least a part of the surface of the electronic component 81.
  • a part of the upper and lower surfaces of the package component 80 is constituted by a coating member 86. That is, the unevenness of the upper surface and the lower surface of the electronic component 81 is flattened by the coating member 86.
  • the Young's modulus of the thermosetting resin constituting the coating member 86 at the softening point temperature of the thermoplastic resin constituting the insulator sheets 22a to 22g constitutes the insulator sheets 22a to 22g. It is larger than the Young's modulus of the thermoplastic resin.
  • the coating member 86 is not softened or hardly softened, and the insulator sheets 22a to 22g are softened.
  • the insulating sheets 22a to 22g soften and flow while the upper and lower surfaces of the package component 80 are maintained flat, and a gap between the surface of the package component 80 and the inner peripheral surface of the space Sp is formed. fill in.
  • the insulator sheets 22a and 22e in the vicinity of the package component 80 are suppressed from being softened and flowed and flowing into the gap in a large amount.
  • the front and back surfaces of the multilayer substrate 20 it is possible to suppress the formation of irregularities directly above and below the package component 80 and in the vicinity thereof.
  • the occurrence of disconnection between the electronic component 81 and the circuit conductor layers 28e and 29e is suppressed. More specifically, since the upper surface and the lower surface of the package component 80 are flat, the gap between the upper surface of the package component 80 and the back surface of the insulator sheet 22a, and the lower surface of the package component 80 and the surface of the insulator sheet 22a. The gap between is very small. Therefore, in the process of FIG. 5E, for example, the package component 80 is prevented from rotating around an axis extending in the front-rear direction (clockwise or counterclockwise in FIG. 5E). Thereby, in the process shown in FIG.
  • the back surface of the insulator sheet 22e immediately below the package component 80 is suppressed from being inclined. Accordingly, the vertical positions of the lower end of the via-hole conductor v100 and the lower end of the via-hole conductor v102 are aligned. As a result, in the step shown in FIG. 7, the via-hole conductor v100 and the circuit conductor layer 28e are more reliably connected, and the via-hole conductor v102 and the circuit conductor layer 29e are more reliably connected.
  • the side surface of the package component 80 is a plane parallel to the vertical direction.
  • the gap between the side surface of the package component 80 and the inner peripheral surfaces of the through holes H1 to H3 is very small. This suppresses a large amount of the insulator sheets 22b to 22e from flowing into the gap during the heat treatment and pressure treatment of the base material 22. As a result, the package component 80 is prevented from rotating around the axis extending in the vertical direction in the space Sp.
  • the gap between the inner peripheral surface of the space Sp and the package component 80 can be reduced when the multilayer substrate 20 is manufactured.
  • the package component 80 is configured by covering an electronic component 81 with a coating member 86. Therefore, the coating member 86 can be processed into an arbitrary shape and size by processing the coating member 86 by polishing or the like. As a result, the shape of the coating member 86 and the shape of the space Sp can be made closer, and the gap between the inner peripheral surface of the space Sp and the package component 80 can be reduced.
  • the gap between the inner peripheral surface of the space Sp and the package component 80 is reduced, the flatness of the upper surface and the lower surface of the base material 22 is improved and the rotation of the package component 80 in the space Sp is suppressed. Is done. Therefore, the occurrence of mounting mistakes in the electronic components 60 and 70 and the multilayer substrate 20 is suppressed, and the occurrence of disconnection between the electronic component 81 and the circuit conductor layers 28e and 29e is suppressed.
  • the material of the via-hole conductors v100 and v102 is the same as the material of the via-hole conductors v1 to v7 and v11 to v17. Therefore, the via-hole conductors v6, v7, v16, v17, v100, and v102 can be simultaneously cured during the heat treatment and pressure treatment of the base material 22.
  • the multilayer substrate 20 it is possible to suppress the occurrence of peeling between the main body 82 and the coating member 86 and the peeling between the coating member 86 and the insulating sheets 22a to 22e. More specifically, heat treatment is performed when the multilayer substrate 20 is manufactured. Since the main body 82, the coating member 86, and the insulator sheets 22a to 22e are made of different materials, their expansion amounts are also different. Such a difference in the expansion amount causes peeling between the main body 82 and the coating member 86 and peeling between the coating member 86 and the insulating sheets 22a to 22e.
  • the linear expansion coefficient of a thermoplastic resin such as an epoxy resin used for the coating member 86 is equal to or greater than the linear expansion coefficient of the material (ceramic) of the main body 82, and the insulator sheets 22a to 22g It is below the linear expansion coefficient of thermoplastic resins, such as a polyimide used and liquid crystal polymer.
  • thermoplastic resin The difference between the linear expansion coefficient of the thermoplastic resin and the linear expansion coefficient of the thermoplastic resin such as polyimide or liquid crystal polymer used for the insulator sheets 22a to 22g can be reduced. As a result, the difference in the expansion amount is reduced, and the occurrence of the peeling is suppressed.
  • FIG. 8 is a cross-sectional structure diagram of the multilayer substrate 20a.
  • the multilayer substrate 20 a is different from the multilayer substrate 20 in the structure of the package component 80. More specifically, in the multilayer substrate 20a, the external electrodes 84a and 84b are exposed on the lower surface of the package component 80. Instead, the lower surface of the package component 80 is covered with the insulator sheet 23 (an example of a second insulator layer). Hereinafter, the multilayer substrate 20a will be described focusing on the difference.
  • the lower surface of the package component 80 is a flat surface. However, a part of the lower surface of the package component 80 is configured by the coating member 86, and the remaining portion of the lower surface of the package component 80 is configured by the external electrodes 84a and 84b. Furthermore, the insulator sheet 23 has the same shape and the same size as the lower surface of the package component 80 when viewed from above, and covers the entire lower surface of the package component 80. Further, the sum of the vertical thickness of the package component 80 and the vertical thickness of the insulating sheet 23 is substantially equal to the total vertical thickness of the insulating sheets 22b to 22d.
  • the via-hole conductor v100 penetrates the insulator sheets 23 and 22e in the vertical direction, and connects the external electrode 84a and the circuit conductor layer 28e. However, the via-hole conductor v100 does not penetrate the coating member 86.
  • the via-hole conductor v102 penetrates the insulator sheets 23 and 22e in the vertical direction, and connects the external electrode 84b and the circuit conductor layer 29e. However, the via-hole conductor v102 does not penetrate the coating member 86.
  • 9A to 9D are perspective views at the time of manufacturing the package component 80 and the insulator sheet 23.
  • 9A to 9D that the electronic component 81 is indicated by a dotted line means that the electronic component 81 is present in the resin.
  • 10 and 11 are cross-sectional structure diagrams when the multilayer substrate 20a is manufactured.
  • the mother sheet 223 is made of a material containing a flexible thermoplastic resin such as polyimide or liquid crystal polymer, and is a large sheet in which the insulator sheets 23 are arranged in a matrix when viewed from above. is there.
  • the material of the mother sheet 223 is the same as the material of the insulator sheets 22a to 22g.
  • the material containing the UV curable epoxy resin is irradiated with UV, and the resin Layer 202 is formed. Accordingly, the plurality of electronic components 81 are buried in the resin layer 202 so that at least a part of the lower surfaces of the external electrodes 84 a and 84 b of the plurality of electronic components 81 are in contact with the mother sheet 223.
  • the upper surface of the resin layer 202 is polished with a grinder to adjust the vertical thickness of the resin layer 202 to an appropriate value, and the upper surface of the resin layer 202 is flattened.
  • the resin layer 202 is cut with a dicer. Thereby, a plurality of package components 80 having the insulator sheet 23 attached to the lower surface are completed.
  • the conductive material is conducted to the through holes formed at positions where the via-hole conductors v1 to v4, v6, v7, v11 to v14, v16, and v17 are formed.
  • the steps up to the step of filling the conductive paste are the same as those steps in the method for manufacturing the multilayer substrate 20, and thus the description thereof is omitted.
  • the through hole is provided so as to penetrate part of the insulator sheet 22e and the insulator sheet 23 and to expose part of the external electrodes 84a and 84b of the package component 80.
  • the package component 80 to which the insulator sheet 23 is attached is inserted into the through holes H1 to H3 from below, and the insulator sheets 22e is laminated below the insulator sheet 22d. Further, heat treatment and pressure treatment (also referred to as thermocompression treatment) are performed on the insulator sheets 22a to 22e (hereinafter, this step is also referred to as a primary press).
  • a through-hole is formed by irradiating a laser beam at a position where the via-hole conductors v5, v15, v100, and v102 are formed. These through holes are filled with a conductive paste whose main component is a metal such as copper, tin or silver. Note that the subsequent steps of the method for manufacturing the multilayer substrate 20a are the same as the method for manufacturing the multilayer substrate 20, and thus the description thereof is omitted.
  • the multilayer substrate 20 a configured as described above can also exhibit the same operational effects as the multilayer substrate 20.
  • the package component 80 can be easily created. More specifically, in the method for manufacturing the multilayer substrate 20, the resin sheet 200 is peeled from the plurality of electronic components 81 and the resin layer 202 in the step illustrated in FIG. 4D. Further, in the step of FIG. 5A, after the front and back of the plurality of electronic components 81 and the resin layer 202 are reversed, the resin sheet 201 is attached to the lower surfaces of the plurality of electronic components 81 and the resin layer 202. As described above, in the method for manufacturing the multilayer substrate 20, it is necessary to peel the resin sheet 200 and attach the resin sheet 201 in order to cover the entire electronic component 81 with the coating member 86.
  • a mother sheet 223 is used instead of the resin sheets 200 and 201.
  • the material of the mother sheet 223 is the same material as the insulator sheets 22a to 22g. Therefore, the insulator sheet 23 obtained by dividing the mother sheet 223 is used as a part of the base material 22 without being peeled off from the lower surface of the package component 80. Therefore, in the manufacturing method of the multilayer substrate 20a, processes such as peeling and reversal are unnecessary, and the package component 80 can be easily created.
  • FIG. 12 is a cross-sectional structure diagram of the multilayer substrates 20b and 20g.
  • the multilayer substrate 20b is different from the multilayer substrate 20 in that the via-hole conductors v100 and v102 are further provided with circuit conductor layers 28f and 29f and via-hole conductors v8 and v18.
  • the multilayer substrate 20b will be described focusing on the differences related to the following.
  • the circuit conductor layers 28f and 29f are provided on the surface of the insulator sheet 22e.
  • the circuit conductor layer 28f is provided on the right side of the circuit conductor layer 28d and extends in the left-right direction.
  • the circuit conductor layer 29f is provided on the left side of the circuit conductor layer 29d and extends in the left-right direction.
  • the circuit conductor layers 28 f and 29 f are in contact with the lower surface of the package component 80.
  • the via-hole conductor v8 penetrates the insulator sheet 22e in the vertical direction, and connects the circuit conductor layer 28f and the circuit conductor layer 28e.
  • the via-hole conductor v18 penetrates the insulator sheet 22e in the vertical direction, and connects the circuit conductor layer 29f and the circuit conductor layer 29e.
  • the via-hole conductor v100 penetrates the coating member 86 in the vertical direction, and connects the external electrode 84a and the circuit conductor layer 28f. More specifically, the upper end of the via hole conductor v100 is connected to the external electrode 84a, and the lower end of the via hole conductor v100 is connected to the circuit conductor layer 28f.
  • the via-hole conductor v100 penetrates the coating member 86 existing between the external electrode 84a and the lower surface of the package component 80 in the vertical direction, and does not penetrate the insulator sheet 22e in the vertical direction.
  • the via-hole conductor v102 penetrates the coating member 86 in the vertical direction, and connects the external electrode 84b and the circuit conductor layer 29f. More specifically, the upper end of the via hole conductor v102 is connected to the external electrode 84b, and the lower end of the via hole conductor v102 is connected to the circuit conductor layer 29f.
  • the via-hole conductor v102 penetrates the coating member 86 existing between the external electrode 84b and the lower surface of the package component 80 in the vertical direction, and does not penetrate the insulator sheet 22e in the vertical direction.
  • 13 to 16 are cross-sectional structure diagrams of the multilayer substrates 20b and 20g when they are manufactured.
  • the manufacturing method of the package component 80 of the multilayer substrate 20b is the same as the manufacturing method of the package component 80 of the multilayer substrate 20, description thereof will be omitted.
  • the conductive material is conducted to the through holes formed at positions where the via-hole conductors v1 to v3, v5 to v7, v11 to v13, and v15 to v17 are formed.
  • the steps up to the step of filling the conductive paste are the same as those steps in the method for manufacturing the multilayer substrate 20, and thus the description thereof is omitted.
  • the conductive paste is filled in the through holes formed at positions where the via-hole conductors v4 and v14 are formed, whereas in the manufacturing method of the multilayer substrate 20b, the via-hole conductors v5 and v15 are formed.
  • the conductive paste is filled in the through-hole formed at the position where it is formed.
  • the package component 80 is inserted into the through holes H1 to H3 from below. Furthermore, the insulating sheets 22a to 22d are subjected to heat treatment and pressure treatment (primary press).
  • a through-hole is formed by irradiating a laser beam at a position where the via-hole conductors v4, v14, v100, and v102 are formed. And as shown in FIG. 15, these through-holes are filled with the electrically conductive paste which has metals, such as copper, tin, and silver, as a main component.
  • the package component 80 is built in the insulator sheets 22a to 22g, and the conductive paste (an example of the connection conductor) to be the via-hole conductors v100 and v102 is provided in the circuit conductor layers 28f and 29f, respectively.
  • Insulator sheets 22e to 22g are laminated below the insulator sheet 22d so as to be connected to the substrate (an example of an eighth step). Further, the insulating sheets 22a to 22g are subjected to heat treatment and pressure treatment, and the insulating sheets 22a to 22g are thermocompression bonded (secondary press). In the secondary press, the insulator sheets 22a to 22g are softened and the conductive paste in the through holes is solidified.
  • the insulator sheets 22a to 22g are joined together, and the via-hole conductors v4 to v8, v14 to v18, v100, and v102 are formed (an example of the seventh step).
  • the multilayer substrate 20b is completed.
  • the multilayer substrate 20b configured as described above can also exhibit the same effects as the multilayer substrate 20.
  • the connection by the via-hole conductors v100 and v102 is stabilized.
  • the via-hole conductors v100 and v102 penetrate the coating member 86 in the vertical direction and do not penetrate the insulator sheet 22e in the vertical direction. That is, the via-hole conductors v100 and v102 connect the external electrodes 84a and 84b and the circuit conductor layers 28f and 29f only through the coating member 86. Thereby, it is not necessary to consider the difference between the deformation amount of the insulator sheet 22e and the deformation amount of the coating member 86 in the heat treatment and the pressure treatment as compared with the multilayer substrate 20. Therefore, the connection by the via-hole conductors v100 and v102 is stabilized.
  • FIG. 17 is a cross-sectional structure diagram of the multilayer substrate 20c.
  • through-hole conductors v5 ′, v15 ′, v100 ′, and v102 ′ are used instead of the via-hole conductors v5, v15, v100, and v102, and the front and back of the insulator sheet 22f are reversed. And the via hole conductors v9 and v19 are different from the multilayer substrate 20.
  • the multilayer substrate 20c will be described focusing on the difference.
  • the via-hole conductors v5, v15, v100, and v102 were formed by filling the through holes formed in the insulator sheet 22e and the coating member 86 with a conductive paste and heating the conductive paste.
  • the through-hole conductors v ⁇ b> 5 ′, v ⁇ b> 15 ′, v ⁇ b> 100 ′, and v ⁇ b> 102 ′ are formed by performing copper plating on the inner peripheral surfaces of the through holes formed in the insulator sheet 22 e and the coating member 86.
  • the via-hole conductors v9 and v19 penetrate the insulator sheet 22f in the vertical direction and are connected to the circuit conductor layers 28e and 29e.
  • the front and back of the insulator sheet 22f are reversed.
  • the through-hole conductors v5 ', v15', v100 ', and v102' are connected to the via-hole conductors v6, v16, v9, and v19, respectively.
  • the external electrode 84a and the circuit conductor layer 28e are connected via the through-hole conductor v100 'and the via-hole conductor v9.
  • the external electrode 84b and the circuit conductor layer 29e are connected through a through-hole conductor v102 'and a via-hole conductor v19.
  • FIGS. 18, 19A, and 19B are cross-sectional structural diagrams of the multilayer substrate 20c when it is manufactured.
  • the manufacturing method of the package component 80 of the multilayer substrate 20c is the same as the manufacturing method of the package component 80 of the multilayer substrate 20, description thereof will be omitted.
  • the steps from the step of preparing the insulator sheets 22a to 22g to the step of applying heat treatment and pressure treatment (primary press) to the insulator sheets 22a to 22e are as follows: Since these steps are the same as those in the method of manufacturing the multilayer substrate 20, the description thereof is omitted.
  • a through hole is formed by irradiating a laser beam at a position where through-hole conductors v5 ', v15', v100 ', and v102' are formed. Then, as shown in FIG. 19A, these through holes are plated with copper to form through-hole conductors v5 ', v15', v100 ', and v102'.
  • insulator sheets 22f and 22g are laminated under the insulator sheet 22e.
  • the insulator sheet 22f is arranged so that the main surface on which the circuit conductor layers 28e and 29e are provided faces downward.
  • the insulating sheets 22a to 22g are subjected to a heat treatment and a pressure treatment.
  • the multilayer substrate 20c is completed through the above steps.
  • the multilayer substrate 20c configured as described above can also exhibit the same effects as the multilayer substrate 20.
  • FIG. 20 is a cross-sectional structure diagram of the multilayer substrate 20d.
  • the multilayer substrate 20d is different from the multilayer substrate 20 in that it further includes a package component 80 '. Thus, two or more package parts may be incorporated in the multilayer substrate 20d.
  • the package component 80 ′ includes an electronic component 81 ′ (an example of a first electronic component) and 81 ′′ (an example of a second electronic component).
  • the electronic components 81 ′ and 81 ′′ are arranged side by side in the package component 80 ′.
  • the package component 80 ′ may include a plurality of electronic components.
  • the external electrodes 84a 'and 84b' of the electronic component 81 ' are provided only on the lower surface of the main body 82'.
  • the external electrodes 84 a ′′ and 84 b ′′ of the electronic component 81 ′′ ′ are provided only on the lower surface of the main body 82 ′′.
  • the external electrode may be provided only on the lower surface of the main body.
  • FIG. 21 is a sectional view of the multilayer substrate 20e.
  • the multilayer substrate 20e is different from the multilayer substrate 20 in that an insulator sheet 22h is laminated on the insulator sheet 22a and further provided with via-hole conductors v110 and v112.
  • the multilayer substrate 20e will be described with reference to the drawings with a focus on the following differences.
  • the base material 22 is configured by laminating insulator sheets 22h and 22a to 22g in this order from the upper side to the lower side.
  • the external electrodes 24a to 24d are provided on the surface of the insulator sheet 22h.
  • the circuit conductor layers 28g and 29g are provided on the surface of the insulator sheet 22a.
  • the via-hole conductor v0 penetrates the insulator sheet 22h in the vertical direction, and connects the external electrode 24a and the circuit conductor layer 28h.
  • the via-hole conductor v10 penetrates the insulator sheet 22h in the vertical direction, and connects the external electrode 24d and the circuit conductor layer 29g.
  • the via-hole conductor v110 penetrates the coating member 86 and the insulating sheet 22a in the vertical direction, and connects the external electrode 84a and the circuit conductor layer 28g. More specifically, the upper end of the via hole conductor v110 is connected to the circuit conductor layer 28g, and the lower end of the via hole conductor v110 is connected to the external electrode 84a.
  • the via-hole conductor v110 penetrates the coating member 86 existing between the external electrode 84a and the upper surface of the package component 80 in the vertical direction and penetrates the insulator sheet 22a in the vertical direction. Therefore, the via-hole conductor v110 passes through the upper surface of the package component 80.
  • the via-hole conductor v112 penetrates the coating member 86 and the insulating sheet 22a in the vertical direction, and connects the external electrode 84b and the circuit conductor layer 29g. More specifically, the upper end of the via hole conductor v112 is connected to the circuit conductor layer 29g, and the lower end of the via hole conductor v112 is connected to the external electrode 84b.
  • the via-hole conductor v112 penetrates the coating member 86 existing between the external electrode 84b and the upper surface of the package component 80 in the vertical direction and penetrates the insulator sheet 22a in the vertical direction. Therefore, the via-hole conductor v112 passes through the upper surface of the package component 80.
  • the multilayer substrate 20e configured as described above can also exhibit the same effects as the multilayer substrate 20.
  • the upper surface of the package component 80 is fixed by the via-hole conductors v110 and v112, and the lower surface of the package component 80 is fixed by the via-hole conductors v100 and v102.
  • the package component 80 is more effectively suppressed from being displaced in the base material 22 due to an external force during use.
  • disconnection between the package component 80 and the circuit conductor layers 28g, 29g, 28f, 29f is suppressed.
  • FIG. 22 is a sectional view of the multilayer substrate 20f.
  • the multilayer substrate 20f is different from the multilayer substrate 20e in that the package component 80 further includes an electronic component 81 '(an example of a second electronic component).
  • the multilayer substrate 20f will be described with reference to the drawings with a focus on the following differences.
  • the electronic component 81 (an example of the first electronic component) and the electronic component 81 ′ are arranged so as to overlap when viewed from above.
  • the coating member 86 includes electronic parts 81 and 81 '. Note that the coating member 86 does not necessarily contain the electronic components 81 and 81 ′, and may cover at least a part of the surface of the electronic components 81 and 81 ′.
  • the electronic component 81 ′ includes a main body 82 ′ and external electrodes 84 a ′ and 84 b ′.
  • the main body 82 ′ has a rectangular parallelepiped shape and is located on the upper side with respect to the main body 82.
  • the external electrodes 84a 'and 84b' are provided on the upper surface of the main body 82 ', and are arranged in this order from the left side to the right side.
  • the via-hole conductor v110 penetrates the coating member 86 and the insulating sheet 22a in the vertical direction, and connects the external electrode 84a 'and the circuit conductor layer 28g.
  • the via-hole conductor v112 passes through the coating member 86 and the insulating sheet 22a in the vertical direction, and connects the external electrode 84b 'and the circuit conductor layer 29g.
  • the multilayer substrate 20 f configured as described above can also exhibit the same effects as the multilayer substrate 20.
  • the package component 80 is prevented from rotating in the space Sp during the heat treatment and the pressure treatment. That is, since the positioning of the package component 80 on the base material 22 is performed with high accuracy, the positioning of the two electronic components 81 and 81 ′ is performed with high accuracy.
  • FIG. 23 is an external perspective view of the package component 80 of the multilayer board 20g.
  • FIG. 24A is a view of the package component 80 as viewed from above.
  • FIG. 24B is a cross-sectional structure diagram along AA in FIG. 24A.
  • 24C is a cross-sectional structure diagram taken along line BB in FIG. 24A.
  • the multilayer substrate 20g is different from the multilayer substrate 20b in that through-hole conductors v120 and v122 are provided in the package component 80. Since the cross-sectional structure diagram of the multilayer substrate 20g is substantially the same as the cross-sectional structure diagram of the multilayer substrate 20b, FIG. 12 is used. Hereinafter, the multilayer substrate 20g will be described focusing on the difference.
  • the through-hole conductor v120 penetrates the coating member 86 in the vertical direction, and connects the external electrode 84a and the circuit conductor layer 28f. More specifically, the upper end of the through-hole conductor v120 is connected to the external electrode 84a, and the lower end of the through-hole conductor v120 is connected to the circuit conductor layer 28f.
  • the through-hole conductor v120 penetrates the coating member 86 existing between the external electrode 84a and the lower surface of the package component 80 in the vertical direction and does not penetrate the insulator sheet 22e in the vertical direction.
  • the through-hole conductor v122 penetrates the coating member 86 in the vertical direction, and connects the external electrode 84b and the circuit conductor layer 29f. More specifically, the upper end of the through-hole conductor v122 is connected to the external electrode 84b, and the lower end of the through-hole conductor v122 is connected to the circuit conductor layer 29f.
  • the through-hole conductor v122 penetrates the coating member 86 existing between the external electrode 84b and the lower surface of the package component 80 in the vertical direction and does not penetrate the insulator sheet 22e in the vertical direction.
  • the through-hole conductors v120 and v122 as described above are formed by performing copper plating on the inner peripheral surface of the through hole provided in the coating member 86.
  • the through-hole conductors v120 and v122 are formed before the package component 80 is accommodated in the space Sp. That is, after the package component 80 is completed, a through hole is formed in the coating member 86 by a laser beam. And copper plating is given to the internal peripheral surface of a through-hole. Thereby, since the conductor which does not protrude from a through-hole can be formed, the unevenness
  • the multilayer substrate and the method of manufacturing the multilayer substrate according to the present invention are not limited to the method of manufacturing the multilayer substrates 20, 20a to 20g and the multilayer substrates 20, 20a to 20g, and can be changed within the scope of the gist.
  • the side surface of the package component 80 may not be parallel to the stacking direction.
  • a square frustum is cited.
  • the side surface of the package component 80 may not be a flat surface.
  • An example of the shape of the package component 80 whose side surface is not flat is a cylinder.
  • FIG. 25 is an external perspective view of the package component 80 whose upper and lower surfaces are constituted by the external electrodes 84 a and 84 b and the coating member 86. As shown in FIG. 25, the external electrodes 84 a and 84 b may be exposed from the coating member 86 by increasing the polishing amount of the resin layers 202 and 203 at the time of manufacturing the package component 80.
  • the external electrodes 84a and 84b and the via-hole conductors v100 and v102 can be connected or the external electrodes 84a and 84b and the circuit conductor layers 28f and 29f can be connected without forming a through hole in the coating member 86. .
  • the multilayer substrates 20 and 20a to 20g may be used without being mounted on the mother substrate 100.
  • the via-hole conductors v100 and v102 do not have to be provided.
  • the insulator sheet 22a is in contact with the upper surface (an example of the second plane) of the package component 80.
  • the via-hole conductors v110 and v112 (an example of a connection conductor) pass through the upper surface of the package component 80 and penetrate the coating member 86 and the insulator sheet 22a.
  • the insulator sheet 23 may be in contact with the upper surface (an example of the second plane) instead of the lower surface of the package component 80.
  • the insulator sheet 22h is further laminated on the insulator sheet 22a.
  • the insulator sheet 22a is in contact with the upper surface (an example of the second plane) of the package component 80.
  • circuit conductor layers 28g and 29g are provided on the surface of the insulator sheet 22a.
  • the multilayer substrate 20a includes via-hole conductors v110 and v112 instead of the via-hole conductors v100 and v102.
  • Via-hole conductors v110 and v112 (an example of a connection conductor) pass through the upper surface of the package component 80 and penetrate the coating member 86 and the insulator sheet 22a.
  • the via-hole conductor v110 connects the circuit conductor layer 28g and the external electrode 84a
  • the via-hole conductor v112 connects the circuit conductor layer 29g and the external electrode 84b.
  • the via-hole conductors v110, v112 are provided instead of the via-hole conductors v100, v102, similarly to the multilayer substrates 20a, 20e. Also good.
  • the insulator sheet 22a is in contact with the upper surface (an example of the second plane) of the package component 80.
  • the via-hole conductors v110 and v112 pass through the upper surface of the package component 80 and penetrate the coating member 86 and the insulator sheet 22a.
  • the via-hole conductors v110 and v112 are directly connected to the circuit conductor layers 28e and 29e, respectively.
  • the circuit conductor layers 28e and 29e are connected via via-hole conductors different from the via-hole conductors v110 and v112. It may be connected directly to. That is, the via-hole conductors v110 and v112 only have to electrically connect the external electrodes 84a and 84b and the circuit conductor layers 28e and 29e, respectively.
  • the present invention is useful for a multilayer substrate and a method for producing the multilayer substrate, and is particularly excellent in that the flatness of the main surface of the base material can be improved.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

To provide a multilayer substrate whereby planarity of a main surface of a base material can be improved, and a method for manufacturing the multilayer substrate. A multilayer substrate relating to the present invention is characterized by being provided with: a base material configured by laminating, in the lamination direction, a plurality of insulating material layers that are configured from a material containing a first resin, i.e., a thermoplastic resin; and a package component embedded in the base material, said package component having a first flat surface and a second flat surface, which are positioned at both ends in the lamination direction, and which are substantially perpendicular to the lamination direction. The multilayer substrate is also characterized in that: the package component includes a first electronic component, and a coating member, which is configured from a material containing a second resin, and which is covering at least a part of the surface of the first electronic component; at the softening temperature of the first resin, the Young's modulus of the second resin is higher than the Young's modulus of the first resin; and at least a part of the first flat surface and at least a part of the second flat surface are configured from the coating member.

Description

多層基板及び多層基板の製造方法Multilayer substrate and method for manufacturing multilayer substrate
　本発明は、多層基板及び多層基板の製造方法に関し、より特定的には、熱可塑性樹脂を材料とする絶縁体層が積層された基材を備える多層基板及び多層基板の製造方法に関する。 The present invention relates to a multilayer substrate and a method for manufacturing the multilayer substrate, and more particularly to a multilayer substrate including a base material on which an insulating layer made of a thermoplastic resin is laminated, and a method for manufacturing the multilayer substrate.
　従来の多層基板に関する発明としては、例えば、特許文献１に記載の樹脂多層基板が知られている。図２６は、樹脂多層基板５００の製造時の断面構造図である。 As an invention related to a conventional multilayer substrate, for example, a resin multilayer substrate described in Patent Document 1 is known. FIG. 26 is a cross-sectional structure diagram when the resin multilayer substrate 500 is manufactured.
　樹脂多層基板５００は、樹脂シート５０２ａ～５０２ｄ及び部品５０３ａ，５０３ｂを備えている。樹脂シート５０２ｂ，５０２ｃにはそれぞれ、貫通孔５１４ａ，５１４ｂが設けられている。このような樹脂シート５０２ｂ～５０２ｄが積層されることにより、キャビティ５０５ａ，５０５ｂが形成されている。そして、部品５０３ａ，５０３ｂがそれぞれキャビティ５０５ａ，５０５ｂ内に収容された後に、樹脂シート５０２ｂ上に樹脂シート５０２ａが積層される。これにより、部品５０３ａ，５０３ｂを内蔵した樹脂多層基板５００が得られる。 The resin multilayer substrate 500 includes resin sheets 502a to 502d and components 503a and 503b. Through holes 514a and 514b are provided in the resin sheets 502b and 502c, respectively. Cavities 505a and 505b are formed by laminating such resin sheets 502b to 502d. Then, after the components 503a and 503b are accommodated in the cavities 505a and 505b, respectively, the resin sheet 502a is laminated on the resin sheet 502b. Thereby, the resin multilayer substrate 500 incorporating the components 503a and 503b is obtained.
国際公開第２０１４／２０３６０３号公報International Publication No. 2014/203603
　ところで、特許文献１に記載の樹脂多層基板５００では、上面及び下面の平坦性を確保することが困難な場合がある。より詳細には、部品５０３ａ，５０３ｂの上面及び下面には図示しない外部電極が設けられている。そのため、部品５０３ａ，５０３ｂの上面及び下面には凹凸が存在する。このような凹凸が存在すると、部品５０３ａ，５０３ｂの上面及び下面と樹脂シート５０２ａ，５０２ｄとの間に隙間が形成される。そして、熱圧着工程において、部品５０３ａ，５０３ｂ近傍の樹脂シート５０２ａ，５０２ｄは、軟化・流動して隙間に流れ込む。その結果、樹脂多層基板５００の上面及び下面において、部品５０３ａ，５０３ｂの直上及び直下並びにその近傍に凹凸が形成されることがある。 Incidentally, in the resin multilayer substrate 500 described in Patent Document 1, it may be difficult to ensure the flatness of the upper surface and the lower surface. More specifically, external electrodes (not shown) are provided on the upper and lower surfaces of the components 503a and 503b. Therefore, there are irregularities on the upper and lower surfaces of the components 503a and 503b. When such irregularities exist, gaps are formed between the upper and lower surfaces of the components 503a and 503b and the resin sheets 502a and 502d. In the thermocompression bonding process, the resin sheets 502a and 502d in the vicinity of the components 503a and 503b soften and flow and flow into the gap. As a result, irregularities may be formed on the upper and lower surfaces of the resin multilayer substrate 500 directly above and below the components 503a and 503b and in the vicinity thereof.
　そこで、本発明の目的は、基材の主面の平坦性を向上させることができる多層基板及び多層基板の製造方法を提供することである。 Therefore, an object of the present invention is to provide a multilayer substrate and a method for manufacturing the multilayer substrate that can improve the flatness of the main surface of the base material.
　本発明の一形態に係る多層基板は、熱可塑性樹脂である第１の樹脂を含む材料により構成されている複数の絶縁体層が積層方向に積層されて構成されている基材と、前記基材に内蔵されているパッケージ部品であって、前記積層方向の両端に位置し、かつ、該積層方向に実質的に垂直な第１の平面及び第２の平面を有するパッケージ部品と、を備えており、前記パッケージ部品は、第１の電子部品と、第２の樹脂を含む材料により構成され、かつ、前記第１の電子部品の表面の少なくとも一部を覆っているコーティング部材と、を含んでおり、前記第１の樹脂の軟化点温度において、前記第２の樹脂のヤング率は、前記第１の樹脂のヤング率よりも大きく、前記第１の平面の少なくとも一部及び前記第２の平面の少なくとも一部は、前記コーティング部材により構成されていること、を特徴とする。 A multilayer substrate according to an embodiment of the present invention includes a base material formed by laminating a plurality of insulator layers made of a material including a first resin, which is a thermoplastic resin, in the stacking direction, and the base A package component embedded in a material, the package component having first and second planes positioned at both ends in the stacking direction and substantially perpendicular to the stacking direction. The package component includes a first electronic component and a coating member made of a material containing a second resin and covering at least a part of the surface of the first electronic component. The Young's modulus of the second resin is larger than the Young's modulus of the first resin at the softening point temperature of the first resin, and at least a part of the first plane and the second plane. At least a portion of It is constituted by coating member, and wherein.
　本発明の一形態に係る多層基板の製造方法は、第１の電子部品の表面の少なくとも一部をコーティング部材により覆うことにより、積層方向の両端に位置し、かつ、該積層方向に実質的に垂直な第１の平面及び第２の平面を有するパッケージ部品を形成する第１の工程と、前記パッケージ部品を内蔵するように複数の絶縁体層を前記積層方向に積層する第２の工程と、前記複数の絶縁体層に対して加熱処理及び加圧処理を施して基材を形成する第３の工程と、を備えており、前記複数の絶縁体層は、熱可塑性樹脂である第１の樹脂を含む材料により構成されており、前記コーティング部材は、第２の樹脂を含む材料により構成されており、前記加熱処理の温度において、前記第２の樹脂のヤング率は、前記第１の樹脂のヤング率よりも大きいこと、を特徴とする。 In the method for manufacturing a multilayer substrate according to one aspect of the present invention, at least a part of the surface of the first electronic component is covered with a coating member, so that it is positioned at both ends in the stacking direction and substantially in the stacking direction. A first step of forming a package component having a vertical first plane and a second plane; a second step of stacking a plurality of insulator layers in the stacking direction so as to incorporate the package component; A third step of forming a base material by subjecting the plurality of insulator layers to a heat treatment and a pressure treatment, wherein the plurality of insulator layers are made of a thermoplastic resin. The coating member is made of a material containing a second resin, and the Young's modulus of the second resin is the first resin at the temperature of the heat treatment. Greater than Young's modulus It features a.
　本発明によれば、基材の主面の平坦性を向上させることができる。 According to the present invention, the flatness of the main surface of the substrate can be improved.
図１は、本発明の一実施形態に係る多層基板２０を備えた電子機器１０の断面構造図である。FIG. 1 is a cross-sectional structure diagram of an electronic device 10 including a multilayer substrate 20 according to an embodiment of the present invention. 図２Ａは、多層基板２０の断面構造図である。FIG. 2A is a sectional view of the multilayer substrate 20. 図２Ｂは、多層基板２０の分解図である。FIG. 2B is an exploded view of the multilayer substrate 20. 図３Ａは、電子部品８１を上側から見た図である。FIG. 3A is a view of the electronic component 81 as viewed from above. 図３Ｂは、電子部品８１を前側から見た図である。FIG. 3B is a view of the electronic component 81 as viewed from the front side. 図３Ｃは、パッケージ部品８０を上側から見た図である。FIG. 3C is a view of the package component 80 as viewed from above. 図３Ｄは、パッケージ部品８０を前側から見た図である。FIG. 3D is a view of the package component 80 as viewed from the front side. 図４Ａは、パッケージ部品８０の製造時の透視図である。FIG. 4A is a perspective view when the package component 80 is manufactured. 図４Ｂは、パッケージ部品８０の製造時の透視図である。FIG. 4B is a perspective view when the package component 80 is manufactured. 図４Ｃは、パッケージ部品８０の製造時の透視図である。FIG. 4C is a perspective view when the package component 80 is manufactured. 図４Ｄは、パッケージ部品８０の製造時の透視図である。FIG. 4D is a perspective view when the package component 80 is manufactured. 図５Ａは、パッケージ部品８０の製造時の透視図である。FIG. 5A is a perspective view when the package component 80 is manufactured. 図５Ｂは、パッケージ部品８０の製造時の透視図である。FIG. 5B is a perspective view when the package component 80 is manufactured. 図５Ｃは、パッケージ部品８０の製造時の透視図である。FIG. 5C is a perspective view when the package component 80 is manufactured. 図５Ｄは、パッケージ部品８０の製造時の透視図である。FIG. 5D is a perspective view when the package component 80 is manufactured. 図５Ｅは、多層基板２０の製造時の断面構造図である。FIG. 5E is a cross-sectional structure diagram when the multilayer substrate 20 is manufactured. 図６Ａは、多層基板２０の製造時の断面構造図である。FIG. 6A is a cross-sectional structure diagram when the multilayer substrate 20 is manufactured. 図６Ｂは、多層基板２０の製造時の断面構造図である。FIG. 6B is a cross-sectional structure diagram when the multilayer substrate 20 is manufactured. 図７は、多層基板２０の製造時の断面構造図である。FIG. 7 is a cross-sectional structure diagram when the multilayer substrate 20 is manufactured. 図８は、多層基板２０ａの断面構造図である。FIG. 8 is a cross-sectional structure diagram of the multilayer substrate 20a. 図９Ａは、パッケージ部品８０及び絶縁体シート２３の製造時の透視図である。FIG. 9A is a perspective view at the time of manufacturing the package component 80 and the insulator sheet 23. 図９Ｂは、パッケージ部品８０及び絶縁体シート２３の製造時の透視図である。FIG. 9B is a perspective view at the time of manufacturing the package component 80 and the insulator sheet 23. 図９Ｃは、パッケージ部品８０及び絶縁体シート２３の製造時の透視図である。FIG. 9C is a perspective view at the time of manufacturing the package component 80 and the insulator sheet 23. 図９Ｄは、パッケージ部品８０及び絶縁体シート２３の製造時の透視図である。FIG. 9D is a perspective view at the time of manufacturing the package component 80 and the insulator sheet 23. 図１０は、多層基板２０ａの製造時の断面構造図である。FIG. 10 is a cross-sectional structure diagram when the multilayer substrate 20a is manufactured. 図１１は、多層基板２０ａの製造時の断面構造図である。FIG. 11 is a cross-sectional structure diagram when the multilayer substrate 20a is manufactured. 図１２は、多層基板２０ｂ，２０ｇの断面構造図である。FIG. 12 is a cross-sectional structure diagram of the multilayer substrates 20b and 20g. 図１３は、多層基板２０ｂ，２０ｇの製造時の断面構造図である。FIG. 13 is a cross-sectional structure diagram when the multilayer substrates 20b and 20g are manufactured. 図１４は、多層基板２０ｂ，２０ｇの製造時の断面構造図である。FIG. 14 is a cross-sectional structure diagram when the multilayer substrates 20b and 20g are manufactured. 図１５は、多層基板２０ｂ，２０ｇの製造時の断面構造図である。FIG. 15 is a cross-sectional structure diagram of the multilayer substrates 20b and 20g during manufacturing. 図１６は、多層基板２０ｂ，２０ｇの製造時の断面構造図である。FIG. 16 is a cross-sectional structure diagram of the multilayer substrates 20b and 20g during manufacturing. 図１７は、多層基板２０ｃの断面構造図である。FIG. 17 is a cross-sectional structure diagram of the multilayer substrate 20c. 図１８は、多層基板２０ｃの製造時の断面構造図である。FIG. 18 is a cross-sectional structure diagram when the multilayer substrate 20c is manufactured. 図１９Ａは、多層基板２０ｃの製造時の断面構造図である。FIG. 19A is a cross-sectional structure diagram when the multilayer substrate 20c is manufactured. 図１９Ｂは、多層基板２０ｃの製造時の断面構造図である。FIG. 19B is a cross-sectional structure diagram when the multilayer substrate 20c is manufactured. 図２０は、多層基板２０ｄの断面構造図である。FIG. 20 is a cross-sectional structure diagram of the multilayer substrate 20d. 図２１は、多層基板２０ｅの断面構造図である。FIG. 21 is a sectional view of the multilayer substrate 20e. 図２２は、多層基板２０ｆの断面構造図である。FIG. 22 is a sectional view of the multilayer substrate 20f. 図２３は、多層基板２０ｇのパッケージ部品８０の外観斜視図である。FIG. 23 is an external perspective view of the package component 80 of the multilayer board 20g. 図２４Ａは、パッケージ部品８０を上側から見た図である。FIG. 24A is a view of the package component 80 as viewed from above. 図２４Ｂは、図２４ＡのＡ－Ａにおける断面構造図である。FIG. 24B is a cross-sectional structure diagram along AA in FIG. 24A. 図２４Ｃは、図２４ＡのＢ－Ｂにおける断面構造図である。24C is a cross-sectional structure diagram taken along line BB in FIG. 24A. 図２５は、上面及び下面が外部電極８４ａ，８４ｂ及びコーティング部材８６により構成されているパッケージ部品８０の外観斜視図である。FIG. 25 is an external perspective view of the package component 80 whose upper and lower surfaces are constituted by the external electrodes 84 a and 84 b and the coating member 86. 図２６は、樹脂多層基板５００の製造時の断面構造図である。FIG. 26 is a cross-sectional structure diagram when the resin multilayer substrate 500 is manufactured.
（実施形態）
＜多層基板及び電子機器の構成＞
　以下に、本発明の一実施形態に係る多層基板及び電子機器の構成について図面を参照しながら説明する。図１は、本発明の一実施形態に係る多層基板２０を備えた電子機器１０の断面構造図である。図２Ａは、多層基板２０の断面構造図である。図２Ｂは、多層基板２０の分解図である。図３Ａは、電子部品８１を上側から見た図である。図３Ｂは、電子部品８１を前側から見た図である。図３Ｃは、パッケージ部品８０を上側から見た図である。図３Ｄは、パッケージ部品８０を前側から見た図である。図３Ｃ及び図３Ｄでは、ビアホール導体ｖ１００，ｖ１０２は省略されている。以下では、多層基板２０の積層方向を上下方向と定義する。図１、図２Ａ及び図２Ｂにおける紙面垂直方向を前後方向（第２の直交方向の一例）と定義し、図１、図２Ａ及び図２Ｂにおける紙面左右方向を左右方向（第１の直交方向の一例）と定義する。上下方向、左右方向及び前後方向は互いに直交している。 (Embodiment)
<Configuration of multilayer substrate and electronic device>
Hereinafter, configurations of a multilayer substrate and an electronic apparatus according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional structure diagram of an electronic device 10 including a multilayer substrate 20 according to an embodiment of the present invention. FIG. 2A is a sectional view of the multilayer substrate 20. FIG. 2B is an exploded view of the multilayer substrate 20. FIG. 3A is a view of the electronic component 81 as viewed from above. FIG. 3B is a view of the electronic component 81 as viewed from the front side. FIG. 3C is a view of the package component 80 as viewed from above. FIG. 3D is a view of the package component 80 as viewed from the front side. In FIG. 3C and FIG. 3D, the via-hole conductors v100 and v102 are omitted. Hereinafter, the stacking direction of the multilayer substrate 20 is defined as the vertical direction. 1, 2A, and 2B is defined as the front-rear direction (an example of the second orthogonal direction), and the left-right direction of the paper in FIGS. Example). The up-down direction, the left-right direction, and the front-rear direction are orthogonal to each other.
　電子機器１０は、例えば、携帯電話やパーソナルコンピュータ、ゲーム機、ウェラブル端末等である。図１では、電子機器１０内に設けられているモジュールやマザー基板のみを図示し、電子機器１０の筺体やその他の構成については省略した。電子機器１０は、図１に示すように、多層基板２０、電子部品６０，７０及びマザー基板１００を備えている。 The electronic device 10 is, for example, a mobile phone, a personal computer, a game machine, a wearable terminal, or the like. In FIG. 1, only modules and mother boards provided in the electronic device 10 are illustrated, and the casing of the electronic device 10 and other configurations are omitted. As shown in FIG. 1, the electronic device 10 includes a multilayer substrate 20, electronic components 60 and 70, and a mother substrate 100.
　まず、多層基板２０について説明する。多層基板２０は、上側から見たときに長方形状をなす板状の樹脂基板である。多層基板２０を上側から見たときに、長辺は左右方向に延在し、短辺は前後方向に延在している。多層基板２０は、図２に示すように、基材２２、外部電極２４ａ～２４ｄ，２６ａ，２６ｂ、回路導体層２８ａ～２８ｅ，２９ａ～２９ｅ、ビアホール導体ｖ１～ｖ７，ｖ１１～ｖ１７，ｖ１００，ｖ１０２、パッケージ部品８０を備えている。なお、外部電極は、外部電極２４ａ～２４ｄ，２６ａ，２６ｂ以外にも設けられているが、外部電極２４ａ～２４ｄ，２６ａ，２６ｂ以外の外部電極については図１及び図２では省略した。同様に、回路導体層は、回路導体層２８ａ～２８ｅ，２９ａ～２９ｅ以外にも設けられているが、回路導体層２８ａ～２８ｅ，２９ａ～２９ｅ以外の回路導体層については図１及び図２では省略した。同様に、ビアホール導体は、ビアホール導体ｖ１～ｖ７，ｖ１１～ｖ１７以外にも設けられているが、ビアホール導体ｖ１～ｖ７，ｖ１１～ｖ１７以外のビアホール導体については図１及び図２Ａでは省略した。 First, the multilayer substrate 20 will be described. The multilayer substrate 20 is a plate-shaped resin substrate having a rectangular shape when viewed from above. When the multilayer substrate 20 is viewed from above, the long side extends in the left-right direction and the short side extends in the front-rear direction. As shown in FIG. 2, the multilayer substrate 20 includes a base material 22, external electrodes 24a to 24d, 26a and 26b, circuit conductor layers 28a to 28e, 29a to 29e, via-hole conductors v1 to v7, v11 to v17, v100, and v102. The package part 80 is provided. The external electrodes are provided in addition to the external electrodes 24a to 24d, 26a, and 26b, but the external electrodes other than the external electrodes 24a to 24d, 26a, and 26b are omitted in FIGS. Similarly, the circuit conductor layers are provided in addition to the circuit conductor layers 28a to 28e and 29a to 29e, but the circuit conductor layers other than the circuit conductor layers 28a to 28e and 29a to 29e are shown in FIGS. Omitted. Similarly, via-hole conductors are provided in addition to the via-hole conductors v1 to v7 and v11 to v17, but the via-hole conductors other than the via-hole conductors v1 to v7 and v11 to v17 are omitted in FIGS. 1 and 2A.
　基材２２は、図２Ａに示すように、上側から見たときに、長方形状をなす可撓性の板状部材である。基材２２は、絶縁体シート２２ａ～２２ｇ（複数の絶縁体層の一例）が上側から下側へとこの順に積層されて構成されている積層体である。基材２２は、２つの主面を有している。以下では、基材２２の上側の主面を表面と称し、基材２２の下側の主面を裏面と称す。基材２２の裏面は、多層基板２０の実装時にマザー基板１００に対向する実装面である。 The base material 22 is a flexible plate-like member having a rectangular shape when viewed from above, as shown in FIG. 2A. The base material 22 is a laminate in which insulator sheets 22a to 22g (an example of a plurality of insulator layers) are laminated in this order from the upper side to the lower side. The base material 22 has two main surfaces. Hereinafter, the upper main surface of the base material 22 is referred to as a front surface, and the lower main surface of the base material 22 is referred to as a back surface. The back surface of the base material 22 is a mounting surface that faces the mother substrate 100 when the multilayer substrate 20 is mounted.
　絶縁体シート２２ａ～２２ｇは、上側から見たときに、長方形状をなしており、基材２２と同じ形状をなしている。絶縁体シート２２ａ～２２ｇは、ポリイミドや液晶ポリマ等の可撓性を有する熱可塑性樹脂（第１の樹脂の一例）を含む材料により構成されている。以下では、絶縁体シート２２ａ～２２ｇの上側の主面を表面と称し、絶縁体シート２２ａ～２２ｇの下側の主面を裏面と称す。 The insulator sheets 22a to 22g have a rectangular shape when viewed from above, and have the same shape as the base material 22. The insulator sheets 22a to 22g are made of a material including a flexible thermoplastic resin (an example of a first resin) such as polyimide or liquid crystal polymer. Hereinafter, the upper main surface of the insulator sheets 22a to 22g is referred to as a front surface, and the lower main surface of the insulator sheets 22a to 22g is referred to as a back surface.
　また、図２Ｂに示すように、絶縁体シート２２ｂ～２２ｄの中央（対角線の交点付近）にはそれぞれ、上側から見たときに、長方形状をなす貫通孔Ｈ１～Ｈ３が設けられている。貫通孔Ｈ１～Ｈ３はそれぞれ、絶縁体シート２２ｂ～２２ｄの表面と裏面とを繋ぐように形成されている。また、貫通孔Ｈ１～Ｈ３の外縁は、上側から見たときに、互いに一致するように重なり合っている。よって、貫通孔Ｈ１～Ｈ３は１つに繋がっている。 Further, as shown in FIG. 2B, through holes H1 to H3 having a rectangular shape when viewed from above are provided at the centers (near the intersections of the diagonal lines) of the insulator sheets 22b to 22d, respectively. The through holes H1 to H3 are formed so as to connect the front and back surfaces of the insulator sheets 22b to 22d, respectively. Further, the outer edges of the through holes H1 to H3 overlap each other when viewed from above. Therefore, the through holes H1 to H3 are connected to one.
　また、貫通孔Ｈ１の上側の開口は、絶縁体シート２２ａによって塞がれている。貫通孔Ｈ３の下側の開口は、絶縁体シート２２ｅによって塞がれている。これにより、基材２２内には、貫通孔Ｈ１～Ｈ３が繋がった直方体状の空間Ｓｐが形成されている。 Further, the upper opening of the through hole H1 is closed by the insulator sheet 22a. The opening on the lower side of the through hole H3 is blocked by the insulator sheet 22e. Thus, a rectangular parallelepiped space Sp in which the through holes H1 to H3 are connected is formed in the base material 22.
　パッケージ部品８０は、図１、図２Ａ及び図２Ｂに示すように、基材２２に内蔵されており、直方体状をなしている。以下では、パッケージ部品８０において、上側（積層方向の一方側の一例）に位置する面を上面（第１の平面の一例）と呼び、下側（積層方向の他方側の一例）に位置する面を下面（第２の平面の一例）と呼び、前側に位置する面を前面と呼び、後側に位置する面を後面と呼び、右側に位置する面を右面と呼び、左側に位置する面を左面と呼ぶ。上面、下面、前面、後面、右面及び左面は、実質的に平面である。上面及び下面は、上下方向に実質的に垂直な平面である。また、前面、後面、右面及び左面は、上面及び下面に対して実質的に垂直であり、上下方向に実質的に平行な平面である。また、前面、後面、右面及び左面を総称して側面と呼ぶこともある。本実施形態では、上面、下面、前面、後面、右面及び左面の接合部分に対して面取りが施されていないが、該接合部分に対して面取りが施されていてもよい。なお、実質的に平面であること、及び、実質的に平行又は垂直であることは、製造ばらつきによって、僅かに平面からずれることや僅かに平行又は垂直からずれることを許容する意味である。 As shown in FIGS. 1, 2A, and 2B, the package component 80 is built in the base material 22 and has a rectangular parallelepiped shape. Hereinafter, in the package component 80, a surface positioned on the upper side (an example of one side in the stacking direction) is referred to as an upper surface (an example of the first plane), and a surface positioned on the lower side (an example of the other side in the stacking direction) Is called the lower surface (an example of the second plane), the front surface is called the front surface, the rear surface is called the rear surface, the right surface is called the right surface, and the left surface is Called the left side. The upper surface, the lower surface, the front surface, the rear surface, the right surface, and the left surface are substantially flat. The upper surface and the lower surface are planes that are substantially perpendicular to the vertical direction. Further, the front surface, the rear surface, the right surface, and the left surface are planes that are substantially perpendicular to the upper surface and the lower surface and substantially parallel to the vertical direction. In addition, the front surface, the rear surface, the right surface, and the left surface may be collectively referred to as a side surface. In the present embodiment, chamfering is not performed on the joint portions of the upper surface, the lower surface, the front surface, the rear surface, the right surface, and the left surface, but the joint portions may be chamfered. It should be noted that being substantially flat and being substantially parallel or vertical means that it is allowed to slightly deviate from the plane or slightly deviate from parallel or vertical due to manufacturing variations.
　パッケージ部品８０は、空間Ｓｐに収容されている。これにより、パッケージ部品８０は、絶縁体シート２２ｂ～２２ｄを上下方向に貫通している。更に、絶縁体シート２２ａの裏面は、パッケージ部品８０の上面に接触しており、絶縁体シート２２ｅ（第１の絶縁体層の一例）の表面は、パッケージ部品８０の下面に接触している。また、貫通孔Ｈ１～Ｈ３の内周面は、パッケージ部品８０の側面に接触している。また、絶縁体シート２２ａ～２２ｅは、パッケージ部品８０に固着している。より詳細には、後述するように、絶縁体シート２２ａ～２２ｇは、基材２２の熱圧着工程において、軟化した後に固化している。そのため、絶縁体シート２２ａ～２２ｇが軟化する際に、空間Ｓｐの内周面とパッケージ部品５０の上面、下面及び側面（以下、表面とも呼ぶ）との間の隙間に絶縁体シート２２ａ～２２ｅが流れ込んで、該隙間が絶縁体シート２２ａ～２２ｅにより埋められる。更に、絶縁体シート２２ａ～２２ｅが固化する際に、空間Ｓｐの内周面とパッケージ部品５０表面とが固着して容易に離れなくなる。 The package component 80 is accommodated in the space Sp. Thereby, the package component 80 penetrates the insulator sheets 22b to 22d in the vertical direction. Furthermore, the back surface of the insulator sheet 22 a is in contact with the upper surface of the package component 80, and the surface of the insulator sheet 22 e (an example of the first insulator layer) is in contact with the lower surface of the package component 80. Further, the inner peripheral surfaces of the through holes H 1 to H 3 are in contact with the side surfaces of the package component 80. Further, the insulator sheets 22a to 22e are fixed to the package component 80. More specifically, as will be described later, the insulator sheets 22a to 22g are solidified after being softened in the thermocompression bonding process of the base material 22. Therefore, when the insulating sheets 22a to 22g are softened, the insulating sheets 22a to 22e are formed in the gaps between the inner peripheral surface of the space Sp and the upper, lower, and side surfaces (hereinafter also referred to as surfaces) of the package component 50. The gaps are filled, and the gaps are filled with the insulator sheets 22a to 22e. Further, when the insulator sheets 22a to 22e are solidified, the inner peripheral surface of the space Sp and the surface of the package component 50 are fixed and are not easily separated.
　パッケージ部品８０は、図２Ａ及び図３Ａないし図３Ｄに示すように、電子部品８１（第１の電子部品の一例）及びコーティング部材８６を含んでいる。電子部品８１は、例えば、コンデンサやインダクタ等のチップ型の電子部品であり、本体８２（第１の本体の一例）及び外部電極８４，８４ｂを有している。 The package component 80 includes an electronic component 81 (an example of a first electronic component) and a coating member 86, as shown in FIGS. 2A and 3A to 3D. The electronic component 81 is, for example, a chip-type electronic component such as a capacitor or an inductor, and includes a main body 82 (an example of a first main body) and external electrodes 84 and 84b.
　本体８２は、セラミック等の材料により作製された直方体状をなす部材であり、内部にコンデンサやインダクタ等の回路素子（図示せず）を含んでいる。外部電極８４ａ（第１の外部電極の一例）は、本体８２の表面に設けられており、本体８２において上面又は下面のいずれか一方に設けられている。本実施形態では、外部電極８４ａは、本体８２の左面（第１の直交方向の一方側の面の一例）の全体を覆うと共に、左面に隣接する領域であって、上面（積層方向の一方側の面の一例）、下面（積層方向の他方側の面の一例）、前面（第２の直交方向の一方側の面の一例）及び後面（第２の直交方向の他方側の面の一例）の一部の領域を覆っている。外部電極８４ｂは、本体８２において上面又は下面のいずれか一方に設けられている。本実施形態では、外部電極８４ｂは、本体８２の表面に設けられており、具体的には、本体８２の右面の全体を覆うと共に、右面に隣接する領域であって、上面、下面、前面及び後面の一部の領域を覆っている。これにより、電子部品８１の上面、下面、前面及び後面には、凹凸が形成されている。外部電極８４ａ，８４ｂは、例えば、銀等を主成分とする導電性ペーストが塗布されて形成された下地電極上にニッケルメッキ及び錫メッキが施されることにより形成されている。 The main body 82 is a rectangular parallelepiped member made of a material such as ceramic, and includes circuit elements (not shown) such as capacitors and inductors therein. The external electrode 84 a (an example of the first external electrode) is provided on the surface of the main body 82, and is provided on either the upper surface or the lower surface of the main body 82. In the present embodiment, the external electrode 84a covers the entire left surface of the main body 82 (an example of a surface on one side in the first orthogonal direction) and is an area adjacent to the left surface, and has an upper surface (one side in the stacking direction). Example of surface), lower surface (example of surface on the other side in the stacking direction), front surface (example of surface on one side in the second orthogonal direction) and rear surface (example of surface on the other side in the second orthogonal direction) Covers some areas. The external electrode 84 b is provided on either the upper surface or the lower surface of the main body 82. In the present embodiment, the external electrode 84b is provided on the surface of the main body 82. Specifically, the external electrode 84b covers the entire right surface of the main body 82 and is adjacent to the right surface, and includes an upper surface, a lower surface, a front surface, and a front surface. It covers a part of the rear surface. Thereby, unevenness is formed on the upper surface, the lower surface, the front surface, and the rear surface of the electronic component 81. The external electrodes 84a and 84b are formed, for example, by performing nickel plating and tin plating on a base electrode formed by applying a conductive paste mainly composed of silver or the like.
　コーティング部材８６は、エポキシ樹脂等の熱硬化性樹脂（第２の樹脂の一例）を含む材料により構成され、かつ、電子部品８１の表面の少なくとも一部を覆っている。これにより、パッケージ部品８０の上面の少なくとも一部及びパッケージ部品８０の下面の少なくとも一部はコーティング部材８６により構成されている。本実施形態では、コーティング部材８６は、電子部品８１の表面の全体を覆っている。そのため、電子部品８１は、コーティング部材８６から露出していない。そして、パッケージ部品８０の上面の全体及びパッケージ部品８０の下面の全体はコーティング部材８６により構成されている。ただし、コーティング部材８６の下面（すなわち、パッケージ部品８０の下面）には、後述するビアホール導体ｖ１００，ｖ１０２のための貫通孔が設けられている。そのため、コーティング部材８６の下面（すなわち、パッケージ部品８０の下面）は貫通孔において窪んでいる。ただし、この貫通孔は小さいので、コーティング部材８６の下面（すなわち、パッケージ部品８０の下面）を便宜上平面と解釈する。 The coating member 86 is made of a material containing a thermosetting resin (an example of a second resin) such as an epoxy resin, and covers at least a part of the surface of the electronic component 81. Thereby, at least a part of the upper surface of the package component 80 and at least a part of the lower surface of the package component 80 are constituted by the coating member 86. In the present embodiment, the coating member 86 covers the entire surface of the electronic component 81. Therefore, the electronic component 81 is not exposed from the coating member 86. The entire upper surface of the package component 80 and the entire lower surface of the package component 80 are constituted by a coating member 86. However, on the lower surface of the coating member 86 (that is, the lower surface of the package component 80), through holes for via-hole conductors v100 and v102 described later are provided. Therefore, the lower surface of the coating member 86 (that is, the lower surface of the package component 80) is recessed in the through hole. However, since the through hole is small, the lower surface of the coating member 86 (that is, the lower surface of the package component 80) is interpreted as a plane for convenience.
　また、絶縁体シート２２ａ～２２ｇに用いられるポリイミドや液晶ポリマ等の熱可塑性樹脂の軟化点温度において、コーティング部材８６に用いられるエポキシ樹脂等の熱硬化性樹脂のヤング率は、絶縁体シート２２ａ～２２ｇに用いられるポリイミドや液晶ポリマ等の熱可塑性樹脂のヤング率よりも大きい。軟化点とは、樹脂の温度が上昇し変形を始めるときの温度である。ポリイミドの軟化点は例えば１２０℃であり、液晶ポリマの軟化点は例えば１５０℃である。本願では、軟化点とはＪＩＳ　Ｋ７２０６に記載の方法に準じて測定したものを意味する。 In addition, the Young's modulus of a thermosetting resin such as an epoxy resin used for the coating member 86 at the softening point temperature of a thermoplastic resin such as polyimide or liquid crystal polymer used for the insulator sheets 22a to 22g is as follows. It is larger than the Young's modulus of thermoplastic resins such as polyimide and liquid crystal polymer used for 22g. The softening point is the temperature at which the temperature of the resin rises and begins to deform. The softening point of polyimide is 120 ° C., for example, and the softening point of liquid crystal polymer is 150 ° C., for example. In the present application, the softening point means a value measured according to the method described in JIS K7206.
　また、コーティング部材８６に用いられるエポキシ樹脂等の熱硬化性樹脂の線膨張係数は、本体８２の材料（セラミック）の線膨張係数以上であり、かつ、絶縁体シート２２ａ～２２ｇに用いられるポリイミドや液晶ポリマ等の熱可塑性樹脂の線膨張係数以下である。より詳細には、セラミックの線膨張係数は、例えば７×１０-6／℃程度であり、液晶ポリマの線膨張係数は、例えば１６×１０-6／℃程度であり、エポキシ樹脂の線膨張係数は、例えば１０×１０-6／℃程度である。ただし、エポキシ樹脂の線膨張係数についてはエポキシ樹脂に添加するフィラーの量で調整されてもよい。 Further, the linear expansion coefficient of a thermosetting resin such as an epoxy resin used for the coating member 86 is equal to or higher than the linear expansion coefficient of the material (ceramic) of the main body 82, and polyimide or the like used for the insulator sheets 22a to 22g. It is below the linear expansion coefficient of thermoplastic resins, such as a liquid crystal polymer. More specifically, the linear expansion coefficient of the ceramic is, for example, about 7 × 10 −6 / ° C., the linear expansion coefficient of the liquid crystal polymer is, for example, about 16 × 10 −6 / ° C., and the linear expansion coefficient of the epoxy resin. Is, for example, about 10 × 10 −6 / ° C. However, the linear expansion coefficient of the epoxy resin may be adjusted by the amount of filler added to the epoxy resin.
　外部電極２４ａ～２４ｄは、長方形状の導体層であり、絶縁体シート２２ａの表面に設けられている。外部電極２４ａ～２４ｄは、左側から右側へとこの順に並んでいる。外部電極２６ａ，２６ｂは、長方形状の導体層であり、絶縁体シート２２ｇの裏面に設けられている。外部電極２６ａ，２６ｂは、左側から右側へとこの順に並んでいる。 The external electrodes 24a to 24d are rectangular conductor layers and are provided on the surface of the insulator sheet 22a. The external electrodes 24a to 24d are arranged in this order from the left side to the right side. The external electrodes 26a and 26b are rectangular conductor layers, and are provided on the back surface of the insulator sheet 22g. The external electrodes 26a and 26b are arranged in this order from the left side to the right side.
　回路導体層２８ａ～２８ｅ，２９ａ～２９ｅはそれぞれ、絶縁体シート２２ｂ～２２ｆの表面上に設けられている導体層であり、多層基板２０内の回路の一部を構成している。回路導体層２８ａ～２８ｅ，２９ａ～２９ｅは、図２では、線状をなす配線であるが、例えば、矩形状等の面状をなすコンデンサ導体やグランド導体等であってもよい。回路導体層２８ａ～２８ｅは、パッケージ部品８０に対して左側において、左右方向に延在している。ただし、回路導体層２８ｅの右端は、上側から見たときに、パッケージ部品８０と重なっている。回路導体層２９ａ～２９ｅは、パッケージ部品８０に対して右側において、左右方向に延在している。ただし、回路導体層２９ｅの左端は、上側から見たときに、パッケージ部品８０と重なっている。 The circuit conductor layers 28a to 28e and 29a to 29e are conductor layers provided on the surfaces of the insulator sheets 22b to 22f, respectively, and constitute a part of the circuit in the multilayer substrate 20. The circuit conductor layers 28a to 28e and 29a to 29e are linear wirings in FIG. 2, but may be capacitor conductors, ground conductors, or the like having a rectangular shape. The circuit conductor layers 28 a to 28 e extend in the left-right direction on the left side with respect to the package component 80. However, the right end of the circuit conductor layer 28e overlaps with the package component 80 when viewed from above. The circuit conductor layers 29 a to 29 e extend in the left-right direction on the right side with respect to the package component 80. However, the left end of the circuit conductor layer 29e overlaps with the package component 80 when viewed from above.
　以上のような回路導体層２８ａ～２８ｅ，２９ａ～２９ｅ及び外部電極２４ａ～２４ｄ，２６ａ，２６ｂの材料は、例えば、銅からなる金属箔である。ただし、回路導体層２８ａ～２８ｅ，２９ａ～２９ｅ及び外部電極２４ａ～２４ｄ，２６ａ，２６ｂの表面には表面粗さを低減するために亜鉛鍍金が施されている。 The material of the circuit conductor layers 28a to 28e, 29a to 29e and the external electrodes 24a to 24d, 26a, and 26b as described above is, for example, a metal foil made of copper. However, the surface of the circuit conductor layers 28a to 28e, 29a to 29e and the external electrodes 24a to 24d, 26a and 26b is plated with zinc to reduce the surface roughness.
　また、回路導体層２８ａ～２８ｅ，２９ａ～２９ｅ及び外部電極２４ａ～２４ｄ，２６ａ，２６ｂにおいて絶縁体シート２２ａ～２２ｇに接触している主面の表面粗さは、回路導体層２８ａ～２８ｅ，２９ａ～２９ｅ及び外部電極２４ａ～２４ｄ，２６ａ，２６ｂにおいて絶縁体シート２２ａ～２２ｇに接触していない主面の表面粗さよりも大きい。これにより、回路導体層２８ａ～２８ｅ，２９ａ～２９ｅ及び外部電極２４ａ～２４ｄ，２６ａ，２６ｂは、絶縁体シート２２ａ～２２ｇの裏面に対してアンカー効果によって固着している。なお、回路導体層２８ａ～２８ｅ，２９ａ～２９ｅ及び外部電極２４ａ～２４ｄ，２６ａ，２６ｂと絶縁体シート２２ａ～２２ｇとは、絶縁体シート２２ａ～２２ｇの材料が回路導体層２８ａ～２８ｅ，２９ａ～２９ｅ及び外部電極２４ａ～２４ｄ，２６ａ，２６ｂの凹凸に入り込むことにより物理的に固着しており、化学結合していない。そのため、回路導体層２８ａ～２８ｅ，２９ａ～２９ｅ及び外部電極２４ａ～２４ｄ，２６ａ，２６ｂと絶縁体シート２２ａ～２２ｇとの境界には接着剤の成分となる樹脂等の異物が殆ど存在していない。 Further, the surface roughness of the main surfaces of the circuit conductor layers 28a to 28e, 29a to 29e and the external electrodes 24a to 24d, 26a, and 26b that are in contact with the insulator sheets 22a to 22g is the circuit conductor layers 28a to 28e, 29a. To 29e and the outer electrodes 24a to 24d, 26a and 26b, the surface roughness of the main surfaces not contacting the insulator sheets 22a to 22g is larger. As a result, the circuit conductor layers 28a to 28e, 29a to 29e and the external electrodes 24a to 24d, 26a and 26b are fixed to the back surfaces of the insulator sheets 22a to 22g by the anchor effect. The circuit conductor layers 28a to 28e, 29a to 29e, the external electrodes 24a to 24d, 26a and 26b, and the insulator sheets 22a to 22g are made of the circuit conductor layers 28a to 28e, 29a to 29e and external electrodes 24a to 24d, 26a and 26b are physically fixed by entering into the irregularities, and are not chemically bonded. For this reason, there is almost no foreign matter such as a resin serving as an adhesive component at the boundary between the circuit conductor layers 28a to 28e, 29a to 29e, the external electrodes 24a to 24d, 26a and 26b, and the insulator sheets 22a to 22g. .
　ビアホール導体ｖ１～ｖ７はそれぞれ、絶縁体シート２２ａ～２２ｇを上下方向に貫通する層間接続導体である。ビアホール導体ｖ１～ｖ６はそれぞれ、上側から下側に行くにしたがって太くなる形状をなしている。ビアホール導体ｖ７は、上側から下側に行くにしたがって細くなる形状をなしている。ビアホール導体ｖ１は、外部電極２４ａと回路導体層２８ａとを接続している。ビアホール導体ｖ２は、回路導体層２８ａと回路導体層２８ｂとを接続している。ビアホール導体ｖ３は、回路導体層２８ｂと回路導体層２８ｃとを接続している。ビアホール導体ｖ４は、回路導体層２８ｃと回路導体層２８ｄとを接続している。ビアホール導体ｖ５は、回路導体層２８ｄと回路導体層２８ｅとを接続している。ビアホール導体ｖ６とビアホール導体ｖ７とは、互いに接続されることにより一連のビアホール導体を構成している。ビアホール導体ｖ６，ｖ７は、回路導体層２８ｅと外部電極２６ａとを接続している。これにより、外部電極２４ａと外部電極２６ａとが電気的に接続されている。 The via-hole conductors v1 to v7 are interlayer connection conductors that penetrate the insulating sheets 22a to 22g in the vertical direction, respectively. Each of the via-hole conductors v1 to v6 has a shape that becomes thicker from the upper side to the lower side. The via-hole conductor v7 has a shape that becomes thinner from the upper side to the lower side. The via-hole conductor v1 connects the external electrode 24a and the circuit conductor layer 28a. The via-hole conductor v2 connects the circuit conductor layer 28a and the circuit conductor layer 28b. The via-hole conductor v3 connects the circuit conductor layer 28b and the circuit conductor layer 28c. The via-hole conductor v4 connects the circuit conductor layer 28c and the circuit conductor layer 28d. The via-hole conductor v5 connects the circuit conductor layer 28d and the circuit conductor layer 28e. The via hole conductor v6 and the via hole conductor v7 are connected to each other to form a series of via hole conductors. The via-hole conductors v6 and v7 connect the circuit conductor layer 28e and the external electrode 26a. Thereby, the external electrode 24a and the external electrode 26a are electrically connected.
　ビアホール導体ｖ１１～ｖ１７はそれぞれ、絶縁体シート２２ａ～２２ｇを上下方向に貫通する層間接続導体である。ビアホール導体ｖ１１～ｖ１６はそれぞれ、上側から下側に行くにしたがって太くなる形状をなしている。ビアホール導体ｖ１７は、上側から下側に行くにしたがって細くなる形状をなしている。ビアホール導体ｖ１１は、外部電極２４ｂと回路導体層２９ａとを接続している。ビアホール導体ｖ１２は、回路導体層２９ａと回路導体層２９ｂとを接続している。ビアホール導体ｖ１３は、回路導体層２９ｂと回路導体層２９ｃとを接続している。ビアホール導体ｖ１４は、回路導体層２９ｃと回路導体層２９ｄとを接続している。ビアホール導体ｖ１５は、回路導体層２９ｄと回路導体層２９ｅとを接続している。ビアホール導体ｖ１６とビアホール導体ｖ１７とは、互いに接続されることにより一連のビアホール導体を構成している。ビアホール導体ｖ１６，ｖ１７は、回路導体層２９ｅと外部電極２６ｂとを接続している。これにより、外部電極２４ｄと外部電極２６ｂとが電気的に接続されている。 Via-hole conductors v11 to v17 are interlayer connection conductors penetrating the insulating sheets 22a to 22g in the vertical direction, respectively. Each of the via-hole conductors v11 to v16 has a shape that becomes thicker from the upper side to the lower side. The via-hole conductor v17 has a shape that becomes thinner from the upper side to the lower side. The via-hole conductor v11 connects the external electrode 24b and the circuit conductor layer 29a. The via-hole conductor v12 connects the circuit conductor layer 29a and the circuit conductor layer 29b. The via-hole conductor v13 connects the circuit conductor layer 29b and the circuit conductor layer 29c. The via-hole conductor v14 connects the circuit conductor layer 29c and the circuit conductor layer 29d. The via-hole conductor v15 connects the circuit conductor layer 29d and the circuit conductor layer 29e. The via hole conductor v16 and the via hole conductor v17 constitute a series of via hole conductors by being connected to each other. The via-hole conductors v16 and v17 connect the circuit conductor layer 29e and the external electrode 26b. Thereby, the external electrode 24d and the external electrode 26b are electrically connected.
　ビアホール導体ｖ１００（接続導体の一例）は、コーティング部材８６及び絶縁体シート２２ｅを上下方向に貫通しており、外部電極８４ａと回路導体層２８ｅとを接続している。より詳細には、ビアホール導体ｖ１００の上端は、外部電極８４ａに接続されており、ビアホール導体ｖ１００の下端は回路導体層２８ｅに接続されている。そして、ビアホール導体ｖ１００は、外部電極８４ａとパッケージ部品８０の下面との間に存在するコーティング部材８６を上下方向に貫通すると共に、絶縁体シート２２ｅを上下方向に貫通している。従って、ビアホール導体ｖ１００は、パッケージ部品８０の下面を通過している。 The via-hole conductor v100 (an example of a connection conductor) penetrates the coating member 86 and the insulating sheet 22e in the vertical direction, and connects the external electrode 84a and the circuit conductor layer 28e. More specifically, the upper end of the via hole conductor v100 is connected to the external electrode 84a, and the lower end of the via hole conductor v100 is connected to the circuit conductor layer 28e. The via-hole conductor v100 penetrates the coating member 86 existing between the external electrode 84a and the lower surface of the package component 80 in the vertical direction and penetrates the insulator sheet 22e in the vertical direction. Therefore, the via-hole conductor v100 passes through the lower surface of the package component 80.
　ビアホール導体ｖ１０２は、コーティング部材８６及び絶縁体シート２２ｅを上下方向に貫通しており、外部電極８４ｂと回路導体層２９ｅとを接続している。より詳細には、ビアホール導体ｖ１０２の上端は、外部電極８４ｂに接続されており、ビアホール導体ｖ１０２の下端は回路導体層２９ｅに接続されている。そして、ビアホール導体ｖ１０２は、外部電極８４ｂとパッケージ部品８０の下面との間に存在するコーティング部材８６を上下方向に貫通すると共に、絶縁体シート２２ｅを上下方向に貫通している。従って、ビアホール導体ｖ１０２は、パッケージ部品８０の下面を通過している。 The via-hole conductor v102 penetrates the coating member 86 and the insulating sheet 22e in the vertical direction, and connects the external electrode 84b and the circuit conductor layer 29e. More specifically, the upper end of the via hole conductor v102 is connected to the external electrode 84b, and the lower end of the via hole conductor v102 is connected to the circuit conductor layer 29e. The via-hole conductor v102 penetrates the coating member 86 existing between the external electrode 84b and the lower surface of the package component 80 in the vertical direction and penetrates the insulator sheet 22e in the vertical direction. Therefore, the via-hole conductor v102 passes through the lower surface of the package component 80.
　ビアホール導体ｖ１～ｖ７，ｖ１１～ｖ１７，ｖ１００，ｖ１０２は、銅、錫や銀等の金属を主成分とする導電性ペーストが固化したものである。本実施形態では、ビアホール導体ｖ１～ｖ７，ｖ１１～ｖ１７の材料とビアホール導体ｖ１００，ｖ１０２の材料とは同じである。 Via-hole conductors v1 to v7, v11 to v17, v100, and v102 are solidified conductive pastes mainly composed of metals such as copper, tin, and silver. In the present embodiment, the material of the via-hole conductors v1 to v7 and v11 to v17 and the material of the via-hole conductors v100 and v102 are the same.
　次に、電子部品６０，７０について説明する。電子部品６０，７０は、基材２２の表面上に実装される電子部品であり、例えば、半導体集積回路である。ただし、電子部品６０，７０は、コンデンサやインダクタ等のチップ型電子部品であってもよい。電子部品６０は、本体６０ａ及び外部電極６２ａ，６２ｂを備えている。本体６０ａは直方体状をなしている。外部電極６２ａ，６２ｂは、本体６０ａの下面に設けられており、左側から右側へとこの順に並んでいる。そして、外部電極６２ａ，６２ｂはそれぞれ、外部電極２４ａ，２４ｂに例えばはんだ６４ａ，６４ｂにより接続される。電子部品７０は、本体７０ａ及び外部電極７２ａ，７２ｂを備えている。本体７０ａは直方体状をなしている。外部電極７２ａ，７２ｂは、本体７０ａの下面に設けられており、左側から右側へとこの順に並んでいる。そして、外部電極７２ａ，７２ｂはそれぞれ、外部電極２４ｃ，２４ｄに例えばはんだ７４ａ，７４ｂにより接続される。 Next, the electronic components 60 and 70 will be described. The electronic components 60 and 70 are electronic components mounted on the surface of the base material 22 and are, for example, semiconductor integrated circuits. However, the electronic components 60 and 70 may be chip-type electronic components such as capacitors and inductors. The electronic component 60 includes a main body 60a and external electrodes 62a and 62b. The main body 60a has a rectangular parallelepiped shape. The external electrodes 62a and 62b are provided on the lower surface of the main body 60a, and are arranged in this order from the left side to the right side. The external electrodes 62a and 62b are connected to the external electrodes 24a and 24b, for example, by solders 64a and 64b. The electronic component 70 includes a main body 70a and external electrodes 72a and 72b. The main body 70a has a rectangular parallelepiped shape. The external electrodes 72a and 72b are provided on the lower surface of the main body 70a, and are arranged in this order from the left side to the right side. The external electrodes 72a and 72b are connected to the external electrodes 24c and 24d by, for example, solders 74a and 74b.
　次に、マザー基板１００について説明する。マザー基板１００は、携帯電話等に用いられる大判の回路基板である。マザー基板１００は、基本的には、可撓性を有さない硬質な基板であるが、可撓性を有していてもよい。マザー基板１００は、本体１０２及び外部電極１０４ａ，１０４ｂを含んでいる。本体１０２は、上側から見たときに、長方形状をなす板状の多層基板である。本体１０２の内部及び表面には電気回路が形成されている。以下では、本体１０２の上側の主面を表面と称し、本体１０２の下側の主面を裏面と称す。なお、マザー基板１００の表面及び裏面の少なくとも一方には、図示しない表面実装型部品やシールドケース等が実装されていてもよい。 Next, the mother substrate 100 will be described. The mother board 100 is a large circuit board used for a mobile phone or the like. The mother substrate 100 is basically a hard substrate that does not have flexibility, but may have flexibility. The mother substrate 100 includes a main body 102 and external electrodes 104a and 104b. The main body 102 is a plate-shaped multilayer substrate having a rectangular shape when viewed from above. An electric circuit is formed inside and on the surface of the main body 102. Hereinafter, the upper main surface of the main body 102 is referred to as a front surface, and the lower main surface of the main body 102 is referred to as a back surface. Note that a surface mount type component, a shield case, or the like (not shown) may be mounted on at least one of the front surface and the back surface of the mother substrate 100.
　外部電極１０４ａ，１０４ｂは、長方形状の導体層であり、本体１０２の表面に設けられている。外部電極１０４ａ，１０４ｂは、左側から右側へとこの順に並ぶように配置されている。なお、マザー基板１００には、外部電極１０４ａ，１０４ｂ以外の図示しない外部電極が更に設けられていてもよい。 The external electrodes 104 a and 104 b are rectangular conductor layers and are provided on the surface of the main body 102. The external electrodes 104a and 104b are arranged in this order from the left side to the right side. The mother substrate 100 may further be provided with external electrodes (not shown) other than the external electrodes 104a and 104b.
　多層基板２０は、マザー基板１００の表面上に実装されている。より詳細には、外部電極２６ａ，２６ｂはそれぞれ、外部電極１０４ａ，１０４ｂに対してはんだ１１０ａ，１１０ｂにより実装されている。 The multilayer substrate 20 is mounted on the surface of the mother substrate 100. More specifically, the external electrodes 26a and 26b are mounted on the external electrodes 104a and 104b by solders 110a and 110b, respectively.
＜多層基板の製造方法＞
　以下に、多層基板２０の製造方法について図面を参照しながら説明する。図４Ａないし図４Ｄ及び図５Ａないし図５Ｄは、パッケージ部品８０の製造時の透視図である。なお、図４Ａないし図４Ｄ及び図５Ａないし図５Ｄにおいて電子部品８１が点線で示されていることは、電子部品８１が樹脂内に存在していることを意味する。図５Ｅ、図６Ａ、図６Ｂ及び図７は、多層基板２０の製造時の断面構造図である。以下では、一つの多層基板２０が作製される場合を例にとって説明するが、実際には、大判の絶縁体シートが積層及びカットされることにより、同時に複数の多層基板２０が作製される。 <Multilayer substrate manufacturing method>
Below, the manufacturing method of the multilayer substrate 20 is demonstrated, referring drawings. 4A to 4D and FIGS. 5A to 5D are perspective views when the package component 80 is manufactured. 4A to 4D and 5A to 5D that the electronic component 81 is indicated by a dotted line means that the electronic component 81 is present in the resin. 5E, FIG. 6A, FIG. 6B, and FIG. 7 are cross-sectional structure diagrams when the multilayer substrate 20 is manufactured. Hereinafter, a case where one multilayer substrate 20 is manufactured will be described as an example, but actually, a plurality of multilayer substrates 20 are manufactured simultaneously by laminating and cutting large-sized insulator sheets.
　パッケージ部品８０の製造方法について、図４Ａないし図４Ｄ及び図５Ａないし図５Ｄを参照しながら説明する。本工程（第１の工程の一例）では、電子部品８１の表面の少なくとも一部をコーティング部材８６により覆うことにより、上下方向の両端に位置し、かつ、上下方向に実質的に平行な上面及び下面を有するパッケージ部品８０を形成する。本実施形態では、電子部品８１の表面の全体をコーティング部材８６により覆うことによりパッケージ部品８０を形成する。 The manufacturing method of the package component 80 will be described with reference to FIGS. 4A to 4D and FIGS. 5A to 5D. In this step (an example of the first step), by covering at least a part of the surface of the electronic component 81 with the coating member 86, the upper surface positioned at both ends in the vertical direction and substantially parallel to the vertical direction and A package component 80 having a lower surface is formed. In the present embodiment, the package component 80 is formed by covering the entire surface of the electronic component 81 with the coating member 86.
　まず、図４Ａに示すように、複数の電子部品８１をＰＥＴフィルム等の樹脂シート２００上に配置する。次に、図４Ｂに示すように、ＵＶ硬化性を有するエポキシ樹脂を含む液体状の材料を樹脂シート２００上に塗布した後に、ＵＶ硬化性を有するエポキシ樹脂を含む材料に対してＵＶを照射して、樹脂層２０２を形成する。これにより、複数の電子部品８１は、樹脂層２０２内に埋没する。 First, as shown in FIG. 4A, a plurality of electronic components 81 are arranged on a resin sheet 200 such as a PET film. Next, as shown in FIG. 4B, after applying a liquid material containing a UV curable epoxy resin on the resin sheet 200, the material containing the UV curable epoxy resin is irradiated with UV. Thus, the resin layer 202 is formed. Thereby, the plurality of electronic components 81 are buried in the resin layer 202.
　次に、図４Ｃに示すように、樹脂層２０２の上面をグラインダーにより研磨して、樹脂層２０２の上下方向の厚みを適切な値に調整すると共に、樹脂層２０２の上面を平坦化する。その後、図４Ｄに示すように、複数の電子部品８１及び樹脂層２０２から樹脂シート２００を剥離する。このとき、外部電極８４ａ，８４ｂの一部が樹脂層２０２から露出している。 Next, as shown in FIG. 4C, the upper surface of the resin layer 202 is polished with a grinder to adjust the vertical thickness of the resin layer 202 to an appropriate value, and the upper surface of the resin layer 202 is flattened. Thereafter, as illustrated in FIG. 4D, the resin sheet 200 is peeled from the plurality of electronic components 81 and the resin layer 202. At this time, a part of the external electrodes 84 a and 84 b is exposed from the resin layer 202.
　次に、図５Ａに示すように、複数の電子部品８１及び樹脂層２０２の表裏を反転した後、複数の電子部品８１及び樹脂層２０２の下面に樹脂シート２０１を貼り付ける。次に、図５Ｂに示すように、ＵＶ硬化性を有するエポキシ樹脂を含む液体状の材料を樹脂層２０２上に塗布した後に、ＵＶ硬化性を有するエポキシ樹脂を含む材料に対してＵＶを照射して、樹脂層２０３を形成する。これにより、複数の電子部品８１は、樹脂層２０２，２０３内に埋没し、外部に露出しなくなる。 Next, as shown in FIG. 5A, after the front and back of the plurality of electronic components 81 and the resin layer 202 are reversed, the resin sheet 201 is attached to the lower surfaces of the plurality of electronic components 81 and the resin layer 202. Next, as shown in FIG. 5B, a liquid material containing a UV curable epoxy resin is applied onto the resin layer 202, and then the material containing the UV curable epoxy resin is irradiated with UV. Thus, the resin layer 203 is formed. Thereby, the plurality of electronic components 81 are buried in the resin layers 202 and 203 and are not exposed to the outside.
　なお、予め樹脂層２０３を形成しておき、樹脂層２０３上に複数の電子部品８１を配置し、樹脂層２０３上に樹脂層２０２を形成してもよい。 The resin layer 203 may be formed in advance, a plurality of electronic components 81 may be disposed on the resin layer 203, and the resin layer 202 may be formed on the resin layer 203.
　次に、図５Ｃに示すように、樹脂層２０３の上面をグラインダーにより研磨して、樹脂層２０２，２０３の上下方向の厚みを適切な値に調整すると共に、樹脂層２０３の上面を平坦化する。次に、図５Ｄに示すように、樹脂層２０２，２０３をダイサーによりカットした後、樹脂層２０３から樹脂シート２０１を剥離する。これにより、複数のパッケージ部品８０が完成する。 Next, as shown in FIG. 5C, the upper surface of the resin layer 203 is polished by a grinder to adjust the vertical thickness of the resin layers 202 and 203 to an appropriate value, and the upper surface of the resin layer 203 is flattened. . Next, as illustrated in FIG. 5D, the resin layers 202 and 203 are cut with a dicer, and then the resin sheet 201 is peeled from the resin layer 203. Thereby, a plurality of package parts 80 are completed.
　次に、液晶ポリマにより作製された絶縁体シート２２ａ～２２ｇを準備する。次に、絶縁体シート２２ａ～２２ｇの一方の主面の全面に銅箔を形成する。具体的には、絶縁体シート２２ａ～２２ｆの表面に銅箔を張り付ける。絶縁体シート２２ｇの裏面に銅箔を張り付ける。更に、絶縁体シート２２ａ～２２ｇの銅箔の表面に、例えば、防錆のための亜鉛鍍金を施して、平滑化する。なお、銅箔以外の金属箔が用いられてもよい。 Next, insulator sheets 22a to 22g made of a liquid crystal polymer are prepared. Next, a copper foil is formed on the entire main surface of one of the insulator sheets 22a to 22g. Specifically, copper foil is attached to the surfaces of the insulator sheets 22a to 22f. A copper foil is attached to the back surface of the insulator sheet 22g. Furthermore, the surface of the copper foils of the insulator sheets 22a to 22g is smoothed by, for example, applying zinc plating for rust prevention. In addition, metal foils other than copper foil may be used.
　次に、絶縁体シート２２ｂ～２２ｄに貫通孔Ｈ１～Ｈ３を形成する。貫通孔Ｈ１～Ｈ３の形成は、例えば、絶縁体シート２２ｂ～２２ｄの裏面からレーザービームを照射することにより行われる。なお、パンチにより絶縁体シート２２ｂ～２２ｄを打ち抜くことによって貫通孔Ｈ１～Ｈ３を形成してもよい。 Next, through holes H1 to H3 are formed in the insulating sheets 22b to 22d. The through holes H1 to H3 are formed, for example, by irradiating a laser beam from the back surfaces of the insulator sheets 22b to 22d. The through holes H1 to H3 may be formed by punching the insulating sheets 22b to 22d by punching.
　次に、絶縁体シート２２ａの表面上に形成された銅箔をパターニングすることにより、図２Ａに示すように、外部電極２４ａ～２４ｄを絶縁体シート２２ａの表面上に形成する。具体的には、絶縁体シート２２ａの表面の銅箔上に、図３に示す外部電極２４ａ～２４ｄと同じ形状のレジストを印刷する。そして、銅箔に対してエッチング処理を施すことにより、レジストにより覆われていない部分の銅箔を除去する。その後、洗浄液（レジスト除去液）を吹き付けてレジストを除去する。これにより、図２Ａに示すような、外部電極２４ａ～２４ｄが絶縁体シート２２ａの表面上にフォトリソグラフィ工程により形成される。 Next, by patterning the copper foil formed on the surface of the insulator sheet 22a, the external electrodes 24a to 24d are formed on the surface of the insulator sheet 22a as shown in FIG. 2A. Specifically, a resist having the same shape as the external electrodes 24a to 24d shown in FIG. 3 is printed on the copper foil on the surface of the insulating sheet 22a. And the copper foil of the part which is not covered with the resist is removed by performing an etching process with respect to copper foil. Thereafter, the resist is removed by spraying a cleaning liquid (resist removing liquid). As a result, external electrodes 24a to 24d as shown in FIG. 2A are formed on the surface of the insulator sheet 22a by a photolithography process.
　次に、図２Ａに示すように、回路導体層２８ａ，２９ａを絶縁体シート２２ｂの表面上に形成する。また、図２Ａに示すように、回路導体層２８ｂ，２９ｂを絶縁体シート２２ｃの表面上に形成する。また、図２Ａに示すように、回路導体層２８ｃ，２９ｃを絶縁体シート２２ｄの表面上に形成する。また、図２Ａに示すように、回路導体層２８ｄ，２９ｄを絶縁体シート２２ｅの表面上に形成する。また、図２Ａに示すように、回路導体層２８ｅ，２９ｅを絶縁体シート２２ｆの表面上に形成する。また、図２Ａに示すように、外部電極２６ａ，２６ｂを絶縁体シート２２ｇの裏面上に形成する。なお、回路導体層２８ａ～２８ｅ，２９ａ～２９ｅ及び外部電極２６ａ，２６ｂの形成工程は、外部電極２４ａ，２４ｂの形成工程と同じであるので説明を省略する。なお、貫通孔Ｈ１～Ｈ３を形成する工程は、外部電極２４ａ，２４ｂ，２６ａ，２６ｂ及び回路導体層２８ａ～２８ｅ，２９ａ～２９ｅを形成する工程の後に行われてもよい。 Next, as shown in FIG. 2A, circuit conductor layers 28a and 29a are formed on the surface of the insulator sheet 22b. Further, as shown in FIG. 2A, circuit conductor layers 28b and 29b are formed on the surface of the insulator sheet 22c. Further, as shown in FIG. 2A, circuit conductor layers 28c and 29c are formed on the surface of the insulator sheet 22d. Further, as shown in FIG. 2A, circuit conductor layers 28d and 29d are formed on the surface of the insulator sheet 22e. Further, as shown in FIG. 2A, circuit conductor layers 28e and 29e are formed on the surface of the insulator sheet 22f. As shown in FIG. 2A, the external electrodes 26a and 26b are formed on the back surface of the insulating sheet 22g. Note that the process of forming the circuit conductor layers 28a to 28e, 29a to 29e and the external electrodes 26a and 26b is the same as the process of forming the external electrodes 24a and 24b, and the description thereof will be omitted. The step of forming the through holes H1 to H3 may be performed after the step of forming the external electrodes 24a, 24b, 26a, 26b and the circuit conductor layers 28a to 28e, 29a to 29e.
　次に、ビアホール導体ｖ１～ｖ４，ｖ６，ｖ７，ｖ１１～ｖ１４，ｖ１６，ｖ１７が形成される位置にレーザービームを照射することによって貫通孔を形成する。そして、貫通孔に銅、錫や銀等の金属を主成分とする導電性ペーストを充填する。 Next, a through hole is formed by irradiating a laser beam at a position where the via-hole conductors v1 to v4, v6, v7, v11 to v14, v16, and v17 are formed. Then, the through hole is filled with a conductive paste whose main component is a metal such as copper, tin or silver.
　次に、図５Ｅに示すように、パッケージ部品８０の下面に接触する絶縁体シート２２ｅ（第１の絶縁体層の一例）、及び、絶縁体シート２２ｅよりも上側（積層方向の一方側の一例）に積層される絶縁体シート２２ａ～２２ｄ（第３の絶縁体層の一例）内にパッケージ部品８０を内蔵させるように、絶縁体シート２２ａ～２２ｅを積層する（第４の工程の一例）。すなわち、絶縁体シート２２ａ～２２ｄを積層した後、下側からパッケージ部品８０を貫通孔Ｈ１～Ｈ３内に挿入し、絶縁体シート２２ｅを絶縁体シート２２ｄの下側に積層する。更に、絶縁体シート２２ａ～２２ｅに対して加熱処理及び加圧処理（熱圧着処理）を施して、絶縁体シート２２ａ～２２ｅを熱圧着する（以下、本工程を１次プレスとも呼ぶ）。この際、絶縁体シート２２ａ～２２ｇを構成する熱可塑性樹脂の軟化点以上、かつ、コーティング部材８６を構成する熱硬化性樹脂が分解しない温度（例えば２６０℃～２９０℃）で加熱処理を行う。ただし、この加熱処理温度において、絶縁体シート２２ａ～２２ｇを構成する熱可塑性樹脂よりもコーティング部材８６を構成する熱硬化性樹脂が大きく軟化しなければよい。軟化とは、ヤング率が小さくなることである。言い換えれば、ある同一の加熱処理温度条件において、コーティング部材８６を構成する樹脂のヤング率は、絶縁体シート２２ａ～２２ｇを構成する樹脂のヤング率よりも大きければよい。１次プレスでは、絶縁体シート２２ａ～２２ｅが軟化すると共に、貫通孔内の導電性ペーストが固化する。これにより、絶縁体シート２２ａ～２２ｅ同士が接合されると共に、ビアホール導体ｖ１～ｖ４，ｖ１１～ｖ１４が形成される。更に、熱圧着によって絶縁体シート２２ａ～２２ｅの熱可塑性樹脂が軟化することにより、空間Ｓｐの内周面とパッケージ部品８０の表面との間に形成されている隙間に熱可塑性樹脂が流れこむ。その後、絶縁体シート２２ａ～２２ｅが冷却されることにより、熱可塑性樹脂が固化し、空間Ｓｐの内周面とパッケージ部品８０の表面とが固着する。 Next, as shown in FIG. 5E, an insulator sheet 22e (an example of a first insulator layer) that contacts the lower surface of the package component 80, and an upper side (an example of one side in the stacking direction) of the insulator sheet 22e. The insulating sheets 22a to 22e are stacked so as to incorporate the package component 80 in the insulating sheets 22a to 22d (an example of the third insulating layer) stacked on (4). That is, after the insulating sheets 22a to 22d are stacked, the package component 80 is inserted into the through holes H1 to H3 from the lower side, and the insulating sheet 22e is stacked on the lower side of the insulating sheet 22d. Further, the insulator sheets 22a to 22e are subjected to heat treatment and pressure treatment (thermocompression treatment), and the insulator sheets 22a to 22e are thermocompression bonded (hereinafter, this process is also referred to as a primary press). At this time, the heat treatment is performed at a temperature not lower than the softening point of the thermoplastic resin constituting the insulating sheets 22a to 22g and at which the thermosetting resin constituting the coating member 86 is not decomposed (for example, 260 ° C. to 290 ° C.). However, at this heat treatment temperature, it is sufficient that the thermosetting resin constituting the coating member 86 does not soften more greatly than the thermoplastic resin constituting the insulator sheets 22a to 22g. Softening means that Young's modulus becomes small. In other words, the Young's modulus of the resin that constitutes the coating member 86 only needs to be larger than the Young's modulus of the resin that constitutes the insulator sheets 22a to 22g under the same heat treatment temperature condition. In the primary press, the insulator sheets 22a to 22e are softened and the conductive paste in the through holes is solidified. As a result, the insulator sheets 22a to 22e are joined together, and the via-hole conductors v1 to v4 and v11 to v14 are formed. Furthermore, the thermoplastic resin of the insulator sheets 22a to 22e is softened by thermocompression, so that the thermoplastic resin flows into the gap formed between the inner peripheral surface of the space Sp and the surface of the package component 80. Thereafter, the insulator sheets 22a to 22e are cooled to solidify the thermoplastic resin, and the inner peripheral surface of the space Sp and the surface of the package component 80 are fixed.
　次に、図６Ａに示すように、ビアホール導体ｖ５，ｖ１５，ｖ１００，ｖ１０２が形成される位置にレーザービームを照射することにより貫通孔を形成する。貫通孔は、絶縁体シート２２ｅ及びコーティング部材８６の一部を貫通し、パッケージ部品８０の外部電極８４ａ，８４ｂの一部が露出するように設けられる。そして、図６Ｂに示すように、貫通孔に銅、錫や銀等の金属を主成分とする導電性ペーストを充填する。 Next, as shown in FIG. 6A, a through hole is formed by irradiating a laser beam at a position where the via-hole conductors v5, v15, v100, and v102 are formed. The through hole is provided so as to penetrate a part of the insulating sheet 22e and the coating member 86 and to expose a part of the external electrodes 84a and 84b of the package component 80. Then, as shown in FIG. 6B, the through hole is filled with a conductive paste mainly composed of a metal such as copper, tin, or silver.
　次に、図７に示すように、絶縁体シート２２ｅよりも下側（積層方向の他方側の一例）に積層される絶縁体シート２２ｆ，２２ｇ（第４の絶縁体層の一例）を絶縁体シート２２ｅの下側に積層する（第２の工程・第６の工程の一例）。この積層において、ビアホール導体ｖ１００，ｖ１０２となるべき導電性ペースト（接続導体の一例）と回路導体層２８ｅ，２９ｅとが接続される。更に、絶縁体シート２２ａ～２２ｇに対して加熱処理及び加圧処理（熱圧着処理）を施して、絶縁体シート２２ａ～２２ｇを熱圧着して基材２２を形成する（以下、本工程を２次プレスとも呼ぶ。第３の工程の一例）。この際、絶縁体シート２２ａ～２２ｇを構成する熱可塑性樹脂の軟化点以上、かつ、コーティング部材８６を構成する熱硬化性樹脂が分解しない温度以下の温度（例えば２６０℃～２９０℃）で加熱処理を行う。２次プレスでは、絶縁体シート２２ａ～２２ｇが軟化すると共に、貫通孔内の導電性ペーストが固化する。これにより、絶縁体シート２２ａ～２２ｇ同士が接合されると共に、ビアホール導体ｖ５～ｖ７，ｖ１５～ｖ１７，ｖ１００，ｖ１０２が形成される（第５の工程の一例）。また、ビアホール導体ｖ１００が外部電極８４ａと回路導体層２８ｅとを接続し、ビアホール導体ｖ１０２が外部電極８４ｂと回路導体層２９ｅとを接続するようになる。以上の工程を経て、多層基板２０が完成する。 Next, as shown in FIG. 7, insulator sheets 22f and 22g (an example of a fourth insulator layer) stacked on the lower side (an example of the other side in the stacking direction) of the insulator sheet 22e are insulators. Laminate below the sheet 22e (an example of the second step and the sixth step). In this lamination, the conductive paste (an example of a connection conductor) to be the via-hole conductors v100 and v102 and the circuit conductor layers 28e and 29e are connected. Further, the insulating sheets 22a to 22g are subjected to heat treatment and pressure treatment (thermocompression treatment), and the insulating sheets 22a to 22g are thermocompression bonded to form the base material 22 (hereinafter, this process is referred to as 2). Also called the next press, an example of the third step). At this time, heat treatment is performed at a temperature (for example, 260 ° C. to 290 ° C.) that is equal to or higher than the softening point of the thermoplastic resin that forms the insulating sheets 22a to 22g and that does not decompose the thermosetting resin that forms the coating member 86. I do. In the secondary press, the insulator sheets 22a to 22g are softened and the conductive paste in the through holes is solidified. As a result, the insulator sheets 22a to 22g are joined together, and the via-hole conductors v5 to v7, v15 to v17, v100, and v102 are formed (an example of the fifth step). The via hole conductor v100 connects the external electrode 84a and the circuit conductor layer 28e, and the via hole conductor v102 connects the external electrode 84b and the circuit conductor layer 29e. The multilayer substrate 20 is completed through the above steps.
　次に、電子部品６０，７０を基材２２に対してはんだ６４ａ，６４ｂ，７４ａ．７４ｂにより実装する。 Next, the electronic components 60 and 70 are soldered to the base material 22 with solder 64a, 64b, 74a. It is mounted by 74b.
　最後に、図１に示すように、多層基板２０をマザー基板１００にはんだ１１０ａ，１１０ｂにより実装する。この後、マザー基板１００を筺体に搭載することにより、電子機器１０が完成する。 Finally, as shown in FIG. 1, the multilayer substrate 20 is mounted on the mother substrate 100 with solders 110a and 110b. After that, the electronic device 10 is completed by mounting the mother substrate 100 on the housing.
＜効果＞
　本実施形態に係る多層基板２０によれば、基材２２の上面及び下面の平坦性を向上させることができる。より詳細には、特許文献１に記載の樹脂多層基板５００では、部品５０３ａ，５０３ｂの上面及び下面には図示しない外部電極が設けられている。そのため、部品５０３ａ，５０３ｂの上面及び下面には凹凸が存在する。このような凹凸が存在すると、部品５０３ａ，５０３ｂの上面及び下面と樹脂シート５０２ａ，５０２ｄとの間に大きな隙間が形成される。そして、熱圧着工程において、部品５０３ａ，５０３ｂ近傍の樹脂シート５０２ａ，５０２ｄは、軟化・流動して隙間に流れ込む。その結果、樹脂多層基板５００の上面及び下面において、部品５０３ａ，５０３ｂの直上及び直下並びにその近傍に凹凸が形成される。 <Effect>
According to the multilayer substrate 20 according to the present embodiment, the flatness of the upper surface and the lower surface of the base material 22 can be improved. More specifically, in the resin multilayer substrate 500 described in Patent Document 1, external electrodes (not shown) are provided on the upper and lower surfaces of the components 503a and 503b. Therefore, there are irregularities on the upper and lower surfaces of the components 503a and 503b. When such irregularities exist, large gaps are formed between the upper and lower surfaces of the components 503a and 503b and the resin sheets 502a and 502d. In the thermocompression bonding process, the resin sheets 502a and 502d in the vicinity of the components 503a and 503b soften and flow and flow into the gap. As a result, irregularities are formed on the upper and lower surfaces of the resin multilayer substrate 500 directly above and below the components 503a and 503b and in the vicinity thereof.
　そこで、多層基板２０では、コーティング部材８６は、熱硬化性樹脂を含む材料により構成され、かつ、電子部品８１の表面の少なくとも一部を覆っている。そして、パッケージ部品８０の上面及び下面の一部は、コーティング部材８６により構成されている。すなわち、電子部品８１の上面及び下面の凹凸がコーティング部材８６により平坦化されている。更に、絶縁体シート２２ａ～２２ｇを構成している熱可塑性樹脂の軟化点温度において、コーティング部材８６を構成している熱硬化性樹脂のヤング率は、絶縁体シート２２ａ～２２ｇを構成している熱可塑性樹脂のヤング率よりも大きい。これにより、基材２２の加熱処理及び加圧処理の際に、コーティング部材８６が軟化せず、又は軟化しにくく、絶縁体シート２２ａ～２２ｇが軟化する。その結果、パッケージ部品８０の上面及び下面が平坦の状態が維持されたままで、絶縁体シート２２ａ～２２ｇが軟化及び流動し、パッケージ部品８０の表面と空間Ｓｐの内周面との間の隙間を埋める。ただし、パッケージ部品８０の上面及び下面は平面であるので、パッケージ部品８０の上面と絶縁体シート２２ａの裏面との間の隙間、及び、パッケージ部品８０の下面と絶縁体シート２２ａの表面との間の隙間は非常に小さい。よって、熱圧着工程において、パッケージ部品８０近傍の絶縁体シート２２ａ，２２ｅが、軟化・流動して大量に隙間に流れ込むことが抑制される。その結果、多層基板２０の表面及び裏面において、パッケージ部品８０の直上及び直下並びにその近傍に凹凸が形成されることが抑制される。 Therefore, in the multilayer substrate 20, the coating member 86 is made of a material including a thermosetting resin and covers at least a part of the surface of the electronic component 81. A part of the upper and lower surfaces of the package component 80 is constituted by a coating member 86. That is, the unevenness of the upper surface and the lower surface of the electronic component 81 is flattened by the coating member 86. Furthermore, the Young's modulus of the thermosetting resin constituting the coating member 86 at the softening point temperature of the thermoplastic resin constituting the insulator sheets 22a to 22g constitutes the insulator sheets 22a to 22g. It is larger than the Young's modulus of the thermoplastic resin. As a result, during the heat treatment and pressure treatment of the base material 22, the coating member 86 is not softened or hardly softened, and the insulator sheets 22a to 22g are softened. As a result, the insulating sheets 22a to 22g soften and flow while the upper and lower surfaces of the package component 80 are maintained flat, and a gap between the surface of the package component 80 and the inner peripheral surface of the space Sp is formed. fill in. However, since the upper surface and the lower surface of the package component 80 are flat, the gap between the upper surface of the package component 80 and the back surface of the insulator sheet 22a, and between the lower surface of the package component 80 and the surface of the insulator sheet 22a. The gap is very small. Therefore, in the thermocompression bonding process, the insulator sheets 22a and 22e in the vicinity of the package component 80 are suppressed from being softened and flowed and flowing into the gap in a large amount. As a result, on the front and back surfaces of the multilayer substrate 20, it is possible to suppress the formation of irregularities directly above and below the package component 80 and in the vicinity thereof.
　基材２２の上面の平坦性が向上すると、基材２２上に電子部品６０，７０を実装する際に、電子部品６０，７０の実装ミスの発生が抑制される。また、基材２２の下面の平坦性が向上すると、多層基板２０をマザー基板１００に実装する際に、多層基板２０の実装ミスの発生が抑制される。 When the flatness of the upper surface of the base material 22 is improved, when mounting the electronic components 60 and 70 on the base material 22, occurrence of mounting errors of the electronic components 60 and 70 is suppressed. Further, when the flatness of the lower surface of the base material 22 is improved, the mounting mistake of the multilayer substrate 20 is suppressed when the multilayer substrate 20 is mounted on the mother substrate 100.
　また、多層基板２０では、電子部品８１と回路導体層２８ｅ，２９ｅとの間で断線が発生することが抑制される。より詳細には、パッケージ部品８０の上面及び下面が平面であるので、パッケージ部品８０の上面と絶縁体シート２２ａの裏面との間の隙間、及び、パッケージ部品８０の下面と絶縁体シート２２ａの表面との間の隙間は非常に小さい。そのため、図５Ｅの工程において、パッケージ部品８０が、例えば、前後方向に延在する軸周り（図５Ｅにおける時計回り又は反時計回り）に回転することが抑制される。これにより、図６Ｂに示す工程において、パッケージ部品８０の直下における絶縁体シート２２ｅの裏面が傾くことが抑制される。従って、ビアホール導体ｖ１００の下端とビアホール導体ｖ１０２の下端の上下方向における位置が揃う。その結果、図７に示す工程において、ビアホール導体ｖ１００と回路導体層２８ｅとがより確実に接続され、ビアホール導体ｖ１０２と回路導体層２９ｅとがより確実に接続されるようになる。 Further, in the multilayer substrate 20, the occurrence of disconnection between the electronic component 81 and the circuit conductor layers 28e and 29e is suppressed. More specifically, since the upper surface and the lower surface of the package component 80 are flat, the gap between the upper surface of the package component 80 and the back surface of the insulator sheet 22a, and the lower surface of the package component 80 and the surface of the insulator sheet 22a. The gap between is very small. Therefore, in the process of FIG. 5E, for example, the package component 80 is prevented from rotating around an axis extending in the front-rear direction (clockwise or counterclockwise in FIG. 5E). Thereby, in the process shown in FIG. 6B, the back surface of the insulator sheet 22e immediately below the package component 80 is suppressed from being inclined. Accordingly, the vertical positions of the lower end of the via-hole conductor v100 and the lower end of the via-hole conductor v102 are aligned. As a result, in the step shown in FIG. 7, the via-hole conductor v100 and the circuit conductor layer 28e are more reliably connected, and the via-hole conductor v102 and the circuit conductor layer 29e are more reliably connected.
　また、多層基板２０では、以下の理由によっても、電子部品８１と回路導体層２８ｅ，２９ｅとの間で断線が発生することが抑制される。より詳細には、パッケージ部品８０の側面は、上下方向に平行な平面である。パッケージ部品８０の側面と貫通孔Ｈ１～Ｈ３の内周面との間の隙間は非常に小さい。これにより、基材２２の加熱処理及び加圧処理の際に、絶縁体シート２２ｂ～２２ｅが隙間に大量に流れ込むことが抑制される。その結果、空間Ｓｐ内においてパッケージ部品８０が上下方向に延在する軸周りに回転することが抑制される。よって、電子部品８１の外部電極８４ａ，８４ｂの位置と回路導体層２８ｅ，２９ｅの位置との間にずれが生じにくい。その結果、外部電極８４ａ，８４ｂと回路導体層２８ｅ，２９ｅとがビアホール導体ｖ１００，ｖ１０２により確実に接続されるようになる。 Further, in the multilayer substrate 20, occurrence of disconnection between the electronic component 81 and the circuit conductor layers 28e and 29e is suppressed for the following reason. More specifically, the side surface of the package component 80 is a plane parallel to the vertical direction. The gap between the side surface of the package component 80 and the inner peripheral surfaces of the through holes H1 to H3 is very small. This suppresses a large amount of the insulator sheets 22b to 22e from flowing into the gap during the heat treatment and pressure treatment of the base material 22. As a result, the package component 80 is prevented from rotating around the axis extending in the vertical direction in the space Sp. Therefore, it is difficult for a deviation to occur between the positions of the external electrodes 84a and 84b of the electronic component 81 and the positions of the circuit conductor layers 28e and 29e. As a result, the external electrodes 84a and 84b and the circuit conductor layers 28e and 29e are reliably connected by the via-hole conductors v100 and v102.
　また、多層基板２０では、多層基板２０の製造時に、空間Ｓｐの内周面とパッケージ部品８０との間の隙間を小さくすることができる。より詳細には、パッケージ部品８０は、電子部品８１がコーティング部材８６により覆われることにより構成されている。よって、コーティング部材８６を研磨等により加工することで、コーティング部材８６を任意の形状及び寸法に加工することができる。その結果、コーティング部材８６の形状と空間Ｓｐの形状とを近づけることができ、空間Ｓｐの内周面とパッケージ部品８０との間の隙間を小さくすることができる。以上のように、空間Ｓｐの内周面とパッケージ部品８０との間の隙間が小さくなると、基材２２の上面及び下面の平坦性が向上すると共に、パッケージ部品８０の空間Ｓｐ内における回転が抑制される。よって、電子部品６０，７０及び多層基板２０の実装ミスの発生が抑制され、電子部品８１と回路導体層２８ｅ，２９ｅとの間で断線が発生することが抑制される。 In the multilayer substrate 20, the gap between the inner peripheral surface of the space Sp and the package component 80 can be reduced when the multilayer substrate 20 is manufactured. More specifically, the package component 80 is configured by covering an electronic component 81 with a coating member 86. Therefore, the coating member 86 can be processed into an arbitrary shape and size by processing the coating member 86 by polishing or the like. As a result, the shape of the coating member 86 and the shape of the space Sp can be made closer, and the gap between the inner peripheral surface of the space Sp and the package component 80 can be reduced. As described above, when the gap between the inner peripheral surface of the space Sp and the package component 80 is reduced, the flatness of the upper surface and the lower surface of the base material 22 is improved and the rotation of the package component 80 in the space Sp is suppressed. Is done. Therefore, the occurrence of mounting mistakes in the electronic components 60 and 70 and the multilayer substrate 20 is suppressed, and the occurrence of disconnection between the electronic component 81 and the circuit conductor layers 28e and 29e is suppressed.
　また、ビアホール導体ｖ１００，ｖ１０２の材料は、ビアホール導体ｖ１～ｖ７，ｖ１１～ｖ１７の材料と同じである。そのため、基材２２の加熱処理及び加圧処理の際に、ビアホール導体ｖ６，ｖ７，ｖ１６，ｖ１７，ｖ１００，ｖ１０２を同時に硬化させることができる。 The material of the via-hole conductors v100 and v102 is the same as the material of the via-hole conductors v1 to v7 and v11 to v17. Therefore, the via-hole conductors v6, v7, v16, v17, v100, and v102 can be simultaneously cured during the heat treatment and pressure treatment of the base material 22.
　また、多層基板２０によれば、本体８２とコーティング部材８６との間の剥離、及び、コーティング部材８６と絶縁体シート２２ａ～２２ｅとの剥離の発生を抑制できる。より詳細には、多層基板２０の製造時には、加熱処理が施される。本体８２、コーティング部材８６及び絶縁体シート２２ａ～２２ｅは異なる材料で作製されているので、これらの膨張量も異なる。このような膨張量の相違は、本体８２とコーティング部材８６との間の剥離、及び、コーティング部材８６と絶縁体シート２２ａ～２２ｅとの剥離の発生の原因となる。 Moreover, according to the multilayer substrate 20, it is possible to suppress the occurrence of peeling between the main body 82 and the coating member 86 and the peeling between the coating member 86 and the insulating sheets 22a to 22e. More specifically, heat treatment is performed when the multilayer substrate 20 is manufactured. Since the main body 82, the coating member 86, and the insulator sheets 22a to 22e are made of different materials, their expansion amounts are also different. Such a difference in the expansion amount causes peeling between the main body 82 and the coating member 86 and peeling between the coating member 86 and the insulating sheets 22a to 22e.
　そこで、多層基板２０では、コーティング部材８６に用いられるエポキシ樹脂等の熱可塑性樹脂の線膨張係数は、本体８２の材料（セラミック）の線膨張係数以上であり、かつ、絶縁体シート２２ａ～２２ｇに用いられるポリイミドや液晶ポリマ等の熱可塑性樹脂の線膨張係数以下である。これにより、コーティング部材８６に用いられるエポキシ樹脂等の熱可塑性樹脂の線膨張係数と本体８２の材料（セラミック）の線膨張係数との差を小さくしつつ、コーティング部材８６に用いられるエポキシ樹脂等の熱可塑性樹脂の線膨張係数と絶縁体シート２２ａ～２２ｇに用いられるポリイミドや液晶ポリマ等の熱可塑性樹脂の線膨張係数との差を小さくすることができる。その結果、前記の膨張量の差が小さくなり、前記の剥離の発生が抑制される。 Therefore, in the multilayer substrate 20, the linear expansion coefficient of a thermoplastic resin such as an epoxy resin used for the coating member 86 is equal to or greater than the linear expansion coefficient of the material (ceramic) of the main body 82, and the insulator sheets 22a to 22g It is below the linear expansion coefficient of thermoplastic resins, such as a polyimide used and liquid crystal polymer. Thereby, while reducing the difference between the linear expansion coefficient of the thermoplastic resin such as an epoxy resin used for the coating member 86 and the linear expansion coefficient of the material (ceramic) of the main body 82, the epoxy resin used for the coating member 86, etc. The difference between the linear expansion coefficient of the thermoplastic resin and the linear expansion coefficient of the thermoplastic resin such as polyimide or liquid crystal polymer used for the insulator sheets 22a to 22g can be reduced. As a result, the difference in the expansion amount is reduced, and the occurrence of the peeling is suppressed.
（第１の変形例）
　以下に、第１の変形例に係る多層基板２０ａについて図面を参照しながら説明する。図８は、多層基板２０ａの断面構造図である。 (First modification)
Hereinafter, a multilayer substrate 20a according to a first modification will be described with reference to the drawings. FIG. 8 is a cross-sectional structure diagram of the multilayer substrate 20a.
　多層基板２０ａは、パッケージ部品８０の構造において多層基板２０と相違する。より詳細には、多層基板２０ａでは、パッケージ部品８０の下面において外部電極８４ａ，８４ｂが露出している。その代わり、パッケージ部品８０の下面が絶縁体シート２３（第２の絶縁体層の一例）により覆われている。以下に、かかる相違点を中心に、多層基板２０ａについて説明する。 The multilayer substrate 20 a is different from the multilayer substrate 20 in the structure of the package component 80. More specifically, in the multilayer substrate 20a, the external electrodes 84a and 84b are exposed on the lower surface of the package component 80. Instead, the lower surface of the package component 80 is covered with the insulator sheet 23 (an example of a second insulator layer). Hereinafter, the multilayer substrate 20a will be described focusing on the difference.
　多層基板２０ａでは、パッケージ部品８０の下面は、平面である。ただし、パッケージ部品８０の下面の一部は、コーティング部材８６により構成されており、パッケージ部品８０の下面の残余の部分は、外部電極８４ａ，８４ｂにより構成されている。更に、絶縁体シート２３は、上側から見たときに、パッケージ部品８０の下面と同じ形状及び同じサイズを有しており、パッケージ部品８０の下面の全体を覆っている。また、パッケージ部品８０の上下方向の厚みと絶縁体シート２３の上下方向の厚みとの合計は、絶縁体シート２２ｂ～２２ｄの上下方向の厚みの合計と実質的に等しくなっている。 In the multilayer substrate 20a, the lower surface of the package component 80 is a flat surface. However, a part of the lower surface of the package component 80 is configured by the coating member 86, and the remaining portion of the lower surface of the package component 80 is configured by the external electrodes 84a and 84b. Furthermore, the insulator sheet 23 has the same shape and the same size as the lower surface of the package component 80 when viewed from above, and covers the entire lower surface of the package component 80. Further, the sum of the vertical thickness of the package component 80 and the vertical thickness of the insulating sheet 23 is substantially equal to the total vertical thickness of the insulating sheets 22b to 22d.
　また、ビアホール導体ｖ１００は、絶縁体シート２３，２２ｅを上下方向に貫通しており、外部電極８４ａと回路導体層２８ｅとを接続している。ただし、ビアホール導体ｖ１００は、コーティング部材８６を貫通していない。ビアホール導体ｖ１０２は、絶縁体シート２３，２２ｅを上下方向に貫通しており、外部電極８４ｂと回路導体層２９ｅとを接続している。ただし、ビアホール導体ｖ１０２は、コーティング部材８６を貫通していない。 The via-hole conductor v100 penetrates the insulator sheets 23 and 22e in the vertical direction, and connects the external electrode 84a and the circuit conductor layer 28e. However, the via-hole conductor v100 does not penetrate the coating member 86. The via-hole conductor v102 penetrates the insulator sheets 23 and 22e in the vertical direction, and connects the external electrode 84b and the circuit conductor layer 29e. However, the via-hole conductor v102 does not penetrate the coating member 86.
　次に、多層基板２０ａの製造方法について説明する。図９Ａないし図９Ｄは、パッケージ部品８０及び絶縁体シート２３の製造時の透視図である。なお、図９Ａないし図９Ｄにおいて電子部品８１が点線で示されていることは、電子部品８１が樹脂内に存在していることを意味する。図１０及び図１１は、多層基板２０ａの製造時の断面構造図である。 Next, a method for manufacturing the multilayer substrate 20a will be described. 9A to 9D are perspective views at the time of manufacturing the package component 80 and the insulator sheet 23. 9A to 9D that the electronic component 81 is indicated by a dotted line means that the electronic component 81 is present in the resin. 10 and 11 are cross-sectional structure diagrams when the multilayer substrate 20a is manufactured.
　まず、図９Ａに示すように、複数の電子部品８１をマザーシート２２３上に配置する。マザーシート２２３は、ポリイミドや液晶ポリマ等の可撓性を有する熱可塑性樹脂を含む材料により構成されており、上側から見たときに、絶縁体シート２３がマトリクス状に配列された大判のシートである。なお、マザーシート２２３の材料は、絶縁体シート２２ａ～２２ｇの材料と同じである。 First, as shown in FIG. 9A, a plurality of electronic components 81 are arranged on the mother sheet 223. The mother sheet 223 is made of a material containing a flexible thermoplastic resin such as polyimide or liquid crystal polymer, and is a large sheet in which the insulator sheets 23 are arranged in a matrix when viewed from above. is there. The material of the mother sheet 223 is the same as the material of the insulator sheets 22a to 22g.
　次に、図９Ｂに示すように、ＵＶ硬化性を有するエポキシ樹脂を含む材料をマザーシート２２３上に塗布した後に、ＵＶ硬化性を有するエポキシ樹脂を含む材料に対してＵＶを照射して、樹脂層２０２を形成する。これにより、複数の電子部品８１は、複数の電子部品８１の外部電極８４ａ，８４ｂの下面の少なくとも一部がマザーシート２２３に接触するように樹脂層２０２内に埋没する。複数の電子部品８１の外部電極８４ａ，８４ｂの下面の少なくとも一部がマザーシート２２３に接触するように樹脂層２０２内に埋没しているので、後の工程で貫通孔を設ける際に、絶縁体シート２２ｅ及び絶縁体シート２３の一部を貫通することにより、外部電極８４ａ，８４ｂの一部が露出させることができる。 Next, as shown in FIG. 9B, after a material containing a UV curable epoxy resin is applied on the mother sheet 223, the material containing the UV curable epoxy resin is irradiated with UV, and the resin Layer 202 is formed. Accordingly, the plurality of electronic components 81 are buried in the resin layer 202 so that at least a part of the lower surfaces of the external electrodes 84 a and 84 b of the plurality of electronic components 81 are in contact with the mother sheet 223. Since at least a part of the lower surfaces of the external electrodes 84a and 84b of the plurality of electronic components 81 are buried in the resin layer 202 so as to be in contact with the mother sheet 223, an insulator is provided when a through hole is provided in a later step. By penetrating part of the sheet 22e and the insulator sheet 23, part of the external electrodes 84a and 84b can be exposed.
　次に、図９Ｃに示すように、樹脂層２０２の上面をグラインダーにより研磨して、樹脂層２０２の上下方向の厚みを適切な値に調整すると共に、樹脂層２０２の上面を平坦化する。最後に、図９Ｄに示すように、樹脂層２０２をダイサーによりカットする。これにより、下面に絶縁体シート２３が貼り付けられた複数のパッケージ部品８０が完成する。 Next, as shown in FIG. 9C, the upper surface of the resin layer 202 is polished with a grinder to adjust the vertical thickness of the resin layer 202 to an appropriate value, and the upper surface of the resin layer 202 is flattened. Finally, as shown in FIG. 9D, the resin layer 202 is cut with a dicer. Thereby, a plurality of package components 80 having the insulator sheet 23 attached to the lower surface are completed.
　次に、多層基板２０ａの製造方法において絶縁体シート２２ａ～２２ｇを準備する工程からビアホール導体ｖ１～ｖ４，ｖ６，ｖ７，ｖ１１～ｖ１４，ｖ１６，ｖ１７が形成される位置に形成した貫通孔に導電性ペーストを充填する工程までの工程については、多層基板２０の製造方法におけるこれらの工程と同じであるので説明を省略する。ただし、貫通孔は、絶縁体シート２２ｅ及び絶縁体シート２３の一部を貫通し、パッケージ部品８０の外部電極８４ａ，８４ｂの一部が露出するように設けられる。 Next, from the step of preparing the insulator sheets 22a to 22g in the manufacturing method of the multilayer substrate 20a, the conductive material is conducted to the through holes formed at positions where the via-hole conductors v1 to v4, v6, v7, v11 to v14, v16, and v17 are formed. The steps up to the step of filling the conductive paste are the same as those steps in the method for manufacturing the multilayer substrate 20, and thus the description thereof is omitted. However, the through hole is provided so as to penetrate part of the insulator sheet 22e and the insulator sheet 23 and to expose part of the external electrodes 84a and 84b of the package component 80.
　次に、図１０に示すように、絶縁体シート２２ａ～２２ｄを積層した後、下側から絶縁体シート２３が貼り付けられたパッケージ部品８０を貫通孔Ｈ１～Ｈ３内に挿入し、絶縁体シート２２ｅを絶縁体シート２２ｄの下側に積層する。更に、絶縁体シート２２ａ～２２ｅに対して加熱処理及び加圧処理（熱圧着処理とも呼ぶ）を施す（以下、本工程を１次プレスとも呼ぶ）。 Next, as shown in FIG. 10, after the insulator sheets 22a to 22d are stacked, the package component 80 to which the insulator sheet 23 is attached is inserted into the through holes H1 to H3 from below, and the insulator sheets 22e is laminated below the insulator sheet 22d. Further, heat treatment and pressure treatment (also referred to as thermocompression treatment) are performed on the insulator sheets 22a to 22e (hereinafter, this step is also referred to as a primary press).
　次に、図１１に示すように、ビアホール導体ｖ５，ｖ１５，ｖ１００，ｖ１０２が形成される位置にレーザービームを照射することにより貫通孔を形成する。そして、これらの貫通孔に銅、錫や銀等の金属を主成分とする導電性ペーストを充填する。なお、多層基板２０ａの製造方法のこの後の工程は、多層基板２０の製造方法と同じであるので説明を省略する。 Next, as shown in FIG. 11, a through-hole is formed by irradiating a laser beam at a position where the via-hole conductors v5, v15, v100, and v102 are formed. These through holes are filled with a conductive paste whose main component is a metal such as copper, tin or silver. Note that the subsequent steps of the method for manufacturing the multilayer substrate 20a are the same as the method for manufacturing the multilayer substrate 20, and thus the description thereof is omitted.
　以上のように構成された多層基板２０ａも多層基板２０と同じ作用効果を奏することが可能である。 The multilayer substrate 20 a configured as described above can also exhibit the same operational effects as the multilayer substrate 20.
　また、多層基板２０ａの製造方法によれば、パッケージ部品８０を容易に作成することができる。より詳細には、多層基板２０の製造方法では、図４Ｄに示す工程において、複数の電子部品８１及び樹脂層２０２から樹脂シート２００を剥離する。更に、図５Ａの工程において、複数の電子部品８１及び樹脂層２０２の表裏を反転した後、複数の電子部品８１及び樹脂層２０２の下面に樹脂シート２０１を貼り付ける。このように、多層基板２０の製造方法では、電子部品８１の全体をコーティング部材８６により覆うために、樹脂シート２００の剥離及び樹脂シート２０１の貼り付けが必要であった。 Further, according to the method for manufacturing the multilayer substrate 20a, the package component 80 can be easily created. More specifically, in the method for manufacturing the multilayer substrate 20, the resin sheet 200 is peeled from the plurality of electronic components 81 and the resin layer 202 in the step illustrated in FIG. 4D. Further, in the step of FIG. 5A, after the front and back of the plurality of electronic components 81 and the resin layer 202 are reversed, the resin sheet 201 is attached to the lower surfaces of the plurality of electronic components 81 and the resin layer 202. As described above, in the method for manufacturing the multilayer substrate 20, it is necessary to peel the resin sheet 200 and attach the resin sheet 201 in order to cover the entire electronic component 81 with the coating member 86.
　一方、多層基板２０ａでは、樹脂シート２００，２０１の代わりにマザーシート２２３が用いられている。マザーシート２２３の材料は、絶縁体シート２２ａ～２２ｇと同じ材料である。そのため、マザーシート２２３が分割されて得られる絶縁体シート２３は、パッケージ部品８０の下面から剥離されることなく、基材２２の一部として用いられる。よって、多層基板２０ａの製造方法では、剥離・反転等の工程が不要となり、パッケージ部品８０を容易に作成することができる。 On the other hand, in the multilayer substrate 20a, a mother sheet 223 is used instead of the resin sheets 200 and 201. The material of the mother sheet 223 is the same material as the insulator sheets 22a to 22g. Therefore, the insulator sheet 23 obtained by dividing the mother sheet 223 is used as a part of the base material 22 without being peeled off from the lower surface of the package component 80. Therefore, in the manufacturing method of the multilayer substrate 20a, processes such as peeling and reversal are unnecessary, and the package component 80 can be easily created.
（第２の変形例）
　以下に、第２の変形例に係る多層基板２０ｂについて図面を参照しながら説明する。図１２は、多層基板２０ｂ，２０ｇの断面構造図である。 (Second modification)
Hereinafter, a multilayer substrate 20b according to a second modification will be described with reference to the drawings. FIG. 12 is a cross-sectional structure diagram of the multilayer substrates 20b and 20g.
　多層基板２０ｂは、ビアホール導体ｖ１００，ｖ１０２の長さ、並びに、回路導体層２８ｆ，２９ｆ及びビアホール導体ｖ８，ｖ１８を更に備えている点において多層基板２０と相違する。以下に係る相違点を中心に、多層基板２０ｂについて説明する。 The multilayer substrate 20b is different from the multilayer substrate 20 in that the via-hole conductors v100 and v102 are further provided with circuit conductor layers 28f and 29f and via-hole conductors v8 and v18. The multilayer substrate 20b will be described focusing on the differences related to the following.
　回路導体層２８ｆ，２９ｆは、絶縁体シート２２ｅの表面上に設けられている。回路導体層２８ｆは、回路導体層２８ｄに対して右側に設けられており、左右方向に延在している。回路導体層２９ｆは、回路導体層２９ｄに対して左側に設けられており、左右方向に延在している。回路導体層２８ｆ，２９ｆは、パッケージ部品８０の下面に接触している。 The circuit conductor layers 28f and 29f are provided on the surface of the insulator sheet 22e. The circuit conductor layer 28f is provided on the right side of the circuit conductor layer 28d and extends in the left-right direction. The circuit conductor layer 29f is provided on the left side of the circuit conductor layer 29d and extends in the left-right direction. The circuit conductor layers 28 f and 29 f are in contact with the lower surface of the package component 80.
　ビアホール導体ｖ８は、絶縁体シート２２ｅを上下方向に貫通しており、回路導体層２８ｆと回路導体層２８ｅとを接続している。ビアホール導体ｖ１８は、絶縁体シート２２ｅを上下方向に貫通しており、回路導体層２９ｆと回路導体層２９ｅとを接続している。 The via-hole conductor v8 penetrates the insulator sheet 22e in the vertical direction, and connects the circuit conductor layer 28f and the circuit conductor layer 28e. The via-hole conductor v18 penetrates the insulator sheet 22e in the vertical direction, and connects the circuit conductor layer 29f and the circuit conductor layer 29e.
　ビアホール導体ｖ１００は、コーティング部材８６を上下方向に貫通しており、外部電極８４ａと回路導体層２８ｆとを接続している。より詳細には、ビアホール導体ｖ１００の上端は、外部電極８４ａに接続されており、ビアホール導体ｖ１００の下端は回路導体層２８ｆに接続されている。そして、ビアホール導体ｖ１００は、外部電極８４ａとパッケージ部品８０の下面との間に存在するコーティング部材８６を上下方向に貫通しており、絶縁体シート２２ｅを上下方向に貫通していない。 The via-hole conductor v100 penetrates the coating member 86 in the vertical direction, and connects the external electrode 84a and the circuit conductor layer 28f. More specifically, the upper end of the via hole conductor v100 is connected to the external electrode 84a, and the lower end of the via hole conductor v100 is connected to the circuit conductor layer 28f. The via-hole conductor v100 penetrates the coating member 86 existing between the external electrode 84a and the lower surface of the package component 80 in the vertical direction, and does not penetrate the insulator sheet 22e in the vertical direction.
　ビアホール導体ｖ１０２は、コーティング部材８６を上下方向に貫通しており、外部電極８４ｂと回路導体層２９ｆとを接続している。より詳細には、ビアホール導体ｖ１０２の上端は、外部電極８４ｂに接続されており、ビアホール導体ｖ１０２の下端は回路導体層２９ｆに接続されている。そして、ビアホール導体ｖ１０２は、外部電極８４ｂとパッケージ部品８０の下面との間に存在するコーティング部材８６を上下方向に貫通しており、絶縁体シート２２ｅを上下方向に貫通していない。 The via-hole conductor v102 penetrates the coating member 86 in the vertical direction, and connects the external electrode 84b and the circuit conductor layer 29f. More specifically, the upper end of the via hole conductor v102 is connected to the external electrode 84b, and the lower end of the via hole conductor v102 is connected to the circuit conductor layer 29f. The via-hole conductor v102 penetrates the coating member 86 existing between the external electrode 84b and the lower surface of the package component 80 in the vertical direction, and does not penetrate the insulator sheet 22e in the vertical direction.
　次に、多層基板２０ｂの製造方法について説明する。図１３ないし図１６は、多層基板２０ｂ，２０ｇの製造時の断面構造図である。 Next, a method for manufacturing the multilayer substrate 20b will be described. 13 to 16 are cross-sectional structure diagrams of the multilayer substrates 20b and 20g when they are manufactured.
　多層基板２０ｂのパッケージ部品８０の製造方法は、多層基板２０のパッケージ部品８０の製造方法と同じであるので説明を省略する。 Since the manufacturing method of the package component 80 of the multilayer substrate 20b is the same as the manufacturing method of the package component 80 of the multilayer substrate 20, description thereof will be omitted.
　次に、多層基板２０ｂの製造方法において絶縁体シート２２ａ～２２ｇを準備する工程からビアホール導体ｖ１～ｖ３，ｖ５～ｖ７，ｖ１１～ｖ１３，ｖ１５～ｖ１７が形成される位置に形成した貫通孔に導電性ペーストを充填する工程までの工程については、多層基板２０の製造方法におけるこれらの工程と同じであるので説明を省略する。ただし、多層基板２０の製造方法では、ビアホール導体ｖ４，ｖ１４が形成される位置に形成した貫通孔に導電性ペーストを充填するのに対して、多層基板２０ｂ製造方法では、ビアホール導体ｖ５，ｖ１５が形成される位置に形成した貫通孔に導電性ペーストを充填する。更に、多層基板２０ｂの製造方法では、回路導体層２８ｆ，２９ｆを形成すると共に、ビアホール導体ｖ８，ｖ１８が形成される位置に形成した貫通孔に導電性ペーストを充填する必要がある。 Next, from the step of preparing the insulator sheets 22a to 22g in the manufacturing method of the multilayer substrate 20b, the conductive material is conducted to the through holes formed at positions where the via-hole conductors v1 to v3, v5 to v7, v11 to v13, and v15 to v17 are formed. The steps up to the step of filling the conductive paste are the same as those steps in the method for manufacturing the multilayer substrate 20, and thus the description thereof is omitted. However, in the manufacturing method of the multilayer substrate 20, the conductive paste is filled in the through holes formed at positions where the via-hole conductors v4 and v14 are formed, whereas in the manufacturing method of the multilayer substrate 20b, the via-hole conductors v5 and v15 are formed. The conductive paste is filled in the through-hole formed at the position where it is formed. Furthermore, in the manufacturing method of the multilayer substrate 20b, it is necessary to form the circuit conductor layers 28f and 29f and to fill the through holes formed at positions where the via-hole conductors v8 and v18 are formed with a conductive paste.
　次に、図１３に示すように、絶縁体シート２２ａ～２２ｄを積層した後、下側からパッケージ部品８０を貫通孔Ｈ１～Ｈ３内に挿入する。更に、絶縁体シート２２ａ～２２ｄに対して加熱処理及び加圧処理を施す（１次プレス）。 Next, as shown in FIG. 13, after the insulator sheets 22a to 22d are stacked, the package component 80 is inserted into the through holes H1 to H3 from below. Furthermore, the insulating sheets 22a to 22d are subjected to heat treatment and pressure treatment (primary press).
　次に、図１４に示すように、ビアホール導体ｖ４，ｖ１４，ｖ１００，ｖ１０２が形成される位置にレーザービームを照射することにより貫通孔を形成する。そして、図１５に示すように、これらの貫通孔に銅、錫や銀等の金属を主成分とする導電性ペーストを充填する。 Next, as shown in FIG. 14, a through-hole is formed by irradiating a laser beam at a position where the via-hole conductors v4, v14, v100, and v102 are formed. And as shown in FIG. 15, these through-holes are filled with the electrically conductive paste which has metals, such as copper, tin, and silver, as a main component.
　次に、図１６に示すように、パッケージ部品８０を絶縁体シート２２ａ～２２ｇに内蔵させると共に、ビアホール導体ｖ１００，ｖ１０２となるべき導電性ペースト（接続導体の一例）がそれぞれ回路導体層２８ｆ，２９ｆに接続されるように、絶縁体シート２２ｄの下に絶縁体シート２２ｅ～２２ｇを積層する（第８の工程の一例）。更に、絶縁体シート２２ａ～２２ｇに対して加熱処理及び加圧処理を施して、絶縁体シート２２ａ～２２ｇを熱圧着する（２次プレス）。２次プレスでは、絶縁体シート２２ａ～２２ｇが軟化すると共に、貫通孔内の導電性ペーストが固化する。これにより、絶縁体シート２２ａ～２２ｇ同士が接合されると共に、ビアホール導体ｖ４～ｖ８，ｖ１４～ｖ１８，ｖ１００，ｖ１０２が形成される（第７の工程の一例）。以上の工程を経て、多層基板２０ｂが完成する。 Next, as shown in FIG. 16, the package component 80 is built in the insulator sheets 22a to 22g, and the conductive paste (an example of the connection conductor) to be the via-hole conductors v100 and v102 is provided in the circuit conductor layers 28f and 29f, respectively. Insulator sheets 22e to 22g are laminated below the insulator sheet 22d so as to be connected to the substrate (an example of an eighth step). Further, the insulating sheets 22a to 22g are subjected to heat treatment and pressure treatment, and the insulating sheets 22a to 22g are thermocompression bonded (secondary press). In the secondary press, the insulator sheets 22a to 22g are softened and the conductive paste in the through holes is solidified. As a result, the insulator sheets 22a to 22g are joined together, and the via-hole conductors v4 to v8, v14 to v18, v100, and v102 are formed (an example of the seventh step). Through the above steps, the multilayer substrate 20b is completed.
　以上のように構成された多層基板２０ｂも多層基板２０と同じ作用効果を奏することが可能である。 The multilayer substrate 20b configured as described above can also exhibit the same effects as the multilayer substrate 20.
　また、多層基板２０ｂによれば、ビアホール導体ｖ１００，ｖ１０２による接続が安定する。 Moreover, according to the multilayer substrate 20b, the connection by the via-hole conductors v100 and v102 is stabilized.
　より詳細には、ビアホール導体ｖ１００，ｖ１０２は、コーティング部材８６を上下方向に貫通し、絶縁体シート２２ｅを上下方向に貫通していない。すなわち、ビアホール導体ｖ１００，ｖ１０２はコーティング部材８６のみを介して外部電極８４ａ，８４ｂと回路導体層２８ｆ，２９ｆとを接続している。これにより、多層基板２０と比較して、加熱処理及び加圧処理における絶縁体シート２２ｅの変形量とコーティング部材８６の変形量との差を考慮する必要がない。従って、ビアホール導体ｖ１００，ｖ１０２による接続が安定する。 More specifically, the via-hole conductors v100 and v102 penetrate the coating member 86 in the vertical direction and do not penetrate the insulator sheet 22e in the vertical direction. That is, the via-hole conductors v100 and v102 connect the external electrodes 84a and 84b and the circuit conductor layers 28f and 29f only through the coating member 86. Thereby, it is not necessary to consider the difference between the deformation amount of the insulator sheet 22e and the deformation amount of the coating member 86 in the heat treatment and the pressure treatment as compared with the multilayer substrate 20. Therefore, the connection by the via-hole conductors v100 and v102 is stabilized.
（第３の変形例）
　以下に、第３の変形例に係る多層基板２０ｃについて図面を参照しながら説明する。図１７は、多層基板２０ｃの断面構造図である。 (Third Modification)
Hereinafter, a multilayer substrate 20c according to a third modification will be described with reference to the drawings. FIG. 17 is a cross-sectional structure diagram of the multilayer substrate 20c.
　多層基板２０ｃは、ビアホール導体ｖ５，ｖ１５，ｖ１００，ｖ１０２の代わりにスルーホール導体ｖ５’，ｖ１５’，ｖ１００’，ｖ１０２’が用いられている点、絶縁体シート２２ｆの表裏が反転している点、及び、ビアホール導体ｖ９，ｖ１９が設けられている点において多層基板２０と相違する。以下に、かかる相違点を中心に多層基板２０ｃについて説明する。 In the multilayer substrate 20c, through-hole conductors v5 ′, v15 ′, v100 ′, and v102 ′ are used instead of the via-hole conductors v5, v15, v100, and v102, and the front and back of the insulator sheet 22f are reversed. And the via hole conductors v9 and v19 are different from the multilayer substrate 20. Hereinafter, the multilayer substrate 20c will be described focusing on the difference.
　ビアホール導体ｖ５，ｖ１５，ｖ１００，ｖ１０２は、絶縁体シート２２ｅ及びコーティング部材８６に形成された貫通孔に導電性ペーストが充填され、導電性ペーストが加熱されることにより形成されていた。一方、スルーホール導体ｖ５’，ｖ１５’，ｖ１００’，ｖ１０２’は、絶縁体シート２２ｅ及びコーティング部材８６に形成された貫通孔の内周面に銅めっきが施されることにより形成されている。 The via-hole conductors v5, v15, v100, and v102 were formed by filling the through holes formed in the insulator sheet 22e and the coating member 86 with a conductive paste and heating the conductive paste. On the other hand, the through-hole conductors v <b> 5 ′, v <b> 15 ′, v <b> 100 ′, and v <b> 102 ′ are formed by performing copper plating on the inner peripheral surfaces of the through holes formed in the insulator sheet 22 e and the coating member 86.
　ビアホール導体ｖ９，ｖ１９は、絶縁体シート２２ｆを上下方向に貫通しており、回路導体層２８ｅ，２９ｅに接続されている。 The via-hole conductors v9 and v19 penetrate the insulator sheet 22f in the vertical direction and are connected to the circuit conductor layers 28e and 29e.
　また、前記のとおり、絶縁体シート２２ｆの表裏が反転している。これにより、スルーホール導体ｖ５’，ｖ１５’，ｖ１００’，ｖ１０２’はそれぞれ、ビアホール導体ｖ６，ｖ１６，ｖ９，ｖ１９に接続されている。よって、外部電極８４ａと回路導体層２８ｅとは、スルーホール導体ｖ１００’及びビアホール導体ｖ９を介して接続されている。外部電極８４ｂと回路導体層２９ｅとは、スルーホール導体ｖ１０２’及びビアホール導体ｖ１９を介して接続されている。 Further, as described above, the front and back of the insulator sheet 22f are reversed. Thereby, the through-hole conductors v5 ', v15', v100 ', and v102' are connected to the via-hole conductors v6, v16, v9, and v19, respectively. Therefore, the external electrode 84a and the circuit conductor layer 28e are connected via the through-hole conductor v100 'and the via-hole conductor v9. The external electrode 84b and the circuit conductor layer 29e are connected through a through-hole conductor v102 'and a via-hole conductor v19.
　次に、多層基板２０ｃの製造方法について説明する。図１８、図１９Ａ及び図１９Ｂは、多層基板２０ｃの製造時の断面構造図である。 Next, a method for manufacturing the multilayer substrate 20c will be described. 18, 19A, and 19B are cross-sectional structural diagrams of the multilayer substrate 20c when it is manufactured.
　多層基板２０ｃのパッケージ部品８０の製造方法は、多層基板２０のパッケージ部品８０の製造方法と同じであるので説明を省略する。 Since the manufacturing method of the package component 80 of the multilayer substrate 20c is the same as the manufacturing method of the package component 80 of the multilayer substrate 20, description thereof will be omitted.
　次に、多層基板２０ｃの製造方法において絶縁体シート２２ａ～２２ｇを準備する工程から絶縁体シート２２ａ～２２ｅに対して加熱処理及び加圧処理（１次プレス）を施す工程までの工程については、多層基板２０の製造方法におけるこれらの工程と同じであるので説明を省略する。 Next, in the manufacturing method of the multilayer substrate 20c, the steps from the step of preparing the insulator sheets 22a to 22g to the step of applying heat treatment and pressure treatment (primary press) to the insulator sheets 22a to 22e are as follows: Since these steps are the same as those in the method of manufacturing the multilayer substrate 20, the description thereof is omitted.
　次に、図１８に示すように、スルーホール導体ｖ５’，ｖ１５’，ｖ１００’，ｖ１０２’が形成される位置にレーザービームを照射することにより貫通孔を形成する。そして、図１９Ａに示すように、これらの貫通孔に銅めっきを施してスルーホール導体ｖ５’，ｖ１５’，ｖ１００’，ｖ１０２’を形成する。 Next, as shown in FIG. 18, a through hole is formed by irradiating a laser beam at a position where through-hole conductors v5 ', v15', v100 ', and v102' are formed. Then, as shown in FIG. 19A, these through holes are plated with copper to form through-hole conductors v5 ', v15', v100 ', and v102'.
　次に、図１９Ｂに示すように、絶縁体シート２２ｅの下に絶縁体シート２２ｆ，２２ｇを積層する。ただし、絶縁体シート２２ｆは、回路導体層２８ｅ，２９ｅが設けられている主面が下側を向くように配置される。この後、絶縁体シート２２ａ～２２ｇに対して加熱処理及び加圧処理を施す。以上の工程を経て、多層基板２０ｃが完成する。 Next, as shown in FIG. 19B, insulator sheets 22f and 22g are laminated under the insulator sheet 22e. However, the insulator sheet 22f is arranged so that the main surface on which the circuit conductor layers 28e and 29e are provided faces downward. Thereafter, the insulating sheets 22a to 22g are subjected to a heat treatment and a pressure treatment. The multilayer substrate 20c is completed through the above steps.
　以上のように構成された多層基板２０ｃも多層基板２０と同じ作用効果を奏することが可能である。 The multilayer substrate 20c configured as described above can also exhibit the same effects as the multilayer substrate 20.
（第４の変形例）
　以下に、第４の変形例に係る多層基板２０ｄについて図面を参照しながら説明する。図２０は、多層基板２０ｄの断面構造図である。 (Fourth modification)
Hereinafter, a multilayer substrate 20d according to a fourth modification will be described with reference to the drawings. FIG. 20 is a cross-sectional structure diagram of the multilayer substrate 20d.
　多層基板２０ｄは、パッケージ部品８０’を更に内蔵している点において多層基板２０と相違する。このように、多層基板２０ｄにおいて、２以上のパッケージ部品が内蔵されていてもよい。 The multilayer substrate 20d is different from the multilayer substrate 20 in that it further includes a package component 80 '. Thus, two or more package parts may be incorporated in the multilayer substrate 20d.
　また、パッケージ部品８０’は、電子部品８１’（第１の電子部品の一例），８１’’（第２の電子部品の一例）を含んでいる。電子部品８１’，８１’’は、パッケージ部品８０’内において左右に並んでいる。このように、パッケージ部品８０’は、複数の電子部品を含んでいてもよい。 Further, the package component 80 ′ includes an electronic component 81 ′ (an example of a first electronic component) and 81 ″ (an example of a second electronic component). The electronic components 81 ′ and 81 ″ are arranged side by side in the package component 80 ′. As described above, the package component 80 ′ may include a plurality of electronic components.
　また、電子部品８１’の外部電極８４ａ’，８４ｂ’は、本体８２’の下面のみに設けられている。同様に、電子部品８１’ ’の外部電極８４ａ’’，８４ｂ’’は、本体８２’’の下面のみに設けられている。このように、外部電極は、本体の下面のみに設けられていてもよい。 Further, the external electrodes 84a 'and 84b' of the electronic component 81 'are provided only on the lower surface of the main body 82'. Similarly, the external electrodes 84 a ″ and 84 b ″ of the electronic component 81 ″ ′ are provided only on the lower surface of the main body 82 ″. Thus, the external electrode may be provided only on the lower surface of the main body.
（第５の変形例）
　以下に、第５の変形例に係る多層基板２０ｅについて図面を参照しながら説明する。図２１は、多層基板２０ｅの断面構造図である。 (Fifth modification)
Hereinafter, a multilayer substrate 20e according to a fifth modification will be described with reference to the drawings. FIG. 21 is a sectional view of the multilayer substrate 20e.
　多層基板２０ｅは、絶縁体シート２２ｈが絶縁体シート２２ａの上側に積層されている点、及び、ビアホール導体ｖ１１０，ｖ１１２を更に備えている点において多層基板２０と相違する。以下に係る相違点を中心に多層基板２０ｅについて図面を参照ながら説明する。 The multilayer substrate 20e is different from the multilayer substrate 20 in that an insulator sheet 22h is laminated on the insulator sheet 22a and further provided with via-hole conductors v110 and v112. The multilayer substrate 20e will be described with reference to the drawings with a focus on the following differences.
　基材２２は、絶縁体シート２２ｈ，２２ａ～２２ｇが上側から下側へとこの順に積層されて構成されている。外部電極２４ａ～２４ｄは、絶縁体シート２２ｈの表面上に設けられている。回路導体層２８ｇ，２９ｇは、絶縁体シート２２ａの表面上に設けられている。ビアホール導体ｖ０は、絶縁体シート２２ｈを上下方向に貫通しており、外部電極２４ａと回路導体層２８ｈとを接続している。ビアホール導体ｖ１０は、絶縁体シート２２ｈを上下方向に貫通しており、外部電極２４ｄと回路導体層２９ｇとを接続している。 The base material 22 is configured by laminating insulator sheets 22h and 22a to 22g in this order from the upper side to the lower side. The external electrodes 24a to 24d are provided on the surface of the insulator sheet 22h. The circuit conductor layers 28g and 29g are provided on the surface of the insulator sheet 22a. The via-hole conductor v0 penetrates the insulator sheet 22h in the vertical direction, and connects the external electrode 24a and the circuit conductor layer 28h. The via-hole conductor v10 penetrates the insulator sheet 22h in the vertical direction, and connects the external electrode 24d and the circuit conductor layer 29g.
　ビアホール導体ｖ１１０は、コーティング部材８６及び絶縁体シート２２ａを上下方向に貫通しており、外部電極８４ａと回路導体層２８ｇとを接続している。より詳細には、ビアホール導体ｖ１１０の上端は、回路導体層２８ｇに接続されており、ビアホール導体ｖ１１０の下端は外部電極８４ａに接続されている。そして、ビアホール導体ｖ１１０は、外部電極８４ａとパッケージ部品８０の上面との間に存在するコーティング部材８６を上下方向に貫通すると共に、絶縁体シート２２ａを上下方向に貫通している。従って、ビアホール導体ｖ１１０は、パッケージ部品８０の上面を通過している。 The via-hole conductor v110 penetrates the coating member 86 and the insulating sheet 22a in the vertical direction, and connects the external electrode 84a and the circuit conductor layer 28g. More specifically, the upper end of the via hole conductor v110 is connected to the circuit conductor layer 28g, and the lower end of the via hole conductor v110 is connected to the external electrode 84a. The via-hole conductor v110 penetrates the coating member 86 existing between the external electrode 84a and the upper surface of the package component 80 in the vertical direction and penetrates the insulator sheet 22a in the vertical direction. Therefore, the via-hole conductor v110 passes through the upper surface of the package component 80.
　ビアホール導体ｖ１１２は、コーティング部材８６及び絶縁体シート２２ａを上下方向に貫通しており、外部電極８４ｂと回路導体層２９ｇとを接続している。より詳細には、ビアホール導体ｖ１１２の上端は、回路導体層２９ｇに接続されており、ビアホール導体ｖ１１２の下端は外部電極８４ｂに接続されている。そして、ビアホール導体ｖ１１２は、外部電極８４ｂとパッケージ部品８０の上面との間に存在するコーティング部材８６を上下方向に貫通すると共に、絶縁体シート２２ａを上下方向に貫通している。従って、ビアホール導体ｖ１１２は、パッケージ部品８０の上面を通過している。 The via-hole conductor v112 penetrates the coating member 86 and the insulating sheet 22a in the vertical direction, and connects the external electrode 84b and the circuit conductor layer 29g. More specifically, the upper end of the via hole conductor v112 is connected to the circuit conductor layer 29g, and the lower end of the via hole conductor v112 is connected to the external electrode 84b. The via-hole conductor v112 penetrates the coating member 86 existing between the external electrode 84b and the upper surface of the package component 80 in the vertical direction and penetrates the insulator sheet 22a in the vertical direction. Therefore, the via-hole conductor v112 passes through the upper surface of the package component 80.
　以上のように構成された多層基板２０ｅも多層基板２０と同じ作用効果を奏することが可能である。 The multilayer substrate 20e configured as described above can also exhibit the same effects as the multilayer substrate 20.
　また、多層基板２０ｅでは、パッケージ部品８０の上面がビアホール導体ｖ１１０，ｖ１１２により固定され、パッケージ部品８０の下面がビアホール導体ｖ１００，ｖ１０２により固定されている。これにより、使用時に外力を受けて、パッケージ部品８０が基材２２内において位置ずれを起こすことがより効果的に抑制されるようになる。その結果、パッケージ部品８０と回路導体層２８ｇ，２９ｇ，２８ｆ，２９ｆとの間で断線が生じることが抑制される。 In the multilayer substrate 20e, the upper surface of the package component 80 is fixed by the via-hole conductors v110 and v112, and the lower surface of the package component 80 is fixed by the via-hole conductors v100 and v102. As a result, the package component 80 is more effectively suppressed from being displaced in the base material 22 due to an external force during use. As a result, disconnection between the package component 80 and the circuit conductor layers 28g, 29g, 28f, 29f is suppressed.
（第６の変形例）
　以下に、第６の変形例に係る多層基板２０ｆについて図面を参照しながら説明する。図２２は、多層基板２０ｆの断面構造図である。 (Sixth Modification)
Hereinafter, a multilayer substrate 20f according to a sixth modification will be described with reference to the drawings. FIG. 22 is a sectional view of the multilayer substrate 20f.
　多層基板２０ｆは、パッケージ部品８０が電子部品８１’（第２の電子部品の一例）を更に含んでいる点において多層基板２０ｅと相違する。以下に係る相違点を中心に多層基板２０ｆについて図面を参照ながら説明する。 The multilayer substrate 20f is different from the multilayer substrate 20e in that the package component 80 further includes an electronic component 81 '(an example of a second electronic component). The multilayer substrate 20f will be described with reference to the drawings with a focus on the following differences.
　電子部品８１（第１の電子部品の一例）と電子部品８１’とは、上側から見たときに、重なるように配置されている。また、コーティング部材８６は、電子部品８１，８１’を内蔵している。なお、コーティング部材８６は、電子部品８１，８１’を必ずしも内蔵する必要はなく、電子部品８１，８１'の表面の少なくとも一部を覆っていればよい。 The electronic component 81 (an example of the first electronic component) and the electronic component 81 ′ are arranged so as to overlap when viewed from above. Further, the coating member 86 includes electronic parts 81 and 81 '. Note that the coating member 86 does not necessarily contain the electronic components 81 and 81 ′, and may cover at least a part of the surface of the electronic components 81 and 81 ′.
　電子部品８１’は、本体８２’及び外部電極８４ａ’，８４ｂ’を含んでいる。本体８２’は、直方体状をなしており、本体８２に対して上側に位置している。外部電極８４ａ’，８４ｂ’はそれぞれ、本体８２’の上面に設けられており、左側から右側へとこの順に並んでいる。 The electronic component 81 ′ includes a main body 82 ′ and external electrodes 84 a ′ and 84 b ′. The main body 82 ′ has a rectangular parallelepiped shape and is located on the upper side with respect to the main body 82. The external electrodes 84a 'and 84b' are provided on the upper surface of the main body 82 ', and are arranged in this order from the left side to the right side.
　ビアホール導体ｖ１１０は、コーティング部材８６及び絶縁体シート２２ａを上下方向に貫通しており、外部電極８４ａ’と回路導体層２８ｇとを接続している。ビアホール導体ｖ１１２は、コーティング部材８６及び絶縁体シート２２ａを上下方向に貫通しており、外部電極８４ｂ’と回路導体層２９ｇとを接続している。 The via-hole conductor v110 penetrates the coating member 86 and the insulating sheet 22a in the vertical direction, and connects the external electrode 84a 'and the circuit conductor layer 28g. The via-hole conductor v112 passes through the coating member 86 and the insulating sheet 22a in the vertical direction, and connects the external electrode 84b 'and the circuit conductor layer 29g.
　以上のように構成された多層基板２０ｆも多層基板２０と同じ作用効果を奏することが可能である。 The multilayer substrate 20 f configured as described above can also exhibit the same effects as the multilayer substrate 20.
　また、多層基板２０ｆでは、加熱処理及び加圧処理において、パッケージ部品８０が空間Ｓｐ内において回転することが抑制される。すなわち、パッケージ部品８０の基材２２における位置決めが精度よく行われるので、２つの電子部品８１、８１’の位置決めが精度よく行われるようになる。 In the multilayer substrate 20f, the package component 80 is prevented from rotating in the space Sp during the heat treatment and the pressure treatment. That is, since the positioning of the package component 80 on the base material 22 is performed with high accuracy, the positioning of the two electronic components 81 and 81 ′ is performed with high accuracy.
（第７の変形例）
　以下に、第７の変形例に係る多層基板２０ｇについて図面を参照しながら説明する。図２３は、多層基板２０ｇのパッケージ部品８０の外観斜視図である。図２４Ａは、パッケージ部品８０を上側から見た図である。図２４Ｂは、図２４ＡのＡ－Ａにおける断面構造図である。図２４Ｃは、図２４ＡのＢ－Ｂにおける断面構造図である。 (Seventh Modification)
The multilayer substrate 20g according to the seventh modification will be described below with reference to the drawings. FIG. 23 is an external perspective view of the package component 80 of the multilayer board 20g. FIG. 24A is a view of the package component 80 as viewed from above. FIG. 24B is a cross-sectional structure diagram along AA in FIG. 24A. 24C is a cross-sectional structure diagram taken along line BB in FIG. 24A.
　多層基板２０ｇは、パッケージ部品８０にスルーホール導体ｖ１２０，ｖ１２２が設けられている点において多層基板２０ｂと相違する。なお、多層基板２０ｇの断面構造図は、多層基板２０ｂの断面構造図と実質的に同じであるので、図１２を援用する。以下に、かかる相違点を中心に多層基板２０ｇについて説明する。 The multilayer substrate 20g is different from the multilayer substrate 20b in that through-hole conductors v120 and v122 are provided in the package component 80. Since the cross-sectional structure diagram of the multilayer substrate 20g is substantially the same as the cross-sectional structure diagram of the multilayer substrate 20b, FIG. 12 is used. Hereinafter, the multilayer substrate 20g will be described focusing on the difference.
　スルーホール導体ｖ１２０は、コーティング部材８６を上下方向に貫通しており、外部電極８４ａと回路導体層２８ｆとを接続している。より詳細には、スルーホール導体ｖ１２０の上端は、外部電極８４ａに接続されており、スルーホール導体ｖ１２０の下端は回路導体層２８ｆに接続されている。そして、スルーホール導体ｖ１２０は、外部電極８４ａとパッケージ部品８０の下面との間に存在するコーティング部材８６を上下方向に貫通しており、絶縁体シート２２ｅを上下方向に貫通していない。 The through-hole conductor v120 penetrates the coating member 86 in the vertical direction, and connects the external electrode 84a and the circuit conductor layer 28f. More specifically, the upper end of the through-hole conductor v120 is connected to the external electrode 84a, and the lower end of the through-hole conductor v120 is connected to the circuit conductor layer 28f. The through-hole conductor v120 penetrates the coating member 86 existing between the external electrode 84a and the lower surface of the package component 80 in the vertical direction and does not penetrate the insulator sheet 22e in the vertical direction.
　スルーホール導体ｖ１２２は、コーティング部材８６を上下方向に貫通しており、外部電極８４ｂと回路導体層２９ｆとを接続している。より詳細には、スルーホール導体ｖ１２２の上端は、外部電極８４ｂに接続されており、スルーホール導体ｖ１２２の下端は回路導体層２９ｆに接続されている。そして、スルーホール導体ｖ１２２は、外部電極８４ｂとパッケージ部品８０の下面との間に存在するコーティング部材８６を上下方向に貫通しており、絶縁体シート２２ｅを上下方向に貫通していない。 The through-hole conductor v122 penetrates the coating member 86 in the vertical direction, and connects the external electrode 84b and the circuit conductor layer 29f. More specifically, the upper end of the through-hole conductor v122 is connected to the external electrode 84b, and the lower end of the through-hole conductor v122 is connected to the circuit conductor layer 29f. The through-hole conductor v122 penetrates the coating member 86 existing between the external electrode 84b and the lower surface of the package component 80 in the vertical direction and does not penetrate the insulator sheet 22e in the vertical direction.
　以上のようなスルーホール導体ｖ１２０，ｖ１２２は、コーティング部材８６に設けられた貫通孔の内周面に銅めっきが施されることにより形成されている。そして、スルーホール導体ｖ１２０，ｖ１２２は、パッケージ部品８０が空間Ｓｐに収容される前に形成される。すなわち、パッケージ部品８０の完成後に、レーザービームによりコーティング部材８６に貫通孔を形成する。そして、貫通孔の内周面に銅めっきを施す。これにより、貫通孔から突出しない導体を形成することができるため、接続部の凹凸を抑制できる。なお、このめっきは貫通孔の内周面だけでなく内周面周囲のコーティング部材８６表面にも設けられていてもよい。この後、パッケージ部品８０を基材２２の空間Ｓｐに収容する。 The through-hole conductors v120 and v122 as described above are formed by performing copper plating on the inner peripheral surface of the through hole provided in the coating member 86. The through-hole conductors v120 and v122 are formed before the package component 80 is accommodated in the space Sp. That is, after the package component 80 is completed, a through hole is formed in the coating member 86 by a laser beam. And copper plating is given to the internal peripheral surface of a through-hole. Thereby, since the conductor which does not protrude from a through-hole can be formed, the unevenness | corrugation of a connection part can be suppressed. This plating may be provided not only on the inner peripheral surface of the through hole but also on the surface of the coating member 86 around the inner peripheral surface. Thereafter, the package component 80 is accommodated in the space Sp of the base material 22.
（その他の実施形態）
　本発明に係る多層基板及び多層基板の製造方法は、多層基板２０，２０ａ～２０ｇ及び多層基板２０，２０ａ～２０ｇの製造方法に限らず、その要旨の範囲内において変更可能である。 (Other embodiments)
The multilayer substrate and the method of manufacturing the multilayer substrate according to the present invention are not limited to the method of manufacturing the multilayer substrates 20, 20a to 20g and the multilayer substrates 20, 20a to 20g, and can be changed within the scope of the gist.
　なお、多層基板２０，２０ａ～２０ｇ及び多層基板２０，２０ａ～２０ｇの製造方法の構成を任意に組み合わせてもよい。 In addition, you may combine arbitrarily the structure of the manufacturing method of the multilayer substrate 20, 20a-20g and the multilayer substrate 20, 20a-20g.
　なお、パッケージ部品８０の側面は積層方向に平行でなくてもよい。側面は積層方向に平行ではないパッケージ部品８０の形状の例としては、例えば、四角錘台が挙げられる。また、パッケージ部品８０の側面は平面でなくてもよい。側面が平面ではないパッケージ部品８０の形状の例としては、円柱が挙げられる。 In addition, the side surface of the package component 80 may not be parallel to the stacking direction. As an example of the shape of the package component 80 whose side surfaces are not parallel to the stacking direction, for example, a square frustum is cited. Further, the side surface of the package component 80 may not be a flat surface. An example of the shape of the package component 80 whose side surface is not flat is a cylinder.
　また、パッケージ部品８０の上面及び下面は、外部電極８４ａ，８４ｂ及びコーティング部材８６により構成されていてもよい。図２５は、上面及び下面が外部電極８４ａ，８４ｂ及びコーティング部材８６により構成されているパッケージ部品８０の外観斜視図である。図２５に示すように、パッケージ部品８０の製造時の樹脂層２０２，２０３の研磨量を多くすることによって、外部電極８４ａ，８４ｂをコーティング部材８６から露出させてもよい。この場合、コーティング部材８６に貫通孔を形成することなく、外部電極８４ａ，８４ｂとビアホール導体ｖ１００，ｖ１０２とを接続したり、外部電極８４ａ，８４ｂと回路導体層２８ｆ，２９ｆとを接続したりできる。 Further, the upper surface and the lower surface of the package component 80 may be constituted by the external electrodes 84 a and 84 b and the coating member 86. FIG. 25 is an external perspective view of the package component 80 whose upper and lower surfaces are constituted by the external electrodes 84 a and 84 b and the coating member 86. As shown in FIG. 25, the external electrodes 84 a and 84 b may be exposed from the coating member 86 by increasing the polishing amount of the resin layers 202 and 203 at the time of manufacturing the package component 80. In this case, the external electrodes 84a and 84b and the via-hole conductors v100 and v102 can be connected or the external electrodes 84a and 84b and the circuit conductor layers 28f and 29f can be connected without forming a through hole in the coating member 86. .
　なお、多層基板２０，２０ａ～２０ｇは、マザー基板１００に実装されずに用いられてもよい。 The multilayer substrates 20 and 20a to 20g may be used without being mounted on the mother substrate 100.
　なお、多層基板２０ｅにおいて、ビアホール導体ｖ１００，ｖ１０２が設けられていなくてもよい。この場合には、絶縁体シート２２ａは、パッケージ部品８０の上面（第２の平面の一例）に接触している。そして、ビアホール導体ｖ１１０，ｖ１１２（接続導体の一例）は、パッケージ部品８０の上面を通過し、コーティング部材８６及び絶縁体シート２２ａを貫通している。 In the multilayer substrate 20e, the via-hole conductors v100 and v102 do not have to be provided. In this case, the insulator sheet 22a is in contact with the upper surface (an example of the second plane) of the package component 80. The via-hole conductors v110 and v112 (an example of a connection conductor) pass through the upper surface of the package component 80 and penetrate the coating member 86 and the insulator sheet 22a.
　なお、多層基板２０ａにおいて、絶縁体シート２３は、パッケージ部品８０の下面ではなく上面（第２の平面の一例）に接触していてもよい。この場合、図２１に示す多層基板２０ｅのように、絶縁体シート２２ａの上側に絶縁体シート２２ｈが更に積層される。これにより、絶縁体シート２２ａは、パッケージ部品８０の上面（第２の平面の一例）に接触している。また、絶縁体シート２２ａの表面上には、回路導体層２８ｇ，２９ｇが設けられる。そして、多層基板２０ａは、ビアホール導体ｖ１００，ｖ１０２の代わりに、ビアホール導体ｖ１１０，ｖ１１２を備えている。ビアホール導体ｖ１１０，ｖ１１２（接続導体の一例）は、パッケージ部品８０の上面を通過し、コーティング部材８６及び絶縁体シート２２ａを貫通する。そして、ビアホール導体ｖ１１０は、回路導体層２８ｇと外部電極８４ａとを接続し、ビアホール導体ｖ１１２は、回路導体層２９ｇと外部電極８４ｂとを接続する。 In the multilayer substrate 20a, the insulator sheet 23 may be in contact with the upper surface (an example of the second plane) instead of the lower surface of the package component 80. In this case, as in the multilayer substrate 20e shown in FIG. 21, the insulator sheet 22h is further laminated on the insulator sheet 22a. Thereby, the insulator sheet 22a is in contact with the upper surface (an example of the second plane) of the package component 80. In addition, circuit conductor layers 28g and 29g are provided on the surface of the insulator sheet 22a. The multilayer substrate 20a includes via-hole conductors v110 and v112 instead of the via-hole conductors v100 and v102. Via-hole conductors v110 and v112 (an example of a connection conductor) pass through the upper surface of the package component 80 and penetrate the coating member 86 and the insulator sheet 22a. The via-hole conductor v110 connects the circuit conductor layer 28g and the external electrode 84a, and the via-hole conductor v112 connects the circuit conductor layer 29g and the external electrode 84b.
　以上のように、多層基板２０，２０ｂ～２０ｄ，２０ｇにおいても、多層基板２０ａ，２０ｅと同様に、ビアホール導体ｖ１００，ｖ１０２の代わりにビアホール導体ｖ１１０，ｖ１１２（接続導体の一例）が設けられていてもよい。この場合には、絶縁体シート２２ａは、パッケージ部品８０の上面（第２の平面の一例）に接触している。そして、ビアホール導体ｖ１１０，ｖ１１２（接続導体の一例）は、パッケージ部品８０の上面を通過し、コーティング部材８６及び絶縁体シート２２ａを貫通している。 As described above, also in the multilayer substrates 20, 20b to 20d, 20g, the via-hole conductors v110, v112 (an example of connection conductors) are provided instead of the via-hole conductors v100, v102, similarly to the multilayer substrates 20a, 20e. Also good. In this case, the insulator sheet 22a is in contact with the upper surface (an example of the second plane) of the package component 80. The via-hole conductors v110 and v112 (an example of a connection conductor) pass through the upper surface of the package component 80 and penetrate the coating member 86 and the insulator sheet 22a.
　なお、多層基板２０ａにおいて、ビアホール導体ｖ１１０，ｖ１１２はそれぞれ、回路導体層２８ｅ，２９ｅに直接に接続されているが、ビアホール導体ｖ１１０，ｖ１１２とは別のビアホール導体を介して回路導体層２８ｅ，２９ｅに直接に接続されていてもよい。すなわち、ビアホール導体ｖ１１０，ｖ１１２はそれぞれ、外部電極８４ａ，８４ｂと回路導体層２８ｅ，２９ｅとを電気的に接続していればよい。 In the multilayer substrate 20a, the via-hole conductors v110 and v112 are directly connected to the circuit conductor layers 28e and 29e, respectively. However, the circuit conductor layers 28e and 29e are connected via via-hole conductors different from the via-hole conductors v110 and v112. It may be connected directly to. That is, the via-hole conductors v110 and v112 only have to electrically connect the external electrodes 84a and 84b and the circuit conductor layers 28e and 29e, respectively.
　以上のように、本発明は、多層基板及び多層基板の製造方法に有用であり、特に、基材の主面の平坦性を向上させることができる点で優れている。 As described above, the present invention is useful for a multilayer substrate and a method for producing the multilayer substrate, and is particularly excellent in that the flatness of the main surface of the base material can be improved.
１０：電子機器
２０，２０ａ～２０ｇ：多層基板
２２：基材
２２ａ～２２ｇ，２３：絶縁体シート
２８ａ～２８ｆ，２９ａ～２９ｆ：回路導体層
５０，８０，８０’：パッケージ部品
６０，７０，８１，８１’，８１’’：電子部品
６０ａ，７０ａ，８２、８２’，８２’’：本体
２４ａ～２４ｄ，２６ａ，２６ｂ，６２ａ，６２ｂ，７２ａ，７２ｂ，８４ａ，８４ａ’，８４ａ’’， ８４ｂ，８４ｂ’，８４ｂ’’：外部電極
８６：コーティング部材
Ｈ１～Ｈ３：貫通孔
Ｓｐ：空間
ｖ１～ｖ９，ｖ１１～ｖ１９，ｖ１００，ｖ１０２，ｖ１１０，ｖ１１２：ビアホール導体
ｖ５’，ｖ１００’，ｖ１０２’，ｖ１２０，ｖ１２２：スルーホール導体 10: Electronic equipment 20, 20a-20g: Multilayer substrate 22: Base materials 22a-22g, 23: Insulator sheets 28a-28f, 29a-29f: Circuit conductor layers 50, 80, 80 ': Package parts 60, 70, 81 , 81 ′, 81 ″: electronic components 60a, 70a, 82, 82 ′, 82 ″: main bodies 24a to 24d, 26a, 26b, 62a, 62b, 72a, 72b, 84a, 84a ′, 84a ″, 84b , 84b ′, 84b ″: External electrode 86: Coating members H1 to H3: Through holes Sp: Spaces v1 to v9, v11 to v19, v100, v102, v110, v112: Via hole conductors v5 ′, v100 ′, v102 ′, v120, v122: Through-hole conductor

Claims (17)

  1. 　熱可塑性樹脂である第１の樹脂を含む材料により構成されている複数の絶縁体層が積層方向に積層されて構成されている基材と、
    　前記基材に内蔵されているパッケージ部品であって、前記積層方向の両端に位置し、かつ、該積層方向に実質的に垂直な第１の平面及び第２の平面を有するパッケージ部品と、
    　を備えており、
    　前記パッケージ部品は、
    　　第１の電子部品と、
    　　第２の樹脂を含む材料により構成され、かつ、前記第１の電子部品の表面の少なくとも一部を覆っているコーティング部材と、
    　を含んでおり、
    　前記第１の樹脂の軟化点温度において、前記第２の樹脂のヤング率は、前記第１の樹脂のヤング率よりも大きく、
    　前記第１の平面の少なくとも一部及び前記第２の平面の少なくとも一部は、前記コーティング部材により構成されていること、
    　を特徴とする多層基板。     A base material constituted by laminating a plurality of insulator layers made of a material containing a first resin that is a thermoplastic resin in a laminating direction;
    A package component embedded in the base material, the package component having first and second planes positioned at both ends in the stacking direction and substantially perpendicular to the stacking direction;
    With
    The package component is:
    A first electronic component;
    A coating member made of a material containing a second resin and covering at least part of the surface of the first electronic component;
    Contains
    At the softening point temperature of the first resin, the Young's modulus of the second resin is larger than the Young's modulus of the first resin,
    At least a part of the first plane and at least a part of the second plane are constituted by the coating member;
    A multilayer board characterized by
  2. 　前記第１の電子部品は、
    　　第１の本体と、
    　　前記第１の本体の表面に設けられている第１の外部電極を、
    　有しており、
    　前記多層基板は、
    　前記絶縁体層に設けられている回路導体層と、
    　前記コーティング部材を貫通しており、前記第１の外部電極と前記回路導体層とを接続している接続導体と、
    　を更に備えていること、
    　を特徴とする請求項１に記載の多層基板。     The first electronic component is:
    A first body;
    A first external electrode provided on a surface of the first main body;
    Have
    The multilayer substrate is
    A circuit conductor layer provided on the insulator layer;
    A connecting conductor passing through the coating member and connecting the first external electrode and the circuit conductor layer;
    Further comprising
    The multilayer substrate according to claim 1.
  3. 　前記複数の絶縁体層は、前記第２の平面に接触する第１の絶縁体層を含んでおり、
    　前記接続導体は、前記第２の平面を通過し、かつ、前記コーティング部材及び前記第１の絶縁体層を貫通していること、
    　を特徴とする請求項２に記載の多層基板。     The plurality of insulator layers include a first insulator layer that contacts the second plane;
    The connection conductor passes through the second plane and passes through the coating member and the first insulator layer;
    The multilayer substrate according to claim 2.
  4. 　前記複数の絶縁体層は、前記第２の平面に接触する第２の絶縁体層を含んでおり、
    前記第１の電子部品は、
    　　第１の本体と、
    　　前記第１の本体の表面に設けられている第１の外部電極を、
    　有しており、
    　前記第２の平面は、前記コーティング部材及び前記第１の外部電極により構成されており、
    　前記多層基板は、
    　前記絶縁体層に設けられている回路導体層と、
    　前記第２の絶縁体層を前記積層方向に貫通しており、前記第１の外部電極と前記回路導体層とを電気的に接続している接続導体と、
    　を更に備えていること、
    　を特徴とする請求項１に記載の多層基板。     The plurality of insulator layers include a second insulator layer in contact with the second plane;
    The first electronic component is:
    A first body;
    A first external electrode provided on a surface of the first main body;
    Have
    The second plane is constituted by the coating member and the first external electrode,
    The multilayer substrate is
    A circuit conductor layer provided on the insulator layer;
    A connection conductor penetrating the second insulator layer in the stacking direction and electrically connecting the first external electrode and the circuit conductor layer;
    Further comprising
    The multilayer substrate according to claim 1.
  5. 　前記絶縁体層を前記積層方向に貫通する層間接続導体を、
    　更に備えており、
    　前記接続導体の材料と前記層間接続導体の材料とは同じであること、
    　を特徴とする請求項２ないし請求項４のいずれかに記載の多層基板。     An interlayer connection conductor that penetrates the insulator layer in the stacking direction,
    In addition,
    The material of the connection conductor and the material of the interlayer connection conductor are the same,
    The multilayer substrate according to any one of claims 2 to 4, wherein:
  6. 　前記第１の電子部品は、
    　　直方体状の第１の本体と、
    　　前記第１の本体において前記積層方向のいずれか一方の面上に設けられている第１の外部電極と、
    　有していること、
    　を特徴とする請求項１ないし請求項５のいずれかに記載の多層基板。     The first electronic component is:
    A rectangular parallelepiped first body;
    A first external electrode provided on any one surface in the stacking direction in the first body;
    Having
    The multilayer substrate according to any one of claims 1 to 5, wherein:
  7. 　前記積層方向に直交する方向を第１の直交方向と定義し、
    　前記積層方向及び前記第１の直交方向に直交する方向を第２の直交方向と定義し、
    　前記第１の外部電極は、前記第１の本体において、前記第１の直交方向の一方側の面の全体を覆うと共に、
    　前記第１の直交方向の一方側の面に隣接する領域であって、前記積層方向の両側の面の一部、及び、前記第２の直交方向の両側の一部の領域を覆っていること、
    　を特徴とする請求項６に記載の多層基板。     A direction orthogonal to the stacking direction is defined as a first orthogonal direction,
    A direction orthogonal to the stacking direction and the first orthogonal direction is defined as a second orthogonal direction,
    The first external electrode covers the entire surface on one side in the first orthogonal direction in the first main body,
    It is a region adjacent to one surface in the first orthogonal direction, and covers a part of both surfaces in the stacking direction and a region on both sides in the second orthogonal direction. ,
    The multilayer substrate according to claim 6.
  8. 　前記第２の樹脂の線膨張係数は、前記第１の本体の材料の線膨張係数以上、かつ、前記第１の樹脂の線膨張係数以下であること、
    　を特徴とする請求項４又は請求項７のいずれかに記載の多層基板。     The linear expansion coefficient of the second resin is not less than the linear expansion coefficient of the material of the first main body and not more than the linear expansion coefficient of the first resin;
    The multilayer substrate according to claim 4 or 7, wherein
  9. 　前記パッケージ部品は、
    　　第２の電子部品を、
    　更に含んでおり、
    　前記コーティング部材は、前記第１の電子部品及び前記第２の電子部品の表面の少なくとも一部を覆っていること、
    　を特徴とする請求項１ないし請求項８のいずれかに記載の多層基板。     The package component is:
    The second electronic component,
    In addition,
    The coating member covers at least a part of the surfaces of the first electronic component and the second electronic component;
    The multilayer substrate according to claim 1, wherein:
  10. 　前記第１の電子部品と前記第２の電子部品は、前記積層方向から見たときに重なっていること、
    　を特徴とする請求項９に記載の多層基板。     The first electronic component and the second electronic component overlap when viewed from the stacking direction;
    The multilayer substrate according to claim 9.
  11. 　前記パッケージ部品は、直方体状をなしていること、
    　を特徴とする請求項１ないし請求項１０のいずれかに記載の多層基板。     The package component has a rectangular parallelepiped shape;
    The multilayer substrate according to any one of claims 1 to 10, wherein:
  12. 　前記第２の樹脂は、熱硬化性樹脂であること、
    　を特徴とする請求項１ないし請求項１１のいずれかに記載の多層基板。     The second resin is a thermosetting resin;
    The multilayer substrate according to any one of claims 1 to 11, wherein:
  13. 　第１の電子部品の表面の少なくとも一部をコーティング部材により覆うことにより、積層方向の両端に位置し、かつ、該積層方向に実質的に垂直な第１の平面及び第２の平面を有するパッケージ部品を形成する第１の工程と、
    　前記パッケージ部品を内蔵するように複数の絶縁体層を前記積層方向に積層する第２の工程と、
    　前記複数の絶縁体層に対して加熱処理及び加圧処理を施して基材を形成する第３の工程と、
    　を備えており、
    　前記複数の絶縁体層は、熱可塑性樹脂である第１の樹脂を含む材料により構成されており、
    　前記コーティング部材は、第２の樹脂を含む材料により構成されており、
    　前記加熱処理の温度において、前記第２の樹脂のヤング率は、前記第１の樹脂のヤング率よりも大きいこと、
    　を特徴とする多層基板の製造方法。     A package having a first plane and a second plane that are located at both ends in the stacking direction and are substantially perpendicular to the stacking direction by covering at least part of the surface of the first electronic component with a coating member A first step of forming a component;
    A second step of laminating a plurality of insulator layers in the laminating direction so as to incorporate the package component;
    A third step of performing a heat treatment and a pressure treatment on the plurality of insulator layers to form a substrate;
    With
    The plurality of insulator layers are made of a material containing a first resin that is a thermoplastic resin,
    The coating member is made of a material containing a second resin,
    The Young's modulus of the second resin is greater than the Young's modulus of the first resin at the temperature of the heat treatment;
    A method for producing a multilayer substrate.
  14. 　前記第１の平面は、前記積層方向の一方側に位置し、
    　前記第２の平面は、前記積層方向の他方側に位置し、
    　前記第１の電子部品は、
    　　第１の本体と、
    　　前記第１の本体の表面に設けられている第１の外部電極を、
    　更に含んでおり、
    　前記複数の絶縁体層は、前記第２の平面に接触する第１の絶縁体層、該第１の絶縁体層よりも前記積層方向の一方側に積層される１以上の第３の絶縁体層、及び、該第１の絶縁体層よりも該積層方向の他方側に積層される第４の絶縁体層を含んでおり、
    　前記多層基板は、
    　前記第４の絶縁体層に設けられている回路導体層を、
    　更に備えており、
    　前記第３の工程は、
    　　前記第１の絶縁体層及び前記第３の絶縁体層内に前記パッケージ部品を内蔵させるように、該第１の絶縁体層及び該第３の絶縁体層を積層する第４の工程と、
    　　前記コーティング部材及び前記第１の絶縁体層を貫通する接続導体を形成する第５の工程と、
    　　前記接続導体と前記回路導体層とが接続されるように、前記第１の絶縁体層及び前記第４の絶縁体層を積層する第６の工程と、
    　を含んでいること、
    　を特徴とする請求項１３に記載の多層基板の製造方法。     The first plane is located on one side in the stacking direction,
    The second plane is located on the other side in the stacking direction,
    The first electronic component is:
    A first body;
    A first external electrode provided on a surface of the first main body;
    In addition,
    The plurality of insulator layers include a first insulator layer in contact with the second plane, and one or more third insulators stacked on one side in the stacking direction with respect to the first insulator layer. And a fourth insulator layer that is laminated on the other side in the laminating direction from the first insulator layer,
    The multilayer substrate is
    A circuit conductor layer provided on the fourth insulator layer;
    In addition,
    The third step includes
    A fourth step of laminating the first insulator layer and the third insulator layer so as to incorporate the package component in the first insulator layer and the third insulator layer;
    A fifth step of forming a connection conductor penetrating the coating member and the first insulator layer;
    A sixth step of laminating the first insulator layer and the fourth insulator layer so that the connection conductor and the circuit conductor layer are connected;
    Including
    The method for producing a multilayer substrate according to claim 13.
  15. 　前記第４の工程では、加熱処理及び加圧処理を施して、前記第１の絶縁体層及び前記第３の絶縁体層を熱圧着し、
    　前記第６の工程では、加熱処理及び加圧処理を施して、前記第１の絶縁体層及び前記第４の絶縁体層を熱圧着すること、
    　を特徴とする請求項１４に記載の多層基板の製造方法。     In the fourth step, heat treatment and pressure treatment are performed, and the first insulator layer and the third insulator layer are thermocompression bonded,
    In the sixth step, heat treatment and pressure treatment are performed, and the first insulator layer and the fourth insulator layer are thermocompression bonded,
    The method for producing a multilayer substrate according to claim 14.
  16. 　前記第１の平面は、前記積層方向の一方側に位置し、
    　前記第２の平面は、前記積層方向の他方側に位置し、
    　前記第１の電子部品は、
    　　第１の本体と、
    　　前記第１の本体の表面に設けられている第１の外部電極と、
    　を更に含んでおり、
    　前記複数の絶縁体層は、前記第２の平面に接触する第１の絶縁体層、該第１の絶縁体層よりも前記積層方向の一方側に積層される１以上の第３の絶縁体層を含んでおり、
    　前記多層基板は、
    　前記第１の絶縁体層に設けられている回路導体層を、
    　更に備えており、
    　前記第３の工程は、
    　　前記コーティング部材を貫通し、前記第１の外部電極に接続されている接続導体を形成する第７の工程、
    　　前記第１の絶縁体層及び前記第３の絶縁体層内に前記パッケージ部品を内蔵させると共に、前記接続導体が前記回路導体層に接続されるように、該第１の絶縁体層及び該第３の絶縁体層を積層する第８の工程と、
    　を含んでいること、
    　を特徴とする請求項１３に記載の多層基板の製造方法。     The first plane is located on one side in the stacking direction,
    The second plane is located on the other side in the stacking direction,
    The first electronic component is:
    A first body;
    A first external electrode provided on a surface of the first body;
    Further including
    The plurality of insulator layers include a first insulator layer in contact with the second plane, and one or more third insulators stacked on one side in the stacking direction with respect to the first insulator layer. Contains layers,
    The multilayer substrate is
    A circuit conductor layer provided on the first insulator layer;
    In addition,
    The third step includes
    A seventh step of forming a connection conductor penetrating the coating member and connected to the first external electrode;
    The package component is embedded in the first insulator layer and the third insulator layer, and the first insulator layer and the first insulator layer are connected so that the connection conductor is connected to the circuit conductor layer. An eighth step of laminating three insulator layers;
    Including
    The method for producing a multilayer substrate according to claim 13.
  17. 　前記第８の工程では、加熱処理及び加圧処理を施して、前記第１の絶縁体層及び前記第
    ３の絶縁体層を熱圧着すること、
    　を特徴とする請求項１６に記載の多層基板の製造方法。     In the eighth step, heat treatment and pressure treatment are performed, and the first insulator layer and the third insulator layer are thermocompression bonded,
    The method for producing a multilayer substrate according to claim 16.
PCT/JP2016/087171 2016-01-07 2016-12-14 Multilayer substrate and method for manufacturing multilayer substrate WO2017119249A1 (en)

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