WO2017118215A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2017118215A1
WO2017118215A1 PCT/CN2016/105455 CN2016105455W WO2017118215A1 WO 2017118215 A1 WO2017118215 A1 WO 2017118215A1 CN 2016105455 W CN2016105455 W CN 2016105455W WO 2017118215 A1 WO2017118215 A1 WO 2017118215A1
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WIPO (PCT)
Prior art keywords
display substrate
gate
driving
powered
pixel
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PCT/CN2016/105455
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English (en)
French (fr)
Inventor
张衎
张斌
董殿正
王光兴
张强
何宇
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/529,898 priority Critical patent/US10204578B2/en
Publication of WO2017118215A1 publication Critical patent/WO2017118215A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/13338—Input devices, e.g. touch panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/026—Arrangements or methods related to booting a display

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a display substrate and a display device.
  • the conventional reset circuit pulls the gate drive output voltage to a high voltage (VGH) after power-off, so that the TFT (thin film transistor) of each row of pixels is turned on for discharge.
  • VGH high voltage
  • the TFTs of all the rows cannot be simultaneously turned on at the same time, the VGH received by the pixel pixels of the latter turn-on has been attenuated, so that the discharge cannot be performed efficiently.
  • the final discharge loop is different from the discharge loop of the common electrode. Discharge through different loops causes the discharge speed of the pixel electrode to be slower than the common electrode and cause DC residual.
  • ADS Advanced Super Dimension Switch
  • Embodiments of the present invention provide a display substrate including a common electrode line and a plurality of pixel units, each of the pixel units including a pixel electrode connected to a common electrode line.
  • the display substrate further includes a plurality of first switching units. Each of the first switching units is disposed between the common electrode line and the pixel electrode, and is configured to be turned on within a preset time after the display substrate is powered off to connect the pixel electrode to the A common electrode line is disconnected when the display substrate is energized to disconnect the pixel electrode from the common electrode line.
  • the first switching unit is disposed between the data line and the common electrode line.
  • each pixel unit further includes a drive transistor.
  • the driving transistor includes a driving source, a driving drain, and a driving gate.
  • the driving source is connected to the data line
  • the driving drain is connected to the pixel electrode
  • the driving source and the driving drain are turned on within a preset time after the display substrate is powered off.
  • each of the pixel units further includes a second switching unit disposed between the driving transistor and the pixel electrode.
  • the second switch unit is configured to be turned on within a preset time after the display substrate is powered off to connect the pixel electrode to the The gate is driven and turned off when the display substrate is energized to disconnect the pixel electrode from the drive gate.
  • the display substrate further includes a gate driving integrated circuit and a third switching unit disposed between the gate driving integrated circuit and the driving transistor.
  • the gate drive integrated circuit is configured to transmit a scan signal to the drive gate when the display substrate is powered.
  • the third switching unit is configured to be turned off within a preset time after the display substrate is powered off to disconnect the gate driving integrated circuit from the driving transistor, and when the display substrate is powered on Passing to connect the gate drive integrated circuit to the drive transistor.
  • the above display substrate further includes a control unit further including an input terminal connected to the first switch unit, an input end of the second switch unit, and an input end of the third switch unit.
  • the control unit is configured to turn on the first switch unit and the second switch unit within a preset time after the display substrate is powered off, and disconnect the third switch unit, and The first switch unit and the second switch unit are disconnected when the display substrate is energized, and the third switch unit is turned on.
  • the first switching unit includes a plurality of first transistors.
  • Each of the first transistors includes a first source, a first drain, and a first gate.
  • the first source is connected to the common electrode line
  • the first drain is connected to one data line
  • each first gate is connected to the control unit.
  • control unit is configured to output a high voltage for a preset time after the display substrate is powered off, and output a low voltage when the display substrate is powered.
  • the second switching unit includes a plurality of second transistors.
  • Each of the second transistors includes a second source, a second drain, and a second gate.
  • the second source is coupled to the drive gate
  • the second drain is coupled to the drive drain
  • the second gate is coupled to the control unit.
  • the third switching unit includes a NOT gate and a plurality of third transistors.
  • the NOT gate includes an input terminal and an output terminal, and each of the third transistors includes a third source, a third drain, and a third gate.
  • An input of the NOT gate is connected to the control unit, an output of the NOT gate is respectively connected to each of the third gates, and each of the third sources is connected to the gate driving integrated circuit And each of the third drains is connected to one gate line, respectively.
  • the first switch unit and the third switch unit are disposed outside In the circuit.
  • the preset time is from 0.1 ms to 10 ms.
  • the embodiment of the invention further provides a display device comprising the above display substrate.
  • FIG. 1 shows a circuit diagram in a display substrate in accordance with one embodiment of the present invention
  • Figure 2 is a partial enlarged view of Figure 1.
  • REFERENCE SIGNS 1- common electrode line; 2-pixel unit; 20-pixel electrode; 21-first switching unit; 22-second switching unit; 23-third switching unit; 24-drive transistor; 3-data line ; 4-gate drive integrated circuit; 5-control unit; 6-data signal integrated circuit; 7-gate line.
  • a display substrate includes a common electrode line 1 and a plurality of pixel units 2.
  • Each of the pixel units 2 includes a pixel electrode 20 connected to the common electrode line 1.
  • the display substrate further includes a first switching unit 21 disposed between the common electrode line 1 and the pixel electrode 20. The first switching unit 21 is turned on for a preset time after the display substrate is powered off to connect the pixel electrode 20 to the common electrode line 1 and is turned off when the display substrate is energized to turn the pixel electrode 20 and the common electrode line 1 Disconnected.
  • the preset time is a time value set during the manufacturing process of the display substrate. In other embodiments, the preset time is a time value that is artificially modified and set during use of the product containing the display substrate. For example, the preset time is a time value between 0.1 ms and 10 ms, and the specific time value is discharged by the display substrate. Speed is determined.
  • the first switch unit can connect the pixel electrode to the common electrode line within a preset time after the display substrate is powered off, so that the charge stored in the pixel electrode of each pixel unit after the power-off is all in the common electrode line. neutralize. Thereby, the pixel electrode and the common electrode can be discharged through the same discharge loop, which ensures that there is no DC residual in the pixel electrode after discharge.
  • each pixel unit 2 further includes a drive transistor 24.
  • the drive transistor 24 includes a drive source, a drive drain, and a drive gate.
  • the driving source is connected to the data line 3, the driving drain is connected to the pixel electrode 20, and the driving source and the driving drain are turned on within a preset time after the display substrate is powered off.
  • the first switching unit 21 is disposed between the data line 3 and the common electrode line 1.
  • the charge in the pixel electrode 20 is introduced into the common electrode line 1 by controlling the driving transistor 24 to be turned on within a preset time after the display substrate is powered off.
  • the original structure of the pixel unit 2 is utilized as a connection structure between the pixel electrode 20 and the common electrode line 1, thereby reducing the adjustment of the pixel unit 2.
  • each pixel unit 2 further includes a plurality of second switching units 22.
  • Each of the second switching units 22 is disposed between each of the driving transistors 24 and each of the pixel electrodes 20.
  • the second switching unit 22 is configured to be turned on within a preset time after the display substrate is powered off to connect the pixel electrode 20 to the driving gate, and is turned off when the display substrate is energized to turn the pixel electrode 20 and the driving gate disconnect.
  • the second switching unit 22 transmits the stored charge of the pixel electrode 20 to the driving gate of the driving transistor 24 when turned on, and fully utilizes the residual charge in the pixel electrode 20 after the power-off to turn on the driving transistor. twenty four.
  • the amount of residual charge in different pixel electrodes may be different.
  • the amount of residual charge of adjacent column pixel electrodes is different.
  • the voltages of the adjacent column pixel electrodes are high level and low level, respectively, but there is no negative voltage. Therefore, when the pixel electrode is connected to the driving gate of the driving transistor, the pixel electrode can supply an opening voltage to the driving gate of the driving transistor for a period of time, so that the driving source and the driving drain of the driving transistor are turned on.
  • the above display substrate further includes a gate driving integrated circuit 4.
  • the gate drive integrated circuit 4 is configured to transmit a scan signal to a drive gate of the drive transistor 24 when the display substrate is powered.
  • the above display substrate further includes a third switching unit 23.
  • the third switching unit 23 is disposed between the gate driving integrated circuit 4 and the driving transistor 24.
  • the third switching unit 23 is turned off within a preset time after the display substrate is powered off to disconnect the gate driving integrated circuit 4 from the driving transistor 24, and is turned on when the display substrate is energized to drive the gate driving integrated circuit. 4 is connected to the drive transistor 24.
  • the second switching unit 22 turns on the driving gate and the driving drain of the driving transistor 24 within the preset time, that is, the gate line 7 and the pixel electrode 20 are turned on, and the display substrate is broken by the third switching unit 23.
  • the disconnection in the preset time after the electric discharge can prevent the electric charge in the gate driving integrated circuit 4 from flowing into the pixel electrode 20 within the predetermined time to cause damage to the pixel electrode 20.
  • the above display substrate further includes a control unit 5.
  • the control unit 5 is connected to the input of the first switching unit 21, the input of the second switching unit 22 and the input of the third switching unit 23.
  • the control unit 5 is configured to turn on the first switching unit 21 and the second switching unit 22 within a preset time after the display substrate is powered off, and to turn off the third switching unit 23, and is configured to cause the display substrate to be energized
  • the first switching unit 21 and the second switching unit 22 are turned off, and the third switching unit 23 is turned on.
  • the switching states of the first switching unit, the second switching unit, and the third switching unit can be uniformly controlled by one control unit, thereby facilitating simplification of circuit wiring.
  • the first switching unit 21 includes a plurality of first transistors.
  • Each of the first transistors includes a first source, a first drain, and a first gate.
  • Each of the first sources is connected to the common electrode line 1
  • each of the first drains is connected to one data line 3
  • each of the first gates is connected to the control unit 5, respectively.
  • the control unit 5 is configured to output a high voltage for a preset time after the display substrate is powered off, and to output a low voltage when the display substrate is energized.
  • the control unit 5 in this embodiment outputs a high voltage to the first gate of each first transistor within the preset time, so that each of the first transistors can be turned on, thereby connecting the common electrode line 1 of the first source terminal with The data line 3 of the first drain terminal is turned on, thereby turning on the common electrode line 1 and the pixel electrode 20.
  • the data line in this embodiment may be a data line between two columns of pixel units for transmitting data signals to one column of pixel units, or may be two columns between two columns of pixel units.
  • the pixel units spaced apart in the pixel unit transmit the data lines of the data signal.
  • the odd line of data lines to a column of pixel cells The prime unit transmits the data signal and transmits the data signal to the even pixel unit of the other column of pixel units.
  • the second switching unit 22 includes a plurality of second transistors.
  • Each of the second transistors includes a second source, a second drain, and a second gate.
  • Each of the second sources is coupled to a drive gate of the drive transistor 24, each second drain is coupled to a drive drain of the drive transistor 24, and each second gate is coupled to the control unit 5.
  • the control unit 5 outputs a high voltage to the gate of each of the second transistors for the preset time period such that each of the second transistors is turned on, thereby discharging the charge of the pixel electrode 20 from the driving drain of the driving transistor 24 (ie, from each The second drains of the second transistors are transferred to the second source of each of the second transistors, and further to the driving gates of the driving transistors 24 to turn on the driving transistors 24.
  • the charge of the pixel electrode of the driving drain terminal of the driving transistor 24 is introduced into the data line through the driving source, and is introduced into the common electrode line 1 through each of the first transistors.
  • each of the data lines is electrically connected to the common electrode line when the first switching unit is turned on, so that charges in each column of pixel electrodes are introduced into the common electrode line for neutralization, And the charge in the common electrode line is derived through the same circuit, which ensures that there is no DC residual in each column of pixel electrodes after discharge.
  • the third switching unit 23 includes a NOT gate and a plurality of third transistors. It should be understood that for simplicity, only one third transistor is shown in the schematic of FIG.
  • the NOT gate includes an input and an output.
  • Each of the third transistors includes a third source, a third drain, and a third gate.
  • the input terminal of the NOT gate is connected to the control unit 5, and the output terminals of the NOT gate are respectively connected to the third gate of each third transistor, and the third source of each third transistor is respectively connected to the gate drive integrated circuit 4, And the third drain of each of the third transistors is connected to one gate line 7, respectively.
  • the gate line 7 is a gate line between two rows of pixel cells for transmitting a scan signal to one of the rows of pixel cells.
  • the gate line 7 is a gate line that transmits a scan signal to pixel cells spaced apart from two rows of pixel cells between two rows of pixel cells. For example, the gate line 7 transmits a scan signal to an odd pixel unit in one row of pixel units, and transmits a scan signal to an even pixel unit in another row of pixel units.
  • the high voltage outputted by the control unit passes through the NOT gate and becomes a low voltage, thereby ensuring that the third transistor is turned off to prevent the charge in the gate driving integrated circuit from flowing into the pixel electrode within the preset time.
  • the low voltage outputted by the control unit passes through the non-gate and becomes a high voltage, thereby ensuring that the third transistor is turned on, A scan signal is normally provided for the pixel unit.
  • the third switching unit is composed of a NOT gate and a plurality of third transistors of the NPN type. In other embodiments, the third switching unit is directly composed of a plurality of third transistors of the PNP type.
  • the first switching unit 21 and the third switching unit 23 are disposed in a peripheral circuit.
  • the peripheral circuit may be a circuit disposed between the bezel and the display substrate for setting the power supply trace, the gate drive integrated circuit 4, the data signal integrated circuit 6, and the like. According to the embodiment, the occupation of the pixel area can be reduced, and the effective light-emitting area can be improved. Further, the peripheral circuit including the first switching unit 21 and the third switching unit 23 may be provided as a flexible circuit to bend the flexible circuit on the back surface of the display substrate when the display substrate is assembled into the display device, thereby reducing The occupation of the plane space. Of course, the control unit 5 can also be placed in the peripheral circuit to reduce the occupation of the pixel area.
  • the embodiment of the invention further provides a display device comprising the above display substrate.
  • the display device in this embodiment may be any product or component having a display function, such as an electronic paper, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator, and the like.
  • the common electrode line and the pixel electrode can be turned on by the first switching unit within a preset time after the display substrate is powered off, so that the charge stored in the pixel electrode after the power is off is at the common electrode. Neutralization is performed in the line so that the pixel electrode and the common electrode can be discharged through the same discharge loop, ensuring no DC residual in the pixel electrode after discharge.
  • the terms "first”, “second”, and “third” are used for descriptive purposes only, and are not to be construed as indicating or implying relative importance.
  • the term “multi” refers to greater than or equal to two unless specifically defined otherwise.

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Abstract

一种显示基板和显示装置。显示基板包括公共电极线（1）和多个像素单元（2）。每个像素单元（2）包括连接至公共电极线（1）的像素电极（20）。显示基板还包括多个第一开关单元（21）。每个第一开关单元（21）设置在公共电极线（1）和像素电极（20）之间，并且配置成在显示基板断电后的预设时间内导通，以将像素电极（20）连接至公共电极线（1），并且在显示基板通电时断开，以将像素电极（20）与公共电极线（1）断开。在显示基板断电后的预设时间内第一开关单元（21）将公共电极线（1）和像素电极（20）导通，使得断电后像素电极（20）中存储的电荷都在公共电极线（1）中进行中和。藉此，像素电极（20）和公共电极可以通过相同的放电回路放电，保证了放电后的像素电极（20）中无直流残留。

Description

显示基板和显示装置 技术领域
本发明涉及显示技术领域，具体而言涉及一种显示基板和一种显示装置。
背景技术
传统复位电路在断电后将栅极驱动输出电压全拉到高电压(VGH)，以便每行像素的TFT(薄膜晶体管)开启进行放电。但是由于所有行的TFT实际上无法同时开启，后开启的行像素接收到的VGH已经衰减，导致无法有效地进行放电。此外，像素电极的电压在中和至公共电压后，最终的放电回路与公共电极的放电回路不同。通过不同回路放电会导致像素电极的放电速度慢于公共电极而造成直流残留。对于某些ADS(Advanced Super Dimension Switch，高级超维场)产品由于液晶电容较大，像素电极放电慢，极易造成通电闪烁漂移。
发明内容
本发明实施例提出一种显示基板，包括公共电极线和多个像素单元，每个像素单元包括连接至公共电极线的像素电极。所述显示基板还包括多个第一开关单元。每个第一开关单元设置在所述公共电极线和所述像素电极之间，并且配置成在所述显示基板断电后的预设时间内导通，以将所述像素电极连接至所述公共电极线，并且在所述显示基板通电时断开，以将所述像素电极与所述公共电极线断开。
在示例性实施例中，所述第一开关单元设置在数据线与所述公共电极线之间。
在示例性实施例中，每个像素单元还包括驱动晶体管。驱动晶体管包括驱动源极、驱动漏极和驱动栅极。所述驱动源极连接至所述数据线，所述驱动漏极连接至所述像素电极，并且所述驱动源极和驱动漏极在所述显示基板断电后的预设时间内导通。
在示例性实施例中，每个像素单元还包括设置在所述驱动晶体管和所述像素电极之间的第二开关单元。所述第二开关单元配置成在所述显示基板断电后的预设时间内导通，以将所述像素电极连接至所述 驱动栅极，并且在所述显示基板通电时断开，以将所述像素电极与所述驱动栅极断开。
在示例性实施例中，上述显示基板还包括栅极驱动集成电路以及设置在所述栅极驱动集成电路和所述驱动晶体管之间的第三开关单元。所述栅极驱动集成电路配置成在所述显示基板通电时，将扫描信号传输至所述驱动栅极。所述第三开关单元配置成在所述显示基板断电后的预设时间内断开，以将所述栅极驱动集成电路与所述驱动晶体管断开，并且在所述显示基板通电时导通，以将所述栅极驱动集成电路连接至所述驱动晶体管。
在示例性实施例中，上述显示基板还包括还包括连接至所述第一开关单元的输入端、所述第二开关单元的输入端和所述第三开关单元的输入端的控制单元。所述控制单元配置成在所述显示基板断电后的预设时间内使所述第一开关单元和所述第二开关单元导通，并且使所述第三开关单元断开，以及在所述显示基板通电时使所述第一开关单元和第二开关单元断开，并且使所述第三开关单元导通。
在示例性实施例中，所述第一开关单元包括多个第一晶体管。每个第一晶体管包括第一源极、第一漏极和第一栅极。所述第一源极连接至所述公共电极线，所述第一漏极连接至一条数据线，并且每个第一栅极连接至所述控制单元。
在示例性实施例中，所述控制单元配置成在所述显示基板断电后的预设时间内输出高电压，并且在所述显示基板通电时输出低电压。
在示例性实施例中，所述第二开关单元包括多个第二晶体管。每个第二晶体管包括第二源极、第二漏极和第二栅极。所述第二源极连接至所述驱动栅极，所述第二漏极连接至所述驱动漏极，并且所述第二栅极连接至所述控制单元。
在示例性实施例中，所述第三开关单元包括一个非门和多个第三晶体管。所述非门包括输入端和输出端，并且每个第三晶体管包括第三源极、第三漏极和第三栅极。所述非门的输入端连接至所述控制单元，所述非门的输出端分别连接至每个所述第三栅极，每个所述第三源极连接至所述栅极驱动集成电路，并且每个所述第三漏极分别连接至一条栅线。
在示例性实施例中，所述第一开关单元和第三开关单元设置在外 围电路中。
在示例性实施例中，所述预设时间为0.1ms至10ms。
本发明实施例还提出一种显示装置，包括上述显示基板。
附图说明
通过参考附图会更加清楚的理解本发明的特征和优点，附图是示意性的而不应理解为对本发明进行任何限制，在附图中：
图1示出了根据本发明一个实施例的显示基板中的电路示意图；以及
图2为图1的局部放大示意图。
具体实施方式
为了能够更清楚地理解本发明的上述目的、特征和优点，下面结合附图和具体实施方式对本发明进行进一步的详细描述。需要说明的是，在不冲突的情况下，本申请的实施例及实施例中的特征可以相互组合。
在下面的描述中阐述了很多具体细节以便于充分理解本发明，但是，本发明还可以采用其他不同于在此描述的其他方式来实施。因此，本发明的保护范围并不受下面公开的具体实施例的限制。
附图标记：1-公共电极线；2-像素单元；20-像素电极；21-第一开关单元；22-第二开关单元；23-第三开关单元；24-驱动晶体管；3-数据线；4-栅极驱动集成电路；5-控制单元；6-数据信号集成电路；7-栅线。
如图1和图2所示，根据本发明一个实施例的显示基板包括公共电极线1和多个像素单元2。每个像素单元2包括连接至公共电极线1的像素电极20。显示基板还包括设置在公共电极线1和像素电极20之间的第一开关单元21。第一开关单元21在显示基板断电后的预设时间内导通，以将像素电极20连接至公共电极线1，并且在显示基板通电时断开，以将像素电极20与公共电极线1断开(disconnect)。
在一些实施例中，上述预设时间为在显示基板的制作过程中设定好的时间值。在其它实施例中，上述预设时间是在使用包含该显示基板的产品的过程中人为修改和设定的时间值。例如，该预设时间为0.1ms至10ms之间的一个时间值，并且具体时间值由显示基板的放电 速度决定。
本实施通过第一开关单元可以在显示基板断电后的预设时间内将像素电极连接至公共电极线，使得断电后每个像素单元的像素电极中存储的电荷都在公共电极线中被中和。藉此，像素电极和公共电极可以通过相同的放电回路放电，这保证了放电后的像素电极中无直流残留。
例如，如图2所示，每个像素单元2还包括驱动晶体管24。驱动晶体管24包括驱动源极、驱动漏极和驱动栅极。驱动源极连接至数据线3，驱动漏极连接至像素电极20，并且驱动源极和驱动漏极在显示基板断电后的预设时间内导通。
例如，第一开关单元21设置在数据线3与公共电极线1之间。
在本实施例中，通过控制驱动晶体管24在显示基板断电后的预设时间内导通，由此将像素电极20中的电荷导入公共电极线1。以此方式，像素单元2的原有结构作被充分利用作为像素电极20和公共电极线1之间的连接结构，从而减少对像素单元2的调整。
在示例性实施例中，每个像素单元2还包括多个第二开关单元22。每个第二开关单元22设置在每个驱动晶体管24和每个像素电极20之间。第二开关单元22配置成在显示基板断电后的预设时间内导通，以将像素电极20连接至驱动栅极，并且在显示基板通电时断开，以将像素电极20与驱动栅极断开。
在本实施例中，第二开关单元22在导通时将像素电极20的存储电荷传输至驱动晶体管24的驱动栅极，充分利用了断电后像素电极20中的残留电荷来导通驱动晶体管24。
需要说明的是，不同像素电极中残留电荷量可以不同。例如对于列反转的像素阵列，相邻列像素电极的残留电荷量不同。具体而言，相邻列像素电极的电压分别为高电平和低电平，但是并不会存在负电压。因此像素电极被连接至驱动晶体管的驱动栅极时，像素电极可在一段时间内向驱动晶体管的驱动栅极提供开启电压，使得驱动晶体管的驱动源极和驱动漏极导通。
例如，上述显示基板还包括栅极驱动集成电路4。栅极驱动集成电路4配置成在显示基板通电时将扫描信号传输到驱动晶体管24的驱动栅极。
例如，上述显示基板还包括第三开关单元23。第三开关单元23设置在栅极驱动集成电路4和驱动晶体管24之间。第三开关单元23在显示基板断电后的预设时间内断开，以将栅极驱动集成电路4与驱动晶体管24断开，并且在显示基板通电时导通，以将栅极驱动集成电路4连接至驱动晶体管24。
由于第二开关单元22在上述预设时间内导通了驱动晶体管24的驱动栅极和驱动漏极，也即导通了栅线7和像素电极20，通过第三开关单元23在显示基板断电后的预设时间内断开，可以避免栅极驱动集成电路4中的电荷在上述预设时间内流入像素电极20而对像素电极20造成的损伤。
例如，上述显示基板还包括控制单元5。控制单元5连接至第一开关单元21的输入端、第二开关单元22的输入端和第三开关单元23的输入端。控制单元5配置成在显示基板断电后的预设时间内使第一开关单元21和第二开关单元22导通，并且使第三开关单元23断开，以及配置成在显示基板通电时使第一开关单元21和第二开关单元22断开，并且使第三开关单元23导通。
本实施例通过一个控制单元可以统一控制第一开关单元、第二开关单元和第三开关单元的开关状态，便于简化电路布线。
例如，第一开关单元21包括多个第一晶体管。每个第一晶体管包括第一源极、第一漏极和第一栅极。每个第一源极连接至公共电极线1，每个第一漏极连接至一条数据线3，并且每个第一栅极分别连接至控制单元5。
控制单元5配置成在显示基板断电后的预设时间内输出高电压，并且在显示基板通电时输出低电压。
本实施例中的控制单元5在上述预设时间内向每个第一晶体管的第一栅极输出高电压，可以使得每个第一晶体管导通，从而将第一源极端的公共电极线1与第一漏极端的数据线3导通，进而将公共电极线1和像素电极20导通。
需要说明的是，本实施例中的数据线可以是位于两列像素单元之间的用于向其中一列像素单元传输数据信号的数据线，也可以是位于两列像素单元之间的向两列像素单元中间隔的像素单元传输数据信号的数据线。例如，在双栅结构中，数据线向一列像素单元中的奇数像 素单元传输数据信号，并且向另一列像素单元中的偶数像素单元传输数据信号。
例如，第二开关单元22包括多个第二晶体管。每个第二晶体管包括第二源极、第二漏极和第二栅极。每个第二源极连接至驱动晶体管24的驱动栅极，每个第二漏极连接至驱动晶体管24的驱动漏极，并且每个第二栅极连接至控制单元5。
控制单元5在上述预设时间内向每个第二晶体管的栅极输出高电压，使得每个第二晶体管导通，从而将像素电极20的电荷从驱动晶体管24的驱动漏极(即，从每个第二晶体管的第二漏极)传输至每个第二晶体管的第二源极，进而传输至驱动晶体管24的驱动栅极，以导通该驱动晶体管24。驱动晶体管24的驱动漏极端的像素电极的电荷通过驱动源极导入数据线，再通过每个第一晶体管导入公共电极线1。
由于一列像素电极连接于同一条数据线，而每条数据线在第一开关单元导通时均与公共电极线导通，从而使得每列像素电极中的电荷都导入公共电极线进行中和，并与公共电极线中的电荷通过同一回路导出，保证了放电后的每列像素电极中均无直流残留。
例如，如图2所示，第三开关单元23包括一个非门和多个第三晶体管。应理解，为了简化起见，图2的示意图中仅仅示出一个第三晶体管。非门包括输入端和输出端。每个第三晶体管包括第三源极、第三漏极和第三栅极。非门的输入端连接至控制单元5，非门的输出端分别连接至每个第三晶体管的第三栅极，每个第三晶体管的第三源极分别连接至栅极驱动集成电路4，并且每个第三晶体管的第三漏极分别连接至一条栅线7。
在一些实施例中，栅线7是位于两行像素单元之间的用于向其中一行像素单元传输扫描信号的栅线。在另一些实施例中，栅线7是位于两行像素单元之间的向两行像素单元中间隔的像素单元传输扫描信号的栅线。例如，栅线7向一行像素单元中的奇数像素单元传输扫描信号，并且向另一行像素单元中的偶数像素单元传输扫描信号。
在上述预设时间内，控制单元输出的高电压经过非门后变为低电压，从而保证第三晶体管断开，以避免栅极驱动集成电路中的电荷在上述预设时间内流入像素电极。同理，在显示基板通电后，控制单元输出的低电压经过非门后变为高电压，从而保证第三晶体管导通，以 为像素单元正常提供扫描信号。
在一些实施例中，如上所述，第三开关单元由非门与多个NPN型的第三晶体管组成。在另一些实施例中，第三开关单元直接由多个PNP型的第三晶体管组成。
例如，第一开关单元21和第三开关单元23设置在***电路中。
***电路可以是设置在边框与显示基板之间的电路，用于设置电源走线、栅极驱动集成电路4、数据信号集成电路6等。根据本实施例可以减少对像素区域的占用，提高有效发光面积。进一步地，可以将包含有第一开关单元21和第三开关单元23的***电路设置为柔性电路，以便在将显示基板组装为显示装置时，将柔性电路弯折在显示基板的背面，从而减少对平面空间的占用。当然，控制单元5也可以设置在***电路中以减少对像素区域的占用。
本发明实施例还提出一种显示装置，包括上述显示基板。
需要说明的是，本实施例中的显示装置可以为：电子纸、手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上结合附图详细说明了本发明实施例的技术方案，考虑到现有技术中，像素电极与公共电极的放电回路不同，容易在像素电极中形成直流残留。根据本发明实施例的技术方案，通过第一开关单元可以在显示基板断电后的预设时间内将公共电极线和像素电极导通，使得断电后像素电极中存储的电荷都在公共电极线中进行中和，从而使得像素电极和公共电极可以通过相同的放电回路放电，保证了放电后的像素电极中无直流残留。
在本发明实施例中，术语“第一”、“第二”和“第三”仅用于描述目的，而不能理解为指示或暗示相对重要性。术语“多”指大于或等于二，除非另有明确的限定。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (13)

  1. 一种显示基板，包括公共电极线和多个像素单元，其中每个像素单元包括连接至公共电极线的像素电极，
    其中所述显示基板还包括多个第一开关单元，每个第一开关单元设置在所述公共电极线和所述像素电极之间，并且配置成在所述显示基板断电后的预设时间内导通，以将所述像素电极连接至所述公共电极线，并且在所述显示基板通电时断开，以将所述像素电极与所述公共电极线断开。
  2. 根据权利要求1所述的显示基板，其中所述第一开关单元设置在数据线与所述公共电极线之间。
  3. 根据权利要求2所述的显示基板，其中每个像素单元还包括驱动晶体管，
    其中所述驱动晶体管包括驱动源极、驱动漏极和驱动栅极，以及
    其中所述驱动源极连接至所述数据线，所述驱动漏极连接至所述像素电极，并且所述驱动源极和驱动漏极在所述显示基板断电后的预设时间内导通。
  4. 根据权利要求3所述的显示基板，其中每个像素单元还包括设置在所述驱动晶体管和所述像素电极之间的第二开关单元，以及
    其中所述第二开关单元配置成在所述显示基板断电后的预设时间内导通，以将所述像素电极连接至所述驱动栅极，并且在所述显示基板通电时断开，以将所述像素电极与所述驱动栅极断开。
  5. 根据权利要求4所述的显示基板，还包括栅极驱动集成电路以及设置在所述栅极驱动集成电路和所述驱动晶体管之间的第三开关单元，
    其中所述栅极驱动集成电路配置成在所述显示基板通电时，将扫描信号传输到所述驱动栅极；以及
    其中所述第三开关单元配置成在所述显示基板断电后的预设时间内断开，以将所述栅极驱动集成电路与所述驱动晶体管断开，并且在所述显示基板通电时导通，以将所述栅极驱动集成电路连接至所述驱动晶体管。
  6. 根据权利要求5所述的显示基板，还包括连接至所述第一开关 单元的输入端、所述第二开关单元的输入端和所述第三开关单元的输入端的控制单元，
    其中所述控制单元配置成在所述显示基板断电后的预设时间内使所述第一开关单元和所述第二开关单元导通，并且使所述第三开关单元断开，以及在所述显示基板通电时使所述第一开关单元和第二开关单元断开，并且使所述第三开关单元导通。
  7. 根据权利要求6所述的显示基板，其中所述第一开关单元包括多个第一晶体管，并且每个第一晶体管包括第一源极、第一漏极和第一栅极，以及
    其中所述第一源极连接至所述公共电极线，所述第一漏极连接至一条数据线，并且所述第一栅极连接至所述控制单元。
  8. 根据权利要求7所述的显示基板，其中所述控制单元配置成在所述显示基板断电后的预设时间内输出高电压，并且在所述显示基板通电时输出低电压。
  9. 根据权利要求6所述的显示基板，其中所述第二开关单元包括多个第二晶体管，并且每个第二晶体管包括第二源极、第二漏极和第二栅极，以及
    其中所述第二源极连接至所述驱动栅极，所述第二漏极连接至所述驱动漏极，并且所述第二栅极连接至所述控制单元。
  10. 根据权利要求6所述的显示基板，其中所述第三开关单元包括一个非门和多个第三晶体管，所述非门包括输入端和输出端，并且每个第三晶体管包括第三源极、第三漏极和第三栅极，以及
    其中所述非门的输入端连接至所述控制单元，所述非门的输出端分别连接至每个所述第三栅极，每个所述第三源极连接至所述栅极驱动集成电路，并且每个所述第三漏极分别连接至一条栅线。
  11. 根据权利要求5至10中任意一项所述的显示基板，其中所述第一开关单元和第三开关单元设置在***电路中。
  12. 根据权利要求1至10中任意一项所述的显示基板，其中所述预设时间为0.1ms至10ms。
  13. 一种显示装置，包括权利要求1至12中任意一项所述的显示基板。
PCT/CN2016/105455 2016-01-05 2016-11-11 显示基板和显示装置 WO2017118215A1 (zh)

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