WO2017113333A1 - Fpga circuit and method for processing configuration file thereof - Google Patents

Fpga circuit and method for processing configuration file thereof Download PDF

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Publication number
WO2017113333A1
WO2017113333A1 PCT/CN2015/100196 CN2015100196W WO2017113333A1 WO 2017113333 A1 WO2017113333 A1 WO 2017113333A1 CN 2015100196 W CN2015100196 W CN 2015100196W WO 2017113333 A1 WO2017113333 A1 WO 2017113333A1
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configuration file
ecc
configuration
crc
error
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PCT/CN2015/100196
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French (fr)
Chinese (zh)
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何轲
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京微雅格（北京）科技有限公司
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Priority to PCT/CN2015/100196 priority Critical patent/WO2017113333A1/en
Priority to CN201580001647.9A priority patent/CN107710325A/en
Publication of WO2017113333A1 publication Critical patent/WO2017113333A1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation

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  • the present invention relates to an integrated circuit, and more particularly to an FPGA circuit and a method of processing the same.
  • Aerospace-class large-scale FPGAs are based on SRAM type. SRAM type FPGAs must be readback by configuration file readback when applied to high reliability requirements, but their internal registers are susceptible to single instance effects. error. Therefore, research on anti-single-particle effects for large-scale FPGAs is very important and urgent.
  • an embodiment of the present invention provides an FPGA circuit.
  • the circuit includes a configuration memory for storing an FPGA configuration file, the configuration file includes configuration data and an ECC code and a CRC code, a hardware ECC decoder, and an error correction and error detection of the configuration data by using an ECC code; a hardware CRC decoder, utilizing The CRC code corrects the configuration data; the single-event flip controller is used to read back the configuration file, and uses the hardware ECC decoder and the hardware CRC decoder to check and correct the readback configuration file, and record the configuration file error.
  • Status information; according to the hardware CRC, ECC decoder detection status, generate corresponding control, and can send an error signal to the system level application, request to reconfigure the FPGA file.
  • the single-event flip controller reads the configuration file in blocks from the configuration memory and transmits them to the CRC decoder to check the configuration file; when the check is in error, the single-event flip controller transmits the faulty configuration file to the ECC decoding. ECC detection or error correction in the device; configuration file has passed ECC After detection or error correction, it is written back to the configuration memory; the single-event flip-flop controller retransmits the profile file that was detected or missed by the ECC to the CRC decoder for CRC detection.
  • the single-event inversion controller reads the configuration file in groups from the configuration memory, and performs ECC detection or error correction in the ECC decoder; each group of configuration files are written back to the ECC detection or error correction.
  • the single-event flip controller reads and transmits the configuration file of the block to the CRC module for verification.
  • the ECC code can be a Hamming, BCH, RS code or other form of encoding.
  • the configuration file has a block structure, each configuration block comprising a plurality of sets of data and ECC encoded check bits; each of the sets of data has a CRC encoded check bit.
  • an embodiment of the present invention provides a configuration file processing method for an FPGA circuit.
  • the method includes: reading a configuration file by a block from a configuration memory, performing a CRC check on the configuration file; and performing an error when checking for an error.
  • the configuration file performs ECC detection or error correction; after the configuration file performs ECC detection or error correction, it is written back to the configuration memory; the configuration file block that is detected or missed by the ECC is again subjected to CRC detection.
  • an embodiment of the present invention provides a configuration file processing method for an FPGA circuit, which includes: reading a configuration file by group from a configuration memory, performing ECC detection or error correction; each group of configuration files has passed After the ECC detects or corrects the error, it is written back to the configuration file of the own block; when the last set of data of the block is written back to the configuration memory, the configuration file of the block is read and transmitted to the CRC module. Check it out.
  • Figure 1 is a configuration file structure with ECC and CRC check code
  • FIG. 2 illustrates an FPGA with ECC error correction and CRC check functionality in accordance with a first embodiment of the present invention. chip
  • FIG. 3 illustrates an FPGA chip with ECC error correction and CRC check functionality in accordance with a second embodiment of the present invention
  • FIG. 4 illustrates the FPGA design and download process with ECC and CRC checksums
  • Figure 5 is another configuration file structure with BCH or RS encoding function
  • FIG. 6 illustrates an FPGA chip with ECC error correction and CRC check functionality in accordance with a third embodiment of the present invention
  • FIG. 7 illustrates an FPGA chip with ECC error correction and CRC check function according to a fourth embodiment of the present invention
  • Figure 8 illustrates the FPGA design and download process with BCH or RS encoding.
  • the embodiment of the invention adds a configuration structure of the CRC and the ECC code in the FPGA configuration file, and the FPGA device performs the readback, check and error correction of the FPGA configuration file based on the CRC and the ECC code during the running process.
  • Figure 1 depicts a configuration file structure with ECC and CRC checksums.
  • each group data Data corresponds to each configuration memory chain, and each configuration memory chain has an ECC-encoded parity bit; each of the plurality of configuration memory chains has a CRC-encoded parity bit, which constitutes a Configure the block structure.
  • the configuration file of the entire configuration FPGA chip contains several such block-like block structures, that is, the configuration file (bitstream, ie bitstream) of the entire FPGA contains CRC-encoded parity bits of multiple blocks.
  • the FPGA chip includes a configuration memory, a hardware ECC (Error Correcting Code) decoder, a hardware CRC (Cyclic Redundancy Check) decoder, and Single event upset (hereinafter referred to as SEU) controller.
  • ECC Error Correcting Code
  • CRC Cyclic Redundancy Check
  • SEU Single event upset
  • the configuration memory can store an FPGA configuration file as shown in Figure 1.
  • Profiles are binary files that customize the functionality of the FPGA device to control the internal logic of the FPGA, internal registers and I/O register initialization, I/O driver enable, and more.
  • the user describes the required functionality in graphics or language, and the development system turns it into the final configuration file.
  • the FPGA uses SRAM cells to store configuration files.
  • SRAMs in FPGAs are volatile, especially in aerospace and other fields where single-particle effects affect the FPGA chip and cause errors.
  • the configuration file must be re-downloaded to the FPGA before each power-up. It is also necessary to read back the configuration file for checking and correcting errors during the running process.
  • the configuration file is pre-combined with an ECC code and a CRC code to perform ECC error correction and CRC check on the configuration file during writing or reading back.
  • the ECC decoder detects and corrects the readback configuration data based on the ECC code in the configuration file.
  • the ECC code has, for example, a Hamming code and its improvement code.
  • the principle of ECC code decoding is to add some redundant codes in the configuration file to establish a certain relationship between these data source codes and redundant codes according to certain rules. Once read back, the configuration file is for some reason (for example, single event effect). When some errors occur, the relationship between the data source code and the check code is destroyed, and an illegal code is formed.
  • the ECC decoding mode has the ability to correct single bit flips and detect multi-bit flips.
  • the CRC decoder performs a corresponding CRC check check on the readback configuration data based on the CRC code in the configuration file, and then transmits the CRC check result to the single particle controller.
  • the CRC code has only error correction function and no error detection function.
  • the SEU controller is used to perform readback, inspection and error correction of the FPGA configuration file during operation.
  • the SEU controller can include an FPGA profile readback controller, a state detection controller, and an FPGA configuration file written back to the controller.
  • the FPGA configuration file is read back to the controller to control the configuration file block or group read operation and the corresponding address
  • the status detection controller records the error information
  • the FPGA configuration file is written back to the controller to control the write operation of the configuration file block or group and the corresponding address.
  • the SEU controller reads a block's configuration file from the configuration memory and transfers it to the CRC decoder for a profile check of the block (see Figure 1). If no error is detected, The result is fed back to the SEU controller, which will check the configuration file for the next block.
  • the SEU controller will transmit the configuration file of the erroneous block, one by one, to the ECC decoder for ECC decoding detection or error correction. (See icon 2).
  • the SEU controller transmits the profile file that was detected or missed by the ECC to the CRC decoder for CRC detection.
  • no error occurs in the CRC detection, indicating that the erroneous configuration file block has been successfully corrected by the ECC hardware, and a request is sent to the SEU controller (see icon 4) to perform the same detection on the next configuration file block;
  • the CRC still detects that an error has occurred, indicating that the erroneous configuration file block has exceeded the error correction capability of the ECC code, the error has been miscorrected, and there is no real problem to solve the error.
  • the status result is sent to the SEU controller ( See icon 4), the controller will issue a corresponding request to the system level based on this result.
  • SRAM-based FPGA devices can perform the process of reading back, checking, and correcting FPGA configuration files during operation.
  • the configuration architecture adds a Cyclic Redundancy Check (CRC). Ensure that each FPGA configuration file is correct by using a combination of CRC and ECC.
  • CRC Cyclic Redundancy Check
  • Figure 3 depicts an architecture for error correction of a configuration file in accordance with a second embodiment of the present invention.
  • this mode of operation is that each group performs ECC check and error correction one by one, and then through the CRC to check whether the configuration file is successfully corrected, so the implementation speed will be slower than that proposed in Figure 2.
  • Operating mode is that each group performs ECC check and error correction one by one, and then through the CRC to check whether the configuration file is successfully corrected, so the implementation speed will be slower than that proposed in Figure 2.
  • the SEU controller reads the configuration file of the first group of a block from the configuration memory, and performs detection or error correction of the decoding in the ECC decoder.
  • the SEU controller issues an instruction to read and transfer the configuration file for that block to the CRC module for verification.
  • the CRC detection error occurs, it indicates that the error configuration file block has exceeded the error correction capability range of the ECC code, the error is miscorrected, and there is no real problem to solve the error. At this time, the status result is sent to the SEU controller. Based on this result, a corresponding request will be sent to the system level.
  • FIG 4 shows the FPGA design and download flow chart with ECC and CRC check functions.
  • the FPGA design flow generally includes circuit design and input, functional simulation, synthesis, integrated simulation, and implementation.
  • design inputs such as the HDL language are translated into logical connections (net tables) consisting of basic logical units such as AND, OR, NOT, RAM, and registers, and the speed and area are logically optimized according to design constraints.
  • the integrated network logic netlist is adapted to the FPGA device based on the model of the selected chip.
  • the check codes of the ECC and the CRC corresponding thereto are added according to the information of the block and the group of the configuration file.
  • the configuration file of the ECC and CRC check code is added and downloaded to the configuration chip based on, for example, the JTAG configuration.
  • the FPGA After the FPGA is powered on, it first enters the configuration mode. After the last configuration data is loaded into the FPGA, it enters the initialization mode (initialization) and enters the user mode (user-mode) after the initialization is completed. In configuration mode and initialization mode, the user I/O of the FPGA is in a high-impedance state (or internal weak pull-up state). When entering user mode, the user I/O works according to the user-designed function.
  • the foregoing embodiment of the present invention has been described in connection with a Hamming code which is characterized by error correction of one bit and detection of two bits.
  • the invention is not limited thereto, and can also be extended to an error correctable multi-bit coding scheme such as BCH, RS or other error correction coding.
  • BCH code is a multi-stage, loop, error correction, variable length digital code for correcting multiple random error modes.
  • RS (Reed-Solomon) code is a special type of non-binary BCH code with strong error correction capability.
  • FIG. 5-8 illustrate a configuration file structure, an FPGA chip structure, and an FPGA design and download process of an embodiment of the present invention using a BCH or RS check code.
  • the difference from the case of Figures 1 - 4 is that the encoding is different. Other content is basically the same and will not be repeated.
  • BCH Bit-Ray-Hocquenghem code
  • RS Random-solomon code

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Abstract

An FPGA circuit, comprising: a configuration memory for storing an FPGA configuration file, wherein the configuration file comprises configuration data, an ECC code and a CRC code; a hardware ECC decoder for performing error correction and error detection on the configuration data by using the ECC code; a hardware CRC decoder for performing error correction on the configuration data by using the CRC code; and a single event upset controller for reading back the configuration file, performing detection and error correction on the readback configuration file by using the hardware ECC decoder and the hardware CRC decoder, recording an error state and information about the configuration file, generating corresponding control according to the detection states of the hardware ECC and CRC decoders, sending an error signal to a system-level application, and requesting to reconfigure the FPGA configuration file. By using the circuit, the capability of an FPGA for supporting single event upset can be enhanced, so that the FPGA can be applied to space navigation and aviation or other fields relatively sensitive to an error of a device.

Description

一种FPGA电路和其配置文件处理方法FPGA circuit and its configuration file processing method 技术领域Technical field
本发明涉及一种集成电路，特别涉及FPGA电路和其配置文件处理方法。The present invention relates to an integrated circuit, and more particularly to an FPGA circuit and a method of processing the same.
背景技术Background technique
随着技术的进步，对星载信号处理能力的要求越来越高，FPGA也越来越多地应用到航天领域，成为星载信号处理和控制的关键部件。目前，从FPGA在星载型号产品中的使用情况来看，单粒子效应成为了影响大规模FPGA可用性和可靠性的主要因素。With the advancement of technology, the requirements for on-board signal processing capabilities are getting higher and higher, and FPGAs are increasingly being applied to the aerospace field, becoming a key component of on-board signal processing and control. At present, from the use of FPGAs in spaceborne models, single-event effects have become a major factor affecting the availability and reliability of large-scale FPGAs.
宇航级大规模FPGA都是基于SRAM型，SRAM型FPGA在应用于可靠性有较高要求的场合时必须通过配置文件回读的方式进行检错，但是其内部寄存器易受单例子效应影响而产生错误。因此，针对大规模FPGA进行抗单粒子效应的研究非常重要且迫切。Aerospace-class large-scale FPGAs are based on SRAM type. SRAM type FPGAs must be readback by configuration file readback when applied to high reliability requirements, but their internal registers are susceptible to single instance effects. error. Therefore, research on anti-single-particle effects for large-scale FPGAs is very important and urgent.
发明内容Summary of the invention
在第一方面，本发明实施例提供一种FPGA电路。该电路包括配置存储器，用于存储有FPGA配置文件，配置文件包括配置数据和ECC码和CRC码；硬件ECC解码器，利用ECC码对配置数据进行纠错和检错；硬件CRC解码器，利用CRC码对配置数据进行纠错；单粒子翻转控制器，用于回读配置文件，并且利用硬件ECC解码器和硬件CRC解码器对回读的配置文件进行检查和纠错，记录配置文件的出错状态、信息；根据硬件CRC、ECC解码器的检测状态，产生相应的控制，并可向***级应用发出出错信号，请求重新配置FPGA文件。In a first aspect, an embodiment of the present invention provides an FPGA circuit. The circuit includes a configuration memory for storing an FPGA configuration file, the configuration file includes configuration data and an ECC code and a CRC code, a hardware ECC decoder, and an error correction and error detection of the configuration data by using an ECC code; a hardware CRC decoder, utilizing The CRC code corrects the configuration data; the single-event flip controller is used to read back the configuration file, and uses the hardware ECC decoder and the hardware CRC decoder to check and correct the readback configuration file, and record the configuration file error. Status, information; according to the hardware CRC, ECC decoder detection status, generate corresponding control, and can send an error signal to the system level application, request to reconfigure the FPGA file.
优选地，单粒子翻转控制器从配置存储器中按块读取配置文件，传输到CRC解码器中对配置文件进行检查；在检查出错时，单粒子翻转控制器将出错的配置文件传输到ECC解码器中进行ECC检测或纠错；配置文件进过ECC 检测或纠错后，被写回到配置存储器中；单粒子翻转控制器将被ECC检测或纠错过的配置文件块再次传输到CRC解码器中进行CRC检测。Preferably, the single-event flip controller reads the configuration file in blocks from the configuration memory and transmits them to the CRC decoder to check the configuration file; when the check is in error, the single-event flip controller transmits the faulty configuration file to the ECC decoding. ECC detection or error correction in the device; configuration file has passed ECC After detection or error correction, it is written back to the configuration memory; the single-event flip-flop controller retransmits the profile file that was detected or missed by the ECC to the CRC decoder for CRC detection.
优选地，单粒子翻转控制器从配置存储器中按组读取配置文件，ECC解码器中进行ECC检测或纠错；每一组的配置文件进过ECC检测或纠错后，被写回到所属块的配置文件中；当这个块的最后一组数据被写回到配置存储器中时，单粒子翻转控制器将这一个块的配置文件读出并传输到CRC模块中进行校验。Preferably, the single-event inversion controller reads the configuration file in groups from the configuration memory, and performs ECC detection or error correction in the ECC decoder; each group of configuration files are written back to the ECC detection or error correction. In the configuration file of the block; when the last set of data of this block is written back to the configuration memory, the single-event flip controller reads and transmits the configuration file of the block to the CRC module for verification.
ECC码可以是汉明、BCH、RS码或其它形式的编码。The ECC code can be a Hamming, BCH, RS code or other form of encoding.
优选地，配置文件具有块结构，每个配置块包括多组数据和ECC编码的校验位；每若干组数据有一个CRC编码的校验位。Preferably, the configuration file has a block structure, each configuration block comprising a plurality of sets of data and ECC encoded check bits; each of the sets of data has a CRC encoded check bit.
在第二方面，本发明实施例提供一种FPGA电路的配置文件处理方法，该方法包括：从配置存储器中按块读取配置文件，对配置文件进行CRC检查；在检查出错时，将出错的配置文件进行ECC检测或纠错；配置文件进行ECC检测或纠错后，被写回到配置存储器中；将被ECC检测或纠错过的配置文件块再次进行CRC检测。In a second aspect, an embodiment of the present invention provides a configuration file processing method for an FPGA circuit. The method includes: reading a configuration file by a block from a configuration memory, performing a CRC check on the configuration file; and performing an error when checking for an error. The configuration file performs ECC detection or error correction; after the configuration file performs ECC detection or error correction, it is written back to the configuration memory; the configuration file block that is detected or missed by the ECC is again subjected to CRC detection.
在第三方面，本发明实施例提供一种FPGA电路的配置文件处理方法，该方法包括：从配置存储器中按组读取配置文件，进行ECC检测或纠错；每一组的配置文件进过ECC检测或纠错后，被写回到所属块的配置文件中；当这个块的最后一组数据被写回到配置存储器中时，将这一个块的配置文件读出并传输到CRC模块中进行校验。In a third aspect, an embodiment of the present invention provides a configuration file processing method for an FPGA circuit, which includes: reading a configuration file by group from a configuration memory, performing ECC detection or error correction; each group of configuration files has passed After the ECC detects or corrects the error, it is written back to the configuration file of the own block; when the last set of data of the block is written back to the configuration memory, the configuration file of the block is read and transmitted to the CRC module. Check it out.
通过使用CRC和ECC相结合的架构，可使FPGA支持单粒子翻转的能力得到大大的增强，从而使FPGA可以应用到宇航、航空或其他对设备出错比较敏感的领域，因此具有广泛和重大的意义。By using a combination of CRC and ECC architecture, the ability of FPGAs to support single-event ups can be greatly enhanced, making FPGAs applicable to aerospace, aerospace or other areas that are sensitive to equipment errors, and therefore have broad and significant implications. .
附图说明DRAWINGS
图1是带有ECC和CRC校验码的一种配置文件结构；Figure 1 is a configuration file structure with ECC and CRC check code;
图2示意了根据本发明第一实施例的带有ECC纠错和CRC校验功能的FPGA 芯片；2 illustrates an FPGA with ECC error correction and CRC check functionality in accordance with a first embodiment of the present invention. chip;
图3示意了根据本发明第二实施例的带有ECC纠错和CRC校验功能的FPGA芯片；3 illustrates an FPGA chip with ECC error correction and CRC check functionality in accordance with a second embodiment of the present invention;
图4示意了带有ECC和CRC校验功能的FPGA设计及下载流程；Figure 4 illustrates the FPGA design and download process with ECC and CRC checksums;
图5是带有BCH或RS编码功能的另一种配置文件结构；Figure 5 is another configuration file structure with BCH or RS encoding function;
图6示意了根据本发明第三实施例的带有ECC纠错和CRC校验功能的FPGA芯片；6 illustrates an FPGA chip with ECC error correction and CRC check functionality in accordance with a third embodiment of the present invention;
图7示意了根据本发明第四实施例的带有ECC纠错和CRC校验功能的FPGA芯片；FIG. 7 illustrates an FPGA chip with ECC error correction and CRC check function according to a fourth embodiment of the present invention; FIG.
图8示意了带有BCH或RS编码功能的FPGA设计及下载流程。Figure 8 illustrates the FPGA design and download process with BCH or RS encoding.
具体实施方式detailed description
下面通过附图和实施例，对本发明的技术方案做进一步的详细描述。The technical solution of the present invention will be further described in detail below through the accompanying drawings and embodiments.
本发明实施例在FPGA配置文件中添加CRC和ECC码的配置架构，并且FPGA器件在运行过程中基于CRC和ECC码执行FPGA配置文件的回读、检查并纠错。通过使用该架构，可使FPGA支持单粒子翻转的能力得到大大的增强。The embodiment of the invention adds a configuration structure of the CRC and the ECC code in the FPGA configuration file, and the FPGA device performs the readback, check and error correction of the FPGA configuration file based on the CRC and the ECC code during the running process. By using this architecture, the ability of the FPGA to support single-event flipping is greatly enhanced.
图1描述了带有ECC和CRC校验码的一种配置文件结构。在图1中，每一个组数据Data对应了每一条配置存储器链，每一条配置存储器链有一个ECC编码的校验位；每若干条配置存储器链有一个CRC编码的校验位，组成了一个配置块(block)结构。整个配置FPGA芯片的配置文件包含了若干个这样的块状block结构，即整个FPGA的配置文件(比特流，即bitstream)含有多个块的CRC编码的校验位。Figure 1 depicts a configuration file structure with ECC and CRC checksums. In FIG. 1, each group data Data corresponds to each configuration memory chain, and each configuration memory chain has an ECC-encoded parity bit; each of the plurality of configuration memory chains has a CRC-encoded parity bit, which constitutes a Configure the block structure. The configuration file of the entire configuration FPGA chip contains several such block-like block structures, that is, the configuration file (bitstream, ie bitstream) of the entire FPGA contains CRC-encoded parity bits of multiple blocks.
图2是本发明第一实施例的FPGA芯片原理示意图。如图2所示，FPGA芯片包括配置存储器、硬件ECC(Error Correcting Code，即错误检查和纠正)解码器、硬件CRC(Cyclic Redundancy Check，循环冗余校验码)解码器和 单粒子翻转(single event upset,下文简称SEU)控制器。2 is a schematic diagram of the principle of an FPGA chip according to a first embodiment of the present invention. As shown in FIG. 2, the FPGA chip includes a configuration memory, a hardware ECC (Error Correcting Code) decoder, a hardware CRC (Cyclic Redundancy Check) decoder, and Single event upset (hereinafter referred to as SEU) controller.
配置存储器可以存储有如图1所示的FPGA配置文件。配置文件是定制FPGA器件功能的二进制文件，用于控制FPGA内部可编程的内部逻辑、内部寄存器和I/O寄存器初始化，I/O驱动器使能等。用户用图形或者语言描述所需要的功能，开发***把它转成最后的配置文件。在一个例子中，FPGA使用SRAM单元来存储配置文件，通常FPGA中的SRAM是易失的，尤其在航天等领域中受单粒子效应影响FPGA芯片而产生错误。每次上电之前，配置文件必须重新下载到FPGA中。在运行过程中也有必要回读配置文件进行检查并纠错。为此，配置文件中除配置数据外，还预先结合有ECC码和CRC码，以便在写入或回读过程中对配置文件进行ECC纠错和CRC校验。The configuration memory can store an FPGA configuration file as shown in Figure 1. Profiles are binary files that customize the functionality of the FPGA device to control the internal logic of the FPGA, internal registers and I/O register initialization, I/O driver enable, and more. The user describes the required functionality in graphics or language, and the development system turns it into the final configuration file. In one example, the FPGA uses SRAM cells to store configuration files. Typically, SRAMs in FPGAs are volatile, especially in aerospace and other fields where single-particle effects affect the FPGA chip and cause errors. The configuration file must be re-downloaded to the FPGA before each power-up. It is also necessary to read back the configuration file for checking and correcting errors during the running process. To this end, in addition to the configuration data, the configuration file is pre-combined with an ECC code and a CRC code to perform ECC error correction and CRC check on the configuration file during writing or reading back.
ECC解码器基于配置文件中的ECC码，对回读的配置数据检测和纠错。ECC码例如有汉明码及其改进码。ECC码解码的原理是在配置文件中加入一些冗余码，使这些数据源码与冗余码之间根据某种规则建立一定的关系，一旦回读时配置文件因为某种原因(例如单粒子效应)而出现某些错误时，数据源码与检验码之间的关系被破坏，就形成非法编码。ECC解码方式具有纠正单比特翻转和检测多比特翻转的能力。The ECC decoder detects and corrects the readback configuration data based on the ECC code in the configuration file. The ECC code has, for example, a Hamming code and its improvement code. The principle of ECC code decoding is to add some redundant codes in the configuration file to establish a certain relationship between these data source codes and redundant codes according to certain rules. Once read back, the configuration file is for some reason (for example, single event effect). When some errors occur, the relationship between the data source code and the check code is destroyed, and an illegal code is formed. The ECC decoding mode has the ability to correct single bit flips and detect multi-bit flips.
CRC解码器基于配置文件中的CRC码对回读的配置数据执行相应的CRC校验检查，然后将CRC校验结果发送给单粒子控制器。CRC编码只有纠错功能，无检错功能。The CRC decoder performs a corresponding CRC check check on the readback configuration data based on the CRC code in the configuration file, and then transmits the CRC check result to the single particle controller. The CRC code has only error correction function and no error detection function.
SEU控制器用于在运行过程中执行FPGA配置文件的回读、检查并纠错。在一个例子中，SEU控制器可以包括FPGA配置文件回读控制器，状态检测控制器和FPGA配置文件写回控制器。FPGA配置文件回读控制器控制配置文件块或组读操作和相应的地址，状态检测控制器记录出错信息，FPGA配置文件写回控制器控制配置文件块或组的写操作和相应的地址等。The SEU controller is used to perform readback, inspection and error correction of the FPGA configuration file during operation. In one example, the SEU controller can include an FPGA profile readback controller, a state detection controller, and an FPGA configuration file written back to the controller. The FPGA configuration file is read back to the controller to control the configuration file block or group read operation and the corresponding address, the status detection controller records the error information, and the FPGA configuration file is written back to the controller to control the write operation of the configuration file block or group and the corresponding address.
在操作中，SEU控制器从配置存储器中读取一个块的配置文件，传输到CRC解码器中进行对这个块的配置文件检查(参见图标1)。如未检测到错误， 将结果反馈给SEU控制器，控制器将会对下一个块的配置文件进行检查。In operation, the SEU controller reads a block's configuration file from the configuration memory and transfers it to the CRC decoder for a profile check of the block (see Figure 1). If no error is detected, The result is fed back to the SEU controller, which will check the configuration file for the next block.
如发生错误，则表明这一个块的配置文件中有错，那么SEU控制器会将这个出错的块的配置文件，一组接一组的传输到ECC解码器中进行ECC解码的检测或纠错(参见图标2)。If an error occurs, it indicates that there is an error in the configuration file of this block, then the SEU controller will transmit the configuration file of the erroneous block, one by one, to the ECC decoder for ECC decoding detection or error correction. (See icon 2).
每一组的配置文件进过ECC解码的检测或纠错后，被写回到这个块的配置文件中(参见图标3)。After each set of configuration files has been detected or corrected by ECC decoding, it is written back to the configuration file of this block (see Figure 3).
SEU控制器将被ECC检测或纠错过的配置文件块再次传输到CRC解码器中进行CRC检测。如此时CRC检测无错误发生，则表明这个出错的配置文件块已经被ECC硬件成功纠错了，向SEU控制器发出请求(参见图标4)，对下一个配置文件块进行同样的检测；如此时CRC依然检测有错误发生，则表明这个出错的配置文件块已经超出了ECC编码的纠错能力范围，错误被误纠了，没有真正的解决出错问题，这时会向SEU控制器发出状态结果(参见图标4)，控制器会根据这一结果向***级发出相应的请求。The SEU controller transmits the profile file that was detected or missed by the ECC to the CRC decoder for CRC detection. In this case, no error occurs in the CRC detection, indicating that the erroneous configuration file block has been successfully corrected by the ECC hardware, and a request is sent to the SEU controller (see icon 4) to perform the same detection on the next configuration file block; The CRC still detects that an error has occurred, indicating that the erroneous configuration file block has exceeded the error correction capability of the ECC code, the error has been miscorrected, and there is no real problem to solve the error. At this time, the status result is sent to the SEU controller ( See icon 4), the controller will issue a corresponding request to the system level based on this result.
通过使用这种新型的FPGA配置架构，可使基于SRAM的FPGA器件在运行过程中一直执行FPGA配置文件的回读、检查并纠错的过程。由于ECC编解码的纠错能力的局限性，该配置架构增加了循环冗余校验码(Cyclic Redundancy Check CRC)。通过使用CRC和ECC相结合的方式，确保每一块FPGA配置文件都是正确的。通过使用该架构，可使FPGA支持单粒子翻转的能力得到大大的增强，从而使FPGA可以应用到宇航、航空或其他对设备出错比较敏感的领域，因此具有广泛和重大的意义。By using this new FPGA configuration architecture, SRAM-based FPGA devices can perform the process of reading back, checking, and correcting FPGA configuration files during operation. Due to the limitations of the error correction capability of the ECC codec, the configuration architecture adds a Cyclic Redundancy Check (CRC). Ensure that each FPGA configuration file is correct by using a combination of CRC and ECC. By using this architecture, the ability of the FPGA to support single-event ups can be greatly enhanced, making FPGAs applicable to aerospace, aerospace or other areas that are sensitive to equipment errors, and therefore have broad and significant implications.
图3描述了本发明第二实施例的对配置文件纠错的架构。和图2相比，这种工作模式是每一组逐个的进行ECC检验和纠错，然后再经过CRC检测配置文件是否真正被纠错成功，因此在实现速度上会慢于图2所提出的工作模式。Figure 3 depicts an architecture for error correction of a configuration file in accordance with a second embodiment of the present invention. Compared with Figure 2, this mode of operation is that each group performs ECC check and error correction one by one, and then through the CRC to check whether the configuration file is successfully corrected, so the implementation speed will be slower than that proposed in Figure 2. Operating mode.
在操作中，SEU控制器从配置存储器中读取某一个块的第一个组的配置文件，ECC解码器中进行解码的检测或纠错。 In operation, the SEU controller reads the configuration file of the first group of a block from the configuration memory, and performs detection or error correction of the decoding in the ECC decoder.
每一组的配置文件进过ECC解码的检测或纠错后，被写回到这个块的配置文件中。After each set of configuration files has been detected or corrected by ECC decoding, it is written back to the configuration file of this block.
当这个块的最后一组数据被写回到配置存储器中时，SEU控制器会发出指令将这一个块的配置文件读出并传输到CRC模块中进行校验。When the last set of data for this block is written back to the configuration memory, the SEU controller issues an instruction to read and transfer the configuration file for that block to the CRC module for verification.
若CRC检测出错，则表明这个出错的配置文件块已经超出了ECC编码的纠错能力范围，错误被误纠了，没有真正的解决出错问题，这时会向SEU控制器发出状态结果，控制器会根据这一结果向***级发出相应的请求。If the CRC detection error occurs, it indicates that the error configuration file block has exceeded the error correction capability range of the ECC code, the error is miscorrected, and there is no real problem to solve the error. At this time, the status result is sent to the SEU controller. Based on this result, a corresponding request will be sent to the system level.
图4示意了带有ECC和CRC校验功能的FPGA设计及下载流程图。如图3所示，FPGA的设计流程大致包括电路设计与输入、功能仿真、综合、综合后仿真、实现。Figure 4 shows the FPGA design and download flow chart with ECC and CRC check functions. As shown in Figure 3, the FPGA design flow generally includes circuit design and input, functional simulation, synthesis, integrated simulation, and implementation.
首先在电路设计与输入阶段，利用硬件描述语言HDL将所设计的功能描述给EDA软件。First, in the circuit design and input phase, the designed function is described to the EDA software using the hardware description language HDL.
在综合阶段，将HDL语言等设计输入翻译为由与、或、非门、RAM以及寄存器等基本逻辑单元组成的逻辑连接(网表)，并根据设计约束对速度和面积进行逻辑优化。In the synthesis phase, design inputs such as the HDL language are translated into logical connections (net tables) consisting of basic logical units such as AND, OR, NOT, RAM, and registers, and the speed and area are logically optimized according to design constraints.
在实现阶段，根据所选芯片的型号，将综合输出的逻辑网表适配到FPGA器件上。In the implementation phase, the integrated network logic netlist is adapted to the FPGA device based on the model of the selected chip.
在码流生成的过程中，根据配置文件的块、组的信息加入与之相应的ECC和CRC的检验码。In the process of generating the code stream, the check codes of the ECC and the CRC corresponding thereto are added according to the information of the block and the group of the configuration file.
最后，加入了ECC和CRC校验码的配置文件，基于例如JTAG的配置方式下载到配置芯片中。Finally, the configuration file of the ECC and CRC check code is added and downloaded to the configuration chip based on, for example, the JTAG configuration.
FPGA上电以后首先进入配置模式(configuration)，在最后一个配置数据载入到FPGA以后，进入初始化模式(initialization)，在初始化完成后进入用户模式(user-mode)。在配置模式和初始化模式下，FPGA的用户I/O处于高阻态(或内部弱上拉状态)，当进入用户模式下，用户I/O就按照用户设计的功能工作。 After the FPGA is powered on, it first enters the configuration mode. After the last configuration data is loaded into the FPGA, it enters the initialization mode (initialization) and enters the user mode (user-mode) after the initialization is completed. In configuration mode and initialization mode, the user I/O of the FPGA is in a high-impedance state (or internal weak pull-up state). When entering user mode, the user I/O works according to the user-designed function.
前文结合汉明码叙述了本发明的实施例，汉明码的特点在于纠错一比特，检测两比特。显然，本发明不限于此，还可以扩展到可纠错多比特的编码方式，如BCH、RS或其它纠错编码。BCH码是用于校正多个随机错误模式的多级、循环、错误校正、变长数字编码。RS(Reed-Solomon)码是一类纠错能力很强的特殊的非二进制BCH码。The foregoing embodiment of the present invention has been described in connection with a Hamming code which is characterized by error correction of one bit and detection of two bits. Obviously, the invention is not limited thereto, and can also be extended to an error correctable multi-bit coding scheme such as BCH, RS or other error correction coding. The BCH code is a multi-stage, loop, error correction, variable length digital code for correcting multiple random error modes. The RS (Reed-Solomon) code is a special type of non-binary BCH code with strong error correction capability.
图5-图8示意了采用BCH或RS校验码的本发明实施例的配置文件结构、FPGA芯片结构和FPGA设计及下载流程。不同于图1-图4的情况在于编码的方式不同。其它内容基本相同，不复赘述。5-8 illustrate a configuration file structure, an FPGA chip structure, and an FPGA design and download process of an embodiment of the present invention using a BCH or RS check code. The difference from the case of Figures 1 - 4 is that the encoding is different. Other content is basically the same and will not be repeated.
通过采用BCH(由Bose-Ray-Hocquenghem码)或者RS(Reed-solomon码)编码后，可以对每一组的配置文件进行多个比特或者字节进行纠错。本发明实施例所提出的配置架构和处理电路仍然适用，可进一步增强对单粒子翻转的检测和纠错能力。By using BCH (Bose-Ray-Hocquenghem code) or RS (Reed-solomon code) encoding, it is possible to perform error correction on multiple bits or bytes for each group of configuration files. The configuration architecture and processing circuit proposed by the embodiments of the present invention are still applicable, and the detection and error correction capability for single-event flipping can be further enhanced.
以上所述的具体实施方式，对本发明的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施方式而已，并不用于限定本发明的保护范围，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。 The specific embodiments of the present invention have been described in detail with reference to the preferred embodiments of the present invention. All modifications, equivalent substitutions, improvements, etc., made within the spirit and scope of the invention are intended to be included within the scope of the invention.

Claims (7)

  1. 一种FPGA电路，包括：An FPGA circuit comprising:
    配置存储器，用于存储有FPGA配置文件，配置文件包括配置数据和ECC码和CRC码；a configuration memory for storing an FPGA configuration file, the configuration file including configuration data and an ECC code and a CRC code;
    硬件ECC解码器，利用ECC码对配置数据进行纠错和检错；a hardware ECC decoder that performs error correction and error detection on the configuration data by using an ECC code;
    硬件CRC解码器，利用CRC码对配置数据进行纠错；a hardware CRC decoder that corrects configuration data using a CRC code;
    单粒子翻转控制器，用于回读配置文件，并且利用硬件ECC解码器和硬件CRC解码器对回读的配置文件进行检查和纠错，记录配置文件的出错状态、信息；根据硬件CRC、ECC解码器的检测状态，产生相应的控制，并可向***级应用发出出错信号，请求重新配置FPGA文件。Single-event flip controller for reading back configuration files, and using hardware ECC decoder and hardware CRC decoder to check and correct the readback configuration file, record the error status and information of the configuration file; according to hardware CRC, ECC The detection state of the decoder generates corresponding control and can send an error signal to the system level application requesting reconfiguration of the FPGA file.
  2. 如权利要求1所述的FPGA电路，其中单粒子翻转控制器从配置存储器中按块读取配置文件，传输到CRC解码器中对配置文件进行检查；在检查出错时，单粒子翻转控制器将出错的配置文件传输到ECC解码器中进行ECC检测或纠错；配置文件进过ECC检测或纠错后，被写回到配置存储器中；单粒子翻转控制器将被ECC检测或纠错过的配置文件块再次传输到CRC解码器中进行CRC检测。The FPGA circuit of claim 1 wherein the single event flip controller reads the configuration file in blocks from the configuration memory and transmits them to the CRC decoder to check the configuration file; in the event of an error check, the single event flip controller The erroneous configuration file is transferred to the ECC decoder for ECC detection or error correction; after the configuration file has been ECC detected or corrected, it is written back to the configuration memory; the single-event flip-flop controller will be detected or missed by the ECC. The profile block is again transmitted to the CRC decoder for CRC detection.
  3. 如权利要求1所述的FPGA电路，其中单粒子翻转控制器从配置存储器中按组读取配置文件，ECC解码器中进行ECC检测或纠错；每一组的配置文件进过ECC检测或纠错后，被写回到所属块的配置文件中；当这个块的最后一组数据被写回到配置存储器中时，单粒子翻转控制器将这一个块的配置文件读出并传输到CRC模块中进行校验。The FPGA circuit of claim 1 wherein the single event rollover controller reads the configuration file in groups from the configuration memory, performs ECC detection or error correction in the ECC decoder; each set of configuration files is subjected to ECC detection or correction After the error, it is written back to the configuration file of the own block; when the last set of data of the block is written back to the configuration memory, the single-event flip controller reads and transmits the configuration file of the block to the CRC module. Check in.
  4. 如权利要求1所述的FPGA电路，其中ECC码是汉明、BCH或RS码。The FPGA circuit of claim 1 wherein the ECC code is a Hamming, BCH or RS code.
  5. 如权利要求1所述的FPGA电路，其中配置文件具有块结构，每个配置块包括多组数据和ECC编码的校验位；每若干组数据有一个CRC编码的校验位。The FPGA circuit of claim 1 wherein the configuration file has a block structure, each configuration block comprising a plurality of sets of data and ECC encoded check bits; each of the sets of data having a CRC encoded check bit.
  6. 一种FPGA电路的配置文件处理方法，包括： A configuration file processing method for an FPGA circuit, comprising:
    从配置存储器中按块读取配置文件，对配置文件进行CRC检查；Read the configuration file by block from the configuration memory, and perform CRC check on the configuration file;
    在检查出错时，将出错的配置文件进行ECC检测或纠错；配置文件进行ECC检测或纠错后，被写回到配置存储器中；When checking for an error, the error configuration file is subjected to ECC detection or error correction; after the configuration file is ECC detected or corrected, it is written back to the configuration memory;
    将被ECC检测或纠错过的配置文件块再次进行CRC检测。The configuration file block to be detected or missed by the ECC is subjected to CRC detection again.
  7. 一种FPGA电路的配置文件处理方法，包括：A configuration file processing method for an FPGA circuit, comprising:
    从配置存储器中按组读取配置文件，进行ECC检测或纠错；Read configuration files by group from configuration memory for ECC detection or error correction;
    每一组的配置文件进过ECC检测或纠错后，被写回到所属块的配置文件中；After each set of configuration files has been ECC detected or corrected, it is written back to the configuration file of the owning block;
    当这个块的最后一组数据被写回到配置存储器中时，将这一个块的配置文件读出并传输到CRC模块中进行校验。 When the last set of data for this block is written back to the configuration memory, the configuration file for that block is read and transferred to the CRC module for verification.
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CN115297071B (en) * 2022-07-15 2023-10-27 中国航空无线电电子研究所 Fault-tolerant design method for SEU and MBU by switch engine of ARINC664 switch
CN115543683B (en) * 2022-09-21 2023-07-18 深圳市紫光同创电子有限公司 Single event upset error correction method, device, electronic equipment and readable storage medium
CN116974813B (en) * 2023-09-25 2024-04-19 南方电网数字电网研究院有限公司 Register data management method and device, register module and computer equipment

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7408381B1 (en) * 2006-02-14 2008-08-05 Xilinx, Inc. Circuit for and method of implementing a plurality of circuits on a programmable logic device
US7576557B1 (en) * 2008-03-26 2009-08-18 Xilinx, Inc. Method and apparatus for mitigating one or more event upsets
CN102203740A (en) * 2011-05-27 2011-09-28 华为技术有限公司 Data processing method, device and system
CN102566982A (en) * 2012-01-10 2012-07-11 复旦大学 Two-stage FPGA (field programmable gate array) pipeline configuration circuit
US8516339B1 (en) * 2011-04-01 2013-08-20 Xilinx, Inc. Method of and circuit for correcting adjacent bit errors in a memory

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6314433B1 (en) * 1998-06-12 2001-11-06 Hewlett-Packard Company Frame-based heroic data recovery
JP3270441B2 (en) * 2000-01-26 2002-04-02 埼玉日本電気株式会社 Error bit correction method and circuit in time division multiple access system
CN103763067B (en) * 2014-01-28 2017-11-10 天地融科技股份有限公司 A kind of communication data packet error checking and correction method and apparatus
CN104484214B (en) * 2014-12-30 2017-06-20 华中科技大学 Integral system is noted in a kind of configuration of SRAM type FPGA, refreshing and program

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7408381B1 (en) * 2006-02-14 2008-08-05 Xilinx, Inc. Circuit for and method of implementing a plurality of circuits on a programmable logic device
US7576557B1 (en) * 2008-03-26 2009-08-18 Xilinx, Inc. Method and apparatus for mitigating one or more event upsets
US8516339B1 (en) * 2011-04-01 2013-08-20 Xilinx, Inc. Method of and circuit for correcting adjacent bit errors in a memory
CN102203740A (en) * 2011-05-27 2011-09-28 华为技术有限公司 Data processing method, device and system
CN102566982A (en) * 2012-01-10 2012-07-11 复旦大学 Two-stage FPGA (field programmable gate array) pipeline configuration circuit

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109491821A (en) * 2018-11-06 2019-03-19 上海航天计算机技术研究所 Primary particle inversion resistant hardened system and method
CN109491821B (en) * 2018-11-06 2022-07-01 上海航天计算机技术研究所 Reinforcing system and method for resisting single event upset
CN113132055A (en) * 2019-12-31 2021-07-16 深圳云天励飞技术有限公司 File transmission method and related product
CN113132055B (en) * 2019-12-31 2023-04-07 深圳云天励飞技术有限公司 File transmission method and related product
CN112506172A (en) * 2020-12-07 2021-03-16 天津津航计算技术研究所 Multi-CPLD real-time monitoring device
CN113608918A (en) * 2021-08-19 2021-11-05 无锡中微亿芯有限公司 FPGA with automatic error detection and correction function for programmable logic module
CN113608919A (en) * 2021-08-19 2021-11-05 无锡中微亿芯有限公司 FPGA for improving reliability of key configuration code stream by multiplexing buffer memory
CN113655745A (en) * 2021-08-19 2021-11-16 无锡中微亿芯有限公司 FPGA for realizing automatic error detection and correction of configuration code stream
CN113655745B (en) * 2021-08-19 2023-04-07 无锡中微亿芯有限公司 FPGA for realizing automatic error detection and correction of configuration code stream
CN113608918B (en) * 2021-08-19 2023-04-28 无锡中微亿芯有限公司 FPGA with automatic error checking and correcting function for programmable logic module
CN113608919B (en) * 2021-08-19 2024-02-02 无锡中微亿芯有限公司 FPGA for improving reliability of key configuration code stream through multiplexing buffer memory
CN114996050A (en) * 2022-08-01 2022-09-02 中科亿海微电子科技（苏州）有限公司 Parameter-configurable automatic error detection and correction circuit and error detection and correction method

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