WO2017112772A1 - Gravure électrochimique de plusieurs matériaux de silicium - Google Patents

Gravure électrochimique de plusieurs matériaux de silicium Download PDF

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Publication number
WO2017112772A1
WO2017112772A1 PCT/US2016/068023 US2016068023W WO2017112772A1 WO 2017112772 A1 WO2017112772 A1 WO 2017112772A1 US 2016068023 W US2016068023 W US 2016068023W WO 2017112772 A1 WO2017112772 A1 WO 2017112772A1
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Prior art keywords
silicon
silicon substrates
current
porous silicon
substrates
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PCT/US2016/068023
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English (en)
Inventor
Sibani L. BISWAL
Abirami DHANABALAN
Steven L. Sinsabaugh
Peng HE
Botao SONG
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William Marsh Rice University
Lockheed Martin Corporation
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Publication of WO2017112772A1 publication Critical patent/WO2017112772A1/fr

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    • C—CHEMISTRY; METALLURGY
    • C01—INORGANIC CHEMISTRY
    • C01B—NON-METALLIC ELEMENTS; COMPOUNDS THEREOF; METALLOIDS OR COMPOUNDS THEREOF NOT COVERED BY SUBCLASS C01C
    • C01B33/00—Silicon; Compounds thereof
    • C01B33/02—Silicon
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25F—PROCESSES FOR THE ELECTROLYTIC REMOVAL OF MATERIALS FROM OBJECTS; APPARATUS THEREFOR
    • C25F3/00—Electrolytic etching or polishing
    • C25F3/02—Etching
    • C25F3/12—Etching of semiconducting materials
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25F—PROCESSES FOR THE ELECTROLYTIC REMOVAL OF MATERIALS FROM OBJECTS; APPARATUS THEREFOR
    • C25F7/00—Constructional parts, or assemblies thereof, of cells for electrolytic removal of material from objects; Servicing or operating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M4/00—Electrodes
    • H01M4/02—Electrodes composed of, or comprising, active material
    • H01M4/36—Selection of substances as active materials, active masses, active liquids
    • H01M4/38—Selection of substances as active materials, active masses, active liquids of elements or alloys
    • H01M4/386—Silicon or alloys based on silicon
    • C—CHEMISTRY; METALLURGY
    • C01—INORGANIC CHEMISTRY
    • C01P—INDEXING SCHEME RELATING TO STRUCTURAL AND PHYSICAL ASPECTS OF SOLID INORGANIC COMPOUNDS
    • C01P2006/00—Physical properties of inorganic compounds
    • C01P2006/16—Pore diameter
    • C—CHEMISTRY; METALLURGY
    • C01—INORGANIC CHEMISTRY
    • C01P—INDEXING SCHEME RELATING TO STRUCTURAL AND PHYSICAL ASPECTS OF SOLID INORGANIC COMPOUNDS
    • C01P2006/00—Physical properties of inorganic compounds
    • C01P2006/40—Electric properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G11/00—Hybrid capacitors, i.e. capacitors having different positive and negative electrodes; Electric double-layer [EDL] capacitors; Processes for the manufacture thereof or of parts thereof
    • H01G11/22—Electrodes
    • H01G11/30—Electrodes characterised by their material
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/10—Energy storage using batteries

Definitions

  • the present disclosure pertains to methods of making a plurality of porous silicon materials by exposing a plurality of silicon substrates to hydrofluoric acid in the presence of a current. In some embodiments, the exposure results in the etching of the surfaces of the silicon substrates to form the porous silicon materials from the silicon substrates.
  • the exposure of the silicon substrates to hydrofluoric acid in the presence of a current occurs simultaneously and under ambient conditions (e.g., room temperature).
  • the exposure occurs in a solution of hydrofluoric acid in a container that houses the silicon substrates.
  • the container contains an anode and a cathode at opposite ends of the container for supplying current.
  • the silicon substrates are positioned between the anode and the cathode.
  • the silicon substrates may be separated from one another by various distances during etching. For instance, in some embodiments, the silicon substrates are separated by distances that range from about 0.5 cm to about 10 cm. In some embodiments, the silicon substrates are separated by distances that range from about 0.5 cm to about 2 cm.
  • the silicon substrates are etched by electrochemical etching under a constant current.
  • the current ranges from about 50 mA to about 500 mA. In some embodiments, the current ranges from about 50 mA to about 100 mA.
  • the methods of the present disclosure also include a step of separating the porous silicon material from the silicon substrate.
  • the separation occurs by a gradual increase of the electric current in sequential increments.
  • the gradual increase of the electric current during the separation step includes an increase of the electric current by about 1-100 mA per sequential increment.
  • each sequential increment takes from about 1 minute to about 60 minutes.
  • the methods of the present disclosure also include a step of incorporating the porous silicon material as a component of an energy storage device.
  • the porous silicon material is utilized as an electrode in the energy storage device.
  • the porous silicon material is utilized as an anode in the energy storage device.
  • the energy storage device is a battery.
  • the methods of the present disclosure can be utilized to form various types of porous silicon materials.
  • the porous silicon materials include a plurality of pores that include nanopores, mesopores, micropores, and combinations thereof.
  • the porous silicon materials include pores that span at least 50% of a thickness of the porous silicon material. In some embodiments, the porous silicon material includes pores that span an entire thickness of the porous silicon material. In some embodiments, the porous silicon materials have a thickness ranging from about 10 micrometers to about 200 micrometers.
  • FIGURES 1A-1B provide a scheme of a method of making a plurality of porous silicon materials (FIG. 1A) and an apparatus for making the porous silicon materials (FIG. IB).
  • FIGURE 2 shows an exemplary experimental set up for etching a single silicon wafer.
  • FIGURE 3 shows setups and images related to the etching of multiple silicon wafers.
  • FIG. 3A shows an image of an etching chamber for etching multiple silicon wafers.
  • FIG. 3B shows a bipolar electrode diagram of the etching chamber in FIG. 3A.
  • FIG. 3C shows images of the etched 2-inch diameter silicon wafers. The images are shown from left to right in the same order as in the etching chamber.
  • FIGURE 4 shows additional setups and images related to the etching of multiple silicon wafers.
  • FIG. 4A shows an image of an etching chamber for etching multiple silicon wafers.
  • FIGS. 4B-C show images of the electrodes in the etching chamber, including the teflon supported plutonium (pt) mesh cathode (FIG. 4B) and the gold coated anode (FIG. 4C).
  • FIG. 4D shows images of the etched 4-inch diameter silicon wafers. The images are shown from left to right in the same order as in the etching chamber.
  • FIGURE 5 provides schematics of an etching chamber for etching multiple silicon wafers.
  • a top view (FIG. 5A) and a side view (FIG. 5B) are shown.
  • FIGURE 6 shows a side view schematic of an immersion tank for etching multiple silicon wafers.
  • FIGURE 7 shows a top view schematic of an etching chamber for etching multiple silicon wafers.
  • FIGURE 8 shows simulation setups for two multiple-wafer etching processes.
  • the simulation geometry (FIG. 8A) and mesh (FIG. 8B) for a first simulation setup that utilizes 2- inch diameter wafers are shown.
  • a simulation setup for etching shards of 4-inch diameter wafers FIG. 8C).
  • FIGURE 9 illustrates a mechanism by which separation of porous silicon layers from silicon wafers can occur.
  • FIGURE 10 shows an etching chamber for etching four silicon wafers that were placed between two floating electrodes.
  • FIGURE 11 shows images of porous silicon wafers formed from etching the silicon wafers in the etching chamber in FIG. 10. The images in FIGS. 11A-C are shown from left to right in the same order as in the etching chamber.
  • FIGURE 12 shows more detailed images of porous silicon wafers formed from etching silicon wafers in the etching chamber in FIG. 10, including a full image of a silicon wafer (FIG. 12A) and scanning electron microscopy (SEM) images of the silicon wafer (FIGS. 12B-D).
  • FIGURE 13 shows additional setups and images related to the etching of multiple silicon wafers.
  • FIGS. 13A-B show images of an etching chamber for etching multiple silicon wafers.
  • FIG. 13C shows images of the etched silicon wafers. The images are shown from left to right in the same order as in the etching chamber.
  • FIGURE 14 shows additional setups and images related to the etching of multiple silicon wafers.
  • FIG. 14A shows an image of an etching chamber for etching multiple silicon wafers.
  • FIG. 14B shows images of the etched silicon wafers. The images are shown from left to right in the same order as in the etching chamber.
  • FIGURE 15 shows additional images related to the etching of multiple silicon wafers.
  • FIG. 15A shows an image of the etched silicon wafers. The images are shown from left to right in the same order as in the etching chamber.
  • FIGS. 15B-C show SEM images of the etched silicon wafers.
  • Porous silicon materials are useful for a number of applications. For instance, porous silicon materials find applications in electrochemical systems, such as batteries and supercapacitors. Porous silicon materials also find applications for use as filters and solar cell devices.
  • porous silicon materials can be successfully synthesized from a single silicon wafer using an electrochemical hydrofluoric acid (HF) etching process.
  • HF electrochemical hydrofluoric acid
  • the present disclosure pertains to methods of making a plurality of porous silicon materials at the same time.
  • the methods of the present disclosure include a step of exposing a plurality of silicon substrates to hydrofluoric acid in the presence of a current (step 10) to result in the etching of the surfaces of the silicon substrates (step 12) and thereby form the plurality of the porous silicon materials from the silicon substrates (step 14).
  • the methods of the present disclosure also include a step of separating the formed porous silicon materials from the silicon substrate (step 16).
  • the methods of the present disclosure also include a step of incorporating the formed porous silicon materials as a component of an energy storage device (step 18).
  • container 22 can be utilized to form porous silicon materials.
  • Container 22 includes a solution of hydrofluoric acid 23.
  • Container 22 also includes floating anode 24 and floating cathode 34.
  • silicon substrates 26, 28, 30, and 32 are placed in container 22 between floating anode 24 and floating cathode 34. This results in the exposure of hydrofluoric acid in solution 23 to the surfaces of silicon substrates 26, 28, 30, and 32.
  • the anode and cathode are utilized to supply a current that results in the electrochemical etching of the surfaces of the silicon substrates, and the formation of the porous silicon materials from the silicon substrates.
  • porous silicon materials are set forth herein.
  • various methods may be utilized to expose various types of silicon substrates to various concentrations of hydrofluoric acid in the presence of various amounts of current to form various types of porous silicon materials.
  • Various methods may also be utilized to separate the formed porous silicon materials from the silicon substrates.
  • Various methods may be utilized to expose silicon substrates to hydrofluoric acid and current.
  • the exposure occurs in a solution that includes hydrofluoric acid (e.g., solution 23 in FIG. IB).
  • the concentration of the hydrofluoric acid in the solution ranges from about 5% by weight to about 75% by weight of the solution. In some embodiments, the concentration of the hydrofluoric acid in the solution ranges from about 5% by weight to about 50% by weight of the solution. In some embodiments, the concentration of the hydrofluoric acid in the solution ranges from about 10% by weight to about 20% by weight of the solution. In some embodiments, the concentration of the hydrofluoric acid in the solution ranges from about 10% by weight to about 15% by weight of the solution.
  • the solution containing hydrofluoric acid is an electrolyte solution.
  • the electrolyte solution includes hydrofluoric acid (HF) and N, N- dimethylformamide (DMF).
  • HF hydrofluoric acid
  • DMF N, N- dimethylformamide
  • the DMF to HF ratio in the electrolyte solution can range from about 5: 1 to about 8: 1.
  • the DMF to HF ratio in the electrolyte solution includes ratios of 5: 1, 7: 1, 7.5: 1, or 8: 1.
  • the exposure of silicon substrates to hydrofluoric acid and current can occur in various environments and under various conditions. For instance, in some embodiments, the exposure of silicon substrates to hydrofluoric acid in the presence of a current occurs simultaneously, where all the silicon substrates are exposed to hydrofluoric acid and current at the same time. In some embodiments, the exposure of the silicon substrates to hydrofluoric acid in the presence of a current occurs under ambient conditions, such as room temperature and atmospheric pressure.
  • the exposure of the silicon substrates to hydrofluoric acid in the presence of a current occurs in a container that houses the silicon substrates (e.g., container 22 in FIG. IB, which houses silicon substrates 26, 28, 30, and 32).
  • the container includes individual slots for immobilizing the silicon substrates.
  • the container includes an anode and a cathode at opposite ends (e.g., cathode 34 and anode 24 in FIG. IB).
  • the silicon substrates are positioned between the anode and the cathode (e.g., silicon substrates 26, 28, 30, and 32 positioned between cathode 34 and anode 24, as shown in FIG. IB).
  • the cathode and the anode are utilized to supply current to the silicon substrates.
  • Various cathodes and anodes may be utilized.
  • the cathode is a platinum-based cathode.
  • the cathode is in the form of a platinum mesh.
  • the anode is an aluminum-based or gold- based anode.
  • additional cathodes and anodes of various materials, such as copper or carbon nanotubes, can also be envisioned.
  • the cathodes and anodes of the present disclosure can have various shapes.
  • the cathodes or anodes can be in the shapes of solid foils, meshes, spiral structures, and combinations thereof.
  • the silicon substrates of the present disclosure can be exposed to various types of currents. For instance, in some embodiments, the silicon substrates of the present disclosure can be exposed to a constant current. In some embodiments, the silicon substrates of the present disclosure can be exposed to a variant current. In some embodiments, the silicon substrates of the present disclosure can be exposed to a gradually increasing current.
  • the silicon substrates of the present disclosure can be exposed to a current between about 50 mA to about 500 mA. In some embodiments, the silicon substrates of the present disclosure can be exposed to a current between about 50 niA to about 250 niA. In some embodiments, the silicon substrates of the present disclosure can be exposed to a current between about 50 mA to about 100 mA. In some embodiments, the silicon substrates of the present disclosure can be exposed to a current between about 60 mA to about 75 mA. In some embodiments, the silicon substrates of the present disclosure are exposed to a constant current of about 60 mA. Additional currents can also be envisioned.
  • the silicon substrates of the present disclosure can be exposed to a current for various periods of time. In some embodiments, the silicon substrates of the present disclosure are exposed to a current for a time sufficient to etch the surfaces of the porous silicon materials. In some embodiments, the silicon substrates of the present disclosure are exposed to a current from about 10 minutes to about 10 hours. In some embodiments, the silicon substrates of the present disclosure are exposed to a current from about 10 minutes to about 3 hours. In some embodiments, the silicon substrates of the present disclosure are exposed to a current from about 10 minutes to about 30 minutes.
  • the exposure time of silicon substrates to a current is correlated to the strength of the applied current. For instance, in some embodiments, shorter times are used for higher currents while longer times are used for weaker currents.
  • the silicon substrates include, without limitation, silicon wafers, n-type silicon substrates, p-type silicon substrates, polished silicon substrates, metal-coated silicon substrates, and combinations thereof.
  • the silicon substrates include p-type silicon substrates. In some embodiments, the silicon substrates include metal-coated silicon substrates. In some embodiments, the metal-coated silicon substrates include copper-coated silicon substrates, such as copper plated silicon wafers.
  • the silicon substrates of the present disclosure include polished silicon substrates.
  • the polished silicon substrates include a polished surface.
  • the methods of the present disclosure also include a step of polishing the surface of a silicon substrate before its exposure to current and hydrofluoric acid.
  • the polished surface of a silicon substrate faces a cathode (e.g., polished surfaces of silicon substrates 26, 28, 30 and 32 facing cathode 34, as shown in FIG. IB).
  • Various numbers of silicon substrates may be simultaneously exposed to hydrofluoric acid and current. For instance, in some embodiments, at least two silicon substrates are exposed to hydrofluoric acid and current. In some embodiments, more than two silicon substrates are exposed to hydrofluoric acid and current. In some embodiments, at least three silicon substrates are exposed to hydrofluoric acid and current. In some embodiments, at least four silicon substrates are exposed to hydrofluoric acid and current. The use of additional numbers of silicon substrates can also be envisioned.
  • the silicon substrates may be separated from one another by various distances during exposure to current and hydrofluoric acid. For instance, in some embodiments, the silicon substrates are separated by distances that range from about 0.5 cm to about 10 cm. In some embodiments, the silicon substrates are separated by distances that range from about 0.5 cm to about 2 cm. In some embodiments, the silicon substrates are separated by about 0.5 cm.
  • the plurality of silicon substrates may be aligned in various manners during exposure to current and hydrofluoric acid.
  • the silicon substrates may be aligned in different directions.
  • the silicon substrates may be aligned in the same direction (e.g., silicon substrates 26, 28, 30 and 32 being aligned in the same direction, as shown in FIG. IB).
  • the porous silicon substrates of the present disclosure can have various resistivities. For instance, in some embodiments, the porous silicon substrates of the present disclosure can have resistivities that range from about 0.1 ohm-cm to about 25 ohm-cm. In some embodiments, the porous silicon substrates of the present disclosure can have resistivities that range from about 0.1 ohm-cm to about 20 ohm-cm. In some embodiments, the porous silicon substrates of the present disclosure can have resistivities that range from about 0.1 ohm-cm to about 10 ohm-cm. In some embodiments, the porous silicon substrates of the present disclosure can have resistivities that range from about 10 ohm-cm to about 20 ohm-cm. [0055] Etching of Silicon Substrates
  • etching occurs by electrochemical etching.
  • etching occurs when fluoride ions from hydrogen fluoride etch the silicon substrate surface as a current is passed through the silicon substrate in a hydrofluoric acid solution.
  • the fluoride ions etch the side of a silicon substrate facing the negative electrode while the other side of the silicon substrate remains unetched.
  • the fluoride ions etch the entire thickness of silicon substrates.
  • the fluoride ions etch a partial thickness of silicon substrates.
  • the depth of etching may be directly related to the strength of the current and the exposure time. For instance, in some embodiments where silicon substrates (e.g., silicon wafers) are 250 microns thick, the etch depths ranged from 10-150 microns.
  • the etching of silicon substrates forms porous silicon materials from the silicon substrates.
  • the methods of the present disclosure also include a step of separating the formed porous silicon materials from the silicon substrates.
  • Various methods may be used to separate the formed porous silicon materials from the silicon substrates. For instance, in some embodiments, the separation occurs by physically separating the porous silicon materials from the silicon substrates.
  • the separation of porous silicon materials from silicon substrates occurs by gradually increasing the electric current in sequential increments.
  • a "lift-off process is implemented, where the increased current results in the separation of the porous silicon materials from the silicon substrates.
  • a multi-step scheme in which the current is step-wise increased incrementally may be required to achieve the lift-off.
  • a current can be increased in an amount and for a time period to provide for the separation of porous silicon materials from the silicon substrates.
  • the gradual increase of the electric current during the separating step includes an increase of the electric current by about 1-100 mA per sequential increment.
  • the gradual increase of the electric current during the separating step includes an increase of the electric current by about 1-50 mA per sequential increment. In some embodiments, the gradual increase of the electric current during the separating step includes an increase of the electric current by about 25-50 mA per sequential increment.
  • each sequential increment takes from about 1 minute to about 60 minutes. In some embodiments, each sequential increment takes from about 10 minutes to about 30 minutes. In some embodiments, each sequential increment takes from about 10 minutes to about 20 minutes.
  • silicon substrates are exposed to about 75 mA of current for about 3 hours to form porous silicon materials.
  • the "lift off of the porous silicon materials from the silicon substrates is then implemented by increasing the current to about 100 mA for 30 minutes, and then increasing the current to 125 mA for about 10 minutes.
  • silicon substrates are exposed to about 60 mA of current for about 3 hours to form porous silicon materials.
  • the "lift off of the porous silicon materials from the silicon substrates is then implemented by increasing the current to about 100 mA for 30 minutes, then increasing the current to 150 mA for about 20 minutes, and then increasing the current to 200 mA for another 20 minutes.
  • the methods of the present disclosure also include a step of incorporating the formed porous silicon materials of the present disclosure into an energy storage device.
  • the formed porous silicon materials of the present disclosure may be utilized as one or more components of energy storage devices.
  • the formed porous silicon materials are utilized as an electrode in the energy storage device.
  • the porous silicon materials may be utilized as an anode in the energy storage device.
  • the porous silicon materials of the present disclosure may be incorporated into various energy storage devices.
  • the energy storage device includes, without limitation, capacitors, batteries, photovoltaic devices, photovoltaic cells, transistors, current collectors, fuel cell devices, water- splitting devices, and combinations thereof.
  • the energy storage device includes batteries, such as lithium-ion batteries.
  • the porous silicon materials of the present disclosure include a plurality of pores.
  • the pores include, without limitation, nanopores, mesopores, micropores, and combinations thereof.
  • the pores include diameters between about 1 nanometer to about 5 micrometers.
  • the pores include diameters between about 500 nanometers to about 3 micrometers.
  • the pores include diameters between about 1 micrometer to about 5 micrometers.
  • the porous silicon materials of the present disclosure can also have various porosities. For instance, in some embodiments, the porous silicon materials of the present disclosure have porosities that range from about 10% to about 75%. In some embodiments, the porous silicon materials of the present disclosure have porosities that range from about 25% to about 60%. In some embodiments, the porous silicon materials of the present disclosure have porosities that range from about 40% to about 60%. In some embodiments, the porous silicon materials of the present disclosure have porosities that range from about 45% to about 55%.
  • the porous silicon materials of the present disclosure can also have various types of pore spans.
  • the porous silicon materials of the present disclosure include pores that span at least 50% of a thickness of the porous silicon material.
  • the porous silicon materials of the present disclosure include pores that span an entire thickness of the porous silicon material.
  • the porous silicon materials of the present disclosure can have various thicknesses.
  • the porous silicon materials of the present disclosure have a thickness ranging from about 10 micrometers to about 200 micrometers.
  • the porous silicon materials of the present disclosure have a thickness ranging from about 10 micrometers to about 50 micrometers.
  • the porous silicon materials of the present disclosure have a thickness ranging from about 20 micrometers to about 25 micrometers.
  • porous silicon materials of the present disclosure can also be in various forms.
  • the porous silicon materials of the present disclosure are in the form of a porous silicon layer.
  • the porous silicon materials of the present disclosure are in the form of a porous silicon film.
  • the porous silicon materials of the present disclosure are in crystalline form.
  • the methods of the present disclosure can be utilized to form various types of porous silicon materials in a scalable manner. Furthermore, the methods of the present disclosure can occur without requiring multiple steps. For instance, in the some embodiments, the methods of the present disclosure can occur without requiring patterning through lithography. In some embodiments, the methods of the present disclosure can occur under ambient conditions and without requiring vacuum technology.
  • the steps in the methods of the present disclosure can be varied in order to produce desired types of porous silicon materials.
  • hydrogen fluoride concentration can be varied in order affect mass etch rate, pore width, and pore location.
  • etching time can be varied in order to affect the pore depth and pore volume.
  • the substrate e.g., silicon wafer
  • doping and environmental conditions such as temperature, can be used to vary the silicon etch rate and porosity.
  • the methods of the present disclosure can be utilized to produce large quantities of porous silicon materials with uniform morphological features while consuming limited time and energy.
  • the formed porous silicon materials can be utilized in various devices and structures.
  • the formed porous silicon materials of the present disclosure can be used in energy storage devices (e.g., lithium ion batteries, super capacitors, and the like), filters, membranes, sensors, photovoltaic devices, and combinations thereof.
  • Example 1 Simultaneous etching of multiple silicon wafers in an HF solution
  • Applicants demonstrate that the etching of silicon in a hydrofluoric acid (HF) solution can occur with a supply of positive charges (holes) from a silicon substrate.
  • HF hydrofluoric acid
  • silicon atoms are selectively dissolved from the silicon substrate with consumption of two holes per silicon atom (e.g. with reaction valence of 2). In this way, pores of various shapes are etched into silicon, and porous silicon is formed. The skeleton of porous silicon remains crystalline.
  • Applicants describe in this Example a process that combines the principles of electrochemical etching and bipolar electrodes (typically used in electro refining, electro winning, and electrolysis).
  • a p-type silicon wafer is used as the working electrode and platinum is used as the counter electrode in an electrolyte bath of hydrofluoric acid (HF) and N, N-dimethylformamide (DMF).
  • HF hydrofluoric acid
  • DMF N, N-dimethylformamide
  • P-type silicon wafers (10-20 Ohm-cm, (lOO)-Si, thickness ca. 200 ⁇ ) were used in the experiments.
  • a 4 inch silicon wafer sat between a Pt ring cathode on the top and an Al sheet anode beneath (wafer in contact with Al anode). The cathode was grounded and a 60 mA current was supplied through the anode.
  • the aforementioned setup which is illustrated in FIG. 2, can achieve a uniform etching rate across the whole wafer surface to produce a good yield of porous silicon structure, which can subsequently be separated from the un-etched part of the wafer by a "lift-off process using increased current density.
  • etching rate and the etched pore width are controlled by the electric current density and the ion density.
  • aforementioned parameters are in turn affected by the voltage (electric potential) and the HF concentration in the electrolyte solution.
  • the uniform electric current density distribution on the wafer guaranteed the uniform etching rate in favor of porous silicon synthesis, as shown in FIG. 2.
  • a multi-wafer etching system was assembled and tested (FIGS. 3-4).
  • the multi-wafer etching was performed in an open-top Teflon chamber with slots to anchor the silicon wafers.
  • the Teflon chamber was filled with an electrolyte solution that contained an HF to DMF ratio of about 1:5.
  • a high surface area platinum (Pt) mesh was used as a cathode at one end of the chamber and a gold (Au)-coated stainless steel plate was used as anode at the other end.
  • About 60 mA of current was applied through the electrodes.
  • Two setups were used: setup A shown in FIG. 3 and setup B shown in FIG. 4.
  • setup A (FIG. 3)
  • four 2 inch silicon wafers were uniformly placed in a chamber with 2 cm spacings in between (FIGS. 3A-B).
  • the wafers were completely immersed in the electrolyte solution.
  • not all immersed silicon surfaces were etched as in the single- wafer setup. Only centered areas were etched, leaving a blank band around the edge of each wafer, as shown in FIG. 3C.
  • One hypothesis is that, because the wafers cannot completely block the area facing plate electrodes, there is shunt current in the unblocked region near the corners of the Teflon chamber, which results in the unetched band near the wafer edge.
  • setup B a multi- wafer etching setup B was tested (FIGS. 4A-C).
  • setup B a 4-inch silicon wafer was broken into 4 identical shards, and they were uniformly placed in the Teflon etching chamber with the same 2 cm spacing as in setup A in FIGS. 3A-B.
  • shard #2 was misplaced in the opposite manner of the other three in order to completely block the shunt-current in the corner regions.
  • the same electrolyte concentration and current density as in setup A was used in the experiments.
  • Example 1.1 Apparatus for simultaneously etching multiple silicon wafers
  • Silicon wafers (2", boron doped, p-type, single-side polished, 275 + 25 micron thick, and 10-20 ⁇ cm with face orientation of (100)) were cleaned with a methanol and HF solution (2: 1) and stacked on a holder with all the polished sides facing one direction (FIGS. 5A-B). The distance between the wafers was around 2 cm. The holder was then transferred to a tank (FIG. 6). The master platinum electrodes were placed on either side of the stack. The electrode facing the polished side of the wafers was connected to the negative terminal and the other electrode to the positive terminal (FIG. 7).
  • Example 1.2 Simulation of current density distribution
  • the three-dimensional geometry was converted to a free-triangle mesh using the default physics-controlled method in the software COMSOL. Finer mesh grids were generated on the electrodes and wafer surface where electrochemical reactions occur. Coarser mesh grids were generated in the bulk electrolyte volume where change was not as significant as on the interface.
  • the Electric Currents (ec) physics interface (built-in of COMSOL) has been applied to all domains for simulation of the current flow in the model. Electric potential on the anode is fixed at 3V. Other parameters were calculated or measured from the following experimental setup: (1) diameter of wafer: 2 inches; (2) thickness of the wafer: 0.3 mm; (3) conductivity of the Si wafer:
  • Example 1.3 Separation of porous silicon layers from silicon wafers
  • a "lift off process separates porous silicon (pSi) from unetched wafer by increasing current density.
  • Example 2 Multi- wafer etching through the use of floating electrodes
  • Applicants utilized the experimental setup illustrated in FIG. 10 to etch four 2-inch boron-doped silicon wafers with resistivities that ranged from 10 - 20 ohm-cm and were 279 + 25 microns thick.
  • the wafers were placed between two floating electrodes (i.e., a platinum-based cathode and an anode wire) with the polished wafer sides facing the platinum- based cathode.
  • the wafers were spaced 2 cm apart.
  • Three tests were conducted. In the first test, an electrolyte solution containing 300 ml of DMF and 42 ml of HF was utilized.
  • an electrolyte solution containing 300 ml of DMF and 60 ml of HF were utilized.
  • the current applied to the batch of 2-inch silicon wafers for the first test were 66 mA, 75 mA, 80 mA, and 96 mA. This corresponds to current densities of 3.25 mA/cm 2 , 3.8 mA/cm 2 , 3.95 mA/cm 2 , and 4.74 mA/cm 2 , respectively.
  • the current applied to the batch of 2-inch silicon wafers for the second test were 60 mA, 75 mA, 100 mA, 120 mA, 150 mA, 200 mA, and 250 mA.
  • FIGS. 11-12 Images of the formed products are shown in FIGS. 11-12.
  • images of the etched wafers from the first test, the second test and the third test are shown in FIGS. 11A, 11B, and llC, respectively.
  • a focused image of an etched wafer is shown in FIG. 12A.
  • Scanning electron microscopy images of the etched wafer are shown in FIGS. 12B-D.
  • Example 3 Multi-wafer etching through the use of a modified etch unit
  • Applicants utilized a modified etching unit illustrated in FIGS. 13A-B to etch multiple silicon wafers.
  • the etching unit was modified to accommodate less electrolyte using chemically inert microcrystalline wax and PTFE sheets.
  • 2-inch boron-doped silicon wafers with resistivities that ranged from 0.1 - 0.9 ohm - cm or 10-20 ohm- cm and were 279 + 25 microns thick were used.
  • the modified etch unit also reduced the gap between the test cell and electrodes, thereby minimizing shunt current.
  • the etch cell was 5.5 cm wide, 10 cm long, and 4.5 cm deep.
  • a high surface area platinum mesh was used to provide fast removal of hydrogen bubbles typically generated during the etch process and improve the efficiency of the cell.
  • silicon wafers were coated with copper by using a copper platant solution (i.e., via dip coating) to reduce the resistance.
  • a similar etching unit illustrated in FIG. 14A was utilized to etch four silicon wafers under similar conditions.
  • the electrolyte solution contained 150 ml of DMF and 30 ml of HF (i.e., a DMF:HF ratio of 5: 1).
  • the silicon wafers were etched using a constant current of 75 niA for 3 hours, 100 niA for 30 minutes, and 125 mA for 10 minutes.
  • FIG. 14B The images of the etched wafers are shown in FIG. 14B. Applicants observed an increase in the area under the electrolyte. Applicants also observed an increase in the etched area. In addition, the etched areas were brown, similar to single wafer etches. The etched wafer resistivity was about 10-20 ohm-cm.
  • the etching unit illustrated in FIG. 14A was also utilized to etch four silicon wafers under slightly different conditions.
  • the electrolyte solution contained 150 ml of DMF and 30 ml of HF (i.e., a DMF:HF ratio of 5: 1).
  • the silicon wafers were etched at a constant current of 60 mA for 3 hours, 100 mA for 30 minutes, 150 mA for 20 minutes, and 200 mA for 20 minutes.
  • the images of the etched wafers are shown in FIG. 15A.
  • Applicants also observed an increase in the etched area, where the etched area is grey.
  • the etched areas were brown, similar to single wafer etches.
  • the etched wafer resistivity was about 0.1 - 0.9 ohm - cm. Scanning electron microscopy images of the fourth etched wafer in FIG. 15A are shown in FIGS. 15B-C.

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Abstract

L'invention concerne, selon certains modes de réalisation, des procédés de fabrication d'une pluralité de matériaux de silicium poreux par exposition d'une pluralité de substrats de silicium à de l'acide fluorhydrique en présence d'un courant afin d'effectuer la gravure des surfaces des substrats de silicium et la formation de matériaux de silicium poreux à partir des substrats de silicium. L'exposition des substrats de silicium à de l'acide fluorhydrique en présence d'un courant peut avoir lieu simultanément et dans des conditions de température ambiante. L'exposition peut également avoir lieu dans une solution d'acide fluorhydrique dans un récipient qui renferme les substrats de silicium. Le récipient peut également comprendre une anode et une cathode à des extrémités opposées pour l'alimentation en courant. Les procédés de la présente invention peuvent également comprendre une étape de séparation du matériau de silicium poreux du substrat en silicium par augmentation progressive du courant électrique selon des incréments séquentiels.
PCT/US2016/068023 2015-12-21 2016-12-21 Gravure électrochimique de plusieurs matériaux de silicium WO2017112772A1 (fr)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5788082A (en) * 1996-07-12 1998-08-04 Fluoroware, Inc. Wafer carrier
US20110120882A1 (en) * 2009-01-15 2011-05-26 Solexel, Inc. Porous silicon electro-etching system and method
US20130341234A1 (en) * 2011-03-09 2013-12-26 Institut National Des Sciences Appliquees De Lyon Process for manufacturing silicon-based nanoparticles from metallurgical-grade silicon or refined metallurgical-grade silicon
US20140193711A1 (en) * 2013-01-07 2014-07-10 Lockheed Martin Corporation Combined electrochemical and chemical etching processes for generation of porous silicon particulates

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5788082A (en) * 1996-07-12 1998-08-04 Fluoroware, Inc. Wafer carrier
US20110120882A1 (en) * 2009-01-15 2011-05-26 Solexel, Inc. Porous silicon electro-etching system and method
US20130341234A1 (en) * 2011-03-09 2013-12-26 Institut National Des Sciences Appliquees De Lyon Process for manufacturing silicon-based nanoparticles from metallurgical-grade silicon or refined metallurgical-grade silicon
US20140193711A1 (en) * 2013-01-07 2014-07-10 Lockheed Martin Corporation Combined electrochemical and chemical etching processes for generation of porous silicon particulates

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