WO2017111870A1

WO2017111870A1 - Selective hard mask processing based on low-valency group iv heterocyclic precursors

Info

Publication number: WO2017111870A1
Application number: PCT/US2015/000494
Authority: WO
Inventors: Marie KRYSAK; Patricio E. ROMERO
Original assignee: Intel Corporation
Priority date: 2015-12-24
Filing date: 2015-12-24
Publication date: 2017-06-29

Abstract

Selective hard mask processing techniques based, at least in part, on a mask material formed from low-valency group IV heterocyclic precursors, and structures associated with such techniques. Techniques exemplified herein employ low-valency group IV heterocyclic precursors to form one or more hard mask material having orthogonal physical and chemical reactivity to other mask materials formed with traditional precursors, such as, but not limited to tetravalent group IV precursors.

Description

Selective Hard Mask Processing Based On Low- Valency Group IV Heterocyclic

Precursors

BACKGROUND

Demand for integrated circuits (ICs) continues to motivate greater levels of semiconductor device integration and reductions in feature geometries. With more demanding feature densities and alignment tolerances, advanced patterning techniques have become prevalent. Many advanced patterning techniques rely, at least in part, on selective etching of one material over another material. For such selective etch processes, two or more materials are exposed to an etchant and a difference in the dissolution rate between the two materials is leveraged to arrive at the desired feature pattern. Such selective etch processing may be referred to as selective "hard mask" or "etch-stop" processing to differentiate the technique from photolithographic printing of a sacrificial mask material (e.g., photoresist). While hard mask processing may also employ a sacrificial hard mask material that is stripped off after enabling a pattern transfer, often the hard mask material is retained as a structural element in the final product (e.g., integrated circuit). Such hard masks may be in the form of sidewall spacers, trench liners, and etch-stop layers within inter-level dielectric (ILD) stacks.

Demands placed on hard mask materials continue to increase and many

considerations in addition to etch selectivity complicate selective hard mask processing. Hard mask materials are often advantageously dielectric materials to maintain electrical isolation between devices. In addition, hard mask materials with a low relative permittivity (e.g., k < 4.0) are advantageous for reducing parasitic capacitance in the integrated circuit. Hard mask materials that are flowable are advantageous for gap-filling and/or planarizing significant device topography. The ability of a hard mask to function as a diffusion barrier may also be important. Another constraint on hardmask materials is their associated deposition temperature with lower deposition temperatures being advantageous for low thermal budget processing. Furthermore, various selective hardmask integration schemes may employ two or more hardmask materials concurrently, each of which is advantageously etched selectively to the other. These constraints significantly limit the number of materials available for various hard mask applications. BRIEF DESCRIPTION OF THE DRAWINGS

The material described herein is illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements. In the figures:

FIG. 1 is a flow diagram illustrating methods of hard mask processing based on low- valency group IV heterocyclic precursors, in accordance with some embodiments;

FIG. 2 is a graph of thermal gravimetric analysis (TGA) profile for each of an exemplary silylene and germylene precursor, in accordance with some embodiments;

FIG. 3 is a graph of a differential scanning calorimetry (DSC) profile for each of the exemplary silylene and germylene precursors graphed in FIG. 3, in accordance with some embodiments;

FIG. 4 is a flow diagram illustrating methods of fabricating interconnects based on a silylene precursor, in accordance with some embodiments;

FIG. 5, 6, 7A, 7B, 8A, 8B are cross-sectional views of an interconnect structure as selected operations in the methods illustrated in FIG. 4 are performed, in accordance with some embodiments;

FIG. 9 is a flow diagram illustrating methods of forming a substrate with plurality of hard masks that may be further employed in the methods illustrated in FIG. 4, in accordance with some embodiments

FIG. 10A, 10B, IOC, and 10D are cross-sectional views of a substrate structure as selected operations in the methods illustrated in FIG. 9 are performed, in accordance with some embodiments;

FIG. 1 1 illustrates a mobile computing platform and a data server machine employing an SoC including a hard mask deposited with a low-valency group IV heterocyclic precursor, in accordance with embodiments; and FIG. 12 is a functional block diagram of an electronic computing device, in accordance with some embodiments.

DETAILED DESCRIPTION

One or more embodiments are described with reference to the enclosed figures. While specific configurations and arrangements are depicted and discussed in detail, it should be understood that this is done for illustrative purposes only. Persons skilled in the relevant art will recognize that other configurations and arrangements are possible without departing from the spirit and scope of the description. It will be apparent to those skilled in the relevant art that techniques and/or arrangements described herein may be employed in a variety of other systems and applications other than what is described in detail herein.

Reference is made in the following detailed description to the accompanying drawings, which form a part hereof and illustrate exemplary embodiments. Further, it is to be understood that other embodiments may be utilized and structural and/or logical changes may be made without departing from the scope of claimed subject matter. It should also be noted that directions and references, for example, up, down, top, bottom, and so on, may be used merely to facilitate the description of features in the drawings. Therefore, the following detailed description is not to be taken in a limiting sense and the scope of claimed subject matter is defined solely by the appended claims and their equivalents.

In the following description, numerous details are set forth. However, it will be apparent to one skilled in the art, that embodiments may be practiced without these specific details. In some instances, well-known methods and devices are shown in block diagram form, rather than in detail, to avoid obscuring features of various embodiments. Reference throughout this specification to "an embodiment" or "one embodiment" or "some embodiments" means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase "in an embodiment" or "in one embodiment" or "some embodiments" in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

As used in the description and the appended claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

The terms "coupled" and "connected," along with their derivatives, may be used herein to describe functional or structural relationships between components. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, "connected" may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. "Coupled" may be used to indicated that two or more elements are in either direct or indirect (with other intervening elements between them) physical or electrical contact with each other, and/or that the two or more elements co-operate or interact with each other (e.g., as in a cause an effect relationship).

The terms "over," "under," "between," and "on" as used herein refer to a relative position of one component or material with respect to other components or materials where such physical relationships are noteworthy. For example in the context of materials, one material or material disposed over or under another may be directly in contact or may have one or more intervening materials. Moreover, one material disposed between two materials or materials may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first material or material "on" a second material or material is in direct contact with that second material/material. Similar distinctions are to be made in the context of component assemblies.

As used throughout this description, and in the claims, a list of items joined by the term "at least one of or "one or more of can mean any combination of the listed terms. For example, the phrase "at least one of A, B or C" can mean A; B; C; A and B; A and C; B and C; or A, B and C.

Described herein are exemplary selective hard mask processing techniques based, at least in part, on a mask material formed from low-valency group IV heterocyclic precursors, and structures associated with such techniques. As noted above, the many constraints on a hard mask material often limits the etch selectivity possible between two or more hard mask materials. Techniques exemplified herein employ low-valency group IV heterocyclic precursors to form one or more hard mask material having orthogonal physical and chemical reactivity to other mask materials formed with traditional precursors, such as, but not limited to tetravalent group IV precursors. While many films such as silicon oxides (SiO), carbon- doped silicon (SiC), silicon nitrides (SiN), and carbon-doped silicon nitrides (SiCN) formed with a tetravalent silicon precursor, such as silane or tetraethylorthosilicate (TEOS), differ in thermodynamic stability, similarity in their compositions limits selectively with which a given etchant may remove one material relative others. The same can be said for films form with a tetravalent germanium precursor, such as germane.

In some embodiments described further below, at least one hard mask material is formed with a vapor deposition process using a group IV heterocyclic precursor. The group IV heteroatom is advantageously either divalent or trivalent, with N-heterocyclic silylenes and N-heterocyclic germylenes being two exemplary classes of group IV heterocyclic precursors. Although generally hygroscopic and reactive in air, many N-heterocyclic silylenes and germylenes exhibit high thermal stability as well as high volatility, and are therefore good candidates for chemical vapor deposition processes. Beyond merely employing such a precursor in the deposition of a film however, embodiments herein teach the combination of two or more dielectric film depositions, where at least one, but not all, of the deposition processes entail the use of a silylene or germylene precursor. In further embodiments, two or more dielectric film depositions are integrated in a manner that leverages a difference in etch characteristics associated with each dielectric material.

Although not bound by theory, it is currently understood that the unique low-valency bonds of the heteroatom within the exemplary group IV heterocyclic precursor molecules can impart additional differentiation in the etch characteristics between a film deposited with one or more these precursors and another film deposited in with one or more high valency precursor.

FIG. 1 is a flow diagram illustrating methods 101 of hard mask processing based on low-valency heterocyclic precursors, in accordance with some embodiments. Methods 101 begin with receiving a substrate at operation 105. The substrate received may have any structure known in the microelectronics and/or microelectromechanical (MEMs) arts.

Various processing may be performed to generate a substrate suitably prepared as an input to methods 101. As used herein, a "substrate" may include any number of material layers built- up upon a base or carrier. For some advantageous embodiments, the substrate received at operation 105 comprises group-crystalline IV materials (e.g., Si, Ge, SiGe) with one or more material layers and/or structural features disposed thereon. In some embodiments, the substrate at operation 105 received includes a substantially monocry stal line silicon substrate, which may either be a bulk semiconductor or may be semiconductor on insulator (SOI). Substrate materials other than silicon are also possible, with examples including silicon carbide (SiC), sapphire, a III-V compound semiconductor (e.g., GaAs, InP). Substrates may have any level of impurity doping. As described further below the substrate received at operation 105 may further include various dielectric, metal, and semiconductor material layers and/or patterned structures disposed on one more working surface of the substrate.

Methods 101 continue at operation 125 where differentiable hard masks are formed over spatially separated features or regions of the substrate. In some embodiments, a first hard mask is deposited over a first feature or region of the substrate while a second hard mask is deposited over a second feature or region of the substrate. Differentiation of the hard masks may be function of the deposition techniques and/or precursor(s) employed in those techniques. As such, hard mask material differentiation may or may not be readily detectable through compositional analysis. Other material properties, such as, but not limited to, film density, film stress, microstructure, and chemical bonding of constituent atoms may be further bases of hard mask differentiation that results in etch selectivity between the two mask materials. Operation 125 may entail any deposition and/or patterning processes known in the art. For example, a subtractive process may be employed in which the first and second hard mask materials are blanket deposited and patterned in succession such that each remains only over one of the first or second features/regions. While the deposition processes performed at operation 125 may entail any known process, such as, but not limited to, chemical vapor deposition (CVD), atomic layer deposition (ALD), and spin-casting, only one of the first and second hard masks is formed by CVD or ALD with a low-valency group IV heterocyclic precursor. In some embodiments where only one of the two hard mask materials is deposited by CVD/ ALD, the other of the two hard mask materials is deposited by an alternate technique, such as spin-casting.

Alternatively, if CVD/ ALD is employed in the formation of both the first and second hard mask materials, the precursor(s) employed between the two CVD/ ALD processes differ at least to the extent that only one employs a low-valency heterocyclic precursor. In some embodiments, the precursors employed between two CVD/ALD processes differ further in the co-reactant, for example where one is an oxidizer and the other is a reducer. However, in some other embodiments the co-reactants used in the two CVD/ALD processes are the same and only the group IV source differs.

A first of the two hard mask materials deposited with other than a low-valency group IV heterocyclic precursor may be any group-IV containing material, metal oxide, metal nitride, metal carbide or diamond-like carbon (DLC). For some embodiments where a tetravalent group IV precursor such as organosilane (e.g., TEOS, BTBAS, or the like) is employed, exemplary compositions of the first of the hard mask materials include, but are not limited to, SiC, SiN, SiCN, SiO, SiOC, and silicon-doped diamond-like carbon (Si- DLC). In other embodiments where an organosilicon precursor is employed, the second of the two hard mask materials may be an organosilsesquioxane, such as, but not limited to methylsilsesquioxane (MSQ) and hydrogen silsesquioxane (HSQ).

The second of the two hard mask materials deposited with the low-valency group IV heterocyclic precursor may be any group-IV containing material. For embodiments where the low-valency group IV heterocyclic precursor is a silylene, exemplary compositions of the first of the two hard mask materials include, but are not limited to, SiC, SiN, SiCN, SiO, SiOC, metal silicates, and Si-DLC. For embodiments where the low-valency group IV heterocyclic precursor is a germylene, exemplary compositions include, but are not limited to, germanium nitrides (GeN), metal germanides, and germanium-doped diamond-like carbon (Ge-DLC).

Methods 101 continue at operation 135, where the first and second hard mask materials are exposed to an etch process that removes one of the first and second hard mask materials selectively to the other of the first and second hard mask materials. Any wet chemical or plasma-based etch process known to be suitable for the etching of either of the first and second hard mask materials may be employed at operation 135. In some advantageous embodiments, the etch process isotropically etches the hard mask material, being more chemical than physical. For some exemplary wet chemical-based etch processes, a hydrofluoric acid, phosphoric acid, or TMAH chemistry is employed. For some exemplary plasma-based etch processes, a fluorocarbon or halogen chemistry is employed. In further embodiments, a down-stream plasma etch process or other ultra-low bias plasma etch is performed at operation 135. Methods 101 continue at operation 145 where processing of the exposed feature or region of the substrate exposed by the selective etch operation 135 is further processed, for example to form an interconnect to the exposed feature or region of the substrate.

In first embodiments the low-valency group IV heterocyclic precursor employed in the deposition of a hard mask material is a silylene or germylene having the five-member ring structure:

where the single divalent heteroatom E is silicon (8ϊ(ΙΙ)(η²-((ΝΒυ')€2Η4(ΝΒυ')) or germanium (Οε(Π)(η²-((ΝΒυ')€2Η4(ΝΒυ^ι). In some of the first embodiments, one or more of the tertiary butyl groups in the structure above is substituted with any of alkyls (e.g., methyl, ethyl, propyl pentyl, etc.), or aryls (e.g., aromatics). Substituent groups, such as an alkyl, may also be on one or more of the two carbon atoms in the backbone of the above heterocycle.

In second embodiments, the precursor molecule is a less saturated heterocycle than those in the first embodiment, with π-bonding resonance further stabilizing the ring structure:

where the single divalent heteroatom E is silicon (8ί(ΙΙ)(η²-((ΝΒυ^ι)€2Η2(ΝΒυ')) or germanium (Οε(ΙΙ)(η²-((ΝΒυ')€2Η2(ΝΒυ')). FIG. 2 is a graph of thermal gravimetric analysis (TGA) profiles for the Si(II)^²-((NBu^,)C2H₂(NBu^t) and Ge(II)(r|²- ((NBu'^I-foCNBu') precursors in accordance with the second embodiments. For each of these molecules, the temperature at which half the mass has been transported, denoted in dashed line, is approximately 130°C. The residual mass at 150°C is slightly higher for the silylene compound, but is only 2% with the germylene compound below 1 %. FIG. 3 is a graph of a differential scanning calorimetry (DSC) profile for each of the exemplary silylene and germylene precursors graphed in FIG. 2. Both of these silicon(II) and germanium(II) precursor molecules show complete evaporation along with high decomposition

temperatures. Indeed, no decomposition occurs over the full evaporation regime making them ideal CVD precursors. While thermal stability simplifies delivery to a deposition chamber, the high chemical reactivity of these low-valency precursors enables

advantageously low temperature growth processes (e.g., below 250°C) and is amenable to known flowable deposition processes.

In third embodiments, the silylene or germylene precursor is a polycyclic molecule in which the carbon atoms of the heterocycle backbone further participate in an

aryl/aromatic group. In some of the third embodiments, the silylene and germylene precursor molecule has the structure:

where the single divalent heteroatom E is again silicon or germanium. In some of the third embodiments, one or more of the tertiary butyl groups in the structure above may be substituted with a variety of alkyls or aryls.

In fourth embodiments, the silylene or germylene precursor includes a single trivalent silicon or germanium heteroatom. In some of the further embodiments, the precursor molecule has the four-member heterocyclic structure:

where the R is an alkyl or aryl, and X is a halogen or amide. In some of the fourth embodiments, one or more of the tertiary butyl groups in the structure above may be substituted with a variety of alkyls or aryls.

In fifth embodiments, the silylene or germylene precursor includes an interconnected polyheterocyclic species with two or more trivalent heteroatoms. Such precursors may provide higher film growth rates in CVD processes, as two linked silicon atoms can be delivered to a substrate surface for each precursor molecule. In some of the fifth embodiments, the polyheterocyclic molecule has the structure:

where R is an alkyl or aryl. In some of the fifth embodiments, one or more of the tertiary butyl groups in the structure above may also be substituted with a variety of alkyls or aryls.

Any of the silylene and germylene precursor embodiments provided above may be employed in embodiments of methods described herein. Along with these precursors, co- reactants, such as oxidizers (e.g., O2, O3, N2O) may be employed to form oxide hard mask materials, or reducers (e.g., H2 or NH3) may be employed to form nitride hard mask materials. Carbon sources, such as, but not limited to, methane, ethane, and benzene can be used to form carbon-doped hard mask materials, such as SiC, SiOC, and SiCN. These same carbon sources can be employed with the silylene precursor embodiments provided above to further provide silicon-doped DLC hard mask materials. FIG. 4 is a flow diagram illustrating methods 401 of fabricating interconnects based on a silylene precursor, in accordance with some embodiments. Methods 401 are specific embodiments of the class of methods 101 introduced in FIG. 1. Methods 401 fabricate an interconnect structure with a via that may be formed to one of a pair of adjacent underlying features as a function of the selective etch process employed. Methods 401 leverage a mutual etch selectivity across three distinct hard mask materials to enable greater interconnect density and misalignment tolerance. The mutual etch selectivity is based, at least in part, on at least one, but not all, of the hard mask materials being deposited with a low-valency group IV precursor (e.g., any of silylene embodiments described above). FIG. 5, 6, 7A, 7B, 8A, 8B are cross-sectional views of an interconnect structure as selected operations in the methods 401 are performed, in accordance with some embodiments. Referring first to FIG. 4, methods 401 begin with receiving a substrate at operation 405. The substrate received may include any front-end structures, such as, but not limited to transistor arrays disposed within active regions surrounded by isolation regions. At operation 410 a pair of features are formed over the substrate. In some embodiments, the features are a pair conductive traces, which may be gate electrodes associated with adjacent transistors or interconnect traces extending laterally over the substrate, for example in substantially parallel directions. A space between the features is filled with an intervening ILD, which may be any material (e.g., a low-k material with a relative permittivity below 3.5). The pair of features are associated with some minimum lithographic feature pitch (e.g., gate-gate pitch, etc.).

At operation 420, a separate hard mask is formed over each of the pair of features and the ILD. As such, three hard masks are formed. A first hard mask is formed over a space between the features. A second hard mask is formed over a first of the pair of features. A third hard mask is formed over a second of the pair of features. The three hard masks have differentiable material properties as a function of distinct deposition processes and/or distinct deposition precursor chemistries enlisted in their formation. One basis for the hard mask material differentiation is that at least one, but not all, of the three hard masks is of a material deposited by CVD or ALD with a silylene precursor. Hence, in some embodiments only one of the three hard masks is deposited with a silylene precursor (or an alternative low-valency group IV heterocyclic precursor) while the other two hard masks are deposited with other than silylene precursors. In alternative embodiments, two of the three hard masks are deposited with a silylene precursor (that need not be the same silylene precursor), while one of the three hard masks is deposited with other than a silylene precursor.

FIG. 5 illustrates one exemplary embodiment following operation 420. In FIG. 5, a low-k ILD 510 has been deposited over substrate 505. Pairs of conductive traces 515 A, 515B are arrayed over an area of substrate 505. ILD 510 is further disposed in spaces between traces 515 A, 515B with a first hard mask 520 disposed over ILD 510. A second hard mask 530 is disposed over first traces 515 A. A third hard mask 540 is disposed over second traces 515B. Any given pair of adjacent conductive traces 515A, 515B are masked by a different hard mask material with the three hard masks 520, 530, 540 forming tri-color elements 550, 560, 570 in a hard mask array disposed over an array of traces. If the tri-color elements are mapped to an RGB color space, the array of hard masks form a spatially repeating RGBG series of hard mask materials. As such, a set of traces 515 A that are masked by hard mask 530 (R) are interdigitated with a set of traces 515B that are masked by hard mask 530 (B) with hard mask 520 in intervening spaces. Although a I D hard mask array is illustrated in FIG. 5 (e.g., with traces 515A,B and hard masks 520, 530, 540 forming parallel stripes extending into the jc-dimension), a 2D spatial hard mask array having this same RGBG arrangement in a grid may be readily fabricated.

Each of the three hard masks 520, 530, 540 may be any of the materials described above in the context of the two differentiable hard masks employed in method 101 (FIG. 1). For some embodiments where two of the three hard masks 520, 530 540 are materials deposited with other than a low-valency group IV heterocyclic precursor, these two hard masks may be any combination of two materials selected from: group-IV containing materials, metal oxides, metal nitrides, metal carbides, or DLC. In some embodiments, a tetravalent group IV precursor, such as an organosilane, is employed in the deposition of at least one of the mask materials. For example, one of the mask materials 520, 530, 540 may be any of SiC, SiN, SiCN, SiO, SiOC and Si-DLC. In some embodiments, a tetravalent group IV precursor such as an organosilane is employed in the deposition of at least two of the mask materials. For example, two of the mask materials 520, 530, 540 may be any combination of SiC, SiN, SiCN, SiO, SiOC, and Si-DLC. In some embodiments, an organosilicon precursor is employed in the deposition of at least one of the hard mask materials 520, 530, 540. For example, one of the mask materials 520, 530, 540 may be an organosilsesquioxane, such as, but not limited MSQ and HSQ. In some such embodiments, an organosilicon precursor is employed in the deposition of one of the hard mask materials 520, 530, 540 while a tetravalent group IV precursor such as an organosilane is employed in the deposition one other of the mask materials 520, 530, 540. For example, hard mask material 530 may be SiC, SiN, SiCN, SiO, SiOC, or Si-DLC while hard mask material 520 is MSQ and HSQ. For any of the above embodiments where two of the three hard masks 520, 530, 540 are materials deposited with other than a low-valency group IV heterocyclic precursor, the third of the hard mask 520, 530, 540 that is deposited with a silylene precursor may be any of: SiC, SiN, SiCN, SiO, SiOC, metal silicates, and Si-DLC. For some embodiments where two of the three hard masks 520, 530, 540 are materials deposited with a low-valency group IV heterocyclic precursor, these two hard masks may be any combination of two materials selected from: SiC; SiN; SiCN; SiO; SiOC; metal silicates; and Si-DLC. For such embodiments, the third of the three hard masks 520, 530, 540 is a material deposited with other than a low-valency group IV heterocyclic precursor, and may be any of: a group-IV containing material; a metal oxide; a metal nitride, a metal carbide, or DLC. For some embodiments where a tetravalent group IV precursor such as organosilane is employed in the deposition of the third hardmask, exemplary compositions of the third hard mask material includes, but is not limited to, SiC, SiN, SiCN, SiO, SiOC, or Si-DLC. In other embodiments where an organosilicon precursor is employed, the third hard mask material may be an organosilsesquioxane, such as, but not limited to MSQ and HSQ. Noting there is some overlap in the various materials possible for the three hard masks 520, 530, 540, distinctions in the mask materials may or may not be readily discernable through material compositional analysis techniques such as SIMS or TXRF. In some embodiments, material composition of at least one of the three hard mask materials is readily discernable from the other hard mask materials through materials analysis. For example, one of the mask materials 520, 530, 540 may comprise a unique constituent (e.g., a metal, nitrogen, carbon, silicon, or oxygen) absent from the other two. In other

embodiments, a trace nitrogen impurity (e.g., < 1%) is present in one of the mask materials that is absent in another of the mask materials that otherwise includes the same constituents. For example, where two of the three hard masks 520, 530, 540 are SiO, one of the two SiO hard mask materials further includes a trace impurity of nitrogen indicative of a deposition process employing a silylene precursor while the SiO lacking the trace nitrogen impurity is indicative of a deposition process employing a silane precursor. Hence, a tri-color hard mask element including a pair of SiO hard mask materials with a third hard mask material (e.g., SiN, SiCN, SiC, SiOC, Si-DLC, metal nitride, metal carbide) comprises three

compositionally distinct mask materials readily discernable through elemental analysis. As another example, where the tri-color hard mask element includes two SiN mask materials, or two SiCN mask materials, one of these mask materials having more nitrogen than the other indicating the nitrogen-rich material has been deposited by a process employing a silylene precursor. Other material properties in addition to material composition, such as, but not limited to film density, film stress, microstructure, and chemical bonding of constituent atoms may be further bases of hard mask differentiation resulting in mutual etch selectivity between the three hard mask materials. For example, films deposited by spin-cast are typically associated with lower density and higher etch rate than compositional ly similar films deposited by CVD/ALD.

Returning to FIG. 4, methods 401 continue at operation 430 where an ILD is deposited over the hard masks. In some exemplary embodiments, the ILD is a low-k material (e.g., <3.5), and may be substantially the same dielectric material as that disposed between the pairs of features. An opening is then patterned into this overlying ILD, for example with any via or trench interconnect patterning technique further comprising one or more lithographic process and ILD etching process. In the example further illustrated in FIG. 6, a low-k ILD 610 is blanket deposed over the substrate, covering each of the hard masks 520, 530, 540. In some embodiments, IDL 610 is the same material as ILD 510. An opening 620 is patterned into ILD 610, exposing a top surface of at least a portion of hard mask 520, hard mask 530, and hard mask 540. Notably, opening 620 has a lateral CD (e.g., in the ^-dimension) that exceeds the pitch of features 515 A, 515B.

Returning to FIG. 4, methods 401 continue at operation 450 where a portion of one of the features is exposed selectively by etching through an exposed portion of one of the hard masks without etching through the other two hard masks. Operation 450 is therefore a self-aligned feature reveal that is reliant on an etch process that etches one of the hard mask materials with sufficient selectively to the other hard mask materials. Any of the etch processes described above in the context of operation 135 may be employed at operation 450. In the example illustrated in FIG. 7A, an exposed portion of hard mask 530 is removed selectively to exposed portions of hard mask 520 and hard mask 540. Feature 515A is then exposed (revealed) within opening 710 without exposing feature 515B and without exposing ILD 510 to the etch process.

In advantageous embodiments the three hard mask materials provide mutual etch selectivity, meaning either of the two hard masks disposed over the features can be etched selectively to the other and also selectively to the third hard mask disposed over the space between the features. For such embodiments, different etch process employed at operation 450 may self-alignedly reveal either of the adjacent features. In the example illustrated in FIG. 7B, an exposed portion of hard mask 540 is etched away selectively to hard mask 520 and hard mask 530 using at etchant at operation 450 that is selective to both hard masks 520 and 530. Feature 515B is then exposed o within opening 710 without exposing feature 515A and without exposing ILD 510 to the etch process. As illustrated by FIG. 7A and 7B, a single lithographic patterning process may therefore be employed to form an opening to either one of an adjacent pair of underlying features without exposing the space between the features.

Returning to FIG. 4, with the mutual hard mask etch selectivity leveraged at operation 450, methods 401 are completed with metal filling operation 460. Operations 440, 450 and 460 may be iterated with different selective etches performed at operation 450 to form a pair of filled self-aligned interconnect vias at a higher effective resolution than the via lithography. A first of the vias is filled with a conductive material in contact with a first of the features, and a second of the vias is filled with a conductive material in contact with a second of the features. As further illustrated in FIG. 8A for example, the via as opened in FIG. 7A is filled with interconnect metallization 810 in contact with feature 515A.

Repetition of patterning another opening in another location with a complementary hard mask etchant may then arrive at the via as opened in FIG. 7B, which is further filled with interconnect metallization 810 in contact with feature 515B. Notably, portions of hard masks 520, 530 and 540 may be retained as permanent features of the interconnect structures fabricated by methods 401.

FIG. 9 is a flow diagram illustrating methods 901 for forming a substrate with plurality of hard masks that may be further employed in the methods 401 , in accordance with some embodiments. Methods 901 provide one example of how the tri-color hard mask materials employed in methods 401 may be prepared. There are however, many alternatives that one of ordinary skill will readily comprehend on the basis of the technique(s) exemplified by methods 901. FIG. 10A, 10B, IOC, and 10D are cross-sectional views of a substrate structure as selected operations in the methods 901 are performed to arrive at the structure that was introduced in FIG. 5, in accordance with some embodiments. Referring first to FIG. 9, methods 901 begin with receiving a substrate with a pair of laterally or spatially adjacent features at operation 905. The pair of features may be any described elsewhere herein, for example. At operation 910, a first hard mask dielectric material is deposited over the pair of features and over a space between the features. In some exemplary embodiments, this first hard mask dielectric material is deposited by CVD/ALD using a silylene precursor (e.g., any of those described above), a silane precursor (e.g., any of those described above), or any other known precursor. FIG. 10A illustrates a cross- sectional view of an interconnect structure following operation 910, in accordance with some embodiments. As shown, mask 520, comprising any of the dielectric materials described above, is blanket deposited over substrate 505, covering features 515 and ILD 510.

Returning to FIG. 9, method 901 proceeds to operation 920 where the first dielectric material deposited at operation 910 is patterned to expose a first of the pair of adjacent features. Operation 920 may entail any known patterning process. In some embodiments, a first lithographic mask of a multi-mask set employed to form the features in a multiple patterning process is further utilized to open a first subset of the features. For example, as further illustrated in FIG. 10B a first lithographic mask that was employed to form features 515B is employed to define openings 1005 through mask 520 aligned with features 515B. The first hard mask etching operation therefore entails reusing a mask to re-expose a top surface of features previously formed by that mask. A unique mask providing for a different etch bias or re-exposing only a portion of the feature may be employed in the alternative.

Returning to FIG. 9, method 901 continues at operation 930 where a second hard mask dielectric is deposited over the first hard mask material and over the exposed feature. In some embodiments, the second hard mask dielectric is deposited by CVD/ALD with either a silylene precursor if the first hard mask material was deposited with other than the silylene precursor), or other than a silylene precursor if the first hard mask material was deposited with a silylene precursor (or at least a different silylene precursor is employed). This second hard mask dielectric material is further planarized (e.g., flowed and/or polished) with the first hard mask material. In the example further illustrated in FIG. 10C, following operation 930, hard mask 540 backfills openings 1005 in hard mask 520, and may be any of the materials described above.

Returning to FIG. 9, method 901 continues at operation 940 where the first hard mask dielectric is patterned a second time to expose a second of the pair of adjacent features. Operation 940 may entail any known patterning process. In some embodiments, a second lithographic mask of a multi-mask set employed to form the features in a multiple patterning process is further utilized to open a second subset of the features. For example, as further illustrated in FIG. 10D a second lithographic mask that was employed to form features 515A is employed to define openings 1010 through mask 520 aligned with features 515A. The second hard mask etching operation therefore entails reusing a mask to re-expose a top surface of features previously formed by that mask. A unique mask providing for a different etch bias or re-exposing only a portion of the feature may be employed in the alternative.

Returning to FIG. 9, method 901 is completed at operation 950 where a third dielectric material is deposited over the first and second dielectric materials, as well as the exposed feature. This third dielectric material is planarized (e.g., flowed and/or polished) with the first and second dielectric materials. Operation 930 may entail any deposition process, such as, but not limited to CVD, ALD, or spin-casting. In some advantageous embodiments, spin-casting is employed, for example to deposit HSQ, MSQ, or any dielectric comprising SiO, etc. to backfill the openings 1010 (FIG. 10D) to arrive at the structure illustrated in FIG. 5 with hard mask 530 being any of the materials described above.

FIG. 1 1 illustrates a mobile computing platform and a data server machine employing an SoC including a hard mask deposited with a low- valency group IV heteroatom precursor, in accordance with embodiments. In some embodiments system 1 100 comprises a mobile computing platform 1 105 and/or a data server machine 1 106 employing an IC including interconnect structures with two or more hard mask dielectrics, one of which was formed with a silylene precursor, for example as describe elsewhere herein. The server machine 1 106 may be any commercial server, for example including any number of high- performance computing platforms disposed within a rack and networked together for electronic data processing, which in the exemplary embodiment includes a packaged monolithic IC 1 150. The mobile computing platform 1 105 may be any portable device configured for each of electronic data display, electronic data processing, wireless electronic data transmission, or the like. For example, the mobile computing platform 1 105 may be any of a tablet, a smart phone, laptop computer, etc., and may include a display screen (e.g., a capacitive, inductive, resistive, or optical touchscreen), a chip-level or package-level integrated system 1 1 10, and a battery 1 1 15.

Whether disposed within the integrated system 1 1 10 illustrated in the expanded view 1 120, or as a stand-alone packaged chip within the server machine 1 106, packaged monolithic IC 1 150 includes a memory chip (e.g., RAM), or a processor chip (e.g., a microprocessor, a multi-core microprocessor, graphics processor, or the like) including interconnect structures with two or more hard mask dielectrics, one of which was formed with a silylene precursor for example as describe elsewhere herein. The monolithic IC 1 150 may be further coupled to a board, a substrate, or an interposer 1 160 along with, one or more of a power management integrated circuit (PMIC) 1 130, RF (wireless) integrated circuit (RFIC) 1 125 including a wideband RF (wireless) transmitter and/or receiver (TX/RX) (e.g., including a digital baseband and an analog front end module further comprises a power amplifier on a transmit path and a low noise amplifier on a receive path), and a controller thereof 1 135. One or more of PMIC 1 130 and RFIC 1 125 may include at least one interconnect structure with two or more hard mask dielectrics, one of which was formed with a silylene precursor, for example as describe elsewhere herein.

Functionally, PMIC 1 130 may perform battery power regulation, DC-to-DC conversion, etc., and so has an input coupled to battery 1 1 15 and with an output providing a current supply to other functional modules. As further illustrated, in the exemplary embodiment, RFIC 1 125 has an output coupled to an antenna (not shown) to implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.1 1 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. In alternative implementations, each of these board-level modules may be integrated onto separate ICs coupled to the package substrate of the monolithic IC 1 150 or within a single IC coupled to the package substrate of the monolithic IC 1 150.

FIG. 12 is a functional block diagram of a computing device 1200, arranged in accordance with at least some implementations of the present disclosure. Computing device 1200 may be found inside platform 1 105 or server machine 1 106, for example. Device 1200 further includes a motherboard 1202 hosting a number of components, such as, but not limited to, a processor 1204 (e.g., an applications processor), which may further incorporate interconnect structures with two or more hard mask dielectrics, one of which was formed with a silylene precursor, for example as describe elsewhere herein. Processor 1204 may be physically and/or electrically coupled to motherboard 1202. In some examples, processor 1204 includes an integrated circuit die packaged within the processor 1204. In general, the term "processor" or "microprocessor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be further stored in registers and/or memory.

In various examples, one or more communication chips 1206 may also be physically and/or electrically coupled to the motherboard 1202. In further implementations, communication chips 1206 may be part of processor 1204. Depending on its applications, computing device 1200 may include other components that may or may not be physically and electrically coupled to motherboard 1202. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, touchscreen display, touchscreen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera, and mass storage device (such as hard disk drive, solid-state drive (SSD), compact disk (CD), digital versatile disk (DVD), and so forth), or the like.

Communication chips 1206 may enable wireless communications for the transfer of data to and from the computing device 1200. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. Communication chips 1206 may implement any of a number of wireless standards or protocols, including but not limited to those described elsewhere herein. As discussed, computing device 1200 may include a plurality of communication chips 1206. For example, a first communication chip may be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to longer-range wireless

communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

While certain features set forth herein have been described with reference to various implementations, this description is not intended to be construed in a limiting sense. Hence, various modifications of the implementations described herein, as well as other

implementations, which are apparent to persons skilled in the art to which the present disclosure pertains are deemed to lie within the spirit and scope of the present disclosure.

It will be recognized that embodiments other than those described in detail above may be practiced with modification and alteration without departing from the scope of the appended claims. For example the above embodiments may include specific combinations of features as further provided below. In one or more first embodiments, a method of fabricating an integrated circuit comprises forming a pair of features over a substrate, the features having a space there between. The method comprises forming a pair of hard masks adjacent to each other, each of the hard masks disposed over a top surface of at least one of the features, or over the space, and wherein the forming of at least one, but not both, of the hard masks comprises depositing a dielectric with a silylene or germylene precursor. The method comprises exposing at least a top surface of a first of the features without exposing a surface of a second of the features by etching through only one of the hard masks with a selective etch process to which both hard masks are exposed.

In furtherance of the first embodiments, forming the pair of hard masks further comprises forming three hard masks adjacent to each other, each of the three hard masks disposed over a top surface of one of the features or over the space, and wherein the forming of at least one, but not all, of the three hard masks comprises depositing a dielectric with the silylene or germylene precursor. Exposing at least a top surface of first of the features without exposing a surface of a second of the features further comprises etching through only one of the three hard masks with the selective etch process to which all three hard masks are exposed.

In furtherance of the first embodiments immediately above, forming the three hard masks comprises depositing a dielectric material with a silylene precursor for only a first of the three hard masks.

In furtherance of the first embodiments, forming the three hard masks further comprises chemical vapor deposition (CVD) or atomic layer deposition (ALD) of a dielectric material employed as the first hard mask, and CVD or ALD of at least one dielectric material employed for the second or third hard masks.

In furtherance of the first embodiments immediately above, forming the three hard masks further comprises spin casting a dielectric for at least one of the second and third hard masks.

In furtherance of the first embodiments, forming an inter-level dielectric (ILD) over a top surface of each of the three hard masks, and etching an opening in the ILD that exposes each of the three hard masks to the selective etch process. In furtherance of the first embodiments immediately above, etching the opening further comprises etching the ILD and one of the hard masks with the selective etch process.

In furtherance of the first embodiments, forming the three hard masks comprises depositing and patterning a first of three hard mask materials to expose the top surface of one of the features depositing and planarizing a second of three hard mask materials, patterning the first of the three hard mask materials to expose the top surface of another of the features, and depositing and planarizing a third of the three hard mask materials.

In furtherance of the first embodiments, the pair of features comprise a pair of conductive traces, the space is filled with a low-k inter-level dielectric (ILD) protected from the selective etch process by one of the three hard masks disposed over the space.

In furtherance of the first embodiments, the silylene or germylene precursor comprises a heterocyclic molecule including a single divalent silicon or germanium heteroatom.

In furtherance of the first embodiments immediately above, the silylene or germylene p consisting of:

silicon or germanium.

In furtherance of the first embodiments, the silylene or germylene precursor comprises a trivalent silicon heteroatom.

In furtherance of the first embodiments immediately above, the silylene precursor

has the four-member heterocyclic structure

wherein R is an alkyl or aryl, and X is a halogen or amide. In furtherance of the first embodiments, the silylene precursor comprises a polyheterocyclic molecule.

In furtherance of the first embodiments immediately above, the polyheterocyclic molecule has the structure:

, and R is an alkyl or aryl.

In one or more second embodiments, a method of fabricating an integrated circuit comprises forming a first interconnect level over a substrate, the first interconnect level comprising a plurality of conductive traces laterally spaced apart by a low-k inter-level dielectric (ILD). The method comprises forming a plurality of dielectric hard masks over the first interconnect level, wherein the hard masks comprise three different dielectric compositions including a first dielectric composition disposed over the low-k ILD, a second dielectric composition disposed over a first set of the conductive traces, and a third dielectric composition disposed over a second set the conductive traces; and wherein the forming of at least one, but not all, of the three dielectric compositions further comprises use of a silylene or germylene precursor. The method comprises depositing the low-k ILD over the plurality of hard masks and etching an opening in the low-k ILD disposed over the hard masks, the opening exposing a portion of at least three of the hard masks, each of the three exposed hard mask portions comprising one of the three dielectric compositions. The method comprises selectively etching through one of the exposed hard mask portions without etching through two of the exposed hard mask portions to further expose a surface of the one of conductive traces, and forming a second interconnect level, the second interconnect level comprising a conductive material disposed in the opening and in contact with one of the conductive traces and two of the exposed hard mask portions.

In furtherance of the second embodiments, forming the plurality of hard masks further comprises forming a pair of: SiO compositions; SiC compositions; SiN compositions; or SiCN compositions, forming a first of the pair of compositions comprises use of a silylene precursor, and forming a second of the pair of compositions comprises use of a tetravalent silicon precursor.

In furtherance of the second embodiments, the silylene precursor is a heterocyclic silicon molecule having the structure selected from the group consisting of:

, wherein R is an alkyl or aryl, and X is a halogen or amide.

In furtherance of the second embodiments immediately above, forming the pair of compositions further comprises chemical vapor deposition (CVD) or atomic layer deposition (ALD), andf forming the plurality of hard masks further comprises forming the dielectric hard mask having the third composition by spin-casting.

In one or more third embodiments, an integrated circuit (IC), comprises a first interconnect level over a substrate, the first interconnect level comprising a plurality of conductive traces laterally spaced apart by an inter-level dielectric (ILD). The IC comprises a plurality of spatially adjacent dielectric hard masks disposed over the first interconnect level, wherein the hard masks comprise three different dielectric compositions including a first dielectric composition disposed over the ILD, a second dielectric composition disposed over a first set of the conductive traces, and a third dielectric composition disposed over a second set the conductive traces. The IC comprises a second ILD further disposed over the plurality of hard masks, and a second interconnect level comprising a conductive material disposed in an opening within the second ILD and over the hardmask stripes, the conductive material in contact with a portion of at least two of three of the hard masks, and in contact with one of the conductive traces.

In furtherance of the third embodiments, the plurality of hard masks further comprises a pair SiO, SiN, or SiCN compositions, one of the pair having more nitrogen than the other.

In furtherance of the third embodiments, the second set of traces is interdigitated with the first set of traces.

In furtherance of the third embodiments, the plurality of hard masks further comprises a pair SiO compositions, only one of the pair having a trace of nitrogen.

However, the above embodiments are not limited in this regard and, in various implementations, the above embodiments may include the undertaking of only a subset of such features, undertaking a different order of such features, undertaking a different combination of such features, and/or undertaking additional features than those features explicitly listed. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

CLAIMS What is claimed is:

1. A method of fabricating an integrated circuit, the method comprising:

forming a pair of features over a substrate, the features having a space there between;

forming a pair of hard masks adjacent to each other, each of the hard masks disposed over a top surface of at least one of the features, or over the space, and wherein the forming of at least one, but not both, of the hard masks comprises depositing a dielectric with a silylene or germylene precursor; and

exposing at least a top surface of a first of the features without exposing a surface of a

second of the features by etching through only one of the hard masks with a selective etch process to which both hard masks are exposed.

2. The method of claim 1 , wherein:

forming the pair of hard masks further comprises forming three hard masks adjacent to each other, each of the three hard masks disposed over a top surface of one of the features or over the space, and wherein the forming of at least one, but not all, of the three hard masks comprises depositing a dielectric with the silylene or germylene precursor; and

exposing at least a top surface of first of the features without exposing a surface of a second of the features further comprises etching through only one of the three hard masks with the selective etch process to which all three hard masks are exposed.

3. The method of claim 2, wherein forming the three hard masks comprises depositing a dielectric material with a silylene precursor for only a first of the three hard masks.

4. The method of claim 2, wherein forming the three hard masks further comprises:

chemical vapor deposition (CVD) or atomic layer deposition (ALD) of a dielectric material employed as the first hard mask; and

CVD or ALD of at least one dielectric material employed for the second or third hard masks.

5. The method of claim 4, wherein forming the three hard masks further comprises spin casting a dielectric for at least one of the second and third hard masks.

6. The method of claim 2, further comprising:

forming an inter-level dielectric (ILD) over a top surface of each of the three hard masks; and

etching an opening in the ILD that exposes each of the three hard masks to the selective etch process.

7. The method of claim 6, wherein etching the opening further comprises etching the ILD and one of the hard masks with the selective etch process.

8. The method of claim 2, wherein forming the three hard masks comprises:

depositing and patterning a first of three hard mask materials to expose the top surface of one of the features;

depositing and planarizing a second of three hard mask materials;

patterning the first of the three hard mask materials to expose the top surface of another of the features; and

depositing and planarizing a third of the three hard mask materials.

9. The method of claim 1 , wherein:

the pair of features comprise a pair of conductive traces;

the space is filled with a low-k inter-level dielectric (ILD) protected from the selective etch process by one of the three hard masks disposed over the space.

10. The method of claim 1 , wherein the silylene or germylene precursor comprises a

heterocyclic molecule including a single divalent silicon or germanium heteroatom.

1 1 . The method of claim 10, wherein the silylene or germylene precursor has a five-member heterocyclic structure selected from the group consisting of:

E is silicon or

germanium.

12. The method of claim 1 , wherein:

the silylene or germylene precursor comprises a trivalent silicon heteroatom.

13. The method of claim 12, wherein the silylene precursor has the four-member

heterocyclic structure

wherein R is an alky I or aryl, and X is a halogen or amide.

14. The method of claim 12, wherein the silylene precursor comprises a polyheterocyclic molecule.

15. The method of claim 14, wherein the polyheterocyclic molecule has the structure:

and R is an alkyl or aryl.

16. A method of fabricating an integrated circuit, the method comprising:

forming a first interconnect level over a substrate, the first interconnect level comprising a plurality of conductive traces laterally spaced apart by a low-k inter-level dielectric

(ILD);

forming a plurality of dielectric hard masks over the first interconnect level, wherein the hard masks comprise three different dielectric compositions including a first dielectric composition disposed over the low-k ILD, a second dielectric composition disposed over a first set of the conductive traces, and a third dielectric composition disposed over a second set the conductive traces; and wherein the forming of at least one, but not all, of the three dielectric compositions further comprises use of a silylene or germylene precursor;

depositing the low-k ILD over the plurality of hard masks;

etching an opening in the low-k ILD disposed over the hard masks, the opening exposing a portion of at least three of the hard masks, each of the three exposed hard mask portions comprising one of the three dielectric compositions; and

selectively etching through one of the exposed hard mask portions without etching through two of the exposed hard mask portions to further expose a surface of the one of conductive traces; and

forming a second interconnect level, the second interconnect level comprising a conductive material disposed in the opening and in contact with one of the conductive traces and two of the exposed hard mask portions.

17. The method of claim 16, wherein:

forming the plurality of hard masks further comprises forming a pair of:

SiO compositions;

SiC compositions;

SiN compositions; or

SiCN compositions;

forming a first of the pair of compositions comprises use of a silylene precursor; and forming a second of the pair of compositions comprises use of a tetravalent silicon

precursor.

18. The method of claim 17, wherein the silylene precursor is a heterocyclic silicon molecule having the structure selected from the group consisting of:

wherein R is an alkyl or aryl, and X is a halogen or amide.

19. The method of claim 18, wherein:

forming the pair of compositions further comprises chemical vapor deposition (CVD) or atomic layer deposition (ALD); and

forming the plurality of hard masks further comprises forming the dielectric hard mask having the third composition by spin-casting.

20. An integrated circuit (IC), comprising:

a first interconnect level over a substrate, the first interconnect level comprising a plurality of conductive traces laterally spaced apart by an inter-level dielectric (ILD);

a plurality of spatially adjacent dielectric hard masks disposed over the first interconnect level, wherein the hard masks comprise three different dielectric compositions including a first dielectric composition disposed over the ILD, a second dielectric composition disposed over a first set of the conductive traces, and a third dielectric composition disposed over a second set the conductive traces;

a second ILD further disposed over the plurality of hard masks; and

a second interconnect level comprising a conductive material disposed in an opening within the second ILD and over the hardmask stripes, the conductive material in contact with a portion of at least two of three of the hard masks, and in contact with one of the conductive traces.

21. The IC of claim 20, wherein the plurality of hard masks further comprises a pair SiO, SiN, or SiCN compositions, one of the pair having more nitrogen than the other

22. The IC of claim 20, wherein the second set of traces is interdigitated with the first set of traces.

23. The IC of claim 20, wherein the plurality of hard masks further comprises a pair SiO compositions, only one of the pair having a trace of nitrogen.