WO2017111829A1 - Thin film switching device - Google Patents

Thin film switching device Download PDF

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Publication number
WO2017111829A1
WO2017111829A1 PCT/US2015/000387 US2015000387W WO2017111829A1 WO 2017111829 A1 WO2017111829 A1 WO 2017111829A1 US 2015000387 W US2015000387 W US 2015000387W WO 2017111829 A1 WO2017111829 A1 WO 2017111829A1
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WO
WIPO (PCT)
Prior art keywords
transition material
stress
dielectric layer
layer
drain
Prior art date
Application number
PCT/US2015/000387
Other languages
French (fr)
Inventor
Elijah V. KARPOV
Prashant Majhi
Brian S. Doyle
Ravi Pillarisetty
Original Assignee
Intel Corporation
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Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to PCT/US2015/000387 priority Critical patent/WO2017111829A1/en
Publication of WO2017111829A1 publication Critical patent/WO2017111829A1/en

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10N99/00—Subject matter not provided for in other groups of this subclass
    • H10N99/03—Devices using Mott metal-insulator transition, e.g. field effect transistors

Definitions

  • the present disclosure relates generally to the field of integrated circuits, and more particularly, to substrates, assemblies, and techniques to enable thin film switching devices.
  • dies may be stacked on top of each other.
  • One approach is based on thin film designs. These designs include a thin film or layer of material ranging from fractions of a nanometer (monolayer) to several micrometers in thickness.
  • FIGURE 1 is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure
  • FIGURE 2A is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure
  • FIGURE 2B is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure
  • FIGURE 3 is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure
  • FIGURE 4 is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure
  • FIGURE 5 is a simplified block diagram illustrating an embodiment of £ portion of an electronic device, in accordance with one embodiment of the present disclosure
  • FIGURE 6 is a simplified block diagram illustrating an embodiment of i portion of an electronic device, in accordance with one embodiment of the present disclosure
  • FIGURE 7 is a simplified block diagram illustrating an embodiment of i portion of an electronic device, in accordance with one embodiment of the present disclosure
  • FIGURE 8 is a simplified block diagram illustrating an embodiment of ⁇ portion of an electronic device, in accordance with one embodiment of the present disclosure
  • FIGURE 9 is a simplified block diagram illustrating an embodiment of ⁇ portion of an electronic device, in accordance with one embodiment of the present disclosure.
  • FIGURE 10 is a simplified block diagram illustrating an embodiment of portion of an electronic device, in accordance with one embodiment of the present disclosure
  • FIGURE 11 is a simplified block diagram illustrating an embodiment of portion of an electronic device, in accordance with one embodiment of the present disclosure
  • FIGURE 12 is a simplified block diagram illustrating an embodiment of portion of an electronic device, in accordance with one embodiment of the present disclosure
  • FIGURE 13 is a simplified block diagram illustrating an embodiment of portion of an electronic device, in accordance with one embodiment of the present disclosure
  • FIGURE 14 is a simplified block diagram illustrating an embodiment of portion of an electronic device, in accordance with one embodiment of the present disclosure
  • FIGURE 15 is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure
  • FIGURE 16 is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure
  • FIGURE 17 is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure
  • FIGURE 18 is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure
  • FIGURE 19 is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure.
  • FIGURE 20 is an interposer implementing one or more of the embodiments disclosed herein.
  • FIGURE 21 is a computing device built in accordance with an embodiment disclosed herein.
  • Described herein are systems and methods of applying a voltage to a film switching device and causing a dielectric to create stress on transition material.
  • the stress or pressure on the transitional material can cause the transition material to change its conduction (e.g., from a metal to an insulator).
  • the change in conduction of the transition material can change the resistance between a source and a drain.
  • Scaling of logic devices is typically accomplished by reducing the size of the logic device.
  • One approach is based on thin film designs. These designs include a thin film or layer of material ranging from fractions of a nanometer (monolayer) to several micrometers in thickness. The density of such devices can be increased not only by the reduction of their size but also by stacking them in a layer-by-layer fashion.
  • a package substrate may include a source, a drain, a transition material located between the source and the drain, and a dielectric layer.
  • the transition material can be pressure induced metal insulator transition material.
  • the dielectric layer can create stress on the transition material and the stress can change the conductivity of the transition material.
  • a voltage applied to a gate electrode is transferred to the dielectric layer and the dielectric layer creates stress on the transition material.
  • the dielectric layer is a piezo-ceramic layer such that stress on the transition material changes the transition material from an insulating material to a conducting material.
  • the terms “over,” “under,” “between,” and “on” as used herein refer to a relative position of one material layer or component with respect to other layers or components.
  • one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers.
  • one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers.
  • a first layer “on” a second layer is in direct contact with that second layer.
  • one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.
  • Implementations of the embodiments disclosed herein may be formed or carried out on a substrate, such as a semiconductor substrate.
  • the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure.
  • the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group lll-V or group IV materials.
  • germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group lll-V or group IV materials Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be
  • the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).
  • the description uses the phrases “in an embodiment” or “in embodiments,” which may each refer to one or more of the same or different embodiments.
  • the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure are synonymous.
  • a "package” and an “IC package” are synonymous.
  • the terms “chip” and “die” may be used interchangeably.
  • FIGURE 1 illustrates one embodiment of a thin film switching device 100.
  • Thin film switching device 100 can include a source 104, drain 106, transition material 108, insulator 110, ground 112, dielectric 114, and a gate electrode 116.
  • voltage applied to gate electrode 116 causes dielectric 114 to create stress on transition material 108 and the created stress can change transitional material 108 from an insulator to a conductor and allow current to flow from source 104 to drain 106.
  • Transition material 108 may be any material such that when pressure is applied to transition material 108, the pressure will cause transition material 108 to change its conduction.
  • transition material 108 may be a pressure induced metal insulator transition material that can transition from a metal to an insulator when pressure is applied to transition material 108 and the conduction of transition material 108 is changed.
  • transition material 108 may include SmSe, NdFe03, MnO, or any other material or elements that will allow transition material 108 to function as a pressure induced metal insulator transition material as described herein.
  • Insulator 110 may be a MOTT insulator.
  • Dielectric 114 can be a piezo-ceramic layer.
  • dielectric 114 can include barium titanate (BaTi03) and lead zirconate titanate (PZT), BiFe03, or other similar materials.
  • a layer that includes dielectric 114 may be deposited on gate electrode 116.
  • the layers may be etched and/or polished, if desired, and a layer that includes ground 112 may be deposited on the layer that includes dielectric 114.
  • the layers may be etched and/or polished, if desired, and a layer that includes insulator 110 may be deposited on the layer that includes ground 112.
  • the layers may be etched and/or polished, if desired, and a layer that includes source 104, drain 106, and transition material 108 may be deposited on the layer that includes insulator 110.
  • the layers may be etched and/or polished, if desired, and a layer that includes insulator 110 may be deposited on the layer that includes source 104, drain 106, and transition material 108.
  • the layers may be etched and/or polished, if desired, and a layer that includes ground 112 may be deposited on the layer that includes insulator 110.
  • the layers may be etched and/or polished, if desired, and a layer that includes dielectric 114 may be deposited on a layer that includes ground 112.
  • the layers may be etched and polished if desired and a layer that includes gate electrode 116 may be deposited on dielectric 114.
  • the layers may be etched and/or polished, if desired.
  • the general shape or profile of thin film switching device 100 depends on the layers, blocking, etching, polishing, etc. and can include a planar square or rectangle shape or profile, curved shape or profile, diamond shape or profile, etc. For example, to create a rectangular or square shape or profile, from bottom to top, each layer can be partitioned by an edge or created in a damascene type process.
  • source, drain 106, and transition material 108 may be exposed on all sides so that the other material layers may be deposited all around source, drain 106, and transition material 108.
  • One implementation includes a layer stack (e.g., a layer of material A, a layer of material B, a layer of material A again, etc.). Trenches that expose the top layer of material A and a layer of material B may be vertically opened. An etchant may be used that removes material B but leaves material A intact. This could undercut the top layer of material A, leaving it exposed on all sides. Such a process could create a rectangular shape or profile.
  • material A is etched as well, but slower so there would be a curve that makes it closer to an actual cylinder, or give a diamond faceted shape or profile.
  • FIGURE 2A illustrates thin film switching device 100 in a horizontal nanowire configuration.
  • FIGURE 2B illustrated thin film switching device in a vertical nanowire configuration.
  • atomic layer deposition may have been used to uniformly deposit source 104, drain 106, transition material 108, insulator 110, ground 112, dielectric 114, and gate electrode 116 to create the horizontal nanowire configuration illustrated in FIGURE 2A and the vertical nanowire configuration illustrated in FIGURE 2B.
  • FIGURE 3 is a simplified block diagram view illustrating an embodiment of an early stage of the formation of nanowire 102 in accordance with one embodiment of the present disclosure.
  • Nanowire 102 can include a source 104 and a drain 106. Between source 104 and drain 106, transition material 108 can be deposited.
  • FIGURE 4 is a simplified block diagram view illustrating an embodiment of a stage of the formation of nanowire 102 in accordance with one embodiment of the present disclosure.
  • insulator 110 can be deposited between source 104 and drain 106 and over transition material 108 (not shown).
  • ground 112 can be deposited over insulator 110.
  • Ground 112 can provide a grounding path or a ground.
  • FIGURE 5 is a simplified block diagram view illustrating an embodiment of a stage of the formation of nanowire 102 in accordance with one embodiment of the present disclosure.
  • dielectric 114 can be deposited.
  • gate electrode 116 can be deposited.
  • FIGURE 6 is a simplified block diagram view illustrating an embodiment of a stage of the formation of thin film switching device 100 in accordance with one embodiment of the present disclosure.
  • a ground contact 118 can be coupled to ground 112.
  • a gate electrode contact 120 can be coupled to gate electrode 116.
  • a voltage e.g., about 5 volts, 3 volts, 2 volts, etc.
  • ground contact 118 about 0 volts can be applied to or on ground 112. This causes a voltage to be applied to thin film switching device 100 and causes dielectric 114 to create stress on transition material 108.
  • transition material 108 causes transition material 108 to change its conduction (e.g., from a metal to an insulator).
  • the change in conduction of transition material 108 changes the resistance between source 104 and drain 106 and allows thin film switching device 100 to function as a gate.
  • FIGURE 7 is a simplified block diagram view illustrating an embodiment of an early stage in the formation of thin film switching device 100 in accordance with one embodiment of the present disclosure.
  • a layer of transitional material 108 can be stacked on top of a layer that will become drain 106.
  • a layer that will become gate 104 can be stacked.
  • a resist layer 122 can be positioned over the area that will become a nanowire.
  • FIGURE 8 is a simplified block diagram view illustrating an embodiment of an early stage in the formation of a film switching device 100 in accordance with one embodiment of the present disclosure.
  • the layer that included gated 104 has been etched away except for gate 104 that was under resist layer 122.
  • transitional material 108 has been etched away except for transitional material 108 that was under resist layer 122.
  • FIGURE 9 is a simplified block diagram view illustrating an embodiment of a stage in the formation of a thin film switching device 100 in accordance with one embodiment of the present disclosure.
  • a layer that includes insulator 110 can be deposited over gate 104, drain 106, and transitional material 108.
  • a layer that includes insulator 110 is deposited over gate 104, drain 106, and transitional material 108 (not shown).
  • FIGURE 10 is a simplified block diagram view illustrating an embodiment of a stage in the formation of thin film switching device 100 in accordance with one embodiment of the present disclosure.
  • a layer that includes ground 112 can be deposited over insulator 110.
  • a layer that includes ground 112 is deposited over insulator 110, gate 104, drain 106, and transitional material 108 (not shown).
  • FIGURE 11 is a simplified block diagram view illustrating an embodiment of a stage in the formation of thin film switching device 100 in accordance with one embodiment of the present disclosure.
  • a layer that includes dielectric 114 can be deposited over ground 112.
  • ground 112 For example, as illustrated in FIGURE 11, a layer that includes dielectric 114 is deposited over ground 112, insulator 110, gate 104, drain 106, and transitional material 108 (not shown).
  • FIGURE 12 is a simplified block diagram view illustrating an embodiment of a stage in the formation of thin film switching device 100 in accordance with one embodiment of the present disclosure.
  • a layer that includes gate electrode 116 can be deposited over dielectric 114.
  • a layer that includes gate electrode 116 is deposited over dielectric 114, ground 112, insulator 110, gate 104, drain 106, and transitional material 108 (not shown).
  • FIGURE 13 is a simplified block diagram view illustrating an embodiment of a stage in the formation of thin film switching device 100 in accordance with one embodiment of the present disclosure.
  • a portion of gate electrode 116 can be etched away.
  • a portion of gate electrode 116 has been etched away and a portion of dielectric 114 is exposed.
  • FIGURE 14 is a simplified block diagram view illustrating an embodiment of a stage in the formation of thin film switching device 100 in accordance with one embodiment of the present disclosure.
  • a portion of dielectric 114 can be etched away.
  • a portion of dielectric 114 has been etched away and a portion of ground 112 is exposed.
  • FIGURE 15 is a simplified block diagram view illustrating an embodiment of a stage in the formation of thin film switching device 100 in accordance with one embodiment of the present disclosure.
  • a portion of ground 112 can be etched away.
  • a portion of ground 112 has been etched away and a portion of insulator 110 is exposed.
  • FIGURE 16 is a simplified block diagram view illustrating an embodiment of a stage in the formation of thin film switching device 100 in accordance with one embodiment of the present disclosure.
  • a portion of ground 110 can be etched away.
  • a portion of ground 110 has been etched away and a portion of gate 104 is exposed.
  • FIGURE 17 is a simplified block diagram view illustrating an embodiment of a stage in the formation of thin film switching device 100 in accordance with one embodiment of the present disclosure.
  • a portion of drain 106 can be etched away.
  • a portion of drain 106 has been etched away.
  • FIGURE 18 is a simplified block diagram view illustrating an embodiment of thin film switching device 100 in accordance with one embodiment of the present disclosure.
  • a portion of an electronic device 140 can include a silicon layer 124, a first layer 126, and a second layer 128. Note that while only three layers are illustrated (i.e., two layers stacked on silicon layer 124) many more layers could be stacked onto of silicon layer and the number of layers that can be stacked is only limited by limited by design, total height, and economic limitations.
  • Silicon layer 124 can include various electronic devices (e.g., CMOS, etc.) 140. Silicon layer 124 can be electrically coupled to first layer 126 using one or more ILDs 144a and 144b. First layer 126 may be a non-silicon layer and can include first layer electronic devices 142 and one or more stackable switching devices 100. First layer electronic devices 142 may be thin-film based electronic devices. First layer 126 can be electrically coupled to second layer 128 using one or more IDLs 144a and 144b. Second layer 128 may be a non- silicon layer and can include second layer electronic devices 146 and one or more stackable switching devices 100. Second layer electronic devices 146 may be thin-film based electronic devices. Second layer 128 may include the same semiconductor substrate as first layer 126 or may include a different semiconductor substrate.
  • the semiconductor substrate for first layer 126 and second layer 128 may be formed using alternate materials, which may or may not be combined with silicon. This includes, but is not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group lll-V or group IV materials.
  • the substrate of any layer may be a flexible substrate including 2D materials such as graphene and MoS2, organic materials such as pentacene, transparent oxides such as IGZO poly/amorphous (low temperature of dep) lll-V semiconductors and Ge/Si, and other non-silicon flexible substrates.
  • a plurality of transistors such as metal-oxide-semiconductor field-effect transistors (MOSFET or simply MOS transistors), may be fabricated on a substrate (e.g., substrate, 124, first layer substrate 126, and second layer substrate 128).
  • the MOS transistors may be planar transistors, nonplanar transistors, or a combination of both.
  • Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors.
  • Each MOS transistor includes a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer.
  • the gate dielectric layer may include one layer or a stack of layers.
  • the one or more layers may include silicon oxide, silicon dioxide (S1O2) and/or a high-k dielectric material.
  • the high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc.
  • high- k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.
  • an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.
  • the gate electrode layer is formed on the gate dielectric layer and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some
  • the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.
  • metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide.
  • a P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV.
  • metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide.
  • An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 e and about 4.2 eV.
  • the gate electrode when viewed as a cross-section of the transistor along the source-channel-drain direction, may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate.
  • at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate.
  • the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures.
  • the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
  • a pair of sidewall spacers may be formed on opposing sides of the gate stack that bracket the gate stack.
  • the sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.
  • source and drain regions are formed within the substrate adjacent to the gate stack of each MOS transistor.
  • the source and drain regions are generally formed using either an implantation/diffusion process or an
  • etching/deposition process In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source and drain regions. In some implementations, the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide.
  • the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous.
  • the source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group lll-V material or alloy.
  • one or more layers of metal and/or metal alloys may be used to form the source and drain regions.
  • ILD interlayer dielectrics
  • the ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials.
  • dielectric materials include, but are not limited to, silicon dioxide (S1O2), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as
  • the ILD layers may include pores or air gaps to further reduce their dielectric constant.
  • FIGURE 19 is an example of a planar switching device 102.
  • Planar switching device 102 can include a source 104, drain 106, MOTT insulator 110a, dielectric 114, a first gate electrode 132 and a second gate electrode 134.
  • a field created using first gate electrode 132 and second gate electrode 134 causes dielectric 114 to create stress on MOTT insulator 110a.
  • the created stress can change MOTT insulator 110a from an insulator to a conductor and allow current to flow from source 104 to drain 106.
  • MOTT insulator 110a can be a material insulator transition material that is doped by charge carries when external pressure is applied by dielectric 114.
  • FIGURE 20 illustrates an interposer 2000 that can include or interact with one or more embodiments disclosed herein.
  • the interposer 2000 is an intervening substrate used to bridge a first substrate 2002 to a second substrate 2004.
  • the first substrate 2002 may be, for instance, an integrated circuit die.
  • the second substrate 2004 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die.
  • the purpose of an interposer 2000 is to spread a connection to a wider pitch or to reroute a connection to a different connection.
  • an interposer 2000 may couple an integrated circuit die to a ball grid array (BGA) 2006 that can subsequently be coupled to the second substrate 2004.
  • BGA ball grid array
  • first and second substrates 2002/2004 are attached to opposing sides of the interposer 2000. In other embodiments, the first and second substrates 2002/2004 are attached to the same side of the interposer 2000. And in further embodiments, three or more substrates are interconnected by way of the interposer 2000.
  • the interposer 2000 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide.
  • the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group lll-V and group IV materials.
  • the interposer may include metal interconnects 2008 and vias 2010, including but not limited to through-silicon vias (TSVs) 2012.
  • the interposer 2000 may further include embedded devices 2014, including both passive and active devices.
  • Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices.
  • More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 2000.
  • apparatuses or processes disclosed herein may be used in the fabrication of interposer 2000.
  • FIGURE 21 illustrates a computing device 2100 in accordance with various embodiments.
  • the computing device 2100 may include a number of components. In one embodiment, these components are attached to one or more motherboards. In an alternate embodiment, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die.
  • the components in the computing device 2100 include, but are not limited to, an integrated circuit die 2102 and at least one communications logic unit 2108.
  • the communications logic unit 2108 is fabricated within the integrated circuit die 2102 while in other implementations the communications logic unit 2108 is fabricated in a separate integrated circuit chip that may be bonded to a substrate or motherboard that is shared with or electronically coupled to the integrated circuit die 2102.
  • the integrated circuit die 2102 may include a CPU 2104 as well as on-die memory 2106, often used as cache memory, that can be provided by technologies such as embedded DRAM (eDRAM) or spin-transfer torque memory (STTM or STT-MRAM).
  • eDRAM embedded DRAM
  • Computing device 2100 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within an SoC die. These other components include, but are not limited to, volatile memory 2110 (e.g., DRAM), non-volatile memory 2112 (e.g., ROM or flash memory), a graphics processing unit 2114 (GPU), a digital signal processor 2116, a crypto processor 2142 (a specialized processor that executes cryptographic algorithms within hardware), a chipset 2120, an antenna 2122, a display or a touchscreen display 2124, a touchscreen controller 2126, a battery 2128 or other power source, a power amplifier (not shown), a voltage regulator (not shown), a global positioning system (GPS) device 2128, a compass 2130, a motion coprocessor or sensors 2132 (that may include an accelerometer, a gyroscope, and a compass), a speaker 2134, a camera 2136, user input devices 2138 (such as a keyboard, mouse
  • the communications logic unit 2108 enables wireless communications for the transfer of data to and from the computing device 2100.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communications logic unit 2108 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • the computing device 2100 may include a plurality of communications logic units 2108. For instance, a first communications logic unit 2108 may be dedicated to shorter range wireless
  • the processor 2104 of the computing device 2100 can communicate with one or more devices that are formed in accordance with various embodiments.
  • the term "processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the communications logic unit 2108 may also include one or more devices, such as transistors or metal interconnects, that are in communication with various ones of the embodiments disclosed herein.
  • another component housed within the computing device 2100 may contain one or more devices, such as transistors or metal interconnects, that are formed in accordance with implementations of the embodiments disclosed herein.
  • the computing device 2100 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an
  • the computing device 2100 may be any other electronic device that processes data.
  • Example 1 is an apparatus including a source, a drain, a transition material located between the source and the drain, and a dielectric layer, where the dielectric layer.
  • the dielectric layer can create stress on the transition material in response to an applied voltage, and the transition material can undergo a change in conductivity in response to the stress.
  • the subject matter of Example 1 can optionally include a gate electrode, wherein a voltage applied to the gate electrode is transferred to the dielectric layer and the dielectric layer creates stress on the transition material.
  • Example 3 the subject matter of any one of Examples 1-2 can optionally include where the dielectric layer is a piezo-ceramic layer.
  • Example 4 the subject matter of any one of Examples 1-3 can optionally include where stress on the transition material changes the transition material from an insulating material to a conducting material.
  • Example 5 the subject matter of any one of Examples 1-4 can optionally include where stress on the transition material allows a current to flow from the source to the drain.
  • Example 6 the subject matter of any one of Examples 1-5 can optionally include an insulator between the dielectric layer and the transition material.
  • Example 7 the subject matter of any one of Example 1-6 can optionally include where the insulator is a MOTT insulator.
  • a method can include depositing transition material between a source and a drain, and depositing a dielectric over the transition material, where the dielectric layer can create stress on the transition material in response to an applied voltage, and the transition material can undergo a change in conductivity in response to the stress.
  • Example 9 the subject matter of Example 8 can optionally include depositing an insulator over the transition material but under the dielectric.
  • Example 10 the subject matter of any one of Examples 8-9 can optionally include depositing a ground layer over the insulator but under the dielectric, and depositing a gate over the dielectric, where a voltage applied to the gate electrode is transferred to the dielectric layer and the dielectric layer creates stress on the transition material.
  • Example 11 the subject matter of any one of Examples 8-10 can optionally include where the dielectric is a piezo-ceramic layer.
  • Example 12 the subject matter of any one of Examples 8-11 can optionally include where stress on the transition material changes the transition material from an insulating material to a conducting material.
  • Example 13 the subject matter of any one of Examples 8-12 can optionally include where the insulator is a MOTT insulator.
  • Example 14 is a computing device including a processor mounted on a substrate, a communications logic unit within the processor, a memory within the processor, a graphics processing unit within the computing device, an antenna within the computing device, a display on the computing device, a battery within the computing device, a power amplifier within the processor, and a voltage regulator within the processor.
  • the processor can include a source, a drain, a transition material located between the source and the drain, and a dielectric layer, where the dielectric layer can create stress on the transition material in response to an applied voltage, and the transition material can undergo a change in conductivity in response to the stress.
  • Example 15 the subject matter of Example 14 can optionally include a gate electrode, wherein a voltage applied to the gate electrode is transferred to the dielectric layer and the dielectric layer creates stress on the transition material.
  • Example 16 the subject matter of Example 14-15 can optionally include where the dielectric layer is a piezo-ceramic layer.
  • Example 17 the subject matter of Example 14-16 can optionally include where stress on the transition material changes the transition material from an insulating material to a conducting material.
  • Example 18 the subject matter of any one of the Examples 14-17 can optionally include where stress on the transition material allows a current to flow from the source to the drain.
  • Example 19 the subject matter of any one of the Examples 14-18 can optionally include an insulator between the dielectric layer and the transition material.
  • Example 20 the subject matter of any one of the Examples 14-19 can optionally include where the insulator is a MOTT insulator.
  • Example 21 is an integrated circuit (IC) assembly including a substrate, a source, a drain, a transition material located between the source and the drain, and a dielectric layer, where the dielectric layer can create stress on the transition material in response to an applied voltage, and the transition material can undergo a change in conductivity in response to the stress.
  • the subject matter of Example 21 can optionally include a gate electrode, wherein a voltage applied to the gate electrode is transferred to the dielectric layer and the dielectric layer creates stress on the transition material.
  • Example 23 the subject matter of any one of the Examples 21-22 can optionally include where stress on the transition material changes the transition material from an insulating material to a conducting material.
  • Example 24 the subject matter of any one of the Examples 21-22 can optionally include where stress on the transition material allows a current to flow from the source to the drain.
  • Example 25 the subject matter of any one of the Examples 21-24 can optionally include a MOTT insulator between the dielectric layer and the transition material.

Abstract

Substrates, assemblies, and techniques for enabling a thin film switching device are disclosed herein. For example, in some embodiments, an apparatus can include a source, a drain, a transition material located between the source and the drain, and a dielectric layer. The dielectric layer can create stress on the transition material in response to an applied voltage, and the transition material can undergo a change in conductivity in response to the stress.

Description

THIN FILM SWITCHING DEVICE
Technical Field
[0001] The present disclosure relates generally to the field of integrated circuits, and more particularly, to substrates, assemblies, and techniques to enable thin film switching devices.
Background
[0002] To increase the density of dies in an integrated circuit (IC) package of a particular footprint, dies may be stacked on top of each other. One approach is based on thin film designs. These designs include a thin film or layer of material ranging from fractions of a nanometer (monolayer) to several micrometers in thickness.
Brief Description of the Drawings
[0003] Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.
[0004] FIGURE 1 is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure;
[0005] FIGURE 2A is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure;
[0006] FIGURE 2B is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure;
[0007] FIGURE 3 is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure;
[0008] FIGURE 4 is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure; [0009] FIGURE 5 is a simplified block diagram illustrating an embodiment of £ portion of an electronic device, in accordance with one embodiment of the present disclosure;
[0010] FIGURE 6 is a simplified block diagram illustrating an embodiment of i portion of an electronic device, in accordance with one embodiment of the present disclosure;
[0011] FIGURE 7 is a simplified block diagram illustrating an embodiment of i portion of an electronic device, in accordance with one embodiment of the present disclosure;
[0012] FIGURE 8 is a simplified block diagram illustrating an embodiment of ι portion of an electronic device, in accordance with one embodiment of the present disclosure;
[0013] FIGURE 9 is a simplified block diagram illustrating an embodiment of ι portion of an electronic device, in accordance with one embodiment of the present disclosure;
[0014] FIGURE 10 is a simplified block diagram illustrating an embodiment of portion of an electronic device, in accordance with one embodiment of the present disclosure;
[0015] FIGURE 11 is a simplified block diagram illustrating an embodiment of portion of an electronic device, in accordance with one embodiment of the present disclosure;
[0016] FIGURE 12 is a simplified block diagram illustrating an embodiment of portion of an electronic device, in accordance with one embodiment of the present disclosure;
[0017] FIGURE 13 is a simplified block diagram illustrating an embodiment of portion of an electronic device, in accordance with one embodiment of the present disclosure;
[0018] FIGURE 14 is a simplified block diagram illustrating an embodiment of portion of an electronic device, in accordance with one embodiment of the present disclosure; [0019] FIGURE 15 is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure;
[0020] FIGURE 16 is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure;
[0021] FIGURE 17 is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure;
[0022] FIGURE 18 is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure;
[0023] FIGURE 19 is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure;
[0024] FIGURE 20 is an interposer implementing one or more of the embodiments disclosed herein; and
[0025] FIGURE 21 is a computing device built in accordance with an embodiment disclosed herein.
[0026] The figures of the drawings are not necessarily drawn to scale, as their dimensions can be varied considerably without departing from the scope of the present disclosure.
Detailed Description
[0027] Described herein are systems and methods of applying a voltage to a film switching device and causing a dielectric to create stress on transition material. The stress or pressure on the transitional material can cause the transition material to change its conduction (e.g., from a metal to an insulator). The change in conduction of the transition material can change the resistance between a source and a drain. In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the embodiments disclosed herein may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the embodiments disclosed herein may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.
[0028] Scaling of logic devices is typically accomplished by reducing the size of the logic device. One approach is based on thin film designs. These designs include a thin film or layer of material ranging from fractions of a nanometer (monolayer) to several micrometers in thickness. The density of such devices can be increased not only by the reduction of their size but also by stacking them in a layer-by-layer fashion.
[0029] Disclosed herein are substrates, assemblies, and techniques for enabling thin film switching devices. In some embodiments, a package substrate may include a source, a drain, a transition material located between the source and the drain, and a dielectric layer. The transition material can be pressure induced metal insulator transition material. The dielectric layer can create stress on the transition material and the stress can change the conductivity of the transition material. In an example, a voltage applied to a gate electrode is transferred to the dielectric layer and the dielectric layer creates stress on the transition material. In some implementations, the dielectric layer is a piezo-ceramic layer such that stress on the transition material changes the transition material from an insulating material to a conducting material.
[0030] Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the embodiments disclosed herein, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.
[0031] The terms "over," "under," "between," and "on" as used herein refer to a relative position of one material layer or component with respect to other layers or components. For example, one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first layer "on" a second layer is in direct contact with that second layer. Similarly, unless explicitly stated otherwise, one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.
[0032] Implementations of the embodiments disclosed herein may be formed or carried out on a substrate, such as a semiconductor substrate. In one implementation, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group lll-V or group IV materials. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the embodiments disclosed herein.
[0033] In the following detailed description, reference is made to the accompanying drawings that form a part hereof wherein like numerals designate like parts throughout, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.
[0034] Various operations may be described as multiple discrete actions or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments. For the purposes of the present disclosure, the phrase "A and/or B" means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). [0035] The description uses the phrases "in an embodiment" or "in embodiments," which may each refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous. As used herein, a "package" and an "IC package" are synonymous. As used herein, the terms "chip" and "die" may be used interchangeably.
[0036] Turning to FIGURE 1, FIGURE 1 illustrates one embodiment of a thin film switching device 100. Thin film switching device 100 can include a source 104, drain 106, transition material 108, insulator 110, ground 112, dielectric 114, and a gate electrode 116. In an example, voltage applied to gate electrode 116 causes dielectric 114 to create stress on transition material 108 and the created stress can change transitional material 108 from an insulator to a conductor and allow current to flow from source 104 to drain 106.
Transition material 108 may be any material such that when pressure is applied to transition material 108, the pressure will cause transition material 108 to change its conduction. In an example, transition material 108 may be a pressure induced metal insulator transition material that can transition from a metal to an insulator when pressure is applied to transition material 108 and the conduction of transition material 108 is changed. For example, transition material 108 may include SmSe, NdFe03, MnO, or any other material or elements that will allow transition material 108 to function as a pressure induced metal insulator transition material as described herein. Insulator 110 may be a MOTT insulator. In an example, when ground 112 and gate electrode 116 are biased, insulator 110 becomes metallic and shorts transition material 108 so source 104 and drain 106 become connected. In another example, when ground 112 and gate electrode 116 are biased, transition material 108 becomes metallic and source 104 and drain 106 become connected. Dielectric 114 can be a piezo-ceramic layer. For example, dielectric 114 can include barium titanate (BaTi03) and lead zirconate titanate (PZT), BiFe03, or other similar materials.
[0037] In an example, to create a planar thin film switching device 100, a layer that includes dielectric 114 may be deposited on gate electrode 116. The layers may be etched and/or polished, if desired, and a layer that includes ground 112 may be deposited on the layer that includes dielectric 114. The layers may be etched and/or polished, if desired, and a layer that includes insulator 110 may be deposited on the layer that includes ground 112. The layers may be etched and/or polished, if desired, and a layer that includes source 104, drain 106, and transition material 108 may be deposited on the layer that includes insulator 110. The layers may be etched and/or polished, if desired, and a layer that includes insulator 110 may be deposited on the layer that includes source 104, drain 106, and transition material 108. The layers may be etched and/or polished, if desired, and a layer that includes ground 112 may be deposited on the layer that includes insulator 110. The layers may be etched and/or polished, if desired, and a layer that includes dielectric 114 may be deposited on a layer that includes ground 112. The layers may be etched and polished if desired and a layer that includes gate electrode 116 may be deposited on dielectric 114. The layers may be etched and/or polished, if desired. The general shape or profile of thin film switching device 100 depends on the layers, blocking, etching, polishing, etc. and can include a planar square or rectangle shape or profile, curved shape or profile, diamond shape or profile, etc. For example, to create a rectangular or square shape or profile, from bottom to top, each layer can be partitioned by an edge or created in a damascene type process.
[0038] In another example, source, drain 106, and transition material 108 may be exposed on all sides so that the other material layers may be deposited all around source, drain 106, and transition material 108. One implementation includes a layer stack (e.g., a layer of material A, a layer of material B, a layer of material A again, etc.). Trenches that expose the top layer of material A and a layer of material B may be vertically opened. An etchant may be used that removes material B but leaves material A intact. This could undercut the top layer of material A, leaving it exposed on all sides. Such a process could create a rectangular shape or profile. In another implementation, material A is etched as well, but slower so there would be a curve that makes it closer to an actual cylinder, or give a diamond faceted shape or profile.
[0039] FIGURE 2A illustrates thin film switching device 100 in a horizontal nanowire configuration. FIGURE 2B illustrated thin film switching device in a vertical nanowire configuration. In an example, atomic layer deposition may have been used to uniformly deposit source 104, drain 106, transition material 108, insulator 110, ground 112, dielectric 114, and gate electrode 116 to create the horizontal nanowire configuration illustrated in FIGURE 2A and the vertical nanowire configuration illustrated in FIGURE 2B. [0040] Turning to FIGURE 3, FIGURE 3 is a simplified block diagram view illustrating an embodiment of an early stage of the formation of nanowire 102 in accordance with one embodiment of the present disclosure. Nanowire 102 can include a source 104 and a drain 106. Between source 104 and drain 106, transition material 108 can be deposited.
[0041] Turning to FIGURE 4, FIGURE 4 is a simplified block diagram view illustrating an embodiment of a stage of the formation of nanowire 102 in accordance with one embodiment of the present disclosure. Between source 104 and drain 106 and over transition material 108 (not shown), insulator 110 can be deposited. Over insulator 110, ground 112 can be deposited. Ground 112 can provide a grounding path or a ground.
[0042] Turning to FIGURE 5, FIGURE 5 is a simplified block diagram view illustrating an embodiment of a stage of the formation of nanowire 102 in accordance with one embodiment of the present disclosure. Between source 104 and drain 106 and over transition material 108 (not shown), dielectric 114 can be deposited. Over dielectric 114, gate electrode 116 can be deposited.
[0043] Turning to FIGURE 6, FIGURE 6 is a simplified block diagram view illustrating an embodiment of a stage of the formation of thin film switching device 100 in accordance with one embodiment of the present disclosure. On nanowire 102, a ground contact 118 can be coupled to ground 112. Also, a gate electrode contact 120 can be coupled to gate electrode 116. Using gate electrode contact 120, a voltage (e.g., about 5 volts, 3 volts, 2 volts, etc.) can be applied to gate electrode 116 and using ground contact 118, about 0 volts can be applied to or on ground 112. This causes a voltage to be applied to thin film switching device 100 and causes dielectric 114 to create stress on transition material 108. The stress or pressure on transitional material 108 causes transition material 108 to change its conduction (e.g., from a metal to an insulator). The change in conduction of transition material 108 changes the resistance between source 104 and drain 106 and allows thin film switching device 100 to function as a gate.
[0044] Turning to FIGURE 7, FIGURE 7 is a simplified block diagram view illustrating an embodiment of an early stage in the formation of thin film switching device 100 in accordance with one embodiment of the present disclosure. As illustrated in FIGURE 7, a layer of transitional material 108 can be stacked on top of a layer that will become drain 106. On the layer of transitional material 108, a layer that will become gate 104 can be stacked. A resist layer 122 can be positioned over the area that will become a nanowire.
[0045] Turning to FIGURE 8, FIGURE 8 is a simplified block diagram view illustrating an embodiment of an early stage in the formation of a film switching device 100 in accordance with one embodiment of the present disclosure. As illustrated in FIGURE 8, the layer that included gated 104 has been etched away except for gate 104 that was under resist layer 122. Also, transitional material 108 has been etched away except for transitional material 108 that was under resist layer 122.
[0046] Turning to FIGURE 9, FIGURE 9 is a simplified block diagram view illustrating an embodiment of a stage in the formation of a thin film switching device 100 in accordance with one embodiment of the present disclosure. A layer that includes insulator 110 can be deposited over gate 104, drain 106, and transitional material 108. For example, as illustrated in FIGURE 9, a layer that includes insulator 110 is deposited over gate 104, drain 106, and transitional material 108 (not shown).
[0047] Turning to FIGURE 10, FIGURE 10 is a simplified block diagram view illustrating an embodiment of a stage in the formation of thin film switching device 100 in accordance with one embodiment of the present disclosure. A layer that includes ground 112 can be deposited over insulator 110. For example, as illustrated in FIGURE 10, a layer that includes ground 112 is deposited over insulator 110, gate 104, drain 106, and transitional material 108 (not shown).
[0048] Turning to FIGURE 11, FIGURE 11 is a simplified block diagram view illustrating an embodiment of a stage in the formation of thin film switching device 100 in accordance with one embodiment of the present disclosure. A layer that includes dielectric 114 can be deposited over ground 112. For example, as illustrated in FIGURE 11, a layer that includes dielectric 114 is deposited over ground 112, insulator 110, gate 104, drain 106, and transitional material 108 (not shown).
[0049] Turning to FIGURE 12, FIGURE 12 is a simplified block diagram view illustrating an embodiment of a stage in the formation of thin film switching device 100 in accordance with one embodiment of the present disclosure. A layer that includes gate electrode 116 can be deposited over dielectric 114. For example, as illustrated in FIGURE 12, a layer that includes gate electrode 116 is deposited over dielectric 114, ground 112, insulator 110, gate 104, drain 106, and transitional material 108 (not shown).
[0050] Turning to FIGURE 13, FIGURE 13 is a simplified block diagram view illustrating an embodiment of a stage in the formation of thin film switching device 100 in accordance with one embodiment of the present disclosure. A portion of gate electrode 116 can be etched away. For example, as illustrated in FIGURE 13, a portion of gate electrode 116 has been etched away and a portion of dielectric 114 is exposed.
[0051] Turning to FIGURE 14, FIGURE 14 is a simplified block diagram view illustrating an embodiment of a stage in the formation of thin film switching device 100 in accordance with one embodiment of the present disclosure. A portion of dielectric 114 can be etched away. For example, as illustrated in FIGURE 14, a portion of dielectric 114 has been etched away and a portion of ground 112 is exposed.
[0052] Turning to FIGURE 15, FIGURE 15 is a simplified block diagram view illustrating an embodiment of a stage in the formation of thin film switching device 100 in accordance with one embodiment of the present disclosure. A portion of ground 112 can be etched away. For example, as illustrated in FIGURE 15, a portion of ground 112 has been etched away and a portion of insulator 110 is exposed.
[0053] Turning to FIGURE 16, FIGURE 16 is a simplified block diagram view illustrating an embodiment of a stage in the formation of thin film switching device 100 in accordance with one embodiment of the present disclosure. A portion of ground 110 can be etched away. For example, as illustrated in FIGURE 21, a portion of ground 110 has been etched away and a portion of gate 104 is exposed.
[0054] Turning to FIGURE 17, FIGURE 17 is a simplified block diagram view illustrating an embodiment of a stage in the formation of thin film switching device 100 in accordance with one embodiment of the present disclosure. A portion of drain 106 can be etched away. For example, as illustrated in FIGURE 17, a portion of drain 106 has been etched away.
[0055] Turning to FIGURE 18, FIGURE 18 is a simplified block diagram view illustrating an embodiment of thin film switching device 100 in accordance with one embodiment of the present disclosure. In an example, a portion of an electronic device 140 can include a silicon layer 124, a first layer 126, and a second layer 128. Note that while only three layers are illustrated (i.e., two layers stacked on silicon layer 124) many more layers could be stacked onto of silicon layer and the number of layers that can be stacked is only limited by limited by design, total height, and economic limitations.
[0056] Silicon layer 124 can include various electronic devices (e.g., CMOS, etc.) 140. Silicon layer 124 can be electrically coupled to first layer 126 using one or more ILDs 144a and 144b. First layer 126 may be a non-silicon layer and can include first layer electronic devices 142 and one or more stackable switching devices 100. First layer electronic devices 142 may be thin-film based electronic devices. First layer 126 can be electrically coupled to second layer 128 using one or more IDLs 144a and 144b. Second layer 128 may be a non- silicon layer and can include second layer electronic devices 146 and one or more stackable switching devices 100. Second layer electronic devices 146 may be thin-film based electronic devices. Second layer 128 may include the same semiconductor substrate as first layer 126 or may include a different semiconductor substrate.
[0057] The semiconductor substrate for first layer 126 and second layer 128 (and any additional layers) may be formed using alternate materials, which may or may not be combined with silicon. This includes, but is not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group lll-V or group IV materials. In other examples, the substrate of any layer may be a flexible substrate including 2D materials such as graphene and MoS2, organic materials such as pentacene, transparent oxides such as IGZO poly/amorphous (low temperature of dep) lll-V semiconductors and Ge/Si, and other non-silicon flexible substrates.
[0058] In an example, a plurality of transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFET or simply MOS transistors), may be fabricated on a substrate (e.g., substrate, 124, first layer substrate 126, and second layer substrate 128). In various implementations, the MOS transistors may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors. Although the implementations described herein may illustrate only planar transistors, it should be noted that the features, examples, and embodiments discussed herein may also be carried out using nonplanar transistors.
[0059] Each MOS transistor includes a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (S1O2) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high- k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.
[0060] The gate electrode layer is formed on the gate dielectric layer and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some
implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.
[0061] For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 e and about 4.2 eV.
[0062] In some implementations, when viewed as a cross-section of the transistor along the source-channel-drain direction, the gate electrode may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further embodiments, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
[0063] In some embodiments, a pair of sidewall spacers may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.
[0064] As is well known in the art, source and drain regions are formed within the substrate adjacent to the gate stack of each MOS transistor. The source and drain regions are generally formed using either an implantation/diffusion process or an
etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source and drain regions. In some implementations, the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group lll-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source and drain regions.
[0065] One or more interlayer dielectrics (ILD) are deposited over the MOS transistors. The ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials. Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (S1O2), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as
silsesquioxane, siloxane, or organosilicate glass. The ILD layers may include pores or air gaps to further reduce their dielectric constant.
[0066] Turning to FIGURE 19, FIGURE 19 is an example of a planar switching device 102. Planar switching device 102 can include a source 104, drain 106, MOTT insulator 110a, dielectric 114, a first gate electrode 132 and a second gate electrode 134. In an example, a field created using first gate electrode 132 and second gate electrode 134 causes dielectric 114 to create stress on MOTT insulator 110a. The created stress can change MOTT insulator 110a from an insulator to a conductor and allow current to flow from source 104 to drain 106. MOTT insulator 110a can be a material insulator transition material that is doped by charge carries when external pressure is applied by dielectric 114.
[0067] Turning to FIGURE 20, FIGURE 20 illustrates an interposer 2000 that can include or interact with one or more embodiments disclosed herein. The interposer 2000 is an intervening substrate used to bridge a first substrate 2002 to a second substrate 2004. The first substrate 2002 may be, for instance, an integrated circuit die. The second substrate 2004 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer 2000 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer 2000 may couple an integrated circuit die to a ball grid array (BGA) 2006 that can subsequently be coupled to the second substrate 2004. In some embodiments, the first and second substrates 2002/2004 are attached to opposing sides of the interposer 2000. In other embodiments, the first and second substrates 2002/2004 are attached to the same side of the interposer 2000. And in further embodiments, three or more substrates are interconnected by way of the interposer 2000.
[0068] The interposer 2000 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group lll-V and group IV materials.
[0069] The interposer may include metal interconnects 2008 and vias 2010, including but not limited to through-silicon vias (TSVs) 2012. The interposer 2000 may further include embedded devices 2014, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 2000. In accordance with various embodiments, apparatuses or processes disclosed herein may be used in the fabrication of interposer 2000.
[0070] Turning to FIGURE 21, FIGURE 21 illustrates a computing device 2100 in accordance with various embodiments. The computing device 2100 may include a number of components. In one embodiment, these components are attached to one or more motherboards. In an alternate embodiment, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die. The components in the computing device 2100 include, but are not limited to, an integrated circuit die 2102 and at least one communications logic unit 2108. In some implementations the communications logic unit 2108 is fabricated within the integrated circuit die 2102 while in other implementations the communications logic unit 2108 is fabricated in a separate integrated circuit chip that may be bonded to a substrate or motherboard that is shared with or electronically coupled to the integrated circuit die 2102. The integrated circuit die 2102 may include a CPU 2104 as well as on-die memory 2106, often used as cache memory, that can be provided by technologies such as embedded DRAM (eDRAM) or spin-transfer torque memory (STTM or STT-MRAM).
[0071] Computing device 2100 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within an SoC die. These other components include, but are not limited to, volatile memory 2110 (e.g., DRAM), non-volatile memory 2112 (e.g., ROM or flash memory), a graphics processing unit 2114 (GPU), a digital signal processor 2116, a crypto processor 2142 (a specialized processor that executes cryptographic algorithms within hardware), a chipset 2120, an antenna 2122, a display or a touchscreen display 2124, a touchscreen controller 2126, a battery 2128 or other power source, a power amplifier (not shown), a voltage regulator (not shown), a global positioning system (GPS) device 2128, a compass 2130, a motion coprocessor or sensors 2132 (that may include an accelerometer, a gyroscope, and a compass), a speaker 2134, a camera 2136, user input devices 2138 (such as a keyboard, mouse, stylus, and touchpad), and a mass storage device 2140 (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
[0072] The communications logic unit 2108 enables wireless communications for the transfer of data to and from the computing device 2100. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communications logic unit 2108 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 2100 may include a plurality of communications logic units 2108. For instance, a first communications logic unit 2108 may be dedicated to shorter range wireless
communications such as Wi-Fi and Bluetooth and a second communications logic unit 2108 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others. [0073] The processor 2104 of the computing device 2100 can communicate with one or more devices that are formed in accordance with various embodiments. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
[0074] The communications logic unit 2108 may also include one or more devices, such as transistors or metal interconnects, that are in communication with various ones of the embodiments disclosed herein. In further embodiments, another component housed within the computing device 2100 may contain one or more devices, such as transistors or metal interconnects, that are formed in accordance with implementations of the embodiments disclosed herein.
[0075] In various embodiments, the computing device 2100 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an
entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 2100 may be any other electronic device that processes data.
[0076] The above description of illustrated implementations, including what is described in the Abstract, is not intended to be exhaustive or to limit the scope of the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the embodiments disclosed herein are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.
OTHER NOTES AND EXAMPLES
[0077] Example 1 is an apparatus including a source, a drain, a transition material located between the source and the drain, and a dielectric layer, where the dielectric layer. In one implementation, the dielectric layer can create stress on the transition material in response to an applied voltage, and the transition material can undergo a change in conductivity in response to the stress. [0078] In Example 2, the subject matter of Example 1 can optionally include a gate electrode, wherein a voltage applied to the gate electrode is transferred to the dielectric layer and the dielectric layer creates stress on the transition material.
[0079] In Example 3, the subject matter of any one of Examples 1-2 can optionally include where the dielectric layer is a piezo-ceramic layer.
[0080] In Example 4, the subject matter of any one of Examples 1-3 can optionally include where stress on the transition material changes the transition material from an insulating material to a conducting material.
[0081] In Example 5, the subject matter of any one of Examples 1-4 can optionally include where stress on the transition material allows a current to flow from the source to the drain.
[0082] In Example 6, the subject matter of any one of Examples 1-5 can optionally include an insulator between the dielectric layer and the transition material.
[0083] In Example 7, the subject matter of any one of Example 1-6 can optionally include where the insulator is a MOTT insulator.
[0084] In Example 8, a method can include depositing transition material between a source and a drain, and depositing a dielectric over the transition material, where the dielectric layer can create stress on the transition material in response to an applied voltage, and the transition material can undergo a change in conductivity in response to the stress.
[0085] In Example 9, the subject matter of Example 8 can optionally include depositing an insulator over the transition material but under the dielectric.
[0086] In Example 10, the subject matter of any one of Examples 8-9 can optionally include depositing a ground layer over the insulator but under the dielectric, and depositing a gate over the dielectric, where a voltage applied to the gate electrode is transferred to the dielectric layer and the dielectric layer creates stress on the transition material.
[0087] In Example 11, the subject matter of any one of Examples 8-10 can optionally include where the dielectric is a piezo-ceramic layer.
[0088] In Example 12, the subject matter of any one of Examples 8-11 can optionally include where stress on the transition material changes the transition material from an insulating material to a conducting material. [0089] In Example 13, the subject matter of any one of Examples 8-12 can optionally include where the insulator is a MOTT insulator.
[0090] In Example 14, is a computing device including a processor mounted on a substrate, a communications logic unit within the processor, a memory within the processor, a graphics processing unit within the computing device, an antenna within the computing device, a display on the computing device, a battery within the computing device, a power amplifier within the processor, and a voltage regulator within the processor. The processor can include a source, a drain, a transition material located between the source and the drain, and a dielectric layer, where the dielectric layer can create stress on the transition material in response to an applied voltage, and the transition material can undergo a change in conductivity in response to the stress.
[0091] In Example, 15, the subject matter of Example 14 can optionally include a gate electrode, wherein a voltage applied to the gate electrode is transferred to the dielectric layer and the dielectric layer creates stress on the transition material.
[0092] In Example 16 the subject matter of Example 14-15 can optionally include where the dielectric layer is a piezo-ceramic layer.
[0093] In Example 17, the subject matter of Example 14-16 can optionally include where stress on the transition material changes the transition material from an insulating material to a conducting material.
[0094] In Example 18, the subject matter of any one of the Examples 14-17 can optionally include where stress on the transition material allows a current to flow from the source to the drain.
[0095] In Example 19, the subject matter of any one of the Examples 14-18 can optionally include an insulator between the dielectric layer and the transition material.
[0096] In Example 20, the subject matter of any one of the Examples 14-19 can optionally include where the insulator is a MOTT insulator.
[0097] Example 21 is an integrated circuit (IC) assembly including a substrate, a source, a drain, a transition material located between the source and the drain, and a dielectric layer, where the dielectric layer can create stress on the transition material in response to an applied voltage, and the transition material can undergo a change in conductivity in response to the stress. [0098] In Example 22, the subject matter of Example 21 can optionally include a gate electrode, wherein a voltage applied to the gate electrode is transferred to the dielectric layer and the dielectric layer creates stress on the transition material.
[0099] In Example 23, the subject matter of any one of the Examples 21-22 can optionally include where stress on the transition material changes the transition material from an insulating material to a conducting material.
[00100] In Example 24, the subject matter of any one of the Examples 21-22 can optionally include where stress on the transition material allows a current to flow from the source to the drain.
[00101] In Example 25, the subject matter of any one of the Examples 21-24 can optionally include a MOTT insulator between the dielectric layer and the transition material.

Claims

Claims
1. An apparatus comprising:
a source;
a drain;
a transition material located between the source and the drain; and
a dielectric layer.
2. The apparatus of Claim 1, further comprising:
a gate electrode, wherein a voltage applied to the gate electrode is transferred to the dielectric layer and the dielectric layer creates stress on the transition material.
3. The apparatus of Claim 1, wherein the dielectric layer is a piezo-ceramic layer.
4. The apparatus of any of Claims 1-3, wherein stress on the transition material changes the transition material from an insulating material to a conducting material.
5. The apparatus of Claim 1, wherein stress on the transition material allows a current to flow from the source to the drain.
6. The apparatus of any of the Claims 1-3, wherein the dielectric layer is to create stress on the transition material in response to an applied voltage, and the transition material is to undergo a change in conductivity in response to the stress.
7. The apparatus of Claim 6, further comprising:
a OTT insulator between the dielectric layer and the transition material.
8. A method comprising:
depositing transition material between a source and a drain; and depositing a dielectric over the transition material, wherein the dielectric layer is to create stress on the transition material in response to an applied voltage, and the transition material is to undergo a change in conductivity in response to the stress.
9. The method of Claim 8, further comprising:
depositing an insulator over the transition material but under the dielectric.
10. The method of Claim 9, further comprising:
depositing a ground layer over the insulator but under the dielectric; and depositing a gate over the dielectric, wherein a voltage applied to the gate electrode is transferred to the dielectric layer and the dielectric layer creates stress on the transition material.
11. The method of Claim 8, wherein the dielectric is a piezo-ceramic layer.
12. The method of any of Claims 8-11, wherein stress on the transition material changes the transition material from an insulating material to a conducting material.
13. The method of Claim 12, wherein the insulator is a MOTT insulator.
14. A computing device comprising:
a processor mounted on a substrate;
a communications logic unit within the processor;
a memory within the processor;
a graphics processing unit within the computing device;
an antenna within the computing device;
a display on the computing device;
a battery within the computing device;
a power amplifier within the processor; and
a voltage regulator within the processor;
wherein the processor includes: a source;
a drain;
a transition material located between the source and the drain; and a dielectric layer;
wherein the dielectric layer is to create stress on the transition material in response to an applied voltage, and the transition material is to undergo a change in conductivity in response to the stress.
15. The computing device of Claim 14, wherein the processor further includes: a gate electrode, wherein a voltage applied to the gate electrode is transferred to the dielectric layer and the dielectric layer creates stress on the transition material.
16. The computing device of Claim 14, wherein the dielectric layer is a piezo- ceramic layer.
17. The computing device of any of Claims 14-16, wherein stress on the transition material changes the transition material from an insulating material to a conducting material.
18. The computing device of Claim 17, wherein stress on the transition material allows a current to flow from the source to the drain.
19. The computing device of any of Claims 14-16, wherein the processor further includes:
an insulator between the dielectric layer and the transition material.
20. The computing device of Claim 19, wherein the insulator is a MOTT insulator.
21. An integrated circuit (IC) assembly, comprising:
a substrate;
a source; a drain;
a transition material located between the source and the drain; and
a dielectric layer;
wherein the dielectric layer is to create stress on the transition material in response to an applied voltage, and the transition material is to undergo a change in conductivity in response to the stress.
22. The IC assembly of Claim 21, further comprising:
a gate electrode, wherein a voltage applied to the gate electrode is transferred to the dielectric layer and the dielectric layer creates stress on the transition material.
23. The IC assembly of Claim 22, wherein stress on the transition material changes the transition material from an insulating material to a conducting material.
24. The IC assembly of Claim 21, wherein stress on the transition material allows a current to flow from the source to the drain.
25. The IC assembly of any of Claims 21-24, further comprising:
a MOTT insulator between the dielectric layer and the transition material.
PCT/US2015/000387 2015-12-26 2015-12-26 Thin film switching device WO2017111829A1 (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080283870A1 (en) * 2007-05-18 2008-11-20 Sanken Electric Co., Ltd. Field-effect semiconductor device
US20120098589A1 (en) * 2008-12-02 2012-04-26 Spanier Jonathan E Ferroelectric nanoshell devices
EP2546883A2 (en) * 2011-07-15 2013-01-16 International Rectifier Corporation Composite Semiconductor Device with a SOI Substrate Having an Integrated Diode
US20130307513A1 (en) * 2011-12-19 2013-11-21 Han Wui Then High voltage field effect transistors
US20150255547A1 (en) * 2012-03-29 2015-09-10 Agency For Science, Technology And Research III-Nitride High Electron Mobility Transistor Structures and Methods for Fabrication of Same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080283870A1 (en) * 2007-05-18 2008-11-20 Sanken Electric Co., Ltd. Field-effect semiconductor device
US20120098589A1 (en) * 2008-12-02 2012-04-26 Spanier Jonathan E Ferroelectric nanoshell devices
EP2546883A2 (en) * 2011-07-15 2013-01-16 International Rectifier Corporation Composite Semiconductor Device with a SOI Substrate Having an Integrated Diode
US20130307513A1 (en) * 2011-12-19 2013-11-21 Han Wui Then High voltage field effect transistors
US20150255547A1 (en) * 2012-03-29 2015-09-10 Agency For Science, Technology And Research III-Nitride High Electron Mobility Transistor Structures and Methods for Fabrication of Same

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