WO2017111804A1

WO2017111804A1 - Structure for improved shorting margin and time dependent dielectric breakdown in interconnect structures

Info

Publication number: WO2017111804A1
Application number: PCT/US2015/000345
Authority: WO
Inventors: Mauro J. KOBRINSKY; James S. CLARKE; Kanwal J. SINGH; Boyan Boyanov; Alan M. Myers
Original assignee: Intel Corporation
Priority date: 2015-12-24
Filing date: 2015-12-24
Publication date: 2017-06-29

Abstract

A method including forming a dielectric layer on a contact point on a device substrate; forming a barrier layer on the dielectric layer; forming a contact through the dielectric layer and the barrier layer to the contact point; recessing the contact relative to a thickness of the barrier layer; conformally forming a passivation layer on the contact and barrier layer; and forming an opening to the contact. An apparatus including an integrated circuit substrate including a device layer including a plurality of devices; a dielectric layer on the device layer; a barrier layer on the dielectric layer; a first contact through the dielectric layer and the barrier layer to a contact point of the device layer; a passivation layer on the barrier layer; and a second contact disposed through the passivation layer and the barrier layer and coupled to the first contact.

Description

STRUCTURE FOR IMPROVED SHORTING MARGIN AND TIME DEPENDENT DIELECTRIC BREAKDOWN IN INTERCONNECT STRUCTURES

BACKGROUND

Field

Integrated circuit structures and processing.

Description of Related Art

As dimensions of interconnects of an integrated circuit device scale down (width and space), the minimum distance between isolated wires decreases even faster. This minimum distance is generally determined by the spacing between a conductive via and adjacent metal interconnects on the layer below. The rapid decrease in minimum distance is a result of the scaling of the line-line spacing as well as a relatively slow pace of improvement of registration, and further in view of an increased relative importance of line edge roughness compared to spacing. The consequences of the rapid decrease of minimum distance are time- zero shorts and time-dependent dielectric breakdown (TDDB) fails during usage, which impacts yield and interconnect reliability.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 shows a cross-sectional schematic side of a portion of an integrated circuit substrate having a number of devices thereon, an interlayer dielectric layer on the devices and a barrier layer on the interlayer dielectric layer.

Figure 2 shows the structure of Figure 1 following the forming of contacts to the devices.

Figure 3 shows the structure of Figure 2 following the recessing of the contacts relative to the barrier layer.

Figure 4 shows the structure of Figure 3 after depositing a dielectric layer.

Figure 5 shows the structure of Figure 4 after forming a via of opening through the second interlayer dielectric layer and the passivation layer to a contact.

Figure 6 shows the structure of Figure 5 following the forming of a contact in the via.

Figure 7 is an interposer implementing one or more embodiments.

Figure 8 illustrates an embodiment of a computing device. DETAILED DESCRIPTION

Integrated circuit devices including interconnect structures and fabrication processes that provide more distance between adjacent conductors (conductive via to lines on an underlying layer) of an integrated circuit device that is scalable with line-to-line spacing are disclosed. In one embodiment, the structure and method disclosed provide less variability of the space, and more reliable materials in regions generally more susceptible to failures. This results in improved yield and reliability (increased shorting margin and less TDDB) without a capacitance penalty.

In one embodiment, a method is disclosed. The method includes forming a dielectric layer on a contact point on device substrate; forming a barrier layer on the dielectric layer; forming a contact through the dielectric layer and the barrier layer to the contact point;

recessing the contact relative to a thickness of the barrier layer; conformally forming a passivation layer on the contact and barrier layer; and forming an opening to the contact. The opening may be filled with an electrically conductive material to form a contact to the previously formed contact. An apparatus is also disclosed. In one embodiment, an apparatus includes an integrated circuit substrate comprising a device layer comprising a plurality of devices; a dielectric layer on the device layer; a barrier layer on the dielectric layer; a first contact through the dielectric layer and the barrier layer to a contact point of the device layer; a passivation layer on the barrier layer; and a second contact exposed through the passivation layer and the barrier layer and coupled to the first contact.

Figure 1 shows a cross-sectional side view of a portion of an integrated circuit structure, such as a portion of a microprocessor chip in the process of forming an

interconnection to a device or devices on the chip, such devices including circuit devices such as transistors or other interconnections. A typical integrated circuit structure such as a microprocessor chip may have, for example, multiple (e.g., six, seven) electrically conductive interconnection layers or levels separated from one another by interlayer dielectric (ILD) material. Referring to Figure 1, structure 100 includes substrate 1 10 which may be a portion of a semiconductor substrate such as a portion of a silicon wafer having circuit devices, including transistors thereon and optionally as one or more levels of interconnection to such circuit devices. Figure 1 shows devices 120 that may be a circuit device (e.g., a transistor device) formed as part of a device level in or on substrate 1 10 or an interconnection line formed above a device level and connected to a lower level interconnection line and/or to a circuit device(s) at the device level through, for example, a conductive via. It is appreciated that techniques described herein may be used for various interconnections within an integrated circuit including interconnects to devices that include circuit devices and other interconnections. In this sense, contact points 120 represent such devices (circuit devices or interconnections) where an interconnection contact may be made.

Overlying substrate 1 10 in Figure 1 is dielectric layer 130 which is, for example, an ILD material. A representative material for dielectric layer 130 is a material having, for example, a dielectric constant (k) less than the dielectric constant of silicon dioxide (Si0₂) (e.g., a "low k" material). Representative low k material includes materials containing silicon, carbon and oxygen and that are known in the art.

Overlying dielectric layer 130 in Figure 1 is barrier layer 140. In one embodiment, barrier layer 140 is a dielectric material. Suitable materials for barrier material 140 are those materials that have an etch selectivity relative to a material for dielectric layer 130 (e.g., can be etched at a different rate than or exclusive of a material for dielectric layer 130).

Representative materials include Si₃N₄, Si, SiC_xN_y, A1₂0₃, SiO_xC_yNz, SiC and SiO_xC_y. In one embodiment, barrier layer is deposited by, for example, a plasma deposition process. In other embodiments, it is deposited by physical vapor deposition (PVD) or atomic layer deposition (ALD) methods. In one embodiment, barrier layer 140 acts as a hermetic to protect underlying dielectric layer 130 from undesired modification from wet or dry etches used in subsequent processing. In one embodiment, a representative thickness of barrier layer 140 is a thickness that will not significantly affect the overall dielectric constant of the combined layers (dielectric layer 130 + barrier layer 140) but at most will marginally affect such overall dielectric constant. In one embodiment, a representative thickness of barrier layer 140 is on the order of 30 angstroms (A) plus or minus 20 angstroms. In another embodiment, a representative thickness of barrier layer 140 is on the order of 2-10 nanometers (nm).

Figure 2 shows the structure of Figure 1 following the forming of openings or vias through barrier layer 140 and dielectric layer 130 to devices 120 and the deposition of an electrically conductive material (e.g., a metal) in such openings or vias to form respective contacts to devices 120. In one embodiment, to form the vias and contacts in such vias, a surface (a top surface as viewed) of barrier layer 140 is masked with, for example, a hard mask (e.g. Ti or TiN) and photolithographic material and openings are defined through the mask for locations of vias to devices 120. Vias are then formed by etching barrier layer 140 and dielectric layer 130 with respective suitable etchants to expose devices 120 or portions of devices. For example, where device 120 is a transistor device (a circuit device), individual vias may be formed to a gate electrode, a source and to a drain of that device. Once the openings are formed, such openings are filled with an electrically conductive material such as a metal (e.g., tungsten, copper) to form contacts 150. Once the contacts are formed, the mask is removed from a surface of barrier layer 140. In one embodiment, where devices 120 are circuit devices in or on a device layer of substrate 1 10, contacts 150 are a material such as tungsten (tungsten plugs) and are formed as individual contacts. Where devices 120 are interconnections (e.g., metal lines, traces), contacts 150 may be formed along with a formation of a subsequent interconnection layer or level on a surface of barrier layer 140 (a superior surface as viewed). In such instance,metal lines or trenches and vias are defined. In one embodiment, pitch multiplication techniques are used for defining the interconnect trenches, and multiple lithographic masks are used to define the vias. In one embodiment, a conductive seed material is introduced after etching the trenches and vias on the surface of barrier layer 140 In one embodiment, this seed material is deposited by PVD techniques; in another embodiment ALD or CVD techniques are used, The seed may include one or multiple layers, some of which may serve as barrier or containment for the main conductive metal that is subsequently deposited. Following, a conductive material such as copper may be introduced through an electroplating process into the vias to form contacts 150 and on a surface of barrier layer 140 to form metal lines (traces) defining such subsequent

interconnection layer. The undesired seed material is then removed.

Following the deposition of conductive material to form contacts 150 in structure 100, a surface of barrier layer 140 and contacts 150 may be polished to planarize such surface.

Figure 3 shows the structure of Figure 2 following the recessing of contacts 150 relative to a thickness of barrier layer 140. In one embodiment, one technique for recessing contacts 150 is by way of wet or dry etches of the metal selective to dielectrics 130 and 140. In the embodiment of Figure 3, contacts 150 are recessed to have a surface that is planar with a surface of dielectric layer .130 (a top surface as viewed). It is appreciated that contacts 150 need not be recessed to a level to be planar with a surface of dielectric layer 130 but may instead be recessed relative to a surface of barrier layer 140 to a larger or lesser extent (e.g., recessed below barrier layer 140 but above a surface of dielectric layer 130 or recessed below a surface of dielectric layer 130).

Figure 4 shows the structure of Figure 3 following the introduction of a passivation layer and subsequent dielectric layer on structure 100. Referring to Figure 4, in this embodiment, passivation layer 160 is, in one embodiment, conformably introduced on a surface of the structure and conforms to the surface profile with the recessed contacts relative to barrier layer 140. In one embodiment, passivation layer 160 is introduced by a plasma deposition process to a thickness that will not significantly affect an overall dielectric constant of an ILD. A suitable material for passivation layer 140 is a dielectric material that will have an etch selectivity relative to a material for barrier layer 140, specifically will etch, for a particular etchant, at a faster or greater rate than a material of barrier layer 140.

Representatively, where barrier layer 140 is Si₃N₄, a suitable material for passivation layer 160 is SiC or A1₂0₃ or a bilayer of A1₂0₃ and SiC. A representative thickness for passivation layer 160 is on the order of 2-10 nm.

Disposed on passivation layer 160 in structure 100 illustrated in Figure 4 is dielectric layer 170 that is an ILD material similar to dielectric layer 130 (e.g., a low k dielectric material). Dielectric layer 170 may be introduced according to conventional techniques.

Figure 5 shows the structure of Figure 4 following the forming of a trench in dielectric layer 170 and a via through dielectric layer 170 and passivation layer 160 to one of underlying contacts 150. In one embodiment, trench 185 is formed in a surface of dielectric layer 170 as part of a process of forming an interconnect layer and via 180 is formed through the previously defined trench through dielectric layer 170 and passivation layer 160 to an underlying contact. To form trench 185, a surface of dielectric layer 170 is masked with, for example, a photolithographic material and the trench is formed by an etch process. Next, a mask is patterned in the trench area for a via opening through dielectric layer 170 and passivation layer is defined over an area above the desired contact 150. An etch is then performed to remove dielectric layer 170 and passivation layer 160 and expose contact 150 through via or opening 180. It is appreciated that registration of an opening directly over a desired contact may not always be possible. In certain instances, such openings may be offset such that only a portion of the underlying contact is exposed through opening 180. In one embodiment, there is a desire that, given such offset, a possibility of shorts to, for example, another contact be avoided. Figure 5 illustrates that opening 180 may be steered (via steering) by etch rates of dielectric materials. Specifically, Figure 5 shows that where an etch rate of barrier layer 140 is slower than an etch rate for passivation layer 160 for a given etchant, the opening may be steered toward a desired contact 150. As a result, for an anisotropic etch, an etch process will remove a greater volume of passivation layer 160 than barrier layer 140. The etch rate difference of a given etchant through barrier layer 140 forms an opening having a cross-sectional area, A₂, that is less than a cross-sectional area of an opening, Ai, through passivation layer 160. Where passivation layer 160 is SiC, A1₂0₃ or a bilayer of Sic and A1₂0₃ and barrier layer 140 is Si₃N₄, suitable etchants to produce an etch rate difference (an etch of barrier layer 140 is slower than an etch of passivation layer 160) include, but are not limited to, CF₄, CHF₃, C₄F₈, NH₃.

Figure 6 shows the structure of Figure 5 following the deposition of an electrically conductive material such as a metal into via or opening 180. Figure 6 shows conductive material of, for example, copper that may be introduced by an electroplating process to contact underlying contact 150 (forming contact 190). A conductive line (trace) may also be formed at the same time on a surface of dielectric layer 170 (a top surface as viewed) and connected to contact 190. Figure 6 also illustrates a shorting margin, W, taken from a base of contact 190. The shorting margin, W, is greater due to reduced area (A₂, see Figure 5) at the base of contact 190 than a shorting margin if the contact has a base with area, Ai . As a further benefit, the via is contained within layer 140, which can be selected to have better breakdown characteristics than the material 130, which is selected to have lower dielectric constant k (generally speaking, the lower the k, the poorer the dielectric breakdown and TDDB characteristics). In this way, TDDB and dielectric berakdown can be optimized with minimal impact to the overall capacitance (or effective dielectric constant k of the layer).

Figure 7 illustrates interposer 200 that includes one or more embodiments. Interposer 200 is an intervening substrate used to bridge a first substrate 202 to second substrate 204. First substrate 202 may be, for instance, an integrated circuit die. Second substrate 204 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of interposer 200 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, interposer 200 may couple an integrated circuit die to ball grid array (BGA) 206 that can subsequently be coupled to second substrate 204. In some embodiments, first and second substrates 202/204 are attached to opposing sides of interposer 200. In other embodiments, first and second substrates 202/204 are attached to the same side of interposer 200. In further embodiments, three or more substrates are interconnected by way of interposer 200.

Interposer 200 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

The interposer may include metal interconnects 208 and vias 210, including but not limited to through-silicon vias (TSVs) 212. Interposer 200 may further include embedded devices 214, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio- frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on interposer 200.

In accordance with embodiments, apparatuses or processes disclosed herein may be used in the fabrication of interposer 200.

Figure 8 illustrates computing device 300 in accordance with one embodiment.

Computing device 300 may include a number of components. In one embodiment, these components are attached to one or more motherboards. In an alternate embodiment, these components are fabricated onto a single system-on-a-chip (SoC) die rather than a

motherboard. The components in computing device 300 include, but are not limited to, integrated circuit die 302 and at least one communication chip 308. In some implementations communication chip 308 is fabricated as part of integrated circuit die 302. Integrated circuit die 302 may include CPU 304 as well as on-die memory 306, often used as cache memory, that can be provided by technologies such as embedded DRAM (eDRAM) or spin-transfer torque memory (STTM or STTM-RAM).

Computing device 300 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within an SoC die.

These other components include, but are not limited to, volatile memory 310 (e.g., DRAM), non- volatile memory 312 (e.g., ROM or flash memory), graphics processing unit 314 (GPU), digital signal processor 316, crypto processor 342 (a specialized processor that executes cryptographic algorithms within hardware), chipset 320, antenna 322, display or a

touchscreen display 324, touchscreen controller 326, battery 328 or other power source, a power amplifier (not shown), global positioning system (GPS) device 344, compass 330, motion coprocessor or sensors 332 (that may include an accelerome^'ter, a gyroscope, and a compass), speaker 334, camera 336, user input devices 338 (such as a keyboard, mouse, stylus, and touchpad), and mass storage device 340 (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

Communications chip 308 enables wireless communications for the transfer of data to and from computing device 300. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. Communication chip 308 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.1 1 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. Computing device 300 may include a plurality of communication chips 308. For instance, a first communication chip may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second

communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

Processor 304 of computing device 300 includes one or more devices, such as transistors or metal interconnects including contacts thereto as described in embodiments. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

Communication chip 308 may also include one or more devices, such as transistors or metal interconnects including contacts thereto as described in embodiments.

In further embodiments, another component housed within computing device 300 may contain one or more devices, such as transistors or metal interconnects including contacts thereto as described in embodiments.

In various embodiments, computing device 300 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, computing device 300 may be any other electronic device^' that processes data.

EXAMPLES

Example 1 is a method including forming a dielectric layer on a contact point on a device substrate; forming a barrier layer on the dielectric layer; forming a contact through the dielectric layer and the barrier layer to the contact point; recessing the contact relative to a thickness of the barrier layer; conformally forming a passivation layer on the contact and barrier layer; and forming an opening to the contact.

In Example 2, forming the opening of the method of Example 1 includes etching.

In Example 3, etching of the method of Example 2 includes etching through a portion of the barrier layer. In Example 4, the passivation layer of the method of Example 3 includes a different etch rate than an etch rate of the barrier layer for an etchant.

In Example 5, an etch rate of the barrier layer of the method of Example 4 is slower than an etch rate of the passivation layer for the etchant.

In Example 6, the dielectric layer of the method of any of Examples 1 -4 includes a first dielectric layer, the method further including forming a second dielectric layer on the passivation layer and forming an opening to the contact includes forming an opening through the second dielectric layer and the passivation layer.

In Example 7, the first dielectric layer and the second dielectric layer of the method of Example 6 include the same material.

In Example 8, recessing the contact relative to a thickness of the barrier layer of the method of any of Examples 1-7 includes recessing the contact to a level of the dielectric layer, or a level below a surface of the dielectric layer or a level above the surface of the dielectric layer.

In Example 9, recessing the contact relative_^to a thickness of the barrier layer of the method of any of Examples 1-7 includes recessing the contact to a level below a surface of the dielectric layer.

In Example 10, recessing the contact relative to a thickness of the barrier layer of the method of any of Examples 1-7 includes recessing the contact to a level above a surface of the dielectric layer.

In Example 1 1 , the contact of the method of any of Examples 1-10 includes a first contact, the method further includes forming a second contact in the opening.

Example 12 is an apparatus including an integrated circuit substrate including a device layer including a plurality of devices; a dielectric layer on the device layer; a barrier layer on the dielectric layer; a first contact through the dielectric layer and the barrier layer to a contact point of the device layer; a passivation layer on the barrier layer; and a second contact disposed through the passivation layer and the barrier layer and coupled to the first contact.

In Example 13, the dielectric layer of the apparatus of Example 12 includes a first dielectric layer, the apparatus further including a second dielectric layer on the first dielectric layer, wherein the second contact is disposed through the second dielectric layer.

In Example 14, the second contact of the apparatus of Example 12 is formed in an opening through the passivation layer and the barrier layer and a dimension of the opening is through the passivation layer is larger than a dimension of the opening through the barrier layer.

In Example 15, an etch rate of the barrier layer of the apparatus of Example 14 is slower than an etch rate of the passivation layer for an etchant.

Example 16 is an apparatus including an integrated circuit substrate including a device layer including a plurality of devices; a dielectric layer on the device layer; a first contact through the dielectric layer; a barrier layer on the dielectric layer a passivation layer on the barrier layer, wherein an etch rate of the passivation layer is greater than an etch rate of the barrier layer for a particular etchant; and a second contact disposed through the passivation layer and the barrier layer and coupled to the first contact.

In Example 17, the dielectric layer of the apparatus of Example 16 includes a first dielectric layer, the apparatus further including a second dielectric layer on the first dielectric layer, wherein the second contact is disposed through the second dielectric layer.

In Example 18, the second contact is formed in an opening through the passivation layer and the barrier layer and a dimension of the opening is through the passivation layer is larger than a dimension of the opening through the barrier layer.

In Example 19, the first contact of the apparatus of Example 16 is recessed relative to a surface of the barrier layer.

In Example 20, the surface of the first contact of the apparatus of Example 19 is recessed to a level that is planar with a surface of the dielectric layer. ₍

In Example 21 , the surface of the first contact of the apparatus of Example 19 is recessed to a level below a surface of the barrier layer but above a surface of the dielectric layer.

In Example 22, the surface of the first contact of the apparatus of Example 19 is recessed below a surface of the dielectric layer.

The above description of illustrated implementations, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific implementations of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope, as those skilled in the relevant art will recognize.

These modifications may be made in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific implementations disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordar^ce with established doctrines of claim interpretation.

Claims

1. A method comprising:

forming a dielectric layer on a contact point on a device substrate;

forming a barrier layer on the dielectric layer;

forming a contact through the dielectric layer and the barrier layer to the contact point;

recessing the contact relative to a thickness of the barrier layer;

conformally forming a passivation layer on the contact and barrier layer; and forming an opening to the contact.

2. The method of claim 1, wherein forming the opening comprises etching.

3. The method of claim 2, wherein etching comprises etching through a portion of the barrier layer.

4. The method of claim 3, wherein the passivation layer comprises a different etch rate than an etch rate of the barrier layer for an etchant.

5. The method of claim 4, wherein an etch rate of the barrier layer is slower than an etch rate of the passivation layer for the etchant.

6. The method of claim 1, wherein the dielectric layer comprises a first dielectric layer, the method further comprising forming a second dielectric layer on the passivation layer and forming an opening to the contact comprises forming an opening through the second dielectric layer and the passivation layer.

7. The method of claim 6, wherein the first dielectric layer and the second dielectric layer comprise the same material.

8. The method of claim 1, wherein recessing the contact relative to a thickness of the barrier layer comprises recessing the contact to a level of a surface of the dielectric layer.

9. The method of claim 1 , wherein recessing the contact relative to a thickness of the barrier layer comprises recessing the contact to a level below a surface of the dielectric layer.

10. The method of claim 1, wherein recessing the contact relative to a thickness of the barrier layer comprises recessing the contact to a level above a surface of the dielectric layer.

11. The method of claim 1, wherein the contact comprises a first contact, the method further comprises forming a second contact in the opening.

12. An apparatus comprising:

an integrated circuit substrate comprising a device layer comprising a plurality of devices;

a dielectric layer on the device layer;

a barrier layer on the dielectric layer;

a first contact through the dielectric layer and the barrier layer to a contact point of the device layer;

a passivation layer on the barrier layer; and

a second contact disposed through the passivation layer and the barrier layer and coupled to the first contact.

13. The apparatus of claim 12, wherein the dielectric layer comprises a first dielectric layer, the apparatus further comprising a second dielectric layer on the first dielectric layer, wherein the second contact is disposed through the second dielectric layer.

14. The apparatus of claim 12, wherein the second contact is formed in an opening through the passivation layer and the barrier layer and a dimension of the opening is through the passivation layer is larger than a dimension of the opening through the barrier layer.

15. The apparatus of claim 14, wherein an etch rate of the barrier layer is slower than an etch rate of the passivation layer for an etchant.

16. An apparatus comprising:

a dielectric layer on the device layer; a first contact through the dielectric layer;

a barrier layer on the dielectric layer

a passivation layer on the barrier layer, wherein an etch rate of the passivation layer is greater than an etch rate of the barrier layer for a particular etchant; and

17. The apparatus of claim 16, wherein the dielectric layer comprises a first dielectric layer, the apparatus further comprising a second dielectric layer on the first dielectric layer, wherein the second contact is disposed through the second dielectric layer.

18. The apparatus of claim 17, wherein the second contact is formed in an opening through the passivation layer and the barrier layer and a dimension of the opening is through the passivation layer is larger than a dimension of the opening through the barrier layer.

19. The apparatus of claim 16, wherein a surface of the first contact is recessed relative to a surface of the barrier layer.

20. The apparatus of claim 19, wherein the surface of the first contact is recessed to a level that is planar with a surface of the dielectric layer.

21. The apparatus of claim 19, wherein the surface of the first contact is recessed to a level below a surface of the barrier layer but above a surface of the dielectric layer.

22. The apparatus of claim 19, wherein the surface of the first contact is recessed below a surface of the dielectric layer.