WO2017098603A1 - Nitride semiconductor device - Google Patents

Nitride semiconductor device Download PDF

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Publication number
WO2017098603A1
WO2017098603A1 PCT/JP2015/084524 JP2015084524W WO2017098603A1 WO 2017098603 A1 WO2017098603 A1 WO 2017098603A1 JP 2015084524 W JP2015084524 W JP 2015084524W WO 2017098603 A1 WO2017098603 A1 WO 2017098603A1
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Prior art keywords
nitride semiconductor
semiconductor device
electrode portion
drain electrode
gate
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PCT/JP2015/084524
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French (fr)
Japanese (ja)
Inventor
裕太郎 山口
新庄　真太郎
山中　宏治
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三菱電機株式会社
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Priority to PCT/JP2015/084524 priority Critical patent/WO2017098603A1/en
Publication of WO2017098603A1 publication Critical patent/WO2017098603A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate

Definitions

  • the present invention relates to a nitride semiconductor device such as a high electron mobility transistor (hereinafter referred to as HEMT) formed of a nitride semiconductor such as GaN on a conductive substrate such as a Si substrate.
  • a nitride semiconductor device such as a high electron mobility transistor (hereinafter referred to as HEMT) formed of a nitride semiconductor such as GaN on a conductive substrate such as a Si substrate.
  • HEMT high electron mobility transistor
  • Gallium nitride has superior characteristics in terms of breakdown voltage and saturation speed than semiconductor materials such as gallium arsenide (GaAs) and silicon (Si), and is used in microwave high-power high-frequency amplifiers as HEMTs. Yes.
  • the HEMT used for the microwave amplifier is formed on a substrate such as semi-insulating sapphire or silicon carbide (SiC) having as little parasitic capacitance as possible.
  • SiC silicon carbide
  • Non-Patent Document 1 describes a HEMT formed by containing GaN on a Si substrate.
  • the HEMT described in Non-Patent Document 1 includes a strip-shaped source electrode portion arranged side by side on an upper layer of a barrier layer, and a gate electrode portion arranged between the source electrode portions and extending in a bifurcated manner from the base portion. . Further, in this HEMT, one strip-shaped drain electrode portion is disposed between the gate electrode portions.
  • the HEMT formed with GaN on the Si substrate has a problem that the output power is drastically reduced at a high temperature as compared with the HEMT formed with GaN on the semi-insulating substrate. This is considered to be due to the increase in high-frequency leakage power due to the increase in intrinsic carriers in the Si substrate due to the temperature rise and the accompanying increase in parasitic capacitance. Therefore, in order to suppress such high frequency leakage power, it is necessary to reduce the parasitic capacitance.
  • the parasitic capacitance is generated between an intrinsic carrier generated at the interface between the buffer layer such as aluminum gallium nitride (AlGaN) and aluminum nitride (AlN) and the Si substrate and the drain electrode portion and the source electrode portion at a high temperature. It is formed.
  • this capacity is referred to as Csub.
  • the capacitance Csub can be regarded as a parallel plate capacitance between the intrinsic carrier and the drain electrode portion, for example, in order to reduce the capacitance Csub, the GaN channel layer or the AlGaN buffer layer is thickened or the width of the drain electrode portion is reduced. Should be narrowed. However, when the channel layer and the buffer layer are thickened, it is necessary to change the conditions of the epitaxial growth process, which may increase the cost. For this reason, in consideration of commercialization of HEMT, it is better to adopt a narrow width of the drain electrode portion.
  • the HEMT described in Non-Patent Document 1 has a structure in which the width of the drain electrode portion and the gate pitch, which is the distance between adjacent gate electrode portions, are approximately the same length.
  • the width of the drain electrode portion and the gate pitch are made substantially the same length because the distance between the gate electrode portion and the drain electrode portion is generally compared with the width of the drain electrode portion or the gate pitch. This is because the distance between the gate electrode portion and the drain electrode portion is negligible.
  • the gate pitch is also narrowed accordingly. For this reason, a thermal resistance increases and a big performance degradation by heat will be caused.
  • the thermal conductivity of Si is 168 (W / mK), which is lower than that of SiC having a thermal conductivity of 350 (W / mK), an increase in thermal resistance leads to significant performance degradation.
  • An object of the present invention is to provide a nitride semiconductor device that can reduce parasitic capacitance generated between an intrinsic carrier and a drain electrode portion and suppress an increase in thermal resistance. .
  • the nitride semiconductor device includes a channel layer, a barrier layer, a source electrode part, a gate electrode part, a drain electrode part, and an ion implantation part.
  • the channel layer is a layer where electrons travel.
  • the barrier layer is formed to contain at least one of indium, aluminum, and gallium and nitrogen in the upper layer of the channel layer to form a two-dimensional electron gas in the channel layer.
  • the strip-shaped source electrode portion is arranged side by side on the upper layer of the barrier layer.
  • the gate electrode portion is disposed between adjacent source electrode portions and extends in a bifurcated manner from the base portion.
  • the drain electrode portion is disposed between the adjacent gate electrode portions and extends bifurcated from the base portion.
  • the ion implantation part insulates a region between adjacent drain electrode parts.
  • the gate electrode portion disposed between the source electrode portions on the barrier layer and extending in a bifurcated manner from the base portion, and the drain disposed between the gate electrode portions and extending in a bifurcated manner from the base portion.
  • An ion implantation part is provided for bringing the region between the electrode part and the drain electrode part into an insulating state.
  • FIG. 1A is a plan view showing a pattern layout of a nitride semiconductor device according to Embodiment 1 of the present invention
  • FIG. 1B is a plan view showing a pattern layout of a conventional nitride semiconductor device
  • FIG. 1B is a cross-sectional view showing the configuration of the nitride semiconductor device according to the first embodiment taken along line AA in FIG. 1A
  • FIG. 3A is a graph showing the relationship between the capacitance Csub and the width of the drain electrode portion in the nitride semiconductor device according to the first embodiment and the conventional nitride semiconductor device.
  • FIG. 1A is a plan view showing a pattern layout of a nitride semiconductor device according to Embodiment 1 of the present invention
  • FIG. 1B is a plan view showing a pattern layout of a conventional nitride semiconductor device.
  • FIG. 1B is a cross-sectional view showing the configuration of the nitride semiconductor device according to the first embodiment taken along
  • 3B is a graph showing the relationship between the thermal resistance Rth and the width of the drain electrode portion in the nitride semiconductor device according to the first embodiment and the conventional nitride semiconductor device. It is sectional drawing which shows the structure of the nitride semiconductor device which concerns on Embodiment 2 of this invention. It is a top view which shows the pattern layout of the nitride semiconductor device which concerns on Embodiment 3 of this invention. It is a top view which shows another pattern layout of the nitride semiconductor device which concerns on Embodiment 3 of this invention. It is a top view which shows the pattern layout of the nitride semiconductor device which concerns on Embodiment 4 of this invention.
  • FIG. 1A is a plan view showing a pattern layout of nitride semiconductor device 1 according to the first embodiment of the present invention, and shows a case where nitride semiconductor device 1 is a HEMT formed of a nitride semiconductor.
  • FIG. 1B is a plan view showing the pattern layout of the conventional nitride semiconductor device 100, and shows a case where the nitride semiconductor device 100 is a HEMT formed of a nitride semiconductor.
  • FIG. 2 is a cross-sectional view showing nitride semiconductor device 1 taken along line AA in FIG. 1A.
  • FIG. 1A, FIG. 1B, and FIG. 2 there are actually element isolation regions, wirings, and the like, but they are not described because they are not related to the characteristic portions of nitride semiconductor device 1. Further, the HEMT of the nitride semiconductor device 1 is applicable not only to the microwave amplifier but also to a power device that operates at a driving frequency of about MHz.
  • the gate electrode 101 includes a gate pad 101a and gate electrode portions 101b and 101b extending in a bifurcated manner from the gate pad 101a.
  • a plurality of strip-like source electrode portions 102 and 102 are formed side by side, and the gate electrode portions 101b and 101b are disposed between adjacent source electrode portions 102 and 102.
  • the drain electrode 103 includes a drain pad 103a and one strip-shaped drain electrode portion 103b extending from the drain pad 103a. As shown in FIG. 1B, the drain electrode portion 103b is disposed between the adjacent gate electrode portions 101b and 101b.
  • the gate electrode 2 includes a gate pad 2a as a base and gate electrode portions 2b and 2b extending in a bifurcated manner from the gate pad 2a.
  • a plurality of strip-like source electrode portions 3, 3 are formed side by side, and the gate electrode portions 2 b, 2 b are arranged between the adjacent source electrode portions 3, 3.
  • the drain electrode 4 includes a drain pad 4a, which is a base, and drain electrode portions 4b and 4b extending bifurcated from the drain pad 4a. As shown in FIG. 1A, the drain electrode portions 4b and 4b are disposed between the adjacent gate electrode portions 2b and 2b.
  • an ion implanted portion 6 is formed by implanting ions such as argon (Ar) and zinc (Zn).
  • the ion implantation part 6 makes the said area
  • the ions to be implanted are not limited to Ar and Zn, and any ions may be used as long as the implanted region is in an insulating state.
  • the nitride semiconductor device 1 is formed on a substrate 7.
  • a substrate formed of a semiconductor material that can be conductive, such as Si is used.
  • the buffer layer 8 is a layer inserted between the substrate 7 and the channel layer 9 for the purpose of improving the crystallinity of the channel layer 9 and confining electrons in the channel layer 9.
  • the buffer layer 8 can be formed with various structures such as AlN, AlGaN, GaN / InGaN, AlN / AlGaN, and their superlattices.
  • the channel layer 9 is a layer through which electrons necessary for transistor operation travel, and is formed in the upper layer of the buffer layer 8.
  • a typical channel layer 9 is made of GaN, but can be formed of InGaN, AlGaN, or a multilayer structure thereof. Further, by implanting impurities into the channel layer 9, the gate controllability of the HEMT can be improved.
  • impurities iron (Fe) and carbon (C), which are transition metals that make the semiconductor semi-insulating, are used. Any impurity implantation profile may be used.
  • the barrier layer 10 is a layer that is formed on the channel layer 9 so as to contain at least one of In, Al, and Ga and nitrogen (N) to form a two-dimensional electron gas in the channel layer 9.
  • An AlGaN single layer is often used as the barrier layer 10, but other than this, a combination of a plurality of AlGaN, a combination of AlGaN and GaN, and a combination of AlGaN and AlN may be used. .
  • the interface where the channel layer 9 and the barrier layer 10 are in contact is formed by a heterojunction having a wider band gap than the channel layer 9.
  • the gate electrode 2, the source electrode portion 3, the drain electrode 4, and the ion implantation portion 6 are formed in the upper layer of the barrier layer 10.
  • the ion implantation part 6 has a cross-sectional structure with a depth reaching the substrate 7 as shown in FIG.
  • the insulating layer 11 is formed between the gate electrode part 2b and the source electrode part 3 and between the gate electrode part 2b and the drain electrode part 4b in the upper layer of the barrier layer 10, and suppresses trapping of the surface of the barrier layer 10 It is a layer to do.
  • an insulating film containing Si that can function as a donor, such as SiN or SiO, is often used. That is, Si contained in the insulating layer 11 supplies electrons to the barrier layer 10 as a donor, whereby the number of traps on the surface of the barrier layer 10 can be reduced.
  • the insulating layer 12 is formed so as to cover the gate electrode portion 2b between the source electrode portion 3 and the drain electrode portion 4b.
  • SiN, SiO 2 , Al 2 O 3 or the like is used as a coverage material.
  • the present invention is not limited to these materials.
  • the source electrode portion 3 and the drain electrode 4 are electrodes for taking out electrons (current) traveling through the channel layer 9 to the outside of the HEMT. For this reason, the source electrode portion 3 and the drain electrode 4 are formed so that the resistance between the two-dimensional electron gas is as small as possible.
  • the source electrode portion 3 and the drain electrode 4 are formed so as to be in contact with the upper surface of the barrier layer 10, but may be formed so as to be in contact with the two-dimensional electron gas in the barrier layer 10. Further, an n + region may be formed under the source electrode portion 3 and the drain electrode 4.
  • vias 5 connected to the back surface of the substrate 7 are formed in the source electrode portions 3 and 3, and the vias 5 are electrically connected to the ground plane on the back surface of the substrate 7.
  • the gate electrode 2 is formed to include a metal in Schottky contact with the barrier layer 10, and transistor operation is realized by controlling the two-dimensional electron gas concentration in the lower layer of the gate electrode 2.
  • the nitride semiconductor device 100 shown in FIG. 1B has the same cross-sectional structure as FIG. 2 described above except for the ion implantation portion 6. That is, the HEMT of the nitride semiconductor device 100 also has a buffer layer, a channel layer, and a barrier layer on the substrate, and the pattern shown in FIG. 1B is formed on the barrier layer.
  • the HEMT formed on the Si substrate containing GaN has high concentration holes of intrinsic carriers at the interface between the substrate 7 and the buffer layer 8 as described above. Such a high-concentration hole forms a high-frequency leak path from the drain electrode 4 to the source electrode portion 3 via the capacitor Csub.
  • the width Wd of the drain electrode portion 103b In order to reduce the power leaked through such a high-frequency leak path, it is conceivable to reduce the width Wd of the drain electrode portion 103b.
  • the conventional nitride semiconductor device 100 is formed so that the width Wd of the drain electrode portion 103b and the gate pitch Lgg are substantially the same, if the width Wd of the drain electrode portion 103b is narrowed, the gate is accompanied accordingly.
  • the pitch Lgg is also narrowed. For this reason, it is possible to reduce the capacitance Csub by narrowing the width Wd of the drain electrode portion 103b.
  • the gate pitch Lgg is also reduced correspondingly, and the thermal resistance Rth is increased.
  • the drain electrode 4 includes drain electrode portions 4b and 4b extending bifurcated from the drain pad 4a, and these drain electrode portions 4b and 4b are gate electrodes. It arrange
  • the width Wd of the drain electrode portion 4b and the gate pitch Lgg between the adjacent gate electrode portions 2b and 2b do not need to be the same size, and these dimensions can be determined independently. Therefore, since the width Wd of the drain electrode portion 4b can be narrowed and the gate pitch Lgg can be kept wide, it is possible to suppress an increase in the thermal resistance Rth and reduce the capacitance Csub.
  • the region between the adjacent drain electrode portions 4 b and 4 b is insulated by the ion implantation portion 6. That is, since the two-dimensional electron gas does not exist in this region, the drain electrode portions 4 b and 4 b are not electrically connected by the two-dimensional electron gas in the channel layer 9.
  • FIG. 3A is a graph showing the relationship between the capacitance Csub and the width of the drain electrode portion in the nitride semiconductor device 1 according to the first embodiment and the conventional nitride semiconductor device 100.
  • the relationship of the capacitance Csub with respect to the width Wd of the drain electrode portion shown in FIG. 3A is obtained by calculating the dependence of the S parameter on the width Wd based on the results of device simulation of the structure according to the first embodiment and the conventional structure. is there.
  • the gate pitch Lgg is fixed to 30 ( ⁇ m)
  • the width Wd of the drain electrode portion 103b and the gate pitch Lgg are the same.
  • the bias conditions are a gate voltage Vg of ⁇ 5 (V) and a drain voltage Vd of 50 (v).
  • the result of the structure according to Embodiment 1 is a rhombus-shaped ( ⁇ ) plot
  • the result of the conventional structure is a quadrangular ( ⁇ ) plot.
  • the capacitance Csub the structure C according to the first embodiment and the conventional structure have the same capacitance Csub at the same width Wd, and as indicated by an arrow in FIG. 3A, the capacitance Csub is reduced as the width Wd becomes narrower. Has been reduced.
  • FIG. 3B is a graph showing the relationship between the thermal resistance Rth and the width of the drain electrode portion in the nitride semiconductor device 1 according to the first embodiment and the conventional nitride semiconductor device 100.
  • the dependence of the thermal resistance Rth on the width Wd shown in FIG. 3B is calculated by the 45 degree method for the structure according to Embodiment 1 and the conventional structure.
  • the thickness of the Si substrate is 60 ⁇ m.
  • the gate pitch Lgg is fixed to 30 ( ⁇ m).
  • the width Wd of the drain electrode portion 103b and the gate pitch Lgg are the same.
  • the result of the structure according to the first embodiment is a rhombus ( ⁇ ) plot
  • the result of the conventional structure is a square ( ⁇ ) plot.
  • FIG. 3B it can be seen that in the conventional structure, the thermal resistance Rth increases as the width Wd of the drain electrode portion 103b is reduced.
  • the gate pitch Lgg is fixed to 30 ( ⁇ m) even when the width Wd of the drain electrode portion 4b is narrowed. Increase is suppressed.
  • the nitride semiconductor device 1 is arranged between the source electrode portions 3 and 3 on the barrier layer 10 and extends in a bifurcated manner from the gate pad 2a. 2b. Further, the drain electrode portions 4b and 4b that are arranged between the gate electrode portions 2b and 2b and extend bifurcated from the drain pad 4a, and the ion implantation portion that insulates the region between the drain electrode portions 4b and 4b. 6 is provided.
  • the dimension of the width Wd of the drain electrode part 4b and the dimension of the gate pitch Lgg between the adjacent gate electrode parts 2b, 2b can be determined independently, and the drain electrode part 4b It is possible to narrow the width Wd and widen the gate pitch Lgg.
  • the width Wd of the drain electrode portion 4b By reducing the width Wd of the drain electrode portion 4b, the capacitance Csub generated between the intrinsic carrier and the drain electrode portion 4b at a high temperature is reduced.
  • the increase in the thermal resistance Rth can be suppressed by increasing the gate pitch Lgg.
  • FIG. 4 is a cross-sectional view showing a configuration of a nitride semiconductor device 1A according to the second embodiment of the present invention, and shows a state cut along the line AA in FIG. 1A.
  • FIG. 4 shows the case where the nitride semiconductor device 1A is a HEMT formed of a nitride semiconductor.
  • an element isolation region, wiring, and the like actually exist, but are not described because they are not related to the characteristic portion of the nitride semiconductor device 1A.
  • the same components as those in FIGS. 1A and 2 are denoted by the same reference numerals and description thereof is omitted.
  • gate field plate 13 and source field plate 14 are added to the configuration of the first embodiment.
  • the gate field plate 13 is formed along the gate electrode portion 2b in the upper layer of the gate electrode portion 2b, and has a function of relaxing the electric field concentration at the end of the gate electrode portion 2b on the drain electrode portion 4b side. .
  • the source field plate 14 is formed so as to protrude from the end of the source electrode portion 3 on the drain electrode portion 4b side, and similarly to the gate field plate 13, the drain in the gate electrode portion 2b is formed. Electric field concentration at the end on the electrode part 4b side is reduced. Although the ability to alleviate electric field concentration is lower than when both the gate field plate 13 and the source field plate 14 are provided, a configuration including any one of these may be used.
  • nitride semiconductor device 1 ⁇ / b> A includes at least one of gate field plate 13 and source field plate 14. With this configuration, the electric field concentration at the end of the gate electrode portion 2b on the drain electrode portion 4b side is alleviated. Thereby, the fall of the pressure resistance performance of HEMT of nitride semiconductor device 1A can be controlled.
  • FIG. 5 is a plan view showing a pattern layout of nitride semiconductor device 1B according to the third embodiment of the present invention, and shows a case where nitride semiconductor device 1B is a HEMT formed of a nitride semiconductor. .
  • nitride semiconductor device 1B is a HEMT formed of a nitride semiconductor.
  • FIG. 5 an element isolation region, wiring, and the like actually exist, but are not described because they are not related to the characteristic portion of the nitride semiconductor device 1B.
  • symbol is attached
  • an ion implantation unit 15 is added to the configuration of the first embodiment.
  • the ion implantation part 15 embodies the pad-side ion implantation part in the present invention, and as shown in FIG. 5, is formed in the drain pad 4a and the surrounding lower layer region to insulate the region.
  • ions to be implanted include ions such as Ar and Zn, but any ions may be used as long as the implanted region is in an insulating state.
  • the ion implantation part 15 has a cross-sectional structure having a depth reaching the substrate 7 as in the case of the ion implantation part 6 shown in FIG.
  • FIG. 5 shows the case where the ion implantation part 15 is formed in the drain pad 4a and the surrounding lower layer, it is sufficient that the ion implantation part 15 is formed at least in the lower layer region of the drain pad 4a. Even if comprised in this way, the effect similar to the above is acquired.
  • FIG. 6 is a plan view showing a pattern layout of nitride semiconductor device 1C according to the third embodiment of the present invention, and shows a case where nitride semiconductor device 1C is a HEMT formed of a nitride semiconductor. . Also in FIG. 6, there are actually element isolation regions, wirings, etc., but the description is omitted because they are not related to the characteristic portions of the nitride semiconductor device 1C. Moreover, the same code
  • an ion implantation unit 16 is added to the configuration of the first embodiment.
  • the ion implantation portion 16 embodies the pad-side ion implantation portion in the present invention, and is formed in the gate pad 2a and the surrounding lower region as shown in FIG.
  • ions to be implanted include ions such as Ar and Zn, but any ions may be used as long as the implanted region is in an insulating state.
  • the ion implantation part 16 has a cross-sectional structure having a depth reaching the substrate 7, similarly to the ion implantation part 6 shown in FIG. 2.
  • FIG. 6 shows the case where the ion implantation portion 16 is formed in the gate pad 2a and the surrounding lower layer, it is sufficient that the ion implantation portion 16 is formed at least in the region under the gate pad 2a. Even if comprised in this way, the effect similar to the above is acquired.
  • the nitride semiconductor device 1B includes the ion implanter 15 that insulates the region under the drain pad 4a that is the base of the drain electrode portion 4b. With this configuration, the parasitic capacitance below the drain pad 4a can also be reduced.
  • nitride semiconductor device 1C includes an ion implantation portion 16 that insulates a region under the gate pad 2a that is a base portion of the gate electrode portion 2b. With this configuration, the parasitic capacitance below the gate pad 2a can also be reduced.
  • FIG. 7 is a plan view showing a pattern layout of a nitride semiconductor device 1D according to the fourth embodiment of the present invention, and shows a case where the nitride semiconductor device 1D is a HEMT formed of a nitride semiconductor. . Even in FIG. 7, an element isolation region, wiring, and the like actually exist, but are not described because they are not related to the characteristic portion of the nitride semiconductor device 1D. Moreover, the same code
  • an air bridge 17 is added to the configuration of the first embodiment.
  • the air bridge 17 embodies the connecting portion in the present invention, and connects the end portions of the gate electrode portions 2b and 2b extending in a bifurcated manner from the gate pad 2a.
  • the end portions of the gate electrode portions 2b and 2b are connected to each other by the air bridge 17, thereby making it possible to suppress parasitic oscillation during high frequency operation.
  • FIG. 8 is a plan view showing a pattern layout of nitride semiconductor device 1E according to the fourth embodiment of the present invention, and shows a case where nitride semiconductor device 1E is a HEMT formed of a nitride semiconductor. . Also in FIG. 8, there are actually element isolation regions, wirings, etc., but the description is omitted because they are not related to the characteristic portions of the nitride semiconductor device 1E. Moreover, the same code
  • an air bridge 18 is added to the configuration of the first embodiment.
  • the air bridge 18 embodies the connection portion in the present invention, and connects the end portions of the adjacent source electrode portions 3 and 3 to each other.
  • the HEMT of the nitride semiconductor device 1E is used for an amplifier, the other end portions extending from the end portion where the via 5 is formed in the source electrode portions 3 and 3 are connected to each other by the air bridge 18 to the via 5. The influence of the generated source inductance is reduced, and the maximum oscillation frequency of the HEMT can be increased.
  • FIG. 9 is a plan view showing a pattern layout of nitride semiconductor device 1F according to the fourth embodiment of the present invention, and shows a case where nitride semiconductor device 1F is a HEMT formed of a nitride semiconductor. .
  • nitride semiconductor device 1F is a HEMT formed of a nitride semiconductor.
  • FIG. 9 shows a case where nitride semiconductor device 1F is a HEMT formed of a nitride semiconductor.
  • FIG. 9 as well, there are actually element isolation regions, wirings, etc., but the description is omitted because they are not related to the characteristic portions of nitride semiconductor device 1F.
  • symbol is attached
  • the nitride semiconductor device 1F has an air bridge 19 added to the configuration of the first embodiment.
  • the air bridge 19 embodies the connection portion in the present invention, and connects the end portions of the drain electrode portions 4b and 4b extending in a bifurcated manner from the drain pad 4a.
  • the HEMT of the nitride semiconductor device 1F is used for an amplifier, by connecting the ends of the drain electrode portions 4b and 4b with the air bridge 19, it is possible to suppress parasitic oscillation during high frequency operation.
  • the structure which formed the air bridge 17, the air bridge 18, and the air bridge 19 separately was shown, the structure provided with two or more of these may be sufficient. For example, all of the air bridge 17, the air bridge 18, and the air bridge 19 may be provided. Further, any combination of the air bridge 17 and the air bridge 18, the air bridge 18 and the air bridge 19, the air bridge 17 and the air bridge 19 may be used. Even with this configuration, the same effect as described above can be obtained.
  • the connecting portion in the present invention is an air bridge
  • a wiring structure other than this may be used.
  • any structure that can electrically connect the ends of the electrode parts to be connected can be employed.
  • the nitride semiconductor device 1D according to the fourth embodiment includes the air bridge 17 that connects the ends of the gate electrode portions 2b and 2b that extend in a bifurcated manner from the gate pad 2a.
  • the nitride semiconductor device 1E according to the fourth embodiment includes an air bridge 18 that connects the end portions of the adjacent source electrode portions 3 and 3 to each other. With this configuration, the influence of the source inductance generated in the via 5 is reduced, and the maximum oscillation frequency of the HEMT of the nitride semiconductor device 1E can be increased.
  • the nitride semiconductor device 1F according to the fourth embodiment includes the air bridge 19 that connects the ends of the drain electrode portions 4b and 4b that extend in a bifurcated manner from the drain pad 4a.
  • FIG. 10 is a plan view showing a pattern layout of nitride semiconductor device 1G according to the fifth embodiment of the present invention, and shows a case where nitride semiconductor device 1G is a HEMT formed of a nitride semiconductor. Also in FIG. 10, there are actually element isolation regions, wirings, etc., but the description is omitted because they are not related to the characteristic portions of the nitride semiconductor device 1G. Moreover, the same code
  • the nitride semiconductor device 1G has a configuration in which a plurality of source electrode portions 3, gate electrode portions 2b, drain electrode portions 4b, and ion implantation portions 6 described in the first embodiment are arranged in an upper layer of the barrier layer 10. ing. As a result, a structure in which a plurality of transistors are integrated is provided, and the total output power in the HEMT having this structure can be increased. 10 shows a configuration in which two patterns of FIG. 1A are arranged, a configuration in which three or more patterns are arranged may be used. Thereby, the total output power in the HEMT having this structure can be further increased.
  • nitride semiconductor device 1G has a plurality of source electrode portions 3, gate electrode portions 2b, drain electrode portions 4b, and ion implantation portions 6 arranged side by side on the upper layer of barrier layer 10. Yes. Thereby, the total output power of the HEMT that is the nitride semiconductor device 1G can be increased.
  • FIG. 10 shows a configuration in which a plurality of the patterns shown in FIG. 1A are arranged on the upper layer of the barrier layer 10, but the present invention is not limited to this.
  • a plurality of the patterns shown in FIGS. 4 to 9 may be formed side by side on the upper layer of the barrier layer 10.
  • a plurality of patterns obtained by appropriately combining the configurations shown in FIGS. 4 to 9 may be formed on the upper layer of the barrier layer 10.
  • FIG. 11 is a plan view showing a pattern layout of nitride semiconductor device 1H according to the sixth embodiment of the present invention, and shows a case where nitride semiconductor device 1H is a HEMT formed of a nitride semiconductor.
  • nitride semiconductor device 1H is a HEMT formed of a nitride semiconductor.
  • FIG. 11 shows a case where nitride semiconductor device 1H is a HEMT formed of a nitride semiconductor.
  • FIG. 11 as well, there are actually element isolation regions, wirings, etc., but the description is omitted because they are not related to the characteristic portions of the nitride semiconductor device 1H.
  • symbol is attached
  • Nitride semiconductor device 1H has a configuration in which a plurality of source electrode portions 3, gate electrode portions 2b, drain electrode portions 4b, and ion implantation portions 6 are arranged in the upper layer of barrier layer 10 as in the fifth embodiment. ing. Furthermore, the nitride semiconductor device 1H includes a source electrode portion 3A. As shown in FIG. 11, the source electrode portion 3A has a planar shape in which electrode portions 3b and 3b extending bifurcated from one end 3a where the via 5 is formed are connected to each other at the other end 3c. Have. In addition, on both sides of the source electrode portion 3A, patterns each including the gate electrode portion 2b, the drain electrode portion 4b, and the ion implantation portion 6 are formed.
  • an ion implanted portion 20 is formed by ion implantation.
  • the ion implantation part 20 embodies the source side ion implantation part of the present invention, and as shown in FIG. 11, is formed in a region between the electrode parts 3b and 3b to make the region insulative.
  • ions to be implanted include ions such as Ar and Zn, but any ions may be used as long as the implanted region is in an insulating state.
  • the ion implantation part 20 has a cross-sectional structure having a depth reaching the substrate 7.
  • source electrode portion 3A has a planar shape in which electrode portions 3b and 3b extending from one end portion 3a and branching into two branches are connected to each other at the other end portion 3c.
  • the source electrode portion 3A is disposed between the adjacent gate electrodes 2 and 2. Thereby, it is not necessary to make the dimension of the width Ws of the electrode part 3b of the source electrode part 3A and the gate pitch Lgg between the adjacent gate electrode parts 2b and 2b the same dimension, and these dimensions can be made independently. Can be determined. Therefore, since the width Ws of the electrode part 3b can be narrowed and the gate pitch Lgg can be kept wide, it is possible to suppress an increase in the thermal resistance Rth and reduce the capacitance Csub below the electrode part 3b.
  • the region between the adjacent electrode portions 3b, 3b is insulated by the ion implantation portion 20. That is, since there is no two-dimensional electron gas in this region, the electrode portions 3 b and 3 b are not electrically connected by the two-dimensional electron gas in the channel layer 9.
  • source electrode portion 3A has electrode portions 3b and 3b extending in a bifurcated manner from one end portion 3a and connected to each other at the other end portion 3c. Has a planar shape. And the ion implantation part 20 which makes the area
  • Lgg the gate pitch
  • a configuration obtained by appropriately combining the feature portions shown in FIGS. 4 to 9 or the feature portions shown in FIGS. 4 to 9 may be added to the configuration shown in FIG.
  • at least one of a gate field plate 13, a source field plate 14, an ion implantation unit 15, an ion implantation unit 16, an air bridge 17, an air bridge 18, and an air bridge 19 is added to the configuration of FIG. 11. Also good. Even if it does in this way, the effect shown in Embodiment 2 to Embodiment 4 will be acquired.
  • any combination of each embodiment, any component of each embodiment can be modified, or any component can be omitted in each embodiment. .
  • the nitride semiconductor device according to the present invention can reduce the parasitic capacitance generated between the intrinsic carrier and the drain electrode portion at a high temperature and can suppress an increase in thermal resistance. It can be used as a HEMT.
  • 1,1A-1H 100 nitride semiconductor device, 2,101 gate electrode, 2a, 101a gate pad, 2b, 101b gate electrode part, 3,3A, 102 source electrode part, 3a, 3c end part, 3b electrode part, 4, 103 drain electrode, 4a, 103a drain pad, 4b, 103b drain electrode part, 5 via, 6, 15, 16, 20 ion implanted part, 7 substrate, 8 buffer layer, 9 channel layer, 10 barrier layer, 11, 12 insulating layers, 13 gate field plates, 14 source field plates, 17-19 air bridge.

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Abstract

A nitride semiconductor device comprises strip source electrodes (3) that are arranged on an upper layer of a barrier layer (10) and gate electrodes (2b,2b) that extend bifurcately from a gate pad (2a) and that are arranged between the source electrodes (3,3). The nitride semiconductor device further comprises drain electrodes (4b,4b) that extend bifurcately from a drain pad (4a) and that are arranged between the gate electrode (2b,2b), and and an ion injection part (6) that brings a region between the drain electrodes (4b,4b) to an insulating state.

Description

窒化物半導体装置Nitride semiconductor device
　この発明は、Ｓｉ基板などの導電性の基板上にＧａＮなどの窒化物半導体で形成された高電子移動トランジスタ（Ｈｉｇｈ　Ｅｌｅｃｔｒｏｎ　Ｍｏｂｉｌｉｔｙ　Ｔｒａｎｓｉｓｔｏｒ；以下、ＨＥＭＴと記載する）などの窒化物半導体装置に関する。 The present invention relates to a nitride semiconductor device such as a high electron mobility transistor (hereinafter referred to as HEMT) formed of a nitride semiconductor such as GaN on a conductive substrate such as a Si substrate.
　窒化ガリウム（ＧａＮ）は、ガリウムヒ素（ＧａＡｓ）、シリコン（Ｓｉ）などの半導体材料より耐圧、飽和速度の観点で優れた特性を有しており、ＨＥＭＴとしてマイクロ波高出力高周波増幅器などに使用されている。ここで、マイクロ波増幅器では高周波性能が重要となるため、マイクロ波増幅器に使用するＨＥＭＴは、できるだけ寄生容量が少ない半絶縁性のサファイアあるいは炭化シリコン（ＳｉＣ）などの基板上に作成されていた。
　ただし、これらの基板は一般的に高価で大口径化に向かないため、より安価なＳｉ基板を用いたＨＥＭＴを作成する技術が開発されている。 Gallium nitride (GaN) has superior characteristics in terms of breakdown voltage and saturation speed than semiconductor materials such as gallium arsenide (GaAs) and silicon (Si), and is used in microwave high-power high-frequency amplifiers as HEMTs. Yes. Here, since high frequency performance is important for the microwave amplifier, the HEMT used for the microwave amplifier is formed on a substrate such as semi-insulating sapphire or silicon carbide (SiC) having as little parasitic capacitance as possible.
However, since these substrates are generally expensive and are not suitable for increasing the diameter, a technique for creating a HEMT using a cheaper Si substrate has been developed.
　Ｓｉ基板の高抵抗化、エピタキシャル成長技術の向上などにより、Ｓｉ基板上にＧａＮで形成されたＨＥＭＴは、ＳｉＣなどの半絶縁性基板上にＧａＮで形成されたＨＥＭＴに対して室温動作でほぼ同等な性能が得られている。
　例えば、非特許文献１には、Ｓｉ基板上にＧａＮを含んで形成されたＨＥＭＴについて記載されている。非特許文献１に記載のＨＥＭＴは、バリア層の上層に並んで配置された短冊状のソース電極部と、ソース電極部の間に配置されて基部から二股に分岐して延びるゲート電極部を備える。さらに、このＨＥＭＴでは、ゲート電極部の間に１つの短冊状のドレイン電極部が配置されている。 HEMTs made of GaN on Si substrates due to higher resistance of Si substrates, improved epitaxial growth technology, etc. are almost equivalent to HEMTs made of GaN on semi-insulating substrates such as SiC at room temperature operation. Performance has been obtained.
For example, Non-Patent Document 1 describes a HEMT formed by containing GaN on a Si substrate. The HEMT described in Non-Patent Document 1 includes a strip-shaped source electrode portion arranged side by side on an upper layer of a barrier layer, and a gate electrode portion arranged between the source electrode portions and extending in a bifurcated manner from the base portion. . Further, in this HEMT, one strip-shaped drain electrode portion is disposed between the gate electrode portions.
　しかしながら、高温下では、Ｓｉ基板上にＧａＮを含んで形成したＨＥＭＴは、半絶縁性基板上にＧａＮを含んで形成されたＨＥＭＴに比べて出力電力が急激に低下するという課題があった。これは、温度上昇でＳｉ基板中の真性キャリアが増大しこれに伴って寄生容量が増大することにより、高周波リーク電力が増加したためであると考えられている。従って、このような高周波リーク電力を抑制するためには、上記寄生容量を低減する必要がある。なお、上記寄生容量は、高温下で、窒化アルミニウムガリウム（ＡｌＧａＮ）、窒化アルミニウム（ＡｌＮ）などのバッファ層とＳｉ基板との界面に生じる真性キャリアと、ドレイン電極部およびソース電極部との間に形成される。以下、この容量をＣｓｕｂと呼ぶ。 However, the HEMT formed with GaN on the Si substrate has a problem that the output power is drastically reduced at a high temperature as compared with the HEMT formed with GaN on the semi-insulating substrate. This is considered to be due to the increase in high-frequency leakage power due to the increase in intrinsic carriers in the Si substrate due to the temperature rise and the accompanying increase in parasitic capacitance. Therefore, in order to suppress such high frequency leakage power, it is necessary to reduce the parasitic capacitance. Note that the parasitic capacitance is generated between an intrinsic carrier generated at the interface between the buffer layer such as aluminum gallium nitride (AlGaN) and aluminum nitride (AlN) and the Si substrate and the drain electrode portion and the source electrode portion at a high temperature. It is formed. Hereinafter, this capacity is referred to as Csub.
　また、容量Ｃｓｕｂは、例えば真性キャリアとドレイン電極部との間における平行平板容量とみなせるので、容量Ｃｓｕｂを低減するためには、ＧａＮチャネル層あるいはＡｌＧａＮバッファ層を厚くするか、ドレイン電極部の幅を狭くすればよい。
　ただし、チャネル層、バッファ層を厚くする場合には、エピタキシャル成長工程の条件の変更が必要となり、コスト高になることが懸念される。このため、ＨＥＭＴの製品化を考慮すると、ドレイン電極部の幅を狭くすることを採用した方がよい。 Further, since the capacitance Csub can be regarded as a parallel plate capacitance between the intrinsic carrier and the drain electrode portion, for example, in order to reduce the capacitance Csub, the GaN channel layer or the AlGaN buffer layer is thickened or the width of the drain electrode portion is reduced. Should be narrowed.
However, when the channel layer and the buffer layer are thickened, it is necessary to change the conditions of the epitaxial growth process, which may increase the cost. For this reason, in consideration of commercialization of HEMT, it is better to adopt a narrow width of the drain electrode portion.
　一方、非特許文献１に記載されるＨＥＭＴは、ドレイン電極部の幅と隣り合ったゲート電極部間の距離であるゲートピッチとがほぼ同じ長さとなる構造を有している。
　このようにドレイン電極部の幅とゲートピッチをほぼ同じ長さにするのは、ゲート電極部とドレイン電極部との間の距離が、ドレイン電極部の幅またはゲートピッチと比較して一般的にかなり短く、ゲート電極部とドレイン電極部との間が無視できる距離であるためである。 On the other hand, the HEMT described in Non-Patent Document 1 has a structure in which the width of the drain electrode portion and the gate pitch, which is the distance between adjacent gate electrode portions, are approximately the same length.
In this way, the width of the drain electrode portion and the gate pitch are made substantially the same length because the distance between the gate electrode portion and the drain electrode portion is generally compared with the width of the drain electrode portion or the gate pitch. This is because the distance between the gate electrode portion and the drain electrode portion is negligible.
　このような構造を有したＨＥＭＴにおいて、ドレイン電極部の幅を狭くすると、これに伴ってゲートピッチも狭くなる。このため、熱抵抗が増大して熱による大きな性能劣化を招いてしまう。特に、Ｓｉの熱伝導率は１６８（Ｗ／ｍＫ）であり、熱伝導率が３５０（Ｗ／ｍＫ）のＳｉＣに比べて低いため、熱抵抗の増大は著しい性能劣化に繋がる。 In the HEMT having such a structure, when the width of the drain electrode portion is narrowed, the gate pitch is also narrowed accordingly. For this reason, a thermal resistance increases and a big performance degradation by heat will be caused. In particular, since the thermal conductivity of Si is 168 (W / mK), which is lower than that of SiC having a thermal conductivity of 350 (W / mK), an increase in thermal resistance leads to significant performance degradation.
　この発明は上記課題を解決するもので、真性キャリアとドレイン電極部との間に発生する寄生容量を低減しかつ熱抵抗の増大を抑制することができる窒化物半導体装置を得ることを目的とする。 SUMMARY OF THE INVENTION An object of the present invention is to provide a nitride semiconductor device that can reduce parasitic capacitance generated between an intrinsic carrier and a drain electrode portion and suppress an increase in thermal resistance. .
　この発明に係る窒化物半導体装置は、チャネル層、バリア層、ソース電極部、ゲート電極部、ドレイン電極部およびイオン注入部を備える。
　チャネル層は電子が走行する層である。バリア層は、チャネル層の上層にインジウム、アルミニウムおよびガリウムのうちの少なくとも１つと窒素を含んで形成されてチャネル層に２次元電子ガスを形成する。短冊状のソース電極部は、バリア層の上層に並んで配置される。ゲート電極部は、隣り合ったソース電極部の間に配置されて基部から二股に分岐して延びる。ドレイン電極部は、隣り合ったゲート電極部の間に配置されて基部から二股に分岐して延びる。イオン注入部は、隣り合ったドレイン電極部の間の領域を絶縁状態にする。 The nitride semiconductor device according to the present invention includes a channel layer, a barrier layer, a source electrode part, a gate electrode part, a drain electrode part, and an ion implantation part.
The channel layer is a layer where electrons travel. The barrier layer is formed to contain at least one of indium, aluminum, and gallium and nitrogen in the upper layer of the channel layer to form a two-dimensional electron gas in the channel layer. The strip-shaped source electrode portion is arranged side by side on the upper layer of the barrier layer. The gate electrode portion is disposed between adjacent source electrode portions and extends in a bifurcated manner from the base portion. The drain electrode portion is disposed between the adjacent gate electrode portions and extends bifurcated from the base portion. The ion implantation part insulates a region between adjacent drain electrode parts.
　この発明によれば、バリア層上のソース電極部の間に配置されて基部から二股に分岐して延びるゲート電極部と、ゲート電極部の間に配置されて基部から二股に分岐して延びるドレイン電極部と、ドレイン電極部の間の領域を絶縁状態とするイオン注入部を備える。
　このように構成することで、ドレイン電極部の幅の寸法と、隣り合ったゲート電極部間のゲートピッチの寸法を独立して決定することができ、ドレイン電極部の幅を狭く、かつゲートピッチを広くすることが可能である。
　ドレイン電極部の幅が狭くなることで、高温下で真性キャリアとドレイン電極部との間に発生する寄生容量Ｃｓｕｂが低減される。またゲートピッチが広くなることで、熱抵抗の増大も抑制することができる。 According to the present invention, the gate electrode portion disposed between the source electrode portions on the barrier layer and extending in a bifurcated manner from the base portion, and the drain disposed between the gate electrode portions and extending in a bifurcated manner from the base portion. An ion implantation part is provided for bringing the region between the electrode part and the drain electrode part into an insulating state.
With this configuration, the width dimension of the drain electrode portion and the dimension of the gate pitch between adjacent gate electrode portions can be determined independently, the width of the drain electrode portion is narrowed, and the gate pitch Can be widened.
By reducing the width of the drain electrode portion, the parasitic capacitance Csub generated between the intrinsic carrier and the drain electrode portion at a high temperature is reduced. In addition, an increase in thermal resistance can be suppressed by increasing the gate pitch.
図１Ａは、この発明の実施の形態１に係る窒化物半導体装置のパターンレイアウトを示す平面図であり、図１Ｂは、従来の窒化物半導体装置のパターンレイアウトを示す平面図である。1A is a plan view showing a pattern layout of a nitride semiconductor device according to Embodiment 1 of the present invention, and FIG. 1B is a plan view showing a pattern layout of a conventional nitride semiconductor device. 図１ＡのＡ－Ａ線で切った実施の形態１に係る窒化物半導体装置の構成を示す断面図である。FIG. 1B is a cross-sectional view showing the configuration of the nitride semiconductor device according to the first embodiment taken along line AA in FIG. 1A. 図３Ａは、実施の形態１に係る窒化物半導体装置と従来の窒化物半導体装置とにおける、容量Ｃｓｕｂとドレイン電極部の幅との関係を示すグラフである。図３Ｂは、実施の形態１に係る窒化物半導体装置と従来の窒化物半導体装置とにおける、熱抵抗Ｒｔｈとドレイン電極部の幅との関係を示すグラフである。FIG. 3A is a graph showing the relationship between the capacitance Csub and the width of the drain electrode portion in the nitride semiconductor device according to the first embodiment and the conventional nitride semiconductor device. FIG. 3B is a graph showing the relationship between the thermal resistance Rth and the width of the drain electrode portion in the nitride semiconductor device according to the first embodiment and the conventional nitride semiconductor device. この発明の実施の形態２に係る窒化物半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the nitride semiconductor device which concerns on Embodiment 2 of this invention. この発明の実施の形態３に係る窒化物半導体装置のパターンレイアウトを示す平面図である。It is a top view which shows the pattern layout of the nitride semiconductor device which concerns on Embodiment 3 of this invention. この発明の実施の形態３に係る窒化物半導体装置の別のパターンレイアウトを示す平面図である。It is a top view which shows another pattern layout of the nitride semiconductor device which concerns on Embodiment 3 of this invention. この発明の実施の形態４に係る窒化物半導体装置のパターンレイアウトを示す平面図である。It is a top view which shows the pattern layout of the nitride semiconductor device which concerns on Embodiment 4 of this invention. この発明の実施の形態４に係る窒化物半導体装置の別のパターンレイアウトを示す平面図である。It is a top view which shows another pattern layout of the nitride semiconductor device which concerns on Embodiment 4 of this invention. この発明の実施の形態４に係る窒化物半導体装置のさらに別のパターンレイアウトを示す平面図である。It is a top view which shows another pattern layout of the nitride semiconductor device which concerns on Embodiment 4 of this invention. この発明の実施の形態５に係る窒化物半導体装置のパターンレイアウトを示す平面図である。It is a top view which shows the pattern layout of the nitride semiconductor device which concerns on Embodiment 5 of this invention. この発明の実施の形態６に係る窒化物半導体装置のパターンレイアウトを示す平面図である。It is a top view which shows the pattern layout of the nitride semiconductor device which concerns on Embodiment 6 of this invention.
　以下、この発明をより詳細に説明するため、この発明を実施するための形態について、添付の図面に従って説明する。
実施の形態１．
　図１Ａは、この発明の実施の形態１に係る窒化物半導体装置１のパターンレイアウトを示す平面図であり、窒化物半導体装置１が窒化物半導体で形成されたＨＥＭＴである場合を示している。また、図１Ｂは、従来の窒化物半導体装置１００のパターンレイアウトを示す平面図であり、窒化物半導体装置１００が窒化物半導体で形成されたＨＥＭＴである場合を示している。図２は、図１ＡのＡ－Ａ線で切った窒化物半導体装置１を示す断面図である。 Hereinafter, in order to describe the present invention in more detail, modes for carrying out the present invention will be described with reference to the accompanying drawings.
Embodiment 1 FIG.
FIG. 1A is a plan view showing a pattern layout of nitride semiconductor device 1 according to the first embodiment of the present invention, and shows a case where nitride semiconductor device 1 is a HEMT formed of a nitride semiconductor. FIG. 1B is a plan view showing the pattern layout of the conventional nitride semiconductor device 100, and shows a case where the nitride semiconductor device 100 is a HEMT formed of a nitride semiconductor. FIG. 2 is a cross-sectional view showing nitride semiconductor device 1 taken along line AA in FIG. 1A.
　なお、図１Ａ、図１Ｂおよび図２において、実際には、素子分離領域、配線などが存在するが、窒化物半導体装置１の特徴部分とは関連がないため、記載を省略している。
　また、窒化物半導体装置１のＨＥＭＴは、マイクロ波増幅器に限らず、ＭＨｚ程度の駆動周波数で動作するパワーデバイスにも適用可能である。 In FIG. 1A, FIG. 1B, and FIG. 2, there are actually element isolation regions, wirings, and the like, but they are not described because they are not related to the characteristic portions of nitride semiconductor device 1.
Further, the HEMT of the nitride semiconductor device 1 is applicable not only to the microwave amplifier but also to a power device that operates at a driving frequency of about MHz.
　従来の窒化物半導体装置１００において、ゲート電極１０１は、ゲートパッド１０１ａとこのゲートパッド１０１ａから二股に分岐して延びるゲート電極部１０１ｂ，１０１ｂとを備える。短冊状のソース電極部１０２，１０２は複数並んで形成されており、ゲート電極部１０１ｂ，１０１ｂは隣り合ったソース電極部１０２，１０２の間に配置される。ドレイン電極１０３は、ドレインパッド１０３ａとこのドレインパッド１０３ａから延びた１つの短冊状のドレイン電極部１０３ｂとを備える。ドレイン電極部１０３ｂは、図１Ｂに示すように、隣り合ったゲート電極部１０１ｂ，１０１ｂの間に配置されている。 In the conventional nitride semiconductor device 100, the gate electrode 101 includes a gate pad 101a and gate electrode portions 101b and 101b extending in a bifurcated manner from the gate pad 101a. A plurality of strip-like source electrode portions 102 and 102 are formed side by side, and the gate electrode portions 101b and 101b are disposed between adjacent source electrode portions 102 and 102. The drain electrode 103 includes a drain pad 103a and one strip-shaped drain electrode portion 103b extending from the drain pad 103a. As shown in FIG. 1B, the drain electrode portion 103b is disposed between the adjacent gate electrode portions 101b and 101b.
　一方、実施の形態１に係る窒化物半導体装置１において、ゲート電極２は、基部であるゲートパッド２ａとこのゲートパッド２ａから二股に分岐して延びるゲート電極部２ｂ，２ｂとを備える。短冊状のソース電極部３，３は複数並んで形成されており、ゲート電極部２ｂ，２ｂは、隣り合ったソース電極部３，３の間に配置される。ドレイン電極４は、基部であるドレインパッド４ａとこのドレインパッド４ａから二股に分岐して延びるドレイン電極部４ｂ，４ｂとを備える。ドレイン電極部４ｂ，４ｂは、図１Ａに示すように、隣り合ったゲート電極部２ｂ，２ｂの間に配置されている。 On the other hand, in the nitride semiconductor device 1 according to the first embodiment, the gate electrode 2 includes a gate pad 2a as a base and gate electrode portions 2b and 2b extending in a bifurcated manner from the gate pad 2a. A plurality of strip-like source electrode portions 3, 3 are formed side by side, and the gate electrode portions 2 b, 2 b are arranged between the adjacent source electrode portions 3, 3. The drain electrode 4 includes a drain pad 4a, which is a base, and drain electrode portions 4b and 4b extending bifurcated from the drain pad 4a. As shown in FIG. 1A, the drain electrode portions 4b and 4b are disposed between the adjacent gate electrode portions 2b and 2b.
　隣り合ったドレイン電極部４ｂ，４ｂ間の領域には、アルゴン（Ａｒ）、亜鉛（Ｚｎ）などのイオンを注入することによってイオン注入部６が形成されている。イオン注入部６は、上記領域を絶縁状態にするものである。なお、注入するイオンは、Ａｒ、Ｚｎに限定されるものではなく、注入領域が絶縁状態になるイオンであればよい。 In the region between the adjacent drain electrode portions 4b and 4b, an ion implanted portion 6 is formed by implanting ions such as argon (Ar) and zinc (Zn). The ion implantation part 6 makes the said area | region insulated. Note that the ions to be implanted are not limited to Ar and Zn, and any ions may be used as long as the implanted region is in an insulating state.
　図２に示すように、窒化物半導体装置１は、基板７上に形成される。基板７としては、Ｓｉのように導電性になり得る半導体材料で形成された基板が使用される。
　バッファ層８は、チャネル層９の結晶性を向上させることおよびチャネル層９に電子を閉じ込めることを目的として基板７とチャネル層９との間に挿入される層である。
　またバッファ層８は、ＡｌＮ、ＡｌＧａＮ、ＧａＮ／ＩｎＧａＮ、ＡｌＮ／ＡｌＧａＮおよびこれらの超格子などの様々な構造で形成することができる。 As shown in FIG. 2, the nitride semiconductor device 1 is formed on a substrate 7. As the substrate 7, a substrate formed of a semiconductor material that can be conductive, such as Si, is used.
The buffer layer 8 is a layer inserted between the substrate 7 and the channel layer 9 for the purpose of improving the crystallinity of the channel layer 9 and confining electrons in the channel layer 9.
The buffer layer 8 can be formed with various structures such as AlN, AlGaN, GaN / InGaN, AlN / AlGaN, and their superlattices.
　チャネル層９は、トランジスタ動作に必要な電子が走行する層であり、バッファ層８の上層に形成される。典型的なチャネル層９はＧａＮから形成されるが、ＩｎＧａＮ、ＡｌＧａＮあるいはこれらの多層構造で形成することも可能である。
　また、チャネル層９に不純物を注入することで、ＨＥＭＴのゲート制御性を向上させることができる。不純物には、半導体を半絶縁性にする遷移金属である鉄（Ｆｅ）、炭素（Ｃ）が用いられる。なお、不純物の注入プロファイルがいかなるものでもよい。 The channel layer 9 is a layer through which electrons necessary for transistor operation travel, and is formed in the upper layer of the buffer layer 8. A typical channel layer 9 is made of GaN, but can be formed of InGaN, AlGaN, or a multilayer structure thereof.
Further, by implanting impurities into the channel layer 9, the gate controllability of the HEMT can be improved. As the impurities, iron (Fe) and carbon (C), which are transition metals that make the semiconductor semi-insulating, are used. Any impurity implantation profile may be used.
　バリア層１０は、チャネル層９の上層にＩｎ、ＡｌおよびＧａのうちの少なくとも１つと窒素（Ｎ）を含んで形成されてチャネル層９に２次元電子ガスを形成する層である。
　バリア層１０としてＡｌＧａＮ単層がよく用いられるが、これ以外の組成、層厚、不純物濃度が異なる、複数のＡｌＧａＮの組み合わせ、ＡｌＧａＮとＧａＮとの組み合わせ、ＡｌＧａＮとＡｌＮとの組み合わせであってもよい。
　チャネル層９とバリア層１０とが接触する界面は、チャネル層９よりもバンドギャップが広いヘテロ接合で形成する。 The barrier layer 10 is a layer that is formed on the channel layer 9 so as to contain at least one of In, Al, and Ga and nitrogen (N) to form a two-dimensional electron gas in the channel layer 9.
An AlGaN single layer is often used as the barrier layer 10, but other than this, a combination of a plurality of AlGaN, a combination of AlGaN and GaN, and a combination of AlGaN and AlN may be used. .
The interface where the channel layer 9 and the barrier layer 10 are in contact is formed by a heterojunction having a wider band gap than the channel layer 9.
　図１Ａに示したゲート電極２、ソース電極部３、ドレイン電極４およびイオン注入部６はバリア層１０の上層に形成される。なお、イオン注入部６は、図２に示すように基板７に至る深さの断面構造を有している。 1A, the gate electrode 2, the source electrode portion 3, the drain electrode 4, and the ion implantation portion 6 are formed in the upper layer of the barrier layer 10. In addition, the ion implantation part 6 has a cross-sectional structure with a depth reaching the substrate 7 as shown in FIG.
　絶縁層１１は、バリア層１０の上層における、ゲート電極部２ｂとソース電極部３との間およびゲート電極部２ｂとドレイン電極部４ｂとの間に形成され、バリア層１０の表面のトラップを抑制する層である。絶縁層１１には、ＳｉＮ、ＳｉＯなどといったドナーとして機能し得るＳｉを含んだ絶縁膜がよく用いられる。すなわち、絶縁層１１に含まれるＳｉがドナーとしてバリア層１０に電子を供給することにより、バリア層１０の表面上のトラップ数を減らすことができる。 The insulating layer 11 is formed between the gate electrode part 2b and the source electrode part 3 and between the gate electrode part 2b and the drain electrode part 4b in the upper layer of the barrier layer 10, and suppresses trapping of the surface of the barrier layer 10 It is a layer to do. For the insulating layer 11, an insulating film containing Si that can function as a donor, such as SiN or SiO, is often used. That is, Si contained in the insulating layer 11 supplies electrons to the barrier layer 10 as a donor, whereby the number of traps on the surface of the barrier layer 10 can be reduced.
　絶縁層１２は、ソース電極部３とドレイン電極部４ｂとの間でゲート電極部２ｂを覆うように形成されている。絶縁層１２には、カバレッジの材料として、ＳｉＮ、ＳｉＯ２、Ａｌ２Ｏ３などが用いられる。ただし、この発明は、これらの材料に限定されるものではない。 The insulating layer 12 is formed so as to cover the gate electrode portion 2b between the source electrode portion 3 and the drain electrode portion 4b. For the insulating layer 12, SiN, SiO 2 , Al 2 O 3 or the like is used as a coverage material. However, the present invention is not limited to these materials.
　ソース電極部３とドレイン電極４は、チャネル層９を走行する電子（電流）をＨＥＭＴの外部に取り出すための電極である。このため、ソース電極部３とドレイン電極４は、２次元電子ガスとの間の抵抗ができるだけ少なくなるように形成されている。
　図２の例では、ソース電極部３とドレイン電極４がバリア層１０の上表面に接するように形成されているが、バリア層１０中の２次元電子ガスに接するように形成してもよい。また、ソース電極部３とドレイン電極４の下層にｎ＋領域を形成してもよい。 The source electrode portion 3 and the drain electrode 4 are electrodes for taking out electrons (current) traveling through the channel layer 9 to the outside of the HEMT. For this reason, the source electrode portion 3 and the drain electrode 4 are formed so that the resistance between the two-dimensional electron gas is as small as possible.
In the example of FIG. 2, the source electrode portion 3 and the drain electrode 4 are formed so as to be in contact with the upper surface of the barrier layer 10, but may be formed so as to be in contact with the two-dimensional electron gas in the barrier layer 10. Further, an n + region may be formed under the source electrode portion 3 and the drain electrode 4.
　ソース電極部３，３には、図１Ａに示すように、基板７の裏面に繋がるビア５が形成されており、ビア５によって基板７の裏面の接地面に電気的に接続されている。
　ゲート電極２は、バリア層１０とショットキー接触する金属を含んで形成されており、ゲート電極２の下層における２次元電子ガス濃度を制御することで、トランジスタ動作が実現される。 As shown in FIG. 1A, vias 5 connected to the back surface of the substrate 7 are formed in the source electrode portions 3 and 3, and the vias 5 are electrically connected to the ground plane on the back surface of the substrate 7.
The gate electrode 2 is formed to include a metal in Schottky contact with the barrier layer 10, and transistor operation is realized by controlling the two-dimensional electron gas concentration in the lower layer of the gate electrode 2.
　なお、図１Ｂに示した窒化物半導体装置１００は、イオン注入部６を除いて、前述した図２と同様の断面構造を有している。すなわち、窒化物半導体装置１００のＨＥＭＴにおいても基板上にバッファ層、チャネル層およびバリア層があり、バリア層の上層に図１Ｂに示したパターンが形成される。 Note that the nitride semiconductor device 100 shown in FIG. 1B has the same cross-sectional structure as FIG. 2 described above except for the ion implantation portion 6. That is, the HEMT of the nitride semiconductor device 100 also has a buffer layer, a channel layer, and a barrier layer on the substrate, and the pattern shown in FIG. 1B is formed on the barrier layer.
　Ｓｉ基板上にＧａＮを含んで形成されたＨＥＭＴは、前述したように基板７とバッファ層８との界面に真性キャリアの高濃度のホールが存在する。このような高濃度のホールによって、容量Ｃｓｕｂを介したドレイン電極４からソース電極部３への高周波リークパスが形成される。 The HEMT formed on the Si substrate containing GaN has high concentration holes of intrinsic carriers at the interface between the substrate 7 and the buffer layer 8 as described above. Such a high-concentration hole forms a high-frequency leak path from the drain electrode 4 to the source electrode portion 3 via the capacitor Csub.
　このような高周波リークパスを介してリークされる電力を低減するためには、ドレイン電極部１０３ｂの幅Ｗｄを狭くすることが考えられる。
　しかしながら、従来の窒化物半導体装置１００では、ドレイン電極部１０３ｂの幅ＷｄとゲートピッチＬｇｇがほぼ同じになるように形成されるので、ドレイン電極部１０３ｂの幅Ｗｄを狭くすると、これに伴ってゲートピッチＬｇｇも狭くなってしまう。
　このため、ドレイン電極部１０３ｂの幅Ｗｄを狭くして容量Ｃｓｕｂを低減することはできるが、その分だけゲートピッチＬｇｇも狭くなって熱抵抗Ｒｔｈが増大する。 In order to reduce the power leaked through such a high-frequency leak path, it is conceivable to reduce the width Wd of the drain electrode portion 103b.
However, since the conventional nitride semiconductor device 100 is formed so that the width Wd of the drain electrode portion 103b and the gate pitch Lgg are substantially the same, if the width Wd of the drain electrode portion 103b is narrowed, the gate is accompanied accordingly. The pitch Lgg is also narrowed.
For this reason, it is possible to reduce the capacitance Csub by narrowing the width Wd of the drain electrode portion 103b. However, the gate pitch Lgg is also reduced correspondingly, and the thermal resistance Rth is increased.
　これに対して、窒化物半導体装置１では、ドレイン電極４が、ドレインパッド４ａから二股に分岐して延びるドレイン電極部４ｂ，４ｂを備えており、これらのドレイン電極部４ｂ，４ｂは、ゲート電極部２ｂ，２ｂの間に配置されている。
　これにより、ドレイン電極部４ｂの幅Ｗｄと、隣り合ったゲート電極部２ｂ，２ｂの間のゲートピッチＬｇｇとを同じ寸法にする必要がなく、これらの寸法を独立して決定することができる。従って、ドレイン電極部４ｂの幅Ｗｄを狭く、かつゲートピッチＬｇｇを広く保つことができるため、熱抵抗Ｒｔｈの増大を抑制し、かつ容量Ｃｓｕｂを低減することが可能となる。 On the other hand, in the nitride semiconductor device 1, the drain electrode 4 includes drain electrode portions 4b and 4b extending bifurcated from the drain pad 4a, and these drain electrode portions 4b and 4b are gate electrodes. It arrange | positions between the parts 2b and 2b.
Thus, the width Wd of the drain electrode portion 4b and the gate pitch Lgg between the adjacent gate electrode portions 2b and 2b do not need to be the same size, and these dimensions can be determined independently. Therefore, since the width Wd of the drain electrode portion 4b can be narrowed and the gate pitch Lgg can be kept wide, it is possible to suppress an increase in the thermal resistance Rth and reduce the capacitance Csub.
　また、隣り合ったドレイン電極部４ｂ，４ｂ間の領域は、イオン注入部６によって絶縁状態となっている。すなわち、この領域には２次元電子ガスが存在しないため、チャネル層９中の２次元電子ガスによってドレイン電極部４ｂ，４ｂが電気的に接続されることがない。 In addition, the region between the adjacent drain electrode portions 4 b and 4 b is insulated by the ion implantation portion 6. That is, since the two-dimensional electron gas does not exist in this region, the drain electrode portions 4 b and 4 b are not electrically connected by the two-dimensional electron gas in the channel layer 9.
　図３Ａは、実施の形態１に係る窒化物半導体装置１と従来の窒化物半導体装置１００とにおける、容量Ｃｓｕｂとドレイン電極部の幅との関係を示すグラフである。
　図３Ａに示すドレイン電極部の幅Ｗｄに対する容量Ｃｓｕｂの関係は、Ｓパラメータの幅Ｗｄに対する依存性を、実施の形態１に係る構造と従来の構造についてデバイスシミュレーションした結果に基づいて算出したものである。
　なお、実施の形態１に係る構造はゲートピッチＬｇｇを３０（μｍ）に固定しており、従来の構造ではドレイン電極部１０３ｂの幅ＷｄとゲートピッチＬｇｇを同じ寸法にしている。バイアス条件は、ゲート電圧Ｖｇを－５（Ｖ）、ドレイン電圧Ｖｄを５０（ｖ）としている。 FIG. 3A is a graph showing the relationship between the capacitance Csub and the width of the drain electrode portion in the nitride semiconductor device 1 according to the first embodiment and the conventional nitride semiconductor device 100.
The relationship of the capacitance Csub with respect to the width Wd of the drain electrode portion shown in FIG. 3A is obtained by calculating the dependence of the S parameter on the width Wd based on the results of device simulation of the structure according to the first embodiment and the conventional structure. is there.
In the structure according to the first embodiment, the gate pitch Lgg is fixed to 30 (μm), and in the conventional structure, the width Wd of the drain electrode portion 103b and the gate pitch Lgg are the same. The bias conditions are a gate voltage Vg of −5 (V) and a drain voltage Vd of 50 (v).
　図３Ａにおいて、実施の形態１に係る構造の結果は菱形形状（◆）のプロットであり、従来の構造の結果は四角形状（□）のプロットである。
　容量Ｃｓｕｂに関しては、実施の形態１に係る構造と従来の構造とにおいて同じ幅Ｗｄでは同じ容量Ｃｓｕｂとなっており、図３Ａ中に矢印で示すように、幅Ｗｄが狭くなるに連れて容量Ｃｓｕｂが低減している。 In FIG. 3A, the result of the structure according to Embodiment 1 is a rhombus-shaped (♦) plot, and the result of the conventional structure is a quadrangular (□) plot.
Regarding the capacitance Csub, the structure C according to the first embodiment and the conventional structure have the same capacitance Csub at the same width Wd, and as indicated by an arrow in FIG. 3A, the capacitance Csub is reduced as the width Wd becomes narrower. Has been reduced.
　図３Ｂは、実施の形態１に係る窒化物半導体装置１と従来の窒化物半導体装置１００とにおける、熱抵抗Ｒｔｈとドレイン電極部の幅との関係を示すグラフである。
　図３Ｂに示す熱抵抗Ｒｔｈの幅Ｗｄに対する依存性は、実施の形態１に係る構造と従来の構造について４５度法で算出したものである。
　なお、実施の形態１に係る構造と従来の構造において、Ｓｉ基板の厚さを６０μｍとしている。また、実施の形態１に係る構造はゲートピッチＬｇｇを３０（μｍ）に固定しており、従来の構造ではドレイン電極部１０３ｂの幅ＷｄとゲートピッチＬｇｇを同じ寸法にしている。 FIG. 3B is a graph showing the relationship between the thermal resistance Rth and the width of the drain electrode portion in the nitride semiconductor device 1 according to the first embodiment and the conventional nitride semiconductor device 100.
The dependence of the thermal resistance Rth on the width Wd shown in FIG. 3B is calculated by the 45 degree method for the structure according to Embodiment 1 and the conventional structure.
In the structure according to the first embodiment and the conventional structure, the thickness of the Si substrate is 60 μm. In the structure according to the first embodiment, the gate pitch Lgg is fixed to 30 (μm). In the conventional structure, the width Wd of the drain electrode portion 103b and the gate pitch Lgg are the same.
　図３Ａと同様に、実施の形態１に係る構造の結果は菱形形状（◆）のプロットであり、従来の構造の結果は四角形状（□）のプロットである。
　図３Ｂに示すように、従来の構造では、ドレイン電極部１０３ｂの幅Ｗｄを狭くするに連れて熱抵抗Ｒｔｈが増大することがわかる。
　これに対し、実施の形態１に係る構造では、ドレイン電極部４ｂの幅Ｗｄを狭くしてもゲートピッチＬｇｇが３０（μｍ）に固定されるので、鎖線の矢印で示すように、熱抵抗Ｒｔｈの増大が抑制される。 Similar to FIG. 3A, the result of the structure according to the first embodiment is a rhombus (♦) plot, and the result of the conventional structure is a square (□) plot.
As shown in FIG. 3B, it can be seen that in the conventional structure, the thermal resistance Rth increases as the width Wd of the drain electrode portion 103b is reduced.
On the other hand, in the structure according to the first embodiment, the gate pitch Lgg is fixed to 30 (μm) even when the width Wd of the drain electrode portion 4b is narrowed. Increase is suppressed.
　以上のように、実施の形態１に係る窒化物半導体装置１は、バリア層１０上のソース電極部３，３の間に配置されてゲートパッド２ａから二股に分岐して延びるゲート電極部２ｂ，２ｂを備える。さらに、ゲート電極部２ｂ，２ｂの間に配置されてドレインパッド４ａから二股に分岐して延びるドレイン電極部４ｂ，４ｂと、ドレイン電極部４ｂ，４ｂの間の領域を絶縁状態とするイオン注入部６を備える。
　このように構成することで、ドレイン電極部４ｂの幅Ｗｄの寸法と、隣り合ったゲート電極部２ｂ，２ｂ間のゲートピッチＬｇｇの寸法を独立して決定することができ、ドレイン電極部４ｂの幅Ｗｄを狭く、かつゲートピッチＬｇｇを広くすることが可能である。
　ドレイン電極部４ｂの幅Ｗｄが狭くなることで、高温下で真性キャリアとドレイン電極部４ｂとの間に発生する容量Ｃｓｕｂが低減される。またゲートピッチＬｇｇが広くなることで、熱抵抗Ｒｔｈの増大も抑制することができる。 As described above, the nitride semiconductor device 1 according to the first embodiment is arranged between the source electrode portions 3 and 3 on the barrier layer 10 and extends in a bifurcated manner from the gate pad 2a. 2b. Further, the drain electrode portions 4b and 4b that are arranged between the gate electrode portions 2b and 2b and extend bifurcated from the drain pad 4a, and the ion implantation portion that insulates the region between the drain electrode portions 4b and 4b. 6 is provided.
By configuring in this way, the dimension of the width Wd of the drain electrode part 4b and the dimension of the gate pitch Lgg between the adjacent gate electrode parts 2b, 2b can be determined independently, and the drain electrode part 4b It is possible to narrow the width Wd and widen the gate pitch Lgg.
By reducing the width Wd of the drain electrode portion 4b, the capacitance Csub generated between the intrinsic carrier and the drain electrode portion 4b at a high temperature is reduced. In addition, the increase in the thermal resistance Rth can be suppressed by increasing the gate pitch Lgg.
実施の形態２．
　図４は、この発明の実施の形態２に係る窒化物半導体装置１Ａの構成を示す断面図であり、図１ＡのＡ－Ａ線と同様の位置で切断した様子を示している。また、図４では、窒化物半導体装置１Ａが、窒化物半導体で形成されたＨＥＭＴである場合を示している。
　なお、図４において、実際には素子分離領域、配線などが存在するが、窒化物半導体装置１Ａの特徴部分とは関連がないため、記載を省略している。
　また、図１Ａおよび図２と同一の構成要素には同一の符号を付して説明を省略する。 Embodiment 2. FIG.
FIG. 4 is a cross-sectional view showing a configuration of a nitride semiconductor device 1A according to the second embodiment of the present invention, and shows a state cut along the line AA in FIG. 1A. FIG. 4 shows the case where the nitride semiconductor device 1A is a HEMT formed of a nitride semiconductor.
In FIG. 4, an element isolation region, wiring, and the like actually exist, but are not described because they are not related to the characteristic portion of the nitride semiconductor device 1A.
Also, the same components as those in FIGS. 1A and 2 are denoted by the same reference numerals and description thereof is omitted.
　窒化物半導体装置１Ａは、実施の形態１の構成に対してゲートフィールドプレート１３およびソースフィールドプレート１４を追加している。
　ゲートフィールドプレート１３は、ゲート電極部２ｂの上層にこのゲート電極部２ｂに沿って形成されて、ゲート電極部２ｂにおけるドレイン電極部４ｂ側の端部における電界集中を緩和する機能を有している。 In nitride semiconductor device 1A, gate field plate 13 and source field plate 14 are added to the configuration of the first embodiment.
The gate field plate 13 is formed along the gate electrode portion 2b in the upper layer of the gate electrode portion 2b, and has a function of relaxing the electric field concentration at the end of the gate electrode portion 2b on the drain electrode portion 4b side. .
　また、ソースフィールドプレート１４は、図４に示すように、ソース電極部３のドレイン電極部４ｂ側の端部から張り出すように形成されて、ゲートフィールドプレート１３と同様にゲート電極部２ｂにおけるドレイン電極部４ｂ側の端部での電界集中を緩和する。
　なお、ゲートフィールドプレート１３とソースフィールドプレート１４の両方を備える場合よりも電界集中を緩和する能力は落ちるが、これらのいずれかを備える構成であってもよい。 Further, as shown in FIG. 4, the source field plate 14 is formed so as to protrude from the end of the source electrode portion 3 on the drain electrode portion 4b side, and similarly to the gate field plate 13, the drain in the gate electrode portion 2b is formed. Electric field concentration at the end on the electrode part 4b side is reduced.
Although the ability to alleviate electric field concentration is lower than when both the gate field plate 13 and the source field plate 14 are provided, a configuration including any one of these may be used.
　以上のように、実施の形態２に係る窒化物半導体装置１Ａは、ゲートフィールドプレート１３およびソースフィールドプレート１４のうちの少なくとも一方を備える。
　この構成を有することで、ゲート電極部２ｂにおけるドレイン電極部４ｂ側の端部での電界集中が緩和される。これにより、窒化物半導体装置１ＡのＨＥＭＴの耐圧性能の低下を抑制することができる。 As described above, nitride semiconductor device 1 </ b> A according to the second embodiment includes at least one of gate field plate 13 and source field plate 14.
With this configuration, the electric field concentration at the end of the gate electrode portion 2b on the drain electrode portion 4b side is alleviated. Thereby, the fall of the pressure resistance performance of HEMT of nitride semiconductor device 1A can be controlled.
実施の形態３．
　図５は、この発明の実施の形態３に係る窒化物半導体装置１Ｂのパターンレイアウトを示す平面図であって、窒化物半導体装置１Ｂが窒化物半導体で形成されたＨＥＭＴである場合を示している。なお、図５において、実際には、素子分離領域、配線などが存在するが、窒化物半導体装置１Ｂの特徴部分とは関連がないため、記載を省略している。また、図１Ａと同一の構成要素には同一の符号を付して説明を省略する。 Embodiment 3 FIG.
FIG. 5 is a plan view showing a pattern layout of nitride semiconductor device 1B according to the third embodiment of the present invention, and shows a case where nitride semiconductor device 1B is a HEMT formed of a nitride semiconductor. . In FIG. 5, an element isolation region, wiring, and the like actually exist, but are not described because they are not related to the characteristic portion of the nitride semiconductor device 1B. Moreover, the same code | symbol is attached | subjected to the component same as FIG. 1A, and description is abbreviate | omitted.
　窒化物半導体装置１Ｂは、実施の形態１の構成に対して、イオン注入部１５を追加している。イオン注入部１５は、この発明におけるパッド側イオン注入部を具体化したものであり、図５に示すように、ドレインパッド４ａおよびその周囲の下層の領域に形成されて当該領域を絶縁状態にする。なお、注入するイオンとしては、Ａｒ、Ｚｎなどのイオンが挙げられるが、注入領域が絶縁状態になるイオンであればよい。また、イオン注入部１５は、図２に示したイオン注入部６と同様に、基板７に至る深さの断面構造を有している。 In the nitride semiconductor device 1B, an ion implantation unit 15 is added to the configuration of the first embodiment. The ion implantation part 15 embodies the pad-side ion implantation part in the present invention, and as shown in FIG. 5, is formed in the drain pad 4a and the surrounding lower layer region to insulate the region. . Note that ions to be implanted include ions such as Ar and Zn, but any ions may be used as long as the implanted region is in an insulating state. Further, the ion implantation part 15 has a cross-sectional structure having a depth reaching the substrate 7 as in the case of the ion implantation part 6 shown in FIG.
　高温下では、ドレインパッド４ａの下方に対応する基板７の部分における真性キャリアも増大し、これに伴って寄生容量も増大する。
　そこで、ドレインパッド４ａおよびその周囲の下層の領域にイオンを注入して絶縁状態にすることで、ドレインパッド４ａの下方における寄生容量も低減することができる。
　従って、イオン注入部６とイオン注入部１５とを形成することで、高温下に発生する寄生容量を、実施の形態１の構成よりも低減することが可能となる。
　なお、図５では、ドレインパッド４ａおよびその周囲の下層にイオン注入部１５を形成した場合を示したが、少なくともドレインパッド４ａの下層の領域にイオン注入部１５が形成されていればよい。このように構成しても上記と同様の効果が得られる。 Under high temperature, intrinsic carriers in the portion of the substrate 7 corresponding to the lower side of the drain pad 4a also increase, and the parasitic capacitance increases accordingly.
Thus, by implanting ions into the drain pad 4a and the surrounding lower layer region to make it insulative, the parasitic capacitance below the drain pad 4a can also be reduced.
Therefore, by forming the ion implantation part 6 and the ion implantation part 15, it is possible to reduce the parasitic capacitance generated at a high temperature as compared with the configuration of the first embodiment.
Although FIG. 5 shows the case where the ion implantation part 15 is formed in the drain pad 4a and the surrounding lower layer, it is sufficient that the ion implantation part 15 is formed at least in the lower layer region of the drain pad 4a. Even if comprised in this way, the effect similar to the above is acquired.
　図６は、この発明の実施の形態３に係る窒化物半導体装置１Ｃのパターンレイアウトを示す平面図であって、窒化物半導体装置１Ｃが窒化物半導体で形成されたＨＥＭＴである場合を示している。図６においても、実際には、素子分離領域、配線などが存在するが、窒化物半導体装置１Ｃの特徴部分とは関連がないため記載を省略している。また、図１Ａと同一の構成要素には同一の符号を付して説明を省略する。 FIG. 6 is a plan view showing a pattern layout of nitride semiconductor device 1C according to the third embodiment of the present invention, and shows a case where nitride semiconductor device 1C is a HEMT formed of a nitride semiconductor. . Also in FIG. 6, there are actually element isolation regions, wirings, etc., but the description is omitted because they are not related to the characteristic portions of the nitride semiconductor device 1C. Moreover, the same code | symbol is attached | subjected to the component same as FIG. 1A, and description is abbreviate | omitted.
　窒化物半導体装置１Ｃは、実施の形態１の構成に対して、イオン注入部１６を追加している。イオン注入部１６は、この発明におけるパッド側イオン注入部を具体化したものであり、図６に示すようにゲートパッド２ａおよびその周囲の下層の領域に形成されて当該領域を絶縁状態にする。なお、注入するイオンとしては、Ａｒ、Ｚｎなどのイオンが挙げられるが、注入領域が絶縁状態になるイオンであればよい。また、イオン注入部１６は、図２に示したイオン注入部６と同様に、基板７に至る深さの断面構造を有している。 In the nitride semiconductor device 1C, an ion implantation unit 16 is added to the configuration of the first embodiment. The ion implantation portion 16 embodies the pad-side ion implantation portion in the present invention, and is formed in the gate pad 2a and the surrounding lower region as shown in FIG. Note that ions to be implanted include ions such as Ar and Zn, but any ions may be used as long as the implanted region is in an insulating state. Further, the ion implantation part 16 has a cross-sectional structure having a depth reaching the substrate 7, similarly to the ion implantation part 6 shown in FIG. 2.
　高温下では、ゲートパッド２ａの下方に対応する基板７の部分における真性キャリアも増大し、これに伴って寄生容量も増大する。
　そこで、ゲートパッド２ａおよびその周囲の下層の領域にイオンを注入して絶縁状態にすることで、ゲートパッド２ａの下方における寄生容量も低減することができる。
　従って、イオン注入部６とイオン注入部１６とを形成することで、高温下に発生する寄生容量を、実施の形態１の構成よりも低減することが可能となる。
　なお、図６では、ゲートパッド２ａおよびその周囲の下層にイオン注入部１６を形成した場合を示したが、少なくともゲートパッド２ａの下層の領域にイオン注入部１６が形成されていればい。このように構成しても上記と同様の効果が得られる。 Under high temperature, intrinsic carriers in the portion of the substrate 7 corresponding to the lower side of the gate pad 2a also increase, and the parasitic capacitance increases accordingly.
Thus, by implanting ions into the gate pad 2a and the surrounding lower layer region so as to be in an insulating state, the parasitic capacitance below the gate pad 2a can also be reduced.
Therefore, by forming the ion implantation part 6 and the ion implantation part 16, it is possible to reduce the parasitic capacitance generated at a high temperature as compared with the configuration of the first embodiment.
Although FIG. 6 shows the case where the ion implantation portion 16 is formed in the gate pad 2a and the surrounding lower layer, it is sufficient that the ion implantation portion 16 is formed at least in the region under the gate pad 2a. Even if comprised in this way, the effect similar to the above is acquired.
　なお、実施の形態１の構成に対してイオン注入部１５とイオン注入部１６の両方を追加してもよい。このように構成することで、ドレインパッド４ａの下方における寄生容量とゲートパッド２ａの下方における寄生容量の両方を低減することができる。 In addition, you may add both the ion implantation part 15 and the ion implantation part 16 with respect to the structure of Embodiment 1. FIG. With this configuration, it is possible to reduce both the parasitic capacitance below the drain pad 4a and the parasitic capacitance below the gate pad 2a.
　以上のように、実施の形態３に係る窒化物半導体装置１Ｂは、ドレイン電極部４ｂの基部であるドレインパッド４ａの下層の領域を絶縁状態にするイオン注入部１５を備える。このように構成することで、ドレインパッド４ａの下方における寄生容量も低減することができる。 As described above, the nitride semiconductor device 1B according to the third embodiment includes the ion implanter 15 that insulates the region under the drain pad 4a that is the base of the drain electrode portion 4b. With this configuration, the parasitic capacitance below the drain pad 4a can also be reduced.
　また、実施の形態３に係る窒化物半導体装置１Ｃは、ゲート電極部２ｂの基部であるゲートパッド２ａの下層の領域を絶縁状態にするイオン注入部１６を備える。
　このように構成することで、ゲートパッド２ａの下方における寄生容量も低減することができる。 In addition, nitride semiconductor device 1C according to the third embodiment includes an ion implantation portion 16 that insulates a region under the gate pad 2a that is a base portion of the gate electrode portion 2b.
With this configuration, the parasitic capacitance below the gate pad 2a can also be reduced.
実施の形態４．
　図７は、この発明の実施の形態４に係る窒化物半導体装置１Ｄのパターンレイアウトを示す平面図であって、窒化物半導体装置１Ｄが窒化物半導体で形成されたＨＥＭＴである場合を示している。図７においても、実際には、素子分離領域、配線などが存在するが、窒化物半導体装置１Ｄの特徴部分とは関連がないため記載を省略している。また、図１Ａと同一の構成要素には同一の符号を付して説明を省略する。 Embodiment 4 FIG.
FIG. 7 is a plan view showing a pattern layout of a nitride semiconductor device 1D according to the fourth embodiment of the present invention, and shows a case where the nitride semiconductor device 1D is a HEMT formed of a nitride semiconductor. . Even in FIG. 7, an element isolation region, wiring, and the like actually exist, but are not described because they are not related to the characteristic portion of the nitride semiconductor device 1D. Moreover, the same code | symbol is attached | subjected to the component same as FIG. 1A, and description is abbreviate | omitted.
　窒化物半導体装置１Ｄは、実施の形態１の構成に対して、エアブリッジ１７を追加している。エアブリッジ１７は、この発明における接続部を具体化したものであり、ゲートパッド２ａから二股に分岐して延びるゲート電極部２ｂ，２ｂの端部同士を接続している。
　窒化物半導体装置１ＤのＨＥＭＴを増幅器に使用した場合、エアブリッジ１７によってゲート電極部２ｂ，２ｂの端部同士を接続することで、高周波動作時の寄生発振を抑制することが可能となる。 In the nitride semiconductor device 1D, an air bridge 17 is added to the configuration of the first embodiment. The air bridge 17 embodies the connecting portion in the present invention, and connects the end portions of the gate electrode portions 2b and 2b extending in a bifurcated manner from the gate pad 2a.
When the HEMT of the nitride semiconductor device 1D is used for an amplifier, the end portions of the gate electrode portions 2b and 2b are connected to each other by the air bridge 17, thereby making it possible to suppress parasitic oscillation during high frequency operation.
　図８は、この発明の実施の形態４に係る窒化物半導体装置１Ｅのパターンレイアウトを示す平面図であって、窒化物半導体装置１Ｅが窒化物半導体で形成されたＨＥＭＴである場合を示している。図８においても、実際には、素子分離領域、配線などが存在するが、窒化物半導体装置１Ｅの特徴部分とは関連がないため記載を省略している。また、図１Ａと同一の構成要素には同一の符号を付して説明を省略する。 FIG. 8 is a plan view showing a pattern layout of nitride semiconductor device 1E according to the fourth embodiment of the present invention, and shows a case where nitride semiconductor device 1E is a HEMT formed of a nitride semiconductor. . Also in FIG. 8, there are actually element isolation regions, wirings, etc., but the description is omitted because they are not related to the characteristic portions of the nitride semiconductor device 1E. Moreover, the same code | symbol is attached | subjected to the component same as FIG. 1A, and description is abbreviate | omitted.
　窒化物半導体装置１Ｅは、実施の形態１の構成に対して、エアブリッジ１８を追加している。エアブリッジ１８は、この発明における接続部を具体化したものであり、隣り合うソース電極部３，３の端部同士を接続している。
　窒化物半導体装置１ＥのＨＥＭＴを増幅器に使用した場合、ソース電極部３，３において、ビア５が形成された端部から延びる他方の端部同士をエアブリッジ１８によって接続することで、ビア５に生じたソースインダクタンスの影響が低減されて、ＨＥＭＴの最大発振周波数を増大させることが可能となる。 In the nitride semiconductor device 1E, an air bridge 18 is added to the configuration of the first embodiment. The air bridge 18 embodies the connection portion in the present invention, and connects the end portions of the adjacent source electrode portions 3 and 3 to each other.
When the HEMT of the nitride semiconductor device 1E is used for an amplifier, the other end portions extending from the end portion where the via 5 is formed in the source electrode portions 3 and 3 are connected to each other by the air bridge 18 to the via 5. The influence of the generated source inductance is reduced, and the maximum oscillation frequency of the HEMT can be increased.
　図９は、この発明の実施の形態４に係る窒化物半導体装置１Ｆのパターンレイアウトを示す平面図であって、窒化物半導体装置１Ｆが窒化物半導体で形成されたＨＥＭＴである場合を示している。図９においても、実際には、素子分離領域、配線などが存在するが、窒化物半導体装置１Ｆの特徴部分とは関連がないため記載を省略している。また、図１Ａと同一の構成要素には同一の符号を付して説明を省略する。 FIG. 9 is a plan view showing a pattern layout of nitride semiconductor device 1F according to the fourth embodiment of the present invention, and shows a case where nitride semiconductor device 1F is a HEMT formed of a nitride semiconductor. . In FIG. 9 as well, there are actually element isolation regions, wirings, etc., but the description is omitted because they are not related to the characteristic portions of nitride semiconductor device 1F. Moreover, the same code | symbol is attached | subjected to the component same as FIG. 1A, and description is abbreviate | omitted.
　窒化物半導体装置１Ｆは、実施の形態１の構成に対して、エアブリッジ１９を追加している。エアブリッジ１９は、この発明における接続部を具体化したものであり、ドレインパッド４ａから二股に分岐して延びるドレイン電極部４ｂ，４ｂの端部同士を接続している。窒化物半導体装置１ＦのＨＥＭＴを増幅器に使用した場合、エアブリッジ１９によりドレイン電極部４ｂ，４ｂの端部同士を接続することで、高周波動作時の寄生発振を抑制することが可能となる。 The nitride semiconductor device 1F has an air bridge 19 added to the configuration of the first embodiment. The air bridge 19 embodies the connection portion in the present invention, and connects the end portions of the drain electrode portions 4b and 4b extending in a bifurcated manner from the drain pad 4a. When the HEMT of the nitride semiconductor device 1F is used for an amplifier, by connecting the ends of the drain electrode portions 4b and 4b with the air bridge 19, it is possible to suppress parasitic oscillation during high frequency operation.
　なお、エアブリッジ１７、エアブリッジ１８およびエアブリッジ１９をそれぞれ別個に形成した構成を示したが、これらのうちの２つ以上を備えた構成であってもよい。
　例えば、エアブリッジ１７、エアブリッジ１８およびエアブリッジ１９の全てを備えてもよい。また、エアブリッジ１７およびエアブリッジ１８、エアブリッジ１８およびエアブリッジ１９、エアブリッジ１７およびエアブリッジ１９のいずれかの組み合わせであってもよい。このように構成することでも、上記と同様の効果が得られる。 In addition, although the structure which formed the air bridge 17, the air bridge 18, and the air bridge 19 separately was shown, the structure provided with two or more of these may be sufficient.
For example, all of the air bridge 17, the air bridge 18, and the air bridge 19 may be provided. Further, any combination of the air bridge 17 and the air bridge 18, the air bridge 18 and the air bridge 19, the air bridge 17 and the air bridge 19 may be used. Even with this configuration, the same effect as described above can be obtained.
　また、この発明における接続部がエアブリッジである場合を示したが、これ以外の配線構造であってもよい。すなわち、接続対象の電極部の端部同士を電気的に接続できる構造であれば採用することができる。 Moreover, although the case where the connecting portion in the present invention is an air bridge is shown, a wiring structure other than this may be used. In other words, any structure that can electrically connect the ends of the electrode parts to be connected can be employed.
　以上のように、実施の形態４に係る窒化物半導体装置１Ｄは、ゲートパッド２ａから二股に分岐して延びるゲート電極部２ｂ，２ｂの端部同士を接続するエアブリッジ１７を備える。このように構成することで、窒化物半導体装置１ＤのＨＥＭＴを増幅器に使用した場合に、高周波動作時の寄生発振を抑制することができる。 As described above, the nitride semiconductor device 1D according to the fourth embodiment includes the air bridge 17 that connects the ends of the gate electrode portions 2b and 2b that extend in a bifurcated manner from the gate pad 2a. With this configuration, when the HEMT of the nitride semiconductor device 1D is used for an amplifier, parasitic oscillation during high-frequency operation can be suppressed.
　また、実施の形態４に係る窒化物半導体装置１Ｅは、隣り合ったソース電極部３，３の端部同士を接続するエアブリッジ１８を備える。このように構成することで、ビア５に生じたソースインダクタンスの影響が低減されて、窒化物半導体装置１ＥのＨＥＭＴの最大発振周波数を増大させることが可能となる。 Further, the nitride semiconductor device 1E according to the fourth embodiment includes an air bridge 18 that connects the end portions of the adjacent source electrode portions 3 and 3 to each other. With this configuration, the influence of the source inductance generated in the via 5 is reduced, and the maximum oscillation frequency of the HEMT of the nitride semiconductor device 1E can be increased.
　さらに、実施の形態４に係る窒化物半導体装置１Ｆは、ドレインパッド４ａから二股に分岐して延びるドレイン電極部４ｂ，４ｂの端部同士を接続するエアブリッジ１９を備える。このように構成することで、窒化物半導体装置１ＦのＨＥＭＴを増幅器に使用した場合に、高周波動作時の寄生発振を抑制することができる。 Furthermore, the nitride semiconductor device 1F according to the fourth embodiment includes the air bridge 19 that connects the ends of the drain electrode portions 4b and 4b that extend in a bifurcated manner from the drain pad 4a. With this configuration, when the HEMT of the nitride semiconductor device 1F is used for an amplifier, it is possible to suppress parasitic oscillation during high-frequency operation.
実施の形態５．
　図１０は、この発明の実施の形態５に係る窒化物半導体装置１Ｇのパターンレイアウトを示す平面図であり、窒化物半導体装置１Ｇが窒化物半導体で形成されたＨＥＭＴである場合を示している。図１０においても、実際には素子分離領域、配線などが存在するが、窒化物半導体装置１Ｇの特徴部分とは関連がないため記載を省略している。また、図１Ａと同一の構成要素には同一の符号を付して説明を省略する。 Embodiment 5 FIG.
FIG. 10 is a plan view showing a pattern layout of nitride semiconductor device 1G according to the fifth embodiment of the present invention, and shows a case where nitride semiconductor device 1G is a HEMT formed of a nitride semiconductor. Also in FIG. 10, there are actually element isolation regions, wirings, etc., but the description is omitted because they are not related to the characteristic portions of the nitride semiconductor device 1G. Moreover, the same code | symbol is attached | subjected to the component same as FIG. 1A, and description is abbreviate | omitted.
　窒化物半導体装置１Ｇは、実施の形態１で示したソース電極部３、ゲート電極部２ｂ、ドレイン電極部４ｂおよびイオン注入部６がバリア層１０の上層に複数並んで配置された構成を有している。これにより、複数のトランジスタが集積された構造となり、この構造のＨＥＭＴにおけるトータル出力電力を増大させることが可能となる。
　なお、図１０では図１Ａのパターンを２つ並べた構成を示したが、３つ以上のパターンを並べた構成であってもよい。これにより、この構造のＨＥＭＴにおけるトータル出力電力をさらに増大させることができる。 The nitride semiconductor device 1G has a configuration in which a plurality of source electrode portions 3, gate electrode portions 2b, drain electrode portions 4b, and ion implantation portions 6 described in the first embodiment are arranged in an upper layer of the barrier layer 10. ing. As a result, a structure in which a plurality of transistors are integrated is provided, and the total output power in the HEMT having this structure can be increased.
10 shows a configuration in which two patterns of FIG. 1A are arranged, a configuration in which three or more patterns are arranged may be used. Thereby, the total output power in the HEMT having this structure can be further increased.
　以上のように、実施の形態５に係る窒化物半導体装置１Ｇは、ソース電極部３、ゲート電極部２ｂ、ドレイン電極部４ｂおよびイオン注入部６をバリア層１０の上層に複数並んで配置している。これにより、窒化物半導体装置１ＧであるＨＥＭＴのトータル出力電力を増大させることができる。 As described above, nitride semiconductor device 1G according to the fifth embodiment has a plurality of source electrode portions 3, gate electrode portions 2b, drain electrode portions 4b, and ion implantation portions 6 arranged side by side on the upper layer of barrier layer 10. Yes. Thereby, the total output power of the HEMT that is the nitride semiconductor device 1G can be increased.
　なお、図１０では、図１Ａに示したパターンをバリア層１０の上層に複数並べて形成した構成を示したが、これに限定されるものではない。例えば、図４から図９までに示した各パターンをバリア層１０の上層に複数並べて形成してもよい。
　また、図４から図９までに示した構成を適宜組み合わせたパターンを、バリア層１０の上層に複数並べて形成してもよい。 10 shows a configuration in which a plurality of the patterns shown in FIG. 1A are arranged on the upper layer of the barrier layer 10, but the present invention is not limited to this. For example, a plurality of the patterns shown in FIGS. 4 to 9 may be formed side by side on the upper layer of the barrier layer 10.
Further, a plurality of patterns obtained by appropriately combining the configurations shown in FIGS. 4 to 9 may be formed on the upper layer of the barrier layer 10.
実施の形態６．
　図１１は、この発明の実施の形態６に係る窒化物半導体装置１Ｈのパターンレイアウトを示す平面図であり、窒化物半導体装置１Ｈが窒化物半導体で形成されたＨＥＭＴである場合を示している。図１１においても、実際には素子分離領域、配線などが存在するが、窒化物半導体装置１Ｈの特徴部分とは関連がないため記載を省略している。また、図１Ａと同一の構成要素には同一の符号を付して説明を省略する。 Embodiment 6 FIG.
FIG. 11 is a plan view showing a pattern layout of nitride semiconductor device 1H according to the sixth embodiment of the present invention, and shows a case where nitride semiconductor device 1H is a HEMT formed of a nitride semiconductor. In FIG. 11 as well, there are actually element isolation regions, wirings, etc., but the description is omitted because they are not related to the characteristic portions of the nitride semiconductor device 1H. Moreover, the same code | symbol is attached | subjected to the component same as FIG. 1A, and description is abbreviate | omitted.
　窒化物半導体装置１Ｈは、実施の形態５と同様にソース電極部３、ゲート電極部２ｂ、ドレイン電極部４ｂおよびイオン注入部６がバリア層１０の上層に複数並んで配置された構成を有している。さらに、窒化物半導体装置１Ｈは、ソース電極部３Ａを備えている。
　ソース電極部３Ａは、図１１に示すように、ビア５が形成された一方の端部３ａから二股に分岐して延びる電極部３ｂ，３ｂが他方の端部３ｃで互いに接続された平面形状を有している。また、ソース電極部３Ａの両側には、ゲート電極部２ｂ、ドレイン電極部４ｂおよびイオン注入部６で構成されるパターンがそれぞれ形成される。 Nitride semiconductor device 1H has a configuration in which a plurality of source electrode portions 3, gate electrode portions 2b, drain electrode portions 4b, and ion implantation portions 6 are arranged in the upper layer of barrier layer 10 as in the fifth embodiment. ing. Furthermore, the nitride semiconductor device 1H includes a source electrode portion 3A.
As shown in FIG. 11, the source electrode portion 3A has a planar shape in which electrode portions 3b and 3b extending bifurcated from one end 3a where the via 5 is formed are connected to each other at the other end 3c. Have. In addition, on both sides of the source electrode portion 3A, patterns each including the gate electrode portion 2b, the drain electrode portion 4b, and the ion implantation portion 6 are formed.
　電極部３ｂ，３ｂの間の領域には、イオン注入によってイオン注入部２０が形成されている。イオン注入部２０は、この発明のソース側イオン注入部を具体化したものであり、図１１に示すように、電極部３ｂ，３ｂの間の領域に形成されて当該領域を絶縁状態にする。なお、注入するイオンとしては、Ａｒ、Ｚｎなどのイオンが挙げられるが、注入領域が絶縁状態になるイオンであればよい。イオン注入部２０は、図２に示したイオン注入部６と同様に、基板７に至る深さの断面構造を有している。 In the region between the electrode portions 3b and 3b, an ion implanted portion 20 is formed by ion implantation. The ion implantation part 20 embodies the source side ion implantation part of the present invention, and as shown in FIG. 11, is formed in a region between the electrode parts 3b and 3b to make the region insulative. Note that ions to be implanted include ions such as Ar and Zn, but any ions may be used as long as the implanted region is in an insulating state. Similar to the ion implantation part 6 shown in FIG. 2, the ion implantation part 20 has a cross-sectional structure having a depth reaching the substrate 7.
　窒化物半導体装置１Ｈでは、ソース電極部３Ａが、一方の端部３ａから二股に分岐して延びる電極部３ｂ，３ｂが、他方の端部３ｃで互いに接続された平面形状を有している。また、ソース電極部３Ａは、隣り合うゲート電極２，２の間に配置されている。
　これにより、ソース電極部３Ａの電極部３ｂの幅Ｗｓの寸法と、隣り合ったゲート電極部２ｂ，２ｂの間のゲートピッチＬｇｇとを同じ寸法にする必要がなく、これらの寸法を独立して決定することができる。従って、電極部３ｂの幅Ｗｓを狭く、かつゲートピッチＬｇｇを広く保つことができるため、熱抵抗Ｒｔｈの増大を抑制しかつ電極部３ｂの下方における容量Ｃｓｕｂを低減することが可能となる。 In nitride semiconductor device 1H, source electrode portion 3A has a planar shape in which electrode portions 3b and 3b extending from one end portion 3a and branching into two branches are connected to each other at the other end portion 3c. The source electrode portion 3A is disposed between the adjacent gate electrodes 2 and 2.
Thereby, it is not necessary to make the dimension of the width Ws of the electrode part 3b of the source electrode part 3A and the gate pitch Lgg between the adjacent gate electrode parts 2b and 2b the same dimension, and these dimensions can be made independently. Can be determined. Therefore, since the width Ws of the electrode part 3b can be narrowed and the gate pitch Lgg can be kept wide, it is possible to suppress an increase in the thermal resistance Rth and reduce the capacitance Csub below the electrode part 3b.
　また、隣り合った電極部３ｂ，３ｂ間の領域は、イオン注入部２０によって絶縁状態となっている。すなわち、この領域には２次元電子ガスが存在しないため、チャネル層９中の２次元電子ガスによって電極部３ｂ，３ｂが電気的に接続されることがない。 Further, the region between the adjacent electrode portions 3b, 3b is insulated by the ion implantation portion 20. That is, since there is no two-dimensional electron gas in this region, the electrode portions 3 b and 3 b are not electrically connected by the two-dimensional electron gas in the channel layer 9.
　以上のように、実施の形態６に係る窒化物半導体装置１Ｈにおいて、ソース電極部３Ａは、一方の端部３ａから二股に分岐して延びる電極部３ｂ，３ｂが他方の端部３ｃで互いに接続された平面形状を有している。そして、隣り合った電極部３ｂ，３ｂの間の領域を絶縁状態にするイオン注入部２０を備える。
　このように構成することで、ゲートピッチＬｇｇを広くしつつ、ドレイン電極部４ｂの幅Ｗｄとソース電極部３Ａの電極部３ｂの幅Ｗｓの両方を狭くすることができる。
　これにより、高温下で基板７中に発生する寄生容量を、実施の形態５の構成よりも低減できる。また、ゲートピッチＬｇｇが広くなるので、熱抵抗Ｒｔｈの増大も抑制することができる。 As described above, in nitride semiconductor device 1H according to the sixth embodiment, source electrode portion 3A has electrode portions 3b and 3b extending in a bifurcated manner from one end portion 3a and connected to each other at the other end portion 3c. Has a planar shape. And the ion implantation part 20 which makes the area | region between the adjacent electrode parts 3b and 3b an insulation state is provided.
With this configuration, it is possible to reduce both the width Wd of the drain electrode portion 4b and the width Ws of the electrode portion 3b of the source electrode portion 3A while increasing the gate pitch Lgg.
Thereby, the parasitic capacitance generated in the substrate 7 at a high temperature can be reduced as compared with the configuration of the fifth embodiment. Further, since the gate pitch Lgg is widened, an increase in the thermal resistance Rth can be suppressed.
　また、図１１に示した構成に対して、例えば図４から図９までに示した特徴部分または図４から図９までに示した特徴部分を適宜組み合わせた構成を追加してもよい。
　例えば、図１１の構成に対してゲートフィールドプレート１３、ソースフィールドプレート１４、イオン注入部１５、イオン注入部１６、エアブリッジ１７、エアブリッジ１８およびエアブリッジ１９のうちの少なくとも１つを追加してもよい。このようにしても、実施の形態２から実施の形態４までに示した効果が得られる。 Further, for example, a configuration obtained by appropriately combining the feature portions shown in FIGS. 4 to 9 or the feature portions shown in FIGS. 4 to 9 may be added to the configuration shown in FIG.
For example, at least one of a gate field plate 13, a source field plate 14, an ion implantation unit 15, an ion implantation unit 16, an air bridge 17, an air bridge 18, and an air bridge 19 is added to the configuration of FIG. 11. Also good. Even if it does in this way, the effect shown in Embodiment 2 to Embodiment 4 will be acquired.
　なお、本発明はその発明の範囲内において、各実施の形態の自由な組み合わせ、あるいは各実施の形態の任意の構成要素の変形、もしくは各実施の形態において任意の構成要素の省略が可能である。 In the present invention, within the scope of the invention, any combination of each embodiment, any component of each embodiment can be modified, or any component can be omitted in each embodiment. .
　この発明に係る窒化物半導体装置は、高温下に、真性キャリアとドレイン電極部との間に発生する寄生容量を低減し、かつ熱抵抗の増大を抑制することができるので、例えば、マイクロ波増幅器などのＨＥＭＴとして利用することができる。 The nitride semiconductor device according to the present invention can reduce the parasitic capacitance generated between the intrinsic carrier and the drain electrode portion at a high temperature and can suppress an increase in thermal resistance. It can be used as a HEMT.
　１，１Ａ～１Ｈ，１００　窒化物半導体装置、２，１０１　ゲート電極、２ａ，１０１ａ　ゲートパッド、２ｂ，１０１ｂ　ゲート電極部、３，３Ａ，１０２　ソース電極部、３ａ，３ｃ　端部、３ｂ　電極部、４，１０３　ドレイン電極、４ａ，１０３ａ　ドレインパッド、４ｂ，１０３ｂ　ドレイン電極部、５　ビア、６，１５，１６，２０　イオン注入部、７　基板、８　バッファ層、９　チャネル層、１０　バリア層、１１，１２　絶縁層、１３　ゲートフィールドプレート、１４　ソースフィールドプレート、１７～１９　エアブリッジ。 1,1A-1H, 100 nitride semiconductor device, 2,101 gate electrode, 2a, 101a gate pad, 2b, 101b gate electrode part, 3,3A, 102 source electrode part, 3a, 3c end part, 3b electrode part, 4, 103 drain electrode, 4a, 103a drain pad, 4b, 103b drain electrode part, 5 via, 6, 15, 16, 20 ion implanted part, 7 substrate, 8 buffer layer, 9 channel layer, 10 barrier layer, 11, 12 insulating layers, 13 gate field plates, 14 source field plates, 17-19 air bridge.

Claims (8)

  1. 　電子が走行するチャネル層と、
    　前記チャネル層の上層にインジウム、アルミニウムおよびガリウムのうちの少なくとも１つと窒素を含んで形成されて前記チャネル層に２次元電子ガスを形成するバリア層と、
    　前記バリア層の上層に並んで配置された短冊状のソース電極部と、
    　隣り合った前記ソース電極部の間に配置されて基部から二股に分岐して延びるゲート電極部と、
    　隣り合った前記ゲート電極部の間に配置されて基部から二股に分岐して延びるドレイン電極部と、
    　隣り合った前記ドレイン電極部の間の領域を絶縁状態にするイオン注入部と
    を備えたことを特徴とする窒化物半導体装置。     A channel layer where electrons travel,
    A barrier layer formed on the channel layer and containing at least one of indium, aluminum, and gallium and nitrogen to form a two-dimensional electron gas in the channel layer;
    A strip-shaped source electrode portion arranged side by side on the upper layer of the barrier layer;
    A gate electrode portion arranged between the source electrode portions adjacent to each other and extending bifurcated from the base portion;
    A drain electrode portion disposed between the gate electrode portions adjacent to each other and extending bifurcated from a base portion; and
    A nitride semiconductor device comprising: an ion implantation portion that insulates a region between adjacent drain electrode portions.
  2. 　前記ゲート電極部および前記ソース電極部のうちの少なくとも一方に設けたフィールドプレートを備えたことを特徴とする請求項１記載の窒化物半導体装置。 The nitride semiconductor device according to claim 1, further comprising a field plate provided on at least one of the gate electrode portion and the source electrode portion.
  3. 　前記ドレイン電極部の基部および前記ゲート電極部の基部のうちの少なくとも一方の下層の領域を絶縁状態にするパッド側イオン注入部を備えたことを特徴とする請求項１記載の窒化物半導体装置。 2. The nitride semiconductor device according to claim 1, further comprising a pad-side ion implantation portion that insulates at least one lower layer region of the base portion of the drain electrode portion and the base portion of the gate electrode portion.
  4. 　基部から二股に分岐して延びる前記ゲート電極部の端部同士を接続する接続部を備えたことを特徴とする請求項１記載の窒化物半導体装置。 2. The nitride semiconductor device according to claim 1, further comprising a connection portion that connects ends of the gate electrode portion extending in a bifurcated manner from the base portion.
  5. 　隣り合った前記ソース電極部の端部同士を接続する接続部を備えたことを特徴とする請求項１記載の窒化物半導体装置。 The nitride semiconductor device according to claim 1, further comprising a connecting portion that connects ends of the adjacent source electrode portions.
  6. 　基部から二股に分岐して延びる前記ドレイン電極部の端部同士を接続する接続部を備えたことを特徴とする請求項１記載の窒化物半導体装置。 2. The nitride semiconductor device according to claim 1, further comprising a connection portion that connects ends of the drain electrode portion extending in a bifurcated manner from the base portion.
  7. 　前記ソース電極部、前記ゲート電極部、前記ドレイン電極部および前記イオン注入部が前記バリア層の上層に複数並んで配置されていることを特徴とする請求項１記載の窒化物半導体装置。 2. The nitride semiconductor device according to claim 1, wherein a plurality of the source electrode portion, the gate electrode portion, the drain electrode portion, and the ion implantation portion are arranged in an upper layer of the barrier layer.
  8. 　前記ソース電極部は、一方の端部から二股に分岐して延びる電極部が他方の端部で互いに接続された平面形状を有しており、
    　隣り合った前記電極部の間の領域を絶縁状態にするソース側イオン注入部を備えたことを特徴とする請求項７記載の窒化物半導体装置。     The source electrode portion has a planar shape in which electrode portions extending in a bifurcated manner from one end portion are connected to each other at the other end portion,
    The nitride semiconductor device according to claim 7, further comprising a source-side ion implantation unit that insulates a region between the adjacent electrode units.
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JP2022147859A (en) * 2021-03-23 2022-10-06 株式会社東芝 Semiconductor device

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