WO2017096520A1

WO2017096520A1 - Hierarchical power domain organization

Info

Publication number: WO2017096520A1
Application number: PCT/CN2015/096640
Authority: WO
Inventors: Xiaoqiang WU; Yanfei CAI; Jonathan Zhang
Original assignee: Qualcomm Incorporated
Priority date: 2015-12-08
Filing date: 2015-12-08
Publication date: 2017-06-15
Also published as: WO2017096750A1

Abstract

An integrated circuit (IC) (106) is disclosed herein for hierarchical power domain organization. An IC (106) includes a power distribution path (110), a first circuit block (202), a first block switch (212), a second circuit block (204), and a second block switch (214). The power distribution path (110) is configured to provide a distribution voltage (120). The first block switch (212) is coupled to the first circuit block (202) and to the power distribution path (110). The first block switch (212) and the second block switch (214) are switchable. The first block switch (212) is configured to provide a first-level voltage (122) to the first circuit block (202) using the distribution voltage (120). The second block switch (214) is coupled to the second circuit block (204) and to the first block switch (212). The second block switch (214) is configured to provide a second-level voltage (124) to the second circuit block (204) using the first-level voltage (122).

Description

HIERARCHICAL POWER DOMAIN ORGANIZATION

BACKGROUND

Field of the Disclosure

This disclosure relates generally to power management of integrated circuits (ICs) that are used in electronic devices and, more specifically, to organizing power domains in a hierarchy to reduce leakage current and thereby lower power consumption.

Description of Related Art

Power consumption is an increasingly important concern in the design and use of electronic devices. From a global perspective, a multitude of electronic devices used by consumers and businesses consume significant amounts of power. Accordingly, efforts are made to lower the power consumption of electronic devices to help conserve the earth's resources and lower costs for both consumers and businesses. From an individual perspective, the prevalence of portable electronic devices that are powered by batteries continues to increase. The less energy that is consumed by, for instance, a portable battery-powered personal computing device, the longer the battery-powered computing device can operate without recharging the battery. Lower energy consumption also enables the use of smaller batteries and therefore the adoption of smaller and thinner form factors for portable electronic devices. Consequently, the popularity of portable electronic devices also provides a strong motivation to lower the power consumption of electronic devices.

Electronic devices include integrated circuits (ICs) that consume power while enabling the devices to perform functions for a user, such as aural or textual communicating, game playing, photo editing, or video streaming. Generally, integrated circuits include multiple circuit devices, such as memory storage units, mathematical processing units, buffers, and so forth. These circuit devices are built using one or more transistors. The transistors consume power while performing operations using voltages and currents. With portable electronic devices in particular, power usage by transistors can significantly impact battery life.

SUMMARY

In an example aspect, an integrated circuit is disclosed. The integrated circuit includes a power distribution path, a first circuit block, a first block switch, a second circuit block, and a second block switch. The power distribution path is configured to provide a distribution voltage. The first block switch is coupled to the first circuit block and to the power distribution path. The first block switch is configured to switchably provide a first-level voltage to the first circuit block using the distribution voltage. The second block switch is coupled to the second circuit block and to the first block switch. The second block switch is configured to switchably provide a second-level voltage to the second circuit block using the first-level voltage.

In an example aspect, an integrated circuit is disclosed. The integrated circuit includes a power distribution path, a first circuit block, and a second circuit block. The power distribution path is configured to provide a distribution voltage. The integrated circuit also includes first switching means for providing power to the first circuit block, with the first switching means configured to provide a first-level voltage to the first circuit block using the distribution voltage. The integrated circuit further includes second switching means for providing power to the second circuit block, with the second switching means configured to provide a second-level voltage to the second circuit block using the first-level voltage.

In an example aspect, a method for implementing a hierarchical power domain organization in an integrated circuit is disclosed. The method includes providing power to a second circuit block by performing a number of operations. An operation includes asserting a first enable power signal. Another operation includes switching on multiple first block switches based on the asserting of the first enable power signal. A further operation includes asserting a second enable power signal. An additional operation includes switching on multiple second block switches based on the asserting of the second enable power signal. A still further operation includes routing power to the second circuit block through the multiple first block switches and through the multiple second block switches.

In an example aspect, an apparatus is disclosed. The apparatus includes a power distribution path, multiple banks of block switches, and multiple power domains. The power distribution path is configured to provide a distribution voltage. The multiple banks of block switches are connected in series and coupled to the power distribution path. The multiple power domains are coupled to respective corresponding ones of the multiple banks of block switches in a hierarchical arrangement. The multiple power domains are configured to receive power from the multiple banks of block switches, with the multiple power domains configured such that a relatively lower-level power domain is provided power by switching on a respective corresponding bank of block switches and at least one bank of block switches corresponding to at least one relatively higher-level power domain.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 depicts a power source and an integrated circuit (IC) that illustrates an example of a hierarchical arrangement for power domain organization.

FIG. 2 depicts a portion of an integrated circuit that illustrates multiple circuit blocks and multiple block switches that are organized in accordance with an example hierarchical scheme.

FIG. 3 depicts a portion of an integrated circuit that illustrates an example component layout for multiple circuit blocks and multiple block switches for hierarchical power domain organization.

FIG. 4 depicts a portion of an integrated circuit that illustrates another example component layout for multiple circuit blocks and multiple block switches for hierarchical power domain organization.

FIG. 5 depicts multiple circuit devices that illustrate an example of a serial coupling for multiple block switches in relation to multiple circuit blocks.

FIG. 6 is a flow diagram illustrating an example process for implementing a hierarchical power domain organization.

FIG. 7 depicts an example electronic device that includes an integrated circuit having multiple blocks.

DETAILED DESCRIPTION

Transistors of integrated circuits (ICs) enable the computing capabilities of electronic devices. To operate, transistors use voltages and currents. If a voltage potential is applied across a transistor and the transistor is active (i.e., turned on) , the transistor consumes a relatively significant amount of power as current flows through the transistor. Unfortunately, even if a transistor is inactive (i.e., turned off) and not performing operations for an integrated circuit, the transistor can still consume power due to leakage current. If an integrated circuit includes numerous inactive transistors, the total amount of power consumed due to the total leakage current can be appreciable, even though the inactive transistors are not performing operations. However, power consumption due to leakage currents can be reduced if a voltage potential across the inactive transistors is reduced or removed.

Controlling or reducing an amount of power that an integrated circuit consumes over time or on an instantaneous basis is termed power management. Energy consumption can be reduced to zero or near zero during times of nonuse if an integrated circuit is powered down completely. At times of lower utilization, an integrated circuit may be partially powered down to reduce power consumption. For example, if an integrated circuit cannot be powered down as a whole, one or more blocks, or cores, may be powered down separately from one or more other blocks by reducing or removing the voltage available to the blocks being powered down. For instance, if an integrated circuit chip having a graphics processing unit (GPU) is waiting for additional data or user input before changing a display on a screen, a block of the integrated circuit that includes the GPU may be powered down. A block containing a modem that is idle may be powered down between incoming or outgoing communications. Also, if a memory is divided into two blocks and half of the memory is unused, the block with the unused memory half may be powered down, and the other block may remain powered.

With a conventional power management approach to organizing power domains, each block of multiple blocks is provided at least one corresponding block switch so that blocks can be powered down independently. If a given block is to be currently powered up, the corresponding block switch is switched on to provide power. If the given block is to be currently powered down, on the other hand, the corresponding block switch is switched off to save power. For integrated circuit chips in a wire-bonding package, a chip-level power path is extended from an external power source, or at least one pad designated for the external power source, directly to each separate block switch that respectively corresponds to each block of the multiple blocks. More specifically, although wire-bonded integrated circuit packages may have multiple pads that provide access to an external power source, the multiple pads are located along one or more edges of a die of the integrated circuit. Consequently, blocks that are disposed toward a center of the die are located relatively far from pads that provide access to external power.

This conventional approach to power domain organization creates a number of problems. With respect to a first problem, some blocks are placed in internal areas of an integrated circuit chip that are relatively far from the pad for the external power source. Consequently, the chip-level power path extends a great distance over the chip from the pad to the internal blocks. The long chip-level power path induces a higher current-resistance (IR) drop that impacts a voltage supply level for the distantly-placed blocks. Furthermore, the long chip-level power path consumes a greater proportion of the limited area of the integrated circuit chip. For this first problem, the increased IR drop can be partially mitigated by increasing a width of a metal forming the chip-level power path. This widening can reduce the IR drop. Unfortunately, the consumption of the limited area of the integrated circuit chip also increases along with the width of the chip-level power path.

With respect to a second problem created by conventional approaches to power domain organization, if multiple blocks are to be powered down to save energy, the respective sets of corresponding block switches for each respective block of the multiple blocks continue to consume power from the external power source due to leakage current, even while the block switches are switched off. For this second problem, the leakage current can be decreased with two approaches. With a first conventional approach, the channels of the transistors forming the block switches are lengthened. Although longer transistor channels result in lower leakage currents, longer transistor channels unfortunately also result in decreased current levels when the transistors are turned on because longer channels create greater resistances. Thus, lowering leakage currents with this first approach causes a corresponding block to receive less current when the block is powered up.

With a second conventional approach to decreasing leakage currents, fewer block switches in a set of block switches are utilized for each corresponding block. Although fewer block switches result in less leakage current when the transistors are turned off, the fewer block switches unfortunately also provide less current when the transistors are turned on. Thus, lowering leakage current with this second conventional approach reduces the on current linearly along with any reduction of the off leakage current. Furthermore, with fewer pathways for current to flow into a given block, IR performance suffers, especially for high frequency scenarios.

To at least partially address these problems, a hierarchical power domain organization can be implemented with an integrated circuit. In one or more embodiments, multiple banks of block switches are connected in series and coupled to a power distribution path for the integrated circuit. Multiple power domains are tied into the multiple banks of block switches at different nodes along the series to obtain power that is provided by the power distribution path if one or more upstream, or higher level, banks of block switches are switched on.

In these manners, the power distribution path may be disposed on the integrated circuit from a power source to a first bank of block switches. Area of the integrated circuit may be saved by avoiding extending the power distribution path to a second bank of block switches that is connected in series with the first bank of block switches. Moreover, if the first bank of block switches is switched off, any leakage current from the second bank of block switches, or one or more other downstream, or lower level, banks of block switches, occurs at a relatively negligible current level.

In one or more embodiments, an integrated circuit includes a power distribution path, a first block switch, a first circuit block, a second block switch, and a second circuit block. The power distribution path is implemented to provide a distribution voltage for multiple circuit blocks. The first block switch is coupled to the power distribution path and to the first circuit block and to the second block switch. The first block switch is implemented to switchably provide a first-level voltage to the first circuit block and the second block switch using the distribution voltage. The second block switch is coupled to the second circuit block and to the first block switch. The second block switch is implemented to switchably provide a second-level voltage to the second circuit block using the first-level voltage. The integrated circuit may additionally include a first-level distribution path that couples multiple first block switches to multiple second block switches, as well as to the first circuit block. The first-level distribution path may be formed using multiple respective parallel paths that extend between the multiple first block switches and the multiple second block switches.

In these manners, the second block switch can obtain power from the power distribution path via the first-level distribution path and the first block switch, which can reduce a length of the power distribution path that is disposed on an integrated circuit. Also, the second block switch does not permit an appreciable leakage current if the first block switch is switched off. Moreover, the overall IR drop to reach the second block switch can be lower because the overall power path to the second block switch is partially formed from multiple parallel paths, which can lower the resistance of the overall power path.

FIG. 1 depicts generally at 100 a power source 108 and an integrated circuit 106 that illustrates an example of a hierarchical arrangement for power domain organization. The power source 108 is shown to include a power management integrated circuit 118 (PMIC) . As illustrated, the integrated circuit 106 includes a first power domain 102, a second power domain 104, a power distribution path 110, a first bank of block switches 112, and a second bank of block switches 114. The first bank of block switches 112 and the second bank of block switches 114 are connected in series and coupled to the power distribution path 110. The first power domain 102 and the second power domain 104 obtain power by being connected at different nodes along the series connection of the banks of block switches.

The first bank of block switches 112 is coupled to the power distribution path 110 at a power distribution node 130. The first bank of block switches 112 is coupled to the second bank of block switches 114 at a first power node 132. A second power node 134 is indicated below the second bank of block switches 114 on the other side from the first bank of block switches 112. The first power domain 102 is coupled between the first power node 132 and ground. The second power domain 104 is coupled between the second power node 134 and ground.

In an example operation, the power management integrated circuit 118 of the power source 108 provides power to the power distribution path 110. Although the power source 108 is shown as being external to the integrated circuit 106, the power source 108 may alternatively be part of the integrated circuit 106. The power source 108 holds the power distribution path 110, and thus the power distribution node 130, at a distribution voltage 120 (VD) . If the first bank of block switches 112 is switched on, the first bank of block switches 112 uses the distribution voltage 120 to produce a first-level voltage 122 (V1L) at the first power node 132. A value of the first-level voltage 122 is close to that of the distribution voltage 120, but the first-level voltage 122 is lower due to the IR drop of intervening circuitry between the power distribution node 130 and the first power node 132. If the second bank of block switches 114 is switched on, as well as the first bank of block switches 112 being on, the second bank of block switches 114 produces a second-level voltage 124 (V2L) at the second power node 134 using the first-level voltage 122. A value of the second-level voltage 124 is close to that of the first-level voltage 122, but the second-level voltage 124 is lower due to the IR drop of intervening circuitry between the first power node 132 and the second power node 134. Thus, the first-level voltage 122 is lower than the distribution voltage 120, and the second-level voltage 124 is lower than the first-level voltage 122.

If the first bank of block switches 112 is holding the first power node 132 at the first-level voltage 122, the first power domain 102 receives power at the first-level voltage 122. If the first bank of block switches 112 is holding the first power node 132 at the first-level voltage 122, and if the second bank of block switches 114 is holding the second power node 134 at the second-level voltage 124, the second power domain 104 receives power at the second-level voltage 124. On one hand, if the first bank of block switches 112 is not switched on, the second bank of block switches 114 cannot produce the second-level voltage 124. On the other hand, if the first bank of block switches 112 is not switched on and the second bank of block switches 114 is not switched on, the second bank of block switches 114 does not generate an appreciable leakage current. Although two levels are shown of an example hierarchical power domain arrangement, three or more levels may alternatively be implemented by an integrated circuit 106.

FIG. 2 depicts a portion 200 of an integrated circuit that illustrates multiple circuit blocks and multiple block switches that are organized in accordance with an example hierarchical scheme. As shown, the portion 200 includes the power distribution path 110, a first block switch 212 (FBS) , a first circuit block 202, a second block switch 214 (SBS) , and a second circuit block 204. The first block switch 212 is coupled to the power distribution path 110. The first block switch 212 is also coupled to the first circuit block 202 and the second block switch 214. The second block switch 214 is coupled to the second circuit block 204 in addition to the first block switch 212. The first block switch 212 or the second block switch 214 may be implemented using, for example, multiple transistors that are arranged in parallel.

In an example operation, the first block switch 212 receives the distribution voltage 120 from the power distribution path 110. The first block switch 212, if switched on, produces the first-level voltage 122 from the supplied distribution voltage 120. The first block switch 212 provides the first-level voltage 122 to the first circuit block 202 and the second block switch 214. If the first block switch 212 is providing the first-level voltage 122, the second block switch 214, if switched on, produces the second-level voltage 124 from the received first-level voltage 122. The second block switch 214 provides the second-level voltage 124 to the second circuit block 204.

In a power management scenario, each circuit block can enter a sleep state or a wake state. In the sleep state, the sleeping circuit block can be powered down by switching off the corresponding block switch. Thus, switching off the second block switch 214 switches off the power to the second circuit block 204. With a hierarchical arrangement of block switches, switching off the first block switch 212 switches off the power, besides leakage power, to both the first circuit block 202 and the second block switch 214. With the power to the second block switch 214 switched off by the first block switch 212, the second block switch 214 cannot power the second circuit block 204 at an operational level that is sufficient for the second circuit block 204 to perform designated processing functionality, such as manipulating graphical information in a GPU or storing data in a volatile memory. Hence, the second circuit block 204 cannot receive power at an operational level from the power distribution path unless both the first block switch 212 and the second block switch 214 are switched on. However, with the power to the second block switch 214 switched off by the first block switch 212, any leakage current generated by the second block switch 214 is substantially less than that generated by the first block switch 212, which is coupled to the power distribution path 110 without any intervening block switch or switches in this example.

FIG. 3 depicts a portion of an integrated circuit that illustrates an example component layout 300 for multiple circuit blocks and multiple block switches for hierarchical power domain organization. As illustrated, the component layout 300 includes the power distribution path 110, the first circuit block 202, and the second circuit block 204. Example banks of block switches are shown as multiple first block switches 212-1 to 212-8 and multiple second block switches 214-1 to 214-8. The component layout 300 further includes a first-level distribution path 302 and a second-level distribution path 304.

In one or more embodiments, the power distribution path 110 may be formed from at least a portion of a layer of metal, such as a top metal layer or a redistribution layer (RDL) . The first-level distribution path 302 and the second-level distribution path 304 may be formed using one or more different layers of metal, such as at least one lower metal layer. The multiple first block switches 212-1 to 212-8 are distributed along at least a portion of the first circuit block 202. The multiple second block switches 214-1 to 214-8 are distributed along at least a portion of the first circuit block 202 or the second circuit block 204.

The multiple first block switches 212-1 to 212-8 are coupled to a power source (e.g., the power source 108 of FIG. 1) via the power distribution path 110. The multiple first block switches 212-1 to 212-8 are also coupled to the multiple second block switches 214-1 to 214-8 via the first-level distribution path 302. The multiple second block switches 214-1 to 214-8 are further coupled to the second circuit block 204 via the second-level distribution path 304. The multiple second block switches 214-1 to 214-8 are shown being disposed at a location relatively closer to the first circuit block 202 than to the second circuit block 204. This reduces the length of the first-level distribution path 302 relative to the length of the second-level distribution path 304, which can save power if the multiple second block switches 214-1 to 214-8 are switched off. However, the multiple second block switches 214-1 to 214-8 may alternatively be disposed relatively closer to the second circuit block 204 than to the first circuit block 202, or approximately equidistant between the two circuit blocks.

For a hierarchical arrangement, the multiple second block switches 214-1 to 214-8 are coupled between the multiple first block switches 212-1 to 212-8 and the second circuit block 204 via the first-level distribution path 302 and the second-level distribution path 304. The multiple first block switches 212-1 to 212-8 provide power to the multiple second block switches 214-1 to 214-8 via the first-level distribution path 302. The multiple second block switches 214-1 to 214-8 provide power to the second circuit block 204 via the second-level distribution path 304. Although the multiple first block switches 212-1 to 212-8 may provide power to the first circuit block 202 via the first-level distribution path 302, the multiple first block switches 212-1 to 212-8 may instead provide power to the first circuit block 202 via separate metal line connections (not shown) that leave the multiple first block switches 212-1 to 212-8 and that connect to many different nodes in the first circuit block 202.

In example implementations, the first-level distribution path 302 or the second-level distribution path 304 are realized using multiple parallel distribution paths. The overall increase in width of the distribution pathway or the parallel nature of the distribution paths effectively lowers the resistance of the first-level distribution path 302 and the second-level distribution path 304. The IR drop attributable to these parallel distribution paths is reduced accordingly. Consequently, the first-level voltage 122, and thus the distribution voltage 120, can be reduced while still achieving a desired minimum threshold for the second-level voltage 124. With lower voltage levels, power provided by a power source can be lowered, and total power consumption is reduced.

The multiple first block switches 212-1 to 212-8 may be implemented as multiple first block header switches, and the multiple second block switches 214-1 to 214-8 may be implemented as multiple second block header switches. Thus, certain examples of block switches, such as the first block switch 212 and the second block switch 214, are described herein or illustrated in the accompanying drawings as block header switches. However, hierarchical power domain organization is nevertheless applicable to implementations in which block switches are realized as block footer switches.

FIG. 4 depicts a portion of an integrated circuit that illustrates another example component layout 400 for multiple circuit blocks and multiple block switches for hierarchical power domain organization. In FIG. 4, the multiple first block switches (FBS) and the multiple second block switches (SBS) are shown over the metal layers of the power distribution path 110, the first-level distribution path 302, and the second-level distribution path 304 to improve clarity by enabling the reference lettering and numbering to be visible.

With component layout 400, multiple rows of block switches are implemented. For example, two rows of first block switches 212-1, 212-2, … 212-7, and 212-8 plus 212-9, 212-10, … 212-15, and 212-16 and two rows of second block switches 214-1, 214-2, … 214-7, 214-8 plus 214-9, 214-10, … 214-15, and 214-16 are shown. Adding a second row to the block switches increases (e.g., doubles) the number of current pathways that are implemented in parallel between the power distribution path 110 and the first-level distribution path 302 and between the first-level distribution path 302 and the second-level distribution path 304 to thereby decrease resistance and lower power usage.

Although two rows of block switches are described above and illustrated in FIG. 4, three or more rows may alternatively be implemented. Although the number of first block switches and the number of second block switches are shown as being equal for the component layout 300 (of FIG. 3) and the component layout 400, these numbers may alternatively differ from each other. For example, 16 first block switches 212-1 to 212-16 and eight second block switches 214-1 to 214-8 may be implemented. Also, each row may have a different number of block switches than eight.

FIG. 5 depicts generally at 500 multiple circuit devices that illustrate an example of a serial coupling for multiple block switches in relation to multiple circuit blocks. As shown, the power distribution path 110 corresponds to the power distribution node 130. A first block switch 212 (FBS) is coupled between the power distribution node 130 and the first power node 132. A second block switch 214 (SBS) is coupled between the first power node 132 and the second power node 134. The first circuit block 202 is coupled between the first power node 132 and ground. The second circuit block 204 is coupled between the second power node 134 and ground.

In one or more embodiments, the first block switch 212 is implemented with at least one first transistor 512, and the second block switch 214 is implemented with at least one second transistor 514. The first transistor 512 and the second transistor 514 are shown as p-type metal-oxide-semiconductor (PMOS) transistors. However, the first transistor 512 or the second transistor 514 may be implemented using an alternative transistor type, such as an n-type metal-oxide-semiconductor (NMOS) field effect transistor (FET) , a bipolar junction transistor (BJT) , and so forth. The first transistor 512 and the second transistor 514 each have a source, a drain, a gate, and a substrate terminal or node.

The source and substrate of the first transistor 512 are coupled to the power distribution node 130. The drain of the first transistor 512 is coupled to the first power node 132. The gate of the first transistor 512 serves as a first control input 532. The source and substrate of the second transistor 514 are coupled to the first power node 132. The drain of the second transistor 514 is coupled to the second power node 134. The gate of the second transistor 514 serves as a second control input 534. If the first transistor 512 is turned off, no appreciable current beyond leakage current flows from the power distribution node 130 to the first power node 132. However, if the first transistor 512 is turned on, current flows and the first transistor 512 produces the first-level voltage 122 at the first power node 132 using the distribution voltage 120 of the power distribution node 130. Thus, if turned on, the first transistor 512 provides the first-level voltage 122 to the first circuit block 202.

If the second transistor 514 is turned off, no appreciable current beyond leakage current flows from the first power node 132 to the second power node 134. However, if the second transistor 514 is turned on, current flows and the second transistor 514 produces the second-level voltage 124 at the second power node 134 using the first-level voltage 122 of the first power node 132. Thus, if the first transistor 512 and the second transistor 514 are both turned on, the second transistor 514 provides the second-level voltage 124 to the second circuit block 204. The first block switch 212 provides first switching means for providing power to the first circuit block 202, with the first switching means configured to provide a first-level voltage 122 to the first circuit block 202 using the distribution voltage 120. The second block switch 214 provides second switching means for providing power to the second circuit block 204, with the second switching means configured to provide a second-level voltage 124 to the second circuit block 204 using the first-level voltage 122.

In an example operation, the first control input 532 receives a first enable power signal 502 via a buffer 522. The second control input 534 receives a second enable power signal 504 via a buffer 524. If the first enable power signal 502 is driven low, the first transistor 512 is turned on. On the other hand, if the first enable power signal 502 is driven high, the first transistor 512 can be turned off. Similarly, if the second enable power signal 504 is driven low, the second transistor 514 is turned on. On the other hand, if the second enable power signal 504 is driven high, the second transistor 514 can be turned off. Although not shown in FIG. 5, the first enable power signal 502 may be forwarded (e.g., after the buffer 522) to another first transistor 512 (not shown) of another first block switch 212 to switch on multiple first block switches of a first bank of block switches. Analogously, the second enable power signal 504 may be forwarded to other second transistors 514 (not shown) .

Power management mode circuitry 506 is configured to implement power management commands, such as one or more commands for entering wake or sleep states for different circuit blocks. Power management mode circuitry 506 may receive separate or joint commands for the power states of the first circuit block 202 and the second circuit block 204. For example, separate first and second commands may respectively indicate that the first circuit block 202 is to enter a wake state and that the second circuit block 204 is to enter a sleep state. Alternatively, a single joint command may indicate that the first circuit block 202 is to enter a wake state and the second circuit block 204 is to enter a sleep state. Regardless, the power management mode circuitry 506 drives the first enable power signal 502 and the second enable power signal 504 to implement the indicated wake or sleep states.

To implement at least one command for a power management mode in which the first circuit block 202 is to enter a sleep state and the second circuit block 204 is to enter a sleep state, the power management mode circuitry 506 de- asserts the first enable power signal 502 and de-asserts the second enable power signal 504. For instance, the power management mode circuitry 506 can provide a high voltage (e.g., a logical one) to the first control input 532 and to the second control input 534 to turn off the first transistor 512 and the second transistor 514, respectively.

To implement at least one command for a power management mode in which the first circuit block 202 is to enter a wake state and the second circuit block 204 is to enter a sleep state, the power management mode circuitry 506 asserts the first enable power signal 502 and de-asserts the second enable power signal 504. For instance, the power management mode circuitry 506 can provide a low voltage (e.g., a logical zero) to the first control input 532 to turn on the first transistor 512 and a high voltage to the second control input 534 to turn off the second transistor 514.

To implement at least one command for a power management mode in which the first circuit block 202 is to enter a wake state and the second circuit block 204 is to enter a wake state, the power management mode circuitry 506 asserts the first enable power signal 502 and asserts the second enable power signal 504. For instance, the power management mode circuitry 506 can provide a low voltage to the first control input 532 and to the second control input 534 to turn on the first transistor 512 and the second transistor 514, respectively.

To implement at least one command for a power management mode in which the first circuit block 202 is to enter a sleep state and the second circuit block 204 is to enter a wake state, the power management mode circuitry 506 asserts the first enable power signal 502 and asserts the second enable power signal 504. For instance, the power management mode circuitry 506 can provide a low voltage to the second control input 534 to turn on the second transistor 514. Because the power domains are coupled in series, the power management mode circuitry 506 also provides a low voltage to the first control input 532 to turn on the first transistor 512 so that the first block switch 212 is producing the first-level voltage 122 at the first power node 132. In this power management mode, the first circuit block 202 does receive power, but the first circuit block 202 is in a sleep state and is not being used functionally. Some power may be saved, e.g., by gating a clock signal (not shown) to the first circuit block 202.

In some implementations, switching transistors that provide power are divided into the “few” and the “rest. ” The few transistors are turned on first in an orderly fashion to handle potential voltage droops and current losses. The rest of the transistors are then turned. To accommodate a “few” versus the “rest” scenario, each first block switch 212 may include two first transistors 512 that are respectively controlled by two first enable power signals 502, one for the “few” transistors and another for the “rest” of the transistors. Analogously, the contents and operation of each second block switch 214 may likewise be adapted to handle two or more different groups of circuitry.

FIG. 6 is a flow diagram illustrating an example process 600 for implementing a hierarchical power domain organization. Process 600 is described in the form of a set of blocks 602-612 that specify operations that may be performed. However, operations are not necessarily limited to the order shown in FIG. 6 or described herein, for the operations may be implemented in alternative orders or in fully or partially overlapping manners. Operations represented by the illustrated blocks of process 600 may be performed by an integrated circuit, such as an integrated circuit 106 of FIG. 1. An example general implementation of an integrated circuit is described below with reference to FIG. 7. Thus, the operations of process 600 may be performed by an integrated circuit, or a portion thereof, having a hierarchical power domain organization.

At block 602, power is provided to a second circuit block. For example, circuitry of an integrated circuit 106 may provide power to a second circuit block 204. To do so, operations of blocks 604-612 may be performed. At block 604, a first enable power signal is asserted. For example, power management mode circuitry 506 of the integrated circuit 106 may assert a first enable power signal 502. To do so, the first enable power signal 502 may be driven high or low such that a first transistor 512 coupled thereto is made active.

At block 606, multiple first block switches are switched on based on the asserting of the first enable power signal. For example, the power management mode circuitry 506 may switch on multiple first block switches 212-1 to 212-8 based on the assertion of the first enable power signal 502. A voltage level at a gate of a PMOS transistor, such as a first control input 532 of the first transistor 512, may be brought low to turn on the transistor.

At block 608, a second enable power signal is asserted. For example, the power management mode circuitry 506 of the integrated circuit 106 may assert a second enable power signal 504. To do so, the second enable power signal 504 may be driven high or low such that a second transistor 514 coupled thereto is made active.

At block 610, multiple second block switches are switched on based on the asserting of the second enable power signal. For example, the power management mode circuitry 506 may switch on multiple second block switches 214-1 to 214-8 based on the assertion of the second enable power signal 504. The integrated circuit 106 may route the second enable power signal 504 to multiple instances of the second buffer 524, which buffer provides the signal to the gate terminals of multiple instances of the second transistor 514 of the second block switch 214.

At block 612, power is routed to the second circuit block through the multiple first block switches and through the multiple second block switches. For example, circuitry of an integrated circuit 106 may route power to the second circuit block 204 through the multiple first block switches 212-1 to 212-8 and through the multiple second block switches 214-1 to 214-8. The power routing may be at least partially effectuated by, for instance, routing power from a power distribution node 130 to a first power node 132 via a first-level distribution path 302 and from the first power node 132 to a second power node 134 via a second-level distribution path 304.

FIG. 7 depicts an example electronic device that includes an integrated circuit (IC) 710 having multiple blocks. As shown, the electronic device 702 includes an antenna 704, a transceiver 706, and a user input/output (I/O) interface 708 in addition to the IC 710. Illustrated examples of an IC 710 include a microprocessor 712, a graphics processing unit (GPU) 714, a memory array 716, and a modem 718.

The electronic device 702 may be a mobile or battery-powered device or a fixed device that is designed to be powered by an electrical grid. Examples of an electronic device 702 include a server computer, a network switch or router, a blade of a data center, a personal computer, a desktop computer, a notebook computer, a tablet computer, a smart phone, an entertainment appliance, or a wearable computing device such as a smartwatch, intelligent glasses, or an article of clothing. An electronic device 702 may also be a device, or a portion thereof, having embedded electronics. Examples of an electronic device 702 with embedded electronics include a passenger vehicle, industrial equipment, a refrigerator or other home appliance, a drone or other unmanned aerial vehicle (UAV) , or a power tool.

For an electronic device with a wireless capability, the electronic device 702 includes an antenna 704 that is coupled to a transceiver 706 to enable reception or transmission of one or more wireless signals. The IC 710 may be coupled to the transceiver 706 to enable the IC 710 to have access to received wireless signals or to provide wireless signals for transmission via the antenna 704. The electronic device 702 as shown also includes at least one user I/O interface 708. Examples of an I/O interface 708 include a keyboard, a mouse, a microphone, a touch-sensitive screen, a camera, an accelerometer, a haptic mechanism, a speaker, a display screen, or a projector.

The IC 710 may comprise, for example, one or more instances of a microprocessor 712, a GPU 714, a memory array 716, a modem 718, and so forth. The microprocessor 712 may function as a central processing unit (CPU) or other general-purpose processor. Some microprocessors include different parts, such as multiple processing cores, that may be individually powered on or off. The GPU 714 may be especially adapted to process visual-related data for display. If visual-related data is not being rendered or otherwise processed, the GPU 714 may be powered down. The memory array 716 stores data for the microprocessor 712 or the GPU 714. Example types of memory for the memory array 716 include random access memory (RAM) , such as dynamic RAM (DRAM) or static RAM (SRAM) , flash memory, and so forth. If programs are not accessing data stored in memory, the memory array 716 may be powered down. The modem 718 modulates a signal to encode information into the signal or demodulates a signal to extract encoded information. If there is no information to encode or decode for outbound or inbound communications, the modem 718 may be idled to reduce power consumption. The IC 710 may include additional or alternative parts than those that are shown, such as an I/O interface, a sensor such as an accelerometer, a transceiver or another part of a receiver chain, a customized or hard-coded processor such as an application-specific integrated circuit (ASIC) , and so forth.

The IC 710 may also comprise a system on a chip (SOC) . An SOC may integrate a sufficient number or type of components to enable the SOC to provide computational functionality as a notebook, a mobile phone, or another electronic apparatus using one chip at least primarily. Components of an SOC, or an IC 710 generally, may be termed blocks or cores. Examples of cores or circuit blocks (e.g., a first circuit block 202 or a second circuit block 204 of FIG. 2) include a voltage regulator, a memory array, a memory controller, a general-purpose processor, a cryptographic processor, a modem, a vector processor, an interface or communication controller, a wireless controller, or a GPU. Any of these cores or circuit blocks, such as a processing or GPU circuit block, may further include multiple internal circuit blocks. A circuit block of an SOC may be powered down if not in use according to the techniques described in this document.

Unless context dictates otherwise, use herein of the word “or” may be considered use of an “inclusive or, ” or a term that permits inclusion or application of one or more items that are linked by the word “or” (e.g., a phrase “A or B” may be interpreted as permitting just “A, ” as permitting just “B, ” or as permitting both “A” and “B” ) . Although subject matter has been described in language specific to structural features or methodological operations, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or operations described above, including not necessarily being limited to the organizations in which features are arranged or the orders in which operations are performed.

Claims

An integrated circuit comprising:

a power distribution path configured to provide a distribution voltage；

a first circuit block；

a first block switch coupled to the first circuit block and to the power distribution path, the first block switch configured to switchably provide a first-level voltage to the first circuit block using the distribution voltage；

a second circuit block； and

a second block switch coupled to the second circuit block and to the first block switch, the second block switch configured to switchably provide a second-level voltage to the second circuit block using the first-level voltage.
The integrated circuit of claim 1, further comprising:

a first-level distribution path that couples the first block switch to the second block switch.
The integrated circuit of claim 2, wherein:

the integrated circuit further comprises multiple first block switches, including the first block switch；

the integrated circuit further comprises multiple second block switches, including the second block switch； and

the first-level distribution path comprises multiple parallel paths extending between the multiple first block switches and the multiple second block switches.
The integrated circuit of claim 2, wherein the first-level distribution path comprises at least a portion of a metal layer.
The integrated circuit of claim 1, wherein:

the integrated circuit further comprises multiple first block switches, including the first block switch, that are distributed along at least a portion of the first circuit block； and

the integrated circuit further comprises multiple second block switches, including the second block switch, that are distributed along at least a portion of the second circuit block.
The integrated circuit of claim 5, wherein:

the multiple first block switches comprise multiple first block header switches； and

the multiple second block switches comprise multiple second block header switches.
The integrated circuit of claim 1, wherein the second block switch is disposed on the integrated circuit at a location that is closer to the first circuit block than to the second circuit block.
The integrated circuit of claim 1, wherein:

the first block switch is configured to be switched on for a wake state of the first circuit block and to be switched off for a sleep state of the first circuit block； and

the second block switch is configured to be switched on for a wake state of the second circuit block and to be switched off for a sleep state of the second circuit block.
The integrated circuit of claim 8, wherein the integrated circuit is configured such that the second circuit block cannot receive power at an operational level from the power distribution path unless both the first block switch and the second block switch are switched on.
The integrated circuit of claim 8, wherein the integrated circuit is configured such that the second circuit block cannot be in the wake state unless at least the first block switch is switched on.
An integrated circuit comprising:

a power distribution path configured to provide a distribution voltage；

a first circuit block；

first switching means for providing power to the first circuit block, the first switching means configured to provide a first-level voltage to the first circuit block using the distribution voltage；

a second circuit block； and

second switching means for providing power to the second circuit block, the second switching means configured to provide a second-level voltage to the second circuit block using the first-level voltage.
The integrated circuit of claim 11, wherein the first switching means is further configured to provide the first-level voltage to the first circuit block responsive to assertion of a first enable power signal that corresponds to the first circuit block.
The integrated circuit of claim 12, wherein the second switching means is further configured to provide the second-level voltage to the second circuit block responsive to assertion of a second enable power signal that corresponds to the second circuit block.
The integrated circuit of claim 13, wherein the integrated circuit is configured such that the first enable power signal and the second enable power signal are both asserted to enable the second switching means to provide the second-level voltage to the second circuit block.
The integrated circuit of claim 11, wherein:

the first switching means includes a first transistor that is coupled between a power distribution node and a first power node, the first transistor having a first control input configured to receive a first enable power signal；

the power distribution path is configured to hold the power distribution node at the distribution voltage of the power distribution path； and

the first transistor is configured to hold the first power node at the first-level voltage based on the first enable power signal.
The integrated circuit of claim 15, wherein:

the second switching means includes a second transistor that is coupled between the first power node and a second power node, the second transistor having a second control input configured to receive a second enable power signal； and

the second transistor is configured to hold the second power node at the second-level voltage based on the second enable power signal.
The integrated circuit of claim 16, wherein the second transistor is further configured to hold the second power node at the second-level voltage based on the first enable power signal and the second enable power signal.
The integrated circuit of claim 17, wherein the second-level voltage comprises a voltage that is sufficient to enable circuitry of the second circuit block to operate.
The integrated circuit of claim 16, wherein:

the first circuit block is coupled to the first power node and configured to receive power at the first-level voltage via the first power node； and

the second circuit block is coupled to the second power node and configured to receive power at the second-level voltage via the second power node.
A method for implementing a hierarchical power domain organization in an integrated circuit, the method comprising:

providing power to a second circuit block by:

asserting a first enable power signal；

switching on multiple first block switches based on the asserting of the first enable power signal；

asserting a second enable power signal；

switching on multiple second block switches based on the asserting of the second enable power signal； and

routing power to the second circuit block through the multiple first block switches and through the multiple second block switches.
The method of claim 20, further comprising:

providing power to a first circuit block by:

asserting the first enable power signal；

switching on the multiple first block switches based on the asserting of the first enable power signal； and

routing power to the first circuit block through the multiple first block switches.
The method of claim 21, further comprising:

implementing at least one command for the first circuit block to enter a sleep state and for the second circuit block to enter a sleep state by:

de-asserting the first enable power signal； and

de-asserting the second enable power signal.
The method of claim 21, further comprising:

implementing at least one command for the first circuit block to enter a wake state and for the second circuit block to enter a sleep state by:

asserting the first enable power signal； and

de-asserting the second enable power signal.
The method of claim 21, further comprising:

implementing at least one command for the first circuit block to enter a wake state and for the second circuit block to enter a wake state by:

asserting the first enable power signal； and

asserting the second enable power signal.
The method of claim 21, further comprising:

implementing at least one command for the first circuit block to enter a sleep state and for the second circuit block to enter a wake state by:

asserting the first enable power signal； and

asserting the second enable power signal.
The method of claim 20, wherein the routing power comprises routing power to the second circuit block via at least one distribution path that includes multiple paths that are parallel to each other.
The method of claim 26, wherein:

the at least one distribution path comprises a first-level distribution path and a second-level distribution path； and

the routing power further comprises:

routing power to the second circuit block between the multiple first block switches and the multiple second block switches via the first-level distribution path； and

routing power to the second circuit block from the multiple second block switches via the second-level distribution path.
The method of claim 20, wherein the routing power comprises routing power from a power source to the multiple first block switches via a power distribution path.
An apparatus comprising:

a power distribution path configured to provide a distribution voltage；

multiple banks of block switches connected in series and coupled to the power distribution path； and

multiple power domains coupled to respective corresponding ones of the multiple banks of block switches in a hierarchical arrangement and configured to receive power from the multiple banks of block switches, the multiple power domains configured such that a relatively lower-level power domain is provided power by switching on a respective corresponding bank of block switches and at least one bank of block switches corresponding to at least one relatively higher-level power domain.
The apparatus of claim 29, wherein:

the at least one relatively higher-level power domain is disposed closer to the power distribution path than is the relatively lower-level power domain； and

the apparatus further comprises power management mode circuitry configured to selectively switch on or off the multiple banks of block switches to implement one or more commands for at least a portion of the multiple power domains to enter a sleep state or a wake state； the power management mode circuitry further configured, if the relatively lower-level power domain is commanded to enter the wake state, to switch on the respective corresponding bank of block switches and the at least one bank of block switches corresponding to the at least one relatively higher-level power domain independently of a state of the at least one relatively higher-level power domain.