WO2017090116A1 - Frequency detection circuit - Google Patents

Frequency detection circuit Download PDF

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Publication number
WO2017090116A1
WO2017090116A1 PCT/JP2015/083050 JP2015083050W WO2017090116A1 WO 2017090116 A1 WO2017090116 A1 WO 2017090116A1 JP 2015083050 W JP2015083050 W JP 2015083050W WO 2017090116 A1 WO2017090116 A1 WO 2017090116A1
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Prior art keywords
frequency
circuit
signal
local oscillation
detection circuit
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PCT/JP2015/083050
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French (fr)
Japanese (ja)
Inventor
田島　賢一
檜枝　護重
鈴木　拓也
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三菱電機株式会社
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Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to PCT/JP2015/083050 priority Critical patent/WO2017090116A1/en
Publication of WO2017090116A1 publication Critical patent/WO2017090116A1/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R23/00—Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
    • G01R23/02—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage
    • G01R23/14—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage by heterodyning; by beat-frequency comparison

Definitions

  • the present invention relates to a frequency detection circuit.
  • a frequency detection circuit that receives an input of an electrical signal and detects the frequency of the input signal has been developed (see, for example, Patent Document 1 and Non-Patent Document 1).
  • the frequency detection circuit is used in a radar device, a receiving device for television broadcasting or radio broadcasting, a communication device, a signal measuring device, and the like.
  • the frequency detection circuit of Patent Document 1 includes an A / D converter, a band pass filter, a Hilbert converter, a delay compensation register, a phase angle calculator, a memory, and a frequency calculator.
  • the A / D converter converts an analog signal input from the outside of the frequency detection circuit into a digital signal.
  • the digitized input signal passes through the bandpass filter and is input to the Hilbert transformer and the delay compensation register.
  • the Hilbert transformer performs a Hilbert transform on the input signal and outputs a signal having a phase difference of 90 degrees with respect to the input signal.
  • the delay compensation register time-shifts the input signal and outputs a signal in which the delay due to the Hilbert transform is compensated.
  • the phase angle calculator calculates the phase of the input signal by calculating an arc tangent between the output signal of the Hilbert transformer and the output signal of the delay compensation register.
  • the memory stores the phase calculated by the phase angle calculator.
  • the frequency calculator calculates the frequency of the input signal using the phase calculated by the phase angle calculator and the phase one sampling time before stored in the memory.
  • the frequency detection circuit of Non-Patent Document 1 performs frequency conversion using a local oscillation signal having a fixed frequency.
  • the frequency detection circuit of Non-Patent Document 1 generates an in-phase signal and a quadrature signal, and detects a frequency from the amplitude ratio of these signals.
  • the input signal of the frequency detection circuit includes thermal noise and noise due to a quantization error generated during conversion from an analog signal to a digital signal.
  • a desired frequency component to be detected hereinafter referred to as “desired frequency component”
  • an unnecessary frequency component due to noise hereinafter referred to as “unnecessary frequency component”
  • the unnecessary frequency component exists over a wide frequency band including the frequency to be detected. Due to the unnecessary frequency component, the frequency detected by the frequency detection circuit from the input signal is not the same value as the desired frequency component, and an error occurs.
  • the conventional frequency detection circuit has a problem that the frequency detection accuracy is lowered due to this error.
  • the frequency detection circuit disclosed in Patent Document 1 can suppress unnecessary frequency components by narrowing the passband width of the bandpass filter, thereby suppressing a decrease in detection accuracy.
  • the pass band width of the bandpass filter is narrowed, the detectable frequency range is narrowed, so that the frequency cannot be detected depending on the frequency of the input signal.
  • the passband width of the bandpass filter is widened, the frequency is detected in a state including unnecessary frequency components, so that the frequency detection accuracy decreases.
  • the present invention has been made to solve the above-described problems, and provides a frequency detection circuit capable of ensuring a detectable frequency range and preventing a reduction in detection accuracy due to noise.
  • the purpose is to do.
  • the frequency detection circuit of the present invention detects a frequency from an input signal, outputs a signal indicating the detected frequency, and within the passband of the filter circuit from the frequency indicated by the output signal of the first frequency detection circuit
  • a local oscillation signal generation circuit for generating a local oscillation signal for frequency conversion to a frequency of a frequency, a frequency conversion circuit for frequency-converting an input signal using the local oscillation signal, and outputting the frequency to a filter circuit, and an output signal of the filter circuit
  • the second frequency detection circuit that detects the frequency and outputs a signal indicating the detected frequency, the frequency indicated by the output signal of the first frequency detection circuit, and the frequency indicated by the output signal of the second frequency detection circuit, And a frequency calculation circuit for calculating the frequency of the input signal.
  • the frequency detection circuit of the present invention is configured as described above, a detectable frequency range can be secured, and a decrease in detection accuracy due to noise can be prevented.
  • FIG. 3A is an explanatory diagram showing the frequency spectrum of the input signal.
  • FIG. 3B is an explanatory diagram showing the frequency spectrum of the signal output from the filter circuit.
  • FIG. 3A is an explanatory diagram showing the frequency spectrum of the input signal.
  • FIG. 3B is an explanatory diagram showing the frequency spectrum of the signal output from the filter circuit.
  • It is a circuit block diagram which shows the principal part of the other local oscillation signal generation circuit which concerns on Embodiment 1 of this invention.
  • FIG. 7A is an explanatory diagram showing the frequency spectrum of the input signal.
  • FIG. 7B is an explanatory diagram showing the frequency spectrum of the signal output from the filter circuit.
  • FIG. 8A is an explanatory diagram showing the frequency spectrum of the input signal.
  • FIG. 8B is an explanatory diagram showing the frequency spectrum of the signal output from the filter circuit.
  • It is a circuit block diagram which shows the principal part of the other filter circuit which concerns on Embodiment 2 of this invention.
  • It is a circuit block diagram which shows the principal part of the frequency detection circuit which concerns on Embodiment 3 of this invention.
  • FIG. 1 is a circuit configuration diagram showing a main part of the frequency detection circuit 100 according to the first embodiment.
  • the frequency detection circuit 100 an input signal X in from the outside of the circuit are inputted.
  • the input signal Xin includes a desired frequency component that is a detection target of the frequency detection circuit 100 and an unnecessary frequency component caused by noise.
  • the first frequency detector circuit 1 receives an input signal X in, and detects the frequency from the input signal X in.
  • the first frequency detection circuit 1 outputs a signal indicating the detected frequency f 1 to the local oscillation signal generation circuit 2 and the second delay compensation circuit 7, respectively.
  • the local oscillation signal generation circuit 2 uses the frequency f 1 indicated by the output signal of the first frequency detection circuit 1 and a preset frequency f m to perform local conversion for frequency conversion from the frequency f 1 to the frequency f m .
  • the oscillation signal Xp is generated.
  • Frequency f m is set is set to a value within the passband Delta] f of the filter circuit 5, the center frequency equal to a value of e.g. passband Delta] f.
  • the local oscillation signal generation circuit 2 outputs the generated local oscillation signal Xp to the frequency conversion circuit 4.
  • First delay compensation circuit 3 receives an input signal X in, is to time shift the input signal X in.
  • the first delay compensation circuit 3 includes a plurality of delay lines having different electrical lengths and a switch for switching these delay lines, and the time shift is performed by switching the delay lines. Shift amount can be set.
  • the first delay compensation circuit 3 is realized by a circuit that temporarily holds a value in a memory or a latch. The shift amount of the time shift is set to a value corresponding to the delay time generated by the first frequency detection circuit 1 and the local oscillation signal generation circuit 2. That is, the first delay compensation circuit 3, the input signal X in, is to compensate for the delay by the first frequency detecting circuit 1 and the local oscillation signal generation circuit 2.
  • the first delay compensation circuit 3 outputs the time-shifted input signal Xin to the frequency conversion circuit 4.
  • Frequency conversion circuit 4 by using the local oscillation signal X p of the local oscillation signal generating circuit 2 has generated, an input signal X in the first delay compensation circuit 3 is shifted time is to frequency conversion.
  • the frequency conversion circuit 4 outputs the frequency-converted input signal Xin to the filter circuit 5.
  • the frequency conversion circuit 4 is configured by a mixer, and by performing multiplication of two input signals, the frequency conversion is performed by outputting the sum and difference of the input signals, or the frequency components of only the sum or the difference. Is what you do. That is, the output signal of the frequency conversion circuit 4, a frequency component of the frequency components and the local oscillation signal X p of the input signal X in is obtained by mixing by the mixer.
  • the filter circuit 5 is, for example, a bandpass filter (Band-Pass Filter, BPF), and the width of the passband ⁇ f and the value of the center frequency are fixed.
  • the filter circuit 5 is for suppressing band Delta] f out of the frequency component passing the output signals of the frequency conversion circuit 4, and outputs a signal X m including frequency components in the passband Delta] f.
  • the second frequency detector circuit 6 is for detecting the frequency from the output signal X m of the filter circuit 5.
  • the second frequency detection circuit 6 outputs a signal indicating the detected frequency f 2 to the frequency calculation circuit 8.
  • the second delay compensation circuit 7 shifts the output signal of the first frequency detection circuit 1 with time.
  • the second delay compensation circuit 7 is configured by a plurality of delay lines having different electrical lengths and a switch for switching these delay lines, and the time shift is performed by switching the delay lines. Shift amount can be set.
  • the second delay compensation circuit 7 is realized by a circuit that temporarily holds a value in a memory or a latch. The shift amount of the time shift is set to a value corresponding to the delay time generated by the local oscillation signal generation circuit 2, the frequency conversion circuit 4, the filter circuit 5, and the second frequency detection circuit 6.
  • the second delay compensation circuit 7 compensates for the delay caused by the local oscillation signal generation circuit 2, the frequency conversion circuit 4, the filter circuit 5, and the second frequency detection circuit 6 with respect to the output signal of the first frequency detection circuit 1. It is.
  • the second delay compensation circuit 7 outputs a time-shifted signal to the frequency calculation circuit 8.
  • a frequency detection circuit 100 is configured.
  • the entire frequency detection circuit 100 may be realized by one analog circuit or may be realized by a digital circuit. Further, each circuit constituting the frequency detection circuit 100 may be realized by an analog circuit or may be realized by a digital circuit.
  • the frequency detection circuit 100 may be realized by a dedicated processing circuit.
  • the processing circuit is, for example, an LSI (Large-Scale Integration) for digital signal processing such as FPGA (Field-Programmable Gate Array) or ASIC (Application Specific Integrated Circuit).
  • the entire frequency detection circuit 100 may be realized by a single processing circuit, or each circuit constituting the frequency detection circuit 100 may be realized by a processing circuit.
  • Phase integrated circuit 22 is for integrating the frequency f p of the arithmetic circuit 21 is calculated at a predetermined period.
  • the phase integrating circuit 22 is configured by an adding circuit that adds and outputs two inputs.
  • This adder circuit performs an accumulation operation by setting its own output as one of the inputs, and when the frequency is input, the output becomes a phase.
  • This adder circuit is a general circuit used in a direct digital synthesizer (Direct Digital Synthesizer) or the like.
  • the cumulative result of the phase accumulation circuit 22 that is configured to indicate a phase of the local oscillation signal X p.
  • the phase amplitude conversion circuit 23 converts the phase indicated by the integration result of the phase integration circuit 22 into an amplitude corresponding to this phase.
  • the conversion method examples include a method of holding an amplitude value in a memory or a lookup table (not shown), a method of calculating an amplitude value by calculation, and the like.
  • the digital / analog conversion circuit 24 converts the output signal of the phase / amplitude conversion circuit 23 from a digital signal to an analog signal. This analog signal becomes a local oscillation signal X p.
  • the phase integrating circuit 22, the phase / amplitude converting circuit 23, and the digital / analog converting circuit 24 constitute a CW (Continuous Wave) generating circuit 25.
  • the arithmetic circuit 21 and the CW generation circuit 25 constitute a local oscillation signal generation circuit 2.
  • FIGS. 3 (a) shows a frequency spectrum of the input signal X in inputted to the frequency detection circuit 100.
  • the input signal X in, a desired frequency component A is a detection target of the frequency detection circuit 100 includes a and the unnecessary frequency component B caused by noise.
  • Unnecessary frequency components B is present over a wide frequency band including the frequency f in the desired frequency components A.
  • the frequency f 1 of the first frequency detecting circuit 1 detects the input signal X in can not be the same value as the frequency f in the desired frequency components A.
  • the frequency f p of the local oscillation signal X p calculated by the arithmetic circuit 21 is expressed by the following formula (4) by substituting the formula (3) into the above formula (2).
  • FIG. 3 (b) shows the frequency spectrum of the signal X m filter circuit 5 has output.
  • Frequency conversion circuit 4 by outputting the frequency components of the sum or difference between the input signal X in the local oscillation signal X p by the mixer performs a frequency conversion of the input signal X in.
  • the frequency f m is set to a value within the passband Delta] f
  • the output signal X m of the filter circuit 5 unnecessary frequency components B Most except in the pass band ⁇ f is suppressed. Therefore, the frequency f 2 detected from the output signal X m by the second frequency detection circuit 6 is so small that the frequency error due to the unnecessary frequency component B can be ignored, and is expressed by the following equation (5).
  • f 2 f in + f p (5)
  • Frequency f x for the frequency calculation circuit 8 calculates, by substituting Equation (3) and (6) in the above equation (1) is expressed by the following equation (7).
  • the frequency f x of the frequency calculation circuit 8 calculates is the same as the frequency f in of the desired frequency component A included in the input signal X in. That is, the frequency detection circuit 100 can prevent the frequency detection accuracy from being reduced by noise.
  • the frequency detection circuit 100 performs frequency conversion of the input signal X in by the frequency conversion circuit 4 based on the detection result of the first frequency detection circuit 1 so that the desired frequency component A is included in the passband ⁇ f. Output to the filter circuit 5. Therefore, even when a BPF having a narrow passband ⁇ f width is used for the filter circuit 5, the frequency of the desired frequency component A can be reliably detected, and the frequency detection range can be ensured.
  • the local oscillation signal generation circuit 2 is not limited to the circuit configuration shown in FIG.
  • the digital-analog conversion circuit 24 shown in FIG. 2 is not necessary. In this case, the output signal of the phase amplitude conversion circuit 23 becomes the local oscillation signal X p.
  • FIG. 4 shows another example of the circuit configuration of the local oscillation signal generation circuit 2.
  • the variable frequency dividing circuit 32 divides the output signal of the oscillation circuit 36 by the frequency dividing number set by the frequency dividing number calculating circuit 31.
  • the reference signal circuit 33 generates and outputs a reference signal.
  • the phase comparison circuit 34 compares the phase of the output signal of the variable frequency dividing circuit 32 with the phase of the output signal of the reference signal circuit 33 and outputs a comparison result.
  • the loop filter circuit 35 suppresses high frequency components contained in the output signal of the phase comparison circuit 34 and generates a control signal for the oscillation circuit 36.
  • the oscillation circuit 36 generates a continuous signal having a frequency corresponding to the control signal input from the loop filter circuit 35. This continuous signal is a local oscillation signal X p.
  • the CW generation circuit 37 is configured by the frequency division number calculation circuit 31, the variable frequency division circuit 32, the reference signal circuit 33, the phase comparison circuit 34, the loop filter circuit 35, and the oscillation circuit 36.
  • the arithmetic circuit 21 and the CW generation circuit 37 constitute a local oscillation signal generation circuit 2.
  • one variable frequency dividing circuit 32 is provided in the CW generation circuit 37, but a plurality of similar variable frequency dividing circuits may be provided.
  • a filter circuit (not shown) to the input of the frequency detection circuit 100 is provided, may be one input signal X in which passes through the filter circuit is input to the first frequency detecting circuit 1 and the first delay compensation circuit 3 .
  • the filter circuit to prevent the detection range of the frequency detection circuit 100 is narrowed, it is preferable to use a filter having a sufficiently wide pass band including the frequency f in of the detection object.
  • the first frequency detection circuit 1 and the second frequency detection circuit 6 may be any circuit that can detect the frequency from the input signal, and may detect the frequency by any circuit configuration.
  • a circuit that detects a frequency by FFT Fast Fourier Transform
  • a circuit that detects a frequency by using a counter a circuit that detects a frequency by using a transversal filter including a Hilbert transform circuit, or a frequency that is detected by orthogonal demodulation Any circuit may be used.
  • the circuit for detecting the frequency by FFT is specifically a circuit for detecting the frequency from the position of the peak spectrum by Fourier-transforming the time waveform.
  • the circuit that detects the frequency using the counter is specifically a circuit that measures the time of a specific period and detects the frequency from the reciprocal of the measurement result.
  • the circuit that detects the frequency using the transversal filter generates a quadrature waveform that is 90 ° phase shifted from the input waveform by Hilbert transform, and calculates the phase from the amplitude ratio of the input waveform and the quadrature waveform.
  • the transversal filter is one of the circuits that realize the Hilbert transform.
  • the circuit that detects the frequency by quadrature demodulation generates two waveforms having a phase difference of 90 degrees by quadrature demodulation of the input waveform, calculates the phase from the amplitude ratio of these waveforms, It is a circuit that detects the frequency from the amount of change.
  • the first frequency detection circuit 1 and the second frequency detection circuit 6 may have the same or different circuit configurations.
  • the first frequency detection circuit 1 and the second frequency detection circuit 6 are circuits that detect a phase from an input signal and convert the phase into a frequency instead of a circuit that directly detects the frequency from the input signal. It may be.
  • a method for converting a phase into a frequency for example, as in the frequency detection circuit of Patent Document 1, there is a method for obtaining a frequency from a difference between a plurality of phases detected successively in time.
  • the frequency f m may be a value in the passband Delta] f, it is not limited to the center frequency equal to the values of the passband Delta] f. However, from the viewpoint of preventing the desired frequency component after frequency conversion from deviating from the pass band ⁇ f due to the frequency error f err , the frequency f m is set to a value equivalent to the center frequency of the pass band ⁇ f or a value near this. Is preferred.
  • the frequency detecting circuit 100 of the first embodiment detects the frequency of the input signal X in, the first frequency detecting circuit 1 outputs a signal indicating the frequency f 1 detected, the first frequency detecting circuit a local oscillation signal generation circuit 2 for generating a local oscillation signal X p for frequency conversion from the frequency f 1 of the first output signal indicates to the frequency f m in the pass band ⁇ f of the filter circuit 5, the local oscillation signal X p used to frequency-convert the input signal X in it, the frequency conversion circuit 4 to be output to the filter circuit 5, detects a frequency from the output signal of the filter circuit 5, the second frequency detection for outputting a signal indicating the frequency f 2 detected calculating a circuit 6, the frequency f 1 of the output signal of the first frequency detecting circuit 1 is shown, using a frequency f 2 where the output signal of the second frequency detection circuit 6 indicates, the frequency f x of the input signal X in Comprising a wave number calculation circuit 8, a.
  • FIG. FIG. 5 is a circuit configuration diagram showing a main part of the frequency detection circuit 100a according to the second embodiment. Referring to FIG. 5, described frequency detection circuit 100a to the center frequency of the pass band ⁇ f and the variable frequency f m and the filter circuit 11. In FIG. 5, a circuit similar to the frequency detection circuit 100 of the first embodiment shown in FIG.
  • the first frequency detection circuit 1 outputs a signal indicating the frequency f 1 detected from the input signal X in to the coefficient calculation circuit 9, the local oscillation signal generation circuit 2, the center frequency control circuit 10, and the second delay compensation circuit 7, respectively. To do.
  • Coefficient calculating circuit 9, according to the frequency f 1 of the output signal of the first frequency detecting circuit 1 is shown, it is to set the frequency f m.
  • the coefficient calculation circuit 9, the reference frequency f th is preset to be compared with the frequency f 1.
  • the coefficient calculation circuit 9 is preset with a reference level that is a comparison target with the level of each frequency component.
  • the reference level is set to a half value with respect to the predicted value of the level of the desired frequency component.
  • Coefficient calculating circuit 9 sets the frequency f m to a value higher than a reference level of the frequency component is only desired frequency components in the passband ⁇ f of the filter circuit 11 in the output signal of the frequency conversion circuit 4.
  • the frequency detection circuit 100a is configured by a processing circuit such as an LSI
  • a frequency that is half the sampling frequency of the digital signal processed by the processing circuit is referred to as a “Nyquist frequency”.
  • Coefficient calculating circuit 9, of the above conditions are satisfied frequency, sets the frequency f m with the following values Nyquist frequency.
  • the coefficient calculation circuit 9 is realized by, for example, a digital circuit that compares an input value with a value stored internally and calculates a coefficient for obtaining a predetermined frequency.
  • Coefficient calculating circuit 9 outputs a signal indicating a frequency f m which is set to the local oscillation signal generation circuit 2.
  • Local oscillation signal generating circuit 2 a frequency f 1 to the output signal of the first frequency detecting circuit 1 is shown, to generate a local oscillation signal X p by using the frequency f m indicated by the output signal of the coefficient calculation circuit 9. That is, the coefficient calculation circuit 9, by setting the frequency f m, and controls the frequency f p of the local oscillation signal X p.
  • the coefficient calculation circuit 9 outputs a signal indicating a frequency f m which is set to the center frequency control circuit 10.
  • Center frequency control circuit 10 according to the frequency f m indicated by the output signal of the coefficient calculation circuit 9, and generates a control signal D f to bring the center frequency of the pass band ⁇ f of the filter circuit 11 to a frequency f m.
  • Center frequency control circuit 10 as an address value representing the f m, may be those having a memory that holds the control signal D f, it may be one constituted by a circuit for calculating a control signal D f from the value representing the f m .
  • the center frequency control circuit 10 outputs the generated control signal Df to the filter circuit 11.
  • the filter circuit 11 is, for example, a BPF, and the center frequency of the pass band ⁇ f is variable.
  • the center frequency of the pass band ⁇ f is controlled by the control signal D f output from the center frequency control circuit 10.
  • the filter circuit 11 is for suppressing the band ⁇ f frequency component outside passage of the output signal of the frequency conversion circuit 4, and outputs a signal X m including frequency components in the pass band ⁇ f to the second frequency detection circuit 6 .
  • the shift amount of the time shift is set to a value corresponding to the delay time generated by the first frequency detection circuit 1, the coefficient calculation circuit 9 and the local oscillation signal generation circuit 2. That is, the first delay compensation circuit 3 compensates for the delay caused by the first frequency detection circuit 1, the coefficient calculation circuit 9, and the local oscillation signal generation circuit 2 with respect to the input signal X in and outputs it to the frequency conversion circuit 4. is there.
  • the shift amount of the time shift is generated by the coefficient calculation circuit 9, the local oscillation signal generation circuit 2, the frequency conversion circuit 4, the center frequency control circuit 10, the filter circuit 11, and the second frequency detection circuit 6.
  • the value is set according to the delay time. That is, the second delay compensation circuit 7 performs the coefficient calculation circuit 9, the local oscillation signal generation circuit 2, the frequency conversion circuit 4, the center frequency control circuit 10, the filter circuit 11, and the filter circuit 11 with respect to the output signal of the first frequency detection circuit 1.
  • the delay by the two-frequency detection circuit 6 is compensated and output to the frequency calculation circuit 8.
  • First frequency detection circuit 1 coefficient calculation circuit 9, local oscillation signal generation circuit 2, first delay compensation circuit 3, frequency conversion circuit 4, center frequency control circuit 10, filter circuit 11, second frequency detection circuit 6, second
  • the delay compensation circuit 7 and the frequency calculation circuit 8 constitute a frequency detection circuit 100a.
  • the output signal of the frequency conversion circuit 4 is input to the first fixed filter circuit 41 and the second fixed filter circuit 42, respectively.
  • Each of the first fixed filter circuit 41 and the second fixed filter circuit 42 is a BPF in which the center frequency of the passband ⁇ f is fixed, and the respective center frequencies are set to different values.
  • the signal that has passed through the first fixed filter circuit 41 and the second fixed filter circuit 42 is input to the switch circuit 43.
  • the switch circuit 43 selectively outputs either the signal that has passed through the first fixed filter circuit 41 or the signal that has passed through the second fixed filter circuit 42 to the second frequency detection circuit 6.
  • Signal switching circuit 43 outputs is controlled by the control signal D f that is input from the central frequency control circuit 10. That is, the control signal D f in this case is of the first fixed filter circuit 41 and the second fixed filter circuit 42, a signal X m to the center frequency of the pass band ⁇ f is passed through the BPF closer the frequency f m the
  • the switch circuit 43 is controlled so as to be output to the two-frequency detection circuit 6.
  • the first fixed filter circuit 41, the second fixed filter circuit 42, and the switch circuit 43 constitute the filter circuit 11.
  • FIGS. 7 (a) shows a frequency spectrum of the input signal X in inputted to the frequency detection circuit 100a.
  • the input signal X in are included and the unnecessary frequency component B desired frequency component A.
  • the frequency f in of the desired frequency component A is lower than the reference frequency f th .
  • the frequency f 1 detected by the first frequency detection circuit 1 from the input signal X in is also lower than the reference frequency f th .
  • the coefficient calculation circuit 9 has a value higher than the reference frequency fth , and in the output signal of the frequency conversion circuit 4, the frequency component equal to or higher than the reference level is only the desired frequency component A in the pass band ⁇ f of the filter circuit 11. setting the frequency f m to the value.
  • the frequency f 2 detected by the second frequency detection circuit 6 from the output signal X m of the filter circuit 11 is higher than the reference frequency f th .
  • the desired frequency component A can be reliably detected.
  • FIG. 8 (a) shows the frequency spectrum of the input signal X in inputted to the frequency detection circuit 100a.
  • the input signal X in are included and the unnecessary frequency component B desired frequency component A.
  • the frequency f in of the desired frequency component A is higher than the reference frequency f th .
  • the frequency f 1 detected by the first frequency detection circuit 1 from the input signal X in is also higher than the reference frequency f th .
  • the coefficient calculation circuit 9 has a value lower than the reference frequency fth , and in the output signal of the frequency conversion circuit 4, the frequency component equal to or higher than the reference level is only the desired frequency component A in the pass band ⁇ f of the filter circuit 11. setting the frequency f m to the value.
  • the frequency f 2 detected by the second frequency detection circuit 6 from the output signal X m of the filter circuit 5 becomes a value lower than the reference frequency f th .
  • the desired frequency component A can be reliably detected.
  • the filter circuit 11 may be a BPF whose center frequency of the pass band ⁇ f is variable, and is not limited to the circuit configuration shown in FIG.
  • the number of fixed filter circuits may be any number of two or more. By increasing the number of fixed filter circuits, the center frequency of the filter circuit 11 can be controlled more precisely.
  • the switch circuit 43 is disposed at the output of the fixed filter circuit. However, the switch circuit 43 may be disposed at the input of the fixed filter circuit, or the switch circuit may be disposed at both the input and output. good.
  • FIG. 9 shows another example of the circuit configuration of the filter circuit 11.
  • the output signal of the frequency conversion circuit 4 is input to the variable filter circuit 44.
  • the variable filter circuit 44 is a BPF in which the center frequency of the pass band ⁇ f is variable.
  • Filter control circuit 45 uses the control signal D f that is input from the central frequency control circuit 10, and controls the center frequency of the variable filter circuit 44.
  • the variable filter circuit 44 may be controlled by an analog value such as a voltage value or a current value, or may be controlled by a digital value.
  • the variable filter circuit 44 and the filter control circuit 45 constitute the filter circuit 11.
  • the filter circuit 11 includes a plurality of variable filter circuits similar to the variable filter circuit 44 illustrated in FIG. 9, and a switch circuit similar to the switch circuit 43 illustrated in FIG. 6 is disposed at the output of the variable filter circuit. It may be a thing. For example, the variable range of the center frequency of the entire filter circuit 11 can be widened by using BPFs having different variable ranges of the center frequency for each variable filter circuit.
  • Equation (1) if the frequency calculating circuit 8 uses a frequency f m in the calculation of the frequency f x, the frequency f m of the coefficient calculation circuit 9 is set to the frequency computing circuit 8 It is good also as a structure to notify.
  • the frequency detection circuit 100 a controls the frequency f p of the local oscillation signal X p generated by the local oscillation signal generation circuit 2 using the output signal of the first frequency detection circuit 1.
  • a coefficient calculation circuit 9 and a center frequency control circuit 10 that controls the center frequency of the pass band ⁇ f of the filter circuit 11 using the output signal of the coefficient calculation circuit 9 are provided.
  • FIG. 10 is a circuit configuration diagram showing a main part of the frequency detection circuit 100b according to the third embodiment.
  • a frequency detection circuit 100b provided with a second frequency detection circuit 12 having a frequency conversion function instead of the frequency conversion circuit 4, the filter circuit 5 and the second frequency detection circuit 6 shown in FIG. To do.
  • the same reference numerals are given to the same circuits as those of the frequency detection circuit 100 according to the first embodiment shown in FIG.
  • Local oscillation signal generating circuit 2 is for generating a local oscillation signal X p for frequency conversion from the frequency f 1 to frequency f m.
  • Frequency f m is set to the center frequency equal to the values of the first set to a value within the passband Delta] f of the filter circuit 54 and the second filter circuit 55 is, for example, passband Delta] f.
  • Local oscillation signal generating circuit 2 and outputs the generated local oscillation signal X p in 90-degree phase shifting circuit 51.
  • 90 degree phase shifting circuit 51 is the same frequency as the local oscillation signal X p, and is for generating a first local oscillation signal and the second local oscillation signal having a phase difference of 90 degrees from each other.
  • the 90-degree phase shift circuit 51 outputs the generated first local oscillation signal to the first frequency conversion circuit 52 and outputs the second local oscillation signal to the second frequency conversion circuit 53.
  • the shift amount of the time shift is set to a value corresponding to the delay time generated by the first frequency detection circuit 1, the local oscillation signal generation circuit 2, and the 90 ° phase shift circuit 51. That is, the first delay compensation circuit 3, the input signal X in, is to compensate for the delay by the first frequency detecting circuit 1, the local oscillation signal generating circuit 2 and the 90-degree phase shifting circuit 51.
  • the first delay compensation circuit 3 outputs the time-shifted input signal Xin to the first frequency conversion circuit 52 and the second frequency conversion circuit 53.
  • the first frequency conversion circuit 52 is configured by a mixer similar to the frequency conversion circuit 4 shown in FIG. 1, and uses the first local oscillation signal output from the 90-degree phase shift circuit 51 to generate the first delay compensation circuit 3. There is for frequency converting an input signal X in shifted time.
  • the first frequency conversion circuit 52 outputs the frequency-converted input signal Xin to the first filter circuit 54. That is, the output signal of the first frequency converting circuit 52, a frequency component of the frequency component and the first local oscillation signal of the input signal X in is obtained by mixing by the mixer.
  • the second frequency conversion circuit 53 is configured by a mixer similar to the frequency conversion circuit 4 shown in FIG. 1, and uses the second local oscillation signal output from the 90-degree phase shift circuit 51, and uses the first delay compensation circuit 3. There is for frequency converting an input signal X in shifted time.
  • the second frequency conversion circuit 53 outputs the frequency-converted input signal Xin to the second filter circuit 55. That is, the output signal of the second frequency converting circuit 53, a frequency component of the frequency component and the second local oscillation signal of the input signal X in is obtained by mixing by the mixer.
  • the first filter circuit 54 is a BPF similar to the filter circuit 5 shown in FIG. 1, and the width of the passband ⁇ f and the value of the center frequency are fixed.
  • the first filter circuit 54 suppresses a frequency component outside the pass band ⁇ f in the output signal of the first frequency conversion circuit 52 and outputs a signal including the frequency component within the pass band ⁇ f to the phase calculation circuit 56. .
  • the second filter circuit 55 is a BPF similar to the filter circuit 5 shown in FIG. 1, and the width of the passband ⁇ f and the value of the center frequency are fixed.
  • the second filter circuit 55 suppresses frequency components outside the pass band ⁇ f in the output signal of the second frequency conversion circuit 53 and outputs a signal including the frequency components within the pass band ⁇ f to the phase calculation circuit 56. .
  • the phase calculation circuit 56 uses the output signal of the first filter circuit 54 and the output signal of the second filter circuit 55 to input the input signal X in that has been frequency converted by the first frequency conversion circuit 52 and the second frequency conversion circuit 53. Is calculated.
  • the phase calculation circuit 56 outputs a signal indicating the calculated phase to the phase frequency conversion circuit 57.
  • the phase frequency conversion circuit 57 converts the phase indicated by the output signal of the phase calculation circuit 56 into a frequency.
  • the phase frequency conversion circuit 57 outputs a signal indicating the converted frequency f 2 to the frequency calculation circuit 8.
  • the second frequency detection circuit includes a 90-degree phase shift circuit 51, a first frequency conversion circuit 52, a second frequency conversion circuit 53, a first filter circuit 54, a second filter circuit 55, a phase calculation circuit 56, and a phase frequency conversion circuit 57. 12 is configured.
  • the shift amount of the time shift is set to a value corresponding to the delay time generated by the local oscillation signal generation circuit 2 and the second frequency detection circuit 12. That is, the second delay compensation circuit 7 compensates for the delay caused by the local oscillation signal generation circuit 2 and the second frequency detection circuit 12 with respect to the output signal of the first frequency detection circuit 1 and outputs it to the frequency calculation circuit 8. is there.
  • the first frequency detection circuit 1, the local oscillation signal generation circuit 2, the first delay compensation circuit 3, the second frequency detection circuit 12, the second delay compensation circuit 7, and the frequency calculation circuit 8 constitute a frequency detection circuit 100b. .
  • Frequency detection circuit 100b similarly to the frequency detecting circuit 100 of the first embodiment, the frequency f x for calculating the frequency computing circuit 8 becomes equal to the frequency f in. That is, the frequency detection circuit 100b can prevent the frequency detection accuracy from being lowered due to noise.
  • the frequency detection circuit 100b is input by the first frequency conversion circuit 52 and the second frequency conversion circuit 53 so that the desired frequency component A is included in the passband ⁇ f based on the detection result of the first frequency detection circuit 1.
  • the signal X in is frequency converted and then output to the first filter circuit 54 and the second filter circuit 55, respectively. Therefore, even when a BPF having a narrow passband ⁇ f width is used for the first filter circuit 54 and the second filter circuit 55, the frequency of the desired frequency component A can be reliably detected, and the frequency is the same as in the first embodiment. Can be ensured.
  • the frequency detection circuit 100 shown in FIG. 1 the frequency conversion circuit 4, the filter circuit 5, and the second frequency detection circuit 6 are each constituted by three independent circuits.
  • the frequency detection circuit 100b shown in FIG. 10 includes the second frequency detection circuit 12 such as the frequency conversion circuit 4 and the filter circuit 5 shown in FIG. Separate frequency conversion circuits and filter circuits are unnecessary. As a result, the number of circuits constituting the frequency detection circuit 100b can be reduced, the entire frequency detection circuit 100b can be reduced in size, the cost can be reduced, and the power consumption can be reduced.
  • the frequency detecting circuit 100b of the third embodiment detects the frequency of the input signal X in, the first frequency detecting circuit 1 outputs a signal indicating the frequency f 1 detected, the first frequency detecting circuit local oscillation signal generating circuit 2 for generating a local oscillation signal X p for frequency conversion from the frequency f 1 of the first output signal indicates to the frequency f m in the pass band ⁇ f of the first filter circuit 54 and the second filter circuit 55
  • the local oscillation signal X 90 degree phase shift circuit 51 for generating a first local oscillation signal and the second local oscillation signal having a phase difference of 90 degrees from each other from p
  • the input signal X in by using a first local oscillation signal
  • the first frequency converting circuit 52 that converts the frequency of the input signal X in using the second local oscillation signal and the second frequency that is output to the second filter circuit 55 Using the conversion circuit 53, the output signal of the first filter circuit 54 and the output signal of the second filter circuit 55, a phase calculation circuit 56 for calculating the phase
  • the second frequency detection circuit 12 has a frequency conversion function, the frequency conversion circuit and the filter circuit that are separate from the second frequency detection circuit 12 are not required, and the entire frequency detection circuit 100b can be reduced in size, cost, and cost. Power consumption can be reduced.
  • FIG. 11 is a circuit configuration diagram showing a main part of the frequency detection circuit 100c according to the fourth embodiment.
  • a frequency detection circuit 100c provided with a second frequency detection circuit 13 having a frequency conversion function in place of the frequency conversion circuit 4, the filter circuit 11, and the second frequency detection circuit 6 shown in FIG. To do.
  • Local oscillation signal generating circuit 2 is for generating a local oscillation signal X p using the frequency f 1 indicated by the output signal of the first frequency detecting circuit 1, a frequency f m indicated by the output signal of the coefficient calculation circuit 9 is there. Local oscillation signal generating circuit 2, and outputs the generated local oscillation signal X p in 90-degree phase shifting circuit 51.
  • 90 degree phase shifting circuit 51 is the same frequency as the local oscillation signal X p, and is for generating a first local oscillation signal and the second local oscillation signal having a phase difference of 90 degrees from each other.
  • the 90-degree phase shift circuit 51 outputs the generated first local oscillation signal to the first frequency conversion circuit 52 and outputs the second local oscillation signal to the second frequency conversion circuit 53.
  • the shift amount of the time shift is set to a value corresponding to the delay time generated by the first frequency detection circuit 1, the coefficient calculation circuit 9, the local oscillation signal generation circuit 2, and the 90-degree phase shift circuit 51.
  • the first delay compensation circuit 3 the input signal X in the first frequency detecting circuit 1, the coefficient calculation circuit 9, to compensate for the delay by the local oscillation signal generating circuit 2 and the 90-degree phase shifting circuit 51 first This is output to the frequency conversion circuit 52 and the second frequency conversion circuit 53.
  • the first frequency conversion circuit 52 is configured by a mixer similar to the frequency conversion circuit 4 shown in FIG. 5, and uses the first local oscillation signal output from the 90-degree phase shift circuit 51, and uses the first delay compensation circuit 3.
  • the frequency of the time-shifted input signal Xin is converted and output to the first filter circuit 61.
  • the second frequency conversion circuit 53 is configured by a mixer similar to the frequency conversion circuit 4 shown in FIG. 5, and uses the second local oscillation signal output from the 90-degree phase shift circuit 51 to generate the first delay compensation circuit 3.
  • the frequency of the time-shifted input signal Xin is converted and output to the second filter circuit 62.
  • the first filter circuit 61 is a BPF similar to the filter circuit 11 shown in FIG. 5, and the center frequency of the pass band ⁇ f is variable.
  • the center frequency of the pass band ⁇ f is controlled by the control signal D f output from the center frequency control circuit 10.
  • the first filter circuit 61 suppresses frequency components outside the pass band ⁇ f in the output signal of the first frequency conversion circuit 52 and outputs a signal including the frequency components within the pass band ⁇ f to the phase calculation circuit 56. .
  • the second filter circuit 62 is a BPF similar to the filter circuit 11 shown in FIG. 5, and the center frequency of the pass band ⁇ f is variable.
  • the center frequency of the pass band ⁇ f is controlled by the control signal D f output from the center frequency control circuit 10.
  • the second filter circuit 62 suppresses the frequency component outside the pass band ⁇ f in the output signal of the second frequency conversion circuit 53 and outputs a signal including the frequency component within the pass band ⁇ f to the phase calculation circuit 56. .
  • the phase calculation circuit 56 uses the output signal of the first filter circuit 54 and the output signal of the second filter circuit 55 to input the input signal X in that has been frequency converted by the first frequency conversion circuit 52 and the second frequency conversion circuit 53. Is calculated.
  • the phase calculation circuit 56 outputs a signal indicating the calculated phase to the phase frequency conversion circuit 57.
  • the phase frequency conversion circuit 57 converts the phase indicated by the output signal of the phase calculation circuit 56 into a frequency.
  • the phase frequency conversion circuit 57 outputs a signal indicating the converted frequency f 2 to the frequency calculation circuit 8.
  • the second frequency detection circuit includes a 90-degree phase shift circuit 51, a first frequency conversion circuit 52, a second frequency conversion circuit 53, a first filter circuit 61, a second filter circuit 62, a phase calculation circuit 56, and a phase frequency conversion circuit 57. 13 is configured.
  • the shift amount of the time shift is set to a value corresponding to the delay time generated by the coefficient calculation circuit 9, the local oscillation signal generation circuit 2, the center frequency control circuit 10 and the second frequency detection circuit 13. ing. That is, the second delay compensation circuit 7 compensates for delays caused by the coefficient calculation circuit 9, the local oscillation signal generation circuit 2, the center frequency control circuit 10, and the second frequency detection circuit 13 with respect to the output signal of the first frequency detection circuit 1. And output to the frequency calculation circuit 8.
  • the first frequency detection circuit 1, the local oscillation signal generation circuit 2, the first delay compensation circuit 3, the second frequency detection circuit 13, the second delay compensation circuit 7, and the frequency calculation circuit 8 constitute a frequency detection circuit 100c. .
  • Frequency detection circuit 100c by setting the frequency f m in the same suitable value in the second embodiment, similarly to the frequency detecting circuit 100b of the third embodiment, that the detection accuracy of the frequency is lowered by noise Can be prevented. In addition, a frequency detection range can be ensured.
  • the frequency conversion circuit 4, the filter circuit 11, and the second frequency detection circuit 6 are each constituted by three independent circuits.
  • the frequency detection circuit 100c shown in FIG. 11 is different from the second frequency detection circuit 13 such as the frequency conversion circuit 4 and the filter circuit 11 shown in FIG. Separate frequency conversion circuits and filter circuits are unnecessary.
  • the number of circuits constituting the frequency detection circuit 100c can be reduced, the entire frequency detection circuit 100c can be reduced in size, the cost can be reduced, and the power consumption can be reduced.
  • the frequency detection circuit 100c of the fourth embodiment by using the first output signal of the frequency detection circuit 1, the local oscillation signal generating circuit 2 controls the frequency f p of the local oscillation signal X p is generated
  • a coefficient calculation circuit 9 and a center frequency control circuit 10 that controls the center frequency of the pass band ⁇ f of the first filter circuit 61 and the second filter circuit 62 using the output signal of the coefficient calculation circuit 9 are provided.
  • the second frequency detection circuit 13 has a frequency conversion function, a frequency conversion circuit and a filter circuit that are separate from the second frequency detection circuit 13 are not required, and the entire frequency detection circuit 100c can be reduced in size, cost, and cost. Power consumption can be reduced.
  • the frequency detection circuit of the present invention can be used in a radar device, a receiving device for television broadcasting or radio broadcasting, a communication device, a signal measuring device, and the like.

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Abstract

A frequency detection circuit (100) is provided with: a first frequency detection circuit (1) that detects the frequency from an input signal, and outputs a signal indicating the detected frequency; a local oscillation signal generation circuit (2) that generates a local oscillation signal for frequency conversion into a frequency in a pass band of a filter circuit (5) from the frequency indicated by the output signal of the first frequency detection circuit (1); a frequency conversion circuit (4) that converts the frequency of the input signal by using the local oscillation signal to output the frequency to the filter circuit (5); a second frequency detection circuit (6) that detects the frequency from an output signal of the filter circuit (5), and outputs a signal indicating the detected frequency; and a frequency calculation circuit 8 that calculates the frequency of the input signal.

Description

周波数検出回路Frequency detection circuit
　本発明は、周波数検出回路に関する。 The present invention relates to a frequency detection circuit.
　従来、電気信号の入力を受け付けて、この入力信号の周波数を検出する周波数検出回路が開発されている（例えば、特許文献１及び非特許文献１参照。）。周波数検出回路は、レーダ装置、テレビ放送又はラジオ放送用の受信装置、通信機器及び信号計測装置などに用いられている。 Conventionally, a frequency detection circuit that receives an input of an electrical signal and detects the frequency of the input signal has been developed (see, for example, Patent Document 1 and Non-Patent Document 1). The frequency detection circuit is used in a radar device, a receiving device for television broadcasting or radio broadcasting, a communication device, a signal measuring device, and the like.
　特許文献１の周波数検出回路は、Ａ／Ｄ変換器、バンドパスフィルタ、ヒルベルト変換器、遅延補償用レジスタ、位相角演算器、メモリ及び周波数演算器を有している。Ａ／Ｄ変換器は、周波数検出回路の外部から入力されたアナログ信号をデジタル信号に変換する。デジタル化された入力信号は、バンドパスフィルタを通過してヒルベルト変換器及び遅延補償用レジスタにそれぞれ入力される。ヒルベルト変換器は、入力信号をヒルベルト変換し、入力信号に対して９０度の位相差を有する信号を出力する。遅延補償用レジスタは、入力信号を時間シフトし、ヒルベルト変換による遅延を補償した信号を出力する。位相角演算器は、ヒルベルト変換器の出力信号と遅延補償用レジスタの出力信号との逆正接演算により、入力信号の位相を算出する。メモリは、位相角演算器が算出した位相を格納する。周波数演算器は、位相角演算器が算出した位相と、メモリに格納された１サンプリング時間前の位相とを用いて、入力信号の周波数を算出する。 The frequency detection circuit of Patent Document 1 includes an A / D converter, a band pass filter, a Hilbert converter, a delay compensation register, a phase angle calculator, a memory, and a frequency calculator. The A / D converter converts an analog signal input from the outside of the frequency detection circuit into a digital signal. The digitized input signal passes through the bandpass filter and is input to the Hilbert transformer and the delay compensation register. The Hilbert transformer performs a Hilbert transform on the input signal and outputs a signal having a phase difference of 90 degrees with respect to the input signal. The delay compensation register time-shifts the input signal and outputs a signal in which the delay due to the Hilbert transform is compensated. The phase angle calculator calculates the phase of the input signal by calculating an arc tangent between the output signal of the Hilbert transformer and the output signal of the delay compensation register. The memory stores the phase calculated by the phase angle calculator. The frequency calculator calculates the frequency of the input signal using the phase calculated by the phase angle calculator and the phase one sampling time before stored in the memory.
　非特許文献１の周波数検出回路は、固定周波数の局部発振信号により周波数変換を行うものである。非特許文献１の周波数検出回路は、同相信号と直交信号を生成し、これらの信号の振幅比から周波数を検出する。 The frequency detection circuit of Non-Patent Document 1 performs frequency conversion using a local oscillation signal having a fixed frequency. The frequency detection circuit of Non-Patent Document 1 generates an in-phase signal and a quadrature signal, and detects a frequency from the amplitude ratio of these signals.
特開２００５－９１２５５号公報JP 2005-91255 A
　一般に、周波数検出回路の入力信号には、熱雑音及びアナログ信号からデジタル信号への変換時に生じた量子化誤差などによる雑音が含まれている。このため、周波数検出回路の入力信号には、検出対象である所望の周波数成分（以下「所望周波数成分」という。）に加えて、これらの雑音による不要な周波数成分（以下「不要周波数成分」という。）が含まれている。不要周波数成分は、検出対象の周波数を含む広い周波数帯域に亘って存在する。不要周波数成分により、周波数検出回路が入力信号から検出する周波数は所望周波数成分と同じ値にならず、誤差が生じる。従来の周波数検出回路は、この誤差により周波数の検出精度が低下する問題があった。 Generally, the input signal of the frequency detection circuit includes thermal noise and noise due to a quantization error generated during conversion from an analog signal to a digital signal. For this reason, in addition to a desired frequency component to be detected (hereinafter referred to as “desired frequency component”), an unnecessary frequency component due to noise (hereinafter referred to as “unnecessary frequency component”) is included in the input signal of the frequency detection circuit. .)It is included. The unnecessary frequency component exists over a wide frequency band including the frequency to be detected. Due to the unnecessary frequency component, the frequency detected by the frequency detection circuit from the input signal is not the same value as the desired frequency component, and an error occurs. The conventional frequency detection circuit has a problem that the frequency detection accuracy is lowered due to this error.
　特許文献１の周波数検出回路は、バンドパスフィルタの通過帯域幅を狭くすることで、不要周波数成分を抑制して検出精度の低下を抑えることができる。しかしながら、バンドパスフィルタの通過帯域幅を狭くすると検出可能な周波数範囲が狭くなるため、入力信号の周波数によっては周波数を検出できなくなる。他方、バンドパスフィルタの通過帯域幅を広くすると、不要周波数成分を含む状態で周波数を検出するため、周波数の検出精度が低下する。 The frequency detection circuit disclosed in Patent Document 1 can suppress unnecessary frequency components by narrowing the passband width of the bandpass filter, thereby suppressing a decrease in detection accuracy. However, if the pass band width of the bandpass filter is narrowed, the detectable frequency range is narrowed, so that the frequency cannot be detected depending on the frequency of the input signal. On the other hand, if the passband width of the bandpass filter is widened, the frequency is detected in a state including unnecessary frequency components, so that the frequency detection accuracy decreases.
　本発明は、上記のような課題を解決するためになされたものであり、検出可能な周波数範囲を確保することができ、かつ、雑音による検出精度の低下を防ぐことができる周波数検出回路を提供することを目的とする。 The present invention has been made to solve the above-described problems, and provides a frequency detection circuit capable of ensuring a detectable frequency range and preventing a reduction in detection accuracy due to noise. The purpose is to do.
　本発明の周波数検出回路は、入力信号から周波数を検出し、検出した周波数を示す信号を出力する第１周波数検出回路と、第１周波数検出回路の出力信号が示す周波数からフィルタ回路の通過帯域内の周波数への周波数変換用の局部発振信号を生成する局部発振信号生成回路と、局部発振信号を用いて入力信号を周波数変換し、フィルタ回路に出力する周波数変換回路と、フィルタ回路の出力信号から周波数を検出し、検出した周波数を示す信号を出力する第２周波数検出回路と、第１周波数検出回路の出力信号が示す周波数と、第２周波数検出回路の出力信号が示す周波数とを用いて、入力信号の周波数を算出する周波数演算回路と、を備えるものである。 The frequency detection circuit of the present invention detects a frequency from an input signal, outputs a signal indicating the detected frequency, and within the passband of the filter circuit from the frequency indicated by the output signal of the first frequency detection circuit A local oscillation signal generation circuit for generating a local oscillation signal for frequency conversion to a frequency of a frequency, a frequency conversion circuit for frequency-converting an input signal using the local oscillation signal, and outputting the frequency to a filter circuit, and an output signal of the filter circuit Using the second frequency detection circuit that detects the frequency and outputs a signal indicating the detected frequency, the frequency indicated by the output signal of the first frequency detection circuit, and the frequency indicated by the output signal of the second frequency detection circuit, And a frequency calculation circuit for calculating the frequency of the input signal.
　本発明の周波数検出回路は、上記のように構成したので、検出可能な周波数範囲を確保することができ、かつ、雑音による検出精度の低下を防ぐことができる。 Since the frequency detection circuit of the present invention is configured as described above, a detectable frequency range can be secured, and a decrease in detection accuracy due to noise can be prevented.
本発明の実施の形態１に係る周波数検出回路の要部を示す回路構成図である。It is a circuit block diagram which shows the principal part of the frequency detection circuit which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係る局部発振信号生成回路の要部を示す回路構成図である。It is a circuit block diagram which shows the principal part of the local oscillation signal generation circuit which concerns on Embodiment 1 of this invention. 図３（ａ）は、入力信号の周波数スペクトルを示す説明図である。図３（ｂ）は、フィルタ回路が出力した信号の周波数スペクトルを示す説明図である。FIG. 3A is an explanatory diagram showing the frequency spectrum of the input signal. FIG. 3B is an explanatory diagram showing the frequency spectrum of the signal output from the filter circuit. 本発明の実施の形態１に係る他の局部発振信号生成回路の要部を示す回路構成図である。It is a circuit block diagram which shows the principal part of the other local oscillation signal generation circuit which concerns on Embodiment 1 of this invention. 本発明の実施の形態２に係る周波数検出回路の要部を示す回路構成図である。It is a circuit block diagram which shows the principal part of the frequency detection circuit which concerns on Embodiment 2 of this invention. 本発明の実施の形態２に係るフィルタ回路の要部を示す回路構成図である。It is a circuit block diagram which shows the principal part of the filter circuit which concerns on Embodiment 2 of this invention. 図７（ａ）は、入力信号の周波数スペクトルを示す説明図である。図７（ｂ）は、フィルタ回路が出力した信号の周波数スペクトルを示す説明図である。FIG. 7A is an explanatory diagram showing the frequency spectrum of the input signal. FIG. 7B is an explanatory diagram showing the frequency spectrum of the signal output from the filter circuit. 図８（ａ）は、入力信号の周波数スペクトルを示す説明図である。図８（ｂ）は、フィルタ回路が出力した信号の周波数スペクトルを示す説明図である。FIG. 8A is an explanatory diagram showing the frequency spectrum of the input signal. FIG. 8B is an explanatory diagram showing the frequency spectrum of the signal output from the filter circuit. 本発明の実施の形態２に係る他のフィルタ回路の要部を示す回路構成図である。It is a circuit block diagram which shows the principal part of the other filter circuit which concerns on Embodiment 2 of this invention. 本発明の実施の形態３に係る周波数検出回路の要部を示す回路構成図である。It is a circuit block diagram which shows the principal part of the frequency detection circuit which concerns on Embodiment 3 of this invention. 本発明の実施の形態４に係る周波数検出回路の要部を示す回路構成図である。It is a circuit block diagram which shows the principal part of the frequency detection circuit which concerns on Embodiment 4 of this invention.
　以下、この発明をより詳細に説明するために、この発明を実施するための形態について、添付の図面に従って説明する。
実施の形態１．
　図１は、実施の形態１に係る周波数検出回路１００の要部を示す回路構成図である。図１に示す如く、周波数検出回路１００は、当該回路の外部から入力信号Ｘｉｎが入力されるようになっている。入力信号Ｘｉｎには、周波数検出回路１００の検出対象である所望周波数成分と、雑音により生じた不要周波数成分とが含まれている。 Hereinafter, in order to explain the present invention in more detail, modes for carrying out the present invention will be described with reference to the accompanying drawings.
Embodiment 1 FIG.
FIG. 1 is a circuit configuration diagram showing a main part of the frequency detection circuit 100 according to the first embodiment. As shown in FIG. 1, the frequency detection circuit 100, an input signal X in from the outside of the circuit are inputted. The input signal Xin includes a desired frequency component that is a detection target of the frequency detection circuit 100 and an unnecessary frequency component caused by noise.
　第１周波数検出回路１は、入力信号Ｘｉｎを受け付けて、入力信号Ｘｉｎから周波数を検出するものである。第１周波数検出回路１は、検出した周波数ｆ１を示す信号を、局部発振信号生成回路２及び第２遅延補償回路７にそれぞれ出力するものである。 The first frequency detector circuit 1 receives an input signal X in, and detects the frequency from the input signal X in. The first frequency detection circuit 1 outputs a signal indicating the detected frequency f 1 to the local oscillation signal generation circuit 2 and the second delay compensation circuit 7, respectively.
　局部発振信号生成回路２は、第１周波数検出回路１の出力信号が示す周波数ｆ１と、予め設定された周波数ｆｍとを用いて、周波数ｆ１から周波数ｆｍへの周波数変換用の局部発振信号Ｘｐを生成するものである。周波数ｆｍは、フィルタ回路５の通過帯域Δｆ内の値に設定されており、例えば通過帯域Δｆの中心周波数と同等の値に設定されている。局部発振信号生成回路２は、生成した局部発振信号Ｘｐを周波数変換回路４に出力するものである。 The local oscillation signal generation circuit 2 uses the frequency f 1 indicated by the output signal of the first frequency detection circuit 1 and a preset frequency f m to perform local conversion for frequency conversion from the frequency f 1 to the frequency f m . The oscillation signal Xp is generated. Frequency f m is set is set to a value within the passband Delta] f of the filter circuit 5, the center frequency equal to a value of e.g. passband Delta] f. The local oscillation signal generation circuit 2 outputs the generated local oscillation signal Xp to the frequency conversion circuit 4.
　第１遅延補償回路３は、入力信号Ｘｉｎを受け付けて、入力信号Ｘｉｎを時間シフトするものである。具体的には、例えば、アナログ回路の場合、第１遅延補償回路３は、電気長の異なる複数の遅延線と、これらの遅延線を切り替えるスイッチとにより構成され、遅延線を切り替えることで時間シフトのシフト量を設定することができる。または、デジタル回路の場合、第１遅延補償回路３は、メモリ又はラッチに値を一時的に保持する回路により実現される。時間シフトのシフト量は、第１周波数検出回路１及び局部発振信号生成回路２により生じる遅延時間に応じた値に設定されている。すなわち、第１遅延補償回路３は、入力信号Ｘｉｎに対し、第１周波数検出回路１及び局部発振信号生成回路２による遅延を補償するものである。第１遅延補償回路３は、時間シフトした入力信号Ｘｉｎを周波数変換回路４に出力するものである。 First delay compensation circuit 3 receives an input signal X in, is to time shift the input signal X in. Specifically, for example, in the case of an analog circuit, the first delay compensation circuit 3 includes a plurality of delay lines having different electrical lengths and a switch for switching these delay lines, and the time shift is performed by switching the delay lines. Shift amount can be set. Alternatively, in the case of a digital circuit, the first delay compensation circuit 3 is realized by a circuit that temporarily holds a value in a memory or a latch. The shift amount of the time shift is set to a value corresponding to the delay time generated by the first frequency detection circuit 1 and the local oscillation signal generation circuit 2. That is, the first delay compensation circuit 3, the input signal X in, is to compensate for the delay by the first frequency detecting circuit 1 and the local oscillation signal generation circuit 2. The first delay compensation circuit 3 outputs the time-shifted input signal Xin to the frequency conversion circuit 4.
　周波数変換回路４は、局部発振信号生成回路２が生成した局部発振信号Ｘｐを用いて、第１遅延補償回路３が時間シフトした入力信号Ｘｉｎを周波数変換するものである。周波数変換回路４は、周波数変換した入力信号Ｘｉｎをフィルタ回路５に出力するものである。具体的には、例えば、周波数変換回路４はミキサにより構成されており、２つの入力信号の乗算により、入力信号の和と差、又は和若しくは差のみの周波数成分を出力することで周波数変換を行うものである。すなわち、周波数変換回路４の出力信号は、入力信号Ｘｉｎの周波数成分と局部発振信号Ｘｐの周波数成分とをミキサにより混合したものである。 Frequency conversion circuit 4, by using the local oscillation signal X p of the local oscillation signal generating circuit 2 has generated, an input signal X in the first delay compensation circuit 3 is shifted time is to frequency conversion. The frequency conversion circuit 4 outputs the frequency-converted input signal Xin to the filter circuit 5. Specifically, for example, the frequency conversion circuit 4 is configured by a mixer, and by performing multiplication of two input signals, the frequency conversion is performed by outputting the sum and difference of the input signals, or the frequency components of only the sum or the difference. Is what you do. That is, the output signal of the frequency conversion circuit 4, a frequency component of the frequency components and the local oscillation signal X p of the input signal X in is obtained by mixing by the mixer.
　フィルタ回路５は、例えばバンドパスフィルタ（Ｂａｎｄ－Ｐａｓｓ　Ｆｉｌｔｅｒ，ＢＰＦ）であり、通過帯域Δｆの幅及び中心周波数の値が固定されている。フィルタ回路５は、周波数変換回路４の出力信号のうち通過帯域Δｆ外の周波数成分を抑制し、通過帯域Δｆ内の周波数成分を含む信号Ｘｍを出力するものである。 The filter circuit 5 is, for example, a bandpass filter (Band-Pass Filter, BPF), and the width of the passband Δf and the value of the center frequency are fixed. The filter circuit 5 is for suppressing band Delta] f out of the frequency component passing the output signals of the frequency conversion circuit 4, and outputs a signal X m including frequency components in the passband Delta] f.
　第２周波数検出回路６は、フィルタ回路５の出力信号Ｘｍから周波数を検出するものである。第２周波数検出回路６は、検出した周波数ｆ２を示す信号を、周波数演算回路８に出力するものである。 The second frequency detector circuit 6 is for detecting the frequency from the output signal X m of the filter circuit 5. The second frequency detection circuit 6 outputs a signal indicating the detected frequency f 2 to the frequency calculation circuit 8.
　第２遅延補償回路７は、第１周波数検出回路１の出力信号を時間シフトするものである。具体的には、例えば、アナログ回路の場合、第２遅延補償回路７は、電気長の異なる複数の遅延線と、これらの遅延線を切り替えるスイッチとにより構成され、遅延線を切り替えることで時間シフトのシフト量を設定することができる。または、デジタル回路の場合、第２遅延補償回路７は、メモリ又はラッチに値を一時的に保持する回路により実現される。時間シフトのシフト量は、局部発振信号生成回路２、周波数変換回路４、フィルタ回路５及び第２周波数検出回路６により生じる遅延時間に応じた値に設定されている。すなわち、第２遅延補償回路７は、第１周波数検出回路１の出力信号に対し、局部発振信号生成回路２、周波数変換回路４、フィルタ回路５及び第２周波数検出回路６による遅延を補償するものである。第２遅延補償回路７は、時間シフトした信号を周波数演算回路８に出力するものである。 The second delay compensation circuit 7 shifts the output signal of the first frequency detection circuit 1 with time. Specifically, for example, in the case of an analog circuit, the second delay compensation circuit 7 is configured by a plurality of delay lines having different electrical lengths and a switch for switching these delay lines, and the time shift is performed by switching the delay lines. Shift amount can be set. Alternatively, in the case of a digital circuit, the second delay compensation circuit 7 is realized by a circuit that temporarily holds a value in a memory or a latch. The shift amount of the time shift is set to a value corresponding to the delay time generated by the local oscillation signal generation circuit 2, the frequency conversion circuit 4, the filter circuit 5, and the second frequency detection circuit 6. That is, the second delay compensation circuit 7 compensates for the delay caused by the local oscillation signal generation circuit 2, the frequency conversion circuit 4, the filter circuit 5, and the second frequency detection circuit 6 with respect to the output signal of the first frequency detection circuit 1. It is. The second delay compensation circuit 7 outputs a time-shifted signal to the frequency calculation circuit 8.
　周波数演算回路８は、第２遅延補償回路７により時間シフトされた第１周波数検出回路１の出力信号が示す周波数ｆ１と、第２周波数検出回路６の出力信号が示す周波数ｆ２とを用いて、周波数ｆｘを算出するものである。具体的には、例えば、周波数演算回路８は以下の式（１）により周波数ｆｘを算出する。周波数演算回路８は、算出した周波数ｆｘを、入力信号Ｘｉｎの周波数として周波数検出回路１００の外部に出力するものである。
　ｆｘ＝ｆ１＋ｆ２－ｆｍ　　　　　　　　　　　　　　（１） The frequency calculation circuit 8 uses the frequency f 1 indicated by the output signal of the first frequency detection circuit 1 shifted by time by the second delay compensation circuit 7 and the frequency f 2 indicated by the output signal of the second frequency detection circuit 6. Te, and calculates the frequency f x. Specifically, for example, the frequency computing circuit 8 computes the frequency f x by the following equation (1). The frequency calculation circuit 8 outputs the calculated frequency f x to the outside of the frequency detection circuit 100 as the frequency of the input signal X in .
f x = f 1 + f 2 −f m (1)
　第１周波数検出回路１、局部発振信号生成回路２、第１遅延補償回路３、周波数変換回路４、フィルタ回路５、第２周波数検出回路６、第２遅延補償回路７及び周波数演算回路８により、周波数検出回路１００が構成されている。 By the first frequency detection circuit 1, the local oscillation signal generation circuit 2, the first delay compensation circuit 3, the frequency conversion circuit 4, the filter circuit 5, the second frequency detection circuit 6, the second delay compensation circuit 7, and the frequency calculation circuit 8, A frequency detection circuit 100 is configured.
　周波数検出回路１００は、全体が１個のアナログ回路で実現されたものでも良く、デジタル回路で実現されたものでも良い。また、周波数検出回路１００を構成する各回路のそれぞれがアナログ回路で実現されたものでも良く、デジタル回路で実現されたものでも良い。 The entire frequency detection circuit 100 may be realized by one analog circuit or may be realized by a digital circuit. Further, each circuit constituting the frequency detection circuit 100 may be realized by an analog circuit or may be realized by a digital circuit.
　また、周波数検出回路１００は、専用の処理回路により実現されたものでも良い。処理回路は、例えば、ＦＰＧＡ（Ｆｉｅｌｄ－Ｐｒｏｇｒａｍｍａｂｌｅ　Ｇａｔｅ　Ａｒｒａｙ）又はＡＳＩＣ（Ａｐｐｌｉｃａｔｉｏｎ　Ｓｐｅｃｉｆｉｃ　Ｉｎｔｅｇｒａｔｅｄ　Ｃｉｒｃｕｉｔ）などのデジタル信号処理用のＬＳＩ（Ｌａｒｇｅ－Ｓｃａｌｅ　Ｉｎｔｅｇｒａｔｉｏｎ）である。周波数検出回路１００全体が１個の処理回路で実現されたものでも良く、周波数検出回路１００を構成する各回路がそれぞれ処理回路で実現されたものでも良い。 Further, the frequency detection circuit 100 may be realized by a dedicated processing circuit. The processing circuit is, for example, an LSI (Large-Scale Integration) for digital signal processing such as FPGA (Field-Programmable Gate Array) or ASIC (Application Specific Integrated Circuit). The entire frequency detection circuit 100 may be realized by a single processing circuit, or each circuit constituting the frequency detection circuit 100 may be realized by a processing circuit.
　次に、図２を参照して、局部発振信号生成回路２の詳細な回路構成について説明する。
　演算回路２１は、周波数ｆ１及び周波数ｆｍを用いて、局部発振信号Ｘｐの周波数ｆｐを算出するものである。具体的には、例えば、フィルタ回路５の通過帯域Δｆの中心周波数が入力信号Ｘｉｎに含まれる所望周波数成分の周波数ｆｉｎよりも高い値に設定されており、周波数ｆｍが周波数ｆ１よりも高い値である場合、演算回路２１は以下の式（２）により周波数ｆｐを算出する。
　ｆｐ＝ｆｍ－ｆ１　　　　　　　　　　　　　　　　　（２） Next, a detailed circuit configuration of the local oscillation signal generation circuit 2 will be described with reference to FIG.
Calculation circuit 21 uses the frequency f 1 and frequency f m, and calculates the frequency f p of the local oscillation signal X p. Specifically, for example, is set to a value higher than the frequency f in of the desired frequency component center frequency of the pass band Δf is included in the input signal X in the filter circuit 5, the frequency f m is from frequency f 1 If also a high value, the arithmetic circuit 21 calculates the frequency f p by the following equation (2).
f p = f m −f 1 (2)
　位相積算回路２２は、演算回路２１が算出した周波数ｆｐを一定周期で積算するものである。具体的には、位相積算回路２２は、２つの入力を加算して出力する加算回路により構成されている。この加算回路は、自身の出力を入力の１つとすることで累算演算を行うものであり、周波数を入力にすると出力は位相となる。この加算回路は、直接デジタルシンセサイザ（Ｄｉｒｅｃｔ　Ｄｉｇｉｔａｌ　Ｓｙｎｔｈｅｓｉｚｅｒ）などに用いられている一般的な回路である。このように構成された位相積算回路２２による積算結果は、局部発振信号Ｘｐの位相を示している。位相振幅変換回路２３は、位相積算回路２２の積算結果が示す位相を、この位相に応じた振幅に変換するものである。変換方法には、例えば、図示しないメモリ若しくはルックアップテーブルに振幅値を保持する方法、又は、演算により振幅値を算出する方法などがある。デジタルアナログ変換回路２４は、位相振幅変換回路２３の出力信号をデジタル信号からアナログ信号に変換するものである。このアナログ信号が局部発振信号Ｘｐとなる。 Phase integrated circuit 22 is for integrating the frequency f p of the arithmetic circuit 21 is calculated at a predetermined period. Specifically, the phase integrating circuit 22 is configured by an adding circuit that adds and outputs two inputs. This adder circuit performs an accumulation operation by setting its own output as one of the inputs, and when the frequency is input, the output becomes a phase. This adder circuit is a general circuit used in a direct digital synthesizer (Direct Digital Synthesizer) or the like. The cumulative result of the phase accumulation circuit 22 that is configured to indicate a phase of the local oscillation signal X p. The phase amplitude conversion circuit 23 converts the phase indicated by the integration result of the phase integration circuit 22 into an amplitude corresponding to this phase. Examples of the conversion method include a method of holding an amplitude value in a memory or a lookup table (not shown), a method of calculating an amplitude value by calculation, and the like. The digital / analog conversion circuit 24 converts the output signal of the phase / amplitude conversion circuit 23 from a digital signal to an analog signal. This analog signal becomes a local oscillation signal X p.
　位相積算回路２２、位相振幅変換回路２３及びデジタルアナログ変換回路２４により、ＣＷ（Ｃｏｎｔｉｎｕｏｕｓ　Ｗａｖｅ）生成回路２５が構成されている。演算回路２１及びＣＷ生成回路２５により、局部発振信号生成回路２が構成されている。 The phase integrating circuit 22, the phase / amplitude converting circuit 23, and the digital / analog converting circuit 24 constitute a CW (Continuous Wave) generating circuit 25. The arithmetic circuit 21 and the CW generation circuit 25 constitute a local oscillation signal generation circuit 2.
　次に、図３を参照して、周波数検出回路１００の動作及び効果について説明する。
　図３（ａ）は、周波数検出回路１００に入力される入力信号Ｘｉｎの周波数スペクトルを示している。図３（ａ）に示す如く、入力信号Ｘｉｎには、周波数検出回路１００の検出対象である所望周波数成分Ａと、雑音により生じた不要周波数成分Ｂとが含まれている。不要周波数成分Ｂは、所望周波数成分Ａの周波数ｆｉｎを含む広い周波数帯域に亘って存在している。 Next, the operation and effect of the frequency detection circuit 100 will be described with reference to FIG.
FIGS. 3 (a) shows a frequency spectrum of the input signal X in inputted to the frequency detection circuit 100. As shown in FIG. 3 (a), the input signal X in, a desired frequency component A is a detection target of the frequency detection circuit 100 includes a and the unnecessary frequency component B caused by noise. Unnecessary frequency components B is present over a wide frequency band including the frequency f in the desired frequency components A.
　不要周波数成分Ｂが存在するため、第１周波数検出回路１が入力信号Ｘｉｎから検出する周波数ｆ１は、所望周波数成分Ａの周波数ｆｉｎと同じ値にならない。周波数ｆ１と周波数ｆｉｎ間の周波数誤差をｆｅｒｒとすると、周波数ｆ１は以下の式（３）で表される。
　ｆ１＝ｆｉｎ＋ｆｅｒｒ　　　　　　　　　　　　　　　（３） Because there are unnecessary frequency component B, the frequency f 1 of the first frequency detecting circuit 1 detects the input signal X in can not be the same value as the frequency f in the desired frequency components A. When the frequency error between the frequency f 1 and the frequency f in the f err, frequency f 1 is represented by the following formula (3).
f 1 = f in + f err (3)
　演算回路２１が算出する局部発振信号Ｘｐの周波数ｆｐは、上記式（２）に式（３）を代入することで、以下の式（４）で表される。
　ｆｐ＝ｆｍ－（ｆｉｎ＋ｆｅｒｒ）
　　　＝ｆｍ－ｆｉｎ－ｆｅｒｒ　　　　　　　　　　　　（４） The frequency f p of the local oscillation signal X p calculated by the arithmetic circuit 21 is expressed by the following formula (4) by substituting the formula (3) into the above formula (2).
f p = f m − (f in + f err )
= F m −f in −f err (4)
　図３（ｂ）は、フィルタ回路５が出力した信号Ｘｍの周波数スペクトルを示している。　周波数変換回路４は、ミクサにより入力信号Ｘｉｎと局部発振信号Ｘｐとの和又は差の周波数成分を出力することで、入力信号Ｘｉｎの周波数変換を行う。ここで、周波数ｆｍが通過帯域Δｆ内の値に設定されているため、周波数変換回路４による周波数変換後の入力信号Ｘｉｎは、所望周波数成分Ａがフィルタ回路５の通過帯域Δｆ内に含まれている。このため、図３（ｂ）に示す如く、フィルタ回路５の出力信号Ｘｍにも所望周波数成分Ａが含まれている。 FIG. 3 (b) shows the frequency spectrum of the signal X m filter circuit 5 has output. Frequency conversion circuit 4, by outputting the frequency components of the sum or difference between the input signal X in the local oscillation signal X p by the mixer performs a frequency conversion of the input signal X in. Here, since the frequency f m is set to a value within the passband Delta] f, the input signal X in after frequency conversion by the frequency conversion circuit 4, included in the passband Delta] f of a desired frequency component A filter circuit 5 It is. Therefore, as shown in FIG. 3 (b), it contains a desired frequency component A to the output signal X m of the filter circuit 5.
　また、フィルタ回路５の出力信号Ｘｍにおいて、不要周波数成分Ｂは通過帯域Δｆ内を除き大半が抑制されている。このため、第２周波数検出回路６が出力信号Ｘｍから検出する周波数ｆ２は、不要周波数成分Ｂによる周波数誤差が無視できるほど小さく、以下の式（５）で表される。
　ｆ２＝ｆｉｎ＋ｆｐ　　　　　　　　　　　　　　　　　　（５） Further, the output signal X m of the filter circuit 5, unnecessary frequency components B Most except in the pass band Δf is suppressed. Therefore, the frequency f 2 detected from the output signal X m by the second frequency detection circuit 6 is so small that the frequency error due to the unnecessary frequency component B can be ignored, and is expressed by the following equation (5).
f 2 = f in + f p (5)
　また、上記式（５）に式（４）を代入することで、周波数ｆ２は以下の式（６）で表される。
　ｆ２＝ｆｉｎ＋（ｆｍ－ｆｉｎ－ｆｅｒｒ）
　　　＝ｆｍ－ｆｅｒｒ　　　　　　　　　　　　　　　　　（６） Further, by substituting equation (4) into the equation (5), the frequency f 2 is expressed by the following equation (6).
f 2 = f in + (f m −f in −f err )
= F m -f err (6)
　周波数演算回路８が算出する周波数ｆｘは、上記式（１）に式（３）及び式（６）を代入することで、以下の式（７）で表される。
　ｆｘ＝（ｆｉｎ＋ｆｅｒｒ）＋（ｆｍ－ｆｅｒｒ）－ｆｍ
　　　＝ｆｉｎ　　　　　　　　　　　　　　　　　　　　　（７） Frequency f x for the frequency calculation circuit 8 calculates, by substituting Equation (3) and (6) in the above equation (1) is expressed by the following equation (7).
f x = (f in + f err ) + (f m −f err ) −f m
= F in (7)
　式（７）に示す如く、周波数演算回路８が算出する周波数ｆｘは、入力信号Ｘｉｎに含まれる所望周波数成分Ａの周波数ｆｉｎと同じ値である。すなわち、周波数検出回路１００は、雑音により周波数の検出精度が低下するのを防ぐことができる。 As shown in equation (7), the frequency f x of the frequency calculation circuit 8 calculates is the same as the frequency f in of the desired frequency component A included in the input signal X in. That is, the frequency detection circuit 100 can prevent the frequency detection accuracy from being reduced by noise.
　また、周波数検出回路１００は、周波数変換回路４により、第１周波数検出回路１の検出結果に基づいて所望周波数成分Ａが通過帯域Δｆ内に含まれるように入力信号Ｘｉｎを周波数変換してからフィルタ回路５に出力している。このため、フィルタ回路５に通過帯域Δｆ幅の狭いＢＰＦを用いた場合でも所望周波数成分Ａの周波数を確実に検出することができ、周波数の検出範囲を確保することができる。 Further, the frequency detection circuit 100 performs frequency conversion of the input signal X in by the frequency conversion circuit 4 based on the detection result of the first frequency detection circuit 1 so that the desired frequency component A is included in the passband Δf. Output to the filter circuit 5. Therefore, even when a BPF having a narrow passband Δf width is used for the filter circuit 5, the frequency of the desired frequency component A can be reliably detected, and the frequency detection range can be ensured.
　なお、局部発振信号生成回路２は、図２に示す回路構成に限定されるものではない。例えば、局部発振信号生成回路２の出力をデジタル信号とする場合、図２に示すデジタルアナログ変換回路２４は不要である。この場合、位相振幅変換回路２３の出力信号が局部発振信号Ｘｐとなる。 The local oscillation signal generation circuit 2 is not limited to the circuit configuration shown in FIG. For example, when the output of the local oscillation signal generation circuit 2 is a digital signal, the digital-analog conversion circuit 24 shown in FIG. 2 is not necessary. In this case, the output signal of the phase amplitude conversion circuit 23 becomes the local oscillation signal X p.
　また、図４に、局部発振信号生成回路２の回路構成の他の例を示す。分周数演算回路３１は、演算回路２１が算出した周波数ｆｐを用いて、可変分周回路３２の分周数を設定するものである。可変分周回路３２は、分周数演算回路３１が設定した分周数で、発振回路３６の出力信号を分周するものである。基準信号回路３３は、基準信号を生成して出力するものである。位相比較回路３４は、可変分周回路３２の出力信号の位相と、基準信号回路３３の出力信号の位相とを比較して、比較結果を出力するものである。ループフィルタ回路３５は、位相比較回路３４の出力信号に含まれる高周波成分を抑制して、発振回路３６の制御信号を生成するものである。発振回路３６は、ループフィルタ回路３５から入力された制御信号に応じた周波数の連続信号を生成するものである。この連続信号が局部発振信号Ｘｐとなる。 FIG. 4 shows another example of the circuit configuration of the local oscillation signal generation circuit 2. Dividing number calculating circuit 31, using the frequency f p of the arithmetic circuit 21 is calculated, is to set the frequency division number of the variable frequency divider 32. The variable frequency dividing circuit 32 divides the output signal of the oscillation circuit 36 by the frequency dividing number set by the frequency dividing number calculating circuit 31. The reference signal circuit 33 generates and outputs a reference signal. The phase comparison circuit 34 compares the phase of the output signal of the variable frequency dividing circuit 32 with the phase of the output signal of the reference signal circuit 33 and outputs a comparison result. The loop filter circuit 35 suppresses high frequency components contained in the output signal of the phase comparison circuit 34 and generates a control signal for the oscillation circuit 36. The oscillation circuit 36 generates a continuous signal having a frequency corresponding to the control signal input from the loop filter circuit 35. This continuous signal is a local oscillation signal X p.
　分周数演算回路３１、可変分周回路３２、基準信号回路３３、位相比較回路３４、ループフィルタ回路３５及び発振回路３６により、ＣＷ生成回路３７が構成されている。演算回路２１及びＣＷ生成回路３７により、局部発振信号生成回路２が構成されている。なお、図４の例ではＣＷ生成回路３７に１個の可変分周回路３２を設けているが、同様の可変分周回路を複数個設けたものであっても良い。 The CW generation circuit 37 is configured by the frequency division number calculation circuit 31, the variable frequency division circuit 32, the reference signal circuit 33, the phase comparison circuit 34, the loop filter circuit 35, and the oscillation circuit 36. The arithmetic circuit 21 and the CW generation circuit 37 constitute a local oscillation signal generation circuit 2. In the example of FIG. 4, one variable frequency dividing circuit 32 is provided in the CW generation circuit 37, but a plurality of similar variable frequency dividing circuits may be provided.
　また、周波数検出回路１００の入力に図示しないフィルタ回路を設け、当該フィルタ回路を通過した入力信号Ｘｉｎが第１周波数検出回路１及び第１遅延補償回路３に入力されるものであっても良い。当該フィルタ回路は、周波数検出回路１００の検出範囲が狭まるのを防ぐため、検出対象の周波数ｆｉｎを含む十分に広い通過帯域を有するフィルタを用いるのが好適である。 Further, a filter circuit (not shown) to the input of the frequency detection circuit 100 is provided, may be one input signal X in which passes through the filter circuit is input to the first frequency detecting circuit 1 and the first delay compensation circuit 3 . The filter circuit, to prevent the detection range of the frequency detection circuit 100 is narrowed, it is preferable to use a filter having a sufficiently wide pass band including the frequency f in of the detection object.
　また、第１周波数検出回路１及び第２周波数検出回路６は、入力された信号から周波数を検出できる回路であれば良く、如何なる回路構成により周波数を検出するものであっても良い。例えば、ＦＦＴ（Ｆａｓｔ　Ｆｏｕｒｉｅｒ　Ｔｒａｎｓｆｏｒｍ）により周波数を検出する回路、カウンタを用いて周波数を検出する回路、ヒルベルト変換回路を含むトランスバーサルフィルタを用いて周波数を検出する回路、又は、直交復調により周波数を検出する回路のいずれの回路であっても良い。
　ここで、ＦＦＴにより周波数を検出する回路は、具体的には、時間波形をフーリエ変換して、ピークスペクトルの位置から周波数を検出する回路である。カウンタを用いて周波数を検出する回路は、具体的には、特定の周期の時間を計測し、計測結果の逆数から周波数を検出する回路である。トランスバーサルフィルタを用いて周波数を検出する回路は、具体的には、ヒルベルト変換により、入力波形に対して９０度位相シフトした直交波形を生成し、入力波形と直交波形の振幅比より位相を算出して、位相の変化量から周波数を検出する回路である。トランスバーサルフィルタは、ヒルベルト変換を実現する回路の１つである。直交復調により周波数を検出する回路は、具体的には、入力波形を直交復調することで、９０度位相差を有する２つの波形を生成し、これら波形の振幅比より位相を算出して、位相の変化量から周波数を検出する回路である。
　また、第１周波数検出回路１と第２周波数検出回路６の回路構成が同じものでも良く、異なるものでも良い。 The first frequency detection circuit 1 and the second frequency detection circuit 6 may be any circuit that can detect the frequency from the input signal, and may detect the frequency by any circuit configuration. For example, a circuit that detects a frequency by FFT (Fast Fourier Transform), a circuit that detects a frequency by using a counter, a circuit that detects a frequency by using a transversal filter including a Hilbert transform circuit, or a frequency that is detected by orthogonal demodulation Any circuit may be used.
Here, the circuit for detecting the frequency by FFT is specifically a circuit for detecting the frequency from the position of the peak spectrum by Fourier-transforming the time waveform. The circuit that detects the frequency using the counter is specifically a circuit that measures the time of a specific period and detects the frequency from the reciprocal of the measurement result. Specifically, the circuit that detects the frequency using the transversal filter generates a quadrature waveform that is 90 ° phase shifted from the input waveform by Hilbert transform, and calculates the phase from the amplitude ratio of the input waveform and the quadrature waveform. Thus, the frequency is detected from the amount of phase change. The transversal filter is one of the circuits that realize the Hilbert transform. Specifically, the circuit that detects the frequency by quadrature demodulation generates two waveforms having a phase difference of 90 degrees by quadrature demodulation of the input waveform, calculates the phase from the amplitude ratio of these waveforms, It is a circuit that detects the frequency from the amount of change.
The first frequency detection circuit 1 and the second frequency detection circuit 6 may have the same or different circuit configurations.
　また、第１周波数検出回路１及び第２周波数検出回路６は、入力された信号から周波数を直接検出する回路に代えて、入力された信号から位相を検出し、この位相を周波数に変換する回路であっても良い。位相を周波数に変換する方法は、例えば、特許文献１の周波数検出回路と同様に、時間的に連続して検出された複数個の位相の差分から周波数を求める方法がある。 The first frequency detection circuit 1 and the second frequency detection circuit 6 are circuits that detect a phase from an input signal and convert the phase into a frequency instead of a circuit that directly detects the frequency from the input signal. It may be. As a method for converting a phase into a frequency, for example, as in the frequency detection circuit of Patent Document 1, there is a method for obtaining a frequency from a difference between a plurality of phases detected successively in time.
　また、周波数ｆｍは通過帯域Δｆ内の値であれば良く、通過帯域Δｆの中心周波数と同等の値に限定されるものではない。しかしながら、周波数誤差ｆｅｒｒにより周波数変換後の所望周波数成分が通過帯域Δｆから外れるのを防ぐ観点から、周波数ｆｍは通過帯域Δｆの中心周波数と同等の値、又はこの近傍の値に設定するのが好適である。 The frequency f m may be a value in the passband Delta] f, it is not limited to the center frequency equal to the values of the passband Delta] f. However, from the viewpoint of preventing the desired frequency component after frequency conversion from deviating from the pass band Δf due to the frequency error f err , the frequency f m is set to a value equivalent to the center frequency of the pass band Δf or a value near this. Is preferred.
　以上のように、実施の形態１の周波数検出回路１００は、入力信号Ｘｉｎから周波数を検出し、検出した周波数ｆ１を示す信号を出力する第１周波数検出回路１と、第１周波数検出回路１の出力信号が示す周波数ｆ１からフィルタ回路５の通過帯域Δｆ内の周波数ｆｍへの周波数変換用の局部発振信号Ｘｐを生成する局部発振信号生成回路２と、局部発振信号Ｘｐを用いて入力信号Ｘｉｎを周波数変換し、フィルタ回路５に出力する周波数変換回路４と、フィルタ回路５の出力信号から周波数を検出し、検出した周波数ｆ２を示す信号を出力する第２周波数検出回路６と、第１周波数検出回路１の出力信号が示す周波数ｆ１と、第２周波数検出回路６の出力信号が示す周波数ｆ２とを用いて、入力信号Ｘｉｎの周波数ｆｘを算出する周波数演算回路８と、を備える。これにより、検出可能な周波数範囲を確保することができ、かつ、雑音により周波数の検出精度が低下するのを防ぐことができる。 As described above, the frequency detecting circuit 100 of the first embodiment detects the frequency of the input signal X in, the first frequency detecting circuit 1 outputs a signal indicating the frequency f 1 detected, the first frequency detecting circuit a local oscillation signal generation circuit 2 for generating a local oscillation signal X p for frequency conversion from the frequency f 1 of the first output signal indicates to the frequency f m in the pass band Δf of the filter circuit 5, the local oscillation signal X p used to frequency-convert the input signal X in it, the frequency conversion circuit 4 to be output to the filter circuit 5, detects a frequency from the output signal of the filter circuit 5, the second frequency detection for outputting a signal indicating the frequency f 2 detected calculating a circuit 6, the frequency f 1 of the output signal of the first frequency detecting circuit 1 is shown, using a frequency f 2 where the output signal of the second frequency detection circuit 6 indicates, the frequency f x of the input signal X in Comprising a wave number calculation circuit 8, a. As a result, a detectable frequency range can be ensured, and the frequency detection accuracy can be prevented from being lowered by noise.
実施の形態２．
　図５は、実施の形態２に係る周波数検出回路１００ａの要部を示す回路構成図である。図５を参照して、周波数ｆｍ及びフィルタ回路１１の通過帯域Δｆの中心周波数を可変とした周波数検出回路１００ａについて説明する。なお、図５において、図１に示す実施の形態１の周波数検出回路１００と同様の回路には同一符号を付して説明を省略する。 Embodiment 2. FIG.
FIG. 5 is a circuit configuration diagram showing a main part of the frequency detection circuit 100a according to the second embodiment. Referring to FIG. 5, described frequency detection circuit 100a to the center frequency of the pass band Δf and the variable frequency f m and the filter circuit 11. In FIG. 5, a circuit similar to the frequency detection circuit 100 of the first embodiment shown in FIG.
　第１周波数検出回路１は、入力信号Ｘｉｎから検出した周波数ｆ１を示す信号を、係数演算回路９、局部発振信号生成回路２、中心周波数制御回路１０及び第２遅延補償回路７にそれぞれ出力するものである。 The first frequency detection circuit 1 outputs a signal indicating the frequency f 1 detected from the input signal X in to the coefficient calculation circuit 9, the local oscillation signal generation circuit 2, the center frequency control circuit 10, and the second delay compensation circuit 7, respectively. To do.
　係数演算回路９は、第１周波数検出回路１の出力信号が示す周波数ｆ１に応じて、周波数ｆｍを設定するものである。具体的には、例えば、係数演算回路９は、周波数ｆ１との比較対象である基準周波数ｆｔｈが予め設定されている。係数演算回路９は、周波数ｆ１が基準周波数ｆｔｈよりも低い場合、基準周波数ｆｔｈよりも高い値に周波数ｆｍを設定する。また、係数演算回路９は、周波数ｆ１が基準周波数ｆｔｈよりも高い場合、基準周波数ｆｔｈよりも低い値に周波数ｆｍを設定する。 Coefficient calculating circuit 9, according to the frequency f 1 of the output signal of the first frequency detecting circuit 1 is shown, it is to set the frequency f m. Specifically, for example, the coefficient calculation circuit 9, the reference frequency f th is preset to be compared with the frequency f 1. Coefficient calculating circuit 9, when the frequency f 1 is lower than the reference frequency f th, to set the frequency f m to a value higher than the reference frequency f th. The coefficient calculation circuit 9, when the frequency f 1 is higher than the reference frequency f th, to set the frequency f m to a value lower than the reference frequency f th.
　また、係数演算回路９は、各周波数成分のレベルとの比較対象である基準レベルが予め設定されている。基準レベルは、例えば、所望周波数成分のレベルの予測値に対し半分の値に設定されている。係数演算回路９は、周波数変換回路４の出力信号においてフィルタ回路１１の通過帯域Δｆ内に基準レベル以上の周波数成分が所望周波数成分のみとなる値に周波数ｆｍを設定する。 The coefficient calculation circuit 9 is preset with a reference level that is a comparison target with the level of each frequency component. For example, the reference level is set to a half value with respect to the predicted value of the level of the desired frequency component. Coefficient calculating circuit 9 sets the frequency f m to a value higher than a reference level of the frequency component is only desired frequency components in the passband Δf of the filter circuit 11 in the output signal of the frequency conversion circuit 4.
　さらに、周波数検出回路１００ａがＬＳＩなどの処理回路で構成されている場合、当該処理回路が処理するデジタル信号のサンプリング周波数の半分の周波数を「ナイキスト周波数」という。係数演算回路９は、上記の条件を満たす周波数のうち、ナイキスト周波数以下の値に周波数ｆｍを設定する。 Furthermore, when the frequency detection circuit 100a is configured by a processing circuit such as an LSI, a frequency that is half the sampling frequency of the digital signal processed by the processing circuit is referred to as a “Nyquist frequency”. Coefficient calculating circuit 9, of the above conditions are satisfied frequency, sets the frequency f m with the following values Nyquist frequency.
　係数演算回路９は、例えば、入力値に対して内部で保存している値と比較し、所定の周波数になるための係数を演算するデジタル回路などにより実現される。 The coefficient calculation circuit 9 is realized by, for example, a digital circuit that compares an input value with a value stored internally and calculates a coefficient for obtaining a predetermined frequency.
　係数演算回路９は、設定した周波数ｆｍを示す信号を局部発振信号生成回路２に出力する。局部発振信号生成回路２は、第１周波数検出回路１の出力信号が示す周波数ｆ１と、係数演算回路９の出力信号が示す周波数ｆｍとを用いて局部発振信号Ｘｐを生成する。すなわち、係数演算回路９は、周波数ｆｍを設定することで、局部発振信号Ｘｐの周波数ｆｐを制御するものである。 Coefficient calculating circuit 9 outputs a signal indicating a frequency f m which is set to the local oscillation signal generation circuit 2. Local oscillation signal generating circuit 2, a frequency f 1 to the output signal of the first frequency detecting circuit 1 is shown, to generate a local oscillation signal X p by using the frequency f m indicated by the output signal of the coefficient calculation circuit 9. That is, the coefficient calculation circuit 9, by setting the frequency f m, and controls the frequency f p of the local oscillation signal X p.
　また、係数演算回路９は、設定した周波数ｆｍを示す信号を中心周波数制御回路１０に出力する。中心周波数制御回路１０は、係数演算回路９の出力信号が示す周波数ｆｍに応じて、フィルタ回路１１の通過帯域Δｆの中心周波数を周波数ｆｍに近づける制御信号Ｄｆを生成するものである。中心周波数制御回路１０は、ｆｍを表す値をアドレスとし、制御信号Ｄｆを保持したメモリを有するものでも良く、ｆｍを表す値から制御信号Ｄｆを演算する回路により構成したものでも良い。中心周波数制御回路１０は、生成した制御信号Ｄｆをフィルタ回路１１に出力するものである。 The coefficient calculation circuit 9 outputs a signal indicating a frequency f m which is set to the center frequency control circuit 10. Center frequency control circuit 10, according to the frequency f m indicated by the output signal of the coefficient calculation circuit 9, and generates a control signal D f to bring the center frequency of the pass band Δf of the filter circuit 11 to a frequency f m. Center frequency control circuit 10, as an address value representing the f m, may be those having a memory that holds the control signal D f, it may be one constituted by a circuit for calculating a control signal D f from the value representing the f m . The center frequency control circuit 10 outputs the generated control signal Df to the filter circuit 11.
　フィルタ回路１１は、例えばＢＰＦであり、通過帯域Δｆの中心周波数が可変である。通過帯域Δｆの中心周波数は、中心周波数制御回路１０が出力した制御信号Ｄｆにより制御される。フィルタ回路１１は、周波数変換回路４の出力信号のうち通過帯域Δｆ外の周波数成分を抑制し、通過帯域Δｆ内の周波数成分を含む信号Ｘｍを第２周波数検出回路６に出力するものである。 The filter circuit 11 is, for example, a BPF, and the center frequency of the pass band Δf is variable. The center frequency of the pass band Δf is controlled by the control signal D f output from the center frequency control circuit 10. The filter circuit 11 is for suppressing the band Δf frequency component outside passage of the output signal of the frequency conversion circuit 4, and outputs a signal X m including frequency components in the pass band Δf to the second frequency detection circuit 6 .
　第１遅延補償回路３は、時間シフトのシフト量が、第１周波数検出回路１、係数演算回路９及び局部発振信号生成回路２により生じる遅延時間に応じた値に設定されている。すなわち、第１遅延補償回路３は、入力信号Ｘｉｎに対し、第１周波数検出回路１、係数演算回路９及び局部発振信号生成回路２による遅延を補償して周波数変換回路４に出力するものである。 In the first delay compensation circuit 3, the shift amount of the time shift is set to a value corresponding to the delay time generated by the first frequency detection circuit 1, the coefficient calculation circuit 9 and the local oscillation signal generation circuit 2. That is, the first delay compensation circuit 3 compensates for the delay caused by the first frequency detection circuit 1, the coefficient calculation circuit 9, and the local oscillation signal generation circuit 2 with respect to the input signal X in and outputs it to the frequency conversion circuit 4. is there.
　第２遅延補償回路７は、時間シフトのシフト量が、係数演算回路９、局部発振信号生成回路２、周波数変換回路４、中心周波数制御回路１０、フィルタ回路１１及び第２周波数検出回路６により生じる遅延時間に応じた値に設定されている。すなわち、第２遅延補償回路７は、第１周波数検出回路１の出力信号に対し、係数演算回路９、局部発振信号生成回路２、周波数変換回路４、中心周波数制御回路１０、フィルタ回路１１及び第２周波数検出回路６による遅延を補償して周波数演算回路８に出力するものである。 In the second delay compensation circuit 7, the shift amount of the time shift is generated by the coefficient calculation circuit 9, the local oscillation signal generation circuit 2, the frequency conversion circuit 4, the center frequency control circuit 10, the filter circuit 11, and the second frequency detection circuit 6. The value is set according to the delay time. That is, the second delay compensation circuit 7 performs the coefficient calculation circuit 9, the local oscillation signal generation circuit 2, the frequency conversion circuit 4, the center frequency control circuit 10, the filter circuit 11, and the filter circuit 11 with respect to the output signal of the first frequency detection circuit 1. The delay by the two-frequency detection circuit 6 is compensated and output to the frequency calculation circuit 8.
　第１周波数検出回路１、係数演算回路９、局部発振信号生成回路２、第１遅延補償回路３、周波数変換回路４、中心周波数制御回路１０、フィルタ回路１１、第２周波数検出回路６、第２遅延補償回路７及び周波数演算回路８により、周波数検出回路１００ａが構成されている。 First frequency detection circuit 1, coefficient calculation circuit 9, local oscillation signal generation circuit 2, first delay compensation circuit 3, frequency conversion circuit 4, center frequency control circuit 10, filter circuit 11, second frequency detection circuit 6, second The delay compensation circuit 7 and the frequency calculation circuit 8 constitute a frequency detection circuit 100a.
　次に、図６を参照して、フィルタ回路１１の詳細な回路構成について説明する。
　周波数変換回路４の出力信号は、第１固定フィルタ回路４１及び第２固定フィルタ回路４２にそれぞれ入力される。第１固定フィルタ回路４１及び第２固定フィルタ回路４２は、いずれも通過帯域Δｆの中心周波数が固定されたＢＰＦであり、各々の中心周波数は互いに異なる値に設定されている。第１固定フィルタ回路４１及び第２固定フィルタ回路４２を通過した信号は、スイッチ回路４３に入力される。 Next, a detailed circuit configuration of the filter circuit 11 will be described with reference to FIG.
The output signal of the frequency conversion circuit 4 is input to the first fixed filter circuit 41 and the second fixed filter circuit 42, respectively. Each of the first fixed filter circuit 41 and the second fixed filter circuit 42 is a BPF in which the center frequency of the passband Δf is fixed, and the respective center frequencies are set to different values. The signal that has passed through the first fixed filter circuit 41 and the second fixed filter circuit 42 is input to the switch circuit 43.
　スイッチ回路４３は、第１固定フィルタ回路４１を通過した信号と、第２固定フィルタ回路４２を通過した信号とのいずれかを選択的に第２周波数検出回路６に出力するものである。スイッチ回路４３が出力する信号は、中心周波数制御回路１０から入力された制御信号Ｄｆにより制御される。すなわち、この場合の制御信号Ｄｆは、第１固定フィルタ回路４１及び第２固定フィルタ回路４２のうち、通過帯域Δｆの中心周波数が周波数ｆｍにより近いほうのＢＰＦを通過した信号Ｘｍを第２周波数検出回路６に出力するようにスイッチ回路４３を切替制御するものである。第１固定フィルタ回路４１、第２固定フィルタ回路４２及びスイッチ回路４３により、フィルタ回路１１が構成されている。 The switch circuit 43 selectively outputs either the signal that has passed through the first fixed filter circuit 41 or the signal that has passed through the second fixed filter circuit 42 to the second frequency detection circuit 6. Signal switching circuit 43 outputs is controlled by the control signal D f that is input from the central frequency control circuit 10. That is, the control signal D f in this case is of the first fixed filter circuit 41 and the second fixed filter circuit 42, a signal X m to the center frequency of the pass band Δf is passed through the BPF closer the frequency f m the The switch circuit 43 is controlled so as to be output to the two-frequency detection circuit 6. The first fixed filter circuit 41, the second fixed filter circuit 42, and the switch circuit 43 constitute the filter circuit 11.
　次に、図７及び図８を参照して、周波数検出回路１００ａの動作及び効果について説明する。
　図７（ａ）は、周波数検出回路１００ａに入力される入力信号Ｘｉｎの周波数スペクトルを示している。入力信号Ｘｉｎには、所望周波数成分Ａと不要周波数成分Ｂとが含まれている。 Next, the operation and effect of the frequency detection circuit 100a will be described with reference to FIGS.
FIGS. 7 (a) shows a frequency spectrum of the input signal X in inputted to the frequency detection circuit 100a. The input signal X in, are included and the unnecessary frequency component B desired frequency component A.
　図７（ａ）に示す入力信号Ｘｉｎは、所望周波数成分Ａの周波数ｆｉｎが基準周波数ｆｔｈよりも低い。この場合、第１周波数検出回路１が入力信号Ｘｉｎから検出する周波数ｆ１も、基準周波数ｆｔｈより低い値となる。係数演算回路９は、基準周波数ｆｔｈよりも高い値であり、かつ、周波数変換回路４の出力信号においてフィルタ回路１１の通過帯域Δｆ内に基準レベル以上の周波数成分が所望周波数成分Ａのみとなる値に周波数ｆｍを設定する。 In the input signal X in shown in FIG. 7A, the frequency f in of the desired frequency component A is lower than the reference frequency f th . In this case, the frequency f 1 detected by the first frequency detection circuit 1 from the input signal X in is also lower than the reference frequency f th . The coefficient calculation circuit 9 has a value higher than the reference frequency fth , and in the output signal of the frequency conversion circuit 4, the frequency component equal to or higher than the reference level is only the desired frequency component A in the pass band Δf of the filter circuit 11. setting the frequency f m to the value.
　この結果、図７（ｂ）に示す如く、第２周波数検出回路６がフィルタ回路１１の出力信号Ｘｍから検出する周波数ｆ２は、基準周波数ｆｔｈよりも高い値になる。また、フィルタ回路１１の通過帯域Δｆ内に所望周波数成分Ａ以外に基準レベル以上の周波数成分が存在しないため、所望周波数成分Ａを確実に検出することができる。 As a result, as shown in FIG. 7B, the frequency f 2 detected by the second frequency detection circuit 6 from the output signal X m of the filter circuit 11 is higher than the reference frequency f th . In addition, since there is no frequency component equal to or higher than the reference level other than the desired frequency component A in the passband Δf of the filter circuit 11, the desired frequency component A can be reliably detected.
　図８（ａ）は、周波数検出回路１００ａに入力される入力信号Ｘｉｎの周波数スペクトルを示している。入力信号Ｘｉｎには、所望周波数成分Ａと不要周波数成分Ｂとが含まれている。 FIG. 8 (a) shows the frequency spectrum of the input signal X in inputted to the frequency detection circuit 100a. The input signal X in, are included and the unnecessary frequency component B desired frequency component A.
　図８（ａ）に示す入力信号Ｘｉｎは、所望周波数成分Ａの周波数ｆｉｎが基準周波数ｆｔｈよりも高い。この場合、第１周波数検出回路１が入力信号Ｘｉｎから検出する周波数ｆ１も、基準周波数ｆｔｈより高い値になる。係数演算回路９は、基準周波数ｆｔｈよりも低い値であり、かつ、周波数変換回路４の出力信号においてフィルタ回路１１の通過帯域Δｆ内に基準レベル以上の周波数成分が所望周波数成分Ａのみとなる値に周波数ｆｍを設定する。 In the input signal X in shown in FIG. 8A, the frequency f in of the desired frequency component A is higher than the reference frequency f th . In this case, the frequency f 1 detected by the first frequency detection circuit 1 from the input signal X in is also higher than the reference frequency f th . The coefficient calculation circuit 9 has a value lower than the reference frequency fth , and in the output signal of the frequency conversion circuit 4, the frequency component equal to or higher than the reference level is only the desired frequency component A in the pass band Δf of the filter circuit 11. setting the frequency f m to the value.
　この結果、図８（ｂ）に示す如く、第２周波数検出回路６がフィルタ回路５の出力信号Ｘｍから検出する周波数ｆ２は、基準周波数ｆｔｈよりも低い値になる。また、フィルタ回路１１の通過帯域Δｆ内に所望周波数成分Ａ以外に基準レベル以上の周波数成分が存在しないため、所望周波数成分Ａを確実に検出することができる。 As a result, as shown in FIG. 8B, the frequency f 2 detected by the second frequency detection circuit 6 from the output signal X m of the filter circuit 5 becomes a value lower than the reference frequency f th . In addition, since there is no frequency component equal to or higher than the reference level other than the desired frequency component A in the passband Δf of the filter circuit 11, the desired frequency component A can be reliably detected.
　なお、フィルタ回路１１は、通過帯域Δｆの中心周波数が可変なＢＰＦであれば良く、図６に示す回路構成に限定されるものではない。例えば、図６では２個の固定フィルタ回路を設けているが、固定フィルタ回路の個数は２個以上の何個でも良い。固定フィルタ回路の個数を増やすことで、フィルタ回路１１の中心周波数をより精密に制御することができる。また、図６では固定フィルタ回路の出力にスイッチ回路４３を配置しているが、固定フィルタ回路の入力にスイッチ回路を配置したものでも良く、又は入力と出力の両方にスイッチ回路を配置したものでも良い。 The filter circuit 11 may be a BPF whose center frequency of the pass band Δf is variable, and is not limited to the circuit configuration shown in FIG. For example, although two fixed filter circuits are provided in FIG. 6, the number of fixed filter circuits may be any number of two or more. By increasing the number of fixed filter circuits, the center frequency of the filter circuit 11 can be controlled more precisely. In FIG. 6, the switch circuit 43 is disposed at the output of the fixed filter circuit. However, the switch circuit 43 may be disposed at the input of the fixed filter circuit, or the switch circuit may be disposed at both the input and output. good.
　また、図９に、フィルタ回路１１の回路構成の他の例を示す。周波数変換回路４の出力信号は、可変フィルタ回路４４に入力される。可変フィルタ回路４４は、通過帯域Δｆの中心周波数が可変なＢＰＦである。フィルタ制御回路４５は、中心周波数制御回路１０から入力された制御信号Ｄｆを用いて、可変フィルタ回路４４の中心周波数を制御するものである。可変フィルタ回路４４の制御は、電圧値又は電流値などのアナログ値による制御でも良く、デジタル値による制御でも良い。可変フィルタ回路４４及びフィルタ制御回路４５により、フィルタ回路１１が構成されている。 FIG. 9 shows another example of the circuit configuration of the filter circuit 11. The output signal of the frequency conversion circuit 4 is input to the variable filter circuit 44. The variable filter circuit 44 is a BPF in which the center frequency of the pass band Δf is variable. Filter control circuit 45 uses the control signal D f that is input from the central frequency control circuit 10, and controls the center frequency of the variable filter circuit 44. The variable filter circuit 44 may be controlled by an analog value such as a voltage value or a current value, or may be controlled by a digital value. The variable filter circuit 44 and the filter control circuit 45 constitute the filter circuit 11.
　また、フィルタ回路１１は、図９に示す可変フィルタ回路４４と同様の可変フィルタ回路を複数個配置し、この可変フィルタ回路の出力に、図６に示すスイッチ回路４３と同様のスイッチ回路を配置したものであっても良い。例えば、各々の可変フィルタ回路に中心周波数の可変範囲が異なるＢＰＦをそれぞれ用いることで、フィルタ回路１１全体の中心周波数の可変範囲を広くすることができる。 The filter circuit 11 includes a plurality of variable filter circuits similar to the variable filter circuit 44 illustrated in FIG. 9, and a switch circuit similar to the switch circuit 43 illustrated in FIG. 6 is disposed at the output of the variable filter circuit. It may be a thing. For example, the variable range of the center frequency of the entire filter circuit 11 can be widened by using BPFs having different variable ranges of the center frequency for each variable filter circuit.
　また、実施の形態１の式（１）に例示した如く、周波数演算回路８が周波数ｆｘの算出に周波数ｆｍを用いる場合、係数演算回路９が設定した周波数ｆｍを周波数演算回路８に通知する構成としても良い。 Further, as illustrated in Equation (1) in the first embodiment, if the frequency calculating circuit 8 uses a frequency f m in the calculation of the frequency f x, the frequency f m of the coefficient calculation circuit 9 is set to the frequency computing circuit 8 It is good also as a structure to notify.
　以上のように、実施の形態２の周波数検出回路１００ａは、第１周波数検出回路１の出力信号を用いて、局部発振信号生成回路２が生成する局部発振信号Ｘｐの周波数ｆｐを制御する係数演算回路９と、係数演算回路９の出力信号を用いて、フィルタ回路１１の通過帯域Δｆの中心周波数を制御する中心周波数制御回路１０と、を備える。周波数ｆｍを適切な値に設定することで、実施の形態１と同様に、検出可能な周波数範囲を確保することができ、かつ、雑音により周波数の検出精度が低下するのを防ぐことができる。 As described above, the frequency detection circuit 100 a according to the second embodiment controls the frequency f p of the local oscillation signal X p generated by the local oscillation signal generation circuit 2 using the output signal of the first frequency detection circuit 1. A coefficient calculation circuit 9 and a center frequency control circuit 10 that controls the center frequency of the pass band Δf of the filter circuit 11 using the output signal of the coefficient calculation circuit 9 are provided. By setting the frequency f m to the appropriate value, as in the first embodiment, it is possible to ensure a detectable frequency range and the detection accuracy of the frequency due to noise can be prevented from being lowered .
実施の形態３．
　図１０は、実施の形態３に係る周波数検出回路１００ｂの要部を示す回路構成図である。図１０を参照して、図１に示す周波数変換回路４、フィルタ回路５及び第２周波数検出回路６に代えて、周波数変換機能を有する第２周波数検出回路１２を設けた周波数検出回路１００ｂについて説明する。なお、図１０において、図１に示す実施の形態１の周波数検出回路１００と同様の回路には同一符号を付して説明を省略する。 Embodiment 3 FIG.
FIG. 10 is a circuit configuration diagram showing a main part of the frequency detection circuit 100b according to the third embodiment. With reference to FIG. 10, a frequency detection circuit 100b provided with a second frequency detection circuit 12 having a frequency conversion function instead of the frequency conversion circuit 4, the filter circuit 5 and the second frequency detection circuit 6 shown in FIG. To do. In FIG. 10, the same reference numerals are given to the same circuits as those of the frequency detection circuit 100 according to the first embodiment shown in FIG.
　局部発振信号生成回路２は、周波数ｆ１から周波数ｆｍへの周波数変換用の局部発振信号Ｘｐを生成するものである。周波数ｆｍは、第１フィルタ回路５４及び第２フィルタ回路５５の通過帯域Δｆ内の値に設定されており、例えば通過帯域Δｆの中心周波数と同等の値に設定されている。局部発振信号生成回路２は、生成した局部発振信号Ｘｐを９０度移相回路５１に出力するものである。 Local oscillation signal generating circuit 2 is for generating a local oscillation signal X p for frequency conversion from the frequency f 1 to frequency f m. Frequency f m is set to the center frequency equal to the values of the first set to a value within the passband Delta] f of the filter circuit 54 and the second filter circuit 55 is, for example, passband Delta] f. Local oscillation signal generating circuit 2, and outputs the generated local oscillation signal X p in 90-degree phase shifting circuit 51.
　９０度移相回路５１は、局部発振信号Ｘｐと同じ周波数であり、かつ、互いに９０度の位相差を有する第１局部発振信号及び第２局部発振信号を生成するものである。９０度移相回路５１は、生成した第１局部発振信号を第１周波数変換回路５２に出力し、第２局部発振信号を第２周波数変換回路５３に出力するものである。 90 degree phase shifting circuit 51 is the same frequency as the local oscillation signal X p, and is for generating a first local oscillation signal and the second local oscillation signal having a phase difference of 90 degrees from each other. The 90-degree phase shift circuit 51 outputs the generated first local oscillation signal to the first frequency conversion circuit 52 and outputs the second local oscillation signal to the second frequency conversion circuit 53.
　第１遅延補償回路３は、時間シフトのシフト量が、第１周波数検出回路１、局部発振信号生成回路２及び９０度移相回路５１により生じる遅延時間に応じた値に設定されている。すなわち、第１遅延補償回路３は、入力信号Ｘｉｎに対し、第１周波数検出回路１、局部発振信号生成回路２及び９０度移相回路５１による遅延を補償するものである。第１遅延補償回路３は、時間シフトした入力信号Ｘｉｎを第１周波数変換回路５２及び第２周波数変換回路５３に出力するものである。 In the first delay compensation circuit 3, the shift amount of the time shift is set to a value corresponding to the delay time generated by the first frequency detection circuit 1, the local oscillation signal generation circuit 2, and the 90 ° phase shift circuit 51. That is, the first delay compensation circuit 3, the input signal X in, is to compensate for the delay by the first frequency detecting circuit 1, the local oscillation signal generating circuit 2 and the 90-degree phase shifting circuit 51. The first delay compensation circuit 3 outputs the time-shifted input signal Xin to the first frequency conversion circuit 52 and the second frequency conversion circuit 53.
　第１周波数変換回路５２は、図１に示す周波数変換回路４と同様のミキサにより構成されており、９０度移相回路５１が出力した第１局部発振信号を用いて、第１遅延補償回路３が時間シフトした入力信号Ｘｉｎを周波数変換するものである。第１周波数変換回路５２は、周波数変換した入力信号Ｘｉｎを第１フィルタ回路５４に出力するものである。すなわち、第１周波数変換回路５２の出力信号は、入力信号Ｘｉｎの周波数成分と第１局部発振信号の周波数成分とをミキサにより混合したものである。 The first frequency conversion circuit 52 is configured by a mixer similar to the frequency conversion circuit 4 shown in FIG. 1, and uses the first local oscillation signal output from the 90-degree phase shift circuit 51 to generate the first delay compensation circuit 3. There is for frequency converting an input signal X in shifted time. The first frequency conversion circuit 52 outputs the frequency-converted input signal Xin to the first filter circuit 54. That is, the output signal of the first frequency converting circuit 52, a frequency component of the frequency component and the first local oscillation signal of the input signal X in is obtained by mixing by the mixer.
　第２周波数変換回路５３は、図１に示す周波数変換回路４と同様のミキサにより構成されており、９０度移相回路５１が出力した第２局部発振信号を用いて、第１遅延補償回路３が時間シフトした入力信号Ｘｉｎを周波数変換するものである。第２周波数変換回路５３は、周波数変換した入力信号Ｘｉｎを第２フィルタ回路５５に出力するものである。すなわち、第２周波数変換回路５３の出力信号は、入力信号Ｘｉｎの周波数成分と第２局部発振信号の周波数成分とをミキサにより混合したものである。 The second frequency conversion circuit 53 is configured by a mixer similar to the frequency conversion circuit 4 shown in FIG. 1, and uses the second local oscillation signal output from the 90-degree phase shift circuit 51, and uses the first delay compensation circuit 3. There is for frequency converting an input signal X in shifted time. The second frequency conversion circuit 53 outputs the frequency-converted input signal Xin to the second filter circuit 55. That is, the output signal of the second frequency converting circuit 53, a frequency component of the frequency component and the second local oscillation signal of the input signal X in is obtained by mixing by the mixer.
　第１フィルタ回路５４は、図１に示すフィルタ回路５と同様のＢＰＦであり、通過帯域Δｆの幅及び中心周波数の値が固定されている。第１フィルタ回路５４は、第１周波数変換回路５２の出力信号のうち通過帯域Δｆ外の周波数成分を抑制し、通過帯域Δｆ内の周波数成分を含む信号を位相演算回路５６に出力するものである。 The first filter circuit 54 is a BPF similar to the filter circuit 5 shown in FIG. 1, and the width of the passband Δf and the value of the center frequency are fixed. The first filter circuit 54 suppresses a frequency component outside the pass band Δf in the output signal of the first frequency conversion circuit 52 and outputs a signal including the frequency component within the pass band Δf to the phase calculation circuit 56. .
　第２フィルタ回路５５は、図１に示すフィルタ回路５と同様のＢＰＦであり、通過帯域Δｆの幅及び中心周波数の値が固定されている。第２フィルタ回路５５は、第２周波数変換回路５３の出力信号のうち通過帯域Δｆ外の周波数成分を抑制し、通過帯域Δｆ内の周波数成分を含む信号を位相演算回路５６に出力するものである。 The second filter circuit 55 is a BPF similar to the filter circuit 5 shown in FIG. 1, and the width of the passband Δf and the value of the center frequency are fixed. The second filter circuit 55 suppresses frequency components outside the pass band Δf in the output signal of the second frequency conversion circuit 53 and outputs a signal including the frequency components within the pass band Δf to the phase calculation circuit 56. .
　位相演算回路５６は、第１フィルタ回路５４の出力信号と第２フィルタ回路５５の出力信号とを用いて、第１周波数変換回路５２及び第２周波数変換回路５３により周波数変換された入力信号Ｘｉｎの位相を算出するものである。位相演算回路５６は、算出した位相を示す信号を位相周波数変換回路５７に出力するものである。 The phase calculation circuit 56 uses the output signal of the first filter circuit 54 and the output signal of the second filter circuit 55 to input the input signal X in that has been frequency converted by the first frequency conversion circuit 52 and the second frequency conversion circuit 53. Is calculated. The phase calculation circuit 56 outputs a signal indicating the calculated phase to the phase frequency conversion circuit 57.
　位相周波数変換回路５７は、位相演算回路５６の出力信号が示す位相を周波数に変換するものである。位相周波数変換回路５７は、変換した周波数ｆ２を示す信号を周波数演算回路８に出力するものである。 The phase frequency conversion circuit 57 converts the phase indicated by the output signal of the phase calculation circuit 56 into a frequency. The phase frequency conversion circuit 57 outputs a signal indicating the converted frequency f 2 to the frequency calculation circuit 8.
　９０度移相回路５１、第１周波数変換回路５２、第２周波数変換回路５３、第１フィルタ回路５４、第２フィルタ回路５５、位相演算回路５６及び位相周波数変換回路５７により、第２周波数検出回路１２が構成されている。 The second frequency detection circuit includes a 90-degree phase shift circuit 51, a first frequency conversion circuit 52, a second frequency conversion circuit 53, a first filter circuit 54, a second filter circuit 55, a phase calculation circuit 56, and a phase frequency conversion circuit 57. 12 is configured.
　第２遅延補償回路７は、時間シフトのシフト量が、局部発振信号生成回路２及び第２周波数検出回路１２により生じる遅延時間に応じた値に設定されている。すなわち、第２遅延補償回路７は、第１周波数検出回路１の出力信号に対し、局部発振信号生成回路２及び第２周波数検出回路１２による遅延を補償して周波数演算回路８に出力するものである。 In the second delay compensation circuit 7, the shift amount of the time shift is set to a value corresponding to the delay time generated by the local oscillation signal generation circuit 2 and the second frequency detection circuit 12. That is, the second delay compensation circuit 7 compensates for the delay caused by the local oscillation signal generation circuit 2 and the second frequency detection circuit 12 with respect to the output signal of the first frequency detection circuit 1 and outputs it to the frequency calculation circuit 8. is there.
　第１周波数検出回路１、局部発振信号生成回路２、第１遅延補償回路３、第２周波数検出回路１２、第２遅延補償回路７及び周波数演算回路８により、周波数検出回路１００ｂが構成されている。 The first frequency detection circuit 1, the local oscillation signal generation circuit 2, the first delay compensation circuit 3, the second frequency detection circuit 12, the second delay compensation circuit 7, and the frequency calculation circuit 8 constitute a frequency detection circuit 100b. .
　周波数検出回路１００ｂは、実施の形態１の周波数検出回路１００と同様に、周波数演算回路８の算出する周波数ｆｘが周波数ｆｉｎと同じ値になる。すなわち、周波数検出回路１００ｂは、雑音により周波数の検出精度が低下するのを防ぐことができる。 Frequency detection circuit 100b, similarly to the frequency detecting circuit 100 of the first embodiment, the frequency f x for calculating the frequency computing circuit 8 becomes equal to the frequency f in. That is, the frequency detection circuit 100b can prevent the frequency detection accuracy from being lowered due to noise.
　また、周波数検出回路１００ｂは、第１周波数変換回路５２及び第２周波数変換回路５３により、第１周波数検出回路１の検出結果に基づいて所望周波数成分Ａが通過帯域Δｆ内に含まれるように入力信号Ｘｉｎを周波数変換してから第１フィルタ回路５４及び第２フィルタ回路５５にそれぞれ出力する。このため、第１フィルタ回路５４及び第２フィルタ回路５５に通過帯域Δｆ幅の狭いＢＰＦを用いた場合でも所望周波数成分Ａの周波数を確実に検出することができ、実施の形態１と同様に周波数の検出範囲を確保することができる。 Further, the frequency detection circuit 100b is input by the first frequency conversion circuit 52 and the second frequency conversion circuit 53 so that the desired frequency component A is included in the passband Δf based on the detection result of the first frequency detection circuit 1. The signal X in is frequency converted and then output to the first filter circuit 54 and the second filter circuit 55, respectively. Therefore, even when a BPF having a narrow passband Δf width is used for the first filter circuit 54 and the second filter circuit 55, the frequency of the desired frequency component A can be reliably detected, and the frequency is the same as in the first embodiment. Can be ensured.
　また、図１に示す周波数検出回路１００は、周波数変換回路４、フィルタ回路５及び第２周波数検出回路６をそれぞれ独立した３個の回路で構成していた。これに対し、図１０に示す周波数検出回路１００ｂは、第２周波数検出回路１２が周波数変換機能を有するため、図１に示す周波数変換回路４及びフィルタ回路５のような第２周波数検出回路１２と別体の周波数変換回路及びフィルタ回路が不要である。この結果、周波数検出回路１００ｂを構成する回路の個数を削減し、周波数検出回路１００ｂ全体を小型にするとともに、コストを低減し、かつ、消費電力を低減することができる。 Further, in the frequency detection circuit 100 shown in FIG. 1, the frequency conversion circuit 4, the filter circuit 5, and the second frequency detection circuit 6 are each constituted by three independent circuits. On the other hand, the frequency detection circuit 100b shown in FIG. 10 includes the second frequency detection circuit 12 such as the frequency conversion circuit 4 and the filter circuit 5 shown in FIG. Separate frequency conversion circuits and filter circuits are unnecessary. As a result, the number of circuits constituting the frequency detection circuit 100b can be reduced, the entire frequency detection circuit 100b can be reduced in size, the cost can be reduced, and the power consumption can be reduced.
　以上のように、実施の形態３の周波数検出回路１００ｂは、入力信号Ｘｉｎから周波数を検出し、検出した周波数ｆ１を示す信号を出力する第１周波数検出回路１と、第１周波数検出回路１の出力信号が示す周波数ｆ１から第１フィルタ回路５４及び第２フィルタ回路５５の通過帯域Δｆ内の周波数ｆｍへの周波数変換用の局部発振信号Ｘｐを生成する局部発振信号生成回路２と、局部発振信号Ｘｐから互いに９０度の位相差を有する第１局部発振信号及び第２局部発振信号を生成する９０度移相回路５１と、第１局部発振信号を用いて入力信号Ｘｉｎを周波数変換し、第１フィルタ回路５４に出力する第１周波数変換回路５２と、第２局部発振信号を用いて入力信号Ｘｉｎを周波数変換し、第２フィルタ回路５５に出力する第２周波数変換回路５３と、第１フィルタ回路５４の出力信号及び第２フィルタ回路５５の出力信号を用いて、入力信号Ｘｉｎの位相を算出する位相演算回路５６と、位相演算回路５６が算出した位相を周波数に変換し、変換した周波数ｆ２を示す信号を出力する位相周波数変換回路５７と、を有する第２周波数検出回路１２と、第１周波数検出回路１の出力信号が示す周波数ｆ１と、位相周波数変換回路５７の出力信号が示す周波数ｆ２とを用いて、入力信号Ｘｉｎの周波数ｆｘを算出する周波数演算回路８と、を備える。これにより、実施の形態１と同様に、検出可能な周波数範囲を確保することができ、かつ、雑音により周波数の検出精度が低下するのを防ぐことができる。また、第２周波数検出回路１２が周波数変換機能を有するため、第２周波数検出回路１２と別体の周波数変換回路及びフィルタ回路を不要として、周波数検出回路１００ｂ全体の小型化、低コス化及び低消費電力化を図ることができる。 As described above, the frequency detecting circuit 100b of the third embodiment detects the frequency of the input signal X in, the first frequency detecting circuit 1 outputs a signal indicating the frequency f 1 detected, the first frequency detecting circuit local oscillation signal generating circuit 2 for generating a local oscillation signal X p for frequency conversion from the frequency f 1 of the first output signal indicates to the frequency f m in the pass band Δf of the first filter circuit 54 and the second filter circuit 55 When the local oscillation signal X 90 degree phase shift circuit 51 for generating a first local oscillation signal and the second local oscillation signal having a phase difference of 90 degrees from each other from p, the input signal X in by using a first local oscillation signal The first frequency converting circuit 52 that converts the frequency of the input signal X in using the second local oscillation signal and the second frequency that is output to the second filter circuit 55 Using the conversion circuit 53, the output signal of the first filter circuit 54 and the output signal of the second filter circuit 55, a phase calculation circuit 56 for calculating the phase of the input signal Xin , and the phase calculated by the phase calculation circuit 56 A second frequency detection circuit 12 having a phase frequency conversion circuit 57 for converting to a frequency and outputting a signal indicating the converted frequency f 2 ; a frequency f 1 indicated by an output signal of the first frequency detection circuit 1; and a phase comprising using a frequency f 2 showing the output signal of the frequency converting circuit 57, a frequency computing circuit 8 for calculating the frequency f x of the input signal X in, the. As a result, as in the first embodiment, a detectable frequency range can be ensured, and the frequency detection accuracy can be prevented from being reduced by noise. Further, since the second frequency detection circuit 12 has a frequency conversion function, the frequency conversion circuit and the filter circuit that are separate from the second frequency detection circuit 12 are not required, and the entire frequency detection circuit 100b can be reduced in size, cost, and cost. Power consumption can be reduced.
実施の形態４．
　図１１は、実施の形態４に係る周波数検出回路１００ｃの要部を示す回路構成図である。図１１を参照して、図５に示す周波数変換回路４、フィルタ回路１１及び第２周波数検出回路６に代えて、周波数変換機能を有する第２周波数検出回路１３を設けた周波数検出回路１００ｃについて説明する。なお、図１１において、図５に示す実施の形態２の周波数検出回路１００ａと同様の構成部材には同一符号を付して説明を省略する。 Embodiment 4 FIG.
FIG. 11 is a circuit configuration diagram showing a main part of the frequency detection circuit 100c according to the fourth embodiment. Referring to FIG. 11, a frequency detection circuit 100c provided with a second frequency detection circuit 13 having a frequency conversion function in place of the frequency conversion circuit 4, the filter circuit 11, and the second frequency detection circuit 6 shown in FIG. To do. In FIG. 11, the same components as those of the frequency detection circuit 100a according to the second embodiment shown in FIG.
　局部発振信号生成回路２は、第１周波数検出回路１の出力信号が示す周波数ｆ１と、係数演算回路９の出力信号が示す周波数ｆｍとを用いて局部発振信号Ｘｐを生成するものである。局部発振信号生成回路２は、生成した局部発振信号Ｘｐを９０度移相回路５１に出力するものである。 Local oscillation signal generating circuit 2 is for generating a local oscillation signal X p using the frequency f 1 indicated by the output signal of the first frequency detecting circuit 1, a frequency f m indicated by the output signal of the coefficient calculation circuit 9 is there. Local oscillation signal generating circuit 2, and outputs the generated local oscillation signal X p in 90-degree phase shifting circuit 51.
　９０度移相回路５１は、局部発振信号Ｘｐと同じ周波数であり、かつ、互いに９０度の位相差を有する第１局部発振信号及び第２局部発振信号を生成するものである。９０度移相回路５１は、生成した第１局部発振信号を第１周波数変換回路５２に出力し、第２局部発振信号を第２周波数変換回路５３に出力するものである。 90 degree phase shifting circuit 51 is the same frequency as the local oscillation signal X p, and is for generating a first local oscillation signal and the second local oscillation signal having a phase difference of 90 degrees from each other. The 90-degree phase shift circuit 51 outputs the generated first local oscillation signal to the first frequency conversion circuit 52 and outputs the second local oscillation signal to the second frequency conversion circuit 53.
　第１遅延補償回路３は、時間シフトのシフト量が、第１周波数検出回路１、係数演算回路９、局部発振信号生成回路２及び９０度移相回路５１により生じる遅延時間に応じた値に設定されている。すなわち、第１遅延補償回路３は、入力信号Ｘｉｎに対し、第１周波数検出回路１、係数演算回路９、局部発振信号生成回路２及び９０度移相回路５１による遅延を補償して第１周波数変換回路５２及び第２周波数変換回路５３に出力するものである。 In the first delay compensation circuit 3, the shift amount of the time shift is set to a value corresponding to the delay time generated by the first frequency detection circuit 1, the coefficient calculation circuit 9, the local oscillation signal generation circuit 2, and the 90-degree phase shift circuit 51. Has been. That is, the first delay compensation circuit 3, the input signal X in the first frequency detecting circuit 1, the coefficient calculation circuit 9, to compensate for the delay by the local oscillation signal generating circuit 2 and the 90-degree phase shifting circuit 51 first This is output to the frequency conversion circuit 52 and the second frequency conversion circuit 53.
　第１周波数変換回路５２は、図５に示す周波数変換回路４と同様のミキサにより構成されており、９０度移相回路５１が出力した第１局部発振信号を用いて、第１遅延補償回路３が時間シフトした入力信号Ｘｉｎを周波数変換し、第１フィルタ回路６１に出力するものである。第２周波数変換回路５３は、図５に示す周波数変換回路４と同様のミキサにより構成されており、９０度移相回路５１が出力した第２局部発振信号を用いて、第１遅延補償回路３が時間シフトした入力信号Ｘｉｎを周波数変換し、第２フィルタ回路６２に出力するものである。 The first frequency conversion circuit 52 is configured by a mixer similar to the frequency conversion circuit 4 shown in FIG. 5, and uses the first local oscillation signal output from the 90-degree phase shift circuit 51, and uses the first delay compensation circuit 3. The frequency of the time-shifted input signal Xin is converted and output to the first filter circuit 61. The second frequency conversion circuit 53 is configured by a mixer similar to the frequency conversion circuit 4 shown in FIG. 5, and uses the second local oscillation signal output from the 90-degree phase shift circuit 51 to generate the first delay compensation circuit 3. The frequency of the time-shifted input signal Xin is converted and output to the second filter circuit 62.
　第１フィルタ回路６１は、図５に示すフィルタ回路１１と同様のＢＰＦであり、通過帯域Δｆの中心周波数が可変である。通過帯域Δｆの中心周波数は、中心周波数制御回路１０が出力した制御信号Ｄｆにより制御される。第１フィルタ回路６１は、第１周波数変換回路５２の出力信号のうち通過帯域Δｆ外の周波数成分を抑制し、通過帯域Δｆ内の周波数成分を含む信号を位相演算回路５６に出力するものである。 The first filter circuit 61 is a BPF similar to the filter circuit 11 shown in FIG. 5, and the center frequency of the pass band Δf is variable. The center frequency of the pass band Δf is controlled by the control signal D f output from the center frequency control circuit 10. The first filter circuit 61 suppresses frequency components outside the pass band Δf in the output signal of the first frequency conversion circuit 52 and outputs a signal including the frequency components within the pass band Δf to the phase calculation circuit 56. .
　第２フィルタ回路６２は、図５に示すフィルタ回路１１と同様のＢＰＦであり、通過帯域Δｆの中心周波数が可変である。通過帯域Δｆの中心周波数は、中心周波数制御回路１０が出力した制御信号Ｄｆにより制御される。第２フィルタ回路６２は、第２周波数変換回路５３の出力信号のうち通過帯域Δｆ外の周波数成分を抑制し、通過帯域Δｆ内の周波数成分を含む信号を位相演算回路５６に出力するものである。 The second filter circuit 62 is a BPF similar to the filter circuit 11 shown in FIG. 5, and the center frequency of the pass band Δf is variable. The center frequency of the pass band Δf is controlled by the control signal D f output from the center frequency control circuit 10. The second filter circuit 62 suppresses the frequency component outside the pass band Δf in the output signal of the second frequency conversion circuit 53 and outputs a signal including the frequency component within the pass band Δf to the phase calculation circuit 56. .
　位相演算回路５６は、第１フィルタ回路５４の出力信号と第２フィルタ回路５５の出力信号とを用いて、第１周波数変換回路５２及び第２周波数変換回路５３により周波数変換された入力信号Ｘｉｎの位相を算出するものである。位相演算回路５６は、算出した位相を示す信号を位相周波数変換回路５７に出力するものである。 The phase calculation circuit 56 uses the output signal of the first filter circuit 54 and the output signal of the second filter circuit 55 to input the input signal X in that has been frequency converted by the first frequency conversion circuit 52 and the second frequency conversion circuit 53. Is calculated. The phase calculation circuit 56 outputs a signal indicating the calculated phase to the phase frequency conversion circuit 57.
　位相周波数変換回路５７は、位相演算回路５６の出力信号が示す位相を周波数に変換するものである。位相周波数変換回路５７は、変換した周波数ｆ２を示す信号を周波数演算回路８に出力するものである。 The phase frequency conversion circuit 57 converts the phase indicated by the output signal of the phase calculation circuit 56 into a frequency. The phase frequency conversion circuit 57 outputs a signal indicating the converted frequency f 2 to the frequency calculation circuit 8.
　９０度移相回路５１、第１周波数変換回路５２、第２周波数変換回路５３、第１フィルタ回路６１、第２フィルタ回路６２、位相演算回路５６及び位相周波数変換回路５７により、第２周波数検出回路１３が構成されている。 The second frequency detection circuit includes a 90-degree phase shift circuit 51, a first frequency conversion circuit 52, a second frequency conversion circuit 53, a first filter circuit 61, a second filter circuit 62, a phase calculation circuit 56, and a phase frequency conversion circuit 57. 13 is configured.
　第２遅延補償回路７は、時間シフトのシフト量が、係数演算回路９、局部発振信号生成回路２、中心周波数制御回路１０及び第２周波数検出回路１３により生じる遅延時間に応じた値に設定されている。すなわち、第２遅延補償回路７は、第１周波数検出回路１の出力信号に対し、係数演算回路９、局部発振信号生成回路２、中心周波数制御回路１０及び第２周波数検出回路１３による遅延を補償して周波数演算回路８に出力するものである。 In the second delay compensation circuit 7, the shift amount of the time shift is set to a value corresponding to the delay time generated by the coefficient calculation circuit 9, the local oscillation signal generation circuit 2, the center frequency control circuit 10 and the second frequency detection circuit 13. ing. That is, the second delay compensation circuit 7 compensates for delays caused by the coefficient calculation circuit 9, the local oscillation signal generation circuit 2, the center frequency control circuit 10, and the second frequency detection circuit 13 with respect to the output signal of the first frequency detection circuit 1. And output to the frequency calculation circuit 8.
　第１周波数検出回路１、局部発振信号生成回路２、第１遅延補償回路３、第２周波数検出回路１３、第２遅延補償回路７及び周波数演算回路８により、周波数検出回路１００ｃが構成されている。 The first frequency detection circuit 1, the local oscillation signal generation circuit 2, the first delay compensation circuit 3, the second frequency detection circuit 13, the second delay compensation circuit 7, and the frequency calculation circuit 8 constitute a frequency detection circuit 100c. .
　周波数検出回路１００ｃは、周波数ｆｍを実施の形態２と同様の適切な値に設定することで、実施の形態３の周波数検出回路１００ｂと同様に、雑音により周波数の検出精度が低下するのを防ぐことができる。また、周波数の検出範囲を確保することができる。 Frequency detection circuit 100c, by setting the frequency f m in the same suitable value in the second embodiment, similarly to the frequency detecting circuit 100b of the third embodiment, that the detection accuracy of the frequency is lowered by noise Can be prevented. In addition, a frequency detection range can be ensured.
　また、図５に示す周波数検出回路１００ａは、周波数変換回路４、フィルタ回路１１及び第２周波数検出回路６をそれぞれ独立した３個の回路で構成していた。これに対し、図１１に示す周波数検出回路１００ｃは、第２周波数検出回路１３が周波数変換機能を有するため、図５に示す周波数変換回路４及びフィルタ回路１１のような第２周波数検出回路１３と別体の周波数変換回路及びフィルタ回路が不要である。この結果、周波数検出回路１００ｃを構成する回路の個数を削減し、周波数検出回路１００ｃ全体を小型にするとともに、コストを低減し、かつ、消費電力を低減することができる。 Further, in the frequency detection circuit 100a shown in FIG. 5, the frequency conversion circuit 4, the filter circuit 11, and the second frequency detection circuit 6 are each constituted by three independent circuits. On the other hand, since the second frequency detection circuit 13 has a frequency conversion function, the frequency detection circuit 100c shown in FIG. 11 is different from the second frequency detection circuit 13 such as the frequency conversion circuit 4 and the filter circuit 11 shown in FIG. Separate frequency conversion circuits and filter circuits are unnecessary. As a result, the number of circuits constituting the frequency detection circuit 100c can be reduced, the entire frequency detection circuit 100c can be reduced in size, the cost can be reduced, and the power consumption can be reduced.
　以上のように、実施の形態４の周波数検出回路１００ｃは、第１周波数検出回路１の出力信号を用いて、局部発振信号生成回路２が生成する局部発振信号Ｘｐの周波数ｆｐを制御する係数演算回路９と、係数演算回路９の出力信号を用いて、第１フィルタ回路６１及び第２フィルタ回路６２の通過帯域Δｆの中心周波数を制御する中心周波数制御回路１０と、を備える。周波数ｆｍを実施の形態２と同様の適切な値に設定することで、検出可能な周波数範囲を確保することができ、かつ、雑音により周波数の検出精度が低下するのを防ぐことができる。また、第２周波数検出回路１３が周波数変換機能を有するため、第２周波数検出回路１３と別体の周波数変換回路及びフィルタ回路を不要として、周波数検出回路１００ｃ全体の小型化、低コスト化及び低消費電力化を図ることができる。 As described above, the frequency detection circuit 100c of the fourth embodiment, by using the first output signal of the frequency detection circuit 1, the local oscillation signal generating circuit 2 controls the frequency f p of the local oscillation signal X p is generated A coefficient calculation circuit 9 and a center frequency control circuit 10 that controls the center frequency of the pass band Δf of the first filter circuit 61 and the second filter circuit 62 using the output signal of the coefficient calculation circuit 9 are provided. By setting the frequency f m in the same suitable value in the second embodiment, it is possible to ensure a detectable frequency range and the detection accuracy of the frequency due to noise can be prevented from being lowered. Further, since the second frequency detection circuit 13 has a frequency conversion function, a frequency conversion circuit and a filter circuit that are separate from the second frequency detection circuit 13 are not required, and the entire frequency detection circuit 100c can be reduced in size, cost, and cost. Power consumption can be reduced.
　なお、本願発明はその発明の範囲内において、各実施の形態の自由な組み合わせ、あるいは各実施の形態の任意の構成要素の変形、もしくは各実施の形態において任意の構成要素の省略が可能である。 In the present invention, within the scope of the invention, any combination of the embodiments, or any modification of any component in each embodiment, or omission of any component in each embodiment is possible. .
　本発明の周波数検出回路は、レーダ装置、テレビ放送又はラジオ放送用の受信装置、通信機器及び信号計測装置などに用いることができる。 The frequency detection circuit of the present invention can be used in a radar device, a receiving device for television broadcasting or radio broadcasting, a communication device, a signal measuring device, and the like.
　１　第１周波数検出回路、２　局部発振信号生成回路、３　第１遅延補償回路、４　周波数変換回路、５　フィルタ回路、６　第２周波数検出回路、７　第２遅延補償回路、８　周波数演算回路、９　係数演算回路、１０　中心周波数制御回路、１１　フィルタ回路、１２　第２周波数検出回路、１３　第２周波数検出回路、２１　演算回路、２２　位相積算回路、２３　位相振幅変換回路、２４　デジタルアナログ変換回路、２５　ＣＷ生成回路、３１　分周数演算回路、３２　可変分周回路、３３　基準信号回路、３４　位相比較回路、３５　ループフィルタ回路、３６　発振回路、３７　ＣＷ生成回路、４１　第１固定フィルタ回路、４２　第２固定フィルタ回路、４３　スイッチ回路、４４　可変フィルタ回路、４５　フィルタ制御回路、５１　９０度移相回路、５２　第１周波数変換回路、５３　第２周波数変換回路、５４　第１フィルタ回路、５５　第２フィルタ回路、５６　位相演算回路、５７　位相周波数変換回路、６１　第１フィルタ回路、６２　第２フィルタ回路、１００，１００ａ，１００ｂ，１００ｃ　周波数検出回路。 1 First frequency detection circuit, 2 Local oscillation signal generation circuit, 3 First delay compensation circuit, 4 Frequency conversion circuit, 5 Filter circuit, 6 Second frequency detection circuit, 7 Second delay compensation circuit, 8 Frequency calculation circuit, 9 Coefficient calculation circuit, 10 center frequency control circuit, 11 filter circuit, 12 second frequency detection circuit, 13 second frequency detection circuit, 21 calculation circuit, 22 phase integration circuit, 23 phase amplitude conversion circuit, 24 digital analog conversion circuit, 25 CW generation circuit, 31 frequency division calculation circuit, 32 variable frequency division circuit, 33 reference signal circuit, 34 phase comparison circuit, 35 loop filter circuit, 36 oscillation circuit, 37 CW generation circuit, 41 first fixed filter circuit, 42nd 2 fixed filter circuit, 43 switch circuit, 44 variable filter circuit, 45 filter system Circuit, 51 90 degree phase shift circuit, 52 first frequency conversion circuit, 53 second frequency conversion circuit, 54 first filter circuit, 55 second filter circuit, 56 phase arithmetic circuit, 57 phase frequency conversion circuit, 61 first filter Circuit, 62 second filter circuit, 100, 100a, 100b, 100c frequency detection circuit.

Claims (8)

  1. 　入力信号から周波数を検出し、検出した周波数を示す信号を出力する第１周波数検出回路と、
    　前記第１周波数検出回路の出力信号が示す周波数からフィルタ回路の通過帯域内の周波数への周波数変換用の局部発振信号を生成する局部発振信号生成回路と、
    　前記局部発振信号を用いて前記入力信号を周波数変換し、前記フィルタ回路に出力する周波数変換回路と、
    　前記フィルタ回路の出力信号から周波数を検出し、検出した周波数を示す信号を出力する第２周波数検出回路と、
    　前記第１周波数検出回路の出力信号が示す周波数と、前記第２周波数検出回路の出力信号が示す周波数とを用いて、前記入力信号の周波数を算出する周波数演算回路と、
    　を備える周波数検出回路。     A first frequency detection circuit that detects a frequency from an input signal and outputs a signal indicating the detected frequency;
    A local oscillation signal generation circuit for generating a local oscillation signal for frequency conversion from a frequency indicated by an output signal of the first frequency detection circuit to a frequency within a pass band of the filter circuit;
    A frequency conversion circuit that converts the frequency of the input signal using the local oscillation signal and outputs the frequency to the filter circuit;
    A second frequency detection circuit that detects a frequency from the output signal of the filter circuit and outputs a signal indicating the detected frequency;
    A frequency calculation circuit that calculates the frequency of the input signal using the frequency indicated by the output signal of the first frequency detection circuit and the frequency indicated by the output signal of the second frequency detection circuit;
    A frequency detection circuit comprising:
  2. 　前記入力信号に対し、前記第１周波数検出回路及び前記局部発振信号生成回路による遅延を補償して前記周波数変換回路に出力する第１遅延補償回路と、
    　前記第１周波数検出回路の出力信号に対し、前記局部発振信号生成回路、前記周波数変換回路、前記フィルタ回路及び前記第２周波数検出回路による遅延を補償して前記周波数演算回路に出力する第２遅延補償回路と、
    　を備えることを特徴とする請求項１記載の周波数検出回路。     A first delay compensation circuit that compensates for a delay caused by the first frequency detection circuit and the local oscillation signal generation circuit and outputs the input signal to the frequency conversion circuit;
    A second delay that compensates for a delay caused by the local oscillation signal generation circuit, the frequency conversion circuit, the filter circuit, and the second frequency detection circuit with respect to an output signal of the first frequency detection circuit and outputs the signal to the frequency calculation circuit A compensation circuit;
    The frequency detection circuit according to claim 1, further comprising:
  3. 　前記第１周波数検出回路の出力信号を用いて、前記局部発振信号生成回路が生成する前記局部発振信号の周波数を制御する係数演算回路と、
    　前記係数演算回路の出力信号を用いて、前記フィルタ回路の前記通過帯域の中心周波数を制御する中心周波数制御回路と、
    　を備えることを特徴とする請求項１記載の周波数検出回路。     A coefficient calculation circuit for controlling the frequency of the local oscillation signal generated by the local oscillation signal generation circuit using the output signal of the first frequency detection circuit;
    A center frequency control circuit for controlling a center frequency of the passband of the filter circuit using an output signal of the coefficient arithmetic circuit;
    The frequency detection circuit according to claim 1, further comprising:
  4. 　前記入力信号に対し、前記第１周波数検出回路、前記係数演算回路及び前記局部発振信号生成回路による遅延を補償して前記周波数変換回路に出力する第１遅延補償回路と、
    　前記第１周波数検出回路の出力信号に対し、前記係数演算回路、前記局部発振信号生成回路、前記周波数変換回路、前記中心周波数制御回路、前記フィルタ回路及び前記第２周波数検出回路による遅延を補償して前記周波数演算回路に出力する第２遅延補償回路と、
    　を備えることを特徴とする請求項３記載の周波数検出回路。     A first delay compensation circuit that compensates for a delay caused by the first frequency detection circuit, the coefficient calculation circuit, and the local oscillation signal generation circuit and outputs the input signal to the frequency conversion circuit;
    The output signal of the first frequency detection circuit is compensated for delay caused by the coefficient calculation circuit, the local oscillation signal generation circuit, the frequency conversion circuit, the center frequency control circuit, the filter circuit, and the second frequency detection circuit. A second delay compensation circuit that outputs to the frequency arithmetic circuit;
    The frequency detection circuit according to claim 3, further comprising:
  5. 　入力信号から周波数を検出し、検出した周波数を示す信号を出力する第１周波数検出回路と、
    　前記第１周波数検出回路の出力信号が示す周波数から第１フィルタ回路及び第２フィルタ回路の通過帯域内の周波数への周波数変換用の局部発振信号を生成する局部発振信号生成回路と、
    　前記局部発振信号から互いに９０度の位相差を有する第１局部発振信号及び第２局部発振信号を生成する９０度移相回路と、前記第１局部発振信号を用いて前記入力信号を周波数変換し、前記第１フィルタ回路に出力する第１周波数変換回路と、前記第２局部発振信号を用いて前記入力信号を周波数変換し、前記第２フィルタ回路に出力する第２周波数変換回路と、前記第１フィルタ回路の出力信号及び前記第２フィルタ回路の出力信号を用いて前記入力信号の位相を算出する位相演算回路と、前記位相演算回路が算出した位相を周波数に変換し、変換した周波数を示す信号を出力する位相周波数変換回路と、を有する第２周波数検出回路と、
    　前記第１周波数検出回路の出力信号が示す周波数と、前記位相周波数変換回路の出力信号が示す周波数とを用いて、前記入力信号の周波数を算出する周波数演算回路と、
    　を備える周波数検出回路。     A first frequency detection circuit that detects a frequency from an input signal and outputs a signal indicating the detected frequency;
    A local oscillation signal generation circuit that generates a local oscillation signal for frequency conversion from a frequency indicated by an output signal of the first frequency detection circuit to a frequency within a pass band of the first filter circuit and the second filter circuit;
    A 90-degree phase shift circuit that generates a first local oscillation signal and a second local oscillation signal having a phase difference of 90 degrees from the local oscillation signal, and a frequency conversion of the input signal using the first local oscillation signal. A first frequency conversion circuit that outputs to the first filter circuit; a second frequency conversion circuit that converts the frequency of the input signal using the second local oscillation signal and outputs the frequency to the second filter circuit; A phase calculation circuit for calculating a phase of the input signal using an output signal of the first filter circuit and an output signal of the second filter circuit; and a phase calculated by the phase calculation circuit is converted into a frequency, and the converted frequency is indicated. A second frequency detection circuit having a phase frequency conversion circuit for outputting a signal;
    A frequency calculation circuit that calculates the frequency of the input signal using the frequency indicated by the output signal of the first frequency detection circuit and the frequency indicated by the output signal of the phase frequency conversion circuit;
    A frequency detection circuit comprising:
  6. 　前記入力信号に対し、前記第１周波数検出回路、前記局部発振信号生成回路及び前記９０度移相回路による遅延を補償して前記第１周波数変換回路及び前記第２周波数変換回路に出力する第１遅延補償回路と、
    　前記第１周波数検出回路の出力信号に対し、前記局部発振信号生成回路及び前記第２周波数検出回路による遅延を補償して前記周波数演算回路に出力する第２遅延補償回路と、
    　を備えることを特徴とする請求項５記載の周波数検出回路。     The first frequency detection circuit, the local oscillation signal generation circuit, and the 90-degree phase shift circuit compensate for the input signal and output the first signal to the first frequency conversion circuit and the second frequency conversion circuit. A delay compensation circuit;
    A second delay compensation circuit that compensates for a delay caused by the local oscillation signal generation circuit and the second frequency detection circuit with respect to an output signal of the first frequency detection circuit and outputs the signal to the frequency calculation circuit;
    The frequency detection circuit according to claim 5, further comprising:
  7. 　前記第１周波数検出回路の出力信号を用いて、前記局部発振信号生成回路が生成する前記局部発振信号の周波数を制御する係数演算回路と、
    　前記係数演算回路の出力信号を用いて、前記第１フィルタ回路及び前記第２フィルタ回路の前記通過帯域の中心周波数を制御する中心周波数制御回路と、
    　を備えることを特徴とする請求項５記載の周波数検出回路。     A coefficient calculation circuit for controlling the frequency of the local oscillation signal generated by the local oscillation signal generation circuit using the output signal of the first frequency detection circuit;
    A center frequency control circuit for controlling a center frequency of the pass band of the first filter circuit and the second filter circuit using an output signal of the coefficient arithmetic circuit;
    The frequency detection circuit according to claim 5, further comprising:
  8. 　前記入力信号に対し、前記第１周波数検出回路、前記係数演算回路、前記局部発振信号生成回路及び前記９０度移相回路による遅延を補償して前記第１周波数変換回路及び前記第２周波数変換回路に出力する第１遅延補償回路と、
    　前記第１周波数検出回路の出力信号に対し、前記係数演算回路、前記局部発振信号生成回路、前記中心周波数制御回路及び前記第２周波数検出回路による遅延を補償して前記周波数演算回路に出力する第２遅延補償回路と、
    　を備えることを特徴とする請求項７記載の周波数検出回路。     The first frequency conversion circuit and the second frequency conversion circuit are compensated for delay caused by the first frequency detection circuit, the coefficient calculation circuit, the local oscillation signal generation circuit, and the 90-degree phase shift circuit with respect to the input signal. A first delay compensation circuit that outputs to
    The output signal of the first frequency detection circuit compensates for delays caused by the coefficient calculation circuit, the local oscillation signal generation circuit, the center frequency control circuit, and the second frequency detection circuit, and outputs the signal to the frequency calculation circuit. 2 delay compensation circuit;
    The frequency detection circuit according to claim 7, further comprising:
PCT/JP2015/083050 2015-11-25 2015-11-25 Frequency detection circuit WO2017090116A1 (en)

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WO2024111034A1 (en) * 2022-11-22 2024-05-30 三菱電機株式会社 Frequency detection circuit and frequency detection system
WO2024111033A1 (en) * 2022-11-22 2024-05-30 三菱電機株式会社 Frequency detection circuit and frequency detection system

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JP2005091255A (en) * 2003-09-19 2005-04-07 Kenwood Corp Tone signal frequency detector
JP2014009979A (en) * 2012-06-28 2014-01-20 Nippon Dempa Kogyo Co Ltd Frequency measurement device

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Publication number Priority date Publication date Assignee Title
JP2005091255A (en) * 2003-09-19 2005-04-07 Kenwood Corp Tone signal frequency detector
JP2014009979A (en) * 2012-06-28 2014-01-20 Nippon Dempa Kogyo Co Ltd Frequency measurement device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024111034A1 (en) * 2022-11-22 2024-05-30 三菱電機株式会社 Frequency detection circuit and frequency detection system
WO2024111033A1 (en) * 2022-11-22 2024-05-30 三菱電機株式会社 Frequency detection circuit and frequency detection system

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