WO2017069462A1 - High electron mobility transistor and method for manufacturing same - Google Patents

High electron mobility transistor and method for manufacturing same Download PDF

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Publication number
WO2017069462A1
WO2017069462A1 PCT/KR2016/011538 KR2016011538W WO2017069462A1 WO 2017069462 A1 WO2017069462 A1 WO 2017069462A1 KR 2016011538 W KR2016011538 W KR 2016011538W WO 2017069462 A1 WO2017069462 A1 WO 2017069462A1
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Prior art keywords
source electrode
pad
insulating layer
forming
electrode wiring
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PCT/KR2016/011538
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French (fr)
Korean (ko)
Inventor
이상민
정연국
구황섭
김현제
정희석
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(주)기가레인
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Priority claimed from KR1020160047552A external-priority patent/KR101841631B1/en
Application filed by (주)기가레인 filed Critical (주)기가레인
Publication of WO2017069462A1 publication Critical patent/WO2017069462A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

Definitions

  • the present invention relates to a high electron mobility transistor and a method of manufacturing the same, and more particularly, to a high electron mobility transistor and a method of manufacturing the same to improve the yield of the device and the reliability of the device.
  • gallium nitride-based transistors Due to the development of information and communication technology, the demand for high withstand voltage transistors operating in a high speed switching environment or a high voltage environment is increasing. Recently, gallium nitride-based transistors have a high-speed switching operation compared to conventional silicon-based transistors, and are suitable for high-speed signal processing and can be applied to high-voltage environments through the high voltage resistance of the material itself. It is getting attention. Particularly in the case of High Electron Mobility Transistor (HEMT) using gallium nitride, electron mobility (2DEG; 2-Dimensional Electron Gas) generated at the interface between heterogeneous materials is used. Mobility can be increased, which is an advantage for high speed signal transmission.
  • HEMT High Electron Mobility Transistor
  • a source electrode wiring electrically connected to the source electrode is formed under the source electrode in order to minimize the size thereof. Etching to a depth to form a source electrode wiring via penetrating the lower portion of the source electrode, and to form a source electrode wiring by plating a thin metal film on the surface of the source electrode wiring via.
  • the substrate since the source electrode wiring forming process performs the back-grinding process to etch to a predetermined depth from the rear surface of the thinned substrate, the substrate may be broken, and thus the etching rate is reduced compared to the case of etching the thick substrate before the back-grinding process. In addition, the etching uniformity is lowered and cracks, ie, cracks, are generated in the substrate, thereby degrading yield and reliability of the device.
  • the source electrode wiring is formed by plating a thin metal film on the surface of the source electrode wiring via. Therefore, since the inside of the via for the electrode wiring is empty, the thermal conductivity of the device is lowered. have.
  • An object of the present invention is to form a source electrode wiring electrically connected to the source electrode under the source electrode to minimize the size of the transistor, to complete the process of forming the source electrode wiring from the front, and to fill the source electrode wiring via with a conductive material conductor. It is to provide a high electron mobility transistor and a method of manufacturing the same, which is easy to process and can improve heat dissipation of a device.
  • a high electron mobility transistor according to an embodiment of the present invention
  • a field plate covering an upper surface of the source electrode pad and an upper surface of the second insulating layer between the gate electrode and the drain electrode and a third insulating layer formed on the front surface of the field plate and the drain electrode pad are exposed. It includes more.
  • the via pad for source electrode wiring, the source electrode pad, and the drain electrode pad may be any one of copper and gold.
  • the diameter of the upper portion of the via pad for source electrode wiring may be larger than that of the lower portion of the rear side.
  • the via pad for source electrode wiring penetrates to the rear surface of the substrate.
  • at least one via pad for source electrode wiring may be formed on the source electrode.
  • an upper surface area of the via pad for source electrode wiring may occupy 50% or more of the bottom area of the source electrode.
  • the active layer includes a gallium nitride (GaN) layer.
  • GaN gallium nitride
  • a base layer on a substrate on which a source electrode wiring forming portion is defined Forming a base layer on a substrate on which a source electrode wiring forming portion is defined, a source electrode having a hollow formed on the base layer of the source electrode wiring forming portion, and an upper portion of the base layer spaced apart from the source electrode wiring forming portion
  • Forming a drain electrode on the substrate forming a first insulating layer on the front surface of the source electrode, the drain electrode and the base layer, and removing the first insulating layer at a predetermined portion between the source electrode and the drain electrode
  • Forming a gate electrode on the exposed base layer Forming a second insulating layer on the entire surface, and forming the first insulating layer, the base layer, and the substrate inside the source electrode hollow on the source electrode wiring forming portion.
  • a method of manufacturing a high electron mobility transistor including: forming a base layer on a substrate on which a source electrode wiring forming portion is defined, and hollowing an upper portion of the base layer on the source electrode wiring forming portion; Forming a drain electrode on the formed source electrode and the base layer spaced apart from the source electrode wiring forming portion, and forming a first insulating layer on an entire surface of the source electrode, the drain electrode and the base layer; Removing the first insulating layer at a predetermined portion between the source electrode and the drain electrode to form a gate electrode on the exposed base layer, forming a second insulating layer on the entire surface of the source electrode wiring forming portion
  • the second insulating layer, the first insulating layer, the base layer, and the substrate inside the hollow of the source electrode are etched to a predetermined depth from an entire surface of the source electrode.
  • Forming a wiring via removing a portion of the second insulating layer and the first insulating layer on the source electrode, and removing a portion of the second insulating layer and the first insulating layer on the drain electrode; Forming vias for source electrode pads and vias for drain electrode pads, and filling the vias for source electrode wiring, the vias for source electrode pad and the vias for drain electrode pad with conductors, respectively; And forming a drain electrode pad, forming a field plate from an upper surface of the source electrode pad to an upper surface of the second insulating layer between the gate electrode and the drain electrode and exposing the field plate and the drain electrode pad. Forming a third insulating layer on the entire surface.
  • the method may further include back-grinding the rear surface of the substrate so that the rear end of the via pad for source electrode wiring is exposed and forming a rear layer connected to the via pad exposed on the rear surface of the substrate.
  • the high electron mobility transistor of the present invention and a method of manufacturing the same have a method of forming a source electrode wiring electrically connected to a source electrode under the source electrode.
  • the back-grinding process is performed to increase the etching rate, improve the etching uniformity, and improve the cracking of the substrate, compared to the conventional technique of etching to the predetermined depth from the back surface of the thinned substrate. It has the effect of suppressing generation to improve the yield of the device and the reliability of the device.
  • the present invention forms the via pad for the source electrode wiring and proceeds the back-grinding process, so that the back-grinding process is performed without the substrate etching process for forming the source electrode wiring via, so that the high temperature bonding agent in the back-grinding process is performed.
  • a low temperature binder which can be more easily removed can be used to facilitate the process, thereby improving the yield of the device.
  • the present invention forms a via pad for source electrode wiring by etching and filling a thick substrate to a predetermined depth from the front surface, so that all the vias for the source electrode wiring are filled, so that most of the prior art have thermal conductivity more than that of the empty source electrode wiring via.
  • This high effect has the effect of improving the heat dissipation of the device to improve the performance of the device.
  • the present invention forms a via pad for source electrode wiring by etching and filling a thick substrate to a predetermined depth from the front, so that solder and flux used for solder bonding for packaging of the device cannot be introduced into the substrate. It has the effect of improving reliability and preventing shortening of the life of the device.
  • the present invention can be etched more stably by etching a thick substrate to a predetermined depth from the front surface, it is possible to form a wider width of the via pad for source electrode wiring than the etching of a thin substrate to a predetermined depth from the rear surface. There can improve the electrical conductivity and thermal conductivity.
  • FIG. 1 is a cross-sectional view illustrating a high electron mobility transistor according to a first embodiment.
  • FIG. 2 is a plan view illustrating a plurality of via pads for source electrode wiring formed in the source electrode of FIG. 1.
  • FIG. 3 is a plan view illustrating one via pad for source electrode wiring formed in the source electrode of FIG. 1.
  • 4A to 4G are cross-sectional views illustrating a method of manufacturing a high mobility transistor according to a first embodiment.
  • 5A through 5B are cross-sectional views illustrating a method of manufacturing a high mobility transistor according to a second embodiment.
  • barrier layer 19 metal mask
  • BSP Back layer VA: Via for source electrode wiring
  • VAP Via pad for source electrode wiring SE: Source electrode
  • drain electrode PDE drain electrode pad
  • PAS1 First Insulation Layer
  • PAS2 Second Insulation Layer
  • PAS3 3rd insulating layer SD1: 1st seed layer
  • SD2 Second Seed Layer SD3: Third Seed Layer
  • first, second, etc. are used herein to describe various members, regions, and / or portions, it is obvious that these members, components, regions, layers, and / or portions should not be limited by these terms. Do. These terms do not imply any particular order, up or down, or superiority, and are only used to distinguish one member, region or region from another member, region or region. Accordingly, the first member, region, or region described below may refer to the second member, region, or region without departing from the teachings of the present invention.
  • the high electron mobility transistor according to the first embodiment includes a substrate 11 having a source electrode wiring forming portion, a base layer 10 formed on the substrate 11, and a source electrode wiring.
  • the gate electrode GE is formed on the base layer 10 between the drain electrodes DE, and the base layer 10 and the substrate 11 of the source electrode wiring forming portion are etched to a predetermined depth from the front side.
  • PSE source electrode pad
  • DE drain electrode pad formed on the drain electrode
  • PDE PDE
  • PAS1 first insulating layer
  • PAS2 A second insulating layer PAS2 is formed between the pole pad PSE and the drain electrode pad PDE and covers the first insulating layer PAS1 and the gate electrode GE.
  • the display device may further include a third insulating layer PAS3 formed on the entire surface of the PDE to expose the PDE.
  • the base layer 10 is formed on the substrate 11.
  • a source electrode pad PSE electrically connected to the source electrode SE is formed on the via pad VAP for source electrode wiring.
  • the via pad VAP for source electrode wiring is electrically connected to the source electrode SE through the source electrode pad PSE.
  • a drain electrode pad PDE electrically connected to the drain electrode DE is formed on the drain electrode DE.
  • the substrate 11 has a source electrode wiring forming portion, a source electrode pad forming portion and a drain electrode pad forming portion, which are formed with a step S above the source electrode wiring forming portion and defined, respectively, and defined by sapphire (Al 2 O). 3 ), gallium nitride (GaN), silicon (Si), silicon carbide (SiC) and the like.
  • the base layer 10 is formed on the substrate 11 along the outer circumference of the source electrode wiring forming portion, the buffer layer 13 is formed on the nucleation layer 12, and the barrier is formed on the buffer layer 13. Layer 15 is formed.
  • the nucleation layer 12, the buffer layer 13, and the barrier layer 15 may be formed of aluminum nitride (AlN), gallium nitride (GaN), and aluminum gallium nitride (AlGaN), respectively.
  • the source electrode SE is a hollow body having a hollow so as to form a step S of the source electrode pad forming portion, and is formed on the base layer 10.
  • the drain electrode DE is formed on the base layer 10 to be spaced apart from the source electrode SE.
  • the gate electrode GE is formed on the base 10 at a predetermined portion between the source electrode SE and the drain electrode DE.
  • FIG. 2 is a plan view illustrating a plurality of source electrode wiring via pads formed in the source electrode of FIG. 1
  • FIG. 3 is a plan view illustrating one source electrode wiring via pad formed in the source electrode of FIG. 1.
  • the via pad VAP for source electrode wiring is surrounded by the substrate 11 and the base layer 10 and is formed by etching and filling the source electrode wiring forming portion from a front surface to a predetermined depth.
  • the via pad VAP for source electrode wiring is integrally formed with the source electrode pad PSE.
  • the via pad for source electrode wiring is formed by etching and filling from the front surface of the substrate 11 to a predetermined depth, so that the diameter of the upper portion in the front side may be larger than the lower portion in the rear side. .
  • it is formed to be opposite to the shape of the prior art and the source electrode wiring via pad (VAP) that is etched from the rear surface.
  • VAP source electrode wiring via pad
  • the via pad VAP for source electrode wiring penetrates to the rear surface of the substrate 11 during the back-grinding process after forming the source electrode pad PSE and the drain electrode pad PDE to be described later.
  • the source electrode wiring via pads VAP penetrating the front and rear surfaces are formed in the same manner as the source electrode wiring via pads VAP are formed on the rear surface of the substrate 11 in the related art. Therefore, the source electrode wiring via pads (VAP) penetrating the front and rear surfaces are formed while solving the problems caused when the source electrode wiring via pads (VAP) are formed on the rear surface, as in the prior art.
  • the via pad for source electrode wiring is formed by filling the source electrode wiring forming portion with a conductive filler conductor such as copper (Cu), gold (Au) to improve the electrical conductivity and the thermal conductivity of the transistor.
  • a conductive filler conductor such as copper (Cu), gold (Au) to improve the electrical conductivity and the thermal conductivity of the transistor.
  • At least one via pad VAP for source electrode wiring is formed in the source electrode SE, as shown in FIG. 2, or as shown in FIG. 3, 50 of the bottom area of the source electrode SE. It can be formed accounting for more than%. Both are to improve the electrical and thermal conductivity through the via pad (VAP).
  • the via pad for source electrode wiring (VAP) is formed on the front surface, only one number may be formed, or two or more may be formed to improve the heat dissipation efficiency of the transistor.
  • the via pad VAP for the source electrode wiring is formed with 50% or more of the bottom area of the source electrode SE, thereby providing electrical conductivity and heat. The conductivity can be improved.
  • the electrical conductivity and thermal conductivity may be improved by forming the size close to the size and shape of the source electrode SE.
  • the substrate 11 in a thick state is etched to a predetermined depth from the front side, so that the substrate 11 in a thin state can be etched more stably than the etching depth from the back side to a predetermined depth, so that a via pad for source electrode wiring (VAP) Since the width of the film can be widened, the via pad for source electrode wiring (VAP) can be formed as shown in FIGS. 2 and 3, thereby improving the electrical conductivity and the thermal conductivity.
  • VAP via pad for source electrode wiring
  • 4A to 4G are cross-sectional views illustrating a method of manufacturing a high mobility transistor according to a first embodiment.
  • a base layer 10 on the substrate 11 where the source electrode wiring forming portion is defined In the method of manufacturing a high electron mobility transistor, forming a base layer 10 on the substrate 11 where the source electrode wiring forming portion is defined, and forming a hollow on the base layer 10 above the source electrode wiring forming region.
  • Forming a drain electrode DE on the formed source electrode SE and the base layer 10 spaced apart from the source electrode wiring forming portion, the source electrode SE, the drain electrode DE, and the base layer Forming a first insulating layer PAS1 on the entire surface of the substrate 10, removing the first insulating layer PAS1 at a predetermined portion between the source electrode SE and the drain electrode DE, and exposing the base layer 10.
  • a gate electrode GE Forming a gate electrode GE on the top, forming a second insulating layer PAS2 on the front surface, a second insulating layer PAS2 inside the hollow of the source electrode SE on the source electrode wiring forming portion, and 1
  • the insulating layer PAS1, the base layer 10, and the substrate 11 are etched to a predetermined depth from the front surface, so that the via for source electrode wiring V Forming A) and removing a part of the second insulating layer PAS2 and the first insulating layer PAS1 on the source electrode SE, and forming the second insulating layer PAS2 and the drain electrode DE on the drain electrode DE.
  • PSEVA source electrode pad via
  • PSE drain electrode pad via
  • PDE drain electrode pad
  • the base layer 10 is deposited on the substrate 11.
  • the base layer may be formed by stacking the nucleation layer 12, the buffer layer 13, and the barrier layer 15.
  • the nucleation layer 12, the buffer layer 13, and the barrier layer 15 may be made of aluminum nitride (AlN), gallium nitride (GaN), and aluminum gallium nitride (AlGaN), respectively.
  • the source electrode pad forming portion is larger in area than the source electrode wiring forming portion.
  • a source electrode SE which is a hollow body having a hollow, is formed on the base layer 10 so that the step S of the source electrode pad forming portion is formed, and the source electrode SE is formed.
  • the drain electrode DE is formed on the base layer to be spaced apart from each other.
  • a photosensitive film (not shown) is coated. Thereafter, the photoresist film is selectively exposed and developed so that the photoresist film is removed only at a portion where the source electrode SE and the drain electrode DE are to be formed. In this case, only the base layer 10 of the portion where the source electrode SE and the drain electrode DE are to be formed is exposed.
  • the first conductive layer (not shown) is deposited on the entire surface using the photosensitive film as a mask, and a hollow having a hollow is formed so that a step S of the source electrode pad forming portion is formed by performing a lift-off process or the like.
  • a source electrode SE which is a formed body, and a drain electrode DE spaced apart from the source electrode SE are formed.
  • the first conductive layer may be made of an ohmic contact metal such as Ti / Al / Ni / Au, Ti / Al / Ti / Ni / Au.
  • the first conductive layer is deposited and then heat treated to form an ohmic contact.
  • the source electrode SE is described as having a hollow shape.
  • the source electrode SE may be non-hollow shape.
  • the source electrode SE may be etched downward including the center portion of the source electrode.
  • a first insulating layer PAS1 is deposited on the entire surface including the source electrode SE and the drain electrode DE, and a base layer in which a lower portion of the gate electrode GE is formed in a later process.
  • the photolithography process is performed to expose 10, and the first insulating layer PAS1 is selectively etched.
  • the first insulating layer PAS1 may be formed of silicon nitride or the like.
  • the photolithography process is performed to expose the first insulating layer PAS1 on which the upper portion of the gate electrode GE is to be seated. Let's do it.
  • the exposed first insulating layer PAS1 may be both sides of the first insulating layer PAS1 selectively etched for the lower portion of the gate electrode GE.
  • a second conductive layer (not shown) is deposited on the entire surface of the portion where the gate electrode GE is to be exposed, and a lift off process is performed to form the gate electrode GE.
  • the second conductive layer may be made of Ni / Au, Ti / Al / Ni / Au, Ti / Al / Ti / Ni / Au, and the like.
  • the gate electrode GE is formed between the source electrode SE and the drain electrode DE.
  • the second insulating layer PAS2 is deposited on the gate electrode GE and the first insulating layer PAS1.
  • the second insulating layer PAS2 is made of silicon nitride or the like.
  • a first seed layer SD1 is deposited on the second insulating layer PAS2.
  • the first seed layer SD1 may be deposited using a deposition process such as sputtering, and may be formed of Ti / Cu, Ti / Al, Ti / W, Ti / Au, Ti / Ni / Cu, or the like. have.
  • the metal mask 19 is grown to about 7 ⁇ 10 ⁇ m.
  • the metal mask 19 may be made of nickel (Ni), copper (Cu), gold (Au), or the like.
  • the substrate 11 is etched to a predetermined depth from the front surface to form vias VA for source electrode wiring. Thereafter, the first seed layer SD1 and the metal mask 19 on the second insulating layer PAS2 are removed.
  • the size of etching the source electrode wiring via VA may be etched according to the size of the hollow portion of the source electrode SE, or may be etched smaller than the size of the hollow portion of the source electrode SE, as shown in FIG. 4D.
  • the photolithography process is performed to remove the first and second insulating layers PAS1 and PAS2 of the source electrode pad forming portion and the drain electrode pad forming portion, respectively.
  • the source electrode pad via PSEVA exposing the base layer 10 and the source electrode SE is formed on the source electrode pad forming portion, and the drain electrode DE is exposed on the drain electrode pad forming portion.
  • a drain electrode via is formed.
  • a second seed layer SD2 is deposited on the entire surface including the source electrode pad via PSEVA and the drain electrode pad via PDEVA, and a photolithography process is performed to proceed with the source electrode pad. Only the second seed layer SD2 on the top of the via PSEVA and the top of the drain electrode pad via PDEVA is exposed.
  • the conductive filler is grown on the exposed second seed layer SD2 to form a via pad for source electrode wiring in the via electrode VA for the source electrode pad forming portion, and a via for source electrode wiring.
  • the source electrode pad PSE is formed integrally with the via pad VAP for source electrode wiring on the via pad VA on the pad VAP, and the drain electrode pad via PDEVA is formed on the drain electrode pad forming portion.
  • PDE drain electrode pad
  • the second seed layer SD2 on the second insulating layer PAS2 on both sides of the source electrode pad PSE and the drain electrode pad PDE is removed.
  • the second seed layer SD2 may be made of Ti / Cu, Ti / Al, Ti / Ni / Cu, Ti / Au, or the like.
  • the conductive filler may be made of copper (Cu), gold (Au), or the like.
  • the rear surface of the substrate 11 facing the front surface of the substrate 11 on which the source electrode pad PSE and the drain electrode pad PDE are formed is back-grinded.
  • the rear end of the via pad VAP for source electrode wiring is exposed by a back-grinding process under the substrate 11.
  • the height of the via pad VAP for source electrode wiring is about 50 ⁇ m to 100 ⁇ m.
  • the back-grinding process is not shown, a low temperature bonded body, a carrier wafer, or the like is used.
  • the back-grinding process is performed without a substrate etching process for forming the source electrode wiring via, the low-temperature binder may be used more easily than the high-temperature binder.
  • the back-grinding process is performed using a low temperature wax (Wax) as a low temperature binder.
  • a third seed layer SD3 is deposited on the rear surface of the substrate 11 where the rear end of the via pad VAP for source electrode wiring is exposed, and then a third conductive layer is grown from the third seed layer SD3.
  • the third seed layer SD3 may be made of Ti / Cu, Ti / Al, Ti / W, Ti / Au, Ti / Ni / Cu, or the like.
  • the back layer BSP may be formed of a conductive material conductor such as copper (Cu), gold (Au), and the like to improve electrical conductivity and thermal conductivity.
  • the high electron mobility transistor according to the first embodiment and the method of manufacturing the same have a method of forming a source electrode wiring electrically connected to the source electrode SE under the source electrode, before the back-grinding process.
  • a thick substrate is etched and filled from the front side to a predetermined depth to form a via pad for source electrode wiring (VAP), thereby performing a back-grinding process to etch to a predetermined depth from the rear surface of the thinned substrate.
  • VAP via pad for source electrode wiring
  • the etching rate is increased, the etching uniformity is improved, and the occurrence of cracks in the substrate can be suppressed to improve the yield of the device and the reliability of the device.
  • the high electron mobility transistor according to the first embodiment and the manufacturing method thereof form a via pad (VAP) for source electrode wiring and perform a back-grinding process, so that the back-grinding process is easier to remove than a high temperature binder.
  • VAP via pad
  • One low temperature binder can be used and the process is easy to improve the yield of the device.
  • the high electron mobility transistor according to the first embodiment and a method of manufacturing the same are etched and filled with a thick substrate from a front surface to a predetermined depth to form a via pad (VAP) for source electrode wiring, so that the source electrode wiring via (VA) is formed. Since most of the conventional technology is filled, the thermal conductivity is higher than that of the via source wiring via (VA), thereby improving heat dissipation of the device, thereby improving performance of the device.
  • VAP via pad
  • the high electron mobility transistor according to the first embodiment and the method of manufacturing the same are filled with all of the source electrode wiring vias as described above, the solder and the flux used for solder bonding for packaging the device are transferred to the substrate. It can not flow in, improving the reliability of the device and preventing the device from shortening its lifespan.
  • the present invention can be etched more stably than the etching of the thin substrate 11 to a predetermined depth from the rear surface of the via pad for source electrode wiring ( The width of the VAP) can be widened to improve the electrical conductivity and the thermal conductivity.
  • 5A and 5B are cross-sectional views illustrating a method of manufacturing a high mobility transistor according to a second embodiment.
  • description of the second embodiment description of the same configuration and manufacturing method as the first embodiment will be omitted.
  • the high electron mobility transistor of the present invention according to the second embodiment has a field plate (FDP) and a third insulating layer in the structure of the high electron mobility transistor according to the first embodiment. It is a structure further equipped with (PAS3). Therefore, description of the remaining identical structure is omitted.
  • FDP field plate
  • PAS3 PAS3
  • the field plate FDP covering the upper surface of the source electrode pad PSE to the upper surface of the second insulating layer SD2 between the gate electrode GE and the drain electrode DE may be formed.
  • the display device may further include a third insulating layer PAS3 formed on the entire surface of the field plate FDP and the drain electrode pad PDE.
  • a subsequent process such as a photolithography process or a third conductive layer deposition process may be performed to form an upper portion of the second insulating layer PAS2 between the gate electrode GE and the drain electrode DE, and the source electrode.
  • a field plate FDP is formed on the field plate forming portion on the pad PSE to contact the source electrode SE through the source electrode pad PSE.
  • the field plate may be made of Ti / Pt / Au, Ti / Al / Ni / Au, Ti / Al / Ti / Ni / Au.
  • a third insulating layer PAS3 is deposited on the entire surface including the field plate FDP.
  • the photolithography process is performed to expose the field plate FDP and the drain electrode pad PDE on the source electrode pad PSE to form a third insulating layer PAS3 and then selectively etch it.
  • the present invention can minimize the size of the high-mobility mobility transistor, and to facilitate heat dissipation, thereby improving reliability, which may be industrially applicable.

Abstract

Disclosed are a high electron mobility transistor and a method for manufacturing the same. The present invention comprises the steps of: forming a base layer on a substrate, which has a source electrode wiring forming part defined thereon; forming a source electrode so as to have a hollow on the upper portion of the base layer, on the source electrode wiring forming part, and forming a drain electrode on the upper portion of the base layer to be spaced from the source electrode wiring forming part; forming a first insulating layer on the front surfaces of the source electrode, the drain electrode, and the base layer, respectively; removing the first insulating layer on a predetermined part between the source electrode and the drain electrode and forming a gate electrode on the exposed base layer; forming a second insulating layer on the front surfaces; etching the first insulating layer, the base layer, and the substrate inside the hollow of the source electrode, on the source electrode wiring forming part, from the front surfaces to a predetermined depth, thereby forming a source electrode wiring via; partially removing the second insulating layer and the first insulating layer, on the upper portion of the source electrode, and partially removing the second insulating layer and the first insulating layer, on the upper portion of the drain electrode, thereby forming a source electrode pad via and a drain electrode pad via, respectively; and filling the source electrode wiring via, the source electrode pad via, and the drain electrode pad via with a conductor, thereby forming a source electrode wiring via pad, a source electrode pad, and a drain electrode pad.

Description

고전자이동도 트랜지스터 및 그의 제조방법High Variability Transistor and Manufacturing Method
본 발명은 고전자이동도 트랜지스터 및 그의 제조방법에 관한 것으로서, 보다 상세하게는 소자의 수율 및 소자의 신뢰성을 향상시키는 고전자이동도 트랜지스터 및 그의 제조방법에 관한 것이다.The present invention relates to a high electron mobility transistor and a method of manufacturing the same, and more particularly, to a high electron mobility transistor and a method of manufacturing the same to improve the yield of the device and the reliability of the device.
정보통신기술의 발달로 인해, 고속 스위칭 환경이나 고전압 환경에서 동작하는 고내압 트랜지스터의 요청이 증가하고 있다. 이에 최근에 등장한 갈륨 나이트라이드계 트랜지스터는 종래의 실리콘계 트랜지스터에 비해 고속 스위칭 동작이 가능하여 초고속 신호 처리에 적합할 뿐만 아니라 소재 자체의 고내압 특성을 통해 고전압 환경에 적용할 수 있는 장점이 있어 업계의 주목을 받고 있다. 특히 갈륨나이트라이드를 이용한 고전자이동도 트랜지스터(HEMT: High Electron Mobility Transistor)의 경우, 이종 물질간 계면에서 발생하는 2차원 전자가스(2DEG; 2-Dimensional Electron Gas)를 이용함으로써 전자의 이동도(mobility)를 높일 수 있어 고속 신호 전송에 적합한 장점이 있다.Due to the development of information and communication technology, the demand for high withstand voltage transistors operating in a high speed switching environment or a high voltage environment is increasing. Recently, gallium nitride-based transistors have a high-speed switching operation compared to conventional silicon-based transistors, and are suitable for high-speed signal processing and can be applied to high-voltage environments through the high voltage resistance of the material itself. It is getting attention. Particularly in the case of High Electron Mobility Transistor (HEMT) using gallium nitride, electron mobility (2DEG; 2-Dimensional Electron Gas) generated at the interface between heterogeneous materials is used. Mobility can be increased, which is an advantage for high speed signal transmission.
이러한, 고전자이동도 트랜지스터는 크기를 최소화하기 위하여 소스 전극과 전기적으로 연결되는 소스전극배선을 소스 전극 하부에 형성하는 공정에 있어서, 백-그라인딩(backgrinding) 공정을 진행하여 얇아진 기판의 후면에서부터 소정 깊이로 식각하여 소스 전극의 하부를 관통하는 소스전극배선용 비아를 형성하고 소스전극배선용 비아의 표면에 얇은 금속막을 도금하여 소스전극배선을 형성한다.In the high electron mobility transistor, a source electrode wiring electrically connected to the source electrode is formed under the source electrode in order to minimize the size thereof. Etching to a depth to form a source electrode wiring via penetrating the lower portion of the source electrode, and to form a source electrode wiring by plating a thin metal film on the surface of the source electrode wiring via.
그러나 상기 소스전극배선 형성 공정은 백-그라인딩 공정을 진행하여 얇아진 기판의 후면에서부터 소정 깊이로 식각하기 때문에, 기판이 깨질 염려가 있어서 백-그라인딩 공정 전의 두꺼운 기판을 식각하는 경우보다 식각속도가 감소되고, 식각 균일도가 저하되며 기판에 균열 즉 크랙(crack)이 발생하여 소자의 수율 및 소자의 신뢰성이 저하되는 문제점이 있다.However, since the source electrode wiring forming process performs the back-grinding process to etch to a predetermined depth from the rear surface of the thinned substrate, the substrate may be broken, and thus the etching rate is reduced compared to the case of etching the thick substrate before the back-grinding process. In addition, the etching uniformity is lowered and cracks, ie, cracks, are generated in the substrate, thereby degrading yield and reliability of the device.
또한, 상기 소스전극배선 형성 공정에 의한 기판의 온도 상승으로 백-그라인딩 공정 시 저온 접합제를 사용하지 못하고 제거가 어려운 고온 접합제를 사용함에 따라 공정을 매우 어렵게 하여 소자의 수율이 저하되는 문제점이 있다.In addition, as the temperature of the substrate is increased by the source electrode wiring forming process, a low temperature binder is not used in the back-grinding process and a high temperature binder is difficult to remove. have.
또한, 상기 소스전극배선 형성 공정은 소스전극배선용 비아의 표면에 얇은 금속막을 도금하여 소스전극배선을 형성하기 때문에, 소스전극배선용 비아 내측이 비어 있어서 열 전도율이 낮아 소자의 열방출이 저하되는 문제점이 있다.In the process of forming the source electrode wiring, the source electrode wiring is formed by plating a thin metal film on the surface of the source electrode wiring via. Therefore, since the inside of the via for the electrode wiring is empty, the thermal conductivity of the device is lowered. have.
또한, 상기 소스전극배선 형성 공정은 소스전극배선용 비아 내측의 대부분이 비어 있기 때문에, 소자의 패키징을 위한 솔더본딩(solder bonding) 시 사용되는 솔더와 플럭스(flux)가 기판으로 유입될 수 있어 소자의 신뢰성이 저하되고 소자의 수명이 단축될 수 있는 문제점이 있다.In the process of forming the source electrode wiring, since most of the inside of the via for source electrode wiring is empty, solder and flux used for solder bonding for packaging the device may flow into the substrate. There is a problem that the reliability is lowered and the life of the device can be shortened.
본 발명의 목적은, 소스전극과 전기적으로 연결되는 소스전극배선을 소스전극 하부에 형성하여 트랜지스터의 크기를 최소화하고, 소스전극배선 형성 공정을 전면에서 하고 소스전극배선용 비아를 도전성물질전도체로 충진함으로써 공정이 용이하고 소자의 열방출을 향상시킬 수 있는 고전자이동도 트랜지스터 및 그의 제조방법을 제공하는 것이다.An object of the present invention is to form a source electrode wiring electrically connected to the source electrode under the source electrode to minimize the size of the transistor, to complete the process of forming the source electrode wiring from the front, and to fill the source electrode wiring via with a conductive material conductor. It is to provide a high electron mobility transistor and a method of manufacturing the same, which is easy to process and can improve heat dissipation of a device.
본 발명의 일실시예에 따른 고전자이동도 트랜지스터는,A high electron mobility transistor according to an embodiment of the present invention,
소스전극배선형성부위가 정의된 기판, 상기 기판 상부에 형성되는 베이스층, 상기 소스전극배선형성부위의 상기 베이스층 상부에 형성되고 중공이 형성된 소스전극, 상기 소스전극과 이격되어 상기 베이스층 상부에 형성되는 드레인전극, 상기 소스전극과 상기 드레인전극 사이 상기 베이스층 상부에 형성되는 게이트전극, 상기 중공 내측으로 상기 소스전극배선형성부위의 상기 베이스층 및 상기 기판을 전면에서부터 소정 깊이로 식각하고 전도체를 충진하여 형성되는 소스전극배선용 비아패드, 상기 소스전극배선용 비아패드에서 연장되어 일체로 형성되는 소스전극패드, 상기 드레인전극 상에 형성되는 드레인전극패드, 상기 베이스층상에 형성되는 제1 절연층 및 상기 소스전극패드와 상기 드레인전극패드 사이에 형성되며 상기 제1 절연층과 상기 게이트전극을 덮는 제2 절연층을 포함한다.A substrate on which a source electrode wiring forming portion is defined, a base layer formed on the substrate, a source electrode formed on the base layer on the source electrode wiring forming portion and formed with a hollow, and spaced apart from the source electrode, A drain electrode is formed, a gate electrode formed on the base layer between the source electrode and the drain electrode, the base layer and the substrate of the source electrode wiring forming portion are etched to a predetermined depth from the front surface inside the hollow and the conductor is formed. A via pad for filling the source electrode wiring, a source electrode pad extending from the source electrode wiring via pad and integrally formed; a drain electrode pad formed on the drain electrode; a first insulating layer formed on the base layer; It is formed between the source electrode pad and the drain electrode pad and is formed on the first insulating layer. And a second insulating layer covering the gate electrode.
또한, 상기 소스전극패드 상면부터, 상기 게이트전극과 상기 드레인전극 사이의 상기 제2 절연층 상면까지를 덮는 필드플레이트 및 상기 필드플레이트와 상기 드레인전극패드가 노출되도록 전면에 형성되는 제3 절연층을 더 포함한다.In addition, a field plate covering an upper surface of the source electrode pad and an upper surface of the second insulating layer between the gate electrode and the drain electrode and a third insulating layer formed on the front surface of the field plate and the drain electrode pad are exposed. It includes more.
또한, 상기 소스전극배선용 비아패드, 상기 소스전극패드 및 상기 드레인전극패드는 구리, 금 중 어느 하나일 수 있다.The via pad for source electrode wiring, the source electrode pad, and the drain electrode pad may be any one of copper and gold.
또한, 상기 소스전극배선용 비아패드는 전면측 방향인 상부부위의 직경이 후면측 방향인 하부부위의 직경보다 클 수 있다.In addition, the diameter of the upper portion of the via pad for source electrode wiring may be larger than that of the lower portion of the rear side.
상기 소스전극배선용 비아패드는 상기 기판의 후면까지 관통된 구조이다. 또한, 상기 소스전극배선용 비아패드는 상기 소스전극에 적어도 하나 이상 형성될 수 있다.The via pad for source electrode wiring penetrates to the rear surface of the substrate. In addition, at least one via pad for source electrode wiring may be formed on the source electrode.
또한, 상기 소스전극배선용 비아패드의 상면 면적은 상기 소스전극의 저면 면적의 50% 이상을 차지할 수 있다.In addition, an upper surface area of the via pad for source electrode wiring may occupy 50% or more of the bottom area of the source electrode.
또한, 상기 활성층은 갈륨나이트라이드(GaN)층을 포함한다.In addition, the active layer includes a gallium nitride (GaN) layer.
본 발명의 다른 실시예에 따른 고전자이동도 트랜지스터의 제조방법은, Method of manufacturing a high electron mobility transistor according to another embodiment of the present invention,
소스전극배선형성부위가 정의된 기판상에 베이스층을 형성하는 단계, 상기 소스전극배선형성부위의 상기 베이스층 상부에 중공이 형성된 소스전극과, 상기 소스전극배선형성부위와 이격된 상기 베이스층 상부에 드레인전극을 형성하는 단계, 상기 소스전극과 상기 드레인전극 및 베이스층의 전면에 제1 절연층을 형성하는 단계, 상기 소스전극과 상기 드레인전극 사이의 소정부위의 상기 제1 절연층을 제거하여 노출된 상기 베이스층상에 게이트전극을 형성하는 단계, 전면에 제2 절연층을 형성하는 단계, 상기 소스전극배선형성부위의 상기 소스전극 중공 내측의 상기 제1 절연층, 상기 베이스층 및 상기 기판을 전면에서부터 소정의 깊이로 식각하여 소스전극배선용 비아를 형성하는 단계, 상기 소스전극 상부의 상기 제2 절연층 및 상기 제1 절연층 일부를 제거하고, 상기 드레인전극 상부의 상기 제2 절연층과 상기 제1 절연층의 일부를 제거하여 각각 소스전극패드용 비아 및 드레인전극패드용 비아를 형성하는 단계 및 상기 소스전극배선용 비아, 상기 소스전극패드용 비아 및 상기 드레인전극패드용 비아를 전도체로 충진하여 각각 소스전극배선용 비아패드, 소스전극패드 및 드레인전극패드를 형성하는 단계를 포함한다.Forming a base layer on a substrate on which a source electrode wiring forming portion is defined, a source electrode having a hollow formed on the base layer of the source electrode wiring forming portion, and an upper portion of the base layer spaced apart from the source electrode wiring forming portion Forming a drain electrode on the substrate, forming a first insulating layer on the front surface of the source electrode, the drain electrode and the base layer, and removing the first insulating layer at a predetermined portion between the source electrode and the drain electrode Forming a gate electrode on the exposed base layer, forming a second insulating layer on the entire surface, and forming the first insulating layer, the base layer, and the substrate inside the source electrode hollow on the source electrode wiring forming portion. Etching through the entire surface to form a source electrode wiring via; forming the second insulating layer and the first insulating layer on the source electrode; And removing portions of the second insulating layer and the first insulating layer on the drain electrode to form vias for source electrode pads and vias for drain electrode pads, respectively. Filling the via pad for the electrode pad and the via for the drain electrode pad with a conductor to form a via pad for source electrode wiring, a source electrode pad, and a drain electrode pad, respectively.
본 발명의 또 다른 실시예에 따른 고전자이동도 트랜지스터의 제조방법은, 소스전극배선형성부위가 정의된 기판상에 베이스층을 형성하는 단계, 상기 소스전극배선형성부위의 상기 베이스층 상부에 중공이 형성된 소스전극과, 상기 소스전극배선형성부위와 이격된 상기 베이스층 상부에 드레인전극을 형성하는 단계, 상기 소스전극과 상기 드레인전극 및 베이스층의 전면에 제1 절연층을 형성하는 단계, 상기 소스전극과 상기 드레인전극 사이의 소정부위의 상기 제1 절연층을 제거하여 노출된 상기 베이스층상에 게이트전극을 형성하는 단계, 전면에 제2 절연층을 형성하는 단계, 상기 소스전극배선형성부위의 상기 소스전극 중공 내측의 상기 제2 절연층, 상기 제1 절연층, 상기 베이스층 및 상기 기판을 전면에서부터 소정의 깊이로 식각하여 소스전극배선용 비아를 형성하는 단계, 상기 소스전극 상부의 상기 제2 절연층 및 상기 제1 절연층 일부를 제거하고, 상기 드레인전극 상부의 상기 제2 절연층과 상기 제1 절연층의 일부를 제거하여 각각 소스전극패드용 비아 및 드레인전극패드용 비아를 형성하는 단계, 상기 소스전극배선용 비아, 상기 소스전극패드용 비아 및 상기 드레인전극패드용 비아를 전도체로 충진하여 각각 소스전극배선용 비아패드, 소스전극패드 및 드레인전극패드를 형성하는 단계, 상기 소스전극패드 상면부터, 상기 게이트전극과 상기 드레인전극 사이의 상기 제2 절연층 상면까지 필드플레이트를 형성하는 단계 및 상기 필드플레이트와 상기 드레인전극패드가 노출되도록 전면에 제3 절연층을 형성하는 단계를 포함한다.In another embodiment of the present invention, there is provided a method of manufacturing a high electron mobility transistor, including: forming a base layer on a substrate on which a source electrode wiring forming portion is defined, and hollowing an upper portion of the base layer on the source electrode wiring forming portion; Forming a drain electrode on the formed source electrode and the base layer spaced apart from the source electrode wiring forming portion, and forming a first insulating layer on an entire surface of the source electrode, the drain electrode and the base layer; Removing the first insulating layer at a predetermined portion between the source electrode and the drain electrode to form a gate electrode on the exposed base layer, forming a second insulating layer on the entire surface of the source electrode wiring forming portion The second insulating layer, the first insulating layer, the base layer, and the substrate inside the hollow of the source electrode are etched to a predetermined depth from an entire surface of the source electrode. Forming a wiring via, removing a portion of the second insulating layer and the first insulating layer on the source electrode, and removing a portion of the second insulating layer and the first insulating layer on the drain electrode; Forming vias for source electrode pads and vias for drain electrode pads, and filling the vias for source electrode wiring, the vias for source electrode pad and the vias for drain electrode pad with conductors, respectively; And forming a drain electrode pad, forming a field plate from an upper surface of the source electrode pad to an upper surface of the second insulating layer between the gate electrode and the drain electrode and exposing the field plate and the drain electrode pad. Forming a third insulating layer on the entire surface.
그리고, 상기 소스전극배선용 비아패드의 후단이 노출되도록 상기 기판 후면을 백-그라인딩하는 단계 및 상기 기판의 후면에 노출된 상기 비아패드와 연결되는 배면층을 형성하는 단계를 더 포함한다.The method may further include back-grinding the rear surface of the substrate so that the rear end of the via pad for source electrode wiring is exposed and forming a rear layer connected to the via pad exposed on the rear surface of the substrate.
본 발명의 고전자이동도 트랜지스터 및 그의 제조방법은 소스전극과 전기적으로 연결되는 소스전극배선을 소스전극 하부에 형성하는 공정에 있어서, 백-그라인딩 공정 전의 소자 형성 공정 중에 두꺼운 상태의 기판을 전면에서부터 소정 깊이로 식각하고 충진하여 소스전극배선용 비아패드를 형성함으로써, 백-그라인딩 공정을 진행하여 얇아진 기판의 후면에서부터 소정 깊이로 식각하는 종래 기술보다 식각속도가 증가하고, 식각 균일도를 향상시키며 기판의 크랙 발생을 억제하여 소자의 수율 및 소자의 신뢰성을 향상시키는 효과를 가진다.The high electron mobility transistor of the present invention and a method of manufacturing the same have a method of forming a source electrode wiring electrically connected to a source electrode under the source electrode. By etching and filling to a predetermined depth to form a via pad for source electrode wiring, the back-grinding process is performed to increase the etching rate, improve the etching uniformity, and improve the cracking of the substrate, compared to the conventional technique of etching to the predetermined depth from the back surface of the thinned substrate. It has the effect of suppressing generation to improve the yield of the device and the reliability of the device.
또한, 본 발명은 소스전극배선용 비아패드를 형성하고 백-그라인딩공정을 진행함으로써, 소스전극배선용 비아를 형성하기 위한 기판 식각 공정 없이 백-그라인딩 공정이 진행되기 때문에, 백-그라인딩 공정 시 고온 접합제보다 제거가 용이한 저온 접합제를 사용할 수 있어 공정이 용이하여 소자의 수율을 향상시키는 효과를 가진다.In addition, the present invention forms the via pad for the source electrode wiring and proceeds the back-grinding process, so that the back-grinding process is performed without the substrate etching process for forming the source electrode wiring via, so that the high temperature bonding agent in the back-grinding process is performed. A low temperature binder which can be more easily removed can be used to facilitate the process, thereby improving the yield of the device.
또한, 본 발명은 두꺼운 상태의 기판을 전면에서부터 소정 깊이로 식각하고 충진하여 소스전극배선용 비아패드를 형성함으로써, 소스전극배선용 비아 전부가 충진되기 때문에 종래 기술의 대부분이 빈 소스전극배선용 비아보다 열 전도율이 높아 소자의 열방출을 향상시켜 소자의 성능을 향상시키는 효과를 가진다.In addition, the present invention forms a via pad for source electrode wiring by etching and filling a thick substrate to a predetermined depth from the front surface, so that all the vias for the source electrode wiring are filled, so that most of the prior art have thermal conductivity more than that of the empty source electrode wiring via. This high effect has the effect of improving the heat dissipation of the device to improve the performance of the device.
또한, 본 발명은 두꺼운 상태의 기판을 전면에서부터 소정 깊이로 식각하고 충진하여 소스전극배선용 비아패드를 형성함으로써, 소자의 패키징을 위한 솔더본딩 시 사용되는 솔더와 플럭스가 기판으로 유입될 수 없어 소자의 신뢰성을 향상시키고 소자의 수명 단축을 방지하는 효과를 가진다.In addition, the present invention forms a via pad for source electrode wiring by etching and filling a thick substrate to a predetermined depth from the front, so that solder and flux used for solder bonding for packaging of the device cannot be introduced into the substrate. It has the effect of improving reliability and preventing shortening of the life of the device.
또한, 본 발명은 두꺼운 상태의 기판을 전면에서부터 소정 깊이로 식각함으로써, 얇은 상태의 기판을 후면에서부터 소정 깊이로 식각하는 것에 비해 안정적으로 식각할 수 있어 소스전극배선용 비아패드의 폭을 넓게 형성할 수 있어 전기 전도율 및 열 전도율을 향상시킬 수 있다.In addition, the present invention can be etched more stably by etching a thick substrate to a predetermined depth from the front surface, it is possible to form a wider width of the via pad for source electrode wiring than the etching of a thin substrate to a predetermined depth from the rear surface. There can improve the electrical conductivity and thermal conductivity.
도 1은 제1 실시예에 따른 고전자이동도 트랜지스터를 나타낸 단면도이다.1 is a cross-sectional view illustrating a high electron mobility transistor according to a first embodiment.
도 2는 도 1의 소스전극에 형성된 복수의 소스전극배선용 비아패드를 나타낸 평면도이다.FIG. 2 is a plan view illustrating a plurality of via pads for source electrode wiring formed in the source electrode of FIG. 1.
도 3은 도 1의 소스전극에 형성된 하나의 소스전극배선용 비아패드를 나타낸 평면도이다.3 is a plan view illustrating one via pad for source electrode wiring formed in the source electrode of FIG. 1.
도 4a 내지 도 4g는 제1 실시예에 따른 고전자이동도 트랜지스터의 제조방법을 나타내기 위한 단면도이다.4A to 4G are cross-sectional views illustrating a method of manufacturing a high mobility transistor according to a first embodiment.
도 5a 내지 도 5b는 제2 실시예에 따른 고전자이동도 트랜지스터의 제조방법을 나타내기 위한 단면도이다.5A through 5B are cross-sectional views illustrating a method of manufacturing a high mobility transistor according to a second embodiment.
- 부호의 설명 -Description of the sign
10 : 베이스층 11 : 기판10 base layer 11 substrate
12 : 핵형성층 13 : 버퍼층12: nucleation layer 13: buffer layer
15 : 배리어층 19 : 메탈마스크15: barrier layer 19: metal mask
BSP : 배면층 VA : 소스전극배선용 비아BSP: Back layer VA: Via for source electrode wiring
VAP : 소스전극배선용 비아패드 SE : 소스전극VAP: Via pad for source electrode wiring SE: Source electrode
PSE : 소스전극패드 GE : 게이트전극PSE: Source electrode pad GE: Gate electrode
DE : 드레인전극 PDE : 드레인전극패드DE: drain electrode PDE: drain electrode pad
PAS1 : 제1 절연층 PAS2 : 제2 절연층PAS1: First Insulation Layer PAS2: Second Insulation Layer
PAS3 : 제3 절연층 SD1 : 제1 시드층PAS3: 3rd insulating layer SD1: 1st seed layer
SD2 : 제2 시드층 SD3 : 제3 시드층SD2: Second Seed Layer SD3: Third Seed Layer
FDP : 필드플레이트 S : 단차부FDP: Field Plate S: Step
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.　Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
본 발명의 실시예들은 당해 기술 분야에서 통상의 지식을 가진 자에게 본 발명을 더욱 완전하게 설명하기 위하여 제공되는 것이며, 아래의 실시예들은 여러 가지 다른 형태로 변형될 수 있으며, 본 발명의 범위가 아래의 실시예들로 한정되는 것은 아니다. 오히려, 이들 실시예는 본 개시를 더욱 충실하고 완전하게 하며 당업자에게 본 발명의 사상을 완전하게 전달하기 위하여 제공되는 것이다.　Embodiments of the present invention are provided to more fully explain the present invention to those skilled in the art, and the following embodiments may be modified in many different forms, the scope of the present invention It is not limited to the following embodiments. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
본 명세서에서 사용된 용어는 특정 실시예를 설명하기 위하여 사용되며, 본 발명을 제한하기 위한 것이 아니다. 본 명세서에서 사용된 바와 같이 단수 형태는 문맥상 다른 경우를 분명히 지적하는 것이 아니라면, 복수의 형태를 포함할 수 있다. 또한, 본 명세서에서 사용되는 경우 "포함한다(comprise)" 및/또는"포함하는(comprising)"은 언급한 형상들, 숫자, 단계, 동작, 부재, 요소 및/또는 이들 그룹의 존재를 특정하는 것이며, 하나 이상의 다른 형상, 숫자, 동작, 부재, 요소 및/또는 그룹들의 존재 또는 부가를 배제하는 것이 아니다. 본 명세서에서 사용된 바와 같이, 용어 "및/또는"은 해당 열거된 항목 중 어느 하나 및 하나 이상의 모든 조합을 포함한다.　The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. Also, as used herein, "comprise" and / or "comprising" specifies the presence of the mentioned shapes, numbers, steps, actions, members, elements and / or groups of these. It is not intended to exclude the presence or the addition of one or more other shapes, numbers, acts, members, elements and / or groups. As used herein, the term "and / or" includes any and all combinations of one or more of the listed items.
본 명세서에서 제1, 제2 등의 용어가 다양한 부재, 영역 및/또는 부위들을 설명하기 위하여 사용되지만, 이들 부재, 부품, 영역, 층들 및/또는 부위들은 이들 용어에 의해 한정되어서는 안됨은 자명하다. 이들 용어는 특정 순서나 상하, 또는 우열을 의미하지 않으며, 하나의 부재, 영역 또는 부위를 다른 부재, 영역 또는 부위와 구별하기 위하여만 사용된다. 따라서, 이하 상술할 제1 부재, 영역 또는 부위는 본 발명의 가르침으로부터 벗어나지 않고서도 제2 부재, 영역 또는 부위를 지칭할 수 있다.Although the terms first, second, etc. are used herein to describe various members, regions, and / or portions, it is obvious that these members, components, regions, layers, and / or portions should not be limited by these terms. Do. These terms do not imply any particular order, up or down, or superiority, and are only used to distinguish one member, region or region from another member, region or region. Accordingly, the first member, region, or region described below may refer to the second member, region, or region without departing from the teachings of the present invention.
이하, 본 발명의 실시예들은 본 발명의 실시예들을 개략적으로 도시하는 도면들을 참조하여 설명한다. 도면들에 있어서, 예를 들면, 제조 기술 및/또는 공차에 따라, 도시된 형상의 변형들이 예상될 수 있다. 따라서, 본 발명의 실시예는 본 명세서에 도시된 영역의 특정 형상에 제한된 것으로 해석되어서는 아니 되며, 예를 들면 제조상 초래되는 형상의 변화를 포함하여야 한다.Hereinafter, embodiments of the present invention will be described with reference to the drawings schematically showing embodiments of the present invention. In the drawings, for example, variations in the shape shown may be expected, depending on manufacturing techniques and / or tolerances. Accordingly, embodiments of the present invention should not be construed as limited to the specific shapes of the regions shown herein, but should include, for example, changes in shape resulting from manufacturing.
제1 First 실시예Example
도 1은 제1 실시예에 따른 고전자이동도 트랜지스터를 나타낸 단면도이다. 도 1에 도시된 바와 같이, 제1 실시예에 따른 고전자이동도 트랜지스터는 소스전극배선형성부위가 정의된 기판(11), 기판(11) 상부에 형성되는 베이스층(10), 소스전극배선형성부위의 베이스층(10) 상부에 형성되고 중공이 형성된 소스전극(SE), 소스전극(SE)과 이격되어 베이스층(10) 상부에 형성되는 드레인전극(DE), 소스전극(SE)과 드레인전극(DE) 사이 베이스층(10) 상부에 형성되는 게이트전극(GE), 중공 내측으로 상기 소스전극배선형성부위의 상기 베이스층(10) 및 기판(11)을 전면에서부터 소정 깊이로 식각하고 전도체를 충진하여 형성되는 소스전극배선용 비아패드(VAP), 소스전극배선용 비아패드(VAP)에서 연장되어 일체로 형성되는 소스전극패드(PSE), 드레인전극(DE) 상에 형성되는 드레인전극패드(PDE), 베이스층(10) 상부에 형성되는 제1 절연층(PAS1) 및 소스전극패드(PSE)와 드레인전극패드(PDE) 사이에 형성되며 제1 절연층(PAS1)과 게이트전극(GE)을 덮는 제2 절연층(PAS2)을 포함한다.1 is a cross-sectional view illustrating a high electron mobility transistor according to a first embodiment. As shown in FIG. 1, the high electron mobility transistor according to the first embodiment includes a substrate 11 having a source electrode wiring forming portion, a base layer 10 formed on the substrate 11, and a source electrode wiring. A source electrode SE formed on the base layer 10 of the formation portion and having a hollow, spaced apart from the source electrode SE, and a drain electrode DE and a source electrode SE formed on the base layer 10. The gate electrode GE is formed on the base layer 10 between the drain electrodes DE, and the base layer 10 and the substrate 11 of the source electrode wiring forming portion are etched to a predetermined depth from the front side. A source electrode wiring via pad (VAP) formed by filling a conductor, a source electrode pad (PSE) extending from the source electrode wiring via pad (VAP), and a drain electrode pad formed on the drain electrode (DE). PDE), the first insulating layer (PAS1) and the source field formed on the base layer 10 A second insulating layer PAS2 is formed between the pole pad PSE and the drain electrode pad PDE and covers the first insulating layer PAS1 and the gate electrode GE.
또한, 소스전극패드(PSE) 상면부터 게이트전극(GE)과 드레인전극(DE) 사이의 제2 절연층(PAS2) 상면까지를 덮는 필드플레이트(FDP) 및 필드플레이트(FDP)와 드레인전극패드(PDE)가 노출되도록 전면에 형성되는 제3 절연층(PAS3)을 더 포함한다.In addition, the field plate FDP and the field plate FDP and the drain electrode pads covering the top surface of the source electrode pad PSE to the top surface of the second insulating layer PAS2 between the gate electrode GE and the drain electrode DE are formed. The display device may further include a third insulating layer PAS3 formed on the entire surface of the PDE to expose the PDE.
여기서, 기판(11) 상부에 베이스층(10)이 형성된다. 그리고 소스전극(SE)과 전기적으로 연결되는 소스전극패드(PSE)가 소스전극배선용 비아패드(VAP) 상부에 형성된다. 이때, 소스전극배선용 비아패드(VAP)는 소스전극패드(PSE)를 통하여 소스전극(SE)과 전기적으로 연결된다. 또한, 드레인전극(DE)과 전기적으로 연결되는 드레인전극패드(PDE)가 드레인전극(DE) 상부에 형성된다.Here, the base layer 10 is formed on the substrate 11. A source electrode pad PSE electrically connected to the source electrode SE is formed on the via pad VAP for source electrode wiring. In this case, the via pad VAP for source electrode wiring is electrically connected to the source electrode SE through the source electrode pad PSE. In addition, a drain electrode pad PDE electrically connected to the drain electrode DE is formed on the drain electrode DE.
상기 기판(11)은 소스전극배선형성부위, 상기 소스전극배선형성부위의 상측으로 단차(S)를 가지며 형성되는 소스전극패드형성부위 및 드레인전극패드 형성부위가 각각 정의되며, 사파이어(Al2O3), 질화 갈륨(GaN), 실리콘(Si), 실리콘카바이드(SiC) 등으로 이루어질 수 있다. 그리고 상기 베이스층(10)은 상기 소스전극배선형성부위의 둘레 외측을 따라 기판(11) 상부에 형성되며, 핵형성층(12) 상부에 버퍼층(13)이 형성되고, 버퍼층(13) 상부에 배리어층(15)이 형성되어 이루어진다.The substrate 11 has a source electrode wiring forming portion, a source electrode pad forming portion and a drain electrode pad forming portion, which are formed with a step S above the source electrode wiring forming portion and defined, respectively, and defined by sapphire (Al 2 O). 3 ), gallium nitride (GaN), silicon (Si), silicon carbide (SiC) and the like. The base layer 10 is formed on the substrate 11 along the outer circumference of the source electrode wiring forming portion, the buffer layer 13 is formed on the nucleation layer 12, and the barrier is formed on the buffer layer 13. Layer 15 is formed.
여기서, 핵형성층(12)과 버퍼층(13)과 배리어층(15)은 각각 알루미늄나이트라이드(AlN)와 갈륨나이트라이드(GaN)와 알루미늄 갈륨나이트라이드(AlGaN)로 이루어질 수 있다.The nucleation layer 12, the buffer layer 13, and the barrier layer 15 may be formed of aluminum nitride (AlN), gallium nitride (GaN), and aluminum gallium nitride (AlGaN), respectively.
소스전극(SE)은 상기 소스전극패드형성부위의 단차(S)가 만들어지도록 중공을 가지는 중공 형성체로써, 상기 베이스층(10) 상부에 형성된다. 그리고 드레인전극(DE)은 소스전극(SE)과 이격되어 상기 베이스층(10) 상부에 형성된다.The source electrode SE is a hollow body having a hollow so as to form a step S of the source electrode pad forming portion, and is formed on the base layer 10. The drain electrode DE is formed on the base layer 10 to be spaced apart from the source electrode SE.
게이트전극(GE)은 소스전극(SE)과 드레인전극(DE)사이 소정부위의 상기 베이스상(10)에 형성된다.The gate electrode GE is formed on the base 10 at a predetermined portion between the source electrode SE and the drain electrode DE.
이하, 상기 소스전극배선용 비아패드(VAP)에 대해 상세하게 설명한다.Hereinafter, the via pad VAP for source electrode wiring will be described in detail.
도 2는 도 1의 소스전극에 형성된 복수의 소스전극배선용 비아패드를 나타낸 평면도이고, 도 3은 도 1의 소스전극에 형성된 하나의 소스전극배선용 비아패드를 나타낸 평면도이다.FIG. 2 is a plan view illustrating a plurality of source electrode wiring via pads formed in the source electrode of FIG. 1, and FIG. 3 is a plan view illustrating one source electrode wiring via pad formed in the source electrode of FIG. 1.
상기 소스전극배선용 비아패드(VAP)는 기판(11)과 상기 베이스층(10)으로 둘러싸이고 상기 소스전극배선형성부위에 전면에서부터 소정 깊이로 식각하고 충진하여 형성된다. 그리고 소스전극배선용 비아패드(VAP)는 소스전극패드(PSE)와 일체형으로 형성된다.The via pad VAP for source electrode wiring is surrounded by the substrate 11 and the base layer 10 and is formed by etching and filling the source electrode wiring forming portion from a front surface to a predetermined depth. The via pad VAP for source electrode wiring is integrally formed with the source electrode pad PSE.
이때, 소스전극배선용 비아패드(VAP)는 기판(11)의 전면에서부터 소정 깊이로 식각하고 충진하여 형성되기 때문에, 전면측 방향인 상부부위의 직경이 후면측 방향인 하부부위보다 크게 형성될 수 있다. 이 경우, 후면에서부터 식각하는 종래 기술과 소스전극배선용 비아패드(VAP)의 모양과 반대로 형성된다. 하지만, 보쉬공정(Bosch process) 등으로 상부부위와 하부부위의 직경을 동일하게 식각 할 수도 있다.In this case, the via pad for source electrode wiring (VAP) is formed by etching and filling from the front surface of the substrate 11 to a predetermined depth, so that the diameter of the upper portion in the front side may be larger than the lower portion in the rear side. . In this case, it is formed to be opposite to the shape of the prior art and the source electrode wiring via pad (VAP) that is etched from the rear surface. However, it is also possible to etch the same diameter of the upper portion and the lower portion by the Bosch process.
그리고 소스전극배선용 비아패드(VAP)는 후술될 소스전극패드(PSE) 및 드레인전극패드(PDE) 형성 이후 백-그라인딩 공정 시, 기판(11)의 후면까지 관통된다. 그렇게 하면 종래 기술에 기판(11) 후면에서 소스전극배선용 비아패드(VAP)를 형성한 것과 같이 전면과 후면을 관통하는 소스전극배선용 비아패드(VAP)가 형성된다. 따라서 종래 기술에서처럼 후면에서 소스전극배선용 비아패드(VAP)를 형성할 경우 발생하는 문제점들을 해결하면서도 전면과 후면을 관통하는 소스전극배선용 비아패드(VAP)가 형성되는 것이다.The via pad VAP for source electrode wiring penetrates to the rear surface of the substrate 11 during the back-grinding process after forming the source electrode pad PSE and the drain electrode pad PDE to be described later. As a result, the source electrode wiring via pads VAP penetrating the front and rear surfaces are formed in the same manner as the source electrode wiring via pads VAP are formed on the rear surface of the substrate 11 in the related art. Therefore, the source electrode wiring via pads (VAP) penetrating the front and rear surfaces are formed while solving the problems caused when the source electrode wiring via pads (VAP) are formed on the rear surface, as in the prior art.
여기서, 소스전극배선용 비아패드(VAP)는 트랜지스터의 전기 전도율 및 열 전도율을 향상시키도록, 상기 소스전극배선형성부위를 구리(Cu), 금(Au) 등 도전성 충진물전도체로 충진하여 형성된다.Here, the via pad for source electrode wiring (VAP) is formed by filling the source electrode wiring forming portion with a conductive filler conductor such as copper (Cu), gold (Au) to improve the electrical conductivity and the thermal conductivity of the transistor.
또한, 상기 소스전극배선용 비아패드(VAP)는 도 2에 도시된 바와 같이, 소스전극(SE)에 적어도 하나 이상 형성되거나, 도 3에 도시된 바와 같이, 소스전극(SE)의 저면 면적의 50% 이상을 차지하며 형성될 수 있다. 모두 비아패드(VAP)를 통한 전기 전도율 및 열 전도율을 향상시키기 위함이다.In addition, at least one via pad VAP for source electrode wiring is formed in the source electrode SE, as shown in FIG. 2, or as shown in FIG. 3, 50 of the bottom area of the source electrode SE. It can be formed accounting for more than%. Both are to improve the electrical and thermal conductivity through the via pad (VAP).
전면에서 소스전극배선용 비아패드(VAP)를 형성할 경우, 그 개수를 하나만 형성할 수도 있고, 트랜지스터의 열방출 효율을 향상시키기 위하여 둘 이상의 복수개로 형성할 수 있다. 또한, 소스전극배선용 비아패드(VAP)를 하나만 형성할 경우에도 도 3에 도시된 것처럼 소스전극(SE)의 저면 면적의 50% 이상으로 소스전극배선용 비아패드(VAP)를 형성함으로써 전기 전도율 및 열 전도율을 향상시킬 수 있다. 소스전극배선용 비아패드(VAP)를 하나만 형성할 경우 도 3에 도시된 것처럼 그 크기를 소스전극(SE)의 크기와 모양에 근접하게 형성한다면 전기 전도율 및 열 전도율을 향상시킬 수 있다.When the via pad for source electrode wiring (VAP) is formed on the front surface, only one number may be formed, or two or more may be formed to improve the heat dissipation efficiency of the transistor. In addition, even when only one via pad VAP is formed for the source electrode wiring, as shown in FIG. 3, the via pad VAP for the source electrode wiring is formed with 50% or more of the bottom area of the source electrode SE, thereby providing electrical conductivity and heat. The conductivity can be improved. When only one via pad VAP for source electrode wiring is formed, as shown in FIG. 3, the electrical conductivity and thermal conductivity may be improved by forming the size close to the size and shape of the source electrode SE.
본 발명은 두꺼운 상태의 기판(11)을 전면에서부터 소정 깊이로 식각함으로써, 얇은 상태의 기판(11)을 후면에서부터 소정 깊이로 식각하는 것에 비해 안정적으로 식각할 수 있어 소스전극배선용 비아패드(VAP)의 폭을 넓게 형성할 수 있으므로 도 2와 도3과 같이 소스전극배선용 비아패드(VAP)를 형성할 수 있어 전기 전도율 및 열 전도율을 향상시킬 수 있다.According to the present invention, the substrate 11 in a thick state is etched to a predetermined depth from the front side, so that the substrate 11 in a thin state can be etched more stably than the etching depth from the back side to a predetermined depth, so that a via pad for source electrode wiring (VAP) Since the width of the film can be widened, the via pad for source electrode wiring (VAP) can be formed as shown in FIGS. 2 and 3, thereby improving the electrical conductivity and the thermal conductivity.
이하, 제1 실시예에 따른 고전자이동도 트랜지스터의 제조방법을 상세하게 설명한다.Hereinafter, the manufacturing method of the high electron mobility transistor according to the first embodiment will be described in detail.
도 4a 내지 도 4g는 제1 실시예에 따른 고전자이동도 트랜지스터의 제조방법을 나타내기 위한 단면도이다.4A to 4G are cross-sectional views illustrating a method of manufacturing a high mobility transistor according to a first embodiment.
고전자이동도 트랜지스터의 제조방법은, 소스전극배선형성부위가 정의된 기판(11) 상부에 베이스층(10)을 형성하는 단계, 소스전극배선형성부위의 상기 베이스층(10) 상부에 중공이 형성된 소스전극(SE)과, 상기 소스전극배선형성부위와 이격된 상기 베이스층(10) 상부에 드레인전극(DE)을 형성하는 단계, 소스전극(SE)과 드레인전극(DE) 및 베이스층(10)의 전면에 제1 절연층(PAS1)을 형성하는 단계, 소스전극(SE)과 드레인전극(DE) 사이의 소정부위의 제1 절연층(PAS1)을 제거하여 노출된 상기 베이스층(10) 상부에 게이트전극(GE)을 형성하는 단계, 전면에 제2 절연층(PAS2)을 형성하는 단계, 소스전극배선형성부위의 소스전극(SE) 중공 내측의 제2 절연층(PAS2), 제1 절연층(PAS1), 상기 베이스층(10) 및 기판(11)을 전면에서부터 소정의 깊이로 식각하여 소스전극배선용 비아(VA)를 형성하는 단계, 소스전극(SE) 상부의 제2 절연층(PAS2) 및 제1 절연층(PAS1) 일부를 제거하고, 드레인전극(DE) 상부의 제2 절연층(PAS2)과 제1 절연층(PAS1)의 일부를 제거하여 각각 소스전극패드용 비아(PSEVA) 및 드레인전극패드용 비아(PDEVA)를 형성하는 단계 및 소스전극배선용 비아(VAP), 소스전극패드용 비아(PSEVA) 및 드레인전극패드용 비아(PDEVA)를 전도체로 충진하여 각각 소스전극배선용 비아패드(VAP), 소스전극패드(PSE) 및 드레인전극패드(PDE)를 형성하는 단계를 포함한다.In the method of manufacturing a high electron mobility transistor, forming a base layer 10 on the substrate 11 where the source electrode wiring forming portion is defined, and forming a hollow on the base layer 10 above the source electrode wiring forming region. Forming a drain electrode DE on the formed source electrode SE and the base layer 10 spaced apart from the source electrode wiring forming portion, the source electrode SE, the drain electrode DE, and the base layer ( Forming a first insulating layer PAS1 on the entire surface of the substrate 10, removing the first insulating layer PAS1 at a predetermined portion between the source electrode SE and the drain electrode DE, and exposing the base layer 10. ) Forming a gate electrode GE on the top, forming a second insulating layer PAS2 on the front surface, a second insulating layer PAS2 inside the hollow of the source electrode SE on the source electrode wiring forming portion, and 1 The insulating layer PAS1, the base layer 10, and the substrate 11 are etched to a predetermined depth from the front surface, so that the via for source electrode wiring V Forming A) and removing a part of the second insulating layer PAS2 and the first insulating layer PAS1 on the source electrode SE, and forming the second insulating layer PAS2 and the drain electrode DE on the drain electrode DE. 1 by removing a portion of the insulating layer PAS1 to form a source electrode pad via (PSEVA) and a drain electrode pad via (PDEVA), a source electrode wiring via (VAP), and a source electrode pad via (PSEVA), respectively. And filling via electrodes for drain electrode pads (PDEVA) with a conductor to form via pads for source electrode wiring (VAP), source electrode pads (PSE), and drain electrode pads (PDE), respectively.
그리고, 소스전극배선용 비아패드(VAP)의 후단이 노출되도록 기판(11) 후면을 백-그라인딩하는 단계 및 기판(11)의 후면에 노출된 비아패드(VAP)와 연결되는 배면층(BSP)을 형성하는 단계를 더 포함한다.Then, back-grinding the rear surface of the substrate 11 so that the rear end of the via pad VAP for source electrode wiring is exposed, and the rear layer BSP connected to the via pad VAP exposed on the rear surface of the substrate 11. It further comprises the step of forming.
도 4a에 도시된 바와 같이, 제1 실시예에 따른 고전자이동도 트랜지스터의 제조방법은 기판(11) 상부에 베이스층(10)을 증착한다. 여기서, 베이스층은 핵형성층(12)과 버퍼층(13)과 배리어층(15)이 적층되어 이루어질 수 있다. 그리고 핵형성층(12)과 버퍼층(13)과 배리어층(15)은 각각 알루미늄나이트라이드(AlN)와 갈륨나이트라이드(GaN)와 알루미늄 갈륨나이트라이드(AlGaN)로 이루어질 수 있다. 그리고 상기 소스전극패드형성부위는 상기 소스전극배선형성부위보다 면적이 크다.As shown in FIG. 4A, in the method of manufacturing the high mobility transistor according to the first embodiment, the base layer 10 is deposited on the substrate 11. Here, the base layer may be formed by stacking the nucleation layer 12, the buffer layer 13, and the barrier layer 15. The nucleation layer 12, the buffer layer 13, and the barrier layer 15 may be made of aluminum nitride (AlN), gallium nitride (GaN), and aluminum gallium nitride (AlGaN), respectively. The source electrode pad forming portion is larger in area than the source electrode wiring forming portion.
도 4b에 도시된 바와 같이, 상기 베이스층(10) 상부에 상기 소스전극패드형성부위의 단차(S)가 만들어지도록 중공을 가지는 중공 형성체인 소스전극(SE)을 형성하고, 소스전극(SE)과 이격되어 상기 베이스층상에 드레인전극(DE)을 형성한다.As shown in FIG. 4B, a source electrode SE, which is a hollow body having a hollow, is formed on the base layer 10 so that the step S of the source electrode pad forming portion is formed, and the source electrode SE is formed. The drain electrode DE is formed on the base layer to be spaced apart from each other.
즉, 포토리소그래피(photolithography) 공정을 진행하기 위해, 감광막(미도시)을 도포한다. 이후, 소스전극(SE) 및 드레인전극(DE)이 형성될 부위에만 상기 감광막이 제거되도록, 상기 감광막을 선택적으로 노광 및 현상한다. 이때, 소스전극(SE) 및 드레인전극(DE)이 형성될 부위의 상기 베이스층(10)만 노출된다.That is, in order to proceed with a photolithography process, a photosensitive film (not shown) is coated. Thereafter, the photoresist film is selectively exposed and developed so that the photoresist film is removed only at a portion where the source electrode SE and the drain electrode DE are to be formed. In this case, only the base layer 10 of the portion where the source electrode SE and the drain electrode DE are to be formed is exposed.
그리고 상기 감광막을 마스크로 전면에 제1 도전층(미도시)을 증착하고, 리프트 오프(lift-off) 공정 등을 진행하여 상기 소스전극패드형성부위의 단차(S)가 만들어지도록 중공을 가지는 중공 형성체인 소스전극(SE), 및 소스전극(SE)과 이격된 드레인전극(DE)을 형성한다. 여기서, 상기 제1 도전층은 Ti/Al/Ni/Au, Ti/Al/Ti/Ni/Au 등의 오믹 접촉(ohmic contact)용 금속으로 이루어질 수 있다. 또한, 상기 제1 도전층을 증착한 후 열처리하여 오믹 접촉을 형성한다.The first conductive layer (not shown) is deposited on the entire surface using the photosensitive film as a mask, and a hollow having a hollow is formed so that a step S of the source electrode pad forming portion is formed by performing a lift-off process or the like. A source electrode SE, which is a formed body, and a drain electrode DE spaced apart from the source electrode SE are formed. Here, the first conductive layer may be made of an ohmic contact metal such as Ti / Al / Ni / Au, Ti / Al / Ti / Ni / Au. In addition, the first conductive layer is deposited and then heat treated to form an ohmic contact.
본 실시예에서는 소스전극(SE)이 중공형상인 경우로 설명하고 있으나, 소스전극(SE)이 중공형상이 아닌 경우도 가능하며, 이 경우에는 소스전극의 중앙부분을 포함하여 그 하방으로 식각할 수도 있으며, 그 공정은 당업자라면 이해할 수 있으므로 상세한 설명을 생략한다. 이러한 구조 및 공정은 후술되는 제2 실시예에서도 동일하게 적용될 수 있다.In the present embodiment, the source electrode SE is described as having a hollow shape. However, the source electrode SE may be non-hollow shape. In this case, the source electrode SE may be etched downward including the center portion of the source electrode. In addition, since the process can be understood by those skilled in the art, detailed description is omitted. This structure and process can be equally applied to the second embodiment described later.
도 4c에 도시된 바와 같이, 상기 소스전극(SE)과 드레인전극(DE)을 포함한 전면에 제1 절연층(PAS1)을 증착하고, 후공정에서 게이트전극(GE) 하부부위가 형성될 베이스층(10)이 노출되도록, 포토리소그래피 공정을 진행하여 제1 절연층(PAS1)을 선택 식각한다. 여기서, 제1 절연층(PAS1)은 질화규소(silicon nitride) 등으로 이루어진다.As shown in FIG. 4C, a first insulating layer PAS1 is deposited on the entire surface including the source electrode SE and the drain electrode DE, and a base layer in which a lower portion of the gate electrode GE is formed in a later process. The photolithography process is performed to expose 10, and the first insulating layer PAS1 is selectively etched. The first insulating layer PAS1 may be formed of silicon nitride or the like.
이후, 게이트전극(GE) 상부부위가 게이트전극(GE)의 하부부위보다 면적이 넓기 때문에, 포토리소그래피 공정을 진행하여 게이트전극(GE)의 상부부위가 안착될 제1 절연층(PAS1)을 노출시킨다. 노출된 제1 절연층(PAS1)부분은 게이트전극(GE)의 하부부위를 위해서 선택적으로 식각된 제1 절연층(PAS1)의 양측부분이다.Since the upper portion of the gate electrode GE is larger than the lower portion of the gate electrode GE, the photolithography process is performed to expose the first insulating layer PAS1 on which the upper portion of the gate electrode GE is to be seated. Let's do it. The exposed first insulating layer PAS1 may be both sides of the first insulating layer PAS1 selectively etched for the lower portion of the gate electrode GE.
제1 절연층(PAS1)그 다음, 게이트전극(GE)을 형성할 부위가 노출된 전면에 제2 도전층(미도시)을 증착하고 리프트 오프 공정을 진행하여 게이트전극(GE)을 형성한다. 여기서, 상기 제2 도전층은 Ni/Au, Ti/Al/Ni/Au, Ti/Al/Ti/Ni/Au 등으로 이루어질 수 있다. 그리고 게이트전극(GE)은 소스전극(SE)과 드레인전극(DE) 사이에 형성된다.First insulating layer PAS1 Next, a second conductive layer (not shown) is deposited on the entire surface of the portion where the gate electrode GE is to be exposed, and a lift off process is performed to form the gate electrode GE. Here, the second conductive layer may be made of Ni / Au, Ti / Al / Ni / Au, Ti / Al / Ti / Ni / Au, and the like. The gate electrode GE is formed between the source electrode SE and the drain electrode DE.
게이트전극(GE) 상부 및 제1 절연층(PAS1) 상부에 제2 절연층(PAS2)을 증착한다. 여기서, 제2 절연층(PAS2)은 질화규소(silicon nitride) 등으로 이루어진다.The second insulating layer PAS2 is deposited on the gate electrode GE and the first insulating layer PAS1. Here, the second insulating layer PAS2 is made of silicon nitride or the like.
도 4d에 도시된 바와 같이, 제2 절연층(PAS2) 상부에 제1 시드(seed)층(SD1)을 증착한다. 여기서, 제1 시드층(SD1)은 스퍼터링(sputter) 등의 증착공정을 이용하여 증착되고, Ti/Cu, Ti/Al, Ti/W, Ti/Au, Ti/Ni/Cu 등으로 이루어 질 수 있다.As shown in FIG. 4D, a first seed layer SD1 is deposited on the second insulating layer PAS2. Here, the first seed layer SD1 may be deposited using a deposition process such as sputtering, and may be formed of Ti / Cu, Ti / Al, Ti / W, Ti / Au, Ti / Ni / Cu, or the like. have.
이후, 제1 시드층(SD1) 상부에 포토리소그래피 공정을 진행하여 상기 소스전극배선형성부위 양측의 제1 시드층(SD1) 상부에 메탈마스크(19)를 성장시킨다. 이때, 상기 메탈마스크(19)는 약 7~10㎛로 성장시킨다. 여기서, 상기 메탈마스크(19)는 니켈(Ni), 구리(Cu), 금(Au) 등으로 이루어질 수 있다.Thereafter, a photolithography process is performed on the first seed layer SD1 to grow the metal mask 19 on the first seed layer SD1 on both sides of the source electrode wiring forming region. At this time, the metal mask 19 is grown to about 7 ~ 10㎛. Here, the metal mask 19 may be made of nickel (Ni), copper (Cu), gold (Au), or the like.
그 다음, 메탈마스크(19)를 마스크로 사용하여 상기 소스전극배선형성부위의 제1 시드층(SD1), 제2 절연층(PAS2), 제1 절연층(PAS1), 베이스층(10), 기판(11)을 전면에서부터 소정의 깊이로 식각하여 소스전극배선용 비아(VA)를 형성한다. 그 후, 제2 절연층(PAS2) 상부의 상기 제1 시드층(SD1)과 메탈마스크(19)를 제거한다.Next, using the metal mask 19 as a mask, the first seed layer SD1, the second insulating layer PAS2, the first insulating layer PAS1, the base layer 10, The substrate 11 is etched to a predetermined depth from the front surface to form vias VA for source electrode wiring. Thereafter, the first seed layer SD1 and the metal mask 19 on the second insulating layer PAS2 are removed.
소스전극배선용 비아(VA)를 식각하는 크기는 소스전극(SE)의 중공부위의 크기에 맞게 식각하거나, 도 4d처럼 소스전극(SE)의 중공부위의 크기보다 작게 식각을 진행할 수도 있다.The size of etching the source electrode wiring via VA may be etched according to the size of the hollow portion of the source electrode SE, or may be etched smaller than the size of the hollow portion of the source electrode SE, as shown in FIG. 4D.
도 4e에 도시된 바와 같이, 포토리소그래피 공정을 진행하여 상기 소스전극패드형성부위와 상기 드레인전극패드형성부위 각각의 제1, 제2 절연층(PAS1, PAS2)을 제거한다. 이때, 상기 소스전극패드형성부위에는 베이스층(10)과 소스전극(SE)이 노출된 소스전극패드용 비아(PSEVA)가 형성되고, 상기 드레인전극패드형성부위에는 드레인전극(DE)이 노출된 드레인전극패드용 비아(PDEVA)가 형성된다.As shown in FIG. 4E, the photolithography process is performed to remove the first and second insulating layers PAS1 and PAS2 of the source electrode pad forming portion and the drain electrode pad forming portion, respectively. The source electrode pad via PSEVA exposing the base layer 10 and the source electrode SE is formed on the source electrode pad forming portion, and the drain electrode DE is exposed on the drain electrode pad forming portion. A drain electrode via is formed.
도 4f에 도시된 바와 같이, 상기 소스전극패드용 비아(PSEVA)와 드레인전극패드용 비아(PDEVA)를 포함한 전면에 제2 시드층(SD2)을 증착하고, 포토리소그래피 공정을 진행하여 소스전극패드용 비아(PSEVA) 상부 및 드레인전극패드용 비아(PDEVA) 상부의 제2 시드층(SD2)만 노출시킨다.As shown in FIG. 4F, a second seed layer SD2 is deposited on the entire surface including the source electrode pad via PSEVA and the drain electrode pad via PDEVA, and a photolithography process is performed to proceed with the source electrode pad. Only the second seed layer SD2 on the top of the via PSEVA and the top of the drain electrode pad via PDEVA is exposed.
그리고 노출된 제2 시드층(SD2) 상부에 도전성 충진물을전도체를 성장시켜 상기 소스전극패드형성부위의 소스전극배선용 비아(VA)에 소스전극배선용 비아패드(VAP)를 형성하고, 소스전극배선용 비아패드(VAP) 상부의 소스전극패드용 비아(VA)에 소스전극배선용 비아패드(VAP)와 일체로 소스전극패드(PSE)를 형성하며, 상기 드레인전극패드형성부위의 드레인전극패드용 비아(PDEVA)에 드레인전극패드(PDE)를 형성한다.The conductive filler is grown on the exposed second seed layer SD2 to form a via pad for source electrode wiring in the via electrode VA for the source electrode pad forming portion, and a via for source electrode wiring. The source electrode pad PSE is formed integrally with the via pad VAP for source electrode wiring on the via pad VA on the pad VAP, and the drain electrode pad via PDEVA is formed on the drain electrode pad forming portion. ) To form a drain electrode pad (PDE).
그 후, 소스전극패드(PSE) 양측과 드레인전극패드(PDE) 양측 제2 절연층(PAS2) 상부의 제2 시드층(SD2)을 제거한다. 여기서, 제2 시드층(SD2)은 Ti/Cu, Ti/Al, Ti/Ni/Cu, Ti/Au 등으로 이루어질 수 있다. 그리고 상기 도전성 충진물은전도체는 구리(Cu), 금(Au) 등으로 이루어질 수 있다.Thereafter, the second seed layer SD2 on the second insulating layer PAS2 on both sides of the source electrode pad PSE and the drain electrode pad PDE is removed. Here, the second seed layer SD2 may be made of Ti / Cu, Ti / Al, Ti / Ni / Cu, Ti / Au, or the like. The conductive filler may be made of copper (Cu), gold (Au), or the like.
도 4g에 도시된 바와 같이, 소스전극패드(PSE) 및 드레인전극패드(PDE)가 형성된 기판(11)의 전면과 대향하는 기판(11)의 후면을 백-그라인딩 한다. 여기서, 기판(11) 하부의 백-그라인딩 공정으로 소스전극배선용 비아패드(VAP)의 후단이 노출된다. 이때, 소스전극배선용 비아패드(VAP)의 높이는 약 50㎛ ~ 100㎛이다. 그리고 상기 백-그라인딩 공정은 도시하지 않았으나, 저온 접합체, 캐리어 웨이퍼(carrier wafer) 등을 사용하여 진행한다. 이때, 상기 백-그라인딩 공정은 상기 소스전극배선용 비아(VA)를 형성하기 위한 기판 식각 공정 없이 진행되기 때문에, 고온 접합제보다 제거가 용이한 저온 접합제를 사용할 수 있다. 여기서, 상기 백-그라인딩 공정은 저온 접합제로써 저온 왁스(Wax)를 사용하여 진행한다.As shown in FIG. 4G, the rear surface of the substrate 11 facing the front surface of the substrate 11 on which the source electrode pad PSE and the drain electrode pad PDE are formed is back-grinded. Here, the rear end of the via pad VAP for source electrode wiring is exposed by a back-grinding process under the substrate 11. In this case, the height of the via pad VAP for source electrode wiring is about 50 μm to 100 μm. Although the back-grinding process is not shown, a low temperature bonded body, a carrier wafer, or the like is used. In this case, since the back-grinding process is performed without a substrate etching process for forming the source electrode wiring via, the low-temperature binder may be used more easily than the high-temperature binder. Here, the back-grinding process is performed using a low temperature wax (Wax) as a low temperature binder.
그 다음, 상기 소스전극배선용 비아패드(VAP)의 후단이 노출된 기판(11)의 후면에 제3 시드층(SD3)을 증착한 다음, 제3 시드층(SD3)으로부터 제3 도전층을 성장시켜 기판(11) 후면의 배면층(BSP)을 형성한다. 여기서, 제3 시드층(SD3)은 Ti/Cu, Ti/Al, Ti/W, Ti/Au, Ti/Ni/Cu 등으로 이루어질 수 있다. 그리고 상기 배면층(BSP)은 전기 전도율 및 열 전도율을 향상시키도록, 구리(Cu), 금(Au) 등의 도전성 물질전도체로 이루어질 수 있다.Next, a third seed layer SD3 is deposited on the rear surface of the substrate 11 where the rear end of the via pad VAP for source electrode wiring is exposed, and then a third conductive layer is grown from the third seed layer SD3. To form the back layer BSP on the back surface of the substrate 11. Here, the third seed layer SD3 may be made of Ti / Cu, Ti / Al, Ti / W, Ti / Au, Ti / Ni / Cu, or the like. The back layer BSP may be formed of a conductive material conductor such as copper (Cu), gold (Au), and the like to improve electrical conductivity and thermal conductivity.
상술한 바와 같이, 제1 실시예에 따른 고전자이동도 트랜지스터 및 그의 제조방법은 소스전극(SE)과 전기적으로 연결되는 소스전극배선을 소스전극 하부에 형성하는 공정에 있어서, 백-그라인딩 공정 전의 소자 형성 공정 중에 두꺼운 상태의 기판을 전면에서부터 소정 깊이로 식각하고 충진하여 소스전극배선용 비아패드(VAP)를 형성함으로써, 백-그라인딩 공정을 진행하여 얇아진 기판의 후면에서부터 소정 깊이로 식각하는 종래 기술보다 식각속도가 증가하고, 식각 균일도를 향상시키며 기판의 크랙 발생을 억제하여 소자의 수율 및 소자의 신뢰성을 향상시킬 수 있다.As described above, the high electron mobility transistor according to the first embodiment and the method of manufacturing the same have a method of forming a source electrode wiring electrically connected to the source electrode SE under the source electrode, before the back-grinding process. During the device formation process, a thick substrate is etched and filled from the front side to a predetermined depth to form a via pad for source electrode wiring (VAP), thereby performing a back-grinding process to etch to a predetermined depth from the rear surface of the thinned substrate. The etching rate is increased, the etching uniformity is improved, and the occurrence of cracks in the substrate can be suppressed to improve the yield of the device and the reliability of the device.
또한, 제1 실시예에 따른 고전자이동도 트랜지스터 및 그의 제조방법은 소스전극배선용 비아패드(VAP)를 형성하고 백-그라인딩 공정을 진행하기 때문에, 백-그라인딩 공정 시 고온 접합제보다 제거가 용이한 저온 접합제를 사용할 수 있어 공정이 용이하여 소자의 수율을 향상시킬 수 있다.In addition, the high electron mobility transistor according to the first embodiment and the manufacturing method thereof form a via pad (VAP) for source electrode wiring and perform a back-grinding process, so that the back-grinding process is easier to remove than a high temperature binder. One low temperature binder can be used and the process is easy to improve the yield of the device.
또한, 제1 실시예에 따른 고전자이동도 트랜지스터 및 그의 제조방법은 두꺼운 상태의 기판을 전면에서부터 소정 깊이로 식각하고 충진하여 소스전극배선용 비아패드(VAP)를 형성함으로써, 소스전극배선용 비아(VA) 전부가 충진되기 때문에 종래 기술의 대부분이 빈 소스전극배선용 비아(VA)보다 열전도도가 높아 소자의 열방출을 향상시켜 소자의 성능을 향상시킬 수 있다.In addition, the high electron mobility transistor according to the first embodiment and a method of manufacturing the same are etched and filled with a thick substrate from a front surface to a predetermined depth to form a via pad (VAP) for source electrode wiring, so that the source electrode wiring via (VA) is formed. Since most of the conventional technology is filled, the thermal conductivity is higher than that of the via source wiring via (VA), thereby improving heat dissipation of the device, thereby improving performance of the device.
또한, 제1 실시예에 따른 고전자이동도 트랜지스터 및 그의 제조방법은 상기와 같이 소스전극배선용 비아(VA) 전부가 충진되기 때문에, 소자의 패키징을 위한 솔더본딩 시 사용되는 솔더와 플럭스가 기판으로 유입될 수 없어 소자의 신뢰성을 향상시키고 소자의 수명 단축을 방지할 수 있다.In addition, since the high electron mobility transistor according to the first embodiment and the method of manufacturing the same are filled with all of the source electrode wiring vias as described above, the solder and the flux used for solder bonding for packaging the device are transferred to the substrate. It can not flow in, improving the reliability of the device and preventing the device from shortening its lifespan.
또한, 본 발명은 두꺼운 상태의 기판(11)을 전면에서부터 소정 깊이로 식각함으로써, 얇은 상태의 기판(11)을 후면에서부터 소정 깊이로 식각하는 것에 비해 안정적으로 식각할 수 있어 소스전극배선용 비아패드(VAP)의 폭을 넓게 형성할 수 있어 전기 전도율 및 열 전도율을 향상시킬 수 있다.In addition, by etching the thick substrate 11 to a predetermined depth from the front surface, the present invention can be etched more stably than the etching of the thin substrate 11 to a predetermined depth from the rear surface of the via pad for source electrode wiring ( The width of the VAP) can be widened to improve the electrical conductivity and the thermal conductivity.
제2 2nd 실시예Example
도 5a 및 5b는 제2 실시예에 따른 고전자이동도 트랜지스터의 제조방법을 나타낸 단면도이다. 상기 제2 실시예를 설명함에 있어, 제1 실시예와 동일한 구성 및 제조방법의 설명은 생략하기로 한다.5A and 5B are cross-sectional views illustrating a method of manufacturing a high mobility transistor according to a second embodiment. In the description of the second embodiment, description of the same configuration and manufacturing method as the first embodiment will be omitted.
도 5a 및 도 5b에 도시된 바와 같이, 제2 실시예에 따른 본 발명의 고전자이동도 트랜지스터는 제1 실시예에 따른 고전자이동도 트랜지스터의 구조에 필드플레이트(FDP)와 제3 절연층(PAS3)을 더 구비한 구조이다. 따라서, 나머지 동일한 구조에 대한 설명은 생략한다.5A and 5B, the high electron mobility transistor of the present invention according to the second embodiment has a field plate (FDP) and a third insulating layer in the structure of the high electron mobility transistor according to the first embodiment. It is a structure further equipped with (PAS3). Therefore, description of the remaining identical structure is omitted.
좀 더 설명하면, 도 4f의 구조에서, 소스전극패드(PSE) 상면부터, 게이트전극(GE)과 드레인전극(DE) 사이의 제2 절연층(SD2) 상면까지를 덮는 필드플레이트(FDP) 및 필드플레이트(FDP)와 드레인전극패드(PDE)가 노출되도록 전면에 형성되는 제3 절연층(PAS3)을 더 포함한다.More specifically, in the structure of FIG. 4F, the field plate FDP covering the upper surface of the source electrode pad PSE to the upper surface of the second insulating layer SD2 between the gate electrode GE and the drain electrode DE may be formed. The display device may further include a third insulating layer PAS3 formed on the entire surface of the field plate FDP and the drain electrode pad PDE.
이하, 제2 실시예에 따른 고전자이동도 트랜지스터의 제조방법을 상세하게 설명한다.Hereinafter, the manufacturing method of the high electron mobility transistor according to the second embodiment will be described in detail.
도 5a에 도시된 바와 같이, 포토리소그래피 공정, 제3 도전층 증착공정 등의 후속 공정을 진행하여 게이트전극(GE)과 드레인전극(DE) 사이의 제2 절연층(PAS2) 상부와, 소스전극패드(PSE) 상부의 필드플레이트형성부위에 소스전극패드(PSE)를 통하여 소스전극(SE)과 접촉되는 필드플레이트(FDP)를 형성한다.As shown in FIG. 5A, a subsequent process such as a photolithography process or a third conductive layer deposition process may be performed to form an upper portion of the second insulating layer PAS2 between the gate electrode GE and the drain electrode DE, and the source electrode. A field plate FDP is formed on the field plate forming portion on the pad PSE to contact the source electrode SE through the source electrode pad PSE.
여기서, 필드플레이트(FDP)는 Ti/Pt/Au, Ti/Al/Ni/Au, Ti/Al/Ti/Ni/Au 등으로 이루어질 수 있다.Here, the field plate (FDP) may be made of Ti / Pt / Au, Ti / Al / Ni / Au, Ti / Al / Ti / Ni / Au.
도 5b에 도시된 바와 같이, 필드플레이트(FDP)를 포함한 전면에 제3 절연층(PAS3)을 증착한다.As shown in FIG. 5B, a third insulating layer PAS3 is deposited on the entire surface including the field plate FDP.
그리고 소스전극패드(PSE) 상부의 필드플레이트(FDP)와 드레인전극패드(PDE)가 노출되도록, 포토리소그래피 공정을 진행하여 제3 절연층(PAS3)을 형성한 후 선택적으로 식각한다.Then, the photolithography process is performed to expose the field plate FDP and the drain electrode pad PDE on the source electrode pad PSE to form a third insulating layer PAS3 and then selectively etch it.
이후 후속 공정은 제1 실시예의 공정과 실질적으로 동일하다.The subsequent process is then substantially the same as the process of the first embodiment.
상기 제2 실시예에서의 소스전극배선용 비아패드(VAP)가 기판(11) 전면에서부터 소정의 깊이로 식각하고 충진하여 형성되는 경우의 효과 및 장점은 제1 실시예와 실질적으로 동일할 수 있다.Effects and advantages when the via pad for source electrode wiring VAP is formed by etching and filling the substrate 11 to a predetermined depth from the front surface of the substrate 11 may be substantially the same as those of the first embodiment.
이상, 본 발명의 실시예에 따른 고전자이동도 트랜지스터 및 그의 제조방법에 관한 구체적인 실시예에 관하여 설명하였으나, 본 발명의 범위에서 벗어나지 않는 한도 내에서는 여러 가지 실시 변형이 가능함은 자명하다.As mentioned above, although the specific embodiment regarding the high electron mobility transistor and its manufacturing method which concerns on the Example of this invention was described, it is obvious that various implementation can be changed as long as it does not depart from the scope of the present invention.
그러므로 본 발명의 범위에는 설명된 실시예에 국한되어 정해져서는 안 되며, 후술하는 특허청구범위뿐만 아니라 이 특허청구범위와 균등한 것들에 의해 정해져야 한다.Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined by the claims below and equivalents thereof.
즉, 전술된 실시예는 모든 면에서 예시적인 것이며, 한정적인 것이 아닌 것으로 이해되어야 하며, 본 발명의 범위는 상세한 설명보다는 후술될 특허청구범위에 의하여 나타내어지며, 그 특허청구범위의 의미 및 범위 그리고 그 등가 개념으로부터 도출되는 모든 변경 또는 변형된 형태가 본 발명의 범위에 포함되는 것으로 해석되어야 한다.In other words, the foregoing embodiments are to be understood in all respects as illustrative and not restrictive, the scope of the invention being indicated by the following claims rather than the detailed description, and the meaning and scope of the claims and All changes or modifications derived from the equivalent concept should be interpreted as being included in the scope of the present invention.
본 발명은 고전자이동도 트랜지스터의 크기를 최소화할 수 있으며, 열방출이 용이하도록 하여 신뢰성을 향상시킬 수 있는 것으로 산업상 이용 가능성이 있다.The present invention can minimize the size of the high-mobility mobility transistor, and to facilitate heat dissipation, thereby improving reliability, which may be industrially applicable.

Claims (17)

  1. 소스전극배선형성부위가 정의된 기판;A substrate on which a source electrode wiring forming portion is defined;
    상기 기판 상부에 형성되는 베이스층;A base layer formed on the substrate;
    상기 소스전극배선형성부위의 상기 베이스층 상부에 형성되고 중공이 형성된 소스전극;A source electrode formed on the base layer on the source electrode wiring forming portion and having a hollow;
    상기 소스전극과 이격되어 상기 베이스층 상부에 형성되는 드레인전극;A drain electrode spaced apart from the source electrode and formed on the base layer;
    상기 소스전극과 상기 드레인전극 사이 상기 베이스층 상부에 형성되는 게이트전극;A gate electrode formed on the base layer between the source electrode and the drain electrode;
    상기 소스전극의 중공 내측 상기 소스전극배선형성부위의 상기 베이스층 및 상기 기판을 전면에서부터 소정 깊이로 식각하고 전도체를 충진하여 형성되는 소스전극배선용 비아패드;A via pad for source electrode wiring formed by etching the base layer and the substrate of the source electrode wiring forming portion in the hollow inner side of the source electrode to a predetermined depth from a front surface and filling a conductor;
    상기 소스전극배선용 비아패드에서 연장되어 일체로 형성되는 소스전극패드;A source electrode pad extending integrally from the via pad for source electrode wiring;
    상기 드레인전극 상에 형성되는 드레인전극패드;A drain electrode pad formed on the drain electrode;
    상기 베이스층상에 형성되는 제1 절연층; 및A first insulating layer formed on the base layer; And
    상기 소스전극패드와 상기 드레인전극패드 사이에 형성되며 상기 제1 절연층과 상기 게이트전극을 덮는 제2 절연층을 포함하는 고전자이동도 트랜지스터.And a second insulating layer formed between the source electrode pad and the drain electrode pad and covering the first insulating layer and the gate electrode.
  2. 제1항에 있어서,The method of claim 1,
    상기 소스전극패드 상면부터 상기 게이트전극과 상기 드레인전극 사이의 상기 제2 절연층 상면까지를 덮는 필드플레이트; 및A field plate covering an upper surface of the source electrode pad to an upper surface of the second insulating layer between the gate electrode and the drain electrode; And
    상기 필드플레이트와 상기 드레인전극패드가 노출되도록 전면에 형성되는 제3 절연층을 더 포함하는 것을 특징으로 하는 고전자이동도 트랜지스터.And a third insulating layer formed on a front surface of the field plate and the drain electrode pad to expose the field plate and the drain electrode pad.
  3. 제 1항에 있어서,The method of claim 1,
    상기 소스전극배선용 비아패드, 상기 소스전극패드 및 상기 드레인전극패드는 구리, 금 중 어느 하나인 고전자이동도 트랜지스터.The via pad for source electrode wiring, the source electrode pad and the drain electrode pad are any one of copper and gold.
  4. 제 1항에 있어서, 상기 소스전극배선용 비아패드는,The via pad of claim 1, wherein the via pad for source electrode wiring comprises:
    전면측 방향인 상부부위의 직경이 후면측 방향인 하부부위의 직경보다 큰 고전자이동도 트랜지스터.A high electron mobility transistor having a diameter of an upper portion in a front side larger than a diameter of a lower portion in a rear side.
  5. 제 1항에 있어서, 상기 소스전극배선용 비아패드는,The via pad of claim 1, wherein the via pad for source electrode wiring comprises:
    상기 기판의 후면까지 관통된 구조인 것을 특징으로 하는 고전자이동도 트랜지스터.A high electron mobility transistor, characterized in that the structure penetrates to the back of the substrate.
  6. 제 1항에 있어서, 상기 소스전극배선용 비아패드는,The via pad of claim 1, wherein the via pad for source electrode wiring comprises:
    상기 소스전극에 적어도 하나 이상 형성되는 것을 특징으로 하는 고전자이동도 트랜지스터.At least one high electron mobility transistor, characterized in that formed on the source electrode.
  7. 제 1항에 있어서, 상기 소스전극배선용 비아패드는,The via pad of claim 1, wherein the via pad for source electrode wiring comprises:
    상기 소스전극의 저면 면적의 50% 이상을 차지하는 것을 특징으로 하는 고전자이동도 트랜지스터.The high electron mobility transistor, characterized in that occupies more than 50% of the bottom area of the source electrode.
  8. 제 1항에 있어서, 상기 베이스층은,The method of claim 1, wherein the base layer,
    갈륨나이트라이드(GaN)층을 포함하는 것을 특징으로 하는 고전자이동도 트랜지스터.A high electron mobility transistor comprising a gallium nitride (GaN) layer.
  9. 소스전극배선형성부위가 정의된 기판상에 베이스층을 형성하는 단계;Forming a base layer on a substrate on which a source electrode wiring forming portion is defined;
    상기 소스전극배선형성부위의 상기 베이스층 상부에 중공이 형성된 소스전극과 상기 소스전극배선형성부위와 이격된 상기 베이스층 상부에 드레인전극을 형성하는 단계;Forming a source electrode having a hollow formed on the base layer of the source electrode wiring forming portion and a drain electrode on the base layer spaced apart from the source electrode wiring forming portion;
    상기 소스전극과 상기 드레인전극 및 베이스층의 전면에 제1 절연층을 형성하는 단계;Forming a first insulating layer on an entire surface of the source electrode, the drain electrode, and the base layer;
    상기 소스전극과 상기 드레인전극 사이의 소정부위의 상기 제1 절연층을 제거하여 노출된 상기 베이스층상에 게이트전극을 형성하는 단계;Removing the first insulating layer at a predetermined portion between the source electrode and the drain electrode to form a gate electrode on the exposed base layer;
    전면에 제2 절연층을 형성하는 단계;Forming a second insulating layer on the front surface;
    상기 소스전극배선형성부위의 상기 소스전극 중공 내측의 상기 제2 절연층, 상기 제1 절연층, 상기 베이스층 및 상기 기판을 전면에서부터 소정의 깊이로 식각하여 소스전극배선용 비아를 형성하는 단계;Forming vias for source electrode wiring by etching the second insulating layer, the first insulating layer, the base layer, and the substrate to a predetermined depth from an entire surface of the source electrode wiring hollow at the source electrode wiring forming portion;
    상기 소스전극 상부의 상기 제2 절연층 및 상기 제1 절연층 일부를 제거하고, 상기 드레인전극 상부의 상기 제2 절연층과 상기 제1 절연층의 일부를 제거하여 각각 소스전극패드용 비아 및 드레인전극패드용 비아를 형성하는 단계; 및A portion of the second insulating layer and the first insulating layer on the source electrode is removed, and a portion of the second insulating layer and the first insulating layer on the drain electrode is removed, so that a via and a drain for the source electrode pad are respectively removed. Forming vias for electrode pads; And
    상기 소스전극배선용 비아, 상기 소스전극패드용 비아 및 상기 드레인전극패드용 비아를 전도체로 충진하여 각각 소스전극배선용 비아패드, 소스전극패드 및 드레인전극패드를 형성하는 단계를 포함하는 고전자이동도 트랜지스터의 제조방법.Filling the vias for the source electrode wirings, the vias for the source electrode pads, and the vias for the drain electrode pads with a conductor to form via pads for forming the source electrode wirings, the source electrode pads, and the drain electrode pads, respectively; Manufacturing method.
  10. 소스전극배선형성부위가 정의된 기판상에 베이스층을 형성하는 단계;Forming a base layer on a substrate on which a source electrode wiring forming portion is defined;
    상기 소스전극배선형성부위의 상기 베이스층 상부에 중공이 형성된 소스전극과 상기 소스전극배선형성부위와 이격된 상기 베이스층 상부에 드레인전극을 형성하는 단계;Forming a source electrode having a hollow formed on the base layer of the source electrode wiring forming portion and a drain electrode on the base layer spaced apart from the source electrode wiring forming portion;
    상기 소스전극과 상기 드레인전극 및 베이스층의 전면에 제1 절연층을 형성하는 단계;Forming a first insulating layer on an entire surface of the source electrode, the drain electrode, and the base layer;
    상기 소스전극과 상기 드레인전극 사이의 소정부위의 상기 제1 절연층을 제거하여 노출된 상기 베이스층상에 게이트전극을 형성하는 단계;Removing the first insulating layer at a predetermined portion between the source electrode and the drain electrode to form a gate electrode on the exposed base layer;
    전면에 제2 절연층을 형성하는 단계;Forming a second insulating layer on the front surface;
    상기 소스전극배선형성부위의 상기 소스전극 중공 내측의 상기 제2 절연층, 상기 제1 절연층, 상기 베이스층 및 상기 기판을 전면에서부터 소정의 깊이로 식각하여 소스전극배선용 비아를 형성하는 단계;Forming vias for source electrode wiring by etching the second insulating layer, the first insulating layer, the base layer, and the substrate to a predetermined depth from an entire surface of the source electrode wiring hollow at the source electrode wiring forming portion;
    상기 소스전극 상부의 상기 제2 절연층 및 상기 제1 절연층 일부를A portion of the second insulating layer and the first insulating layer on the source electrode
    제거하고, 상기 드레인전극 상부의 상기 제2 절연층과 상기 제1 절연층의 일부를 제거하여 각각 소스전극패드용 비아 및 드레인전극패드용 비아를 형성하는 단계;Removing and removing a portion of the second insulating layer and the first insulating layer on the drain electrode to form vias for source electrode pads and vias for drain electrode pads, respectively;
    상기 소스전극배선용 비아, 상기 소스전극패드용 비아 및 상기 드레인전극패드용 비아를 전도체로 충진하여 각각 소스전극배선용 비아패드, 소스전극패드 및 드레인전극패드를 형성하는 단계; 상기 소스전극패드 상면부터 상기 게이트전극과 상기 드레인전극 사이의 상기 제2 절연층 상면까지 필드플레이트를 형성하는 단계; 및 상기 필드플레이트와 상기 드레인전극패드가 노출되도록 전면에 제3 절연층을 형성하는 단계를 포함하는 것을 특징으로 하는 고전자이동도 트랜지스터의 제조방법.Filling the source electrode wiring via, the source electrode pad via and the drain electrode pad via with a conductor to form a via pad for source electrode wiring, a source electrode pad and a drain electrode pad, respectively; Forming a field plate from an upper surface of the source electrode pad to an upper surface of the second insulating layer between the gate electrode and the drain electrode; And forming a third insulating layer on a front surface of the field plate and the drain electrode pad to expose the field plate and the drain electrode pad.
  11. 제 9항 또는 제 10항에 있어서,The method according to claim 9 or 10,
    상기 소스전극배선용 비아패드의 후단이 노출되도록 상기 기판 후면을 백-그라인딩하는 단계; 및 Back-grinding the back surface of the substrate such that a rear end of the via pad for source electrode wiring is exposed; And
    상기 기판의 후면에 노출된 상기 비아패드와 연결되는 배면층을 형성하는 단계를 더 포함하는 고전자이동도 트랜지스터의 제조방법.And forming a back layer connected to the via pad exposed on the rear surface of the substrate.
  12. 제 9항 또는 제 10항에 있어서, 상기 소스전극배선용 비아패드는,The via pad of claim 9 or 10, wherein the via pad for source electrode wiring comprises:
    트랜지스터의 열방출을 향상시키도록, 구리, 금 중 어느 하나인 고전자이동도 트랜지스터의 제조방법.A method for manufacturing a high electron mobility transistor, which is either copper or gold, to improve heat dissipation of the transistor.
  13. 제 9항 또는 제 10항에 있어서, 상기 소스전극배선용 비아패드를 형성하는 단계는,The method of claim 9, wherein the forming of the via pad for source electrode wiring comprises:
    상기 소스전극과 인접한 상부부위의 직경이 상기 기판과 인접한 하부부위의 직경보다 큰 상기 소스전극배선용 비아패드를 형성하는 고전자이동도 트랜지스터의 제조방법.And a via pad for source electrode wiring having a diameter of an upper portion adjacent to the source electrode larger than a diameter of a lower portion adjacent to the substrate.
  14. 제 9항 또는 제 10항에 있어서, 상기 소스전극배선용 비아패드는,The via pad of claim 9 or 10, wherein the via pad for source electrode wiring comprises:
    상기 소스전극에 적어도 하나 이상 형성하는 것을 특징으로 하는 고전자이동도 트랜지스터의 제조방법.At least one method for manufacturing a high electron mobility transistor, characterized in that formed on the source electrode.
  15. 제 9항 또는 제 10항에 있어서, 상기 소스전극배선용 비아패드의 상면 면적은,The method of claim 9 or 10, wherein the top surface area of the via pad for source electrode wiring,
    상기 소스전극의 저면 면적의 50% 이상을 차지하는 것을 특징으로 하는 고전자이동도 트랜지스터의 제조방법.And at least 50% of the bottom area of the source electrode.
  16. 제 9항 또는 제 10항에 있어서, 상기 베이스층은,The method of claim 9 or 10, wherein the base layer,
    갈륨나이트라이드(GaN)층을 포함하는 것을 특징으로 하는 고전자이동도 트랜지스터의 제조방법.A method of manufacturing a high electron mobility transistor comprising a gallium nitride (GaN) layer.
  17. 제 9항 또는 제 10항에 있어서, 상기 소스전극배선용 비아패드는,The via pad of claim 9 or 10, wherein the via pad for source electrode wiring comprises:
    상기 소스전극패드와 일체로 형성되는 것을 특징으로 하는 고전자이동도 트랜지스터의 제조방법.The method of manufacturing a high electron mobility transistor, characterized in that formed integrally with the source electrode pad.
PCT/KR2016/011538 2015-10-23 2016-10-14 High electron mobility transistor and method for manufacturing same WO2017069462A1 (en)

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KR20140042470A (en) * 2012-09-28 2014-04-07 삼성전자주식회사 Normally off high electron mobility transistor
KR20150109213A (en) * 2014-03-19 2015-10-01 에스케이하이닉스 주식회사 Semiconductor device having through silicon via and the method for manufacturing of the same

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US20090230429A1 (en) * 2005-06-10 2009-09-17 Nec Corporation Field effect transistor
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US20120104580A1 (en) * 2010-10-29 2012-05-03 Alpha And Omega Semiconductor Incorporated Substrateless power device packages
KR20140042470A (en) * 2012-09-28 2014-04-07 삼성전자주식회사 Normally off high electron mobility transistor
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