WO2017049835A1 - 薄膜晶体管及其制备方法、阵列基板和显示装置 - Google Patents

薄膜晶体管及其制备方法、阵列基板和显示装置 Download PDF

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WO2017049835A1
WO2017049835A1 PCT/CN2016/073297 CN2016073297W WO2017049835A1 WO 2017049835 A1 WO2017049835 A1 WO 2017049835A1 CN 2016073297 W CN2016073297 W CN 2016073297W WO 2017049835 A1 WO2017049835 A1 WO 2017049835A1
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electrode
layer
film transistor
thin film
oxidation preventing
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PCT/CN2016/073297
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English (en)
French (fr)
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黄勇潮
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京东方科技集团股份有限公司
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Priority to US15/326,399 priority Critical patent/US10224409B2/en
Priority to EP16822102.6A priority patent/EP3179518B1/en
Publication of WO2017049835A1 publication Critical patent/WO2017049835A1/zh

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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a thin film transistor, a method for fabricating the same, an array substrate, and a display device.
  • the thin film transistor 10 includes a gate electrode 102, a gate insulating layer 103, a semiconductor active layer 104, a source electrode 105, and a drain electrode 106 which are disposed on a base substrate 101.
  • the gate electrode 102, the source electrode 105, and the drain electrode 106 are generally made of a metal material having a low electrical resistance, such as copper (Cu), Cu alloy, aluminum (Al), silver (Ag), or the like.
  • Cu and Cu alloys Compared with Al, Cu and Cu alloys have better electrical conductivity, but copper is more active and easy to oxidize. When Cu and Cu alloys are used as electrode materials, Cu oxidation caused by the process needs to be considered. Therefore, it is more commonly used at present. Al is used as the electrode material.
  • Embodiments of the present invention provide a thin film transistor and a method of fabricating the same, an array substrate, and a display device in which Cu and a Cu alloy can be used as an electrode material while preventing oxidation of Cu.
  • a thin film transistor including a gate electrode, a gate insulating layer, a semiconductor active layer, a source electrode, and a drain electrode disposed on a substrate; the gate electrode and/or the source electrode and the drain Extremely made of Cu or Cu alloy material; the thin film transistor further comprises: an oxidation preventing layer made of a topological insulator material, the anti-oxidation layer being disposed on the gate electrode made of Cu or Cu alloy material and/or The source electrode and the drain electrode are over and in contact with the drain electrode.
  • the gate electrode, the source electrode and the drain electrode are made of Cu or Cu alloy material.
  • the oxidation preventing layer includes a first oxidation preventing layer disposed above and in contact with the gate electrode, and the second oxidation preventing layer is disposed at the source The electrode and the drain electrode are in contact with each other and with both.
  • the semiconductor active layer is a graphene nitride active layer.
  • the gate insulating layer is a silicon nitride layer, the silicon nitride layer is in contact with the nitride graphene active layer;
  • the oxidation preventing layer comprises a first oxidation preventing layer, the first anti-oxidation layer
  • An oxide layer is disposed over and in contact with the gate electrode, the silicon nitride layer being in contact with the first oxidation protecting layer.
  • the gate insulating layer includes a first silicon nitride layer, a second silicon nitride layer, and a silicon dioxide layer between the first and second silicon nitride layers, the first nitridation a silicon layer is in contact with the active layer of graphene nitride;
  • the oxidation preventing layer includes a first oxidation preventing layer, and the first oxidation preventing layer is disposed above and in contact with the gate electrode, the second nitriding A silicon layer is in contact with the first oxidation protecting layer.
  • the projection of the oxidation preventing layer on the substrate substrate completely covers the gate electrode and/or the source electrode and the substrate made of Cu or Cu alloy material in the direction perpendicular to the substrate.
  • the projection of the drain electrode on the substrate is described.
  • the topological insulator includes at least one of a HgTe quantum well, a BiSb alloy, Bi 2 Se 3 , Sb 2 Te 3 , and Bi 2 Te 3 .
  • an array substrate including the thin film transistor described above.
  • the array substrate further includes a pixel electrode or an anode connected to a drain electrode of the thin film transistor; and the material of the pixel electrode or the anode is a topological insulator.
  • the array substrate further includes a common electrode; wherein the material of the common electrode is indium tin oxide, indium zinc oxide or a topological insulator.
  • the array substrate further includes a gate line connected to a gate electrode of the thin film transistor, a gate line lead connected to the gate line, a data line connected to the source electrode, and a connection with the data line.
  • Data line lead when the anti-oxidation layer made of the topological insulator material is over the gate electrode made of Cu or Cu alloy material and is in contact with the gate electrode, the oxidation preventing layer is also located at the gate line and Above the gate line lead and in contact with both; and/or when an anti-oxidation layer made of a topological insulator material is over the source electrode and the drain electrode made of Cu or Cu alloy material and both When both are in contact, the oxidation protecting layer is also located above the data line and the data line lead and in contact with both.
  • a display device including the array substrate described above.
  • a method of fabricating a thin film transistor including forming a gate electrode, a gate insulating layer, a semiconductor active layer, a source electrode, and a drain electrode on a base substrate; the gate electrode and/or the source electrode and The leak The electrode is made of a Cu or Cu alloy material; the method further includes forming an oxidation preventing layer using a topological insulator material while forming a gate electrode and/or a source electrode and a drain electrode using a Cu or Cu alloy material; The oxidation preventing layer is located above the gate electrode and/or the source and drain electrodes made of Cu or Cu alloy material.
  • the step of forming the oxidation preventing layer using the topological insulator material comprises: completely covering the gate electrode made of Cu or Cu alloy material with the projection of the oxidation preventing layer on the substrate substrate in the direction of the vertical substrate. Projection of source and drain electrodes on a substrate.
  • the step of forming the semiconductor active layer comprises: forming a graphene nitride active layer by chemical vapor deposition in an atmosphere of hydrogen and argon using ammonia gas and methane as a reaction source.
  • Embodiments of the present invention provide a thin film transistor and a method for fabricating the same, an array substrate, and a display device.
  • Cu or a Cu alloy is used as an electrode of a thin film transistor, which has good electrical conductivity and low power consumption, so that the performance of the thin film transistor is improved. it is good.
  • the anti-oxidation layer made of the topological insulator material can protect the electrodes of the Cu or Cu alloy material in each preparation process of the thin film transistor. Achieve the purpose of preventing oxidation of Cu.
  • the topological insulator due to the good electrical conductivity of the topological insulator, the impedance between the electrode and the electrode of the Cu or Cu alloy material is small, which can avoid the influence on the performance of the thin film transistor, and the topological insulator also has good thermal conductivity and can be avoided. The problem of deterioration in performance caused by heat generation in the thin film transistor.
  • FIG. 1 is a schematic structural view of a thin film transistor provided by the prior art
  • FIG. 2 is a schematic structural diagram of an example 1 of a thin film transistor according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of an example 2 of a thin film transistor according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of an example 3 of a thin film transistor according to an embodiment of the present invention.
  • 5a is a schematic structural diagram of an example 4 of a thin film transistor according to an embodiment of the present invention.
  • FIG. 5b is a schematic structural diagram of a fifth example of a thin film transistor according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of an example 1 of an array substrate applied to a liquid crystal display device according to an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of an array substrate applied to an organic electroluminescent diode display device according to an embodiment of the present invention. Schematic;
  • FIG. 8 is a schematic structural diagram of an example 2 of an array substrate applied to a liquid crystal display device according to an embodiment of the present disclosure
  • FIG. 9a is a schematic top view of an array substrate according to an embodiment of the present invention.
  • Figure 9b is a cross-sectional view taken along line A-A and B-B of Figure 9a;
  • Figure 9c is a cross-sectional view taken along line C-C and D-D of Figure 9a.
  • 10-thin film transistor 101-substrate substrate; 102-gate electrode; 103-gate insulating layer; 104-semiconductor active layer; 105-source electrode; 106-drain electrode; 1041-graphene nitride active layer; - silicon nitride layer; 1032-silicon dioxide layer; 20-pixel electrode; 30-common electrode; 40-anode; 50-functional layer of organic material; 60-cathode; 70-protective layer; 801-gate line; Gate line lead; 901-data line; 902-data line lead; 100-display area; 200-wiring area.
  • the embodiment of the present invention provides a thin film transistor 10 including a gate electrode 102, a gate insulating layer 103, a semiconductor active layer 104, and a source electrode 105 disposed on a base substrate 101, as shown in FIGS. 2-4.
  • the drain electrode 106 wherein the gate electrode 102 and/or the source electrode 105 and the drain electrode 106 are made of Cu or Cu alloy material; on the basis of the thin film transistor 10, the thin film transistor 10 further comprises: an anti-oxidation layer made of a topological insulator material.
  • the oxidation preventing layer is disposed over and in contact with the gate electrode 102 and/or the source electrode 105 and the drain electrode 106 made of a Cu or Cu alloy material.
  • the gate electrode 102 may be made of Cu or Cu alloy material, the source electrode 105 and The drain electrode 106 may employ other conductive materials that are less susceptible to oxidation, such as Al.
  • the anti-oxidation layer may include a first oxidation preventing layer 107 disposed above the gate electrode 102 and in contact with the gate electrode 102.
  • the thickness of the first oxidation preventing layer 107 may be several hundred
  • the source electrode 105 and the drain electrode 106 may be made of Cu or Cu alloy material, and the gate electrode 102 may be made of other conductive materials that are less susceptible to oxidation, such as Al.
  • the anti-oxidation layer may include a second oxidation preventing layer 108 disposed above the source electrode 105 and the drain electrode 106 and in contact with the source electrode 105 and the drain electrode 106.
  • the thickness of the second oxidation preventing layer 108 may be several hundred
  • the gate electrode 102, the source electrode 105, and the drain electrode 106 may each be made of a Cu or Cu alloy material.
  • the above oxidation preventing layer may include a first oxidation protecting layer 107 and a second oxidation preventing layer 108.
  • the first oxidation protecting layer 107 is disposed above the gate electrode 102 and is in contact with the gate electrode 102.
  • the second oxidation protecting layer 108 is disposed above the source electrode 105 and the drain electrode 106 and is in contact with the source electrode 105 and the drain electrode 106.
  • the thickness of the first oxidation preventing layer 107 may be the same as the thickness of the second oxidation protecting layer 108, which are several hundred
  • the material of the semiconductor active layer 104 may be amorphous silicon, metal oxide, organic semiconductor, graphene or the like, which is not limited herein.
  • the thin film transistor 10 can be classified into a staggered type, an inverted staggered type, and a coplanar type, an anti-coplanar type. It can also be divided into a bottom gate type and a top gate type.
  • the in vivo band structure of the topological insulator has the same energy gap as the ordinary insulator at the Fermi level, but there is a Dirac that crosses the energy gap at its boundary or surface.
  • the electronic state of the type so that its boundary or surface always has a conductive edge state, and this edge state is stable, and is not affected by impurities and disorder, and has high electron mobility and good electrical conductivity.
  • the topological insulator also has good thermal conductivity, which can avoid the problem of degradation of performance caused by heat generation in the thin film transistor.
  • the embodiment of the present invention provides a corresponding oxidation preventing layer in order to solve the problem.
  • the oxidation preventing layer is disposed above and in contact with the electrode made of Cu or Cu alloy material, that is, the oxidation preventing layer is disposed away from the lining of the electrode made of Cu or Cu alloy material.
  • One side of the base substrate 101 and The electrodes are in contact, and in the direction perpendicular to the base substrate 101, the projection of the oxidation preventing layer on the base substrate 101 needs to completely cover the projection of the electrode made of Cu or Cu alloy material on the base substrate 101.
  • An embodiment of the present invention provides a thin film transistor 10 including a gate electrode 102, a gate insulating layer 103, a semiconductor active layer 104, a source electrode 105, and a drain electrode 106 disposed on a base substrate 101; wherein, the gate electrode 102 and / Or the source electrode 105 and the drain electrode 106 are made of Cu or Cu alloy material; on the basis of this, the thin film transistor 10 further includes: an oxidation preventing layer of a topological insulator material, and the oxidation preventing layer is disposed on a gate electrode made of a Cu or Cu alloy material. 102 and/or source electrode 105 and drain electrode 106 are over and in contact therewith.
  • the electrode of the thin film transistor 10 which has good electrical conductivity and low power consumption, so that the performance of the thin film transistor 10 is better.
  • the topological insulator itself is structurally stable and is not easily oxidized, by providing an anti-oxidation layer of the topological insulator material, the electrode made of Cu or Cu alloy material can be protected in each preparation process of the thin film transistor. Achieve the purpose of preventing oxidation of Cu.
  • the topological insulator has good electrical conductivity, the impedance between the electrode and the electrode made of Cu or Cu alloy material is small, which can avoid the influence on the performance of the thin film transistor 10, and the topological insulator also has good thermal conductivity. The problem of deterioration in performance caused by heat generation in the thin film transistor 10 can be avoided.
  • the gate electrode 102, the source electrode 105, and the drain electrode 106 are preferably disposed of Cu or Cu alloy materials.
  • the embodiment of the present invention preferably sets the gate electrode 102, the source electrode 105, and the drain electrode 106 to be made of Cu or Cu alloy materials. This allows the performance of the thin film transistor 10 to be optimized.
  • the semiconductor active layer 104 is a graphene nitride active layer 1041. That is, the material of the semiconductor active layer 104 is graphene nitride.
  • the electronic band structure of the graphene can be changed, so that the graphene is converted from a conductor to a semiconductor, and the original physical properties of the graphene are substantially retained, that is, the electron mobility is high, and the thermal conductivity is high. Ok, the structure is stable.
  • graphene nitride as the semiconductor active layer 104, better electron mobility can be obtained.
  • the thin film transistor 10 When the thin film transistor 10 is applied to a display device, the thin film transistor 10 can be charged to the electrode connected thereto. The discharge rate increases the pixel response speed, resulting in a faster refresh rate, which can be applied to ultra-high resolution display devices.
  • graphene nitride is relatively stable as a material of the semiconductor active layer 104, and also plays a role in the stability of the thin film transistor 10.
  • the gate insulating layer 103 includes a silicon nitride layer, and the silicon nitride layer is in contact with the graphitized nitride active layer 1041; on the basis of this, when the first anti-oxidation layer 107 in contact therewith is disposed above the gate electrode 102 The silicon nitride layer in the gate insulating layer 103 is in contact with the first oxidation protecting layer 107.
  • the gate insulating layer 103 may include only the silicon nitride layer 1031, that is, the silicon nitride layer. 1031 is in contact with the graphene nitride active layer 1041 and also with the first oxidation protecting layer 107.
  • the gate insulating layer 103 may include two silicon nitride layers 1031 and a silicon dioxide layer 1032 between the two silicon nitride layers 1031, wherein the two silicon nitride layers 1031 are respectively
  • the graphene nitride active layer 1041 is in contact with the first oxidation preventing layer 107.
  • the silicon nitride layer 1031 has nitrogen, when the graphene nitride active layer 1041 is formed thereon, nitrogen can be supplied thereto, and the silicon nitride layer 1031 is in contact with the graphene nitride active layer 1041. it is good.
  • the topological insulator may include at least one of a HgTe quantum well, a BiSb alloy, Bi 2 Se 3 , Sb 2 Te 3 , and Bi 2 Te 3 .
  • the embodiment of the present invention preferably uses Bi 2 Se 3 as a topological insulator material.
  • the embodiment of the invention further provides an array substrate, which comprises the above thin film transistor.
  • the array substrate further includes a pixel electrode 20 or an anode 40 connected to the drain electrode 106 of the thin film transistor 10 .
  • the pixel electrode 20 or the anode 40 may be connected to the drain electrode 106 of the thin film transistor 10 through a via located on the pixel electrode 20 or the protective layer 70 between the anode 40 and the thin film transistor 10.
  • the material of the protective layer 70 may be at least one of SiON (silicon oxynitride), SiO 2 (silicon dioxide), SiNx (silicon nitride), and SiO (silicon oxide), wherein the second oxidation protecting layer 108 is considered.
  • SiNx or SiON is preferably used for the interface problem of the topological insulator.
  • the material of the pixel electrode 20 or the anode 40 is a topological insulator.
  • the array substrate when the array substrate further includes an anode 40 , the array substrate further includes an organic material functional layer 50 and a cathode 60 .
  • the organic material functional layer 50 includes at least a light emitting layer.
  • the organic material functional layer 50 may further include an electron transport layer and a hole transport layer.
  • an electron injecting layer disposed between the cathode 60 and the electron transporting layer, and a hole injecting layer disposed between the hole transporting layer and the anode 40 may be further included.
  • the cathode 60 may be opaque, that is, it is made of a metal material and has a relatively thick thickness, in which case, due to The light emitted from the organic material functional layer 50 is emitted only from the anode 40 side. Therefore, when the array substrate is applied to a display device, the display device is a bottom emission type display device.
  • the cathode 60 may be translucent, that is, it is made of a metal material and has a small thickness. In this case, since light emitted from the functional layer 50 of the organic material may be emitted from the side of the anode 40 or may be emitted from the side of the cathode 60. Therefore, when the array substrate is applied to a display device, the display device is a double-sided illumination type display device.
  • the array substrate further includes a common electrode 30.
  • the material of the common electrode 30 may be ITO (indium tin oxide), IZO (indium zinc oxide), a topological insulator, or the like.
  • the pixel electrode 20 and the common electrode 30 are disposed in different layers, and opposite to the base substrate 101, the upper electrode such as the pixel electrode 20 is a strip electrode, and the lower electrode is, for example, The common electrode 30 employs a plate electrode.
  • the topological insulator has both good electrical conductivity and stable property structure, and the surface state of the topological insulator is metallic, even if the film quality has defects, the topological property does not change, so that the influence of the electrical conductivity is very small.
  • the material of the common electrode 30 is also a topological insulator.
  • the array substrate further includes a gate line 801 connected to the gate electrode 102 of the thin film transistor 10, a gate line lead 802 connected to the gate line 801, a data line 901 connected to the source electrode 105, and A data line lead 902 connected to the data line 901.
  • the gate line 801 and the data line 901 are located in the display area 100 of the array substrate, and the gate line lead 802 and the data line lead 902 are located in the wiring area 200 of the array substrate.
  • the display area 100 is used for image display, and the wiring area 200 is located at the periphery of the display area 100 for wiring.
  • the thin film transistor 10, the pixel electrode 20, the common electrode 30, the anode 40, the organic material functional layer 50, the cathode 60, and the like mentioned above are all located in the display region 100.
  • the anti-oxidation layer made of the topological insulator material that is, the first oxidation preventing layer 107 is located above the gate electrode 102 made of Cu or Cu alloy material and with the gate electrode 102.
  • the first oxidation protecting layer 107 is also located above the gate line 801 and the gate line lead 802 and is in contact with both the gate line 801 and the gate line lead 802.
  • the material of the gate electrode 102 is Cu or a Cu alloy
  • the gate line 801 and the gate line lead 802 are generally formed simultaneously with the gate electrode 102
  • the material of the gate line 801 and the gate line lead 802 is also Cu or a Cu alloy.
  • an oxidation preventing layer made of a topological insulator material that is, a second oxidation protecting layer 108
  • the second oxidation protecting layer 108 is also located above the data line 901 and the data line lead 902 and with the data line 901 and the data line lead 902 when being over the source electrode 105 and the drain electrode 106 of the Cu or Cu alloy material and in contact with both. All contact.
  • the material of the drain electrode 106 is Cu or a Cu alloy
  • the material of the data line 901 and the data line lead 902 is also Cu or a Cu alloy.
  • the projection completely covers the electrode made of the underlying Cu or Cu alloy material in contact therewith.
  • the embodiment of the invention further provides a display device comprising the above array substrate.
  • the display device when the array substrate includes the pixel electrode 20, the display device further includes a counter substrate. That is, the display device is a liquid crystal display device.
  • the display substrate further includes a package substrate. That is, the display device is an organic electroluminescent diode display device.
  • the display device may specifically be a product or component having any display function, such as a liquid crystal display, an organic electroluminescent diode display, a liquid crystal television, an organic electroluminescent diode television, a digital photo frame, a mobile phone, a tablet computer, or the like.
  • the embodiment of the present invention further provides a method for fabricating a thin film transistor.
  • the method includes forming a gate electrode 102, a gate insulating layer 103, a semiconductor active layer 104, and a source electrode 105 on a base substrate 101.
  • a drain electrode 106 wherein the gate electrode 102 and/or the source electrode 105 and the drain electrode 106 are made of a Cu or Cu alloy material; the method further includes: forming a gate electrode and/or a source electrode using a Cu or Cu alloy material Simultaneously with the drain electrode, an anti-oxidation layer is formed using a topological insulator material; wherein the anti-oxidation layer is located above the gate electrode and/or the source and drain electrodes made of Cu or Cu alloy material.
  • the gate electrode 102 may be made of Cu or Cu alloy material, and the source electrode 105 and the drain electrode 106 may be made of other conductive materials that are less susceptible to oxidation, such as Al.
  • the anti-oxidation layer may include a first oxidation preventing layer 107 located above the gate electrode 102 and in contact with the gate electrode 102.
  • the source electrode 105 and the drain electrode 106 may be made of Cu or Cu alloy material, and the gate electrode 102 may be made of other conductive materials that are less susceptible to oxidation, such as Al.
  • the anti-oxidation layer may include a second oxidation preventing layer 108 located above the source electrode 105 and the drain electrode 106 and in contact with the source electrode 105 and the drain electrode 106.
  • the gate electrode 102, the source electrode 105, and the drain electrode 106 may each be made of a Cu or Cu alloy material.
  • the above oxidation preventing layer may include a first oxidation protecting layer 107 and a second oxidation preventing layer 108.
  • the first oxidation protecting layer 107 is located above the gate electrode 102 and is in contact with the gate electrode 102.
  • the second oxidation protecting layer 108 is located above the source electrode 105 and the drain electrode 106 and is in contact with the source electrode 105 and the drain electrode 106.
  • Embodiments of the present invention provide a method for fabricating a thin film transistor.
  • Cu or a Cu alloy is used as an electrode of the thin film transistor 10, which has good electrical conductivity and low power consumption, so that the performance of the thin film transistor 10 is better.
  • the electrode made of Cu or Cu alloy material can be protected in the preparation process of the thin film transistor by forming the anti-oxidation layer of the topological insulator material. Achieve the purpose of preventing oxidation of Cu.
  • the topological insulator has good electrical conductivity, the impedance between the electrode and the electrode of the Cu or Cu alloy material is small, the influence on the performance of the thin film transistor 10 can be avoided, and the topological insulator also has good thermal conductivity. The problem of deterioration in performance caused by heat generation in the thin film transistor 10 is avoided.
  • the oxidation preventing layer is formed simultaneously with the electrode made of the Cu or Cu alloy material underneath, it does not cause an increase in the number of patterning processes.
  • forming the oxidation preventing layer comprises: forming a topological insulator film by using a Plasma Enhanced Chemical Vapor Deposition (PECVD) method or a sputtering method, and forming a corresponding oxidation preventing layer by a patterning process, for example, An oxidation preventing layer 107 and/or a first oxidation protecting layer 108.
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • forming the semiconductor active layer 104 includes: using an atmosphere of hydrogen (H 2 ) and argon (Ar), using ammonia (NH 3 ) and methane (CH 4 ) as a reaction source, by chemical vapor deposition A graphene nitride active layer 1041 is formed.
  • H 2 can be used as a gas in the reaction atmosphere to ensure formation of the H component in the olefin.

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Abstract

提供一种薄膜晶体管及其制备方法、阵列基板、显示装置，其可采用Cu或Cu合金作为电极材料，以防氧化层来防止Cu氧化。该薄膜晶体管包括：设置在衬底基板（101）上的栅电极（102）、栅绝缘层（103）、半导体有源层（104）、源漏电极（105，106），其中栅电极（102）和/或源漏电极（105，106）采用Cu或Cu合金材料制成，拓扑绝缘体材料制成的防氧化层（108）设置在由Cu或Cu合金制成的栅电极（102）和/或源漏电极,105，106）上方并与其接触。

Description

薄膜晶体管及其制备方法、阵列基板和显示装置
本申请要求于2015年9月23日递交的、申请号为201510613414.6、发明名称为“一种薄膜晶体管及其制备方法、阵列基板、显示装置”的中国专利申请的优先权，其全部内容通过引用并入本申请中。
技术领域
本发明涉及显示技术领域，尤其涉及一种薄膜晶体管及其制备方法、阵列基板、显示装置。
背景技术
薄膜晶体管(Thin Film Transistor，简称TFT)是当今应用较为广泛的晶体管之一。如图1所示，薄膜晶体管10包括设置在衬底基板101上的栅电极102、栅绝缘层103、半导体有源层104、源电极105和漏电极106。
其中，栅电极102、源电极105和漏电极106一般采用电阻较低的金属材料，例如铜(Cu)、Cu合金、铝(Al)、银(Ag)等。
由于Ag比较贵，会导致薄膜晶体管的成本升高，因此，采用Ag作为薄膜晶体管的电极材料使用较少。
相对Al，Cu和Cu合金具有更优良的导电性能，但是由于铜的活性比较强，容易氧化，采用Cu和Cu合金作为电极材料时需考虑工艺过程中导致的Cu氧化，因此，目前较常用的是以Al作为电极材料。
发明内容
本发明的实施例提供一种薄膜晶体管及其制备方法、阵列基板、显示装置，其中可采用Cu和Cu合金作为电极材料，同时又能够防止Cu氧化。
为达到上述目的，本发明的实施例采用如下技术方案：
一方面，提供一种薄膜晶体管，包括设置在衬底基板上的栅电极、栅绝缘层、半导体有源层、源电极和漏电极；所述栅电极和/或所述源电极和所述漏电极采用Cu或Cu合金材料制成；所述薄膜晶体管还包括：拓扑绝缘体材料制成的防氧化层，所述防氧化层设置在采用Cu或Cu合金材料制成的所述栅电极和/或所述源电极和所述漏电极上方并与其接触。
优选的，所述栅电极、所述源电极和所述漏电极均采用Cu或Cu合金材料制 成；所述防氧化层包括第一防氧化层和第一防氧化层，所述第一防氧化层设置在所述栅电极上方并与其接触，所述第二防氧化层设置在所述源电极和所述漏电极上方并与二者都接触。
优选的，所述半导体有源层为氮化石墨烯有源层。
进一步优选的，所述栅绝缘层为氮化硅层，所述氮化硅层与所述氮化石墨烯有源层接触；所述防氧化层包括第一防氧化层，所述第一防氧化层设置在所述栅电极上方并与其接触，所述氮化硅层与所述第一防氧化层接触。
还优选的，所述栅绝缘层包括第一氮化硅层、第二氮化硅层和位于所述第一和第二氮化硅层之间的二氧化硅层，所述第一氮化硅层与所述氮化石墨烯有源层接触；所述防氧化层包括第一防氧化层，所述第一防氧化层设置在所述栅电极上方并与其接触，所述第二氮化硅层与所述第一防氧化层接触。
在一实施例中，沿垂直衬底基板的方向，所述防氧化层在衬底基板上的投影完全覆盖采用Cu或Cu合金材料制成的所述栅电极和/或所述源电极和所述漏电极在衬底基板上的投影。
基于上述，可选的，拓扑绝缘体包括HgTe量子井、BiSb合金、Bi2Se3、Sb2Te3和Bi2Te3中的至少一种。
另一方面，提供一种阵列基板，包括上述的薄膜晶体管。
优选的，所述阵列基板还包括与所述薄膜晶体管的漏电极连接的像素电极或阳极；所述像素电极或所述阳极的材料为拓扑绝缘体。
进一步优选的，在所述阵列基板包括所述像素电极的情况下，所述阵列基板还包括公共电极；其中，所述公共电极的材料为氧化铟锡、氧化铟锌或拓扑绝缘体。
基于上述，优选的，所述阵列基板还包括与所述薄膜晶体管的栅电极连接的栅线以及与所述栅线连接的栅线引线、与源电极连接的数据线和与所述数据线连接的数据线引线；当拓扑绝缘体材料制成的防氧化层位于Cu或Cu合金材料制成的所述栅电极上方并与所述栅电极接触时，所述防氧化层还位于所述栅线和所述栅线引线上方并与二者都接触；和/或，当拓扑绝缘体材料制成的防氧化层位于Cu或Cu合金材料制成的所述源电极和所述漏电极上方并与二者都接触时，所述防氧化层还位于所述数据线和所述数据线引线上方并与二者都接触。
再一方面，提供一种显示装置，包括上述的阵列基板。
又一方面，提供一种薄膜晶体管的制备方法，包括在衬底基板上形成栅电极、栅绝缘层、半导体有源层、源电极和漏电极；所述栅电极和/或所述源电极和所述漏 电极采用Cu或Cu合金材料制成；所述方法还包括：在使用Cu或Cu合金材料形成栅电极和/或源电极和漏电极的同时，使用拓扑绝缘体材料形成防氧化层；其中，所述防氧化层位于Cu或Cu合金材料制成的栅电极和/或源电极和漏电极上方。
优选的，使用拓扑绝缘体材料形成防氧化层的步骤包括：在垂直衬底基板的方向上，使防氧化层在衬底基板上的投影完全覆盖Cu或Cu合金材料制成的栅电极和/或源电极和漏电极在衬底基板上的投影。
优选的，形成半导体有源层的步骤包括：在氢气和氩气的气氛中，以氨气和甲烷为反应源，通过化学气相沉积法形成氮化石墨烯有源层。
本发明的实施例提供一种薄膜晶体管及其制备方法、阵列基板、显示装置，一方面，采用Cu或Cu合金作为薄膜晶体管的电极，其导电性能好，功耗小，使得薄膜晶体管的性能更好。另一方面，由于拓扑绝缘体本身结构稳定，不易被氧化，因此，通过设置拓扑绝缘体材料制成的防氧化层，可在薄膜晶体管各制备工序中对Cu或Cu合金材料的电极起到保护作用，达到防止Cu氧化的目的。在此基础上，由于拓扑绝缘体具有良好的导电性能，其与Cu或Cu合金材料的电极之间阻抗小，可避免对薄膜晶体管性能产生影响，且拓扑绝缘体还具有良好的热导性能，可避免薄膜晶体管内发热所导致其性能下降的问题。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术提供的一种薄膜晶体管的结构示意图；
图2为本发明实施例提供的薄膜晶体管的示例一的结构示意图；
图3为本发明实施例提供的薄膜晶体管的示例二的结构示意图；
图4为本发明实施例提供的薄膜晶体管的示例三的结构示意图；
图5a为本发明实施例提供的薄膜晶体管的示例四的结构示意图；
图5b为本发明实施例提供的薄膜晶体管的示例五的结构示意图；
图6为本发明实施例提供的应用于液晶显示装置的阵列基板的示例一的结构示意图；
图7为本发明实施例提供的应用于有机电致发光二极管显示装置的阵列基板的 结构示意图；
图8为本发明实施例提供的应用于液晶显示装置的阵列基板的示例二的结构示意图；
图9a为本发明实施例提供的一种阵列基板的俯视示意图；
图9b为图9a中的A-A向和B-B向剖视示意图；
图9c为图9a中的C-C向和D-D向剖视示意图。
附图标记：
10-薄膜晶体管；101-衬底基板；102-栅电极；103-栅绝缘层；104-半导体有源层；105-源电极；106-漏电极；1041-氮化石墨烯有源层；1031-氮化硅层；1032-二氧化硅层；20-像素电极；30-公共电极；40-阳极；50-有机材料功能层；60-阴极；70-保护层；801-栅线；802-栅线引线；901-数据线；902-数据线引线；100-显示区；200-布线区。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本领域技术人员所理解的通常意义。本发明专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明。
本发明实施例提供一种薄膜晶体管10，如图2-4所示，该薄膜晶体管10包括设置在衬底基板101上的栅电极102、栅绝缘层103、半导体有源层104、源电极105和漏电极106；其中，栅电极102和/或源电极105和漏电极106采用Cu或Cu合金材料制成；在此基础上，薄膜晶体管10还包括：拓扑绝缘体材料制成的防氧化层，防氧化层设置在采用Cu或Cu合金材料制成的栅电极102和/或源电极105和漏电极106上方并与其接触。
具体的，如图2所示，栅电极102可以采用Cu或Cu合金材料，源电极105和 漏电极106可以采用其他比较不容易氧化的导电材料，例如Al。
在此基础上，上述防氧化层可以包括第一防氧化层107，该第一防氧化层107设置在栅电极102上方，并与栅电极102接触。
其中，第一防氧化层107的厚度可以为几百
Figure PCTCN2016073297-appb-000001
或者，如图3所示，源电极105和漏电极106可以采用Cu或Cu合金材料，栅电极102可以采用其他比较不容易氧化的导电材料，例如Al。
在此基础上，上述防氧化层可以包括第二防氧化层108，该第二防氧化层108设置在源电极105和漏电极106上方，并与源电极105和漏电极106接触。
其中，第二防氧化层108的厚度可以为几百
Figure PCTCN2016073297-appb-000002
或者，如图4所示，栅电极102、源电极105和漏电极106均可以采用Cu或Cu合金材料。
在此基础上，上述防氧化层可以包括第一防氧化层107和第二防氧化层108。第一防氧化层107设置在栅电极102上方，并与栅电极102接触。第二防氧化层108设置在源电极105和漏电极106上方，并与源电极105和漏电极106接触。
其中，第一防氧化层107的厚度可以与第二防氧化层108的厚度相同，均为几百
Figure PCTCN2016073297-appb-000003
需要说明的是，第一，所述半导体有源层104的材料可以是非晶硅、金属氧化物、有机半导体、石墨烯等，具体在此不做限定。
第二，根据半导体有源层104与源电极105和漏电极106的形成次序不同，所述薄膜晶体管10可以分为交错型、反交错型、以及共面型、***面型。还可以分为底栅型和顶栅型。
第三，拓扑绝缘体(topological insulator)的体内的能带结构和普通绝缘体一样，都在费米能级处有一有限大小的能隙，但是在它的边界或表面却存在着穿越能隙的狄拉克型的电子态，因而使得它的边界或表面总是存在导电的边缘态，且这种边缘态是稳定存在的，而且不受杂质和无序的影响，其电子迁移率高，导电性能好。
此外，拓扑绝缘体还具有良好的导热性能，可避免薄膜晶体管内发热所导致的其性能下降的问题。
第四，由于采用Cu或Cu合金作为电极材料时，其存在容易氧化的问题，因而，本发明实施例为了解决该问题设置了相应的防氧化层。基于此，本领域技术人员应该明白，防氧化层设置在采用Cu或Cu合金材料制成的电极上方并与其接触，即为：防氧化层设置在Cu或Cu合金材料制成的电极的远离衬底基板101的一侧且与 该电极接触，且沿垂直衬底基板101的方向，防氧化层在衬底基板101上的投影需完全覆盖Cu或Cu合金材料制成的电极在衬底基板101上的投影。
本发明实施例提供一种薄膜晶体管10，包括设置在衬底基板101上的栅电极102、栅绝缘层103、半导体有源层104、源电极105和漏电极106；其中，栅电极102和/或源电极105和漏电极106采用Cu或Cu合金材料；在此基础上，薄膜晶体管10还包括：拓扑绝缘体材料的防氧化层，防氧化层设置在采用Cu或Cu合金材料制成的栅电极102和/或源电极105和漏电极106上方并与其接触。一方面，采用Cu或Cu合金作为薄膜晶体管10的电极，其导电性能好，功耗小，使得薄膜晶体管10的性能更好。另一方面，由于拓扑绝缘体本身结构稳定，不易被氧化，因此，通过设置拓扑绝缘体材料的防氧化层，可在薄膜晶体管各制备工序中对Cu或Cu合金材料制成的电极起到保护作用，达到防止Cu氧化的目的。在此基础上，由于拓扑绝缘体具有良好的导电性能，其与Cu或Cu合金材料制成的电极之间阻抗小，可避免对薄膜晶体管10性能产生影响，且拓扑绝缘体还具有良好的热导性能，可避免薄膜晶体管10内发热所导致的其性能下降的问题。
相对只将栅电极102或源电极105和漏电极106设置为采用Cu或Cu合金材料，本发明实施例优选将栅电极102、源电极105和漏电极106设置为均采用Cu或Cu合金材料，这样可使薄膜晶体管10的性能达到最好。
优选的，如图2-4所示，半导体有源层104为氮化石墨烯有源层1041。即，半导体有源层104的材料为氮化石墨烯。
其中，通过控制石墨烯中的氮含量可改变石墨烯的电子能带结构，从而使得石墨烯由导体向半导体转变，同时又基本保留石墨烯原有的物理性能，即电子迁移率高，导热性能好，结构稳定。
本发明实施例中通过将氮化石墨烯作为半导体有源层104，可获得更好的电子迁移率，当该薄膜晶体管10应用于显示装置时，可提高薄膜晶体管10对与其连接的电极的充放电速率，提高了像素响应速度，从而可实现更快的刷新率，因而可以将其应用于超高分辨率的显示装置。此外，将氮化石墨烯作为半导体有源层104的材料，相对更稳定，对薄膜晶体管10的稳定性也起到一定作用。
进一步优选的，栅绝缘层103包括氮化硅层，氮化硅层与氮化石墨烯有源层1041接触；在此基础上，当栅电极102上方设置与其接触的第一防氧化层107时，栅绝缘层103中的氮化硅层与第一防氧化层107接触。
具体的，如图5a所示，栅绝缘层103可以只包括氮化硅层1031，即该氮化硅层 1031既与氮化石墨烯有源层1041接触，也与第一防氧化层107接触。
或者，如图5b所示，栅绝缘层103可以包括两层氮化硅层1031、以及位于两层氮化硅层1031之间的二氧化硅层1032，其中两层氮化硅层1031分别与氮化石墨烯有源层1041和第一防氧化层107接触。
其中，由于氮化硅层1031中具有氮，当在其上方形成氮化石墨烯有源层1041时，可向其提供氮，并且氮化硅层1031与氮化石墨烯有源层1041接触性好。
此外，相比二氧化硅层1032中具有氧，氮化硅层1031中没有氧，当氮化硅层1031与第一防氧化层107接触时，可进一步避免氧对Cu或Cu合金材料制成的栅电极102的氧化问题。
基于上述，拓扑绝缘体可以包括HgTe量子井、BiSb合金、Bi2Se3、Sb2Te3和Bi2Te3中的至少一种。
其中，由于Bi2Se3易于合成，化学结构稳定，因此，本发明实施例优选采用Bi2Se3作为拓扑绝缘体材料。
本发明实施例还提供了一种阵列基板，该阵列基板包括上述的薄膜晶体管。
可选的，如图6和图7所述，阵列基板还包括与薄膜晶体管10的漏电极106连接的像素电极20或阳极40。
其中，像素电极20或阳极40可通过位于像素电极20或阳极40和薄膜晶体管10之间的保护层70上的过孔与薄膜晶体管10的漏电极106连接。保护层70的材料可以为SiON(氮氧化硅)、Si02(二氧化硅)、SiNx(氮化硅)和SiO(氧化硅)中的至少一种，其中，考虑到第二防氧化层108的拓扑绝缘体的界面问题，优选采用SiNx或SiON。
由于拓扑绝缘体既具有良好的导电性能又具有稳定的性质结构，且拓扑绝缘体表面态为金属态，即使膜质量存在缺陷问题，其拓扑性质不改变使得导电所受影响也非常小，因此，本发明实施例优选像素电极20或阳极40的材料为拓扑绝缘体。
需要说明的是，如图7所示，当所述阵列基板还包括阳极40时，则该阵列基板还需包括有机材料功能层50和阴极60。
其中，有机材料功能层50至少包括发光层。在此基础上为了能够提高电子和空穴注入发光层的效率，有机材料功能层50还可以包括电子传输层、空穴传输层。进一步还可以包括设置在阴极60与电子传输层之间的电子注入层，以及设置在空穴传输层与阳极40之间的空穴注入层。
阴极60可以为不透明，即，其采用金属材料且厚度较厚，在此情况下，由于从 有机材料功能层50出射的光仅从阳极40一侧出射，因此当该阵列基板应用于显示装置时，该显示装置为底发光型显示装置。
阴极60可以为半透明，即，其采用金属材料且厚度较薄，在此情况下，由于从有机材料功能层50出射的光既可以从阳极40一侧出射，也可以从阴极60一侧出射，因此当该阵列基板应用于显示装置时，该显示装置为双面发光型显示装置。
进一步的，如图8所示，在阵列基板包括像素电极20的情况下，所述阵列基板还包括公共电极30。其中，公共电极30的材料可以为ITO(氧化铟锡)、IZO(氧化铟锌)、拓扑绝缘体等。
由于采用高级超维场转换技术(Advanced Super Dimensional Switching，简称ADS)可以提高产品的画面品质，具有高分辨率、高透过率、低功耗、宽视角、高开口率、低色差、无挤压水波纹(Push Mura)等优点。因此，本发明实施例中，如图8所示，优选像素电极20和公共电极30不同层设置，且相对衬底基板101，在上的电极例如像素电极20采用条形电极，在下的电极例如公共电极30采用板状电极。
进一步，由于拓扑绝缘体既具有良好的导电性能又具有稳定的性质结构，且拓扑绝缘体表面态为金属态，即使膜质量存在缺陷问题，其拓扑性质不改变使得导电所受影响也非常小，因此，本发明实施例优选公共电极30的材料也为拓扑绝缘体。
基于上述，如图9a所示，所述阵列基板还包括与薄膜晶体管10的栅电极102连接的栅线801以及与栅线801连接的栅线引线802、与源电极105连接的数据线901和与数据线901连接的数据线引线902。其中，栅线801和数据线901位于阵列基板的显示区100，栅线引线802和数据线引线902位于阵列基板的布线区200。
需要说明的是，本领域技术人员应该明白，显示区100用于图像显示，布线区200位于显示区100***，用于进行布线。上述提到的薄膜晶体管10、像素电极20、公共电极30、阳极40、有机材料功能层50、阴极60等均位于显示区100中。
在此基础上，如图9b所示，优选的，当拓扑绝缘体材料制成的防氧化层，即第一防氧化层107位于Cu或Cu合金材料制成的栅电极102上方并与栅电极102接触时，第一防氧化层107还位于栅线801和栅线引线802上方并与栅线801和栅线引线802都接触。
其中，当栅电极102的材料为Cu或Cu合金时，由于栅线801和栅线引线802一般与栅电极102同时形成，因此，栅线801和栅线引线802的材料也为Cu或Cu合金。
和/或，如图9c所示，当拓扑绝缘体材料制成的防氧化层，即第二防氧化层108 位于Cu或Cu合金材料的源电极105和漏电极106上方并与二者都接触时，第二防氧化层108还位于数据线901和数据线引线902上方并与数据线901和数据线引线902都接触。
其中，当漏电极106的材料为Cu或Cu合金时，由于数据线901和数据线引线902一般与漏电极106同时形成，因此，数据线901和数据线引线902的材料也为Cu或Cu合金。
需要说明的是，不管是第一防氧化层107，还是第二防氧化层108，在垂直衬底基板101的方向上，其投影完全覆盖与其接触的下方的Cu或Cu合金材料制成的电极。
本发明实施例还提供一种显示装置，包括上述的阵列基板。
其中，当阵列基板包括像素电极20时，显示装置还包括对盒基板。即，该显示装置为液晶显示装置。
当阵列基板包括阳极40、有机材料功能层50和阴极60时，显示基板还包括封装基板。即，该显示装置为有机电致发光二极管显示装置。
上述显示装置具体可以是液晶显示器、有机电致发光二极管显示器、液晶电视、有机电致发光二极管电视、数码相框、手机、平板电脑等具有任何显示功能的产品或者部件。
本发明实施例还提供了一种薄膜晶体管的制备方法，参考2-4所示，该方法包括在衬底基板101上形成栅电极102、栅绝缘层103、半导体有源层104、源电极105和漏电极106；其中，栅电极102和/或源电极105和漏电极106采用Cu或Cu合金材料制成；所述方法还包括：在使用Cu或Cu合金材料形成栅电极和/或源电极和漏电极的同时，使用拓扑绝缘体材料形成防氧化层；其中，防氧化层位于Cu或Cu合金材料制成的栅电极和/或源电极和漏电极上方。
具体的，参考图2所示，栅电极102可以采用Cu或Cu合金材料，源电极105和漏电极106可以采用其他比较不容易氧化的导电材料，例如Al。
在此基础上，上述防氧化层可以包括第一防氧化层107，该第一防氧化层107位于在栅电极102上方，并与栅电极102接触。
或者，参考图3所示，源电极105和漏电极106可以采用Cu或Cu合金材料，栅电极102可以采用其他比较不容易氧化的导电材料，例如Al。
在此基础上，上述防氧化层可以包括第二防氧化层108，该第二防氧化层108位于源电极105和漏电极106上方，并与源电极105和漏电极106接触。
或者，参考图4所示，栅电极102、源电极105和漏电极106可以均采用Cu或Cu合金材料。
在此基础上，上述防氧化层可以包括第一防氧化层107和第二防氧化层108。第一防氧化层107位于栅电极102上方，并与栅电极102接触。第二防氧化层108位于源电极105和漏电极106上方，并与源电极105和漏电极106接触。
本发明实施例提供一种薄膜晶体管的制备方法，一方面，采用Cu或Cu合金作为薄膜晶体管10的电极，其导电性能好，功耗小，使得薄膜晶体管10的性能更好。另一方面，由于拓扑绝缘体本身结构稳定，不易被氧化，因此，通过形成拓扑绝缘体材料的防氧化层，可在薄膜晶体管各制备工序中对Cu或Cu合金材料制成的电极起到保护作用，达到防止Cu氧化的目的。在此基础上，由于拓扑绝缘体具有良好的导电性能，其与Cu或Cu合金材料的电极之间阻抗小，可避免对薄膜晶体管10性能产生影响，且拓扑绝缘体还具有良好的热导性能，可避免薄膜晶体管10内发热所导致的其性能下降的问题。此外，由于防氧化层与其下方的Cu或Cu合金材料制成的电极同时形成，因此也不会导致构图工艺次数的增加。
可选的，形成防氧化层包括：采用等离子体增强化学气相沉积法(Plasma Enhanced Chemical Vapor Deposition，简称PECVD)或溅射方法形成拓扑绝缘体薄膜，并通过构图工艺形成相应的防氧化层，例如第一防氧化层107和/或第一防氧化层108。
可选的，形成半导体有源层104包括：在氢气(H2)和氩气(Ar)的气氛中，以氨气(NH3)和甲烷(CH4)为反应源，通过化学气相沉积法形成氮化石墨烯有源层1041。
其中，H2可以作为反应气氛中的气体，以确保形成烯烃中的H成分。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种薄膜晶体管，包括设置在衬底基板上的栅电极、栅绝缘层、半导体有源层、源电极和漏电极；所述栅电极和/或所述源电极和所述漏电极采用Cu或Cu合金材料制成；
    其中所述薄膜晶体管还包括：拓扑绝缘体材料制成的防氧化层，所述防氧化层设置在采用Cu或Cu合金材料制成的所述栅电极和/或所述源电极和所述漏电极上方并与其接触。
  2. 根据权利要求1所述的薄膜晶体管，其中，所述栅电极、所述源电极和所述漏电极均采用Cu或Cu合金材料制成；
    所述防氧化层包括第一防氧化层和第一防氧化层，所述第一防氧化层设置在所述栅电极上方并与其接触，所述第二防氧化层设置在所述源电极和所述漏电极上方并与二者都接触。
  3. 根据权利要求1所述的薄膜晶体管，其中，所述半导体有源层为氮化石墨烯有源层。
  4. 根据权利要求3所述的薄膜晶体管，其中，所述栅绝缘层为氮化硅层，所述氮化硅层与所述氮化石墨烯有源层接触；
    所述防氧化层包括第一防氧化层，所述第一防氧化层设置在所述栅电极上方并与其接触，所述氮化硅层与所述第一防氧化层接触。
  5. 根据权利要求3所述的薄膜晶体管，其中，所述栅绝缘层包括第一氮化硅层、第二氮化硅层和位于所述第一和第二氮化硅层之间的二氧化硅层，所述第一氮化硅层与所述氮化石墨烯有源层接触；
    所述防氧化层包括第一防氧化层，所述第一防氧化层设置在所述栅电极上方并与其接触，所述第二氮化硅层与所述第一防氧化层接触。
  6. 根据权利要求1-5中任一项所述的薄膜晶体管，其中，沿垂直所述衬底基板的方向，所述防氧化层在所述衬底基板上的投影完全覆盖采用Cu或Cu合金材料制成的所述栅电极和/或所述源电极和所述漏电极在所述衬底基板上的投影。
  7. 根据权利要求6所述的薄膜晶体管，其中，拓扑绝缘体包括HgTe量子井、BiSb合金、Bi2Se3、Sb2Te3和Bi2Te3中的至少一种。
  8. 一种阵列基板，其中，包括权利要求1-7中任一项所述的薄膜晶体管。
  9. 根据权利要求8所述的阵列基板，其中，所述阵列基板还包括与所述薄膜晶体管的漏电极连接的像素电极或阳极；
    所述像素电极或所述阳极的材料为拓扑绝缘体。
  10. 根据权利要求9所述的阵列基板，其中，在所述阵列基板包括所述像素电极的情况下，所述阵列基板还包括公共电极；
    其中，所述公共电极的材料为氧化铟锡、氧化铟锌或拓扑绝缘体。
  11. 根据权利要求8-10中任一项所述的阵列基板，其中，所述阵列基板还包括与所述薄膜晶体管的栅电极连接的栅线以及与所述栅线连接的栅线引线、与源电极连接的数据线和与所述数据线连接的数据线引线；
    当拓扑绝缘体材料制成的防氧化层位于Cu或Cu合金材料制成的所述栅电极上方并与所述栅电极接触时，所述防氧化层还位于所述栅线和所述栅线引线上方并与二者都接触；和/或，
    当拓扑绝缘体材料制成的防氧化层位于Cu或Cu合金材料制成的所述源电极和所述漏电极上方并与二者都接触时，所述防氧化层还位于所述数据线和所述数据线引线上方并与二者都接触。
  12. 一种显示装置，其中，包括权利要求8-11中任一项所述的阵列基板。
  13. 一种薄膜晶体管的制备方法，包括在衬底基板上形成栅电极、栅绝缘层、半导体有源层、源电极和漏电极；所述栅电极和/或所述源电极和所述漏电极采用Cu或Cu合金材料制成；
    所述方法还包括：在使用Cu或Cu合金材料形成所述栅电极和/或所述源电极和所述漏电极的同时，使用拓扑绝缘体材料形成防氧化层；其中，所述防氧化层位于Cu或Cu合金材料制成的所述栅电极和/或所述源电极和所述漏电极上方。
  14. 根据权利要求13所述的制备方法，其中，使用拓扑绝缘体材料形成防氧化层的步骤包括：在垂直所述衬底基板的方向上，使所述防氧化层在衬底基板上的投影完全覆盖Cu或Cu合金材料制成的所述栅电极和/或所述源电极和所述漏电极在衬底基板上的投影。
  15. 根据权利要求13或14所述的制备方法，其中，形成半导体有源层的步骤包括：
    在氢气和氩气的气氛中，以氨气和甲烷为反应源，通过化学气相沉积法形成氮化石墨烯有源层。
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