WO2017036041A1 - Procédé d'accès synchrone aux données et dispositif d'accès synchrone - Google Patents

Procédé d'accès synchrone aux données et dispositif d'accès synchrone Download PDF

Info

Publication number
WO2017036041A1
WO2017036041A1 PCT/CN2015/099893 CN2015099893W WO2017036041A1 WO 2017036041 A1 WO2017036041 A1 WO 2017036041A1 CN 2015099893 W CN2015099893 W CN 2015099893W WO 2017036041 A1 WO2017036041 A1 WO 2017036041A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
accessed
synchronously
bits
atomic operation
Prior art date
Application number
PCT/CN2015/099893
Other languages
English (en)
Chinese (zh)
Inventor
易鸿斌
Original Assignee
安一恒通（北京）科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 安一恒通（北京）科技有限公司 filed Critical 安一恒通（北京）科技有限公司
Publication of WO2017036041A1 publication Critical patent/WO2017036041A1/fr

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt

Definitions

  • the present disclosure relates generally to computer technology, and more particularly to data access technologies, and more particularly to a method for synchronous access of data and a synchronous access device.
  • data is located somewhere in the storage area, and each data corresponds to a synchronization object for synchronization.
  • the synchronization object corresponding to the setting data is in a no-signal state, and the data is accessed through the atomic operation instruction, and if the value of the data satisfies the pre-specified correspondence, the corresponding synchronization object is set as There is a signal state.
  • the synchronization object corresponding to all other data is waited for the signal state, and the data is accessed through the atomic operation instruction.
  • the existing synchronous access method needs to wait for a synchronization object for synchronous access of data having an association relationship, which affects efficiency.
  • this method is not available when the processor's interrupt request level is above the thread scheduling level.
  • an embodiment of the present application provides a method for synchronously accessing data, including: allocating a contiguous memory unit to data to be accessed synchronously, wherein a data bit of the contiguous memory unit is a data bit of data to be synchronously accessed.
  • the atomic operation instruction is divided into data segments corresponding to the number of data to be synchronously accessed, wherein the bits of each data segment The number is greater than or equal to the number of bits of data to be accessed synchronously corresponding thereto; and accessing data to be accessed synchronously in one instruction cycle, wherein the instruction cycle is the duration of execution of the atomic operation instruction.
  • the embodiment of the present application further provides a data synchronization access device, including: an allocation module, configured to allocate a contiguous memory unit to data to be accessed synchronously, wherein the data bits of the contiguous memory unit are data The sum of the data bits; the dividing module configured to divide the atomic operation instruction into data corresponding to the number of data to be synchronously accessed based on the number of data to be accessed synchronously and the number of data bits of each data to be synchronously accessed a segment, wherein the number of bits of each data segment is greater than or equal to a corresponding number of bits of data to be accessed synchronously; and an access module configured to access data to be accessed synchronously within one instruction cycle, wherein the instruction cycle The length of time to execute an atomic operation instruction.
  • an allocation module configured to allocate a contiguous memory unit to data to be accessed synchronously, wherein the data bits of the contiguous memory unit are data The sum of the data bits
  • the dividing module configured to divide the atomic operation
  • the solution provided by the embodiment of the present application can simultaneously access multiple data in one atomic operation instruction cycle, thereby improving the efficiency of data reading and writing.
  • synchronous access of data under the premise that the total number of bits of data is less than or equal to the number of atomic operation instructions can avoid modification of data by other threads, and ensure the correctness of the relationship between the data.
  • the association relationship between the data may also be determined by an atomic operation instruction.
  • FIG. 1 is a schematic flowchart of a method for synchronous access of data according to an embodiment of the present application
  • FIG. 2 shows, in FIG. 1, the atomic operation instruction is divided into data to be accessed synchronously based on the number of data to be synchronously accessed and the number of data bits of data to be synchronously accessed.
  • FIG. 3 is a schematic diagram of an application scenario of a method for synchronous access of data according to an embodiment of the present application
  • FIG. 4 shows a schematic structural diagram of a synchronous access device for data according to an embodiment of the present application.
  • FIG. 1 a schematic flowchart 100 of a method for synchronous access of data according to an embodiment of the present application is shown.
  • step 110 contiguous memory locations are allocated to the data to be accessed synchronously.
  • the data bit number of the contiguous memory unit is the sum of the data bits of the data to be accessed synchronously.
  • Memory allocation refers to the operation of allocating or reclaiming storage space during program execution.
  • the continuous allocation of memory refers to allocating a contiguous memory space for a user program.
  • the continuous allocation of memory includes a single continuous allocation, fixed partition allocation, and dynamic partition allocation.
  • each data to be accessed synchronously includes 16 bits. Then, when allocating contiguous memory cells to these data, a 64-bit contiguous memory cell (16 ⁇ 4) can be allocated for storing the data to be accessed synchronously.
  • step 120 based on the number of data to be synchronously accessed and the number of data bits of each data to be synchronously accessed, the atomic operation instruction is divided into data segments corresponding to the number of data to be synchronously accessed, wherein each data The number of bits in the segment is greater than or equal to the number of bits of data to be accessed synchronously.
  • An atomic operation is an operation that cannot be interrupted, or an operation that is not interrupted by the thread scheduling mechanism. There is no context switch during the operation.
  • the access is not interrupted by other threads, that is, the data stored in the memory unit before the execution of the atomic operation instruction instruction is completed. The value will not be changed by other threads.
  • each data to be accessed synchronously includes 16 bits for explanation.
  • the atomic operation instruction may be divided into four data segments to respectively access the four data to be synchronously accessed.
  • the data processing digits of each data segment are not less than 16 bits.
  • each of the data to be synchronously accessed includes 16 bits.
  • the data to be accessed synchronously may have the same number of data bits, or may have different numbers of data bits.
  • the data processing bits of the data segment of the atomic operation instruction corresponding to the data to be synchronously accessed may also be the same or different.
  • the data bit number of the data A to be synchronously accessed is 16 bits
  • the data bit number of the data B to be synchronously accessed is 8 bits
  • at least when the data segment is divided, the data segment for accessing the data A to be synchronously accessed is at least There are 16 bits of data processing bits
  • the data segment for accessing data B to be accessed synchronously has at least 8 bits of data processing bits.
  • step 130 the data to be accessed synchronously is accessed during an instruction cycle, wherein the instruction cycle is the length of time during which the atomic operation instruction is executed.
  • each data segment to be accessed synchronously is accessed through each data segment of the atomic operation instruction.
  • access to each data to be accessed synchronously may include, for example, read, write or other operational categories.
  • step 210 the number of data bits of each data to be synchronously accessed is obtained.
  • the number of data bits of each data to be accessed synchronously may be determined by the number of data bits of consecutive memory cells allocated to the data to be accessed synchronously.
  • contiguous memory locations have been allocated to the data based on the number of data bits of the data in step 110.
  • the number of data bits of each data to be synchronously accessed can be determined based on the number of data bits of the contiguous memory unit and the size of the memory space occupied when the memory unit is allocated to each data.
  • step 220 the sum of the data bits of each data to be synchronously accessed and the number of data processed bits of the atomic operation instruction are compared.
  • step 230 the atomic operation instruction is divided into data segments corresponding to the number of data based on the sum of the data processing bits of the atomic operation instruction being greater than or equal to the data bit number of each data to be synchronously accessed.
  • the data is also shared by four data to be accessed synchronously (A to D), and each data includes 16 bits for explanation. If the number of data processing bits of the atomic operation instruction is 64 bits, that is, the number of data processing bits of the atomic operation instruction is equal to the sum of the data bits of the data to be synchronously accessed (16 ⁇ 4), then the atomic operation can be performed.
  • the instruction is divided into four data segments. Each data segment can respectively access one of the data to be accessed synchronously.
  • the number of data processing bits of the atomic operation instruction is 32 bits, that is, the data processing digit of the atomic operation instruction is smaller than the sum of the data bits of the data to be synchronously accessed (16 ⁇ 4)
  • the atomic operation instruction performs the corresponding data segment division. The reason is because the sum of the number of data bits to be accessed synchronously exceeds the index of an atomic operation instruction. The upper limit of the number of data bits that can be processed by the cycle. These data to be synchronized cannot be accessed synchronously within the instruction cycle of the same atomic operation instruction.
  • the step of performing the atomic operation instructions of step 130 to access the data corresponding thereto may include, for example, reading and/or modifying data in one instruction cycle.
  • the instruction cycle is the length of time during which the atomic operation instruction is executed.
  • the execution of the atomic operation instructions is "read.” Then, after the atomic operation instruction is executed, the value of each data can be returned as a return value.
  • the execution of the atomic operation instructions is "modified.” Then, after the atomic operation instruction is executed, the value of each data will be changed accordingly.
  • the method for synchronously accessing data of the embodiment may further include the step 140, determining, according to the return value of the data to be accessed synchronously, the association relationship of the data to be synchronously accessed in the instruction cycle. .
  • the association relationship of each data to be accessed synchronously may include, for example, a numerical operation relationship or a logical operation relationship.
  • the data is also shared by four data to be accessed synchronously (A to D), and each data includes 16 bits for explanation.
  • the values of other data to be accessed synchronously may be determined according to one of the four data to be accessed synchronously, for example, when the data to be accessed synchronously is B, C, and D. If the value is 0, the value of the data A to be accessed synchronously is set to 1.
  • the value of the remaining data may be calculated according to the values of the data of the four to be accessed synchronously.
  • a continuous memory unit 310 is allocated for the four to-be-synchronized access data A to D (as shown in step 110 in FIG. 1).
  • the data between the to-be-synchronized access data A to D is determined.
  • the association relationship (shown as step 140 in Figure 1). After the association is determined, it may be necessary to update other data based on one or more of the data to be accessed synchronously.
  • synchronous access of data to be synchronously accessed is performed under the premise that the total number of bits of the data is less than or equal to the number of data processing bits of the atomic operation instruction, so that other threads can be prevented from modifying the data to be simultaneously accessed.
  • FIG. 4 there is shown a schematic structural diagram 400 of a synchronous access device for data according to an embodiment of the present application.
  • the synchronous access device of the data of this embodiment may include an allocation module 410, a dividing module 420, and an access module 430.
  • the distribution module 410 can be configured to allocate contiguous memory units to data to be accessed synchronously.
  • the number of data bits of the contiguous memory unit is the sum of the data bits of the data to be accessed synchronously.
  • the partitioning module 420 is configurable to divide the atomic operation instruction into data segments corresponding to the number of data to be accessed synchronously based on the number of data to be accessed synchronously and the number of data bits of data to be accessed synchronously.
  • the number of bits of each data segment is greater than or equal to the number of bits of data to be accessed synchronously corresponding thereto.
  • the access module 430 can be configured to access data to be accessed synchronously within one instruction cycle.
  • the instruction cycle is the length of time during which the atomic operation instruction is executed.
  • the dividing module 420 may be further configured to obtain data bits for each data to be accessed synchronously; compare the sum of the data bits of each data to be synchronously accessed and the data processing of the atomic operation instruction The number of bits; and the number of data processing bits based on the atomic operation instruction is greater than or equal to the sum of the data bits of the data to be synchronously accessed, and the atomic operation instruction is divided into data segments corresponding to the number of data.
  • the access module 430 can be further configured to read and/or modify data to be accessed synchronously within one instruction cycle.
  • the synchronous access device of the data in this embodiment may further include an association determining module 440.
  • the association determining module 440 can be configured to determine an association relationship of each data to be synchronously accessed based on a return value of the data accessed for accessing the synchronization during the instruction cycle.
  • association relationship may include, for example, a numerical operation relationship or a logical operation relationship.
  • each block of the flowchart or block diagrams can represent a module, a program segment, or a portion of code that includes one or more logic for implementing the specified.
  • Functional executable instructions can also occur in a different order than that illustrated in the drawings. For example, two successively represented blocks may in fact be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending upon the functionality involved.
  • each block of the block diagrams and/or flowcharts, and combinations of blocks in the block diagrams and/or flowcharts can be implemented in a dedicated hardware-based system that performs the specified function or operation. Or it can be implemented by a combination of dedicated hardware and computer instructions.
  • the units or modules described in the embodiments of the present application may be implemented by software or by hardware.
  • the described unit or module may also be provided in the processor, for example, as a processor including an allocation module, a partitioning module, and an access module.
  • the names of these units or modules do not constitute a limitation on the unit or the module itself in some cases.
  • the allocation module may also be described as "a module for allocating contiguous memory units to data".
  • the present application further provides a computer readable storage medium, which may be a computer readable storage medium included in the apparatus described in the foregoing embodiment, or may exist separately, not A computer readable storage medium that is assembled into the device.
  • the computer readable storage medium stores one or more programs that are used by one or more processors to perform the formula input methods described in this application.

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

L'invention concerne un procédé d'accès synchrone aux données (100) et un dispositif d'accès synchrone. Le procédé d'accès synchrone aux données (100) comprend les étapes qui consistent : à attribuer une unité de mémoire continue à des données devant faire l'objet d'un accès synchrone (110), l'élément numérique de données de l'unité de mémoire continue étant la somme des éléments numériques de données de toutes les données devant faire l'objet d'un accès synchrone ; à diviser une instruction d'opération atomique en segments de données correspondant à la quantité de données devant faire l'objet d'un accès synchrone en fonction de la quantité de données devant faire l'objet d'un accès synchrone et de l'élément numérique de données de chacune des données devant faire l'objet d'un accès synchrone (120), l'élément numérique de chaque segment de données étant supérieur ou égal à celui des données correspondantes devant faire l'objet d'un accès synchrone ; et à accéder aux données devant faire l'objet d'un accès synchrone au cours d'une période d'instruction (130), cette période d'instruction étant une durée destinée à l'exécution de l'instruction d'opération atomique. Au moyen de ce procédé et de cet appareil, des données ayant une relation d'association peuvent faire l'objet d'un accès synchrone au cours de la même période d'instruction d'opération atomique, ce qui permet d'améliorer l'efficacité de l'accès aux données, et, par conséquent, d'augmenter la vitesse de traitement de données d'un ordinateur.
PCT/CN2015/099893 2015-08-31 2015-12-30 Procédé d'accès synchrone aux données et dispositif d'accès synchrone WO2017036041A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510548924.X 2015-08-31
CN201510548924.XA CN105159766B (zh) 2015-08-31 2015-08-31 数据的同步访问方法和同步访问装置

Publications (1)

Publication Number Publication Date
WO2017036041A1 true WO2017036041A1 (fr) 2017-03-09

Family

ID=54800629

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/099893 WO2017036041A1 (fr) 2015-08-31 2015-12-30 Procédé d'accès synchrone aux données et dispositif d'accès synchrone

Country Status (2)

Country Link
CN (1) CN105159766B (fr)
WO (1) WO2017036041A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105159766B (zh) * 2015-08-31 2018-05-25 安一恒通（北京）科技有限公司 数据的同步访问方法和同步访问装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101052947A (zh) * 2004-11-03 2007-10-10 皇家飞利浦电子股份有限公司 支持simd指令的可编程数据处理电路
CN101133396A (zh) * 2005-01-24 2008-02-27 国际商业机器公司 用于在多处理器环境中管理对共享资源的存取的方法
US20140181421A1 (en) * 2012-12-21 2014-06-26 Advanced Micro Devices, Inc. Processing engine for complex atomic operations
CN103970506A (zh) * 2008-03-28 2014-08-06 英特尔公司 用于实现高效同步和并行归约操作的向量指令
CN104025031A (zh) * 2011-12-28 2014-09-03 英特尔公司 减少应用中对共享存储器单元执行的顺序操作的数量
CN105159766A (zh) * 2015-08-31 2015-12-16 安一恒通（北京）科技有限公司 数据的同步访问方法和同步访问装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9256476B2 (en) * 2011-12-10 2016-02-09 International Business Machines Corporation Expedited module unloading for kernel modules that execute read-copy update callback processing code

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101052947A (zh) * 2004-11-03 2007-10-10 皇家飞利浦电子股份有限公司 支持simd指令的可编程数据处理电路
CN101133396A (zh) * 2005-01-24 2008-02-27 国际商业机器公司 用于在多处理器环境中管理对共享资源的存取的方法
CN103970506A (zh) * 2008-03-28 2014-08-06 英特尔公司 用于实现高效同步和并行归约操作的向量指令
CN104025031A (zh) * 2011-12-28 2014-09-03 英特尔公司 减少应用中对共享存储器单元执行的顺序操作的数量
US20140181421A1 (en) * 2012-12-21 2014-06-26 Advanced Micro Devices, Inc. Processing engine for complex atomic operations
CN105159766A (zh) * 2015-08-31 2015-12-16 安一恒通（北京）科技有限公司 数据的同步访问方法和同步访问装置

Also Published As

Publication number Publication date
CN105159766B (zh) 2018-05-25
CN105159766A (zh) 2015-12-16

Similar Documents

Publication Publication Date Title
US9824011B2 (en) Method and apparatus for processing data and computer system
CN106569891B (zh) 一种存储***中任务调度执行的方法和装置
US9710306B2 (en) Methods and apparatus for auto-throttling encapsulated compute tasks
CN106951488B (zh) 一种日志记录方法和装置
US9798543B2 (en) Fast mapping table register file allocation algorithm for SIMT processors
JPH03282958A (ja) 電子計算機
US10019283B2 (en) Predicting a context portion to move between a context buffer and registers based on context portions previously used by at least one other thread
US11720496B2 (en) Reconfigurable cache architecture and methods for cache coherency
US20230367637A1 (en) Shared memory management method and device
US8359459B2 (en) Using hardware support to reduce synchronization costs in multithreaded applications
US20170300255A1 (en) Method and Apparatus for Detecting Transaction Conflict and Computer System
US9442759B2 (en) Concurrent execution of independent streams in multi-channel time slice groups
WO2017036041A1 (fr) Procédé d'accès synchrone aux données et dispositif d'accès synchrone
US10976934B2 (en) Prioritizing pages to transfer for memory sharing
CN105378652A (zh) 线程共享资源分配方法及装置
US9501328B2 (en) Method for exploiting parallelism in task-based systems using an iteration space splitter
KR20130021637A (ko) 멀티 코어 시스템의 인터럽트 할당 방법 및 장치
US11656905B2 (en) Delegation control based on program privilege level and page privilege level
CN112527502A (zh) 一种优化音视频编解码器内存的方法、装置及介质及设备
US20130110882A1 (en) System and method for persisting object pointers
JPH04120652A (ja) 並列処理装置
US20160275220A1 (en) Multi-processor simulation on a multi-core machine
CN112506660A (zh) 一种优化音视频编解码器内存的方法、装置及存储介质
KR20210021848A (ko) 멀티코어 프로세서 시스템에서 메모리 할당 방법 및 장치, 이를 위한 기록매체
CN117687805A (zh) 一种应用于plc与装置的多线程数据同步方法及***

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15902845

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 11.06.2018)

122 Ep: pct application non-entry in european phase

Ref document number: 15902845

Country of ref document: EP

Kind code of ref document: A1