WO2017032911A1 - System and method for generating images on tft screens - Google Patents

System and method for generating images on tft screens Download PDF

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Publication number
WO2017032911A1
WO2017032911A1 PCT/ES2016/070511 ES2016070511W WO2017032911A1 WO 2017032911 A1 WO2017032911 A1 WO 2017032911A1 ES 2016070511 W ES2016070511 W ES 2016070511W WO 2017032911 A1 WO2017032911 A1 WO 2017032911A1
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WIPO (PCT)
Prior art keywords
tft
signal
screen
clock
serial
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PCT/ES2016/070511
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Spanish (es)
French (fr)
Inventor
Jesús Manuel HERNÁNDEZ MANGAS
Jesús ARIAS ÁLVAREZ
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Universidad De Valladolid
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Publication of WO2017032911A1 publication Critical patent/WO2017032911A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/22—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of characters or indicia using display control signals derived from coded signals representing the characters or indicia, e.g. with a character-code memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/42—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of patterns using a display memory without fixed position correspondence between the display memory contents and the display position on the screen

Definitions

  • the present invention relates to a novel system and method of generating images on TFT screens (thin film transistor screen) in which predetermined and pre-stored characters or figures are transferred directly from a non-volatile serial flash memory to the TFT screen.
  • TFT screens thin film transistor screen
  • the invention has been provided for low-cost TFT displays in which the computational capabilities of the electronics associated with the display are limited.
  • the solution described here allows the use of general-purpose microcontrollers avoiding the need to integrate specific controllers of TFT displays and internal or external RAM. Additionally, the memory requirements in the general-purpose microcontroller are minimal as they are limited to a brief set of pointers instead of the video data itself relative to the images to be displayed on the TFT screen.
  • the invention falls within the technical field of electronic systems for the visualization of content, more specifically in that related to TFT screens.
  • the pixels are smaller than one millimeter in size with three color components, red, green and blue, which can be chosen from a palette of at least 64 levels individually for each pixel, and with resolutions that are around one million pixels even for screens of reduced dimensions. They also have a fairly reduced cost.
  • these TFT screens require a control electronics (internal or external to the microcontroller) that allows data storage (internal or external RAM) and generates a periodic data refresh to the TFT screen.
  • WO2003021566 A1, CN204178686 U and CN102945658 A describe various TFT controllers. TFT technology implies that even on small screens the volume of data to be transferred is considerable.
  • Image generation systems for conventional TFT screens change the image displayed indirectly: they first write to the RAM area of video destined to refresh the video, and then the TFT controller (peripheral interface) will transfer that data to the screen in successive refresh cycles.
  • the graphic character of the images represented translates into a remarkable volume of data that must be modified in the video RAM when large areas of the image are changed, resulting in a slow response to changes.
  • This aspect is not usually relevant in desktop computers because they have large bandwidths in their memories and a lot of computing power. But in the microcontrollers that integrate this type of TFT screens for specific applications, such as elevator position indicators, road indicator panels, etc., these resources are usually much more limited.
  • processors such as the LPC2478
  • a clock frequency below 100MHz
  • internal RAM and / or Flash memory below the Mbyte and external DRAM of 32 or 16 bit data width
  • changes in video memory tend to far exceed the duration of a screen refresh cycle, creating a visual sensation of false image persistence.
  • the images shown are generally not arbitrary but combinations of predefined figures such as alphanumeric characters of various sizes and fixed icons. These elements have to be stored in the non-volatile memory of the system from which they are transferred to the video RAM when they want to be represented on the screen, so that you have the same information taking up space in two different memories. Therefore, the technical problem that arises is the display on TFT screens of predetermined characters or figures by means of an image generation system that implies a reduction of components and therefore of economic cost and a reduction of the computing power necessary to do so. , with respect to the currently existing solutions.
  • a first object of the present invention is an image generation system on TFT screens comprising a TFT screen, at least one flash memory with serial interface where characters to be displayed on the TFT screen and a microcontroller are stored. Depending on the type of characters to be displayed or their color needs, a single or several flash memories connected in parallel will be necessary to store the different characters to be displayed.
  • the microcontroller comprises:
  • a timer module configured to generate a signal of width proportional to a number of cycles of a clock signal.
  • the number of cycles of the clock signal will be programmable depending on the particularities of the TFT screen and the associated electronics as well as the type of character to be displayed. Each cycle of this signal generated by the timer module corresponds to one pixel of the TFT screen.
  • the clock signal will be synchronous with the internal clock of the microcontroller. This signal will control the number of clock cycles that are applied to flash memories during data reading;
  • serial peripheral interface port configured to manage the at least one flash memory. This port will generate the signals that will enable reading in flash memories;
  • system additionally comprises means for generating a clock input signal of the TFT screen from the signal generated by the timer module and the clock signal and a switch that selects a signal clock of the at least one flash memory between the clock input signal of the TFT screen and a clock signal of the serial peripheral interface port, so that the characters in the at least one flash memory are transmitted directly to the TFT screen
  • the system comprises an internal clock for the generation of the clock signal.
  • This internal clock generally provides a fixed frequency square wave. This signal can also be provided from a clock external to the system.
  • the timer module comprises having an active output selected between an output by comparison and an output with pulse width modulation whereby the signal of width proportional to the clock signal is generated.
  • the at least one single flash memory with serial interface is a peripheral interface memory (SPI) connected in series to the microcontroller.
  • the at least one serial interface flash memory is a quad-serial serial interface (SQI) memory, which is capable of reading 4 bits of data for each clock cycle.
  • SQL quad-serial serial interface
  • the at least one flash memory with serial system interface are two quad serial serial interface (SQI) memories connected in parallel.
  • the system comprises a color allocation module connected to the at least one flash memory to assign colors to the characters shown on the TFT screen.
  • the color allocation module comprises 4 AND doors.
  • Each of the AND doors has a first common input connected to a video output of the serial SPI memory and additionally a second input.
  • Each second input of each AND gate is connected, respectively, to one of the general purpose input / output pins, so that the color assignment module is configured to generate black background monochrome characters.
  • the color allocation module comprises a quadruplex multiplexer with an input connected to a video output of the SPI memory, 4 first inputs connected respectively to 4 general purpose input / output pins to assign a color to each character and 4 second inputs respectively connected to 4 general purpose input / output pins to assign a color to a background.
  • the color assignment module is configured to generate monochrome characters with a monochrome background.
  • a second object of the present invention is a method of generating images on TFT screens that makes use of the system described above. Said procedure comprises the following steps:
  • the method also assigns color to the characters shown on the TFT screen by means of the color assignment module.
  • the method sends a number of clock pulses between two active cycles of the TFT display clock input signal to mark a start of a new line of characters.
  • the method comprises sending read commands to the at least one flash memory.
  • the memory requirements in the microcontroller are minimal as they are limited to a brief set of pointers instead of the video data itself.
  • the change in the value of these pointers will immediately result in the representation of a different image, with no more time elapsing than that of a single refresh cycle;
  • TFT is made directly from the video output of the memories to the video inputs on the screen (RGB inputs) or through the interposition of very simple logic gates or multiplexers, which significantly reduces the memory needs of the system; Y,
  • Figure 1. Shows the block diagram of an embodiment of the image generation system on TFT screens.
  • Figure 2. Shows the block diagram of an embodiment of the color assignment module for the representation of characters with a depth of 1 bit per pixel, with 16 possible colors for the foreground and black background.
  • Figure 3. Shows the block diagram of an embodiment of the color assignment module for the representation of characters with a depth of 1 bit per pixel, 16 possible colors for the foreground and color background will be selected from 16 colors.
  • Figure 4. Shows the block diagram of an embodiment of the color assignment module for the representation of characters with a depth of 4 bits per pixel.
  • the flash memory has a quad-serial serial input / output (SQI) interface with a data width selected by command of 1 or 4 bits.
  • SQL quad-serial serial input / output
  • Figure 5. Shows the block diagram of an embodiment example of the color assignment module for a depth of 8 bit per pixel.
  • the two flash memories have a quad-serial serial input / output interface (SQI) with a data width selected by command of 1 or 4 bits.
  • SQL quad-serial serial input / output interface
  • Figure 6. Shows a schedule of an example of the process of generating images on a TFT screen showing the shape of the different control signals generated for the transmission of a video line from the flash memories to the TFT screen.
  • FIG. 1 is the block diagram of an embodiment of the image generation system on TFT screens in which the main components of said system and the way in which they are connected are shown. These components are: the TFT display (1.1), the general purpose microcontroller (1.2), the integrated peripherals (1.21-1.24) in the microcontroller (1.2), a plurality of serial Flash memories (1.3) with the graphic information (characters ) stored, the clock generation logic (1.4) for the generation of the screen clock signals (1.1) and the memories (1.3) and the color generation logic (1.5) that will depend on the color depth desired.
  • the peripherals integrated in the microcontroller are: a clock generator (1.21), a timer (1.22), a SPI serial port (1.23) and GPIO general purpose input and output pins (1.24).
  • the system in Figure 1 shows the TFT screen (1.1) with Your typical interface signals.
  • TFT displays are synchronous devices, with a clock input (CLK) through which a clock signal (PIXCLK) is received that governs your internal state machine. It is therefore not necessary to follow a rigorous timing during the refresh of the screen, as long as the total count of clock pulses is correct and the total time of the refreshment is not too large and in place of flickering.
  • the TFT screens have a data validation (DE) input and two synchronization inputs, horizontal (HSYNC) and vertical (VSYNC), although in many cases these last two signals are optional since they are generated internally from the signal of.
  • DE data validation
  • HSYNC horizontal
  • VSYNC vertical
  • the remaining inputs of the TFT screen (1.1) are the video inputs of the screen corresponding to the bits with the level of each color component (R: red, G: green, B: blue) encoded as a binary number of 8 or 6 bits.
  • the bit width will depend on the specific TFT display model (1.1).
  • These RGB inputs will be connected directly to the specific outputs of the series flash memories (1.3) or by interposition of logic gates, multiplexers or demultiplexers, among others, that make up the logic of color generation (1.5).
  • the other basic component of the system is the microcontroller (1.2), of which only the subsystems involved in the generation of the images towards the TFT screen (1.1) have been represented, but which would have additional subsystems for the management of other aspects related to TFT screen control such as serial communication interfaces (CAN / LIN / RS485 / USB, ...) or timers for the generation of acoustic signals, etc.
  • the microcontroller has the following peripherals:
  • a clock generator (1.21) that allows a square signal (CLKosc) of a frequency compatible with the display to be obtained on a pin, (in the order of tens of megahertz, proportional to the total number of pixels on the screen).
  • CLKosc square signal
  • Many modern microcontrollers generate their clock signal internally and can direct it to a pin if configured properly. If the microcontroller does not have an internal clock generator, said clock signal can still be generated externally and applied to both the clock generation logic (1.4) and the microcontroller (1.2) itself.
  • a timer module (1.22) with at least one active output by comparison or with PWM mode ('Pulse width modulation').
  • This peripheral will be used to generate a pulse corresponding to a programmable number of cycles of the square signal of the clock generator (CLKosc).
  • a logical AND type function is performed, through an AND gate (1.41), between this pulse and the clock signal (CLKosc), thereby obtaining a train of a precise number of pulses at the clock input of the screen (PIXCLK ). If the DE signal is active each of these pulses will enter the data of a pixel on the screen, while if DE is inactive the pulses correspond to the horizontal or vertical retracement times of the screen.
  • Flash memories with serial interface (1.3).
  • the type, number, and capacity of these memories will depend on the color depth of the generated images as well as the total amount of graphic objects that they should store and their respective pixel sizes. For the types of applications envisaged, color depths of 1, 4 or 8 bits per pixel have been considered (although greater color depths could be achieved by connecting more SQI memories in parallel, for example with 3 SQI memories 12-bit depths would be achieved per pixel):
  • a single SPI memory is used; or in the case of 4 bits per pixel the memory must be SQI to be able to simultaneously obtain the 4 bits with the pixel color information; and, or in the case of 8 bits per pixel, two SQI type memories connected in parallel are used.
  • All these memories have the characteristic of being able to present a new data at the output and increase their address counter automatically for each clock pulse they receive (each positive pulse of the PIXCLK signal), needing only an initial command from the SPI serial port
  • a clock generation logic comprising a switch (1.42) for selecting the input clock signal of the Flash memories (1.3) between the SCK signal from the SPI serial port (1.23) and the PIXCLK signal corresponding to the clock signal of the TFT screen previously generated in the AND gate (1.41).
  • the SCK signal will be selected while the read commands are sent to memory via the SPI serial port (1.23), then the PIXCLK signal will be selected to send the characters to the screen (1.1) through the corresponding ones Video outputs of flash memories (1.3). In this way, once the Flash memory has been read, the data automatically passes to the screen without the need for direct intervention from the microcontroller CPU.
  • the SCK signal must also be selected when programming the contents of flash memories from the microcontroller or when reading memory data that is relevant to the microcontroller but not for image generation.
  • a logic block related to the generation of color (1.5) This block depends on the desired color depth, and can have the following implementations:
  • FIG. 2 shows a particular implementation of this color assignment block (1.5) for this color depth. This is the most basic implementation of the block (1.5) and only requires 4 AND (2.2) doors, so that the pixel will have the color selected by the 4 pins I, R, G, and B general purpose output GPIO (2.5) when a logical level of 1 is output from the video (SO) output of the SPI flash memory (2.1), or black otherwise. Note that although the images stored in flash memory are monochrome, their color can be varied depending on their position on the screen, so that we can simultaneously display up to 16 different colors.
  • connection will be (2.3) for a TFT with a resolution of 24 bit / pixel or (2.4) for a TFT with a resolution of 18 bit / pixel.
  • connection will be (2.3) for a TFT with a resolution of 24 bit / pixel or (2.4) for a TFT with a resolution of 18 bit / pixel.
  • FIG. 3 shows a particular implementation of this color assignment block (1.5) for this color depth.
  • a quadruple multiplexer (3.2), 4 pins I, R, G, and B general purpose output GPIO (3.3) are used to assign the color of the foreground characters and another 4 pins I, R, G, and B general purpose output GPIO (3.4) for background color assignment.
  • the connection will be (3.5) for a TFT with a resolution of 24 bit / pixel or (3.6) for a TFT with a resolution of 18 bit / pixel.
  • FIG. 4 shows a particular implementation of this color assignment block (1.5) for this color depth.
  • the video data comes from an SQI (4.1) memory and is 4 bits, so that it can be connected directly to the video inputs of the TFT screen.
  • the connection will be (4.2) for a TFT with a resolution of 24 bit / pixel or (4.3) for a TFT with a resolution of 18 bit / pixel.
  • a resistor (4.4) connected between the MOSI output of the microcontroller and the SI output of the memory (4.1) is required since when the SQI memory (4.1) is transferred to the 4-bit mode the SI pin is no longer input to be output, which would cause a conflict with the MOSI output of the microcontroller.
  • each pixel can have up to 16 different colors,
  • FIG. 5 shows a particular implementation of this color assignment block (1.5) for this color depth.
  • two SQI Flash memories (5.1 and 5.2) are used connected in parallel that provide a total of 8 bits per pixel whose clock signal comes from the clock logic (1.4) described above.
  • the color assignment responds to an RGB332 mode (with 3 bits for the red (R0, R1, R2) and green (G0, G1, G2) and 2 bits for the blue component (B0, B1) components.
  • Each pixel can have 256 different colors.
  • the resistors (5.5) connected between the MOSI output of the microcontroller and the SI inputs of the memories (4.1) are necessary to mitigate the possible logical conflicts between the SI / D3 output pins of both memories during the data reading phase of 4 bits (function D3), as well as with the MOSI pin of the microcontroller.
  • the resistances (5.6) between the MISO input and the SO outputs of the memories (4.1) are necessary to mitigate the possible logical conflicts between the SO / DO output pins of both memories during the data reading phase of 4 bits (DO function).
  • the connection could be (5.3) for a TFT with a resolution of 24 bit / pixel or (5.4) for a TFT with a resolution of 18 bit / pixel.
  • Figure 6 shows an example of carrying out a schedule with the control signals that are implemented for the generation of the images on the TFT screens.
  • This exemplary embodiment shows the time schedule corresponding to the single line refresh (6.1) on a TFT screen of the "DE only type, without HSYNC or VSYNC".
  • Said line (6.1) includes the sending of 3 characters (" ⁇ " (6.2), " ⁇ " (6.3), and an icon representing a man (6.4)) of the serial flash memories where they are stored on the TFT screen.
  • the signal DE (6.5) generated by one of the GPIO output pins (1.24) is activated for the duration of the visible part of the line to enable writing on the TFT screen.
  • the timer module Simultaneously the timer module generates the corresponding TIMER signal (6.6) the width of a programmable number of cycles of the clock signal.
  • the switch selects the PIXCLK signal (6.7) as the clock input of the serial flash memories, the characters (6.2, 6.3, 6.4) of the line (6.1) are sent, sending one character for each high cycle of the CLKSEL signal (6.8).
  • Each of the high cycles of the PIXCLK signal (6.7) comprises a plurality of pulses, so that in each pulse a pixel of the characters (6.2, 6.3, 6.4) of the line (6.1) that are to be transmitted is transmitted show on screen.
  • the SPI port clock is used to send read commands to Flash memory, which means sending a total of 32 or 40 clock pulses with the command byte, 3 address bytes and a possible padding byte.
  • PIXCLK (6.7) is used in the subsequent phase of reading data, so that the contents of the Flash memory are transferred to the screen directly, without the intervention of the microcontroller CPU.
  • each send of a character (6.2, 6.3, 6.4) from the memories to the screen is preceded by a pulse train of the SCK clock signal (6.9) of the SPI serial port for the character read command a send, so the switch will select a signal between PIXCLK (6.7) and SCK (SPI) (6.9) alternately to first send the character read command (RD-cmd) and then send the character data (data) to the screen.
  • the composite clock signal, CLK (FLASH) (6.10) is obtained at the clock input of the Flash memories.
  • the system sends, between every two lines, a certain number of clock pulses (6.13), depending on the display model, which signal the beginning of a new line.
  • a larger number of pulses with the low DE signal would signal the start of the image frame or vertical retracement (not shown in Fig. 6).
  • the total number of clock pulses generated in the PIXCLK signal (6.7) is controlled by the TIMER timer output (6.6), while CLKSEL (6.8) indicates whether the SCK clock signal of the SPI port (6.9) reaches the Flash memory. ) or the PIXCLK signal (6.7).
  • CLKSEL (6.8) indicates whether the SCK clock signal of the SPI port (6.9) reaches the Flash memory.
  • PIXCLK signal (6.7) the PIXCLK (6.7) and SCK (SPI) (6.9) signals can be generated simultaneously if the CLKSEL (6.8) signal is inactive, which can be useful for reducing PIXCLK downtimes and thus increasing the frequency of screen refresh. In particular, this possibility can be used in the delayed times or if in the image we have large gaps (6.14) between the characters (6.2, 6.3, 6.4).
  • Flash memories have an additional input, / CS (6.11), which must be at a low level during the execution of the character read commands (RD-cmd) the data send commands (data) of the CLK signal (6.10 ) and in which a falling edge signals the first bit of the said commands.
  • / CS character read commands
  • a falling edge signals the first bit of the said commands.
  • Fig. 6 the temporal evolution of said signal is shown, which is only set to a high level briefly before of sending a new read command to Flash memories.
  • the VIDEO signal (6.12) is obtained at the outputs of the Flash memories, and in the example of Fig. 6 it is a single bit, which will generate monochrome images (blocks of color generation as shown in Fig. 2 or Fig. 3).
  • the VIDEO signal (6.12) can have an arbitrary value during the reading of the characters, according to the data programmed in the flash memories, although in Fig. 6 the trace corresponding to the video line is shown superimposed (6.1) Particular of this example.

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Abstract

The invention relates to a system and a method for generating images on TFT screens, comprising flash memories (1.3) with a serial interface where characters to be displayed are stored and a microcontroller (.2), where the microcontroller (1.2) comprises a timer module (1.22) which generates a signal proportional to a programmable clock signal; a serial peripheral interface port (1.23) for managing the flash memories; and general-purpose input/output pins (1.24) for enabling the writing on the TFT screen, where the system is configured so as to transmit the characters stored in the flash memories directly to the TFT screen without the insertion of RAM memories or TFT controllers.

Description

SISTEMA Y PROCEDIMIENTO DE GENERACIÓN  GENERATION SYSTEM AND PROCEDURE
DE IMÁGENES EN PANTALLAS TFT  OF IMAGES ON TFT SCREENS
OBJETO DE LA INVENCIÓN OBJECT OF THE INVENTION
La presente invención se refiere a un novedoso sistema y un procedimiento de generación de imágenes en pantallas TFT (pantalla de transistores de películas finas) en el que caracteres o figuras predeterminadas y prealmacenadas se transfieren de forma directa desde una memoria no volátil de tipo flash serie a la pantalla TFT. Preferentemente, la invención se ha previsto para pantallas TFT de bajo coste en el que las capacidades computacionales de la electrónica asociada a la pantalla son limitadas. The present invention relates to a novel system and method of generating images on TFT screens (thin film transistor screen) in which predetermined and pre-stored characters or figures are transferred directly from a non-volatile serial flash memory to the TFT screen. Preferably, the invention has been provided for low-cost TFT displays in which the computational capabilities of the electronics associated with the display are limited.
La solución aquí descrita permite utilizar microcontroladores de propósito general evitando la necesidad de integrar controladores específicos de pantallas TFT y memorias RAM internas o externas. Adicionalmente, los requisitos de memoria en el microcontrolador de propósito general son mínimos ya que se limitan a un breve conjunto de punteros en lugar de a los propios datos de vídeo relativos a las imágenes a mostrar en la pantalla TFT. The solution described here allows the use of general-purpose microcontrollers avoiding the need to integrate specific controllers of TFT displays and internal or external RAM. Additionally, the memory requirements in the general-purpose microcontroller are minimal as they are limited to a brief set of pointers instead of the video data itself relative to the images to be displayed on the TFT screen.
La invención se encuadra en el campo técnico de los sistemas electrónicos para la visualización de contenidos, más concretamente en el relacionado con pantallas TFT. The invention falls within the technical field of electronic systems for the visualization of content, more specifically in that related to TFT screens.
ANTECEDENTES DE LA INVENCIÓN BACKGROUND OF THE INVENTION
Las pantallas y paneles indicadores electrónicos convencionales de bajo coste suelen estar basados en dispositivos LCD (Pantallas de cristal líquido) segmentados de tipo pasivo que no incluyen ninguna electrónica integrada y donde sus terminales se conectan directamente a los electrodos del LCD. La electrónica de control de la propia pantalla LCD es de bajo coste ya que la memoria de vídeo que incorpora se limita a un bit por segmento. Este tipo de pantallas presentan una serie de inconvenientes entre los que están: Conventional, low-cost conventional electronic display panels and panels are usually based on segmented passive-type LCD (liquid crystal displays) that do not include any integrated electronics and where their terminals connect directly to the LCD electrodes. The electronic control of the LCD screen itself is low cost since the video memory it incorporates is limited to one bit per segment. These types of screens have a series of drawbacks, among which are:
• Mala estética: los caracteres alfanuméricos tienen formas artificiosas dado que se descomponen en un conjunto común de segmentos poligonales. La separación entre los segmentos es claramente visible. • Mal contraste: cuando el número de segmentos es elevado (>40) se recurre a su multiplexado mediante el uso de dos o más backplanes lo que reduce el contraste y puede requerir un ajuste manual mediante potenciómetros. • Poor aesthetics: alphanumeric characters have artificial forms since they decompose into a common set of polygonal segments. The separation between the segments is clearly visible. • Bad contrast: when the number of segments is high (> 40), multiplexing is used through the use of two or more backplanes, which reduces the contrast and may require manual adjustment by potentiometers.
• Imagen monocroma: los problemas de contraste excluyen la posibilidad de representar imágenes de colores variables. Mediante técnicas como el LCD de campo secuencial consistente en cambiar el color de la retroiluminación del LCD de forma sincronizada con el refresco de los segmentos se consiguen simular hasta 16 colores (US7502004 B2, CN1680994 A, US7557787 B2). Otra tecnología de visualizacion son las pantallas TFT (US8937691 B2) en las que a cada segmento (pixel) se puede aplicar una tensión concreta de forma individual gracias a la electrónica de conmutación incluida en la propia pantalla basada en transistores MOSFET de silicio amorfo, que dan nombre a esta tecnología. Este tipo de pantallas presentan una calidad de imagen muy superior a las pantallas LCD. Los píxeles son de tamaños inferiores al milímetro con tres componentes de color, rojo, verde y azul, que pueden elegirse entre una paleta de al menos 64 niveles de forma individual para cada pixel, y con resoluciones que rondan el millón de píxeles incluso para pantallas de dimensiones reducidas. Además tienen un coste bastante reducido. Sin embargo, estas pantallas TFT requieren una electrónica de control (interna o externa al microcontrolador) que permita el almacenamiento de datos (memoria RAM interna o externa) y que genere un refresco de datos periódico hacia la pantalla TFT. Los documentos WO2003021566 A1 , CN204178686 U y CN102945658 A describen diversos controladores de TFT. La tecnología TFT implica que incluso en pantallas pequeñas el volumen de datos a transferir sea considerable. Por ejemplo, en una pantalla de 480x272 pixeles, se necesitan 391.680 bytes que se deben transferir a la pantalla al menos cada 20 milisegundos para evitar parpadeos en la imagen. Estas cantidades de memoria superan ampliamente la capacidad de las memorias internas de los microcontroladores de propósito general actuales, lo que obliga a incorporar en las pantallas TFT controladores para memorias dinámicas externas además de periféricos de interfaz (controladores TFT) para la pantalla que se encargue del refresco periódico de la misma.  • Monochrome image: contrast problems exclude the possibility of representing images of variable colors. Through techniques such as the sequential field LCD consisting of changing the color of the LCD backlight in a synchronized manner with the refreshment of the segments, up to 16 colors can be simulated (US7502004 B2, CN1680994 A, US7557787 B2). Another display technology is the TFT screens (US8937691 B2) in which each segment (pixel) can be applied a specific voltage individually thanks to the switching electronics included in the screen based on amorphous silicon MOSFET transistors, which They give name to this technology. These types of screens have an image quality far superior to LCD screens. The pixels are smaller than one millimeter in size with three color components, red, green and blue, which can be chosen from a palette of at least 64 levels individually for each pixel, and with resolutions that are around one million pixels even for screens of reduced dimensions. They also have a fairly reduced cost. However, these TFT screens require a control electronics (internal or external to the microcontroller) that allows data storage (internal or external RAM) and generates a periodic data refresh to the TFT screen. WO2003021566 A1, CN204178686 U and CN102945658 A describe various TFT controllers. TFT technology implies that even on small screens the volume of data to be transferred is considerable. For example, on a 480x272 pixel screen, 391,680 bytes are needed, which must be transferred to the screen at least every 20 milliseconds to avoid flickering in the image. These amounts of memory far exceed the capacity of the internal memories of current general-purpose microcontrollers, forcing controllers for external dynamic memories in addition to interface peripherals (TFT controllers) for the screen that handles periodic soda of it.
Los sistemas de generación de imágenes para pantallas TFT convencionales cambian la imagen visualizada de forma indirecta: primero escriben en el área de memoria RAM de video destinada al refresco del video, y después el controlador TFT (periférico de interfaz) transferirá esos datos a la pantalla en los sucesivos ciclos de refresco. El carácter gráfico de las imágenes representadas se traduce en un notable volumen de datos que hay que modificar en la memoria RAM de video cuando se cambian áreas grandes de la imagen, lo que resulta en una respuesta lenta ante los cambios. Este aspecto no suele ser relevante en los equipos informáticos de sobremesa pues disponen de grandes anchos de banda en sus memorias y mucha potencia de cálculo. Pero en los microcontroladores que integran este tipo de pantallas TFT para aplicaciones específicas, como por ejemplo los indicadores de posición en ascensores, paneles indicadores de carretera, etc, estos recursos suelen estar mucho más limitados. Con procesadores como el LPC2478, con frecuencia de reloj inferior a los 100MHz, memorias RAM y/o Flash internas por debajo del Mbyte y DRAM externa de 32 o 16 bit de anchura de datos, los cambios en la memoria de vídeo suelen superar ampliamente la duración de un ciclo de refresco de la pantalla, creando una sensación visual de falsa persistencia de la imagen. Image generation systems for conventional TFT screens change the image displayed indirectly: they first write to the RAM area of video destined to refresh the video, and then the TFT controller (peripheral interface) will transfer that data to the screen in successive refresh cycles. The graphic character of the images represented translates into a remarkable volume of data that must be modified in the video RAM when large areas of the image are changed, resulting in a slow response to changes. This aspect is not usually relevant in desktop computers because they have large bandwidths in their memories and a lot of computing power. But in the microcontrollers that integrate this type of TFT screens for specific applications, such as elevator position indicators, road indicator panels, etc., these resources are usually much more limited. With processors such as the LPC2478, with a clock frequency below 100MHz, internal RAM and / or Flash memory below the Mbyte and external DRAM of 32 or 16 bit data width, changes in video memory tend to far exceed the duration of a screen refresh cycle, creating a visual sensation of false image persistence.
También conviene destacar que en las pantallas y paneles indicadores electrónicos convencionales de bajo coste, las imágenes que se muestran no son por lo general arbitrarias sino combinaciones de figuras predefinidas tales como caracteres alfanuméricos de diversos tamaños e iconos fijos. Estos elementos han de almacenarse en la memoria no volátil del sistema desde la que se transfieren a la memoria RAM de vídeo cuando se desean representar en la pantalla, de modo que se tiene la misma información ocupando espacio en dos memorias distintas. Por tanto, el problema técnico que se plantea es la visualización en pantallas TFT de caracteres o figuras predeterminadas mediante un sistema de generación de imágenes que implique una reducción de componentes y por tanto de coste económico y una reducción de la potencia de cálculo necesaria para hacerlo, con respecto a las soluciones actualmente existentes. It should also be noted that in conventional low-cost electronic displays and display panels, the images shown are generally not arbitrary but combinations of predefined figures such as alphanumeric characters of various sizes and fixed icons. These elements have to be stored in the non-volatile memory of the system from which they are transferred to the video RAM when they want to be represented on the screen, so that you have the same information taking up space in two different memories. Therefore, the technical problem that arises is the display on TFT screens of predetermined characters or figures by means of an image generation system that implies a reduction of components and therefore of economic cost and a reduction of the computing power necessary to do so. , with respect to the currently existing solutions.
DESCRIPCIÓN DE LA INVENCIÓN DESCRIPTION OF THE INVENTION
Con el objeto de solventar los problemas expuestos anteriormente, la presente invención describe un sistema y un procedimiento de generación de imágenes en pantallas TFT en el que figuras predeterminadas y previamente almacenadas en memorias no volátiles de tipo flash serie se transfieren de forma directa a la pantalla TFT. Esto permite utilizar microcontroladores de propósito general sin controlador de TFT ni memorias RAM internas o externas. Así, un primer objeto de la presente invención es un sistema de generación de imágenes en pantallas TFT que comprende una pantalla TFT, al menos una memoria flash con interfaz serie donde se almacenan unos caracteres a ser mostrados en la pantalla TFT y un microcontrolador. Dependiendo del tipo de caracteres que se vayan a mostrar o de las necesidades de color de los mismos, se hará necesario una única o varias memorias flash conectadas en paralelo para almacenar los diferentes caracteres que se vayan a mostrar. Nótese que a lo largo del presente documento cuando se dice "caracteres" se refiere a imágenes, letras, números, iconos o figuras predefinidas, que pueden tener tamaños y formas muy dispares. La capacidad de las memorias flash determinará la forma, tamaño y cantidad de caracteres que se almacenen. Estas memorias flash con interfaz serie son memorias externas a la pantalla TFT y al microcontrolador. El microcontrolador comprende: In order to solve the problems set forth above, the present invention describes a system and method of generating images on TFT screens in which predetermined figures and previously stored in Non-volatile series flash memories are transferred directly to the TFT screen. This allows you to use general-purpose microcontrollers without a TFT controller or internal or external RAM. Thus, a first object of the present invention is an image generation system on TFT screens comprising a TFT screen, at least one flash memory with serial interface where characters to be displayed on the TFT screen and a microcontroller are stored. Depending on the type of characters to be displayed or their color needs, a single or several flash memories connected in parallel will be necessary to store the different characters to be displayed. Note that throughout this document when it says "characters" it refers to predefined images, letters, numbers, icons or figures, which may have very different sizes and shapes. The capacity of flash memories will determine the shape, size and quantity of characters that are stored. These flash memories with serial interface are external memories to the TFT screen and the microcontroller. The microcontroller comprises:
- un módulo temporizador configurado para generar una señal de anchura proporcional a un número de ciclos de una señal de reloj. El número de ciclos de la señal de reloj será programable dependiendo de las particularidades de la pantalla TFT y de la electrónica asociada así como del tipo de carácter que vaya a mostrarse. Cada ciclo de esta señal generada por el módulo temporizador se corresponde a un pixel de la pantalla TFT. Además la señal de reloj será síncrona con el reloj interno del microcontrolador. Esta señal controlará el número de ciclos de reloj que se aplica a las memorias flash durante la lectura de datos;  - a timer module configured to generate a signal of width proportional to a number of cycles of a clock signal. The number of cycles of the clock signal will be programmable depending on the particularities of the TFT screen and the associated electronics as well as the type of character to be displayed. Each cycle of this signal generated by the timer module corresponds to one pixel of the TFT screen. In addition, the clock signal will be synchronous with the internal clock of the microcontroller. This signal will control the number of clock cycles that are applied to flash memories during data reading;
- un puerto de interfaz de periféricos serie configurado para gestionar la al menos una memoria flash. Este puerto generará las señales que habilitarán la lectura en las memorias flash;  - a serial peripheral interface port configured to manage the at least one flash memory. This port will generate the signals that will enable reading in flash memories;
- unos pines de entrada/salida de propósito general configurados para habilitar la escritura en la pantalla TFT. También estarán configurados para gestionar la selección de las memorias flash serie, el multiplexado de la señal de reloj de las memorias flash serie, y la selección del color de la imagen en las realizaciones con una profundidad de color de 1 bit por pixel;  - General purpose input / output pins configured to enable writing on the TFT screen. They will also be configured to manage the selection of the serial flash memories, the multiplexing of the clock signal of the serial flash memories, and the selection of the color of the image in the embodiments with a color depth of 1 bit per pixel;
donde el sistema adicionalmente comprende unos medios de generación de una señal de entrada de reloj de la pantalla TFT a partir de la señal generada por el módulo temporizador y de la señal de reloj y un conmutador que selecciona una señal de reloj de la al menos una memoria flash entre la señal de entrada del reloj de la pantalla TFT y una señal de reloj del puerto de interfaz de periféricos serie, de manera que los caracteres en la al menos una memoria flash se transmiten directamente a la pantalla TFT. where the system additionally comprises means for generating a clock input signal of the TFT screen from the signal generated by the timer module and the clock signal and a switch that selects a signal clock of the at least one flash memory between the clock input signal of the TFT screen and a clock signal of the serial peripheral interface port, so that the characters in the at least one flash memory are transmitted directly to the TFT screen
Dado que se emplean microcontroladores de propósito general (no específicamente diseñados para la gestión de pantallas TFT) se carece también de un periférico de interfaz TFT específico. Esto implica la necesidad de generar las señales de control tanto de la pantalla TFT como de las memorias flash mediante el microcontrolador empleando los periféricos habituales integrados en los mismos: temporizadores y puertos serie síncronos que ayudan a reducir la carga computacional en la CPU del microcontrolador, dejando aún un porcentaje apreciable del tiempo de CPU disponible para ejecutar el código principal de la aplicación. En una realización particular de la invención, el sistema comprende un reloj interno para la generación de la señal de reloj. Este reloj interno proporciona, generalmente, una onda cuadrada de frecuencia fija. Esta señal también puede ser proporcionada desde un reloj externo al sistema. En otra realización particular de la invención, el módulo temporizador comprende tener una salida activa seleccionada entre una salida por comparación y una salida con modulación por ancho de pulsos por donde se genera la señal de anchura proporcional a la señal de reloj. En otra realización particular de la invención, la al menos una única memoria flash con interfaz serie es una memoria de interfaz periférica (SPI) conectada en serie al microcontrolador. Since general purpose microcontrollers are used (not specifically designed for the management of TFT screens), a specific TFT interface peripheral is also lacking. This implies the need to generate the control signals of both the TFT screen and the flash memories by means of the microcontroller using the usual peripherals integrated in them: synchronous timers and serial ports that help reduce the computational load on the microcontroller's CPU, leaving still an appreciable percentage of the CPU time available to execute the main code of the application. In a particular embodiment of the invention, the system comprises an internal clock for the generation of the clock signal. This internal clock generally provides a fixed frequency square wave. This signal can also be provided from a clock external to the system. In another particular embodiment of the invention, the timer module comprises having an active output selected between an output by comparison and an output with pulse width modulation whereby the signal of width proportional to the clock signal is generated. In another particular embodiment of the invention, the at least one single flash memory with serial interface is a peripheral interface memory (SPI) connected in series to the microcontroller.
En otra realización particular de la invención, la al menos una memoria flash con interfaz serie es una memoria de interfaz serial cuádruple (SQI, "Serial Quad Interface"), que es capaz de leer 4 bits de datos por cada ciclo de reloj. In another particular embodiment of the invention, the at least one serial interface flash memory is a quad-serial serial interface (SQI) memory, which is capable of reading 4 bits of data for each clock cycle.
En otra realización particular de la invención, la al menos una memoria flash con interfaz serie del sistema son dos memorias de interfaz serial cuádruple (SQI) conectadas en paralelo. En otra realización particular de la invención, el sistema comprende un módulo de asignación de color conectado a la al menos una memoria flash para asignar colores a los caracteres mostrados en la pantalla TFT. In another particular embodiment of the invention, the at least one flash memory with serial system interface are two quad serial serial interface (SQI) memories connected in parallel. In another particular embodiment of the invention, the system comprises a color allocation module connected to the at least one flash memory to assign colors to the characters shown on the TFT screen.
En otra realización particular de la invención, para el caso de disponer de una única memoria de interfaz periférica (SPI) conectada en serie al microcontrolador, el módulo de asignación de color comprende 4 puertas AND. Cada una de las puertas AND tiene una primera entrada común conectada a una salida de vídeo de la memoria SPI en serie y adicionalmente una segunda entrada. Cada segunda entrada de cada puerta AND está conectada, respectivamente, a uno de los pines de entrada/salida de propósito general, de forma que el módulo de asignación de color está configurado para generar caracteres monocromos con fondo negro. En otra realización particular de la invención, para el caso de disponer de una única memoria de interfaz periférica (SPI) conectada en serie al microcontrolador, el módulo de asignación de color comprende un multiplexor cuádruple con una entrada conectada a una salida de video de la memoria SPI, 4 primeras entradas conectadas respectivamente a 4 pines de entrada/salida de propósito general para asignar un color a cada carácter y 4 segundas entradas conectadas respectivamente a 4 pines de entrada/salida de propósito general para asignar un color a un fondo. De este modo, el módulo de asignación de color está configurado para generar caracteres monocromos con fondo monocromo. En otra realización particular de la invención, cuando se dispone de una única memoria SQI, dicha memoria tiene 4 salidas de video conectadas directamente a unas entradas de video de la pantalla TFT de forma que el sistema está configurado para generar caracteres con profundidades de color de 4 bits por pixel. En otra realización particular de la invención, cuando se dispone de dos memorias SQI conectadas en paralelo, cada memoria tiene 4 salidas de video conectadas directamente a unas entradas de video de la pantalla TFT, estando el sistema configurado para generar caracteres con profundidades de color de 8 bits por pixel. Opcionalmente, también se ha previsto la interconexión de más de dos memorias SQI en paralelo para aumentar la profundidad de color de la imagen generada, aunque profundidades de 8 bits por pixel proporcionan una calidad de imagen en fotografías más que aceptable (los caracteres podrían ser fotos). Un segundo objeto de la presente invención es un procedimiento de generación de imágenes en pantallas TFT que hace uso del sistema descrito anteriormente. Dicho procedimiento comprende las siguientes etapas: In another particular embodiment of the invention, in the case of having a single peripheral interface memory (SPI) connected in series to the microcontroller, the color allocation module comprises 4 AND doors. Each of the AND doors has a first common input connected to a video output of the serial SPI memory and additionally a second input. Each second input of each AND gate is connected, respectively, to one of the general purpose input / output pins, so that the color assignment module is configured to generate black background monochrome characters. In another particular embodiment of the invention, in the case of having a single peripheral interface memory (SPI) connected in series to the microcontroller, the color allocation module comprises a quadruplex multiplexer with an input connected to a video output of the SPI memory, 4 first inputs connected respectively to 4 general purpose input / output pins to assign a color to each character and 4 second inputs respectively connected to 4 general purpose input / output pins to assign a color to a background. In this way, the color assignment module is configured to generate monochrome characters with a monochrome background. In another particular embodiment of the invention, when a single SQI memory is available, said memory has 4 video outputs directly connected to video inputs of the TFT screen so that the system is configured to generate characters with color depths of 4 bits per pixel In another particular embodiment of the invention, when two SQI memories are connected in parallel, each memory has 4 video outputs directly connected to video inputs of the TFT screen, the system being configured to generate characters with color depths of 8 bits per pixel Optionally, the interconnection of more than two SQI memories is also planned in parallel to increase the color depth of the generated image, although depths of 8 bits per pixel provide an image quality in photographs more than acceptable (characters could be photos). A second object of the present invention is a method of generating images on TFT screens that makes use of the system described above. Said procedure comprises the following steps:
- generar en el módulo temporizador una señal de anchura proporcional a un número programable de ciclos de una señal reloj;  - generate in the timer module a signal of width proportional to a programmable number of cycles of a clock signal;
- activar un modo escritura de la pantalla TFT mediante uno de los pines de entrada salida de propósito general del microcontrolador durante una duración de una parte visible de una línea de caracteres;  - activate a write mode of the TFT screen by means of one of the general purpose output input pins of the microcontroller for a duration of a visible part of a character line;
- generar una señal de entrada de reloj de la pantalla TFT a partir de la señal generada por el módulo temporizador y de la señal de reloj;  - generate a clock input signal from the TFT screen from the signal generated by the timer module and the clock signal;
-seleccionar mediante un conmutador una señal entre la señal de entrada del reloj de la pantalla TFT y una señal de reloj del puerto de interfaz de periféricos serie, donde la señal seleccionada es la señal de entrada de reloj de la al menos una memoria flash; y,  - select by means of a switch a signal between the clock input signal of the TFT screen and a clock signal of the serial peripheral interface port, where the selected signal is the clock input signal of the at least one flash memory; Y,
- enviar desde la al menos una memoria flash un carácter de la línea de caracteres directamente a la pantalla TFT cuando el conmutador seleccione la señal de entrada de reloj de la pantalla TFT y la señal de entrada de reloj de la pantalla TFT esté activa.  - send from the at least one flash memory a character from the character line directly to the TFT screen when the switch selects the clock input signal from the TFT screen and the clock input signal from the TFT screen is active.
En una realización particular, el método además asigna color a los caracteres mostrados en la pantalla TFT mediante el módulo de asignación de color. In a particular embodiment, the method also assigns color to the characters shown on the TFT screen by means of the color assignment module.
En otra realización particular, el método envía un número de pulsos de reloj entre dos ciclos activos de la señal de entrada de reloj de la pantalla TFT para marcar un comienzo de una nueva línea de caracteres. In another particular embodiment, the method sends a number of clock pulses between two active cycles of the TFT display clock input signal to mark a start of a new line of characters.
En otra realización particular, cuando el conmutador selecciona la señal de reloj del puerto de interfaz de periféricos serie, el procedimiento comprende enviar comandos de lectura a la al menos una memoria flash. Así, la solución aquí descrita presenta las siguientes ventajas con respecto a otras soluciones existentes: In another particular embodiment, when the switch selects the clock signal from the serial peripheral interface port, the method comprises sending read commands to the at least one flash memory. Thus, the solution described here has the following advantages over other existing solutions:
- los requisitos de memoria en el microcontrolador son mínimos pues se limitan a un breve conjunto de punteros en lugar de a los propios datos de vídeo. El cambio en el valor de dichos punteros se traducirá inmediatamente en la representación de una imagen distinta, sin que transcurra más tiempo que el de un único ciclo de refresco;  - The memory requirements in the microcontroller are minimal as they are limited to a brief set of pointers instead of the video data itself. The change in the value of these pointers will immediately result in the representation of a different image, with no more time elapsing than that of a single refresh cycle;
- no se hace necesaria la existencia de un controlador específico de la pantalla TFT ni de memorias RAM internas ni externas lo que simplifica la implementación del sistema reduciendo el número de componentes y por ende de su coste económico;  - the existence of a specific TFT screen controller or internal or external RAM memory is not necessary, which simplifies the implementation of the system by reducing the number of components and therefore its economic cost;
- la transmisión de los caracteres desde las memorias flash hasta la pantalla - the transmission of characters from flash memories to the screen
TFT se hace de forma directa desde la salida de video de las memorias hacia las entradas de video la pantalla (entradas RGB) o mediante la interposición de puertas lógicas o multiplexores muy simples, lo que reduce muy significativamente las necesidades de memoria del sistema; y, TFT is made directly from the video output of the memories to the video inputs on the screen (RGB inputs) or through the interposition of very simple logic gates or multiplexers, which significantly reduces the memory needs of the system; Y,
- se evitan duplicidades de memorias al no hacerse necesario incluir memorias - duplication of memories is avoided as it is not necessary to include memories
RAM. RAM.
BREVE DESCRIPCIÓN DE LAS FIGURAS Para complementar la descripción que se está realizando y con objeto de ayudar a una mejor comprensión de las características de la invención, se acompaña como parte integrante de dicha descripción, un juego de dibujos en donde con carácter ilustrativo y no limitativo, se ha representado lo siguiente: Figura 1.- Muestra el diagrama de bloques de un ejemplo de realización del sistema de generación de imágenes en pantallas TFT. BRIEF DESCRIPTION OF THE FIGURES To complement the description that is being made and in order to help a better understanding of the characteristics of the invention, a set of drawings is attached as an integral part of said description, where it is illustrative and not limiting , the following has been represented: Figure 1.- Shows the block diagram of an embodiment of the image generation system on TFT screens.
Figura 2.- Muestra el diagrama de bloques de un ejemplo de realización del módulo de asignación de color para la representación de caracteres con una profundidad de 1 bit por pixel, con 16 colores posibles para el primer plano y fondo negro. Figure 2.- Shows the block diagram of an embodiment of the color assignment module for the representation of characters with a depth of 1 bit per pixel, with 16 possible colors for the foreground and black background.
Figura 3.- Muestra el diagrama de bloques de un ejemplo de realización del módulo de asignación de color para la representación de caracteres con una profundidad de 1 bit por pixel, 16 colores posibles para el primer plano y fondo de color seleccionare entre 16 colores. Figura 4.- Muestra el diagrama de bloques de un ejemplo de realización del módulo de asignación de color para la representación de caracteres con una profundidad de 4 bits por pixel. La memoria flash tiene una interfaz de entrada/salida serial cuádruple (SQI) con un ancho de datos seleccionare por comando de 1 o 4 bits. Figure 3.- Shows the block diagram of an embodiment of the color assignment module for the representation of characters with a depth of 1 bit per pixel, 16 possible colors for the foreground and color background will be selected from 16 colors. Figure 4.- Shows the block diagram of an embodiment of the color assignment module for the representation of characters with a depth of 4 bits per pixel. The flash memory has a quad-serial serial input / output (SQI) interface with a data width selected by command of 1 or 4 bits.
Figura 5.- Muestra el diagrama de bloques de un ejemplo de realización del módulo de asignación de color para una profundidad de 8 bit por pixel. Las dos memorias flash tienen una interfaz de entrada/salida serial cuádruple (SQI) con un ancho de datos seleccionare por comando de 1 o 4 bits. Figure 5.- Shows the block diagram of an embodiment example of the color assignment module for a depth of 8 bit per pixel. The two flash memories have a quad-serial serial input / output interface (SQI) with a data width selected by command of 1 or 4 bits.
Figura 6.- Muestra un cronograma de un ejemplo de realización del proceso de generación de imágenes en una pantalla TFT mostrando la forma de las distintas señales de control generadas para la transmisión de una línea de video desde las memorias flash hasta la pantalla TFT. Figure 6.- Shows a schedule of an example of the process of generating images on a TFT screen showing the shape of the different control signals generated for the transmission of a video line from the flash memories to the TFT screen.
DESCRIPCIÓN DE VARIOS EJEMPLOS DE REALIZACIÓN DE LA INVENCIÓN DESCRIPTION OF VARIOUS EXAMPLES OF EMBODIMENT OF THE INVENTION
Seguidamente se realiza, con carácter ilustrativo y no limitativo, una descripción de varios ejemplos de realización de la invención, haciendo referencia a la numeración adoptada en las figuras. Next, a description of several embodiments of the invention is made, by way of illustration and not limitation, with reference to the numbering adopted in the figures.
La figura 1 es el diagrama de bloques de un ejemplo de realización del sistema de generación de imágenes en pantallas TFT en el que se muestran los principales componentes del citado sistema y el modo en que se conectan entre sí. Dichos componentes son: la pantalla TFT (1.1), el microcontrolador (1.2) de propósito general, los periféricos integrados (1.21-1.24) en el microcontrolador (1.2), una pluralidad de memorias Flash serie (1.3) con la información gráfica (caracteres) almacenada, la lógica de generación de reloj (1.4) para la generación de las señales de reloj de la pantalla (1.1) y de las memorias (1.3) y la lógica de generación del color (1.5) que dependerá de la profundidad de color deseada. A su vez, los periféricos integrados en el microcontrolador son: un generador de reloj (1.21), un temporizador (1.22), un puerto serie SPI (1.23) y pines de entrada y salida de propósito general GPIO (1.24). De manera más específica, el sistema de la figura 1 muestra la pantalla TFT (1.1) con sus señales de interfaz típicas. Las pantallas TFT son dispositivos síncronos, con una entrada de reloj (CLK) por la que se recibe una señal de reloj (PIXCLK) que gobierna su máquina de estados interna. No es por lo tanto necesario seguir una temporización rigurosa durante el refresco de la pantalla, siempre y cuando el cómputo total de pulsos de reloj sea correcto y el tiempo total del refresco no sea demasiado grande y de lugar a parpadeo. Además las pantallas TFT disponen de una entrada de validación de datos (DE) y dos entradas de sincronismo, horizontal (HSYNC) y vertical (VSYNC), si bien en muchos casos estas dos últimas señales son opcionales ya que se generan internamente a partir de la señal DE. Estas entradas DE, HSYNC y VSYNC se controlan desde los pines de entrada y salida de propósito general GPIO (1.24). El resto de entradas de la pantalla TFT (1.1) son las entradas de video de la pantalla correspondientes a los bits con el nivel de cada componente de color (R: rojo, G: verde, B: azul) codificado como un número binario de 8 o de 6 bits. El ancho de bit dependerá del modelo concreto de pantalla TFT (1.1). Dichas entradas RGB se conectarán directamente a las salidas específicas de las propias memorias flash serie (1.3) o bien por interposición de puertas lógicas, multiplexores o demultiplexores, entre otros, que conforman la lógica de generación del color (1.5). Figure 1 is the block diagram of an embodiment of the image generation system on TFT screens in which the main components of said system and the way in which they are connected are shown. These components are: the TFT display (1.1), the general purpose microcontroller (1.2), the integrated peripherals (1.21-1.24) in the microcontroller (1.2), a plurality of serial Flash memories (1.3) with the graphic information (characters ) stored, the clock generation logic (1.4) for the generation of the screen clock signals (1.1) and the memories (1.3) and the color generation logic (1.5) that will depend on the color depth desired. In turn, the peripherals integrated in the microcontroller are: a clock generator (1.21), a timer (1.22), a SPI serial port (1.23) and GPIO general purpose input and output pins (1.24). More specifically, the system in Figure 1 shows the TFT screen (1.1) with Your typical interface signals. TFT displays are synchronous devices, with a clock input (CLK) through which a clock signal (PIXCLK) is received that governs your internal state machine. It is therefore not necessary to follow a rigorous timing during the refresh of the screen, as long as the total count of clock pulses is correct and the total time of the refreshment is not too large and in place of flickering. In addition, the TFT screens have a data validation (DE) input and two synchronization inputs, horizontal (HSYNC) and vertical (VSYNC), although in many cases these last two signals are optional since they are generated internally from the signal of. These DE, HSYNC and VSYNC inputs are controlled from the GPIO general purpose input and output pins (1.24). The remaining inputs of the TFT screen (1.1) are the video inputs of the screen corresponding to the bits with the level of each color component (R: red, G: green, B: blue) encoded as a binary number of 8 or 6 bits. The bit width will depend on the specific TFT display model (1.1). These RGB inputs will be connected directly to the specific outputs of the series flash memories (1.3) or by interposition of logic gates, multiplexers or demultiplexers, among others, that make up the logic of color generation (1.5).
El otro componente básico del sistema es el microcontrolador (1.2), del que sólo se han representado los subsistemas implicados en la generación de las imágenes hacia la pantalla TFT (1.1), pero que dispondría de subsistemas adicionales para la gestión de otros aspectos relacionados con el control de la pantalla TFT como por ejemplo interfaces de comunicación serie (CAN/LIN/RS485/USB,... ) o temporizadores para la generación de señales acústicas, etc. En esta realización particular, el microcontrolador dispone de los siguientes periféricos: The other basic component of the system is the microcontroller (1.2), of which only the subsystems involved in the generation of the images towards the TFT screen (1.1) have been represented, but which would have additional subsystems for the management of other aspects related to TFT screen control such as serial communication interfaces (CAN / LIN / RS485 / USB, ...) or timers for the generation of acoustic signals, etc. In this particular embodiment, the microcontroller has the following peripherals:
• un generador de reloj (1.21) que permita obtener en un pin una señal cuadrada (CLKosc) de una frecuencia compatible con la pantalla, (en el orden de las decenas de megahercios, proporcional con el número total de pixeles de la pantalla). Muchos microcontroladores modernos generan su señal de reloj internamente y pueden dirigirla a un pin si se configuran adecuadamente. Si el microcontrolador no dispusiera de un generador de reloj interno aún se puede generar dicha señal de reloj externamente y aplicarla tanto a la lógica de generación de reloj (1.4) como al propio microcontrolador (1.2).  • a clock generator (1.21) that allows a square signal (CLKosc) of a frequency compatible with the display to be obtained on a pin, (in the order of tens of megahertz, proportional to the total number of pixels on the screen). Many modern microcontrollers generate their clock signal internally and can direct it to a pin if configured properly. If the microcontroller does not have an internal clock generator, said clock signal can still be generated externally and applied to both the clock generation logic (1.4) and the microcontroller (1.2) itself.
• un modulo temporizador (1.22) con al menos una salida activa por comparación o con modo PWM ("Modulación por ancho de pulsos'). Este periférico se usará para generar un pulso correspondiente a un número programable de ciclos de la señal cuadrada del generador de reloj (CLKosc). Se realiza una función de tipo AND lógico, mediante una puerta AND (1.41), entre este pulso y la señal de reloj (CLKosc), obteniendo con ello un tren de un número preciso de pulsos en la entrada de reloj de la pantalla (PIXCLK). Si la señal DE está activa cada uno de estos pulsos introducirá los datos de un pixel en la pantalla, mientras que si DE está inactiva los pulsos se corresponden con los tiempos de retrazado horizontal o vertical de la pantalla. • a timer module (1.22) with at least one active output by comparison or with PWM mode ('Pulse width modulation'). This peripheral will be used to generate a pulse corresponding to a programmable number of cycles of the square signal of the clock generator (CLKosc). A logical AND type function is performed, through an AND gate (1.41), between this pulse and the clock signal (CLKosc), thereby obtaining a train of a precise number of pulses at the clock input of the screen (PIXCLK ). If the DE signal is active each of these pulses will enter the data of a pixel on the screen, while if DE is inactive the pulses correspond to the horizontal or vertical retracement times of the screen.
• una o varias memorias Flash con interfaz serie (1.3). El tipo, número, y capacidad de dichas memorias va a depender de la profundidad de color de las imágenes generadas así como de la cantidad total de objetos gráficos que deben almacenar y de sus respectivos tamaños en pixeles. Para los tipos de aplicaciones previstas se ha considerado unas profundidades de color de 1 , 4 u 8 bits por pixel (aunque se podrían conseguir mayor profundidades de color conectando más memorias SQI en paralelo, por ejemplo con 3 memorias SQI se conseguirían profundidades de 12 bits por pixel):  • one or more Flash memories with serial interface (1.3). The type, number, and capacity of these memories will depend on the color depth of the generated images as well as the total amount of graphic objects that they should store and their respective pixel sizes. For the types of applications envisaged, color depths of 1, 4 or 8 bits per pixel have been considered (although greater color depths could be achieved by connecting more SQI memories in parallel, for example with 3 SQI memories 12-bit depths would be achieved per pixel):
o en el caso de 1 bit/pixel se hace uso de una única memoria de tipo SPI; o en el caso de 4 bits por pixel la memoria ha de ser SQI para poder obtener de forma simultánea los 4 bits con la información de color del pixel; y, o en el caso de 8 bits por pixel se usan dos memorias de tipo SQI conectadas en paralelo.  or in the case of 1 bit / pixel, a single SPI memory is used; or in the case of 4 bits per pixel the memory must be SQI to be able to simultaneously obtain the 4 bits with the pixel color information; and, or in the case of 8 bits per pixel, two SQI type memories connected in parallel are used.
Todas estas memorias tienen la característica de poder presentar un nuevo dato en la salida e incrementar su contador de direcciones de forma automática por cada pulso de reloj que reciben (cada pulso positivo de la señal PIXCLK), necesitando tan solo de un comando inicial proveniente del puerto serie SPI All these memories have the characteristic of being able to present a new data at the output and increase their address counter automatically for each clock pulse they receive (each positive pulse of the PIXCLK signal), needing only an initial command from the SPI serial port
(1.23) que indique la operación de lectura (ciclo activo de la señal MOSI) y la dirección inicial de la memoria a partir de la cual se leerán los datos. Otro aspecto destacado de este tipo de memorias es que sus terminales son siempre los mismos, independientemente de su capacidad, lo que permite elegir el dispositivo que mejor se ajuste a las necesidades de la aplicación sin necesidad de rediseñar la electrónica del sistema. (1.23) indicating the reading operation (active cycle of the MOSI signal) and the initial address of the memory from which the data will be read. Another highlight of this type of memory is that its terminals are always the same, regardless of their capacity, which allows you to choose the device that best suits the needs of the application without redesigning the electronics of the system.
• una lógica de generación de reloj (1.4) que comprende un conmutador (1.42) para seleccionar la señal de reloj de entrada de las memorias Flash (1.3) entre la señal SCK proveniente de puerto serie SPI (1.23) y la señal PIXCLK correspondiente a la señal de reloj de la pantalla TFT previamente generada en la puerta AND (1.41). La señal SCK se seleccionará mientras se envían a la memoria los comandos de lectura a través del puerto serie SPI (1.23), pasando a continuación a seleccionarse la señal PIXCLK para el envío de los caracteres a la pantalla (1.1) a través de las correspondientes salidas de video de las memorias flash (1.3). De este modo, una vez iniciada la lectura de la memora Flash los datos pasan de forma automática a la pantalla sin necesidad de intervención directa desde la CPU del microcontrolador. La señal SCK también deberá seleccionarse cuando se programe el contenido de las memorias flash desde el microcontrolador o cuando se lean datos de la memoria que sean relevantes para el microcontrolador pero no para la generación de imágenes. Un bloque de lógica relacionado con la generación de color (1.5) Este bloque depende de la profundidad de color deseada, pudiendo tener las siguientes implementaciones: • a clock generation logic (1.4) comprising a switch (1.42) for selecting the input clock signal of the Flash memories (1.3) between the SCK signal from the SPI serial port (1.23) and the PIXCLK signal corresponding to the clock signal of the TFT screen previously generated in the AND gate (1.41). The SCK signal will be selected while the read commands are sent to memory via the SPI serial port (1.23), then the PIXCLK signal will be selected to send the characters to the screen (1.1) through the corresponding ones Video outputs of flash memories (1.3). In this way, once the Flash memory has been read, the data automatically passes to the screen without the need for direct intervention from the microcontroller CPU. The SCK signal must also be selected when programming the contents of flash memories from the microcontroller or when reading memory data that is relevant to the microcontroller but not for image generation. A logic block related to the generation of color (1.5) This block depends on the desired color depth, and can have the following implementations:
o Profundidad de color de 1 bit por pixel y color de fondo negro. La figura 2 muestra una implementación particular de este bloque de asignación de color (1.5) para esta profundidad de color. Esta es la implementación más básica del bloque (1.5) y tan solo requiere de 4 puertas AND (2.2), de modo que el pixel tendrá el color seleccionado mediante los 4 pines I, R, G, y B de salida de propósito general GPIO (2.5) cuando desde la salida de video (SO) de la memoria flash SPI (2.1) salga un nivel lógico de 1 , o color negro en caso contrario. Obsérvese que aunque las imágenes almacenadas en la memoria flash son monocromas, su color se puede variar dependiendo de su posición en la pantalla, de modo que podemos visualizar simultáneamente hasta 16 colores distintos. Según la pantalla TFT elegida el conexionado será (2.3) para una TFT con una resolución de 24 bit/pixel o (2.4) para un TFT con una resolución de 18 bit/pixel. Así en una realización particular (se pueden elegir conexionados diferentes que den como resultado paletas de colores distintas) para la generación de imágenes con una profundidad de color de 1 bit por pixel y color de fondo negro, los colores obtenidos pueden ser: o 1 bit color depth per pixel and black background color. Figure 2 shows a particular implementation of this color assignment block (1.5) for this color depth. This is the most basic implementation of the block (1.5) and only requires 4 AND (2.2) doors, so that the pixel will have the color selected by the 4 pins I, R, G, and B general purpose output GPIO (2.5) when a logical level of 1 is output from the video (SO) output of the SPI flash memory (2.1), or black otherwise. Note that although the images stored in flash memory are monochrome, their color can be varied depending on their position on the screen, so that we can simultaneously display up to 16 different colors. Depending on the TFT screen chosen, the connection will be (2.3) for a TFT with a resolution of 24 bit / pixel or (2.4) for a TFT with a resolution of 18 bit / pixel. Thus, in a particular embodiment (different connections can be chosen that result in different color palettes) for the generation of images with a color depth of 1 bit per pixel and black background color, the colors obtained can be:
I RGB CO LOR I RGB CO LOR
0000 Neg ro 0000 Black ro
0001 Azul oscu ro 0010 Ve rde oscu ro 0001 Dark blue 0010 Go rde oscu ro
0011 Cyan oscu ro  0011 Cyan dark
0100 Roj o oscu ro  0100 Red or Dark
0101 Magenta oscu ro  0101 Dark Magenta
0110 Amari l l o oscu ro  0110 Amari l l o oscu ro
0111 Gri s cl aro  0111 Gri s cl aro
1000 Gri s oscu ro  1000 Gri s dark
1001 Azul cl aro  1001 Blue cl hoop
1010 Ve rde cl aro  1010 Ve rde cl aro
1011 Cyan cl aro  1011 Cyan cl aro
1100 Rojo cl aro  1100 Red cl hoop
1101 Magenta cl aro  1101 Magenta cl hoop
1110 Amari l l o cl aro  1110 Amari l l o cl aro
1111 Bl anco o Profundidad de color de 1 bit por pixel y color de fondo seleccionable. La figura 3 muestra una implementación particular de este bloque de asignación de color (1.5) para esta profundidad de color. En este caso se emplea un multiplexor cuádruple (3.2), 4 pines I, R, G, y B de salida de propósito general GPIO (3.3) para la asignación del color de los caracteres de primer plano y otros 4 pines I, R, G, y B de salida de propósito general GPIO (3.4) para la asignación del color de fondo. Según la pantalla TFT elegida el conexionado será (3.5) para una TFT con una resolución de 24 bit/pixel o (3.6) para una TFT con una resolución de 18 bit/pixel.  1111 Wide bl or 1 bit color depth per pixel and selectable background color. Figure 3 shows a particular implementation of this color assignment block (1.5) for this color depth. In this case, a quadruple multiplexer (3.2), 4 pins I, R, G, and B general purpose output GPIO (3.3) are used to assign the color of the foreground characters and another 4 pins I, R, G, and B general purpose output GPIO (3.4) for background color assignment. Depending on the TFT screen chosen, the connection will be (3.5) for a TFT with a resolution of 24 bit / pixel or (3.6) for a TFT with a resolution of 18 bit / pixel.
o Profundidad de color de 4 bits por pixel. La figura 4 muestra una implementación particular de este bloque de asignación de color (1.5) para esta profundidad de color. En este caso los datos de video provienen de una memoria de tipo SQI (4.1) y son de 4 bits, de modo que se pueden conectar directamente a las entradas de video de la pantalla TFT. Según la pantalla TFT elegida el conexionado será (4.2) para un TFT con una resolución de 24 bit/pixel o (4.3) para un TFT con una resolución de 18 bit/pixel. Se requiere una resistencia (4.4) conectada entre la salida MOSI del microcontrolador y la salida SI de la memoria (4.1) ya que al pasar la memoria SQI (4.1) al modo de 4 bits el pin SI deja de ser de entrada para ser de salida, lo que provocaría un conflicto con la salida MOSI del microcontrolador. En esta implementación cada pixel puede tener hasta 16 colores diferentes, o Color depth of 4 bits per pixel. Figure 4 shows a particular implementation of this color assignment block (1.5) for this color depth. In this case, the video data comes from an SQI (4.1) memory and is 4 bits, so that it can be connected directly to the video inputs of the TFT screen. Depending on the TFT screen chosen, the connection will be (4.2) for a TFT with a resolution of 24 bit / pixel or (4.3) for a TFT with a resolution of 18 bit / pixel. A resistor (4.4) connected between the MOSI output of the microcontroller and the SI output of the memory (4.1) is required since when the SQI memory (4.1) is transferred to the 4-bit mode the SI pin is no longer input to be output, which would cause a conflict with the MOSI output of the microcontroller. In this implementation each pixel can have up to 16 different colors,
o Profundidad de color de 8 bits por pixel. La figura 5 muestra una implementación particular de este bloque de asignación de color (1.5) para esta profundidad de color. En este caso se emplean dos memorias Flash SQI (5.1 y 5.2) conectadas en paralelo que proporcionan un total de 8 bits por pixel cuya señal de reloj procede de la lógica de reloj (1.4) descrita anteriormente. La asignación de colores responde a un modo RGB332 (con 3 bits para las componentes roja (R0, R1 , R2) y verde (G0, G1 , G2) y 2 bits para la componente azul (B0, B1)). Cada pixel puede tener 256 colores diferentes. Las resistencias (5.5) conectadas entre la salida MOSI del micro controlador y las entradas SI de las memorias (4.1) son necesarias para mitigar los posibles conflictos lógicos entre los pines de salida SI/D3 de ambas memorias durante la fase de lectura de datos de 4 bits (función D3), así como con el pin MOSI del microcontrolador. De igual modo las resistencias (5.6) entre la entrada MISO y las salidas SO de las memorias (4.1) son necesarias para mitigar los posibles conflictos lógicos entre los pines de salida SO/DO de ambas memorias durante la fase de lectura de datos de 4 bits (función DO). Según la pantalla TFT elegida el conexionado podría ser (5.3) para una TFT con una resolución de 24 bit/pixel o (5.4) para una TFT con una resolución de 18 bit/pixel. La figura 6 muestra un ejemplo de realización de un cronograma con las señales de control que se implementan para la generación de las imágenes en las pantallas TFT. Este ejemplo de realización muestra el cronograma temporal correspondiente al refresco de una única línea (6.1) en una pantalla TFT del tipo "sólo DE, sin HSYNC ni VSYNC". Dicha línea (6.1) comprende el envío de 3 caracteres ("∞" (6.2), "<" (6.3), y un icono representando un hombre (6.4)) de las memorias flash serie donde se almacenan a la pantalla TFT. En primer lugar, la señal DE (6.5) generada por uno de los pines de salida GPIO (1.24) se activa durante la duración de la parte visible de la línea para habilitar la escritura en la pantalla TFT. Simultáneamente el módulo temporizador genera la señal TIMER (6.6) correspondiente la anchura de un número programable de ciclos de la señal de reloj. Así, una vez el conmutador selecciona como entrada de reloj de las memorias flash serie la señal PIXCLK (6.7) se procede al envío de los caracteres (6.2, 6.3, 6.4) de la línea (6.1), enviándose un carácter por cada ciclo alto de la señal CLKSEL (6.8). Cada uno de los ciclos altos de la señal PIXCLK (6.7) comprende una pluralidad de pulsos, de manera que en cada pulso se transmite un pixel de los caracteres (6.2, 6.3, 6.4) de la línea (6.1) que se van a mostrar por pantalla. o 8 bit color depth per pixel. Figure 5 shows a particular implementation of this color assignment block (1.5) for this color depth. In this case, two SQI Flash memories (5.1 and 5.2) are used connected in parallel that provide a total of 8 bits per pixel whose clock signal comes from the clock logic (1.4) described above. The color assignment responds to an RGB332 mode (with 3 bits for the red (R0, R1, R2) and green (G0, G1, G2) and 2 bits for the blue component (B0, B1) components. Each pixel can have 256 different colors. The resistors (5.5) connected between the MOSI output of the microcontroller and the SI inputs of the memories (4.1) are necessary to mitigate the possible logical conflicts between the SI / D3 output pins of both memories during the data reading phase of 4 bits (function D3), as well as with the MOSI pin of the microcontroller. Similarly, the resistances (5.6) between the MISO input and the SO outputs of the memories (4.1) are necessary to mitigate the possible logical conflicts between the SO / DO output pins of both memories during the data reading phase of 4 bits (DO function). Depending on the TFT screen chosen, the connection could be (5.3) for a TFT with a resolution of 24 bit / pixel or (5.4) for a TFT with a resolution of 18 bit / pixel. Figure 6 shows an example of carrying out a schedule with the control signals that are implemented for the generation of the images on the TFT screens. This exemplary embodiment shows the time schedule corresponding to the single line refresh (6.1) on a TFT screen of the "DE only type, without HSYNC or VSYNC". Said line (6.1) includes the sending of 3 characters ("∞" (6.2), "<" (6.3), and an icon representing a man (6.4)) of the serial flash memories where they are stored on the TFT screen. First, the signal DE (6.5) generated by one of the GPIO output pins (1.24) is activated for the duration of the visible part of the line to enable writing on the TFT screen. Simultaneously the timer module generates the corresponding TIMER signal (6.6) the width of a programmable number of cycles of the clock signal. Thus, once the switch selects the PIXCLK signal (6.7) as the clock input of the serial flash memories, the characters (6.2, 6.3, 6.4) of the line (6.1) are sent, sending one character for each high cycle of the CLKSEL signal (6.8). Each of the high cycles of the PIXCLK signal (6.7) comprises a plurality of pulses, so that in each pulse a pixel of the characters (6.2, 6.3, 6.4) of the line (6.1) that are to be transmitted is transmitted show on screen.
El reloj del puerto SPI se emplea para enviar comandos de lectura a la memoria Flash, lo que supone enviar un total de 32 o 40 pulsos de reloj con el byte de comando, 3 bytes de dirección y un posible byte de relleno. PIXCLK (6.7) se utiliza en la posterior fase de lectura de datos, de forma que el contenido de la memoria Flash se transfiere a la pantalla de forma directa, sin la intervención de la CPU del microcontrolador. Por lo tanto, a cada envío de un carácter (6.2, 6.3, 6.4) desde las memorias a la pantalla le precede un tren de pulsos de la señal de reloj SCK (6.9) del puerto serie SPI para el comando de lectura del carácter a enviar, por lo que el conmutador seleccionara una señal entre PIXCLK (6.7) y SCK (SPI) (6.9) de forma alterna para primero enviar el comando de lectura del carácter (RD-cmd) y luego enviar los datos (data) del carácter a la pantalla. De este modo se obtiene la señal de reloj compuesta, CLK (FLASH) (6.10), en la entrada de reloj de las memorias Flash. The SPI port clock is used to send read commands to Flash memory, which means sending a total of 32 or 40 clock pulses with the command byte, 3 address bytes and a possible padding byte. PIXCLK (6.7) is used in the subsequent phase of reading data, so that the contents of the Flash memory are transferred to the screen directly, without the intervention of the microcontroller CPU. Therefore, each send of a character (6.2, 6.3, 6.4) from the memories to the screen is preceded by a pulse train of the SCK clock signal (6.9) of the SPI serial port for the character read command a send, so the switch will select a signal between PIXCLK (6.7) and SCK (SPI) (6.9) alternately to first send the character read command (RD-cmd) and then send the character data (data) to the screen. In this way the composite clock signal, CLK (FLASH) (6.10), is obtained at the clock input of the Flash memories.
Adicionalmente, el sistema envía, entre cada dos líneas, un cierto número de pulsos de reloj (6.13), dependiente del modelo de pantalla, que señalizan el comienzo de una nueva línea. Un número mayor de pulsos con la señal DE en bajo señalizaría el comienzo del cuadro de imagen o retrazado vertical (no representado en la Fig. 6). Additionally, the system sends, between every two lines, a certain number of clock pulses (6.13), depending on the display model, which signal the beginning of a new line. A larger number of pulses with the low DE signal would signal the start of the image frame or vertical retracement (not shown in Fig. 6).
El número total de pulsos de reloj generados en la señal PIXCLK (6.7) se controla mediante la salida del temporizador TIMER (6.6), mientras que CLKSEL (6.8) indica si a la memoria Flash llega la señal de reloj SCK del puerto SPI (6.9) o la señal PIXCLK (6.7). También conviene destacar que las señales PIXCLK (6.7) y SCK (SPI) (6.9) se pueden generar simultáneamente si la señal CLKSEL (6.8) está inactiva, lo que puede resultar de utilidad para reducir los tiempos muertos de PIXCLK y así aumentar la frecuencia de refresco de la pantalla. En particular esta posibilidad se puede aprovechar en los tiempos de retrazado o si en la imagen tenemos huecos grandes (6.14) entre los caracteres (6.2, 6.3, 6.4). The total number of clock pulses generated in the PIXCLK signal (6.7) is controlled by the TIMER timer output (6.6), while CLKSEL (6.8) indicates whether the SCK clock signal of the SPI port (6.9) reaches the Flash memory. ) or the PIXCLK signal (6.7). It should also be noted that the PIXCLK (6.7) and SCK (SPI) (6.9) signals can be generated simultaneously if the CLKSEL (6.8) signal is inactive, which can be useful for reducing PIXCLK downtimes and thus increasing the frequency of screen refresh. In particular, this possibility can be used in the delayed times or if in the image we have large gaps (6.14) between the characters (6.2, 6.3, 6.4).
Las memorias Flash tienen una entrada adicional, /CS (6.11), que debe estar en nivel bajo durante la ejecución de los comandos de lectura del carácter (RD-cmd) los comandos de envío de datos (data) de la señal CLK (6.10) y en la que un flanco de bajada señaliza el primer bit de los citados comandos. En la Fig. 6 se muestra la evolución temporal de dicha señal, que sólo se pone en nivel alto de forma breve antes del envío de un nuevo comando de lectura a las memorias Flash. Flash memories have an additional input, / CS (6.11), which must be at a low level during the execution of the character read commands (RD-cmd) the data send commands (data) of the CLK signal (6.10 ) and in which a falling edge signals the first bit of the said commands. In Fig. 6 the temporal evolution of said signal is shown, which is only set to a high level briefly before of sending a new read command to Flash memories.
La señal VIDEO (6.12) se obtiene en las salidas de las memorias Flash, y en el ejemplo de la Fig. 6 es de un solo bit, lo que generará imágenes monocromas (bloques de generación de color como los mostrados en las Fig. 2 o Fig. 3). La señal de VIDEO (6.12) puede tener un valor arbitrario durante la lectura de los caracteres, acorde con los datos programados en las memorias Flash, si bien en la Fig. 6 se muestra superpuesta la traza correspondiente a la línea de vídeo (6.1) particular de este ejemplo. The VIDEO signal (6.12) is obtained at the outputs of the Flash memories, and in the example of Fig. 6 it is a single bit, which will generate monochrome images (blocks of color generation as shown in Fig. 2 or Fig. 3). The VIDEO signal (6.12) can have an arbitrary value during the reading of the characters, according to the data programmed in the flash memories, although in Fig. 6 the trace corresponding to the video line is shown superimposed (6.1) Particular of this example.

Claims

REIVINDICACIONES
1. Sistema de generación de imágenes en pantallas TFT, caracterizado porque comprende una pantalla TFT, al menos una memoria flash con interfaz serie donde se almacenan unos caracteres a ser mostrados en la pantalla TFT y un microcontrolador, donde el microcontrolador comprende: 1. Image generation system on TFT screens, characterized in that it comprises a TFT screen, at least one flash memory with serial interface where characters are stored to be displayed on the TFT screen and a microcontroller, where the microcontroller comprises:
- un módulo temporizador configurado para generar una señal proporcional a un número programable de ciclos de una señal de reloj;  - a timer module configured to generate a signal proportional to a programmable number of cycles of a clock signal;
-un puerto de interfaz de periféricos serie configurado para gestionar la al menos una memoria flash;  -a serial peripheral interface port configured to manage the at least one flash memory;
- unos pines de entrada/salida de propósito general configurados para habilitar una escritura en la pantalla TFT;  - general purpose input / output pins configured to enable writing on the TFT screen;
donde el sistema adicionalmente comprende unos medios de generación de una señal de entrada de reloj de la pantalla TFT a partir de la señal generada por el módulo temporizador y de la señal de reloj y un conmutador que selecciona una señal de reloj de la al menos una memoria flash entre la señal de entrada del reloj de la pantalla TFT y una señal de reloj del puerto de interfaz de periféricos serie, de manera que los caracteres en la al menos una memoria flash se transmiten directamente a la pantalla TFT.  where the system additionally comprises means for generating a clock input signal of the TFT screen from the signal generated by the timer module and the clock signal and a switch that selects a clock signal of the at least one flash memory between the clock input signal of the TFT screen and a clock signal of the serial peripheral interface port, so that the characters in the at least one flash memory are transmitted directly to the TFT screen.
2. Sistema de generación de imágenes en pantallas TFT, según la reivindicación 1 , que comprende un reloj interno para la generación de la señal de reloj. 2. Image generation system on TFT screens, according to claim 1, comprising an internal clock for the generation of the clock signal.
3. - Sistema de generación de imágenes en pantallas TFT, según la reivindicación 1 , donde el módulo temporizador comprende una salida activa seleccionada entre una salida por comparación y una salida con modulación por ancho de pulsos. 3. - Image generation system on TFT screens, according to claim 1, wherein the timer module comprises an active output selected from an output by comparison and an output with pulse width modulation.
4. - Sistema de generación de imágenes en pantallas TFT, según la reivindicación 1 , donde la al menos una memoria flash con interfaz serie es una memoria de interfaz periférica en serie. 4. - Image generation system on TFT screens, according to claim 1, wherein the at least one flash memory with serial interface is a serial peripheral interface memory.
5. - Sistema de generación de imágenes en pantallas TFT, según la reivindicación 1 , donde la al menos una memoria flash con interfaz serie es una memoria de entrada/salida serial cuádruple. 5. - Image generation system on TFT screens, according to claim 1, wherein the at least one flash memory with serial interface is a quad-serial serial input / output memory.
6.- Sistema de generación de imágenes en pantallas TFT, según la reivindicación 1 , donde la al menos una memoria flash con interfaz serie son dos memorias de entrada/salida serial cuádruple conectadas en paralelo. 6. Image generation system on TFT screens, according to claim 1, wherein the at least one flash memory with serial interface are two quad serial serial input / output memories connected in parallel.
7.- Sistema de generación de imágenes en pantallas TFT, según una cualquiera de las reivindicaciones anteriores, que comprende un módulo de asignación de color conectado a la al menos una memoria flash para asignar colores a los caracteres mostrados en la pantalla TFT. 7. Image generation system on TFT screens, according to any one of the preceding claims, comprising a color allocation module connected to the at least one flash memory to assign colors to the characters shown on the TFT screen.
8.- Sistema de generación de imágenes en pantallas TFT, según las reivindicaciones 4 y 7, donde el módulo de asignación de color comprende 4 puertas AND, cada puerta AND teniendo una primera entrada común conectada a una salida de vídeo de la memoria de interfaz periférica en serie y una segunda entrada, donde la segunda entrada de cada puerta AND está conectada, respectivamente, a uno de los pines de entrada/salida de propósito general, de forma que el módulo de asignación de color está configurado para generar caracteres monocromos con fondo negro. 8. Image generation system on TFT screens, according to claims 4 and 7, wherein the color assignment module comprises 4 AND doors, each AND gate having a first common input connected to a video output of the interface memory serial peripheral and a second input, where the second input of each AND gate is connected, respectively, to one of the general purpose input / output pins, so that the color assignment module is configured to generate monochrome characters with black background.
9. - Sistema de generación de imágenes en pantallas TFT, según las reivindicaciones 4 y 7, donde el módulo de asignación de color comprende un multiplexor cuádruple con una entrada conectada a una salida de video de la memoria de interfaz periférica en serie, 4 primeras entradas conectadas respectivamente a 4 pines de entrada/salida de propósito general para asignar un color a cada carácter y 4 segundas entradas conectadas respectivamente a 4 pines de entrada/salida de propósito general para asignar un color a un fondo, de forma que el módulo de asignación de color está configurado para generar caracteres monocromos con fondo monocromo. 9. - Image generation system on TFT screens, according to claims 4 and 7, wherein the color allocation module comprises a quadruplex multiplexer with an input connected to a video output of the serial peripheral interface memory, first 4 inputs connected respectively to 4 general purpose input / output pins to assign a color to each character and 4 second inputs respectively connected to 4 general purpose input / output pins to assign a color to a background, so that the module Color mapping is set to generate monochrome characters with monochrome background.
10. - Sistema de generación de imágenes en pantallas TFT, según la reivindicación 5, donde la una memoria de entrada/salida serial cuádruple tiene 4 salidas de imagen conectadas directamente a unas entradas de imagen de la pantalla TFT, estando el sistema configurado para generar caracteres con profundidades de color de 4 bits por pixel. 10. - Image generation system on TFT screens, according to claim 5, wherein the quad serial input / output memory has 4 image outputs directly connected to image inputs of the TFT screen, the system being configured to generate characters with color depths of 4 bits per pixel.
1 1. - Sistema de generación de imágenes en pantallas TFT, según la reivindicación 6, donde cada una memoria de entrada/salida serial cuádruple tiene 4 salidas de imagen conectadas directamente a unas entradas de imagen de la pantalla TFT, estando el sistema configurado en un modo RGB 332 para generar caracteres con profundidades de color de 8 bits por pixel. 1 1. Image generation system on TFT screens, according to claim 6, wherein each quadruple serial input / output memory has 4 image outputs directly connected to image inputs of the TFT screen, the system configured in an RGB 332 mode to generate characters with color depths of 8 bits per pixel.
12. - Procedimiento de generación de imágenes en pantallas TFT que hace uso del sistema descrito en una cualquiera de las reivindicaciones anteriores, caracterizado porque comprende las etapas de: 12. - Procedure for generating images on TFT screens using the system described in any one of the preceding claims, characterized in that it comprises the steps of:
- generar en el módulo temporizador una señal proporcional a un número programable de ciclos de la señal reloj;  - generate in the timer module a signal proportional to a programmable number of cycles of the clock signal;
- activar un modo escritura de la pantalla TFT mediante uno de los pines de entrada salida de propósito general del microcontrolador durante una duración de una parte visible de una línea de caracteres;  - activate a write mode of the TFT screen by means of one of the general purpose output input pins of the microcontroller for a duration of a visible part of a character line;
- generar una señal de entrada de reloj de la pantalla TFT a partir de la señal generada por el módulo temporizador y de la señal de reloj;  - generate a clock input signal from the TFT screen from the signal generated by the timer module and the clock signal;
-seleccionar mediante un conmutador una señal entre la señal de entrada del reloj de la pantalla TFT y una señal de reloj del puerto de interfaz de periféricos serie, donde la señal seleccionada es la señal de entrada de reloj de la al menos una memoria flash; y,  - select by means of a switch a signal between the clock input signal of the TFT screen and a clock signal of the serial peripheral interface port, where the selected signal is the clock input signal of the at least one flash memory; Y,
- enviar desde la al menos una memoria flash un carácter de la línea de caracteres directamente a la pantalla TFT cuando el conmutador seleccione la señal de entrada de reloj de la pantalla TFT y la señal de entrada de reloj de la pantalla TFT esté activa.  - send from the at least one flash memory a character from the character line directly to the TFT screen when the switch selects the clock input signal from the TFT screen and the clock input signal from the TFT screen is active.
13. - Procedimiento de generación de imágenes en pantallas TFT, según la reivindicación 12, donde comprende asignar color a los caracteres mostrados en la pantalla TFT. 13. - Procedure for generating images on TFT screens, according to claim 12, wherein it comprises assigning color to the characters shown on the TFT screen.
14. - Procedimiento de generación de imágenes en pantallas TFT, según la reivindicación 12, que comprende enviar un número de pulsos de reloj entre dos ciclos activos de la señal de entrada de reloj de la pantalla TFT para marcar un comienzo de una nueva línea de caracteres. 14. - Procedure for generating images on TFT screens, according to claim 12, comprising sending a number of clock pulses between two active cycles of the TFT screen clock input signal to mark a start of a new line of characters.
15. - Procedimiento de generación de imágenes en pantallas TFT, según la reivindicación 12, que cuando el conmutador selecciona la señal de reloj del puerto de interfaz de periféricos serie, el procedimiento comprende enviar comandos de lectura a la al menos una memoria flash. 15. - Procedure for generating images on TFT screens, according to claim 12, that when the switch selects the clock signal from the serial peripheral interface port, the method comprises sending read commands to at least one flash memory.
PCT/ES2016/070511 2015-08-21 2016-07-07 System and method for generating images on tft screens WO2017032911A1 (en)

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