WO2017028557A1 - 一种基带芯片及信号处理方法 - Google Patents

一种基带芯片及信号处理方法 Download PDF

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Publication number
WO2017028557A1
WO2017028557A1 PCT/CN2016/080978 CN2016080978W WO2017028557A1 WO 2017028557 A1 WO2017028557 A1 WO 2017028557A1 CN 2016080978 W CN2016080978 W CN 2016080978W WO 2017028557 A1 WO2017028557 A1 WO 2017028557A1
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task
subtask
soft core
core array
hardware
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PCT/CN2016/080978
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English (en)
French (fr)
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成竹
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深圳市中兴微电子技术有限公司
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines

Definitions

  • the present invention relates to wireless access technologies in the field of wireless communications, and in particular, to a baseband chip and a signal processing method.
  • the wireless access technology based on code division multiple access technology has been widely used in the field of wireless communication and is an important part of the existing wireless access technology.
  • wireless data traffic is growing exponentially, and the demand for wireless access is increasing.
  • how to quickly expand, and how to efficiently customize personalized access devices according to user needs especially in the end to achieve better user experience, while reducing the cost, risk, and cycle of development.
  • the baseband processing part of the wireless access equipment of code division multiple access technology is also a crucial part of it, especially the chip processing part, because of its real-time performance, overall computing performance and high design difficulty, it often restricts the performance of the whole device. And an important part of the function.
  • the chip processing part of the wireless access device of the existing code division multiple access technology mainly has the following implementation modes:
  • FPGA Field-Programmable Gate Array
  • the baseband function is realized by a field-programmable FPGA.
  • the advantage is that the design can be completed quickly and upgraded easily.
  • the disadvantage is that the cost is high, the FPGA is also controlled by several giants, and the design area of the self-planning space is limited.
  • ASIC Application Specific Integrated Circuit
  • CPU Central Processing Unit
  • Chip processing with CPU array + ASIC essentially takes up the upper-level advanced CPU array (such as Advanced ARM RISC Machines) resources to complete part of the chip processing.
  • the advantage is that the CPU array of the existing system on chip (SOC) platform turns some ASIC functions into software processing, which reduces the difficulty and risk, and also facilitates the update and upgrade.
  • SOC system on chip
  • This part of the function replaced by software is often Repeated scheduling or query will consume a lot of resources of the CPU array, and the power consumption is large and the cost performance is low.
  • embodiments of the present invention are expected to provide a baseband chip and a signal processing method.
  • An embodiment of the present invention provides a baseband chip, including: a CPU array, a soft core array, and a hardware basic unit; the CPU array, the soft core array, and the hardware basic unit are connected by a bus;
  • the CPU array is configured to send a first task to the soft core array, where the first task is a chip processing task;
  • the soft core array is configured to send the first task to the hardware basic unit
  • the hardware basic unit is configured to perform the first task.
  • the soft core array is further configured to, before transmitting the first task to the hardware basic unit, configure the first task as at least one subtask to form the at least one sub The task list for the task.
  • the baseband chip further includes: direct memory access (DMA, Direct Memory access) and the memory;
  • DMA direct memory access
  • the DMA is connected to the hardware base unit, the DMA is connected to the soft core array through the bus, and the memory is respectively connected to the soft core array and the hardware through the bus Basic unit connection;
  • the soft core array is configured to send a move command corresponding to the at least one subtask to the DMA according to the task list, where the move command is used to instruct the DMA to send the at least one subtask Each subtask to the hardware base unit, and indicating that the DMA feedback is interrupted to the soft core array after the hardware base unit processes the each subtask;
  • the DMA is configured to send the each subtask to the hardware basic unit
  • the hardware basic unit is configured to separately execute each of the subtasks, and store the task result of each subtask in a memory
  • the DMA is further configured to detect a processing status of the sub-task by the hardware basic unit, and send the interrupt to the soft core array when the processing status is complete;
  • the soft core array is further configured to: in response to the interrupt, acquire a task result of the one subtask from the memory, perform an auxiliary function processing on the task result of the one subtask, and process the auxiliary function result Stored to the memory;
  • the DMA is further configured to report the result of the auxiliary function processing in the memory for symbol level or bit level processing.
  • the soft core array is further configured to detect a buffer state of the hardware basic unit before transmitting a move command corresponding to the at least one subtask to the DMA;
  • the soft core array is further configured to send a move command corresponding to the at least one subtask to the DMA when detecting that the cache state of the hardware base unit is idle.
  • the soft core array includes a random access memory (RAM) and a first input first output (FIFO). a memory; the at least one subtask includes the at least one subtask request and the at least one subtask parameter;
  • the FIFO memory is configured to store the at least one subtask request
  • the RAM is configured to store the at least one subtask parameter.
  • the embodiment of the invention provides a signal processing method, including:
  • the soft core array receives a first task sent by the central processor CPU array, and the first task is a chip processing task;
  • the soft core array sends the first task to a hardware basic unit
  • the hardware base unit performs the first task.
  • the method before the soft core array sends the first task to the hardware basic unit, the method further includes:
  • the soft core array configures the first task as at least one subtask to form a task list including the at least one subtask;
  • the soft core array sends the first task to the hardware basic unit, including:
  • the hardware basic unit performs the first task, including:
  • the hardware base unit executes each of the subtasks separately and stores the task results of each of the subtasks in a memory.
  • the method further includes:
  • the DMA detects a processing state of the hardware basic unit for a subtask, and the When the processing status is complete, the soft core array receives the interrupt sent by the DMA;
  • the soft core array acquires a task result of the one subtask from the memory, and performs an auxiliary function processing on the task result of the one subtask, and stores the auxiliary function processing result to the And a memory for the DMA to report the result of the auxiliary function processing in the memory for symbol level or bit level processing.
  • the soft core array sends a move command corresponding to the at least one subtask to the DMA according to the task list, and the method further includes:
  • the soft core array detects a cache state of the hardware base unit.
  • the soft core array sends a move command corresponding to the at least one subtask to the DMA according to the task list, including:
  • Embodiments of the present invention provide a baseband chip and a signal processing method.
  • the baseband chip includes: a CPU array, a soft core array, and a hardware basic unit.
  • the CPU array, the soft core array, and the hardware basic unit are connected by a bus; the CPU array is soft.
  • the core array sends a first task, the first task is a chip processing task; the soft core array sends the first task to the hardware basic unit; the hardware basic unit performs the first task.
  • the above technology implementation scheme is adopted, that is, the baseband chip adopts the architecture of the CPU array + soft core array + hardware basic unit to realize chip processing, since only the chip core algorithm is implemented in one hardware basic unit, and the hardware is basically scheduled by the soft core array.
  • the unit realizes the chip processing task, so that the design of the baseband chip is difficult, and the design area and power consumption of the baseband chip are greatly reduced, and the development cycle of the baseband chip is reduced.
  • FIG. 1 is a schematic structural view of an exemplary baseband chip in the prior art
  • FIG. 2 is a schematic structural diagram 1 of a baseband chip according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram 1 of a hardware basic unit according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram 2 of a hardware basic unit according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram 2 of a baseband chip according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram 3 of a baseband chip according to an embodiment of the present invention.
  • FIG. 7 is a flowchart 1 of a signal processing method according to an embodiment of the present invention.
  • FIG. 8 is a second flowchart of a signal processing method according to an embodiment of the present invention.
  • FIG. 9 is a third flowchart of a signal processing method according to an embodiment of the present invention.
  • FIG. 1 The structure of the existing CPU array + ASIC chip processing is shown in FIG. 1 , and the CPU array performs data interaction with the ASIC through a bus (BUS).
  • BUS bus
  • the ASIC can realize five major functions, wherein n1-n5 respectively represent the number of As that need to be used by five functional modules; C1-C5 respectively represent the auxiliary functions of five functional modules except A, and A is the core algorithm part of the chip. .
  • the CPU array, the soft core array, and the hardware basic unit are connected by a bus; the CPU array sends a first task to the soft core array, the first task is a chip processing task; The core array sends the first task to the hardware base unit; the hardware base unit performs the first task.
  • an embodiment of the present invention provides a baseband chip 1 including a CPU array 10, a soft core array 11 and a hardware basic unit 12, the CPU array 10, the soft core array 11 and The hardware base unit 12 is connected by a bus 13.
  • the CPU array 10 is configured to send a first task to the soft core array 11, and the first task is a chip processing task.
  • the soft core array 11 is configured to send the first task to the hardware base unit 12.
  • the hardware base unit 12 is configured to perform the first task.
  • the background of the application of the embodiment of the present invention is that the chip processing part of the baseband processing part of the wireless access device of the code division multiple access technology mainly uses the baseband chip for chip processing, and the embodiment of the present invention
  • the provided baseband chip 1 adopts the architecture of the CPU array + soft core array + hardware basic unit to realize chip processing.
  • the hardware basic unit 12 may include: sub-modules such as antenna interpolation 120, antenna descrambling 121, antenna despreading 122, and frequency offset compensation 123; or, as shown in FIG.
  • the hardware base unit 12 may include sub-modules such as a symbol map 124, a scrambling 125, an add/drop 126, and a multiplying power 127.
  • the hardware portion of the baseband chip 1 that supports the core algorithm of the chip level is used as the hardware basic unit 12.
  • the structure of the hardware base unit 12 shown in FIG. 3 supports core chip processing at the upstream chip level
  • the structure of the hardware base unit 12 shown in FIG. 4 supports core algorithm processing at the downstream chip level. Therefore, the baseband chip 1 provided by the embodiment of the present invention can determine the structure of the hardware basic unit 12 according to the type of the actual processing signal.
  • the hardware basic unit in the embodiment of the present invention is formed by combining and integrating the chip core algorithm part in the hardware architecture in the prior art, that is, the hardware basic unit is used as a hardware resource pool.
  • n1-n5 respectively indicate that five functional modules need to use the set number of A, and C1-C5 respectively represent five functional modules except the auxiliary functions except A.
  • A is a chip core algorithm.
  • A is used as a hardware basic unit, and a soft core array calling method is used to implement scheduling of different numbers of A, complete chip core algorithm, and then complete C1 in the soft core array. - The processing of the auxiliary functions of the C5 is sufficient.
  • the soft core array 11 in the embodiment of the present invention is a firmware soft core array composed of a simple processor, and specifically may be a simple CPU array such as an arm M series processor. It can support common buses such as AXI (Advanced eXtensible Interface) or Advanced Peripheral Bus (APB) to communicate with upper CPU arrays and lower hardware basic units.
  • AXI Advanced eXtensible Interface
  • API Advanced Peripheral Bus
  • the first task in the embodiment of the present invention refers to a task of performing chip processing on a baseband signal (antenna signal), where the first task includes a first task request and a first task parameter (ie, characterizing a baseband signal) What to do with the chip processing of the function).
  • the hardware base unit 12 performs processing of a core algorithm at the chip level.
  • the soft core array 11 is further configured to: after the CPU array 10 sends the first task, before sending the first task to the hardware basic unit 12, configuring the first task to be at least A subtask forming a task list including the at least one subtask.
  • the baseband signal that needs to be processed in the embodiment of the present invention may be at least one antenna signal. Therefore, the CPU array 10 transmits a chip processing task of at least one antenna signal; the soft core array 11 The chip processing task of each type of function of each segment of the antenna signal is divided into a subtask, and the soft core array 11 completes at least one subtask corresponding to the at least one antenna signal by scheduling the hardware base unit 12.
  • the soft core array 11 includes a RAM 110 and a FIFO memory 111; the at least one subtask includes the at least one subtask request and the at least one subtask parameter.
  • the FIFO memory 111 is configured to store the at least one subtask request.
  • the RAM 110 is configured to store the at least one subtask parameter.
  • the plurality of cores of the soft core array 11 do not communicate, and data interaction is realized by the shared RAM or by the FIFO.
  • the CPU array 10 configures a basic task (first task) to the soft core array 11.
  • the soft core array 11 allocates the divided at least one subtask request to the respective FIFO memory 111 of the soft core in the soft core array 11, and configures at least one subtask parameter into the RAM 110 shared by each soft core.
  • the soft core array 11 reads at least one subtask request in the FIFO memory 111, and then establishes a task list, which is a task list including at least one subtask.
  • the task list includes a subtask identifier of each of the at least one subtask.
  • the form and manner of the specific sub-task identification are not limited in the embodiment of the present invention.
  • the baseband chip 1 may further include: a DMA 14 and a memory 15; the DMA 14 is connected to the hardware base unit 12, and the DMA 14 passes through the bus 13 and the The soft core array 11 is connected, and the memory 15 is connected to the soft core array 11 and the DMA 14 via the bus 13 respectively.
  • the soft core array 11 is configured to send a move command corresponding to the at least one subtask to the DMA 14 according to the task list, where the move command is used to instruct the DMA 14 to send the at least one Each of the subtasks to the hardware base unit 12, and indicating that the DMA 14 feedback interrupts to the soft core array 11 after the hardware base unit 12 has processed the each subtask.
  • the DMA 14 is configured to send each of the subtasks to the hardware base unit 12.
  • the hardware base unit 12 is specifically configured to execute each of the subtasks separately and store the task results of each of the subtasks in the memory 15.
  • the hardware base unit 12 stores the task results of each of the subtasks into the memory 15 through the DMA 14.
  • the hardware base unit 12 transmits the task result of each subtask to the DMA 14; the DMA 14 stores the received task result of each subtask into the memory 15.
  • the DMA 14 is further configured to detect a processing status of the subtask by the hardware base unit 12, and send the interrupt to the soft core array 11 when the processing status is complete.
  • the soft core array 11 is further configured to: in response to the interruption, acquire a task result of the one subtask from the memory 15, perform an auxiliary function processing on the task result of the one subtask, and perform an auxiliary function
  • the processing result is stored to the memory 15.
  • the DMA 14 is further configured to process the auxiliary function in the memory 15 Reported for symbol level or bit level processing.
  • the function of the DMA 14 is scheduled by the soft core array 11 to directly interact with the hardware basic unit 12, that is, to transfer the task parameters to be sent by the soft core array 11 and the data and parameters to be reported by the hardware basic unit 12. .
  • the DMA 14 detects that the processing status of the hardware basic unit 12 for one subtask can be implemented by: the DMA 14 determines the processing status by detecting the value of the processing flag bit in the hardware basic unit 12, for example, the DMA 14 detects the hardware basic.
  • the processing of the null signal in unit 12, when the processing null signal is 1, represents that a subtask is not completed; when the processing null signal is 0, it represents that a subtask is completed.
  • the soft core array 11 is further configured to: after the CPU array 10 sends the first task, send the moving command corresponding to the at least one subtask to the DMA 14 to detect the hardware basic unit. 12 cache status.
  • the soft core array 11 is further configured to send a move command corresponding to the at least one subtask to the DMA 14 when detecting that the cache state of the hardware base unit 12 is idle.
  • the hardware basic unit 12 in the embodiment of the present invention is used as a hardware resource pool.
  • the soft core array 11 issues a subtask to the hardware basic unit 12. .
  • the soft core array 11 divides the first task into 10 subtasks, and the soft core array 11 detects that the cache state of the hardware base unit 12 is idle, and can support the implementation of two subtasks. Therefore, the soft core array 11 passes the DMA.
  • the sub-task is sent to the hardware basic unit 12 for processing first, and when the cache of the hardware basic unit 12 is idle again, other sub-tasks are issued.
  • the soft core array 11 detects that the cache state of the hardware base unit 12 is implemented. For example, the soft core array 11 determines the buffer status by detecting the value of the cache flag bit of the hardware base unit 12. For example, the soft core array detects the non-full signal of the hardware base unit 12, and when the non-full signal is 1, the hardware basic unit is characterized. The buffer of 12 is full; when the non-full signal is 0, the cache characterizing the hardware base unit 12 is not full.
  • the implementation of the buffer state of the hardware core unit 12 by the soft core array 11 can be implemented in various manners in the prior art, which is not limited in the embodiment of the present invention.
  • the embodiment of the present invention designs a CPU array + soft core array (simple processor array) + hardware basic unit (The baseband chip of the hard core architecture replaces the original baseband chip based on pure hard core, pure soft core, or CPU array + hard core architecture. Therefore, the power consumption and area of the chip are greatly reduced, and the chip design difficulty and development cycle are greatly increased. reduce. Since the soft core array 11 can perform the subtask task to the hardware basic unit 12 in parallel, the success rate of the streaming chip is greatly improved, and the user can be provided with a fast customized development project to provide rapid upgrade and expansion.
  • the order in which the sub-tasks are issued by the soft-core array 11 is performed according to the task list.
  • the soft-core array 11 determines that the sub-tasks are to be issued, the sub-tasks to be delivered will be delivered in the order of the task list.
  • the identification and moving command is sent to the DMA 14, and the DMA 14 can read the subtask parameters corresponding to the subtask identifier from the RAM according to the moving command, and package and send the subtask request and subtask parameters corresponding to the subtask to the hardware basic. Unit 12 for chip processing.
  • the process of issuing the subtask by the soft core array 11 may be sent periodically. Therefore, when the soft core array 11 detects that the buffer status of the hardware basic unit 12 is idle and reaches the delivery period, the soft core array 11 The transfer command is issued to the DMA 14.
  • the first task sent by the CPU array 10 to the soft core array 11 may be a fixed task package. At this time, the soft core array 11 ends the task by processing the tasks in the task package. If the first task sent by the CPU array 10 is a non-stop task, then the soft core array 11 will continue to perform the tasks of the CPU array 10. But the soft core array 11 is executed The method of the task is the above process.
  • the baseband chip provided by the embodiment of the present invention includes: a CPU array, a soft core array, and a hardware basic unit, wherein the CPU array, the soft core array, and the hardware basic unit connect the CPU array to send a first task to the soft core array through a bus.
  • the first task is a chip processing task; the soft core array sends a first task to a hardware basic unit; and the hardware basic unit performs a first task.
  • the above technology implementation scheme is adopted, that is, the baseband chip adopts the architecture of the CPU array + soft core array + hardware basic unit to realize chip processing, since only the chip core algorithm is implemented in one hardware basic unit, and the hardware is basically scheduled by the soft core array.
  • the unit realizes the chip processing task, so that the design of the baseband chip is difficult, and the design area and power consumption of the baseband chip are greatly reduced, and the development cycle of the baseband chip is reduced.
  • the embodiment of the invention provides a signal processing method. As shown in FIG. 7, the method includes the following steps:
  • the soft core array receives a first task sent by the CPU array, where the first task is a chip processing task.
  • the background of the application of the embodiment of the present invention is that the chip processing part of the baseband processing part of the wireless access device of the code division multiple access technology mainly uses the baseband chip for chip processing, and the embodiment of the present invention
  • the provided baseband chip adopts the architecture of CPU array + soft core array + hardware basic unit to realize chip processing.
  • the soft core array in the embodiment of the present invention is a firmware soft core array composed of a simple processor, and specifically may be a simple CPU array such as an arm M series processor, and can support a common bus such as AXI and APB, so that Communicates with the upper CPU array and the lower hardware base unit.
  • the first task in the embodiment of the present invention refers to a task of performing chip processing on a baseband signal (antenna signal), where the first task includes a first task request and a first task parameter (ie, a baseband signal is required). What is the function of the chip processing).
  • the soft core array receives the first task sent by the CPU array, and the first task is a task of performing chip processing on the baseband signal.
  • the soft core array sends the first task to a hardware basic unit, where the hardware basic unit performs the first task.
  • the soft core array After the soft core array receives the first task sent by the CPU array, the soft core array sends a first task to the hardware basic unit, so that the hardware basic unit performs the first task, and performs code The processing of the chip-level core algorithm.
  • the hardware basic unit 12 may include: sub-modules such as antenna interpolation 120, antenna descrambling 121, antenna despreading 122, and frequency offset compensation 123; or, as shown in FIG.
  • the hardware base unit 12 may include sub-modules such as a symbol map 124, a scrambling 125, an add/drop 126, and a multiplying power 127.
  • the hardware part of the baseband chip that supports the core algorithm of the chip level is used as the hardware basic unit.
  • the structure of the hardware base unit 12 shown in FIG. 3 supports core chip processing at the upstream chip level
  • the structure of the hardware base unit 12 shown in FIG. 4 supports core algorithm processing at the downstream chip level. Therefore, the baseband chip provided by the embodiment of the present invention can determine the structure of using the hardware basic unit according to the type of the actual processing signal.
  • the hardware basic unit in the embodiment of the present invention is formed by combining and integrating the chip core algorithm part in the hardware architecture in the prior art, that is, the hardware basic unit is used as a hardware resource pool.
  • n1-n5 respectively indicate that five functional modules need to use the set number of A, and C1-C5 respectively represent five functional modules except the auxiliary functions except A.
  • A is a chip core algorithm.
  • A is used as a hardware basic unit, and a soft core array calling method is used to implement scheduling of different numbers of A, complete chip core algorithm, and then complete C1 in the soft core array. - The processing of the auxiliary functions of the C5 is sufficient.
  • a soft core array receiving CPU array is sent The first task is sent, the first task is a chip processing task; the soft core array sends the first task to the hardware basic unit, so that the hardware basic unit performs the first task.
  • the baseband chip adopts the architecture of the CPU array + soft core array + hardware basic unit to realize chip processing, since only the chip core algorithm is implemented in one hardware basic unit, and the hardware basic unit is scheduled through the soft core array.
  • the design of the baseband chip is difficult, and the design area and power consumption of the baseband chip are greatly reduced, and the development cycle of the baseband chip is reduced.
  • a signal processing method provided by an embodiment of the present invention is as shown in FIG. 8.
  • the method includes the following steps:
  • the soft core array receives a first task sent by the CPU array, where the first task is a chip processing task.
  • the background of the application of the embodiment of the present invention is that the chip processing part of the baseband processing part of the wireless access device of the code division multiple access technology mainly uses the baseband chip for chip processing, and the embodiment of the present invention
  • the provided baseband chip adopts the architecture of CPU array + soft core array + hardware basic unit to realize chip processing.
  • the soft core array in the embodiment of the present invention is a firmware soft core array composed of a simple processor, and specifically may be a simple CPU array such as an arm M series processor, and can support a common bus such as AXI and APB, so that Communicates with the upper CPU array and the lower hardware base unit.
  • the first task in the embodiment of the present invention refers to a task of performing chip processing on a baseband signal (antenna signal), where the first task includes a first task request and a first task parameter (ie, a baseband signal is required). What is the function of the chip processing).
  • the soft core array receives the first task sent by the CPU array, and the first task is a task of performing chip processing on the baseband signal.
  • the first task that the CPU array sends to the soft core array may be a fixed one.
  • the soft core array ends the task as long as the tasks in the task package are processed. If the first task sent by the CPU array is a non-stop task, then the soft core array will always perform the task of configuring the CPU array.
  • the method for performing the task by the soft core array is the process of signal processing provided by the embodiment of the present invention.
  • the soft core array configures the first task as at least one subtask to form a task list including the at least one subtask.
  • the soft core array After the soft core array receives the first task sent by the CPU array, the soft core array configures the first task as at least one subtask and forms a task list including the at least one subtask.
  • the CPU array configures a basic task (first task) to the soft core array.
  • the soft core array allocates at least one subtask request into the FIFO memory of the soft core in the soft core array, and configures at least one subtask parameter into the RAM shared by each soft core.
  • the baseband signal that needs to be processed in the embodiment of the present invention may be at least one antenna signal. Therefore, the CPU array transmits a chip processing task of at least one antenna signal; in the soft core array, The soft core array divides the chip processing task of each type of function of each segment of the antenna signal into a subtask, and the soft core array completes at least one subtask corresponding to the at least one antenna signal by scheduling the hardware basic unit.
  • the soft core array reads at least one subtask request in the FIFO memory, and then establishes a task list, which is a task list including at least one subtask.
  • the task list includes a subtask identifier of each of the at least one subtask.
  • the form and manner of the specific sub-task identification are not limited in the embodiment of the present invention.
  • the soft core array sends a move command corresponding to the at least one subtask to the DMA according to the task list, where the DMA sends each subtask to the hardware basic unit, and the hardware basic unit respectively executes each sub a task, and storing a task result of each subtask in a memory, the moving command being used to instruct the DMA to send each of the at least one subtask Subtasks to the hardware base unit, and indicating that the DMA feedback is interrupted after the hardware base unit processes each subtask.
  • the soft core array configures the first task as at least one subtask
  • the soft core array after forming a task list including the at least one subtask, the soft core array sends a move command corresponding to the at least one subtask according to the task list. To DMA.
  • the soft core array sends a move command corresponding to the identifier of the at least one subtask to the DMA according to the task list.
  • the DMA sends each subtask to the hardware basic unit; the hardware basic unit executes each subtask separately to perform the processing of the core algorithm at the chip level, and stores the task result of each subtask in the memory (hardware basic The unit stores the task result of each subtask into the memory through DMA.
  • the hardware basic unit sends the task result of each subtask to the DMA; the DMA receives the task result of each subtask received into the memory)
  • the DMA detects the processing status of the hardware basic unit for a subtask, and when the processing status is complete, sends an interrupt to the soft core array.
  • the hardware basic unit 12 may include: sub-modules such as antenna interpolation 120, antenna descrambling 121, antenna despreading 122, and frequency offset compensation 123; or, as shown in FIG.
  • the hardware base unit 12 may include sub-modules such as a symbol map 124, a scrambling 125, an add/drop 126, and a multiplying power 127.
  • the hardware part of the baseband chip that supports the core algorithm of the chip level is used as the hardware basic unit.
  • the structure of the hardware base unit 12 shown in FIG. 3 supports core chip processing at the upstream chip level
  • the structure of the hardware base unit 12 shown in FIG. 4 supports core algorithm processing at the downstream chip level. Therefore, the baseband chip provided by the embodiment of the present invention can determine the structure of using the hardware basic unit according to the type of the actual processing signal.
  • the hardware basic unit in the embodiment of the present invention is formed by combining and integrating the chip core algorithm part in the hardware architecture in the prior art, that is, the hardware basic unit. Used as a hardware resource pool.
  • n1-n5 respectively indicate that five functional modules need to use the set number of A, and C1-C5 respectively represent five functional modules except the auxiliary functions except A.
  • A is a chip core algorithm.
  • A is used as a hardware basic unit, and a soft core array calling method is used to implement scheduling of different numbers of A, complete chip core algorithm, and then complete C1 in the soft core array. - The processing of the auxiliary functions of the C5 is sufficient.
  • the DMA detects the processing status of the hardware basic unit for a subtask, and when the processing status is completed, the soft core array receives the interrupt of the DMA transmission.
  • the soft core array sends a processing command corresponding to at least one subtask to the DMA according to the task list, and the DMA detects the processing status of the hardware basic unit for one subtask, and when the processing status is completed, the soft core array receives the DMA transmission. Interrupted.
  • the function of the DMA is to be dispatched by the soft core array to directly interact with the hardware basic unit, that is, to transfer the task parameters to be sent by the soft core array and the data and parameters to be reported by the hardware basic unit.
  • the DMA detection hardware basic unit can implement the processing state of a subtask by: the DMA determines the processing state by detecting the value of the processing flag bit in the hardware basic unit, for example, the processing in the DMA detection hardware basic unit is empty.
  • the soft core array responds to the interrupt, acquires the task result of a subtask from the memory, and performs an auxiliary function processing on the task result of the subtask, and stores the auxiliary function processing result into the memory for the DMA to attach to the memory.
  • the function processing result is reported and processed at the symbol level or bit level.
  • the soft core array After the soft core array receives the interrupt sent by the DMA, it is completed by the hardware basic unit.
  • the chip core algorithm of a subtask, but the subordinate function of a subtask has not been processed. Therefore, the soft core array responds to the interrupt, acquires the task result of a subtask from the memory, and performs the auxiliary function processing on the task result of a subtask. And storing the auxiliary function processing result to the memory for the DMA to report the result of the auxiliary function processing in the memory for symbol level or bit level processing.
  • a signal processing method provided by the embodiment of the present invention is as shown in FIG. 9. After S202, before S203, the method may further include: S206. Specifically include:
  • the soft core array detects a buffer status of the hardware basic unit.
  • the soft core array configures the first task as at least one subtask, and after forming the task list including the at least one subtask, the soft core array can issue the subtask due to the idleness of the hardware basic unit cache.
  • the soft core array first detects the cache state of the hardware base unit.
  • the hardware basic unit in the embodiment of the present invention is used as a hardware resource pool.
  • the soft core array issues a sub-task to the hardware basic unit.
  • the soft core array divides the first task into 10 subtasks, and the soft core array detects that the cache state of the hardware basic unit is idle, and can support the implementation of two subtasks. Therefore, the soft core array delivers 2 subordinates through the DMA.
  • the task is processed by the hardware basic unit first, and when the cache of the hardware basic unit is idle again, other subtasks are issued.
  • the implementation manner of the buffer state of the soft core array detecting hardware basic unit may be: the soft core array determines the buffer status by detecting the value of the cache flag bit of the hardware basic unit, for example, the soft core array detects the non-full signal of the hardware basic unit. When the non-full signal is 1, the buffer representing the hardware basic unit is full; when the non-full signal is 0, the cache representing the hardware basic unit is not full.
  • the embodiment of the present invention designs a baseband chip based on CPU array + soft core array (simple processor array) + hardware basic unit (hard core architecture), instead of the original pure hard core, pure soft core, Or the baseband chip of the CPU array + hard core architecture, therefore, the power consumption and area of the chip are greatly reduced, and the chip design difficulty and development cycle are greatly reduced. Since the soft core array can be deployed in parallel to the hardware basic unit, the success rate of the streaming chip is greatly improved, and it is also convenient for the user to provide a fast customized development project, providing rapid upgrade and expansion.
  • the order of the sub-tasks issued by the soft-core array is performed according to the task list.
  • the soft-nuclear array determines that the sub-tasks are to be sent
  • the sub-tasks to be delivered will be identified according to the order of the task list.
  • the transfer command is sent to the DMA, and the DMA can read the subtask parameters corresponding to the subtask identifier from the RAM according to the move command, and package the subtask request and the subtask parameters corresponding to the subtask to the hardware basic unit to perform Chip processing.
  • the process of issuing the sub-task of the soft-core array may be sent periodically. Therefore, when the soft-nuclear array detects that the cache state of the hardware basic unit is idle and reaches the delivery period, the soft core array is sent and moved. Command to DMA.
  • S203 may be specifically as follows:
  • the soft core array After the soft core array detects the cache state of the hardware basic unit, when the soft core array detects that the cache state of the hardware basic unit is idle, the soft core array sends a move command corresponding to the at least one subtask to the DMA.
  • a soft core array receives a first task sent by a CPU array, where the first task is a chip processing task; and the soft core array sends the first task to a hardware basic unit.
  • the baseband chip adopts the architecture of the CPU array + soft core array + hardware basic unit to realize chip processing, since only the chip core algorithm is implemented in a hardware basic unit, and through soft
  • the basic unit of the nuclear array scheduling hardware implements the chip processing task, so that the design of the baseband chip is difficult, and the design area and power consumption of the baseband chip are greatly reduced, and the development cycle of the baseband chip is reduced.
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.
  • the baseband chip includes: a CPU array, a soft core array, and a hardware basic unit, wherein the CPU array, the soft core array, and the hardware basic unit are connected by a bus; the CPU array sends the soft core array to the soft core array.
  • the first task is that the first task is a chip processing task; the soft core array sends the first task to a hardware basic unit; and the hardware basic unit performs a first task.
  • the scheme of the embodiment of the present invention is adopted, that is, the baseband chip adopts the architecture of the CPU array + the soft core array + the hardware basic unit to implement chip processing, since only the chip core algorithm is implemented in one hardware basic unit, and is scheduled by the soft core array.
  • the hardware basic unit realizes the chip processing task, so that the design of the baseband chip is difficult, the design area and power consumption of the baseband chip are greatly reduced, thereby reducing the development cycle of the baseband chip.

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Abstract

本发明实施例公开了一种基带芯片，包括：CPU阵列、软核阵列和硬件基本单元；所述CPU阵列、软核阵列和硬件基本单元通过总线连接；所述CPU阵列，配置为向所述软核阵列发送第一任务，所述第一任务为码片处理任务；所述软核阵列，配置为将第一任务发送至所述硬件基本单元；所述硬件基本单元，配置为执行第一任务。本发明实施例还同时公开了一种信号处理方法。

Description

一种基带芯片及信号处理方法 技术领域
本发明涉及无线通信领域中的无线接入技术，尤其涉及一种基带芯片及信号处理方法。
背景技术
基于码分多址技术的无线接入技术，已经在无线通讯领域广泛使用，并且是现有无线接入技术的重要组成部分。随着互联网的纵深繁荣，无线数据流量正以指数曲线巨幅增长，无线接入方式需求也越来越多。那么，如何快速扩容，以及如何根据用户需求，高效地定制个性化的接入设备，特别是在最终实现为用户提高更好体验的同时，降低开发的成本、风险、及周期。这些问题给无线运营商，特别是无线设备制造商提出了新的要求。
码分多址技术的无线接入设备中基带处理部分也是其中至关重要的一环，特别是码片处理部分，因其实时性、整体运算性能以及设计难度较高，常常是制约整个设备性能和功能的重要环节。现***分多址技术的无线接入设备的码片处理部分主要有以下几种实现方式：
1、现场可编程门阵列(FPGA，Field－Programmable Gate Array)
用可现场编程的FPGA实现基带功能，其优点是可以快速完成设计，并且容易升级更新，其缺点是成本高，FPGA也由几大巨头控制，自主规划空间的设计面积有限。
2、专用集成电路(ASIC，Application Specific Integrated Circuit)
最成熟的实现方法是纯ASIC。因码分多址技术已经比较成熟，基于ASIC的技术演进多年也日臻完美，其优点是成本极低，但缺点也很明显：开发周期长，难度大，容量提升或者设计面积会受到ASIC固化架构的制约。
3、中央处理器(CPU，Central Processing Unit)阵列+ASIC
用CPU阵列+ASIC实现码片处理，本质上是占用上层高级CPU阵列(如微处理器ARM，Advanced RISC Machines))资源来完成码片处理的部分工作。其优点是借助现有片上***(SOC，System on Chip)平台的CPU阵列将部分ASIC功能变成软件处理，降低难度和风险，也便于更新升级，其缺点是用软件替代的这部分功能往往是重复调度或查询，会消耗CPU阵列大量资源，功耗大，性价比低。
因此，针对码分多址技术的无线接入设备中基带处理码片部分设计，现有技术中存在的开发难度大、周期长、功耗或设计面积受制约明显等问题和缺陷亟需解决。
发明内容
为解决上述技术问题，本发明实施例期望提供一种基带芯片及信号处理方法。
本发明实施例的技术方案是这样实现的：
本发明实施例提供一种基带芯片，包括：CPU阵列、软核阵列和硬件基本单元；所述CPU阵列、所述软核阵列和所述硬件基本单元通过总线连接；
所述CPU阵列，配置为向所述软核阵列发送第一任务，所述第一任务为码片处理任务；
所述软核阵列，配置为将所述第一任务发送至所述硬件基本单元；
所述硬件基本单元，配置为执行所述第一任务。
在上述基带芯片中，所述软核阵列，还配置为将所述第一任务发送至所述硬件基本单元之前，将所述第一任务配置为至少一个子任务，形成包括所述至少一个子任务的任务列表。
在上述基带芯片中，所述基带芯片还包括：直接内存访问(DMA，Direct  Memory Access)和存储器；所述DMA与所述硬件基本单元连接，所述DMA通过所述总线与所述软核阵列连接，所述存储器通过所述总线分别与所述软核阵列和所述硬件基本单元连接；
所述软核阵列，配置为根据所述任务列表，发送与所述至少一个子任务对应的搬移命令至所述DMA；所述搬移命令用于指示所述DMA发送所述至少一个子任务中的每个子任务至所述硬件基本单元，以及指示在所述硬件基本单元处理完所述每个子任务之后，所述DMA反馈中断至所述软核阵列；
所述DMA，配置为发送所述每个子任务至所述硬件基本单元；
所述硬件基本单元，配置为分别执行所述每个子任务，并将所述每个子任务的任务结果存储在存储器中；
所述DMA，还配置为检测所述硬件基本单元对一个子任务的处理状态，以及所述处理状态为完成时，发送所述中断至所述软核阵列；
所述软核阵列，还配置为响应所述中断，从所述存储器中获取所述一个子任务的任务结果，并对所述一个子任务的任务结果进行附属功能处理，并将附属功能处理结果存储至所述存储器；
所述DMA，还配置为将所述存储器中的所述附属功能处理结果上报，以进行符号级或比特级处理。
在上述基带芯片中，所述软核阵列，还配置为发送与所述至少一个子任务对应的搬移命令至所述DMA之前，检测所述硬件基本单元的缓存状态；
所述软核阵列，还配置为检测到所述硬件基本单元的缓存状态为空闲时，发送与所述至少一个子任务对应的搬移命令至所述DMA。
在上述基带芯片中，所述软核阵列中包括随机存取存储器(RAM，Random Access Memory)和先入先出队列(FIFO，First Input First Output) 存储器；所述至少一个子任务包括所述至少一个子任务请求和所述至少一个子任务参数；
所述FIFO存储器，配置为存储所述至少一个子任务请求；
所述RAM，配置为存储所述至少一个子任务参数。
本发明实施例提供一种信号处理方法，包括：
软核阵列接收中央处理器CPU阵列发送的第一任务，所述第一任务为码片处理任务；
所述软核阵列将所述第一任务发送至硬件基本单元；
所述硬件基本单元执行所述第一任务。
在上述方案中，所述软核阵列将所述第一任务发送至硬件基本单元之前，所述方法还包括：
所述软核阵列将所述第一任务配置为至少一个子任务，形成包括所述至少一个子任务的任务列表；
相应地，所述软核阵列将所述第一任务发送至硬件基本单元，包括：
所述软核阵列根据所述任务列表，发送与所述至少一个子任务对应的搬移命令至所述DMA，以供所述DMA发送所述每个子任务至所述硬件基本单元；所述搬移命令用于指示所述DMA发送所述至少一个子任务中的每个子任务至所述硬件基本单元，以及指示在所述硬件基本单元处理完所述每个子任务之后，所述DMA反馈中断；
所述硬件基本单元执行所述第一任务，包括：
所述硬件基本单元分别执行所述每个子任务，并将所述每个子任务的任务结果存储在存储器中。
在上述方案中，所述发送与所述至少一个子任务对应的搬移命令至所述DMA之后，所述方法还包括：
所述DMA检测所述硬件基本单元对一个子任务的处理状态，以及所述 处理状态为完成时，所述软核阵列接收所述DMA发送的所述中断；
所述软核阵列响应所述中断，从所述存储器中获取所述一个子任务的任务结果，并对所述一个子任务的任务结果进行附属功能处理，并将附属功能处理结果存储至所述存储器，供所述DMA将所述存储器中的所述附属功能处理结果上报，以进行符号级或比特级处理。
在上述方案中，所述软核阵列根据所述任务列表，发送与所述至少一个子任务对应的搬移命令至所述DMA之前，所述方法还包括：
所述软核阵列检测所述硬件基本单元的缓存状态。
在上述方案中，所述软核阵列根据所述任务列表，发送与所述至少一个子任务对应的搬移命令至所述DMA，包括：
所述软核阵列检测到所述硬件基本单元的缓存状态为空闲时，根据所述任务列表，发送与所述至少一个子任务对应的搬移命令至所述DMA。
本发明实施例提供了一种基带芯片及信号处理方法，基带芯片包括：CPU阵列、软核阵列和硬件基本单元，所述CPU阵列、软核阵列和硬件基本单元通过总线连接；CPU阵列向软核阵列发送第一任务，所述第一任务为码片处理任务；软核阵列将第一任务发送至硬件基本单元；硬件基本单元执行第一任务。采用上述技术实现方案，即基带芯片采用CPU阵列+软核阵列+硬件基本单元的架构实现码片处理，由于只将码片核心算法在一个硬件基本单元中实现，并通过软核阵列调度硬件基本单元实现码片处理任务，这样设计的基带芯片的设计难度低，就将基带芯片的设计面积和功耗大大降低了，进而基带芯片的开发周期就降低了。
附图说明
图1为现有技术中的示例性的基带芯片的结构示意图；
图2为本发明实施例提供的一种基带芯片的结构示意图一；
图3为本发明实施例提供的硬件基本单元的结构示意图一；
图4为本发明实施例提供的硬件基本单元的结构示意图二；
图5为本发明实施例提供的一种基带芯片的结构示意图二；
图6为本发明实施例提供的一种基带芯片的结构示意图三；
图7为本发明实施例提供的一种信号处理方法的流程图一；
图8为本发明实施例提供的一种信号处理方法的流程图二；
图9为本发明实施例提供的一种信号处理方法的流程图三。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。
现有的CPU阵列+ASIC实现码片处理的结构如图1所示，CPU阵列通过总线(BUS)与ASIC进行数据交互。其中，ASIC可以实现五大功能，其中，n1-n5分别表示五个功能模块需要使用A的数量；C1-C5分别表示五个功能模块除去A之外的附属功能，A为码片的核心算法部分。
由于A已完成了解扩，附属功能C1-C5的数据率已大幅降低，所以本发明实施例采用软件实现(软核阵列)。
基于此，在本发明的各种实施例中：CPU阵列、软核阵列和硬件基本单元通过总线连接；CPU阵列向软核阵列发送第一任务，所述第一任务为码片处理任务；软核阵列将第一任务发送至硬件基本单元；硬件基本单元执行第一任务。
实施例一
如图2所示，本发明实施例提供一种基带芯片1，该基带芯片1包括：CPU阵列10、软核阵列11和硬件基本单元12，所述CPU阵列10、所述软核阵列11和所述硬件基本单元12通过总线13连接。
所述CPU阵列10，配置为向所述软核阵列11发送第一任务，所述第一任务为码片处理任务。
所述软核阵列11，配置为将所述第一任务发送至所述硬件基本单元12。
所述硬件基本单元12，配置为执行所述第一任务。
需要说明的是，本发明实施例应用的背景为：码分多址技术的无线接入设备中基带处理部分其中的码片处理部分，主要使用基带芯片来进行码片处理，而本发明实施例提供的基带芯片1采用CPU阵列+软核阵列+硬件基本单元的架构实现码片处理。
实际应用时，如图3所示，所述硬件基本单元12可以包括：天线插值120、天线解扰121、天线解扩122、频偏补偿123等子模块；或者，如图4所示，所述硬件基本单元12可以包括：符号映射124、加扰125、加扩126、乘功率127等子模块。
需要说明的是，本发明实施例中，将基带芯片1中支持码片级的核心算法处理的硬件部分作为硬件基本单元12使用。图3所示的硬件基本单元12的结构支持上行码片级的核心算法处理，图4所示的硬件基本单元12的结构支持下行码片级的核心算法处理。因此，本发明实施例提供的基带芯片1可以根据实际处理信号的类型决定使用硬件基本单元12的结构。
可以理解的是，本发明实施例中的硬件基本单元是将现有技术中的硬件架构中的码片核心算法部分经过合并和整合构成的，即将硬件基本单元作为硬件资源池使用。
示例性地，如图1所示，现有的硬件架构中，由n1-n5分别表示五个功能模块需要使用A的套数，C1-C5分别表示五个功能模块除去A之外的附属功能，其中，A就是码片核心算法；本发明实施例中，将A作为硬件基本单元，采用软核阵列调用的方法实现不同数量A的调度，完成码片核心算法，再在软核阵列中完成C1-C5的附属功能的处理即可。
在一实施例中，本发明实施例中的软核阵列11是使用简单处理器组成的firmware软核阵列，具体可以是arm的M系列处理器等简单CPU阵列， 能够支持总线协议(AXI，Advanced eXtensible Interface)、或***总线(APB，Advanced Peripheral Bus)等常用总线，以便和上层CPU阵列以及下层硬件基本单元通信。
需要说明的是，本发明实施例中的第一任务指的是对基带信号(天线信号)做码片处理的任务，第一任务中包括第一任务请求和第一任务参数(即表征基带信号要做什么功能的码片处理)。
进一步地，硬件基本单元12进行码片级的核心算法的处理。
可选地，所述软核阵列11，还配置为所述CPU阵列10发送第一任务之后，将所述第一任务发送至所述硬件基本单元12之前，将所述第一任务配置为至少一个子任务，形成包括所述至少一个子任务的任务列表。
需要说明的是，本发明实施例中需要处理的基带信号，即天线信号，可以是至少一段天线信号，因此，CPU阵列10发送的是至少一段天线信号的码片处理任务；软核阵列11将每一段天线信号的每一类功能的码片处理任务分成一个子任务，软核阵列11通过对硬件基本单元12的调度完成至少一个天线信号对应的至少一个子任务。
可选地，如图5所示，所述软核阵列11中包括RAM 110和FIFO存储器111；所述至少一个子任务包括所述至少一个子任务请求和所述至少一个子任务参数。
所述FIFO存储器111，配置为存储所述至少一个子任务请求。
所述RAM 110，配置为存储所述至少一个子任务参数。
需要说明的是，软核阵列11的多个核间不通信，由共享RAM或通过FIFO实现数据交互。
特别地，CPU阵列10向软核阵列11配置基本任务(第一任务)。软核阵列11将分成的至少一个子任务请求配到软核阵列11中软核各自的FIFO存储器111中，将至少一个子任务参数配置到各软核共享的RAM 110中。
具体地，软核阵列11读取FIFO存储器111中的至少一个子任务请求，然后建立任务列表，建立的任务列表为包括至少一个子任务的任务列表。
可选地，上述任务列表中包括至少一个子任务各自的子任务标识。具体的子任务标识的形式及表现方式，本发明实施例不作限制。
可选地，如图6所示，所述基带芯片1还可以包括：DMA 14和存储器15；所述DMA 14与所述硬件基本单元12连接，所述DMA 14通过所述总线13与所述软核阵列11连接，所述存储器15通过所述总线13分别与所述软核阵列11和所述DMA 14连接。
所述软核阵列11，具体配置为根据所述任务列表，发送与所述至少一个子任务对应的搬移命令至所述DMA 14，所述搬移命令用于指示所述DMA 14发送所述至少一个子任务中的每个子任务至所述硬件基本单元12，以及指示在所述硬件基本单元12处理完所述每个子任务之后，所述DMA14反馈中断至所述软核阵列11。
所述DMA 14，配置为发送所述每个子任务至所述硬件基本单元12。
所述硬件基本单元12，具体配置为分别执行所述每个子任务，并将所述每个子任务的任务结果存储在存储器15中。其中，所述硬件基本单元12通过所述DMA 14将所述每个子任务的任务结果存储至存储器15中。换句话说，所述硬件基本单元12将每个子任务的任务结果发送给所述DMA 14；由所述DMA 14将收到的每个子任务的任务结果存储至存储器15中。
所述DMA 14，还配置为检测所述硬件基本单元12对一个子任务的处理状态，以及所述处理状态为完成时，发送所述中断至所述软核阵列11。
所述软核阵列11，还配置为响应所述中断，从所述存储器15中获取所述一个子任务的任务结果，并对所述一个子任务的任务结果进行附属功能处理，并将附属功能处理结果存储至所述存储器15。
所述DMA 14，还配置为将所述存储器15中的所述附属功能处理结果 上报，以进行符号级或比特级处理。
需要说明的是，DMA 14的功能就是被软核阵列11调度，用来直接和硬件基本单元12交互，即搬移软核阵列11要下发的任务参数和硬件基本单元12要上报的数据和参数。
具体地，DMA 14检测硬件基本单元12对一个子任务的处理状态的实现方式可以为：DMA 14通过检测硬件基本单元12中的处理标志位的值来判断处理状态，例如，DMA 14检测硬件基本单元12中的处理空信号，当处理空信号为1时，表征一个子任务未完成；当处理空信号为0时，表征一个子任务完成。
需要说明的是，DMA 14检测硬件基本单元12对一个子任务的处理状态的实现方式可以采用现有技术的多种方式来实现，本发明实施例不作限制。
可选地，所述软核阵列11，还配置为所述CPU阵列10发送第一任务之后，发送与所述至少一个子任务对应的搬移命令至所述DMA 14之前，检测所述硬件基本单元12的缓存状态。
所述软核阵列11，还具体配置为检测到所述硬件基本单元12的缓存状态为空闲时，发送与所述至少一个子任务对应的搬移命令至所述DMA 14。
需要说明的是，本发明实施例中的硬件基本单元12是作为硬件资源池使用的，在硬件基本单元12的缓存有空闲的状态下，软核阵列11下发子任务给硬件基本单元12的。例如，软核阵列11将第一任务分成了10个子任务，而软核阵列11检测到硬件基本单元12的缓存状态有空闲，可以支持2个子任务的实施，因此，软核阵列11就通过DMA 14下发2子任务给硬件基本单元12先处理，等到硬件基本单元12的缓存再次为空闲时，再下发其他子任务。
具体地，软核阵列11检测硬件基本单元12的缓存状态实现方式可以 为：软核阵列11通过检测硬件基本单元12的缓存标志位的值来判断缓存状态，例如，软核阵列检测硬件基本单元12的非满信号，当非满信号为1时，表征硬件基本单元12的缓存已满；当非满信号为0时，表征硬件基本单元12的缓存未满。
需要说明的是，软核阵列11检测硬件基本单元12的缓存状态实现方式可以采用现有技术的多种方式来实现，本发明实施例不作限制。
可以理解的是，针对码分多址技术的无线接入设备中基带处理码片部分设计，本发明实施例设计了一种基于CPU阵列+软核阵列(简单处理器阵列)+硬件基本单元(硬核架构)的基带芯片，以替代原有基于纯硬核，纯软核，或者CPU阵列+硬核架构的基带芯片，因此，芯片的功耗和面积大幅降低，芯片设计难度和开发周期大幅降低。由于软核阵列11可以并列下发子任务至硬件基本单元12，因此，流片成功率大幅提高，也便于为用户提供快速定制开发项目，提供快速升级扩容。
进一步地，软核阵列11下发子任务是的顺序是按照任务列表进行的，当软核阵列11判断出要下发子任务时，将按照任务列表的顺序，将需要下发的子任务的标识及搬移命令发送给DMA 14，DMA 14就可以根据搬移命令，将子任务标识对应的子任务参数从RAM中读取出来，并将子任务对应的子任务请求和子任务参数打包发送给硬件基本单元12，以进行码片处理。
进一步地，软核阵列11下发子任务的过程可以是定时下发的，因此，当软核阵列11检测到硬件基本单元12的缓存状态为空闲，且到达下发周期时，软核阵列11才下发搬移命令给DMA 14。
进一步地，CPU阵列10发送给软核阵列11的第一任务可以是一个固定的任务包，此时，软核阵列11只要将这个任务包中的任务处理完就结束了任务。若是CPU阵列10发送的第一任务是一直不停的任务，那么，软核阵列11就会一直在进行CPU阵列10配置的任务。但是软核阵列11执行 任务的方法都是上述的过程。
本发明实施例所提供的基带芯片，包括：CPU阵列、软核阵列和硬件基本单元，所述CPU阵列、软核阵列和硬件基本单元通过总线连接所述CPU阵列向软核阵列发送第一任务，所述第一任务为码片处理任务；所述软核阵列将第一任务发送至硬件基本单元；所述硬件基本单元执行第一任务。采用上述技术实现方案，即基带芯片采用CPU阵列+软核阵列+硬件基本单元的架构实现码片处理，由于只将码片核心算法在一个硬件基本单元中实现，并通过软核阵列调度硬件基本单元实现码片处理任务，这样设计的基带芯片的设计难度低，就将基带芯片的设计面积和功耗大大降低了，进而基带芯片的开发周期就降低了。
实施例二
本发明实施例提供一种信号处理方法，如图7所示，该方法包括以下步骤：
S101、软核阵列接收CPU阵列发送的第一任务，所述第一任务为码片处理任务。
需要说明的是，本发明实施例应用的背景为：码分多址技术的无线接入设备中基带处理部分其中的码片处理部分，主要使用基带芯片来进行码片处理，而本发明实施例提供的基带芯片采用CPU阵列+软核阵列+硬件基本单元的架构实现码片处理。
可选地，本发明实施例中的软核阵列是使用简单处理器组成的firmware软核阵列，具体的可以是arm的M系列处理器等简单CPU阵列，能够支持AXI、APB等常用总线，以便和上层CPU阵列以及下层硬件基本单元通信。
需要说明的是，本发明实施例中的第一任务指的是对基带信号(天线信号)做码片处理的任务，第一任务中包括第一任务请求和第一任务参数(即基带信号要做什么功能的码片处理)。
在本发明实施例中，软核阵列接收CPU阵列发送的第一任务，所述第一任务为将基带信号进行码片处理的任务。
S102、所述软核阵列将第一任务发送至硬件基本单元，以供所述硬件基本单元执行所述第一任务。
所述软核阵列接收所述CPU阵列发送的第一任务之后，所述软核阵列将第一任务发送至所述硬件基本单元，以使所述硬件基本单元执行所述第一任务，进行码片级的核心算法的处理。
实际应用时，如图3所示，所述硬件基本单元12可以包括：天线插值120、天线解扰121、天线解扩122、频偏补偿123等子模块；或者，如图4所示，所述硬件基本单元12可以包括：符号映射124、加扰125、加扩126、乘功率127等子模块。
需要说明的是，本发明实施例中，将基带芯片中支持码片级的核心算法处理的硬件部分作为硬件基本单元使用。图3所示的硬件基本单元12的结构支持上行码片级的核心算法处理，图4所示的硬件基本单元12的结构支持下行码片级的核心算法处理。因此，本发明实施例提供的基带芯片可以根据实际处理信号的类型决定使用硬件基本单元的结构。
可以理解的是，本发明实施例中的硬件基本单元是将现有技术中的硬件架构中的码片核心算法部分经过合并和整合构成的，即将硬件基本单元作为硬件资源池使用。
示例性地，如图1所示，现有的硬件架构中，由n1-n5分别表示五个功能模块需要使用A的套数，C1-C5分别表示五个功能模块除去A之外的附属功能，其中，A就是码片核心算法；本发明实施例中，将A作为硬件基本单元，采用软核阵列调用的方法实现不同数量A的调度，完成码片核心算法，再在软核阵列中完成C1-C5的附属功能的处理即可。
本发明实施例所提供的一种信息处理方法，软核阵列接收CPU阵列发 送的第一任务，所述第一任务为码片处理任务；所述软核阵列将第一任务发送至硬件基本单元，以使所述硬件基本单元执行第一任务。采用上述技术实现方案，基带芯片采用CPU阵列+软核阵列+硬件基本单元的架构实现码片处理，由于只将码片核心算法在一个硬件基本单元中实现，并通过软核阵列调度硬件基本单元实现码片处理任务，这样设计的基带芯片的设计难度低，就将基带芯片的设计面积和功耗大大降低了，进而基带芯片的开发周期就降低了。
实施例三
本发明实施例所提供的一种信号处理方法，如图8所示，该方法包括以下步骤：
S201、软核阵列接收CPU阵列发送的第一任务，所述第一任务为码片处理任务。
需要说明的是，本发明实施例应用的背景为：码分多址技术的无线接入设备中基带处理部分其中的码片处理部分，主要使用基带芯片来进行码片处理，而本发明实施例提供的基带芯片采用CPU阵列+软核阵列+硬件基本单元的架构实现码片处理。
可选地，本发明实施例中的软核阵列是使用简单处理器组成的firmware软核阵列，具体的可以是arm的M系列处理器等简单CPU阵列，能够支持AXI、APB等常用总线，以便和上层CPU阵列以及下层硬件基本单元通信。
需要说明的是，本发明实施例中的第一任务指的是对基带信号(天线信号)做码片处理的任务，第一任务中包括第一任务请求和第一任务参数(即基带信号要做什么功能的码片处理)。
在本发明实施例中，软核阵列接收CPU阵列发送的第一任务，所述第一任务为将基带信号进行码片处理的任务。
进一步地，CPU阵列发送给软核阵列的第一任务可以是一个固定的任 务包，此时，软核阵列只要将这个任务包中的任务处理完就结束任务。若是CPU阵列发送的第一任务是一直不停的任务，那么，软核阵列就会一直在进行CPU阵列配置的任务。但是软核阵列执行任务的方法都是本发明实施例提供的信号处理的过程。
S202、软核阵列将第一任务配置为至少一个子任务，形成包括所述至少一个子任务的任务列表。
所述软核阵列接收CPU阵列发送的第一任务之后，所述软核阵列将第一任务配置为至少一个子任务，并且形成了包括所述至少一个子任务的任务列表。
特别地，所述CPU阵列向所述软核阵列配置基本任务(第一任务)。所述软核阵列将分成的至少一个子任务请求配到所述软核阵列中软核各自的FIFO存储器中，将至少一个子任务参数配置到各软核共享的RAM中。
需要说明的是，本发明实施例中需要处理的基带信号，即天线信号，可以是至少一段天线信号，因此，CPU阵列发送的是至少一段天线信号的码片处理任务；在软核阵列中，软核阵列将每一段天线信号的每一类功能的码片处理任务分成一个子任务，软核阵列通过对硬件基本单元的调度完成至少一个天线信号对应的至少一个子任务。
具体地，所述软核阵列读取FIFO存储器中的至少一个子任务请求，然后建立任务列表，所述任务列表为包括至少一个子任务的任务列表。
可选地，上述任务列表中包括至少一个子任务各自的子任务标识。具体的子任务标识的形式及表现方式，本发明实施例不作限制。
S203、所述软核阵列根据任务列表，发送与所述至少一个子任务对应的搬移命令至DMA，以供所述DMA发送每个子任务至硬件基本单元，及所述硬件基本单元分别执行每个子任务，并将每个子任务的任务结果存储在存储器中，所述搬移命令用于指示所述DMA发送至少一个子任务中的每 个子任务至所述硬件基本单元，以及指示在所述硬件基本单元处理完每个子任务之后，所述DMA反馈中断。
所述软核阵列将第一任务配置为至少一个子任务，形成包括所述至少一个子任务的任务列表之后，所述软核阵列根据任务列表，发送与所述至少一个子任务对应的搬移命令至DMA。
具体地，软核阵列根据任务列表，发送与所述至少一个子任务的标识对应的搬移命令至DMA。
需要说明的是，DMA发送每个子任务至硬件基本单元；硬件基本单元分别执行每个子任务，以进行码片级的核心算法的处理，并将每个子任务的任务结果存储在存储器中(硬件基本单元通过DMA将每个子任务的任务结果存储至存储器中，换句话说，硬件基本单元将每个子任务的任务结果发送给DMA；由DMA将收到的每个子任务的任务结果存储至存储器中)；DMA检测硬件基本单元对一个子任务的处理状态，以及该处理状态为完成时，发送中断至软核阵列。
实际应用时，如图3所示，所述硬件基本单元12可以包括：天线插值120、天线解扰121、天线解扩122、频偏补偿123等子模块；或者，如图4所示，所述硬件基本单元12可以包括：符号映射124、加扰125、加扩126、乘功率127等子模块。
需要说明的是，本发明实施例中，将基带芯片中支持码片级的核心算法处理的硬件部分作为硬件基本单元使用。图3所示的硬件基本单元12的结构支持上行码片级的核心算法处理，图4所示的硬件基本单元12的结构支持下行码片级的核心算法处理。因此，本发明实施例提供的基带芯片可以根据实际处理信号的类型决定使用硬件基本单元的结构。
可以理解的是，本发明实施例中的硬件基本单元是将现有技术中的硬件架构中的码片核心算法部分经过合并和整合构成的，即将硬件基本单元 作为硬件资源池使用。
示例性地，如图1所示，现有的硬件架构中，由n1-n5分别表示五个功能模块需要使用A的套数，C1-C5分别表示五个功能模块除去A之外的附属功能，其中，A就是码片核心算法；本发明实施例中，将A作为硬件基本单元，采用软核阵列调用的方法实现不同数量A的调度，完成码片核心算法，再在软核阵列中完成C1-C5的附属功能的处理即可。
S204、DMA检测硬件基本单元对一个子任务的处理状态，以及处理状态为完成时，软核阵列接收DMA发送的中断。
软核阵列根据任务列表，发送与至少一个子任务对应的搬移命令至DMA之后，DMA检测硬件基本单元的对一个子任务的处理状态，并当处理状态为完成时，软核阵列接收DMA发送的中断。
需要说明的是，DMA的功能就是被软核阵列调度，用来直接和硬件基本单元交互，即搬移软核阵列要下发的任务参数和硬件基本单元要上报的数据和参数。
具体地，DMA检测硬件基本单元对一个子任务的处理状态的实现方式可以为：DMA通过检测硬件基本单元中的处理标志位的值来判断处理状态，例如，DMA检测硬件基本单元中的处理空信号，当处理空信号为1时，表征一个子任务未完成；当处理空信号为0时，表征一个子任务完成。
需要说明的是，DMA检测硬件基本单元对一个子任务的处理状态的实现方式可以采用现有技术的多种方式来实现，本发明实施例不作限制。
S205、软核阵列响应中断，从存储器中获取一个子任务的任务结果，并对一个子任务的任务结果进行附属功能处理，并将附属功能处理结果存储至存储器，以供DMA将存储器中的附属功能处理结果上报，进行符号级或比特级处理。
软核阵列接收DMA发送的中断之后，由于通过硬件基本单元完成了一 个子任务的码片核心算法，但是一个子任务的附属功能还没有处理，因此，软核阵列响应中断，从存储器中获取一个子任务的任务结果，并对一个子任务的任务结果进行附属功能处理，并将附属功能处理结果存储至存储器，以供DMA将所述存储器中的附属功能处理结果上报，以进行符号级或比特级处理。
进一步地，本发明实施例所提供的一种信号处理方法，如图9所示，S202之后，S203之前，该方法还可以包括：S206。具体包括：
S206、软核阵列检测硬件基本单元的缓存状态。
软核阵列将第一任务配置为至少一个子任务，形成包括所述至少一个子任务的任务列表之后，由于在硬件基本单元的缓存有空闲时，所述软核阵列才能下发子任务，因此，所述软核阵列先检测硬件基本单元的缓存状态。
需要说明的是，本发明实施例中的硬件基本单元是作为硬件资源池使用的，在硬件基本单元的缓存有空闲的状态下，软核阵列下发子任务给硬件基本单元的。例如，软核阵列将第一任务分成了10个子任务，而软核阵列检测到硬件基本单元的缓存状态有空闲，可以支持2个子任务的实施，因此，软核阵列就通过DMA下发2子任务给硬件基本单元先处理，等到硬件基本单元的缓存再次为空闲时，再下发其他子任务。
具体地，软核阵列检测硬件基本单元的缓存状态实现方式可以为：软核阵列通过检测硬件基本单元的缓存标志位的值来判断缓存状态，例如，软核阵列检测硬件基本单元的非满信号，当非满信号为1时，表征硬件基本单元的缓存已满；当非满信号为0时，表征硬件基本单元的缓存未满。
需要说明的是，软核阵列检测硬件基本单元的缓存状态实现方式可以采用现有技术的多种方式来实现，本发明实施例不作限制。
可以理解的是，针对码分多址技术的无线接入设备中基带处理码片部 分设计，本发明实施例设计了一种基于CPU阵列+软核阵列(简单处理器阵列)+硬件基本单元(硬核架构)的基带芯片，以替代原有基于纯硬核，纯软核，或者CPU阵列+硬核架构的基带芯片，因此，芯片的功耗和面积大幅降低，芯片设计难度和开发周期大幅降低。由于软核阵列可以并列下发子任务至硬件基本单元，因此，流片成功率大幅提高，也便于为用户提供快速定制开发项目，提供快速升级扩容。
进一步地，软核阵列下发子任务是的顺序是按照任务列表进行的，当软核阵列判断出要下发子任务时，将按照任务列表的顺序，将需要下发的子任务的标识及搬移命令发送给DMA，DMA就可以根据搬移命令，将子任务标识对应的子任务参数从RAM中读取出来，并将子任务对应的子任务请求和子任务参数打包发送给硬件基本单元，以进行码片处理。
进一步地，软核阵列下发子任务的过程可以是定时下发的，因此，当软核阵列检测到硬件基本单元的缓存状态为空闲，且到达下发周期时，软核阵列才下发搬移命令给DMA。
具体地，S206之后，S203可以具体如下：
S203、软核阵列检测到硬件基本单元的缓存状态为空闲时，发送与至少一个子任务对应的搬移命令至DMA。
软核阵列检测硬件基本单元的缓存状态之后，所述软核阵列检测到硬件基本单元的缓存状态为空闲时，所述软核阵列发送与至少一个子任务对应的搬移命令至DMA。
本发明实施例所提供的一种信息处理方法，软核阵列接收CPU阵列发送的第一任务，所述第一任务为码片处理任务；所述软核阵列将第一任务发送至硬件基本单元，以供所述硬件基本单元执行第一任务。采用上述技术实现方案，基带芯片采用CPU阵列+软核阵列+硬件基本单元的架构实现码片处理，由于只将码片核心算法在一个硬件基本单元中实现，并通过软 核阵列调度硬件基本单元实现码片处理任务，这样设计的基带芯片的设计难度低，就将基带芯片的设计面积和功耗大大降低了，进而基带芯片的开发周期就降低了。
本领域内的技术人员应明白，本发明的实施例可提供为方法、***、或计算机程序产品。因此，本发明可采用硬件实施例、软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器和光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、设备(***)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
以上所述，仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围。
工业实用性
本发明实施例的方案中，基带芯片包括：CPU阵列、软核阵列和硬件基本单元，所述CPU阵列、软核阵列和硬件基本单元通过总线连接；所述CPU阵列向所述软核阵列发送第一任务，所述第一任务为码片处理任务；所述软核阵列将所述第一任务发送至硬件基本单元；所述硬件基本单元执行第一任务。采用本发明实施实例的方案，即基带芯片采用CPU阵列+软核阵列+硬件基本单元的架构实现码片处理，由于只将码片核心算法在一个硬件基本单元中实现，并通过软核阵列调度硬件基本单元实现码片处理任务，这样设计的基带芯片的设计难度低，基带芯片的设计面积和功耗大大降低了，进而降低了基带芯片的开发周期。

Claims (10)

  1. 一种基带芯片，所述基带芯片包括：中央处理器CPU阵列、软核阵列和硬件基本单元；所述CPU阵列、所述软核阵列和所述硬件基本单元通过总线连接；
    所述CPU阵列，配置为向所述软核阵列发送第一任务，所述第一任务为码片处理任务；
    所述软核阵列，配置为将所述第一任务发送至所述硬件基本单元；
    所述硬件基本单元，配置为执行所述第一任务。
  2. 根据权利要求1所述的基带芯片，其中，
    所述软核阵列，还配置为将所述第一任务发送至所述硬件基本单元之前，将所述第一任务配置为至少一个子任务，形成包括所述至少一个子任务的任务列表。
  3. 根据权利要求2所述的基带芯片，其中，所述基带芯片还包括：直接内存访问DMA和存储器；所述DMA与所述硬件基本单元连接，所述DMA通过所述总线与所述软核阵列连接，所述存储器通过所述总线分别与所述软核阵列和所述硬件基本单元连接；
    所述软核阵列，配置为根据所述任务列表，发送与所述至少一个子任务对应的搬移命令至所述DMA；所述搬移命令用于指示所述DMA发送所述至少一个子任务中的每个子任务至所述硬件基本单元，以及指示在所述硬件基本单元处理完所述每个子任务之后，所述DMA反馈中断至所述软核阵列；
    所述DMA，配置为发送所述每个子任务至所述硬件基本单元；
    所述硬件基本单元，配置为分别执行所述每个子任务，并将所述每个子任务的任务结果存储在存储器中；
    所述DMA，还配置为检测所述硬件基本单元对一个子任务的处理状 态，以及所述处理状态为完成时，发送所述中断至所述软核阵列；
    所述软核阵列，还配置为响应所述中断，从所述存储器中获取所述一个子任务的任务结果，并对获取的子任务的任务结果进行附属功能处理，并将附属功能处理结果存储至所述存储器；
    所述DMA，还配置为将所述存储器中的所述附属功能处理结果上报，以进行符号级或比特级处理。
  4. 根据权利要求3所述的基带芯片，其中，
    所述软核阵列，还配置为发送与所述至少一个子任务对应的搬移命令至所述DMA之前，检测所述硬件基本单元的缓存状态；
    所述软核阵列，还配置为检测到所述硬件基本单元的缓存状态为空闲时，发送与所述至少一个子任务对应的搬移命令至所述DMA。
  5. 根据权利要求2至4任一项所述的基带芯片，其中，所述软核阵列中包括随机存取存储器RAM和先入先出队列FIFO存储器；所述至少一个子任务包括所述至少一个子任务请求和所述至少一个子任务参数；
    所述FIFO存储器，配置为存储所述至少一个子任务请求；
    所述RAM，配置为存储所述至少一个子任务参数。
  6. 一种信号处理方法，所述方法包括：
    软核阵列接收CPU阵列发送的第一任务，所述第一任务为码片处理任务；
    所述软核阵列将所述第一任务发送至硬件基本单元；
    所述硬件基本单元执行所述第一任务。
  7. 根据权利要求6所述的方法，其中，所述软核阵列将所述第一任务发送至硬件基本单元之前，所述方法还包括：
    所述软核阵列将所述第一任务配置为至少一个子任务，形成包括所述至少一个子任务的任务列表；
    相应地，所述软核阵列将所述第一任务发送至硬件基本单元，包括：
    所述软核阵列根据所述任务列表，发送与所述至少一个子任务对应的搬移命令至DMA，以供所述DMA发送所述每个子任务至所述硬件基本单元；所述搬移命令用于指示所述DMA发送所述至少一个子任务中的每个子任务至所述硬件基本单元，以及指示在所述硬件基本单元处理完所述每个子任务之后，所述DMA反馈中断；
    所述硬件基本单元执行所述第一任务，包括：
    所述硬件基本单元分别执行所述每个子任务，并将所述每个子任务的任务结果存储在存储器中。
  8. 根据权利要求7所述的方法，其中，所述发送与所述至少一个子任务对应的搬移命令至所述DMA之后，所述方法还包括：
    所述DMA检测所述硬件基本单元对一个子任务的处理状态，以及所述处理状态为完成时，所述软核阵列接收所述DMA发送的所述中断；
    所述软核阵列响应所述中断，从所述存储器中获取所述一个子任务的任务结果，并对所述一个子任务的任务结果进行附属功能处理，并将附属功能处理结果存储至所述存储器，供所述DMA将所述存储器中的所述附属功能处理结果上报，以进行符号级或比特级处理。
  9. 根据权利要求7或8所述的方法，其中，所述软核阵列根据所述任务列表，发送与所述至少一个子任务对应的搬移命令至所述DMA之前，所述方法还包括：
    所述软核阵列检测所述硬件基本单元的缓存状态。
  10. 根据权利要求9所述的方法，其中，所述软核阵列根据所述任务列表，发送与所述至少一个子任务对应的搬移命令至所述DMA，包括：
    所述软核阵列检测到所述硬件基本单元的缓存状态为空闲时，根据所述任务列表，发送与所述至少一个子任务对应的搬移命令至所述DMA。
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