WO2017020380A1 - Clipping circuit, liquid crystal display with the clipping circuit, and driving method - Google Patents

Clipping circuit, liquid crystal display with the clipping circuit, and driving method Download PDF

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Publication number
WO2017020380A1
WO2017020380A1 PCT/CN2015/088372 CN2015088372W WO2017020380A1 WO 2017020380 A1 WO2017020380 A1 WO 2017020380A1 CN 2015088372 W CN2015088372 W CN 2015088372W WO 2017020380 A1 WO2017020380 A1 WO 2017020380A1
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WO
WIPO (PCT)
Prior art keywords
type mos
mos transistor
rising edge
potential transfer
clock signal
Prior art date
Application number
PCT/CN2015/088372
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French (fr)
Chinese (zh)
Inventor
张华�
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深圳市华星光电技术有限公司
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Priority to US14/783,407 priority Critical patent/US9824663B2/en
Publication of WO2017020380A1 publication Critical patent/WO2017020380A1/en

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2203/00—Function characteristic
    • G02F2203/26—Pulse shaping; Apparatus or methods therefor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/066—Waveforms comprising a gently increasing or decreasing portion, e.g. ramp
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a chamfering circuit, a liquid crystal display device having the same, and a driving method.
  • the scan line is used to transmit a scan signal to the thin film transistor to open the thin film transistor
  • the data line is used to transmit a data signal to the pixel unit when the thin film transistor is turned on to charge the pixel unit, thereby controlling the pixel.
  • the display of the unit the pixel unit displays colors R (red, Red), G (green, Green), and B (blue, blue), respectively.
  • FIG. 1 is a waveform diagram of a scanning signal input to both sides and an intermediate position of the same panel in the prior art.
  • 2 and 3 are schematic diagrams showing the structure of a liquid crystal display device and a timing signal control waveform of a scan signal.
  • the rising edge of the scan signal is triggered by the rising edge of the first clock signal, and the rising edge of the second clock signal is triggered.
  • the falling edge of the scan signal As shown in FIG. 1 , in the prior art liquid crystal display device, due to the influence of resistance and capacitance, the original normal scanning signal is deformed, resulting in scanning signal waveforms (such as waveform A) on both sides of the panel and intermediate positions.
  • the difference of the scanning signal waveform (such as waveform B) is obvious, which causes a large difference in the time when all the thin film transistors in each row are turned on, and panel display difference occurs, which seriously affects the display quality of the TFT-LCD.
  • the technical problem to be solved by the present invention is to provide a chamfering circuit, a liquid crystal display device having the same, and a driving method, which can reduce the waveform difference of the scanning signals on both sides of the panel and the intermediate position, thereby improving the display quality of the liquid crystal display device.
  • a technical solution adopted by the present invention is to provide a liquid crystal display device including: a pixel unit; a data line for transmitting a data signal to the pixel unit; and a clock signal generating chip for generating the first a second clock signal; a chamfering circuit, connected to the clock signal generating chip, for receiving the first and second clock signals, and outputting a rising edge chamfering scan signal according to the first and second clock signals; scanning A line for transmitting the chamfered scan signal to the pixel unit.
  • the pixel unit comprises a thin film transistor and a pixel electrode
  • the thin film transistor comprises a gate, a source and a drain
  • the pixel electrode is connected to the drain
  • the scan line is connected to the gate to transmit the chamfered scan signal to the gate, thereby controlling
  • the thin film transistor is turned on, and the data line is connected to the source to transmit a data signal to the pixel electrode through the source when the thin film transistor is turned on.
  • the rising edge of the scan signal after the chamfer is inclined into an inclined portion.
  • the inclined portion rises from a low level of the scan signal to a high level of the scan signal.
  • the chamfering circuit includes a potential transfer chip, a resistor and a capacitor, the first input pin of the potential transfer chip is configured to receive the first clock signal, and the second input pin of the potential transfer chip is used. Receiving the second clock signal, the scan signal output pin of the potential transfer chip is configured to output a scan signal to the scan line, and the delay pin of the potential transfer chip is grounded through the resistor and the capacitor in sequence .
  • the potential transfer chip includes a first rising edge detection circuit, a falling edge detection circuit, a second rising edge detection circuit, first to third N-type MOS transistors, a first voltage generator, and a second a voltage generator, an output voltage of the first voltage generator is greater than an output voltage of the second voltage generator, and an input end of the first rising edge detection circuit is connected to the first input pin, An output end of a rising edge detecting circuit is connected to a gate of the first N-type MOS transistor, a drain of the first N-type MOS transistor is connected to a delay pin of the potential transfer chip, and a source of the first N-type MOS transistor a pole is connected to the scan signal output pin of the potential transfer chip, an input end of the falling edge detection circuit is connected to the first input pin, and an output end of the falling edge detection circuit is connected to the second N type a gate of the MOS transistor, a drain of the second N-type MOS transistor is connected to the first voltage generator, and a source of the second N-type MOS transistor is connected to
  • the front rake angle of the output scan signal is controlled by adjusting the time from the rising edge to the falling edge of the first clock signal.
  • a chamfering circuit including a potential transfer chip, a resistor and a capacitor, and the first input pin of the potential transfer chip is configured to receive a a first clock signal, a second input pin of the potential transfer chip is configured to receive a second clock signal, and scan signal output pins of the potential transfer chip are respectively used to output a scan signal, and the delay of the potential transfer chip The pin is grounded through the resistor and the capacitor in sequence.
  • the potential transfer chip includes a first rising edge detection circuit, a falling edge detection circuit, a second rising edge detection circuit, first to third N-type MOS transistors, a first voltage generator, and a second a voltage generator, an output voltage of the first voltage generator is greater than an output voltage of the second voltage generator, and an input end of the first rising edge detection circuit is connected to the first input pin, An output end of a rising edge detecting circuit is connected to a gate of the first N-type MOS transistor, a drain of the first N-type MOS transistor is connected to a delay pin of the potential transfer chip, and a source of the first N-type MOS transistor a pole is connected to the scan signal output pin of the potential transfer chip, an input end of the falling edge detection circuit is connected to the first input pin, and an output end of the falling edge detection circuit is connected to the second N type a gate of the MOS transistor, a drain of the second N-type MOS transistor is connected to the first voltage generator, and a source of the second N-type MOS transistor is connected to
  • another technical solution adopted by the present invention is to provide a driving method of a liquid crystal display device, comprising: providing a scan signal; chamfering a rising edge of the scan signal; and transmitting the scan signal after the chamfering To the scan line.
  • the liquid crystal display device of the present invention chamfers the rising edge of the scan signal by using a chamfering circuit, and then transmits the chamfered scan signal to the pixel by using the scan line.
  • the unit reduces the waveform difference of the scanning signals on both sides of the panel and the intermediate position, thereby improving the display quality of the display device.
  • 1 is a waveform diagram of scanning signals input to both sides and intermediate positions of the same panel in the prior art
  • FIG. 2 is a schematic structural view of a liquid crystal display device in the prior art
  • FIG. 3 is a waveform diagram of a timing signal control of a scanning signal in the prior art
  • FIG. 4 is a schematic structural view of a liquid crystal display device of the present invention.
  • Figure 5 is a circuit diagram of a chamfering circuit of the present invention.
  • Figure 6 is a waveform diagram of a scan signal after chamfering according to the present invention.
  • Fig. 7 is a flow chart showing a method of driving the liquid crystal display device of the present invention.
  • FIG. 4 is a schematic structural view of a liquid crystal display device of the present invention.
  • the liquid crystal display device 20 of the present invention includes a plurality of pixel units 21, a clock signal generating chip 22, a chamfering circuit 23, a data driver 24, a plurality of scanning lines A, and a plurality of data lines C.
  • the data driver 24 is used to generate a data signal.
  • the data line C is connected to the data driver 24 for transmitting the data signal to the pixel unit 21.
  • the clock signal generating chip 22 is for generating a first clock signal and a second clock signal.
  • the chamfering circuit 23 is connected to the clock signal generating chip 22 for receiving the first and second clock signals and chamfering the rising edge of the scanning signal according to the first and second clock signals.
  • the scanning line A is connected to the chamfering circuit 23 for transmitting the chamfered scanning signal to the pixel unit 21.
  • the pixel unit 21 includes a thin film transistor T and a pixel electrode P, and the thin film transistor T includes a gate G0, a source S0, and a drain D0.
  • the pixel electrode P is connected to the drain D0, and the scan line A is connected to the gate G0 to transmit the chamfered scan signal to the gate G0, thereby controlling the thin film transistor T to be turned on, and the data line C is connected to the source S0 to When the thin film transistor T is turned on, the data signal is transmitted to the pixel electrode P via the source S0.
  • the same scanning line A drives a plurality of pixel units 21, and the plurality of pixel units 21 respectively display colors G, R, and B as shown in FIG.
  • the scan line A transmits the scan signal
  • the thin film transistors T of the plurality of pixel units 21 driven by the same scan line A are turned on.
  • the plurality of data lines C simultaneously transmit the data signals to the pixel electrodes in the corresponding pixel unit 21. P, to charge the pixel unit 21 that displays different colors.
  • the scanning signal is chamfered by the chamfering circuit 23, and the specific chamfering circuit 23 is as shown in FIG.
  • the chamfering circuit 23 includes a potential transfer chip 30, a resistor R and a capacitor C.
  • the first input pin 1 of the potential transfer chip 30 is for receiving the first clock signal
  • the second input pin 2 of the potential transfer chip 30 is for receiving the second clock signal
  • the potential transfer The scan signal output pin 4 of the chip 30 is used to output the scan signal CK1 to the scan line A
  • the delay pin 3 of the potential transfer chip 30 is grounded via the resistor R and the capacitor C in sequence.
  • the chamfering circuit 23 outputs a plurality of scanning signals, such as CK1-CK4, and only the scanning signal CK1 is taken as an example.
  • the potential transfer chip 30 includes a rising edge detecting circuit 31, a falling edge detecting circuit 32, a rising edge detecting circuit 33, first to third N-type MOS transistors Q1-Q3, a first voltage generator 35, and a second Voltage generator 36.
  • the output voltage of the first voltage generator 35 is greater than the output voltage of the second voltage generator 36.
  • the input end of the rising edge detecting circuit 31 is connected to the first input pin 1, and the output end of the rising edge detecting circuit 31 is connected to the gate of the N-type MOS transistor Q1, the N-type MOS transistor
  • the drain of Q1 is connected to the delay pin 3 of the potential transfer chip 30, and the source of the N-type MOS transistor Q1 is connected to the scan signal output pin 4 of the potential transfer chip 30, and the input of the falling edge detection circuit 32
  • the first input pin 1 is connected to the first input pin 1
  • the output end of the falling edge detecting circuit 32 is connected to the gate of the N-type MOS transistor Q2, and the drain of the N-type MOS transistor Q2 is connected to the first voltage.
  • a source of the N-type MOS transistor Q2 is connected to a source of the N-type MOS transistor Q1 and a scan signal output pin 4 of the potential transfer chip 30, and an input of the rising edge detection circuit 33
  • the second input pin 2 is connected to the second input pin 2
  • the output end of the rising edge detecting circuit 33 is connected to the gate of the N-type MOS transistor Q3, and the drain of the N-type MOS transistor Q3 is connected to the second voltage.
  • the first to third N-type MOS transistors Q1-Q3 may also be other types of electronic switches, such as a triode or a P-type MOS transistor.
  • the N-type MOS transistors Q1 and Q2 are both When the N-type MOS transistor Q3 is turned off, the scan signal CK1 outputted by the scan signal output pin 4 of the potential transfer chip 30 is connected in parallel with the resistor R and the capacitor C. The first voltage generator 35 is turned on.
  • the output voltage charges the capacitor C through the resistor R, at which time the rising edge of the scan signal CK1 rises slowly; when the clock signal generating chip 22 outputs the first clock signal and does not output the second clock signal, and When the first clock signal is at a falling edge level, the N-type MOS transistor Q1 is turned off, the N-type MOS transistor Q2 continues to be turned on, and the N-type MOS transistor Q3 continues to be turned off, at which time the scan signal CK1 is directly Connected to the first voltage generator 35 for receiving a stable high voltage; when the clock signal generating chip 22 outputs a second clock signal and does not output a first clock signal, and the second clock signal is a rising edge Usually, the N type The MOS transistors Q1 and Q2 are both turned off, and the N-type MOS transistor Q3 is turned on. At this time, the scan signal CK1 is directly connected to the second voltage generator 36 for receiving a stable low voltage.
  • FIG. 6 is a waveform diagram of signals received and outputted by the chamfering circuit 23.
  • the first and second clock signals output by the clock signal generating chip 22 are supplied to the chamfering circuit 23 and passed through the chamfering circuit 23 to obtain the chamfered scanning signals CK1-CK4.
  • the rising edges of the chamfered scanning signals CK1-CK4 are both inclined to an inclined portion, and the inclined portion is ramped from a low level to a high level of the chamfered scanning signals CK1-CK4.
  • the front chamfering inclination of each of the scanning signals CK1-CK4 is controlled by adjusting the time from the rising edge to the falling edge of the first clock signal.
  • the chamfering circuit 23 only chamfers the rising edge of the scanning signals CK1-CK4, and therefore, the high level and the low level of the chamfered scanning signals CK1-CK4 are respectively higher than the scanning signals CK1-CK4. The level is equal to the low level.
  • the waveforms of the rising edges of the scanning signals CK1-CK4 after each chamfer are similar or identical, so that the time for opening each of the thin film transistors T is close or equal, so that the pixel electrodes P in each of the pixel units 21 are charged.
  • the voltages are similar or equal, and therefore, the brightness of the colors displayed by each of the pixel units 21 is ensured to be similar or the same, thereby reducing the color shift phenomenon and improving the display quality of the display device.
  • FIG. 7 is a flowchart of a driving method of the liquid crystal display device of the present invention.
  • the driving method includes:
  • Step S61 providing a scan signal
  • Step S62 chamfering the rising edge of the scan signal
  • Step S63 The chamfered scan signal is transmitted to the scan line.
  • step S63 the scan line transmits the chamfered scan signal to the gate of the thin film transistor to turn on the thin film transistor.
  • the data line transmits the data signal to the source of the thin film transistor, and is further transported to the pixel electrode through the source of the thin film transistor, and the pixel electrode performs color display according to the received data signal. Since the present invention chamfers the rising edge of the scanning signal, the time for opening each of the thin film transistors is similar or equal, so that the voltages of the pixel electrodes charged in each pixel unit are close or equal, thus ensuring each The brightness of the colors displayed by the pixel unit is similar or the same, thereby reducing the color shift phenomenon and improving the display quality of the display device.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Nonlinear Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

Provided are a clipping circuit, a liquid crystal display with the clipping circuit, and a driving method. The liquid crystal display (20) comprises: a pixel unit (21); a data line (C), used for transmitting a data signal to the pixel unit (21); a clock signal generation chip (22), used for generating a first clock signal and a second clock signal; a clipping circuit (23), connected to the clock signal generation chip (22) and used for: receiving the first clock signal and the second clock signal, and outputting, according to the first clock signal and the second clock signal, a scanning signal whose rising edge is clipped; and a scanning line (A), used for transmitting the scanning signal obtained after clipping to the pixel unit (21). According to the driving method, a waveform difference between scanning signals on two sides and a middle position of a panel can be lowered, thereby improving the display quality of a liquid crystal display.

Description

削角电路、具有该电路的液晶显示装置及驱动方法 Chamfer circuit, liquid crystal display device having the same, and driving method
【技术领域】[Technical Field]
本发明涉及显示技术领域，特别是涉及一种削角电路、具有该电路的液晶显示装置及驱动方法。The present invention relates to the field of display technologies, and in particular, to a chamfering circuit, a liquid crystal display device having the same, and a driving method.
【背景技术】 【Background technique】
目前在薄膜晶体管液晶显示装置（Thin Film Transistor-Liquid Crystal Display，TFT-LCD）中，扫描线用于传输扫描信号到薄膜晶体管中，以打开薄膜晶体管，数据线用于在薄膜晶体管打开时传输数据信号到像素单元，以向像素单元充电，从而控制像素单元的显示。其中，像素单元分别显示颜色R（红色，Red）、G（绿色，Green）以及B（蓝色，Blue）。Currently in thin film transistor liquid crystal display device (Thin Film Transistor-Liquid Crystal In Display, TFT-LCD, the scan line is used to transmit a scan signal to the thin film transistor to open the thin film transistor, and the data line is used to transmit a data signal to the pixel unit when the thin film transistor is turned on to charge the pixel unit, thereby controlling the pixel. The display of the unit. Among them, the pixel unit displays colors R (red, Red), G (green, Green), and B (blue, blue), respectively.
请参阅图1，是现有技术中输入同一面板两侧与中间位置的扫描信号的波形图。图2及图3是现有技术中的液晶显示装置的结构示意图及扫描信号时序控制波形图，其通过第一时钟信号的上升沿触发扫描信号的上升沿，通过第二时钟信号的上升沿触发扫描信号的下降沿。如图1所示，现有技术的液晶显示装置中，扫描信号由于电阻和电容的影响，原本正常的扫描信号会发生变形，导致面板两侧的扫描信号波形（如波形A）与中间位置的扫描信号波形（如波形B）差异明显，这样会导致每一行的所有薄膜晶体管导通的时间存在较大差异，出现面板显示差异，严重影响TFT-LCD的显示品质。Please refer to FIG. 1 , which is a waveform diagram of a scanning signal input to both sides and an intermediate position of the same panel in the prior art. 2 and 3 are schematic diagrams showing the structure of a liquid crystal display device and a timing signal control waveform of a scan signal. The rising edge of the scan signal is triggered by the rising edge of the first clock signal, and the rising edge of the second clock signal is triggered. The falling edge of the scan signal. As shown in FIG. 1 , in the prior art liquid crystal display device, due to the influence of resistance and capacitance, the original normal scanning signal is deformed, resulting in scanning signal waveforms (such as waveform A) on both sides of the panel and intermediate positions. The difference of the scanning signal waveform (such as waveform B) is obvious, which causes a large difference in the time when all the thin film transistors in each row are turned on, and panel display difference occurs, which seriously affects the display quality of the TFT-LCD.
【发明内容】 [Summary of the Invention]
本发明主要解决的技术问题是提供一种削角电路、具有该电路的液晶显示装置及驱动方法，能够降低面板两侧与中间位置的扫描信号的波形差异，从而提高液晶显示装置的显示品质。The technical problem to be solved by the present invention is to provide a chamfering circuit, a liquid crystal display device having the same, and a driving method, which can reduce the waveform difference of the scanning signals on both sides of the panel and the intermediate position, thereby improving the display quality of the liquid crystal display device.
为解决上述技术问题，本发明采用的一个技术方案是：提供一种液晶显示装置，包括：像素单元；数据线，用于传输数据信号至像素单元；时钟信号产生芯片，用于产生第一及第二时钟信号；削角电路，与时钟信号产生芯片连接，用于接收所述第一及第二时钟信号，并根据所述第一及第二时钟信号输出上升沿削角的扫描信号；扫描线，用于将削角后的扫描信号传输至像素单元。In order to solve the above technical problem, a technical solution adopted by the present invention is to provide a liquid crystal display device including: a pixel unit; a data line for transmitting a data signal to the pixel unit; and a clock signal generating chip for generating the first a second clock signal; a chamfering circuit, connected to the clock signal generating chip, for receiving the first and second clock signals, and outputting a rising edge chamfering scan signal according to the first and second clock signals; scanning A line for transmitting the chamfered scan signal to the pixel unit.
其中，像素单元包括薄膜晶体管和像素电极，薄膜晶体管包括栅极、源极和漏极，像素电极连接漏极，扫描线连接栅极，以将削角后的扫描信号传输至栅极，进而控制薄膜晶体管导通，数据线连接源极，以在薄膜晶体管导通时经源极传输数据信号至像素电极。Wherein, the pixel unit comprises a thin film transistor and a pixel electrode, the thin film transistor comprises a gate, a source and a drain, the pixel electrode is connected to the drain, and the scan line is connected to the gate to transmit the chamfered scan signal to the gate, thereby controlling The thin film transistor is turned on, and the data line is connected to the source to transmit a data signal to the pixel electrode through the source when the thin film transistor is turned on.
其中，削角后的扫描信号的上升沿倾斜成一倾斜部。The rising edge of the scan signal after the chamfer is inclined into an inclined portion.
其中，所述倾斜部从所述扫描信号的低电平倾斜上升至所述扫描信号的高电平。Wherein the inclined portion rises from a low level of the scan signal to a high level of the scan signal.
其中，削角电路包括一电位转移芯片、一电阻及一电容，所述电位转移芯片的第一输入引脚用于接收所述第一时钟信号，所述电位转移芯片的第二输入引脚用于接收所述第二时钟信号，所述电位转移芯片的扫描信号输出引脚用于输出扫描信号给所述扫描线，所述电位转移芯片的延迟引脚依次经所述电阻及所述电容接地。The chamfering circuit includes a potential transfer chip, a resistor and a capacitor, the first input pin of the potential transfer chip is configured to receive the first clock signal, and the second input pin of the potential transfer chip is used. Receiving the second clock signal, the scan signal output pin of the potential transfer chip is configured to output a scan signal to the scan line, and the delay pin of the potential transfer chip is grounded through the resistor and the capacitor in sequence .
其中，所述电位转移芯片包括第一上升沿侦测电路、下降沿侦测电路、第二上升沿侦测电路、第一至第三N型MOS管、一第一电压发生器及一第二电压发生器，所述第一电压发生器的输出电压大于所述第二电压发生器的输出电压，所述第一上升沿侦测电路的输入端连接所述第一输入引脚，所述第一上升沿侦测电路的输出端连接所述第一N型MOS管的栅极，第一N型MOS管的漏极连接所述电位转移芯片的延迟引脚，第一N型MOS管的源极连接所述电位转移芯片的扫描信号输出引脚，所述下降沿侦测电路的输入端连接所述第一输入引脚，所述下降沿侦测电路的输出端连接所述第二N型MOS管的栅极，所述第二N型MOS管的漏极连接所述第一电压发生器，所述第二N型MOS管的源极连接所述第一N型MOS管的源极及所述电位转移芯片的扫描信号输出引脚，所述第二上升沿侦测电路的输入端连接所述第二输入引脚，所述第二上升沿侦测电路的输出端连接所述第三N型MOS管的栅极，所述第三N型MOS管的漏极连接所述第二电压发生器，所述第三N型MOS管的源极连接所述第一N型MOS管的源极、所述第二N型MOS管的源极及所述电位转移芯片的扫描信号输出引脚，所述第一上升沿侦测电路与所述下降沿侦测电路连接，所述下降沿侦测电路与所述第二上升沿侦测电路连接。The potential transfer chip includes a first rising edge detection circuit, a falling edge detection circuit, a second rising edge detection circuit, first to third N-type MOS transistors, a first voltage generator, and a second a voltage generator, an output voltage of the first voltage generator is greater than an output voltage of the second voltage generator, and an input end of the first rising edge detection circuit is connected to the first input pin, An output end of a rising edge detecting circuit is connected to a gate of the first N-type MOS transistor, a drain of the first N-type MOS transistor is connected to a delay pin of the potential transfer chip, and a source of the first N-type MOS transistor a pole is connected to the scan signal output pin of the potential transfer chip, an input end of the falling edge detection circuit is connected to the first input pin, and an output end of the falling edge detection circuit is connected to the second N type a gate of the MOS transistor, a drain of the second N-type MOS transistor is connected to the first voltage generator, and a source of the second N-type MOS transistor is connected to a source of the first N-type MOS transistor a scan signal output pin of the potential transfer chip, and a second rising edge detection circuit The second input pin is connected to the input terminal, the output end of the second rising edge detecting circuit is connected to the gate of the third N-type MOS transistor, and the drain of the third N-type MOS transistor is connected to the a second voltage generator, a source of the third N-type MOS transistor is connected to a source of the first N-type MOS transistor, a source of the second N-type MOS transistor, and a scan signal of the potential transfer chip An output pin, the first rising edge detection circuit is connected to the falling edge detection circuit, and the falling edge detection circuit is connected to the second rising edge detection circuit.
其中，通过调节所述第一时钟信号的上升沿到下降沿的时间，来控制输出的扫描信号的前削角倾斜度。Wherein, the front rake angle of the output scan signal is controlled by adjusting the time from the rising edge to the falling edge of the first clock signal.
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种削角电路，包括一电位转移芯片、一电阻及一电容，所述电位转移芯片的第一输入引脚用于接收一第一时钟信号，所述电位转移芯片的第二输入引脚用于接收一第二时钟信号，所述电位转移芯片的扫描信号输出引脚分别用于输出扫描信号，所述电位转移芯片的延迟引脚依次经所述电阻及所述电容接地。In order to solve the above technical problem, another technical solution adopted by the present invention is to provide a chamfering circuit including a potential transfer chip, a resistor and a capacitor, and the first input pin of the potential transfer chip is configured to receive a a first clock signal, a second input pin of the potential transfer chip is configured to receive a second clock signal, and scan signal output pins of the potential transfer chip are respectively used to output a scan signal, and the delay of the potential transfer chip The pin is grounded through the resistor and the capacitor in sequence.
其中，所述电位转移芯片包括第一上升沿侦测电路、下降沿侦测电路、第二上升沿侦测电路、第一至第三N型MOS管、一第一电压发生器及一第二电压发生器，所述第一电压发生器的输出电压大于所述第二电压发生器的输出电压，所述第一上升沿侦测电路的输入端连接所述第一输入引脚，所述第一上升沿侦测电路的输出端连接所述第一N型MOS管的栅极，第一N型MOS管的漏极连接所述电位转移芯片的延迟引脚，第一N型MOS管的源极连接所述电位转移芯片的扫描信号输出引脚，所述下降沿侦测电路的输入端连接所述第一输入引脚，所述下降沿侦测电路的输出端连接所述第二N型MOS管的栅极，所述第二N型MOS管的漏极连接所述第一电压发生器，所述第二N型MOS管的源极连接所述第一N型MOS管的源极及所述电位转移芯片的扫描信号输出引脚，所述第二上升沿侦测电路的输入端连接所述第二输入引脚，所述第二上升沿侦测电路的输出端连接所述第三N型MOS管的栅极，所述第三N型MOS管的漏极连接所述第二电压发生器，所述第三N型MOS管的源极连接所述第一N型MOS管的源极、所述第二N型MOS管的源极及所述电位转移芯片的扫描信号输出引脚，所述第一上升沿侦测电路与所述下降沿侦测电路连接，所述下降沿侦测电路与所述第二上升沿侦测电路连接。The potential transfer chip includes a first rising edge detection circuit, a falling edge detection circuit, a second rising edge detection circuit, first to third N-type MOS transistors, a first voltage generator, and a second a voltage generator, an output voltage of the first voltage generator is greater than an output voltage of the second voltage generator, and an input end of the first rising edge detection circuit is connected to the first input pin, An output end of a rising edge detecting circuit is connected to a gate of the first N-type MOS transistor, a drain of the first N-type MOS transistor is connected to a delay pin of the potential transfer chip, and a source of the first N-type MOS transistor a pole is connected to the scan signal output pin of the potential transfer chip, an input end of the falling edge detection circuit is connected to the first input pin, and an output end of the falling edge detection circuit is connected to the second N type a gate of the MOS transistor, a drain of the second N-type MOS transistor is connected to the first voltage generator, and a source of the second N-type MOS transistor is connected to a source of the first N-type MOS transistor a scan signal output pin of the potential transfer chip, and a second rising edge detection circuit The second input pin is connected to the input terminal, the output end of the second rising edge detecting circuit is connected to the gate of the third N-type MOS transistor, and the drain of the third N-type MOS transistor is connected to the a second voltage generator, a source of the third N-type MOS transistor is connected to a source of the first N-type MOS transistor, a source of the second N-type MOS transistor, and a scan signal of the potential transfer chip An output pin, the first rising edge detection circuit is connected to the falling edge detection circuit, and the falling edge detection circuit is connected to the second rising edge detection circuit.
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种液晶显示装置的驱动方法，包括：提供扫描信号；对扫描信号的上升沿进行削角；将削角后的扫描信号传输至扫描线。In order to solve the above technical problem, another technical solution adopted by the present invention is to provide a driving method of a liquid crystal display device, comprising: providing a scan signal; chamfering a rising edge of the scan signal; and transmitting the scan signal after the chamfering To the scan line.
本发明的有益效果是：区别于现有技术的情况，本发明的液晶显示装置通过用削角电路对扫描信号的上升沿进行削角，然后利用扫描线将削角后的扫描信号传输至像素单元，使得面板两侧与中间位置的扫描信号的波形差异减小，以此来提高显示装置的显示品质。The beneficial effects of the present invention are: different from the prior art, the liquid crystal display device of the present invention chamfers the rising edge of the scan signal by using a chamfering circuit, and then transmits the chamfered scan signal to the pixel by using the scan line. The unit reduces the waveform difference of the scanning signals on both sides of the panel and the intermediate position, thereby improving the display quality of the display device.
【附图说明】 [Description of the Drawings]
图1是现有技术中输入同一面板两侧与中间位置扫描信号的波形图；1 is a waveform diagram of scanning signals input to both sides and intermediate positions of the same panel in the prior art;
图2是现有技术中液晶显示装置的结构示意图；2 is a schematic structural view of a liquid crystal display device in the prior art;
图3是现有技术中扫描信号时序控制波形图；3 is a waveform diagram of a timing signal control of a scanning signal in the prior art;
图4是本发明的液晶显示装置的结构示意图；4 is a schematic structural view of a liquid crystal display device of the present invention;
图5是本发明的削角电路的电路图；Figure 5 is a circuit diagram of a chamfering circuit of the present invention;
图6是本发明的削角后的扫描信号的波形图；Figure 6 is a waveform diagram of a scan signal after chamfering according to the present invention;
图7是本发明的液晶显示装置的驱动方法的流程图。Fig. 7 is a flow chart showing a method of driving the liquid crystal display device of the present invention.
【具体实施方式】【detailed description】
请参阅图4，是本发明的液晶显示装置的结构示意图。如图4所示，本发明的液晶显示装置20包括多个像素单元21、时钟信号产生芯片22、削角电路23、数据驱动器24、多条扫描线A以及多条数据线C。其中，数据驱动器24用于产生数据信号。数据线C与数据驱动器24连接，用于传输该数据信号至像素单元21。时钟信号产生芯片22用于产生第一时钟信号及第二时钟信号。削角电路23与时钟信号产生芯片22连接，用于接收第一及第二时钟信号并根据所述第一及第二时钟信号对扫描信号的上升沿进行削角。扫描线A连接削角电路23，用于将削角后的扫描信号传输至像素单元21。Please refer to FIG. 4, which is a schematic structural view of a liquid crystal display device of the present invention. As shown in FIG. 4, the liquid crystal display device 20 of the present invention includes a plurality of pixel units 21, a clock signal generating chip 22, a chamfering circuit 23, a data driver 24, a plurality of scanning lines A, and a plurality of data lines C. Among them, the data driver 24 is used to generate a data signal. The data line C is connected to the data driver 24 for transmitting the data signal to the pixel unit 21. The clock signal generating chip 22 is for generating a first clock signal and a second clock signal. The chamfering circuit 23 is connected to the clock signal generating chip 22 for receiving the first and second clock signals and chamfering the rising edge of the scanning signal according to the first and second clock signals. The scanning line A is connected to the chamfering circuit 23 for transmitting the chamfered scanning signal to the pixel unit 21.
像素单元21包括薄膜晶体管T和像素电极P，薄膜晶体管T包括栅极G0、源极S0和漏极D0。其中，像素电极P连接漏极D0，扫描线A连接栅极G0，以将削角后的扫描信号传输至栅极G0，进而控制薄膜晶体管T导通，数据线C连接源极S0，以在薄膜晶体管T导通时经源极S0传输数据信号至像素电极P。The pixel unit 21 includes a thin film transistor T and a pixel electrode P, and the thin film transistor T includes a gate G0, a source S0, and a drain D0. The pixel electrode P is connected to the drain D0, and the scan line A is connected to the gate G0 to transmit the chamfered scan signal to the gate G0, thereby controlling the thin film transistor T to be turned on, and the data line C is connected to the source S0 to When the thin film transistor T is turned on, the data signal is transmitted to the pixel electrode P via the source S0.
本实施例中，同一条扫描线A驱动多个像素单元21，并且该多个像素单元21分别显示如图2所示的颜色G、R以及B。在扫描线A传输扫描信号时，同一条扫描线A驱动的多个像素单元21的薄膜晶体管T都打开，此时，多条数据线C同时传输数据信号到相应的像素单元21中的像素电极P，以向显示不同颜色的像素单元21进行充电。本实施例中，由于液晶显示装置20中的电阻和电容的影响，使得产生的扫描信号由低电位变化到高电位时产生延迟现象。因此本实施例采用削角电路23对扫描信号进行削角，具体的削角电路23如图5所示。In the present embodiment, the same scanning line A drives a plurality of pixel units 21, and the plurality of pixel units 21 respectively display colors G, R, and B as shown in FIG. When the scan line A transmits the scan signal, the thin film transistors T of the plurality of pixel units 21 driven by the same scan line A are turned on. At this time, the plurality of data lines C simultaneously transmit the data signals to the pixel electrodes in the corresponding pixel unit 21. P, to charge the pixel unit 21 that displays different colors. In the present embodiment, due to the influence of the resistance and the capacitance in the liquid crystal display device 20, a delay phenomenon occurs when the generated scanning signal changes from a low potential to a high potential. Therefore, in this embodiment, the scanning signal is chamfered by the chamfering circuit 23, and the specific chamfering circuit 23 is as shown in FIG.
请参阅图5，所述削角电路23包括一电位转移芯片30、一电阻R及一电容C。所述电位转移芯片30的第一输入引脚1用于接收所述第一时钟信号，所述电位转移芯片30的第二输入引脚2用于接收所述第二时钟信号，所述电位转移芯片30的扫描信号输出引脚4用于输出扫描信号CK1给所述扫描线A，所述电位转移芯片30的延迟引脚3依次经所述电阻R及所述电容C接地。在本实施例中，所述削角电路23输出若干扫描信号，如CK1-CK4，在此仅以扫描信号CK1为例进行说明。Referring to FIG. 5, the chamfering circuit 23 includes a potential transfer chip 30, a resistor R and a capacitor C. The first input pin 1 of the potential transfer chip 30 is for receiving the first clock signal, and the second input pin 2 of the potential transfer chip 30 is for receiving the second clock signal, the potential transfer The scan signal output pin 4 of the chip 30 is used to output the scan signal CK1 to the scan line A, and the delay pin 3 of the potential transfer chip 30 is grounded via the resistor R and the capacitor C in sequence. In the present embodiment, the chamfering circuit 23 outputs a plurality of scanning signals, such as CK1-CK4, and only the scanning signal CK1 is taken as an example.
所述电位转移芯片30包括上升沿侦测电路31、下降沿侦测电路32、上升沿侦测电路33、第一至第三N型MOS管Q1-Q3、第一电压发生器35及第二电压发生器36。其中所述第一电压发生器35的输出电压大于所述第二电压发生器36的输出电压。所述上升沿侦测电路31的输入端连接所述第一输入引脚1，所述上升沿侦测电路31的输出端连接所述N型MOS管Q1的栅极，所述N型MOS管Q1的漏极连接所述电位转移芯片30的延迟引脚3，N型MOS管Q1的源极连接所述电位转移芯片30的扫描信号输出引脚4，所述下降沿侦测电路32的输入端连接所述第一输入引脚1，所述下降沿侦测电路32的输出端连接所述N型MOS管Q2的栅极，所述N型MOS管Q2的漏极连接所述第一电压发生器35，所述N型MOS管Q2的源极连接所述N型MOS管Q1的源极及所述电位转移芯片30的扫描信号输出引脚4，所述上升沿侦测电路33的输入端连接所述第二输入引脚2，所述上升沿侦测电路33的输出端连接所述N型MOS管Q3的栅极，所述N型MOS管Q3的漏极连接所述第二电压发生器36，所述N型MOS管Q3的源极连接所述N型MOS管Q1的源极、所述N型MOS管Q2的源极及所述电位转移芯片30的扫描信号输出引脚4，所述上升沿侦测电路31与所述下降沿侦测电路32连接，所述下降沿侦测电路32与所述上升沿侦测电路33连接。在其他实施例中，所述第一至第三N型MOS管Q1-Q3也可为其他类型的电子开关，如三极管或P型MOS管等。The potential transfer chip 30 includes a rising edge detecting circuit 31, a falling edge detecting circuit 32, a rising edge detecting circuit 33, first to third N-type MOS transistors Q1-Q3, a first voltage generator 35, and a second Voltage generator 36. The output voltage of the first voltage generator 35 is greater than the output voltage of the second voltage generator 36. The input end of the rising edge detecting circuit 31 is connected to the first input pin 1, and the output end of the rising edge detecting circuit 31 is connected to the gate of the N-type MOS transistor Q1, the N-type MOS transistor The drain of Q1 is connected to the delay pin 3 of the potential transfer chip 30, and the source of the N-type MOS transistor Q1 is connected to the scan signal output pin 4 of the potential transfer chip 30, and the input of the falling edge detection circuit 32 The first input pin 1 is connected to the first input pin 1, the output end of the falling edge detecting circuit 32 is connected to the gate of the N-type MOS transistor Q2, and the drain of the N-type MOS transistor Q2 is connected to the first voltage. a generator 35, a source of the N-type MOS transistor Q2 is connected to a source of the N-type MOS transistor Q1 and a scan signal output pin 4 of the potential transfer chip 30, and an input of the rising edge detection circuit 33 The second input pin 2 is connected to the second input pin 2, the output end of the rising edge detecting circuit 33 is connected to the gate of the N-type MOS transistor Q3, and the drain of the N-type MOS transistor Q3 is connected to the second voltage. a generator 36, a source of the N-type MOS transistor Q3 is connected to a source of the N-type MOS transistor Q1, a source of the N-type MOS transistor Q2, and a scan signal of the potential transfer chip 30 Output pin 4, the rising edge detecting circuit 31 is connected to the detection circuit 32 is falling, the falling edge detecting circuit 32 and the rising edge detection circuit 33 is connected. In other embodiments, the first to third N-type MOS transistors Q1-Q3 may also be other types of electronic switches, such as a triode or a P-type MOS transistor.
以下对图4及5所示的削角电路23的工作原理进行详细说明：The working principle of the chamfering circuit 23 shown in FIGS. 4 and 5 will be described in detail below:
在本实施例中，当所述时钟信号产生芯片22输出第一时钟信号且不输出第二时钟信号，并且所述第一时钟信号为上升沿电平时，所述N型MOS管Q1和Q2均导通，所述N型MOS管Q3截止，此时所述电位转移芯片30的扫描信号输出引脚4输出的扫描信号CK1与所述电阻R及电容C并联，所述第一电压发生器35的输出电压通过所述电阻R给所述电容C充电，此时所述扫描信号CK1的上升沿缓慢上升；当所述时钟信号产生芯片22输出第一时钟信号且不输出第二时钟信号，并且所述第一时钟信号为下降沿电平时，所述N型MOS管Q1截止，所述N型MOS管Q2继续导通，所述N型MOS管Q3继续截止，此时所述扫描信号CK1直接连接到所述第一电压发生器35用于接收稳定的高电压；当所述时钟信号产生芯片22输出第二时钟信号且不输出第一时钟信号，并且所述第二时钟信号为上升沿电平时，所述N型 MOS管Q1及Q2均截止，所述N型 MOS管Q3导通，此时所述扫描信号CK1直接连接到所述第二电压发生器36用于接收稳定的低电压。In this embodiment, when the clock signal generating chip 22 outputs the first clock signal and does not output the second clock signal, and the first clock signal is at a rising edge level, the N-type MOS transistors Q1 and Q2 are both When the N-type MOS transistor Q3 is turned off, the scan signal CK1 outputted by the scan signal output pin 4 of the potential transfer chip 30 is connected in parallel with the resistor R and the capacitor C. The first voltage generator 35 is turned on. The output voltage charges the capacitor C through the resistor R, at which time the rising edge of the scan signal CK1 rises slowly; when the clock signal generating chip 22 outputs the first clock signal and does not output the second clock signal, and When the first clock signal is at a falling edge level, the N-type MOS transistor Q1 is turned off, the N-type MOS transistor Q2 continues to be turned on, and the N-type MOS transistor Q3 continues to be turned off, at which time the scan signal CK1 is directly Connected to the first voltage generator 35 for receiving a stable high voltage; when the clock signal generating chip 22 outputs a second clock signal and does not output a first clock signal, and the second clock signal is a rising edge Usually, the N type The MOS transistors Q1 and Q2 are both turned off, and the N-type MOS transistor Q3 is turned on. At this time, the scan signal CK1 is directly connected to the second voltage generator 36 for receiving a stable low voltage.
请一并参阅图6，是所述削角电路23接收和输出的各信号的波形图。其中，时钟信号产生芯片22输出的第一及第二时钟信号给削角电路23并经削角电路23后得到削角后的扫描信号CK1-CK4。本实施例中，削角后的扫描信号CK1-CK4的上升沿均倾斜成一倾斜部，并且该倾斜部从低电平倾斜上升至削角后的扫描信号CK1-CK4的高电平。本实施例通过调节第一时钟信号的上升沿到下降沿的时间，来控制各扫描信号CK1-CK4的前削角倾斜度。具体的，第一时钟信号的上升沿到下降沿的时间越长，各扫描信号CK1-CK4的前削角的倾斜度越小，第一时钟信号的上升沿到下降沿的时间越短，各扫描信号CK1-CK4的前削角的倾斜度越大。Please refer to FIG. 6 together, which is a waveform diagram of signals received and outputted by the chamfering circuit 23. The first and second clock signals output by the clock signal generating chip 22 are supplied to the chamfering circuit 23 and passed through the chamfering circuit 23 to obtain the chamfered scanning signals CK1-CK4. In the present embodiment, the rising edges of the chamfered scanning signals CK1-CK4 are both inclined to an inclined portion, and the inclined portion is ramped from a low level to a high level of the chamfered scanning signals CK1-CK4. In this embodiment, the front chamfering inclination of each of the scanning signals CK1-CK4 is controlled by adjusting the time from the rising edge to the falling edge of the first clock signal. Specifically, the longer the rising edge to the falling edge of the first clock signal is, the smaller the inclination of the front chamfering angle of each scanning signal CK1-CK4 is, and the shorter the time from the rising edge to the falling edge of the first clock signal is The inclination of the front chamfering angle of the scanning signals CK1-CK4 is larger.
值得注意的是，削角电路23只对扫描信号CK1-CK4的上升沿进行削角，因此，削角后的扫描信号CK1-CK4的高电平和低电平分别与扫描信号CK1-CK4的高电平和低电平相等。It should be noted that the chamfering circuit 23 only chamfers the rising edge of the scanning signals CK1-CK4, and therefore, the high level and the low level of the chamfered scanning signals CK1-CK4 are respectively higher than the scanning signals CK1-CK4. The level is equal to the low level.
因此，每个削角之后的扫描信号CK1-CK4的上升沿的波形相似或相同，使得打开每个薄膜晶体管T的时间相近或相等，从而使得充入每个像素单元21中的像素电极P的电压相近或相等，因此，保证了每个像素单元21显示的颜色的亮度相近或相同，从而减小了色偏现象，提高了显示装置的显示品质。Therefore, the waveforms of the rising edges of the scanning signals CK1-CK4 after each chamfer are similar or identical, so that the time for opening each of the thin film transistors T is close or equal, so that the pixel electrodes P in each of the pixel units 21 are charged. The voltages are similar or equal, and therefore, the brightness of the colors displayed by each of the pixel units 21 is ensured to be similar or the same, thereby reducing the color shift phenomenon and improving the display quality of the display device.
请参阅图7，是本发明液晶显示装置的驱动方法的流程图。所述驱动方法包括：Please refer to FIG. 7, which is a flowchart of a driving method of the liquid crystal display device of the present invention. The driving method includes:
步骤S61：提供扫描信号；Step S61: providing a scan signal;
步骤S62：对扫描信号的上升沿进行削角；Step S62: chamfering the rising edge of the scan signal;
步骤S63：将削角后的扫描信号传输至扫描线。Step S63: The chamfered scan signal is transmitted to the scan line.
在步骤S63中，扫描线将削角后的扫描信号传输到薄膜晶体管的栅极，以打开薄膜晶体管。在薄膜晶体管打开时，数据线将数据信号传输到薄膜晶体管的源极，通过薄膜晶体管的源极进一步输送到像素电极，像素电极根据接收到的数据信号进行颜色的显示。因为本发明对扫描信号的上升沿进行了削角，使得打开每个薄膜晶体管的时间相近或相等，从而使得充入每个像素单元中的像素电极的电压相近或相等，因此，保证了每个像素单元显示的颜色的亮度相近或相同，从而减小了色偏现象，提高了显示装置的显示品质。In step S63, the scan line transmits the chamfered scan signal to the gate of the thin film transistor to turn on the thin film transistor. When the thin film transistor is turned on, the data line transmits the data signal to the source of the thin film transistor, and is further transported to the pixel electrode through the source of the thin film transistor, and the pixel electrode performs color display according to the received data signal. Since the present invention chamfers the rising edge of the scanning signal, the time for opening each of the thin film transistors is similar or equal, so that the voltages of the pixel electrodes charged in each pixel unit are close or equal, thus ensuring each The brightness of the colors displayed by the pixel unit is similar or the same, thereby reducing the color shift phenomenon and improving the display quality of the display device.
以上仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。The above is only the embodiment of the present invention, and is not intended to limit the scope of the invention, and the equivalent structure or equivalent process transformation made by the specification and the drawings of the present invention may be directly or indirectly applied to other related technical fields. The same is included in the scope of patent protection of the present invention.

Claims (10)

  1. 一种液晶显示装置，其中，所述液晶显示装置包括：A liquid crystal display device, wherein the liquid crystal display device comprises:
    像素单元；Pixel unit
    数据线，用于传输数据信号至所述像素单元；a data line for transmitting a data signal to the pixel unit;
    时钟信号产生芯片，用于产生第一时钟信号及第二时钟信号；a clock signal generating chip, configured to generate a first clock signal and a second clock signal;
    削角电路，与所述时钟信号产生芯片连接用于接收所述第一时钟信号及所述第二时钟信号，并根据所述第一时钟信号及所述第二时钟信号输出上升沿削角的扫描信号；a chamfering circuit connected to the clock signal generating chip for receiving the first clock signal and the second clock signal, and outputting a rising edge chamfer according to the first clock signal and the second clock signal Scanning signal
    扫描线，用于将削角后的所述扫描信号传输至所述像素单元。a scan line for transmitting the scan signal after the chamfer to the pixel unit.
  2. 根据权利要求1所述的液晶显示装置，其中，所述像素单元包括薄膜晶体管和像素电极，所述薄膜晶体管包括栅极、源极和漏极，所述像素电极连接所述漏极，所述扫描线连接所述栅极，以将削角后的所述扫描信号传输至所述栅极，进而控制所述薄膜晶体管导通，所述数据线连接所述源极，以在所述薄膜晶体管导通时经所述源极传输数据信号至所述像素电极。The liquid crystal display device of claim 1, wherein the pixel unit comprises a thin film transistor including a gate, a source and a drain, and the pixel electrode is connected to the drain, a scan line is connected to the gate to transmit the chamfered scan signal to the gate, thereby controlling the thin film transistor to be turned on, and the data line is connected to the source to be in the thin film transistor A data signal is transmitted to the pixel electrode via the source when turned on.
  3. 根据权利要求1所述的液晶显示装置，其中，削角后的所述扫描信号的上升沿倾斜成一倾斜部。 The liquid crystal display device according to claim 1, wherein a rising edge of said scan signal after chamfering is inclined to an inclined portion.
  4. 根据权利要求3所述的液晶显示装置，其中，所述倾斜部从所述扫描信号的低电平倾斜上升至所述扫描信号的高电平。The liquid crystal display device according to claim 3, wherein the inclined portion rises from a low level of the scan signal to a high level of the scan signal.
  5. 根据权利要求1所述的液晶显示装置，其中，所述削角电路包括一电位转移芯片、一电阻及一电容，所述电位转移芯片的第一输入引脚用于接收所述第一时钟信号，所述电位转移芯片的第二输入引脚用于接收所述第二时钟信号，所述电位转移芯片的扫描信号输出引脚用于输出扫描信号给所述扫描线，所述电位转移芯片的延迟引脚依次经所述电阻及所述电容接地。 The liquid crystal display device of claim 1 , wherein the chamfering circuit comprises a potential transfer chip, a resistor and a capacitor, and the first input pin of the potential transfer chip is configured to receive the first clock signal a second input pin of the potential transfer chip is configured to receive the second clock signal, and a scan signal output pin of the potential transfer chip is configured to output a scan signal to the scan line, where the potential transfer chip The delay pin is grounded through the resistor and the capacitor in sequence.
  6. 根据权利要求5所述的液晶显示装置，其中，所述电位转移芯片包括第一上升沿侦测电路、下降沿侦测电路、第二上升沿侦测电路、第一至第三N型MOS管、一第一电压发生器及一第二电压发生器，所述第一电压发生器的输出电压大于所述第二电压发生器的输出电压，所述第一上升沿侦测电路的输入端连接所述第一输入引脚，所述第一上升沿侦测电路的输出端连接所述第一N型MOS管的栅极，第一N型MOS管的漏极连接所述电位转移芯片的延迟引脚，第一N型MOS管的源极连接所述电位转移芯片的扫描信号输出引脚，所述下降沿侦测电路的输入端连接所述第一输入引脚，所述下降沿侦测电路的输出端连接所述第二N型MOS管的栅极，所述第二N型MOS管的漏极连接所述第一电压发生器，所述第二N型MOS管的源极连接所述第一N型MOS管的源极及所述电位转移芯片的扫描信号输出引脚，所述第二上升沿侦测电路的输入端连接所述第二输入引脚，所述第二上升沿侦测电路的输出端连接所述第三N型MOS管的栅极，所述第三N型MOS管的漏极连接所述第二电压发生器，所述第三N型MOS管的源极连接所述第一N型MOS管的源极、所述第二N型MOS管的源极及所述电位转移芯片的扫描信号输出引脚，所述第一上升沿侦测电路与所述下降沿侦测电路连接，所述下降沿侦测电路与所述第二上升沿侦测电路连接。The liquid crystal display device of claim 5, wherein the potential transfer chip comprises a first rising edge detection circuit, a falling edge detection circuit, a second rising edge detection circuit, and first to third N-type MOS transistors a first voltage generator and a second voltage generator, wherein an output voltage of the first voltage generator is greater than an output voltage of the second voltage generator, and an input end of the first rising edge detection circuit is connected The first input pin, the output end of the first rising edge detecting circuit is connected to the gate of the first N-type MOS transistor, and the drain of the first N-type MOS transistor is connected to the delay of the potential transfer chip a pin, a source of the first N-type MOS transistor is connected to the scan signal output pin of the potential transfer chip, and an input end of the falling edge detection circuit is connected to the first input pin, the falling edge detection An output end of the circuit is connected to a gate of the second N-type MOS transistor, a drain of the second N-type MOS transistor is connected to the first voltage generator, and a source connection of the second N-type MOS transistor a source of the first N-type MOS transistor and a scan signal of the potential transfer chip a pin, an input end of the second rising edge detecting circuit is connected to the second input pin, and an output end of the second rising edge detecting circuit is connected to a gate of the third N-type MOS transistor a drain of the third N-type MOS transistor is connected to the second voltage generator, a source of the third N-type MOS transistor is connected to a source of the first N-type MOS transistor, and the second N-type MOS a source of the tube and a scan signal output pin of the potential transfer chip, the first rising edge detection circuit is connected to the falling edge detection circuit, the falling edge detection circuit and the second rising edge Detect circuit connections.
  7. 根据权利要求8所述的液晶显示装置，其中，通过调节所述第一时钟信号的上升沿到下降沿的时间，来控制输出的扫描信号的前削角倾斜度。The liquid crystal display device according to claim 8, wherein the front chamfering slope of the output scan signal is controlled by adjusting a time from a rising edge to a falling edge of the first clock signal.
  8. 一种削角电路，其中，所述削角电路包括一电位转移芯片、一电阻及一电容，所述电位转移芯片的第一输入引脚用于接收一第一时钟信号，所述电位转移芯片的第二输入引脚用于接收一第二时钟信号，所述电位转移芯片的扫描信号输出引脚分别用于输出扫描信号，所述电位转移芯片的延迟引脚依次经所述电阻及所述电容接地。A chamfering circuit, wherein the chamfering circuit comprises a potential transfer chip, a resistor and a capacitor, and the first input pin of the potential transfer chip is configured to receive a first clock signal, the potential transfer chip The second input pin is configured to receive a second clock signal, the scan signal output pins of the potential transfer chip are respectively used to output a scan signal, and the delay pin of the potential transfer chip is sequentially passed through the resistor and the The capacitor is grounded.
  9. 根据权利要求8所述的削角电路，其中，所述电位转移芯片包括第一上升沿侦测电路、下降沿侦测电路、第二上升沿侦测电路、第一至第三N型MOS管、一第一电压发生器及一第二电压发生器，所述第一电压发生器的输出电压大于所述第二电压发生器的输出电压，所述第一上升沿侦测电路的输入端连接所述第一输入引脚，所述第一上升沿侦测电路的输出端连接所述第一N型MOS管的栅极，第一N型MOS管的漏极连接所述电位转移芯片的延迟引脚，第一N型MOS管的源极连接所述电位转移芯片的扫描信号输出引脚，所述下降沿侦测电路的输入端连接所述第一输入引脚，所述下降沿侦测电路的输出端连接所述第二N型MOS管的栅极，所述第二N型MOS管的漏极连接所述第一电压发生器，所述第二N型MOS管的源极连接所述第一N型MOS管的源极及所述电位转移芯片的扫描信号输出引脚，所述第二上升沿侦测电路的输入端连接所述第二输入引脚，所述第二上升沿侦测电路的输出端连接所述第三N型MOS管的栅极，所述第三N型MOS管的漏极连接所述第二电压发生器，所述第三N型MOS管的源极连接所述第一N型MOS管的源极、所述第二N型MOS管的源极及所述电位转移芯片的扫描信号输出引脚，所述第一上升沿侦测电路与所述下降沿侦测电路连接，所述下降沿侦测电路与所述第二上升沿侦测电路连接。The chamfering circuit according to claim 8, wherein the potential transfer chip comprises a first rising edge detecting circuit, a falling edge detecting circuit, a second rising edge detecting circuit, and first to third N-type MOS transistors a first voltage generator and a second voltage generator, wherein an output voltage of the first voltage generator is greater than an output voltage of the second voltage generator, and an input end of the first rising edge detection circuit is connected The first input pin, the output end of the first rising edge detecting circuit is connected to the gate of the first N-type MOS transistor, and the drain of the first N-type MOS transistor is connected to the delay of the potential transfer chip a pin, a source of the first N-type MOS transistor is connected to the scan signal output pin of the potential transfer chip, and an input end of the falling edge detection circuit is connected to the first input pin, the falling edge detection An output end of the circuit is connected to a gate of the second N-type MOS transistor, a drain of the second N-type MOS transistor is connected to the first voltage generator, and a source connection of the second N-type MOS transistor a source of the first N-type MOS transistor and a scan signal output of the potential transfer chip The input end of the second rising edge detecting circuit is connected to the second input pin, and the output end of the second rising edge detecting circuit is connected to the gate of the third N-type MOS transistor, a drain of the three N-type MOS transistor is connected to the second voltage generator, and a source of the third N-type MOS transistor is connected to a source of the first N-type MOS transistor and a source of the second N-type MOS transistor a source and a scan signal output pin of the potential transfer chip, the first rising edge detection circuit is connected to the falling edge detection circuit, the falling edge detection circuit and the second rising edge detection Circuit connection.
  10. 一种液晶显示装置的驱动方法，所述驱动方法包括： A driving method of a liquid crystal display device, the driving method comprising:
    提供扫描信号；Providing a scan signal;
    对所述扫描信号的上升沿进行削角；Sharpening the rising edge of the scan signal;
    将所述削角后的所述扫描信号传输至扫描线。The chamfered scan signal is transmitted to a scan line.
PCT/CN2015/088372 2015-07-31 2015-08-28 Clipping circuit, liquid crystal display with the clipping circuit, and driving method WO2017020380A1 (en)

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