WO2017020345A1 - Array substrate and manufacturing method therefor - Google Patents

Array substrate and manufacturing method therefor Download PDF

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Publication number
WO2017020345A1
WO2017020345A1 PCT/CN2015/087002 CN2015087002W WO2017020345A1 WO 2017020345 A1 WO2017020345 A1 WO 2017020345A1 CN 2015087002 W CN2015087002 W CN 2015087002W WO 2017020345 A1 WO2017020345 A1 WO 2017020345A1
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Prior art keywords
layer
metal layer
metal
polysilicon layer
array substrate
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PCT/CN2015/087002
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French (fr)
Chinese (zh)
Inventor
王聪
杜鹏
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深圳市华星光电技术有限公司
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Priority to US14/781,536 priority Critical patent/US9899425B2/en
Publication of WO2017020345A1 publication Critical patent/WO2017020345A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
    • H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular, to an array substrate and a method of fabricating the same.
  • the heavily doped region is generally performed by using a metal pattern above the active layer as a mask, and the activation process is usually further performed after the doping is completed.
  • FIG. 1 A schematic diagram of a conventional method for fabricating an array substrate is shown in FIG. 1. After a buffer layer 112 and a polysilicon layer (Poly) 113 are sequentially deposited on a glass substrate 111, exposure, development, etching is performed to a specified pattern, and then excimer laser annealing is performed. (excimer laser annealer, ELA) treatment.
  • ELA excimer laser annealer
  • gate insulater gate insulater , GI
  • first metal layer above the GI layer (Metal 1) 115, and etched into a specified pattern to expose a portion of the Poly layer that needs to be doped, and the first metal layer 115 is used to block the region where the Poly layer 113 does not need to be doped, and is directly doped to form the heavily doped region 116.
  • high temperature activation treatment is performed to form an ohmic contact between the semiconductor layer and the metal layer (Source/Drain), and the thin film transistor is improved (Thin Film Conductivity of Transistor, TFT). The activation temperature is higher.
  • the first metal layer 115 Since the first metal layer 115 has been deposited as a gate on the substrate at this time, the first metal layer 115 is required to have a high temperature resistant material.
  • Depositing an interlayer medium after activation (inter Layer The dielectric, ILD) layer 117 is etched into a designated pattern to expose the Poly layer 113 that needs to be in contact with the metal.
  • a second metal layer (Metal 2) 118 is deposited to form a source/drain electrode.
  • ITO indium tin oxide transparent conductive
  • the metal layer Due to the high activation temperature, the metal layer is required to have high temperature resistance.
  • the metal under the active layer is usually made of molybdenum (Mo), but the metal Mo is used as a conductive metal material, and the resistance is very large. Resistor capacity delay of the fabricated signal line (RC The delay is very serious, affecting the reliability of the screen display, which is not conducive to the large size of the product.
  • the embodiment of the invention provides an array substrate and a manufacturing method thereof, which can reduce the RC delay of the product metal line and realize the large size of the product.
  • a technical solution adopted by the present invention is to provide a method for fabricating an array substrate, comprising: growing a polysilicon layer on a glass substrate; performing heavy doping on both sides of the polysilicon layer and performing activation treatment to form a weight a doped region; a first metal layer is grown on the heavily doped region to form a source/drain; a gate insulating layer and a second metal layer are sequentially grown on the polysilicon layer to form a gate, wherein the second metal layer material is metal aluminum
  • a heavily doped region on both sides of the polysilicon layer is provided with a first metal layer to form a source/drain; and a second passivation layer and a top ITO film are sequentially grown on the second metal layer.
  • the first metal layer on one side of the polysilicon layer is provided with an underlying ITO film.
  • the first metal layer material is metal aluminum.
  • another technical solution adopted by the present invention is to provide a method for fabricating an array substrate, comprising: growing a polysilicon layer on a glass substrate; and heavily doping and performing activation treatment on both sides of the polysilicon layer to form a heavily doped region; a first metal layer is grown on the heavily doped region to form a source/drain; a gate insulating layer and a second metal layer are sequentially grown on the polysilicon layer to form a gate, wherein the second metal layer material is a metal aluminum.
  • the first metal layer is disposed on the heavily doped regions on both sides of the polysilicon layer to form a source/drain.
  • the first metal layer on one side of the polysilicon layer is provided with an underlying ITO film.
  • the first metal layer material is metal aluminum.
  • the passivation layer and the top ITO film are sequentially grown on the second metal layer.
  • an array substrate comprising: a glass substrate; a polysilicon layer disposed on the glass substrate, the two sides of the polysilicon layer being heavily doped regions; The metal layer is disposed on the heavily doped region to form a source/drain; the gate insulating layer and the first metal layer are sequentially disposed on the polysilicon layer, wherein the first metal layer material is metal aluminum to form a gate.
  • a buffer layer is further disposed between the glass substrate and the polysilicon layer.
  • the first metal layer material is metal aluminum.
  • the first metal layer on one side of the polysilicon layer is provided with an underlying ITO film.
  • the heavily doped region is subjected to activation treatment after being heavily doped.
  • the beneficial effects of the present invention are: the present invention forms a heavily doped region by heavily doping and performing activation treatment on both sides of the polysilicon layer by growing a polysilicon layer on the glass substrate; growing on the heavily doped region a first metal layer, forming a source/drain; a gate insulating layer and a second metal layer, which are sequentially disposed on the polysilicon layer, wherein the second metal layer material is metal aluminum, which can reduce the RC delay of the product metal line, and realize the product Large size.
  • FIG. 1 is a schematic view showing a method of fabricating an array substrate in the prior art
  • FIG. 2 is a schematic flow chart of a method for fabricating an array substrate according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of a method for fabricating a polysilicon layer in an array substrate according to an embodiment of the present invention
  • FIG. 4 is a schematic view showing heavy doping in an array substrate according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a method for fabricating a first metal layer in an array substrate according to an embodiment of the invention
  • FIG. 6 is a schematic structural view of an array substrate according to an embodiment of the present invention.
  • FIG. 2 is a schematic flow chart of a method for fabricating an array substrate according to an embodiment of the present invention. As shown in FIG. 2, the method for fabricating the array substrate includes:
  • Step S10 growing a polysilicon layer on the glass substrate.
  • a buffer layer is further grown between the glass substrate and the polysilicon layer.
  • a buffer layer 102 is grown on the glass substrate 101, and then a polysilicon layer 103 is regrown, and the substrate is subjected to ELA treatment, so that the surface layer of the polysilicon layer 103 is crystallized and formed by a mask and etching.
  • Figure 3 shows the shape of a photoresist (Photoresist, PR) of 104.
  • Step S11 Both sides of the polysilicon layer are heavily doped and activated to form a heavily doped region.
  • the remaining photoresist is further subjected to an exposure process to remove the photoresist 104 on the region of the polysilicon layer 103 that needs to be heavily doped, and then the region is heavily doped to form a heavily doped layer. Miscellaneous area 105.
  • the heavily doped region 105 is capable of forming an ohmic contact with the metal.
  • the heavy doping preferably employs an ion implantation method.
  • the photoresist 104 on the polysilicon layer 103 is peeled off after the heavy doping is completed.
  • the heavily doped region 105 is then subjected to an activation treatment. Since the activation temperature is relatively high, it is preferably about 600 ° C, which requires that the layers which have been formed before the activation treatment are resistant to high temperatures. In the embodiment of the present invention, the metal layer has not been formed before the activation treatment of the heavily doped region 105, so that it is not necessary to consider the high temperature resistance of the metal.
  • Step S12 growing a first metal layer on the heavily doped region to form a source/drain.
  • the first metal layer 106 is disposed on the heavily doped regions 105 on both sides of the polysilicon layer 103 to form a source/drain.
  • the heavily doped region 105 is used to form an ohmic contact with the source/drain.
  • An underlying ITO film 107 is disposed on the first metal layer 106 on one side of the polysilicon layer 103.
  • the underlying ITO film 107 is generally disposed on the source as a pixel electrode of the display panel.
  • the material of the first metal layer 106 may also be metal aluminum.
  • Step S13 sequentially growing a gate insulating layer and a second metal layer on the polysilicon layer to form a gate, wherein the second metal layer material is metal aluminum.
  • the gate insulating layer 108 is deposited, and then the second metal layer 109 is deposited on the gate insulating layer 108 directly above the polysilicon layer 103.
  • the second metal layer 109 is made of metallic aluminum and is provided as a gate of the display panel.
  • the passivation layer and the top ITO film are then sequentially applied.
  • the top ITO film is provided as a common electrode of the display panel.
  • the wire load is smaller than that of metal molybdenum, which can effectively reduce the RC caused by metal traces.
  • Delay which improves the reliability of the display panel, is advantageous for the large size of the LTPS display panel.
  • FIG. 6 is a schematic structural view of an array substrate according to an embodiment of the present invention.
  • the array substrate 20 includes a glass substrate 201, a polysilicon layer 202, a gate insulating layer 203, a first metal layer 204, and a second metal layer 205.
  • the polysilicon layer 202 is disposed on the glass substrate 201, and the polysilicon layer 202 is heavily doped regions 206 on both sides; the first metal layer 204 is disposed on the heavily doped region 206 to form a source/drain; the gate insulating layer 203, the second The metal layer 205 is sequentially disposed on the polysilicon layer 202, wherein the second metal layer 205 is made of metal aluminum to form a gate.
  • a buffer layer 207 is further disposed between the glass substrate 201 and the polysilicon layer 202.
  • the material of the first metal layer 204 is metal aluminum.
  • An underlying ITO film 208 is disposed on the first metal layer 204 on one side of the polysilicon layer 202.
  • a passivation layer 209 and a top ITO film 210 are also disposed on the second metal layer 205 in this order.
  • the underlying ITO film 208 is set as the pixel electrode of the display panel, and the top ITO film 210 is set as the common electrode of the display panel.
  • the heavily doped region 206 is subjected to an activation treatment after completion of the heavy doping. Since the activation temperature is relatively high, it is preferably about 600 ° C, which requires that the layers which have been formed before the activation treatment are resistant to high temperatures.
  • the activation process of the heavily doped region 206 in the array substrate of the embodiment of the present invention is performed immediately after the heavy doping. At this time, the first metal layer 204 and the second metal layer 205 are not yet fabricated, so there is no need to consider the metal. High temperature resistance.
  • the material of the first metal layer 204 and/or the second metal layer 205 can be a metal aluminum having a lower resistivity. Compared with the metal molybdenum, the trace load is smaller, and the RC caused by the metal trace can be effectively reduced. Delay, improve the reliability of the display panel.
  • the present invention provides a buffer layer on a glass substrate, the polysilicon layer is disposed on the buffer layer, and the polysilicon layer is heavily doped on both sides, and the heavily doped region is activated after being heavily doped;
  • the insulating layer and the first metal layer are sequentially disposed on the polysilicon layer, wherein the first metal layer material is metal aluminum, which can reduce the RC delay of the product metal line and realize the large size of the product.

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Abstract

An array substrate and a manufacturing method therefor. The method comprises: growing a polysilicon layer (103) on a glass substrate (101); carrying out heavy doping and activation treatment on two sides of the polysilicon layer (103) to form a heavily-doped region (105); growing a first metal layer (106) on the heavily-doped region (105) to form a source/drain; sequentially growing a gate insulator layer (108) and a second metal layer (109) on the polysilicon layer (103) to form a gate, the second metal layer (109) being made of metallic aluminum. In this manner, the activation technological process can be improved; the RC delay of a product metal wire can be reduced, and the large size of the product is realized.

Description

阵列基板及其制作方法 Array substrate and manufacturing method thereof
【技术领域】[Technical Field]
本发明涉及液晶显示技术领域，特别是涉及一种阵列基板及其制作方法。The present invention relates to the field of liquid crystal display technology, and in particular, to an array substrate and a method of fabricating the same.
【背景技术】 【Background technique】
传统的低温多晶硅（Low Temperature Poly-silicon，LTPS）设计中，重掺杂区域一般是利用活性层上方的金属版图（Pattern）作为掩模来进行，掺杂完成之后通常会进一步活化处理。Traditional low temperature polysilicon (Low Temperature) In the design of the poly-silicon (LTPS), the heavily doped region is generally performed by using a metal pattern above the active layer as a mask, and the activation process is usually further performed after the doping is completed.
传统的阵列基板制作方法示意图如图1所示，在玻璃基板111上依次沉积缓冲层112和多晶硅层（Poly）113后，曝光，显影，蚀刻为指定的图案，再进行准分子激光退火 (excimer laser annealer，ELA)处理。然后沉积栅绝缘层（gate insulater ，GI）114，再在GI层上方沉积第一金属层（Metal 1）115，并蚀刻为指定图案，露出Poly层需要掺杂的部分，利用第一金属层115遮挡住Poly层113不需要掺杂的区域，直接掺杂，形成重掺杂区116。重掺杂完成后进行高温活化处理，以实现半导体层与金属层（Source/Drain）形成欧姆接触，提升薄膜晶体管（Thin Film Transistor，TFT）的导电性能。活化的温度较高，由于此时的基板上已经沉积有第一金属层115作为栅极，所以第一金属层115需采用耐高温的材料。活化后沉积一层层间介质（inter layer dielectric，ILD）层117，蚀刻为指定的图案，露出需要与金属接触的Poly层113。再沉积第二金属层（Metal2）118，形成源/漏（Source/Drain）极。之后依次沉积底层氧化铟锡透明导电（Indium tin oxide，ITO）薄膜119、钝化层120以及顶层ITO薄膜121。A schematic diagram of a conventional method for fabricating an array substrate is shown in FIG. 1. After a buffer layer 112 and a polysilicon layer (Poly) 113 are sequentially deposited on a glass substrate 111, exposure, development, etching is performed to a specified pattern, and then excimer laser annealing is performed. (excimer laser annealer, ELA) treatment. Then deposit a gate insulating layer (gate insulater , GI) 114, and then deposit a first metal layer above the GI layer (Metal 1) 115, and etched into a specified pattern to expose a portion of the Poly layer that needs to be doped, and the first metal layer 115 is used to block the region where the Poly layer 113 does not need to be doped, and is directly doped to form the heavily doped region 116. After the heavy doping is completed, high temperature activation treatment is performed to form an ohmic contact between the semiconductor layer and the metal layer (Source/Drain), and the thin film transistor is improved (Thin Film Conductivity of Transistor, TFT). The activation temperature is higher. Since the first metal layer 115 has been deposited as a gate on the substrate at this time, the first metal layer 115 is required to have a high temperature resistant material. Depositing an interlayer medium after activation (inter Layer The dielectric, ILD) layer 117 is etched into a designated pattern to expose the Poly layer 113 that needs to be in contact with the metal. A second metal layer (Metal 2) 118 is deposited to form a source/drain electrode. Subsequent deposition of underlying indium tin oxide transparent conductive (Indium Tin oxide, ITO) film 119, passivation layer 120, and top layer ITO film 121.
由于活化温度较高，所以要求金属层耐高温性能较强，一般在活性层下方的金属通常采用金属钼（Molybdenum，Mo）来制作，但是金属Mo作为导电金属材料，电阻非常大，由金属Mo制成的信号线的阻容延迟（RC delay）很严重，影响画面显示的信赖性，不利于产品的大尺寸化。Due to the high activation temperature, the metal layer is required to have high temperature resistance. Generally, the metal under the active layer is usually made of molybdenum (Mo), but the metal Mo is used as a conductive metal material, and the resistance is very large. Resistor capacity delay of the fabricated signal line (RC The delay is very serious, affecting the reliability of the screen display, which is not conducive to the large size of the product.
【发明内容】 [Summary of the Invention]
本发明实施例提供了一种阵列基板及其制作方法，能够减小产品金属线的RC延迟，实现产品的大尺寸化。The embodiment of the invention provides an array substrate and a manufacturing method thereof, which can reduce the RC delay of the product metal line and realize the large size of the product.
为解决上述技术问题，本发明采用的一个技术方案是：提供一种阵列基板的制作方法，包括：在玻璃基板上生长多晶硅层；对多晶硅层两侧进行重掺杂并进行活化处理，形成重掺杂区；在重掺杂区上生长第一金属层，形成源/漏极；在多晶硅层上依次生长栅绝缘层和第二金属层，形成栅极，其中第二金属层材料为金属铝；其中，多晶硅层的两侧的重掺杂区上设置有第一金属层，形成源/漏极；第二金属层上还依次生长有钝化层和顶层ITO薄膜。In order to solve the above technical problem, a technical solution adopted by the present invention is to provide a method for fabricating an array substrate, comprising: growing a polysilicon layer on a glass substrate; performing heavy doping on both sides of the polysilicon layer and performing activation treatment to form a weight a doped region; a first metal layer is grown on the heavily doped region to form a source/drain; a gate insulating layer and a second metal layer are sequentially grown on the polysilicon layer to form a gate, wherein the second metal layer material is metal aluminum Wherein, a heavily doped region on both sides of the polysilicon layer is provided with a first metal layer to form a source/drain; and a second passivation layer and a top ITO film are sequentially grown on the second metal layer.
其中，多晶硅层的其中一侧的第一金属层上设置有底层ITO薄膜。Wherein, the first metal layer on one side of the polysilicon layer is provided with an underlying ITO film.
其中，第一金属层材料为金属铝。Wherein, the first metal layer material is metal aluminum.
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种阵列基板的制作方法，包括：在玻璃基板上生长多晶硅层；对多晶硅层两侧进行重掺杂并进行活化处理，形成重掺杂区；在重掺杂区上生长第一金属层，形成源/漏极；在多晶硅层上依次生长栅绝缘层和第二金属层，形成栅极，其中第二金属层材料为金属铝。In order to solve the above technical problem, another technical solution adopted by the present invention is to provide a method for fabricating an array substrate, comprising: growing a polysilicon layer on a glass substrate; and heavily doping and performing activation treatment on both sides of the polysilicon layer to form a heavily doped region; a first metal layer is grown on the heavily doped region to form a source/drain; a gate insulating layer and a second metal layer are sequentially grown on the polysilicon layer to form a gate, wherein the second metal layer material is a metal aluminum.
其中，多晶硅层的两侧的重掺杂区上设置有第一金属层，形成源/漏极。Wherein, the first metal layer is disposed on the heavily doped regions on both sides of the polysilicon layer to form a source/drain.
其中，多晶硅层的其中一侧的第一金属层上设置有底层ITO薄膜。Wherein, the first metal layer on one side of the polysilicon layer is provided with an underlying ITO film.
其中，第一金属层材料为金属铝。Wherein, the first metal layer material is metal aluminum.
其中，第二金属层上还依次生长有钝化层和顶层ITO薄膜。The passivation layer and the top ITO film are sequentially grown on the second metal layer.
为解决上述技术问题，本发明采用的又一个技术方案是：还提供一种阵列基板，包括：玻璃基板；多晶硅层，设置在玻璃基板上，多晶硅层的两侧为重掺杂区；第二金属层，设置在重掺杂区上，形成源/漏极；栅绝缘层、第一金属层，依次设置在多晶硅层上，其中第一金属层材料为金属铝，形成栅极。In order to solve the above technical problem, another technical solution adopted by the present invention is to provide an array substrate, comprising: a glass substrate; a polysilicon layer disposed on the glass substrate, the two sides of the polysilicon layer being heavily doped regions; The metal layer is disposed on the heavily doped region to form a source/drain; the gate insulating layer and the first metal layer are sequentially disposed on the polysilicon layer, wherein the first metal layer material is metal aluminum to form a gate.
其中，玻璃基板与多晶硅层之间还设置缓冲层。A buffer layer is further disposed between the glass substrate and the polysilicon layer.
其中，第一金属层材料为金属铝。Wherein, the first metal layer material is metal aluminum.
其中，多晶硅层的其中一侧的第一金属层上设置有底层ITO薄膜。Wherein, the first metal layer on one side of the polysilicon layer is provided with an underlying ITO film.
其中，重掺杂区完成重掺杂后即进行活化处理。Wherein, the heavily doped region is subjected to activation treatment after being heavily doped.
通过上述方案，本发明的有益效果是：本发明通过在玻璃基板上生长多晶硅层，对多晶硅层的两侧进行重掺杂并进行活化处理，形成重掺杂区；在重掺杂区上生长第一金属层，形成源/漏极；栅绝缘层、第二金属层，依次设置在多晶硅层上，其中第二金属层材料为金属铝，能够减小产品金属线的RC延迟，实现产品的大尺寸化。Through the above solution, the beneficial effects of the present invention are: the present invention forms a heavily doped region by heavily doping and performing activation treatment on both sides of the polysilicon layer by growing a polysilicon layer on the glass substrate; growing on the heavily doped region a first metal layer, forming a source/drain; a gate insulating layer and a second metal layer, which are sequentially disposed on the polysilicon layer, wherein the second metal layer material is metal aluminum, which can reduce the RC delay of the product metal line, and realize the product Large size.
【附图说明】 [Description of the Drawings]
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。其中：In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the present invention. Other drawings may also be obtained from those of ordinary skill in the art in light of the inventive work. among them:
图1是现有技术中的阵列基板的制作方法示意图；1 is a schematic view showing a method of fabricating an array substrate in the prior art;
图2是本发明实施例的阵列基板的制作方法的流程示意图；2 is a schematic flow chart of a method for fabricating an array substrate according to an embodiment of the present invention;
图3是本发明实施例的阵列基板中的多晶硅层制作方法示意图；3 is a schematic diagram of a method for fabricating a polysilicon layer in an array substrate according to an embodiment of the present invention;
图4是本发明实施例的阵列基板中的重掺杂的示意图；4 is a schematic view showing heavy doping in an array substrate according to an embodiment of the present invention;
图5是本发明实施例的阵列基板中的第一金属层制作方法示意图；5 is a schematic diagram of a method for fabricating a first metal layer in an array substrate according to an embodiment of the invention;
图6是本发明实施例的阵列基板的结构示意图。FIG. 6 is a schematic structural view of an array substrate according to an embodiment of the present invention.
【具体实施方式】【detailed description】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, but not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without departing from the inventive scope are the scope of the present invention.
请参见图2所示，图2是本发明实施例的阵列基板的制作方法的流程示意图。如图2所示，阵列基板的制作方法包括：Referring to FIG. 2, FIG. 2 is a schematic flow chart of a method for fabricating an array substrate according to an embodiment of the present invention. As shown in FIG. 2, the method for fabricating the array substrate includes:
步骤S10：在玻璃基板上生长多晶硅层。Step S10: growing a polysilicon layer on the glass substrate.
其中玻璃基板与多晶硅层之间还生长有缓冲层。如图3所示，在玻璃基板101上生长一层缓冲层102，然后再生长一层多晶硅层103，将基板进行ELA处理，使得多晶硅层103表层结晶化，并经一次光罩和蚀刻后形成图3所示的形状，其中104的光刻胶（Photoresist，PR）。A buffer layer is further grown between the glass substrate and the polysilicon layer. As shown in FIG. 3, a buffer layer 102 is grown on the glass substrate 101, and then a polysilicon layer 103 is regrown, and the substrate is subjected to ELA treatment, so that the surface layer of the polysilicon layer 103 is crystallized and formed by a mask and etching. Figure 3 shows the shape of a photoresist (Photoresist, PR) of 104.
步骤S11：对多晶硅层两侧进行重掺杂并进行活化处理，形成重掺杂区。Step S11: Both sides of the polysilicon layer are heavily doped and activated to form a heavily doped region.
如图4所示，进一步对余留的光刻胶进行曝光处理，去除位于多晶硅层103的需要进行重掺杂的区域上的光刻胶104，然后对该区域进行重掺杂，形成重掺杂区105。该重掺杂区105能够与金属形成欧姆接触。重掺杂优选地采用离子注入方法。重掺杂完成后剥离多晶硅层103上的光刻胶104。As shown in FIG. 4, the remaining photoresist is further subjected to an exposure process to remove the photoresist 104 on the region of the polysilicon layer 103 that needs to be heavily doped, and then the region is heavily doped to form a heavily doped layer. Miscellaneous area 105. The heavily doped region 105 is capable of forming an ohmic contact with the metal. The heavy doping preferably employs an ion implantation method. The photoresist 104 on the polysilicon layer 103 is peeled off after the heavy doping is completed.
随即对重掺杂区105进行活化处理。由于活化温度较高，优选地一般600℃左右，这就要求在活化处理之前已经形成的各层都能够耐高温。而在本发明实施例中，在对重掺杂区105进行活化处理前，还没有制作金属层，因此无需考虑金属的耐高温性能。The heavily doped region 105 is then subjected to an activation treatment. Since the activation temperature is relatively high, it is preferably about 600 ° C, which requires that the layers which have been formed before the activation treatment are resistant to high temperatures. In the embodiment of the present invention, the metal layer has not been formed before the activation treatment of the heavily doped region 105, so that it is not necessary to consider the high temperature resistance of the metal.
步骤S12：在重掺杂区上生长第一金属层，形成源/漏极。Step S12: growing a first metal layer on the heavily doped region to form a source/drain.
如图5所示，在对重掺杂区105进行活化处理之后，多晶硅层103的两侧的重掺杂区105上设置有第一金属层106，形成源/漏极。重掺杂区105用于与源/漏极形成欧姆接触。多晶硅层103的其中一侧的第一金属层106上设置有底层ITO薄膜107。底层ITO薄膜107一般设置在源极上，作为显示面板的像素电极。第一金属层106材料也可以为金属铝。As shown in FIG. 5, after the active treatment of the heavily doped region 105, the first metal layer 106 is disposed on the heavily doped regions 105 on both sides of the polysilicon layer 103 to form a source/drain. The heavily doped region 105 is used to form an ohmic contact with the source/drain. An underlying ITO film 107 is disposed on the first metal layer 106 on one side of the polysilicon layer 103. The underlying ITO film 107 is generally disposed on the source as a pixel electrode of the display panel. The material of the first metal layer 106 may also be metal aluminum.
步骤S13：在多晶硅层上依次生长栅绝缘层和第二金属层，形成栅极，其中第二金属层材料为金属铝。Step S13: sequentially growing a gate insulating layer and a second metal layer on the polysilicon layer to form a gate, wherein the second metal layer material is metal aluminum.
参见图5，第一金属层106制作完成后，再沉积栅绝缘层108，然后在位于多晶硅层103的正上方的栅绝缘层108上沉积第二金属层109。第二金属层109材料为金属铝，设置为显示面板的栅极。之后再依次钝化层以及顶层ITO薄膜。其中顶层ITO薄膜设置为显示面板的公共电极。与现有技术相比，本发明实施例的阵列基板制作方法中减少了层间介质层的制作，优化了制造过程，能够降低制造成本。Referring to FIG. 5, after the first metal layer 106 is formed, the gate insulating layer 108 is deposited, and then the second metal layer 109 is deposited on the gate insulating layer 108 directly above the polysilicon layer 103. The second metal layer 109 is made of metallic aluminum and is provided as a gate of the display panel. The passivation layer and the top ITO film are then sequentially applied. The top ITO film is provided as a common electrode of the display panel. Compared with the prior art, the method for fabricating the array substrate of the embodiment of the invention reduces the fabrication of the interlayer dielectric layer, optimizes the manufacturing process, and can reduce the manufacturing cost.
由于金属铝电阻率非常低，与金属钼相比，走线负载更小，能有效的降低金属走线造成的RC delay，提高显示面板的信赖性，对于LTPS显示面板的大尺寸化很有利。Due to the very low electrical resistivity of metal aluminum, the wire load is smaller than that of metal molybdenum, which can effectively reduce the RC caused by metal traces. Delay, which improves the reliability of the display panel, is advantageous for the large size of the LTPS display panel.
图6是本发明实施例的阵列基板的结构示意图。如图6所示，阵列基板20包括：玻璃基板201、多晶硅层202、栅绝缘层203、第一金属层204以及第二金属层205。多晶硅层202设置在玻璃基板201上，多晶硅层202的两侧为重掺杂区206；第一金属层204设置在重掺杂区206上，形成源/漏极；栅绝缘层203、第二金属层205，依次设置在多晶硅层202上，其中第二金属层205材料为金属铝，形成栅极。FIG. 6 is a schematic structural view of an array substrate according to an embodiment of the present invention. As shown in FIG. 6, the array substrate 20 includes a glass substrate 201, a polysilicon layer 202, a gate insulating layer 203, a first metal layer 204, and a second metal layer 205. The polysilicon layer 202 is disposed on the glass substrate 201, and the polysilicon layer 202 is heavily doped regions 206 on both sides; the first metal layer 204 is disposed on the heavily doped region 206 to form a source/drain; the gate insulating layer 203, the second The metal layer 205 is sequentially disposed on the polysilicon layer 202, wherein the second metal layer 205 is made of metal aluminum to form a gate.
在本发明实施例中，玻璃基板201与多晶硅层202之间还设置缓冲层207。第一金属层204材料为金属铝。多晶硅层202的其中一侧的第一金属层204上设置有底层ITO薄膜208。第二金属层205上还依次设置有钝化层209、顶层ITO薄膜210。底层ITO薄膜208设为显示面板的像素电极，顶层ITO薄膜210设为显示面板的公共电极。与现有技术相比，本发明实施例的阵列基板20中减少了层间介质层，优化了阵列基板的结构，能够降低制造成本。In the embodiment of the present invention, a buffer layer 207 is further disposed between the glass substrate 201 and the polysilicon layer 202. The material of the first metal layer 204 is metal aluminum. An underlying ITO film 208 is disposed on the first metal layer 204 on one side of the polysilicon layer 202. A passivation layer 209 and a top ITO film 210 are also disposed on the second metal layer 205 in this order. The underlying ITO film 208 is set as the pixel electrode of the display panel, and the top ITO film 210 is set as the common electrode of the display panel. Compared with the prior art, the interlayer dielectric layer is reduced in the array substrate 20 of the embodiment of the present invention, the structure of the array substrate is optimized, and the manufacturing cost can be reduced.
重掺杂区206完成重掺杂后即进行活化处理。由于活化温度较高，优选地一般600℃左右，这就要求在活化处理之前已经形成的各层都能够耐高温。而本发明实施例的阵列基板对重掺杂区206进行活化处理是在重掺杂后随即进行的，此时第一金属层204和第二金属层205都还没有制作，所以无需考虑金属的耐高温性能。也就使得第一金属层204和/或第二金属层205的材料可以为电阻率较低的金属铝，与金属钼相比，走线负载更小，能有效的降低金属走线造成的RC delay，提高显示面板的信赖性。The heavily doped region 206 is subjected to an activation treatment after completion of the heavy doping. Since the activation temperature is relatively high, it is preferably about 600 ° C, which requires that the layers which have been formed before the activation treatment are resistant to high temperatures. The activation process of the heavily doped region 206 in the array substrate of the embodiment of the present invention is performed immediately after the heavy doping. At this time, the first metal layer 204 and the second metal layer 205 are not yet fabricated, so there is no need to consider the metal. High temperature resistance. In other words, the material of the first metal layer 204 and/or the second metal layer 205 can be a metal aluminum having a lower resistivity. Compared with the metal molybdenum, the trace load is smaller, and the RC caused by the metal trace can be effectively reduced. Delay, improve the reliability of the display panel.
综上所述，本发明通过将缓冲层设置在玻璃基板上，多晶硅层设置在缓冲层上，多晶硅层的两侧为重掺杂区，重掺杂区完成重掺杂后即进行活化；栅绝缘层、第一金属层，依次设置在多晶硅层上，其中第一金属层材料为金属铝，能够减小产品金属线的RC延迟，实现产品的大尺寸化。In summary, the present invention provides a buffer layer on a glass substrate, the polysilicon layer is disposed on the buffer layer, and the polysilicon layer is heavily doped on both sides, and the heavily doped region is activated after being heavily doped; The insulating layer and the first metal layer are sequentially disposed on the polysilicon layer, wherein the first metal layer material is metal aluminum, which can reduce the RC delay of the product metal line and realize the large size of the product.
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。The above is only the embodiment of the present invention, and is not intended to limit the scope of the invention, and the equivalent structure or equivalent process transformation of the present invention and the contents of the drawings may be directly or indirectly applied to other related technologies. The fields are all included in the scope of patent protection of the present invention.

Claims (13)

  1. 一种阵列基板的制作方法，其中，所述方法包括：A method of fabricating an array substrate, wherein the method comprises:
    在玻璃基板上生长多晶硅层；Growing a polysilicon layer on the glass substrate;
    对多晶硅层两侧进行重掺杂并进行活化处理，形成重掺杂区；Doping both sides of the polysilicon layer and performing activation treatment to form a heavily doped region;
    在所述重掺杂区上生长第一金属层，形成源/漏极；Growing a first metal layer on the heavily doped region to form a source/drain;
    在所述多晶硅层上依次生长栅绝缘层和第二金属层，形成栅极，其中所述第二金属层材料为金属铝；Forming a gate insulating layer and a second metal layer sequentially on the polysilicon layer to form a gate, wherein the second metal layer material is metal aluminum;
    其中，所述玻璃基板与所述多晶硅层之间还生长有缓冲层；所述第二金属层上还依次生长有钝化层和顶层ITO薄膜。A buffer layer is further grown between the glass substrate and the polysilicon layer; and a passivation layer and a top ITO film are sequentially grown on the second metal layer.
  2. 根据权利要求1所述的方法，其中，所述多晶硅层的其中一侧的所述第一金属层上设置有底层ITO薄膜。 The method according to claim 1, wherein said first metal layer on one side of said polysilicon layer is provided with an underlying ITO film.
  3. 根据权利要求1所述的方法，其中，所述第一金属层材料为金属铝。The method of claim 1 wherein the first metal layer material is metallic aluminum.
  4. 一种阵列基板的制作方法，其中，所述方法包括：A method of fabricating an array substrate, wherein the method comprises:
    在玻璃基板上生长多晶硅层；Growing a polysilicon layer on the glass substrate;
    对多晶硅层两侧进行重掺杂并进行活化处理，形成重掺杂区；Doping both sides of the polysilicon layer and performing activation treatment to form a heavily doped region;
    在所述重掺杂区上生长第一金属层，形成源/漏极；Growing a first metal layer on the heavily doped region to form a source/drain;
    在所述多晶硅层上依次生长栅绝缘层和第二金属层，形成栅极，其中所述第二金属层材料为金属铝。A gate insulating layer and a second metal layer are sequentially grown on the polysilicon layer to form a gate, wherein the second metal layer material is metal aluminum.
  5. 根据权利要求4所述的方法，其中，所述玻璃基板与所述多晶硅层之间还生长有缓冲层。 The method according to claim 4, wherein a buffer layer is further grown between the glass substrate and the polysilicon layer.
  6. 根据权利要求5所述的方法，其中，所述多晶硅层的其中一侧的所述第一金属层上设置有底层ITO薄膜。The method according to claim 5, wherein the first metal layer on one side of the polysilicon layer is provided with an underlying ITO film.
  7. 根据权利要求5所述的方法，其中，所述第一金属层材料为金属铝。The method of claim 5 wherein the first metal layer material is metallic aluminum.
  8. 根据权利要求4所述的方法，其中，所述第二金属层上还依次生长有钝化层和顶层ITO薄膜。The method according to claim 4, wherein a passivation layer and a top ITO film are sequentially grown on the second metal layer.
  9. 一种阵列基板，其中，所述阵列基板包括：An array substrate, wherein the array substrate comprises:
    玻璃基板；glass substrate;
    多晶硅层，设置在所述玻璃基板上，所述多晶硅层的两侧为重掺杂区；a polysilicon layer disposed on the glass substrate, the two sides of the polysilicon layer being heavily doped regions;
    第一金属层，设置在所述重掺杂区上，形成源/漏极；a first metal layer disposed on the heavily doped region to form a source/drain;
    栅绝缘层、第二金属层，依次设置在所述多晶硅层上，其中所述第二金属层材料为金属铝，形成栅极。A gate insulating layer and a second metal layer are sequentially disposed on the polysilicon layer, wherein the second metal layer material is metal aluminum to form a gate.
  10. 根据权利要求9所述的阵列基板，其中，所述玻璃基板与所述多晶硅层之间还设置缓冲层。The array substrate according to claim 9, wherein a buffer layer is further disposed between the glass substrate and the polysilicon layer.
  11. 根据权利要求9所述的阵列基板，其中，所述第一金属层材料为金属铝。The array substrate according to claim 9, wherein the first metal layer material is metal aluminum.
  12. 根据权利要求9所述的阵列基板，其中，所述多晶硅层的其中一侧的所述第一金属层上设置有底层ITO薄膜。The array substrate according to claim 9, wherein the first metal layer on one side of the polysilicon layer is provided with an underlying ITO film.
  13. 根据权利要求9所述的阵列基板，其中，所述重掺杂区完成重掺杂后即进行活化处理。 The array substrate according to claim 9, wherein the heavily doped region is subjected to an activation treatment after completion of heavy doping.
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