WO2017012487A1 - 数据传输*** - Google Patents

数据传输*** Download PDF

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Publication number
WO2017012487A1
WO2017012487A1 PCT/CN2016/089706 CN2016089706W WO2017012487A1 WO 2017012487 A1 WO2017012487 A1 WO 2017012487A1 CN 2016089706 W CN2016089706 W CN 2016089706W WO 2017012487 A1 WO2017012487 A1 WO 2017012487A1
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WIPO (PCT)
Prior art keywords
memory
pcmcia
slave
interface
address
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PCT/CN2016/089706
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English (en)
French (fr)
Inventor
邓远峰
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深圳市特博赛科技有限公司
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Publication of WO2017012487A1 publication Critical patent/WO2017012487A1/zh

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/41—Structure of client; Structure of client peripherals
    • H04N21/418—External card to be used in combination with the client device, e.g. for conditional access
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/436—Interfacing a local distribution network, e.g. communicating with another STB or one or more peripheral devices inside the home
    • H04N21/43607—Interfacing a plurality of external cards, e.g. through a DVB Common Interface [DVB-CI]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/41—Structure of client; Structure of client peripherals
    • H04N21/418—External card to be used in combination with the client device, e.g. for conditional access
    • H04N21/4181—External card to be used in combination with the client device, e.g. for conditional access for conditional access
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/436—Interfacing a local distribution network, e.g. communicating with another STB or one or more peripheral devices inside the home

Definitions

  • the present invention relates to the field of video data processing, and in particular to a data transmission system.
  • the DVB system In DVB (Digital video In the broadcast, digital video broadcasting system, in order to realize the separation of the set-top box and the smart card, the DVB system generally includes two parts: a host part (which may be a digital television set or a set-top box) and a conditional receiving module (generally called a Conditional Access Module, CAM)). These two parts are set by DVB CI (Digital video broadcast Common on the host) Interface, digital video broadcast common interface) connects and communicates.
  • the condition receiving module is used for plugging in a smart card.
  • the RF input signal is processed by the tuner and the demodulator to obtain a digital signal of the video content, and then output to the conditional receiving module in a scrambled manner.
  • the conditional receiving module obtains the key from the smart card through the read/write command interface, and sends the key to the descrambler for descrambling.
  • the descrambled data is output from the conditional receiving module to the host. The host decodes the descrambled data, outputs image data, and displays the image.
  • the versatility and data processing capability of the dedicated chip is too limited. If the general-purpose CPU is used for processing, since the general-purpose CPU bus is not compatible with the PCMCIA specification, an additional chip is needed to solve the communication problem between the CPU and the CAM. This requires solving the communication problem between the chip and the system, which is not conducive to the integration and modularization of the entire system.
  • IPTV Internet Protocol
  • IPTV Internet Protocol
  • network protocol TV based on the traditional set-top box dedicated chip
  • IPTV Internet Protocol
  • a data transmission system includes an I2C host and an I2C bus connected to the I2C host.
  • the I2C bus is provided with a plurality of I2C slaves, and the I2C slaves are respectively connected to corresponding PCMCIA hosts, and the PCMCIA host passes the PCMCIA control interface. Connect the corresponding PCMCIA slave.
  • the above data transmission system uses an I2C bus to control multiple PCMCIA control interfaces, and can simultaneously implement multi-channel DVB CI, cost saving, is more conducive to system integration.
  • FIG. 1 is a schematic structural diagram of a conventional technology for implementing a single-channel DVB CI
  • FIG. 2 is a schematic diagram of a connection between the host shown in FIG. 1 and a PCMCIA control interface
  • FIG. 3 is a schematic structural diagram of a data transmission system according to an embodiment
  • FIG. 4 is a schematic diagram of the principle of a data transmission system according to an embodiment
  • Figure 5 is a schematic diagram of the principle of implementing multi-channel DVB CI.
  • the RF input signal is demodulated by the host and then output to the PCMCIA control interface in a scrambled manner, that is, the conditional receiving module.
  • Conditional access module through the read and write command interface and get smart card (smart After the information is integrated, the key is obtained, and the key is sent to the descrambling module for descrambling.
  • the descrambled data is output from the conditional receiving module to the host, and the host decodes the image and outputs it to the television to realize image display.
  • the PCMCIA control interface usually includes a control signal, an address (Address (15 bit)) signal, a data (Data (8 bit)) signal, and the like.
  • Control signal group includes CE, WE, OE, IORD, IOWR, CardRST and WAIT PC Card data control signal and detection signals such as CD1 and CD2.
  • the general host CPU bus in Figure 1 is not compatible with the PCMCIA control interface.
  • the host CPU must be externally extended to implement DVB. CI function; existing IPTV usually needs to implement multi-channel DVB CI function. If the external expansion chip is separately, it is obviously not conducive to the integration of the whole system.
  • the data transmission system of an embodiment includes an I2C host and an I2C bus connected to the I2C host (such as the serial data line SDA and the serial clock in the figure).
  • I2C host such as the serial data line SDA and the serial clock in the figure.
  • SCL a number of I2C slaves are provided on the I2C bus, and the I2C slaves are respectively connected to the corresponding PCMCIA masters, and the PCMCIA masters are connected to the corresponding PCMCIA slaves through the PCMCIA control interface.
  • the above data transmission system uses an I2C bus to control multiple PCMCIA control interfaces, and can simultaneously implement multi-channel DVB CI, cost saving, is more conducive to system integration.
  • the I2C slave is a storage logic device, including a CPLD, an FPGA, an ASIC, etc.
  • the embodiment adopts a CPLD (Complex). Programmable Logic Device, complex programmable logic device).
  • the CPLD can construct its own logic function according to the needs of the user. In this embodiment, it is only necessary to perform corresponding configuration according to the PCMCIA control interface according to the PCMCIA control interface as shown in FIG.
  • PCMCIA control interface has three memory Common Memory, Attribute Memory (memory memory) and I/O Interface.
  • each I2C slave is mapped with a virtual memory connected to the I2C bus, and the virtual memory includes three storage blocks, and the three storage blocks respectively correspond to the common memory in the PCMCIA control interface (common Memory), attribute memory (attribute Memory) and I/O interface, and the three memory blocks have the same addressing space as the common memory, attribute memory and I/O interface in the corresponding PCMCIA control interface.
  • the I2C slave also has a memory mapped to reflect the state of the PCMCIA slave and the switching of the three memory blocks.
  • the state of the PCMCIA slave includes at least device insertion, device pull-out and communication error.
  • the memory can display different states by controlling the external device. When the I2C host reads and writes three memory blocks, it can identify different memory blocks. .
  • the address space of the common memory, the attribute memory and the I/O interface in the PCMCIA control interface respectively correspond to the sub address addressing space of the I2C bus, and the I2C host passes through the I2C bus to read and write data to the virtual memory.
  • the three memory blocks in the virtual memory synchronously read and write data to the common memory, attribute memory, and I/O interface in the PCMCIA control interface. Therefore, in the present embodiment, the operation of all PCMCIA control interfaces can be realized by a single I2C bus during operation.
  • I2C Inter-Integrated Circuit
  • I2C Inter-Integrated Circuit
  • Each slave connected to the I2C bus can set the address through a unique address and a simple host/slave relationship. Can be used as a host transmitter or host receiver. Therefore, when the embodiment is implemented, specifically, when the I2C host reads and writes data to the virtual memory through the I2C bus, if the I2C host sends an I2C read signal, the I2C host determines the corresponding address according to the address of the unique I2C slave. When the I2C slave receives the I2C read signal, it confirms which one of the virtual memory is to be read according to the read address in the I2C read signal, and the confirmed memory block is received.
  • the read address in the I2C read signal is converted into the common memory read address, the attribute memory read address or the I/O interface read address in the corresponding PCMCIA control interface, and the corresponding PCMCIA control interface
  • the common memory, attribute memory or I/O interface reads the data according to the converted read address and latches it on the PCMCIA bus.
  • the I2C slave reads the data directly from the PCMCIA bus. The above operation can convert the read operation of the I2C bus into the read operation of the PCMCIA bus.
  • the I2C master When the I2C master reads and writes data to the virtual memory through the I2C bus, if the I2C master sends an I2C write signal, the I2C master determines the corresponding I2C slave according to the address of the unique I2C slave, and the I2C slave receives the I2C write. When the signal is input, it is confirmed which one of the corresponding virtual memory is to be written according to the write address in the I2C write signal, and the confirmed memory block writes the I2C into the signal when receiving the I2C write signal.
  • the write address is converted into a common memory write address, an attribute memory write address or an I/O interface write address in the corresponding PCMCIA control interface, and the common memory, attribute memory or I/O interface in the corresponding PCMCIA control interface is
  • the I2C write signal is received, the data is written to the common memory, the attribute memory or the I/O interface in the corresponding PCMCIA control interface according to the converted write address.
  • the write operation of the I2C bus can be converted into a write operation of the PCMCIA bus.
  • the PCMCIA slave is the CAM, which performs data interaction with the I2C host, and then combines the read smart card information to confirm the host's authority, and then performs the descrambling processing of the transport stream according to the authority, and finally the data. Transfer to the I2C host for video data display.
  • This embodiment will include the CE, WE, OE, IORD, IOWR, CardRST, and WAIT PCs included in the Control signal group.
  • the Card data control signal and the detection signals such as CD1 and CD2 become I2C signals, which simplifies the interaction between the host and the PCMCIA control interface, enabling a single host to simultaneously control multiple PCMCIA control interfaces through the I2C bus, facilitating the implementation of multi-channel DVB. CI function.
  • the I2C host connects multiple cplds through the I2C bus, and each cpld connects to a corresponding conditional access module (CAM), that is, respectively connects the corresponding PCMCIA control interface.
  • CAM conditional access module
  • the three-way DVB in FIG. 4 can be realized by the above contents of this embodiment. CI functionality significantly increases integration and reduces costs.
  • the I2C master connects multiple I2C slaves through the I2C bus.
  • Each I2C slave connects to the corresponding PCMCIA master.
  • the PCMCIA master connects to the corresponding PCMCIA slave (CAM) through the PCMCIA control interface.
  • the PCMCIA slave connects to the I2C master through the transport stream interface TSI.
  • I2C host can control the read and write operations of the PCMCIA control interface through the I2C bus, and easily realize multi-channel DVB CI.
  • the PCMCIA slave can transmit the descrambled data to the transport stream interface TSI of the I2C host through the transport stream interface TSI.
  • the I2C host can be a display processor or the like having a display function, and the descrambled data can be videoized. display.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Storage Device Security (AREA)
  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)

Abstract

本发明涉及一种数据传输***，包括I2C主机及与I2C主机连接的I2C总线，所述I2C总线上设置有若干I2C从机，所述I2C从机分别连接对应的PCMCIA主机，所述PCMCIA主机通过PCMCIA控制接口连接对应的PCMCIA从机。

Description

数据传输***
【技术领域】
本发明涉及视频数据处理领域，特别是涉及一种数据传输***。
【背景技术】
在DVB（Digital video broadcast，数字视频广播）***中，为了实现机顶盒和智能卡的分离，DVB***一般包括两个部分：主机部分（可以是数字电视机或机顶盒）和条件接收模块（一般称为视密卡（Conditional Access Module，CAM））。这两个部分通过设置在主机上的DVB CI（Digital video broadcast Common Interface，数字视频广播公用接口）连接并通信。其中条件接收模块用于插接智能卡。
如图1所示，在实现视频接收及播放时，射频输入信号经调谐器、解调制器处理后获得视频内容的数字信号，然后以加扰的方式输出至条件接收模块。条件接收模块通过读写命令接口从智能卡获得密匙，将密匙送给解扰器进行解扰。解扰后的数据从条件接收模块输出至主机。主机将解扰后的数据进行解码，输出图像数据，实现图像的显示。
然而，在实现条件接收模块时，为了符合PCMCIA （Personal Computer Memory Card International Association，个人计算机内存卡国际组织）规范，能够实现和CAM进行数据交互，机顶盒在实现***功能时，需要采用专用芯片。
专用芯片的通用性和数据处理能力太过局限，而若采用通用型CPU进行处理，由于通用型CPU总线与PCMCIA规范并不兼容，则需要额外的芯片来解决CPU与CAM之间的通信问题。这就需要解决芯片与***之间的通讯问题，不利于整个***的集成化与模块化。
此外，随着IPTV（Internet Protocol Television，网路协议电视）的迅速发展，基于传统的机顶盒专用芯片已经不能满足多个用户同时观看相应节目的应用。如果要实现多路DVB CI，需要多个机顶盒，还需要解决多个机顶盒与***之间的通讯问题，不利于***的集成。
【发明内容】
基于此，有必要针对提供一种数据传输***，以简易化地实现多路DVB CI。
一种数据传输***，包括I2C主机及与I2C主机连接的I2C总线，所述I2C总线上设置有若干I2C从机，所述I2C从机分别连接对应的PCMCIA主机，所述PCMCIA主机通过PCMCIA控制接口连接对应的PCMCIA从机。
以上所述数据传输***，采用I2C总线控制多个PCMCIA控制接口，可同时实现多路DVB CI，节约成本，更有利于***的集成。
【附图说明】
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为传统技术实现单路现DVB CI的结构示意图；
图2为图1中所示主机与PCMCIA控制接口之间的连接示意图；
图3为一实施例的数据传输***的结构示意图；
图4为一实施例的数据传输***的原理示意图；
图5为实现多路DVB CI的原理示意图。
【具体实施方式】
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
如图1中所示，实现DVB CI功能时，射频输入信号经主机解调制后，以加扰的方式输出至PCMCIA控制接口，即条件接收模块。条件接收模块通过读写命令接口以及获取智能卡（smart card）信息等综合后得到密匙，并将密匙送给解扰模块进行解扰，解扰后的数据从条件接收模块输出传输至主机，主机解码图像输出给电视，实现图像的显示。如图2所示，PCMCIA控制接口通常包括控制（Control）信号、地址（Address（15bit））信号、数据（Data（8bit））信号等 3种信号线，Control信号组包括CE,、WE、OE、IORD、IOWR、CardRST以及WAIT等PC Card数据控制信号和CD1、CD2等检测信号。图1中通用的主机CPU总线与PCMCIA控制接口无法兼容，主机CPU必须外接拓展芯片才能实现DVB CI功能；现有的IPTV通常需要实现多路DVB CI功能，若分别外接拓展芯片，明显不利于整个***的集成。
为此，如图3所示，一实施例的数据传输***包括I2C主机及与I2C主机连接的I2C总线（如图中串行数据线SDA和串行时钟 SCL所示），I2C总线上设置有若干I2C从机，I2C从机分别连接对应的PCMCIA主机，PCMCIA主机通过PCMCIA控制接口连接对应的PCMCIA从机。
以上所述数据传输***，采用I2C总线控制多个PCMCIA控制接口，可同时实现多路DVB CI，节约成本，更有利于***的集成。
具体的，为节约成本，I2C从机为存储逻辑器件，包括CPLD、FPGA、ASIC等，优选的，本实施例采用CPLD（Complex Programmable Logic Device，复杂可编程逻辑器件）。CPLD可根据用户的需要自行构造逻辑功能，在本实施例中，只需要根据图3中所示，根据PCMCIA控制接口通常包括3种信号进行相对应的构造即可。
PCMCIA控制接口具有三个内存Common Memory（公共内存）、Attribute Memory（属性内存）和I/O 接口。本实施例在实现时，每个I2C从机映射有与I2C总线连接的虚拟存储器，虚拟存储器包括三个存储区块，三个存储区块分别对应连接PCMCIA控制接口中的公共内存（common memory）、属性内存(attribute memory)和I/O接口，且三个存储区块分别与对应PCMCIA控制接口中的公共内存、属性内存和I/O接口具有相同的寻址空间。I2C从机还映射有存储器，用于反映PCMCIA从机的状态和三个存储区块的切换。PCMCIA从机的状态至少包括设备***，设备拔出及通讯错误，存储器可以通过控制外部装置显示不同的状态，I2C主机在对三个存储区块进行读写操作时，可以识别不同的存储区块。
在具体设置时，PCMCIA控制接口中的公共内存、属性内存和I/O接口的寻址空间分别与I2C总线的子地址寻址空间对应，I2C主机通过I2C总线向虚拟存储器读写数据时，通过虚拟存储器中的三个存储区块同步向PCMCIA控制接口中的公共内存、属性内存和I/O接口读写数据。因此，本实施例在操作时，由单一的I2C总线即可实现对所有PCMCIA控制接口的操作。
I2C（Inter－Integrated Circuit）总线是两线式串行总线，接口线少，控制方式简单，每个连接到I2C总线的从机都可以通过唯一的地址和一直存在的简单的主机/从机关系设定地址，主机可以作为主机发送器或主机接收器。因此，本实施例在实现时，具体的，在I2C主机通过I2C总线向虚拟存储器读写数据时，若I2C主机发出的是I2C读取信号，I2C主机根据唯一的I2C从机的地址确定对应的I2C从机，I2C从机在接收到I2C读取信号时根据I2C读取信号中的读取地址确认要读取是对应虚拟存储器中的哪一个存储区块，确认的那个存储区块在接收到I2C读取信号时，将I2C读取信号中的读取地址转换为对应的PCMCIA控制接口中的公共内存读取地址、属性内存读取地址或I/O接口读取地址，对应的PCMCIA控制接口中的公共内存、属性内存或I/O接口在接收到I2C读取信号时，根据转换后的读取地址读取数据并锁存在PCMCIA总线上，I2C从机直接从PCMCIA总线上读取数据。由以上操作即可将I2C总线的读操作转换为PCMCIA总线的读操作。
在I2C主机通过I2C总线向虚拟存储器读写数据时，若I2C主机发出的是I2C写入信号，I2C主机根据唯一的I2C从机的地址确定对应的I2C从机，I2C从机在接收到I2C写入信号时根据I2C写入信号中的写入地址确认要写入对应虚拟存储器中的哪一个存储区块，确认的那个存储区块在接收到I2C写入信号时，将I2C写入信号中的写入地址转换为对应的PCMCIA控制接口中的公共内存写入地址、属性内存写入地址或I/O接口写入地址，对应的PCMCIA控制接口中的公共内存、属性内存或I/O接口在接收到I2C写入信号时，根据转换后的写入地址将数据写入对应的PCMCIA控制接口中的公共内存、属性内存或I/O接口。由以上操作即可将I2C总线的写操作转换为PCMCIA总线的写操作。
本实施例不仅可以应用于DVB CI，还可以应用于其它相关技术。在DVB CI应用实例中，PCMCIA从机即为CAM，其通过和I2C主机进行数据交互，再结合读取的智能卡信息，以确认主机的权限，再根据权限来进行传输流的解扰处理，最终将数据传输至I2C主机，进行视频数据的显示。
本实施例将Control信号组包括的CE,、WE、OE、IORD、IOWR、CardRST以及WAIT等PC Card数据控制信号和CD1、CD2等检测信号变成I2C信号，简化了主机与PCMCIA控制接口之间的交互，可使单个主机通过I2C总线同时控制多路PCMCIA控制接口，方便实现多路DVB CI功能。
如图4所示，I2C主机通过I2C总线连接多个cpld，每个cpld连接对应的条件接收模块（CAM），即分别连接对应的PCMCIA控制接口。通过本实施例的以上所述内容可以实现图4中的三路DVB CI功能，明显提高了集成度，降低了成本。
如图5所示，I2C主机通过I2C总线连接多个I2C从机，每个I2C从机连接对应的PCMCIA主机，PCMCIA主机通过PCMCIA控制接口连接对应的PCMCIA从机（CAM）。PCMCIA从机通过传输流接口TSI连接I2C主机。I2C主机通过I2C总线可以控制对PCMCIA控制接口的读写操作，轻松实现多路DVB CI。PCMCIA从机可以将解扰后的数据通过传输流接口TSI传输至I2C主机的传输流接口TSI，I2C主机可以是显示处理器等具有显示功能的设备，可以将解扰后的数据以视频的方式显示。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (8)

  1. 一种数据传输***，包括：
    I2C主机；
    I2C总线，与所述I2C主机连接的；
    若干I2C从机，设置在所述I2C总线上；
    PCMCIA主机；
    PCMCIA控制接口；以及
    PCMCIA从机；
    其中所述I2C从机分别连接对应的PCMCIA主机，所述PCMCIA主机通过所述PCMCIA控制接口连接对应的PCMCIA从机。
  2. 根据权利要求1所述的数据传输***，其特征在于，所述I2C从机包括存储逻辑器件。
  3. 根据权利要求2所述的数据传输***，其特征在于，所述存储逻辑器件包括CPLD、FPGA和ASIC。
  4. 根据权利要求1所述的数据传输***，其特征在于，还包括与I2C总线连接的虚拟存储器，其中所述I2C从机与所述虚拟存储器映射，所述虚拟存储器包括三个存储区块；所述PCMCIA控制接口包括公共内存、属性内存和I/O接口；所述三个存储区块分别对应连接所述公共内存、属性内存和I/O接口，且所述三个存储区块分别与对应的所述公共内存、属性内存和I/O接口具有相同的寻址空间。
  5. 根据权利要求4所述的数据传输***，其特征在于，还包括存储器，所述I2C从机还与所述存储器映射，用于反映所述PCMCIA从机的状态和所述三个存储区块的切换，所述PCMCIA从机的状态至少包括设备***，设备拔出及通讯错误。
  6. 根据权利要求4所述的数据传输***，其特征在于，所述公共内存、属性内存和I/O接口的寻址空间分别与所述I2C总线的子地址寻址空间对应，所述I2C主机通过I2C总线向虚拟存储器读写数据时，通过所述三个存储区块同步向所述公共内存、属性内存和I/O接口读写数据。
  7. 根据权利要求6所述的数据传输***，其特征在于，所述I2C主机通过I2C总线向虚拟存储器读写数据时，若I2C主机发出的是I2C读取信号，I2C主机根据唯一的I2C从机的地址确定对应的I2C从机，所述I2C从机在接收到I2C读取信号时根据所述I2C读取信号中的读取地址确认要读取的对应所述虚拟存储器中的存储区块，所述确认的存储区块在接收到I2C读取信号时，将所述I2C读取信号中的读取地址转换为对应的PCMCIA控制接口中的公共内存读取地址、属性内存读取地址或I/O接口读取地址，所述对应的PCMCIA控制接口中的公共内存、属性内存或I/O接口在接收到I2C读取信号时，根据转换后的读取地址读取数据并锁存在PCMCIA总线上，I2C从机直接从PCMCIA总线上读取数据。
  8. 根据权利要求7所述的数据传输***，其特征在于，所述I2C主机通过I2C总线向虚拟存储器读写数据时，若I2C主机发出的是I2C写入信号，I2C主机根据唯一的I2C从机的地址确定对应的I2C从机，所述I2C从机在接收到I2C写入信号时根据所述I2C写入信号中的写入地址确认要写入的对应所述虚拟存储器中的存储区块，所述确认的存储区块在接收到I2C写入信号时，将所述I2C写入信号中的写入地址转换为对应的PCMCIA控制接口中的公共内存写入地址、属性内存写入地址或I/O接口写入地址，所述对应的PCMCIA控制接口中的公共内存、属性内存或I/O接口在接收到I2C写入信号时，根据转换后的写入地址将数据写入对应的PCMCIA控制接口中的公共内存、属性内存或I/O接口。
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