WO2017002565A1 - Wiring board, thermal head, and method for producing wiring board - Google Patents
Wiring board, thermal head, and method for producing wiring board Download PDFInfo
- Publication number
- WO2017002565A1 WO2017002565A1 PCT/JP2016/067116 JP2016067116W WO2017002565A1 WO 2017002565 A1 WO2017002565 A1 WO 2017002565A1 JP 2016067116 W JP2016067116 W JP 2016067116W WO 2017002565 A1 WO2017002565 A1 WO 2017002565A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- conductive layer
- layer
- wiring board
- gold
- electrode
- Prior art date
Links
Images
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
- B41J2/315—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of heat to a heat sensitive printing or impression-transfer material
- B41J2/32—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of heat to a heat sensitive printing or impression-transfer material using thermal heads
- B41J2/335—Structure of thermal heads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Definitions
- the present invention relates to a wiring board, a thermal head, and a manufacturing method of the wiring board.
- Migration electrochemical migration
- metal ions are deposited on the cathode side when an electric field is applied between narrowly spaced electrodes, which extend to the anode side in a branch shape and short-circuit between conductor circuits.
- Patent Document 1 gold (Au) paste-like composition is printed on a substrate in a predetermined pattern, and silver (Ag) powder is conductorized on the thick film of the formed paste-like composition.
- a method for manufacturing a high-density wiring board is described in which a paste-like composition containing a material is printed with a size smaller than the predetermined pattern size.
- the high-density wiring board described in Patent Document 1 forms a predetermined pattern of Au paste-like composition by printing, and then has a size smaller than the predetermined pattern size of Ag paste-like composition. Since the pattern is formed by printing, it is not suitable for forming a fine pattern, and there is room for improvement.
- the wiring board includes an insulating substrate, and a first conductive layer and a second conductive layer stacked on the substrate, and the second conductive layer includes the first conductive layer.
- the portion is provided on the outer periphery of the boundary between the first conductive layer and the second conductive layer.
- the first conductive layer is provided on the second conductive layer.
- the second conductive layer is provided on the first conductive layer.
- the stepped portion or the alloy portion is exposed.
- the wiring board according to any one of the first to third aspects the insulating substrate, the first conductive layer and the second layer laminated on the substrate.
- a conductive layer, and the second conductive layer has a smaller ionization tendency than the first conductive layer, and the second conductive layer is disposed at a boundary outer peripheral portion of the first conductive layer and the second conductive layer.
- a stepped portion or an alloy portion protruding laterally from the first conductive layer is formed, and is composed of positional accuracy between the first conductive layer and the second conductive layer or the first conductive layer and the second conductive layer.
- the width or interval of the laminated structure is set to 10 ⁇ m or less.
- the first conductive layer is provided on the second conductive layer.
- the second conductive layer is provided on the first conductive layer.
- the stepped portion or the alloy portion is preferably exposed.
- the wiring board is provided on the same plane as the first conductive layer on the insulating board, the first conductive layer provided on the board, and the substrate.
- the thermal head includes a wiring board according to any one of the first to fourth aspects, a glaze layer provided on the substrate, and a heat generation provided on the glaze layer.
- the thermal head includes a wiring board according to any one of the fifth to eighth aspects, a glaze layer provided on the substrate, and a heat generation provided on the glaze layer.
- a thermal head includes a wiring board according to the ninth aspect, a glaze layer provided on the substrate, a heating resistor provided on the glaze layer, and the glaze layer.
- the electrode terminal of an electrode and the wire which connects the said driver IC are provided,
- the said overlap part or a non-overlap part is formed in each of these individual electrodes.
- FIG. 1 is a schematic cross-sectional view showing the configuration of the thermal head.
- FIG. 2 is a schematic view showing a main part of a conventional thermal head.
- FIG. 3 is an enlarged schematic view showing the wire bonding portion of FIG.
- FIG. 4 is a schematic diagram showing the main part of the thermal head according to the first embodiment.
- FIG. 5A is a schematic plan view of the wiring board before the etching process
- FIG. 5B is a schematic side sectional view of the wiring board before the etching process
- 6A is a schematic plan view of the wiring board after the etching process
- FIG. 6B is a schematic side sectional view of the wiring board after the etching process.
- 7A is a partially enlarged view showing a VII portion in FIG. 6A, and FIG.
- FIG. 7B is a schematic cross-sectional view taken along the line viib-viib in FIG. 7A.
- FIG. 8 is a graph showing experimental results on the migration resistance of the wiring board.
- FIG. 9 is a table showing experimental results on the migration resistance of the wiring board.
- FIG. 10 is a table showing experimental results on the resistance to sulfurization of the wiring board.
- FIG. 11 is a schematic diagram showing a main part of a thermal head according to the second embodiment.
- 12A is a schematic plan view of the wiring board before the etching process
- FIG. 12B is a schematic side sectional view of the wiring board before the etching process.
- FIG. 13A is a schematic plan view of the wiring board after the etching process, and FIG.
- FIG. 13B is a schematic side sectional view of the wiring board after the etching process.
- 14A is a partially enlarged view showing the XIV portion of FIG. 13A
- FIG. 14B is a schematic cross-sectional view taken along the line xivb-xivb of FIG. 14A.
- FIG. 15 is a schematic diagram showing a main part of a thermal head according to the third embodiment.
- FIG. 1 is a schematic cross-sectional view showing the configuration of the thermal head 100.
- FIG. 2 is a schematic diagram showing a main part of a conventional thermal head 100.
- FIG. 2A is a schematic plan view of a main part of the thermal head 100
- FIG. 2B is a schematic cross-sectional view of the main part of the thermal head 100.
- hatching that represents a cross section of each component in FIG.
- FIG. 3 is an enlarged schematic view showing the wire bonding portion of FIG.
- the thermal head 100 includes a wiring board 50 and a printed wiring board 30 fixed on a support plate 32. On the printed wiring board 30, a driver IC 11 and a connector 31 for connecting the thermal head 100 to an external device that performs printing control and the like are provided.
- the wiring board 50 has wirings and electrodes formed on the insulating substrate 12.
- the insulating substrate 12 is formed of an electrically insulating ceramic or the like.
- a glaze layer 13 made of glass or the like is formed on the entire top surface of the insulating substrate 12.
- the glaze layer 13 serves as a heat storage layer that shortens the time required to raise the temperature of the heating resistor 6 described later and enhances the thermal response characteristics of the thermal head 100.
- a common electrode 5 and a plurality of individual electrodes 8 are formed on the upper surface of the glaze layer 13.
- the common electrode 5 includes a rectangular electrode surface 5a in a plan view and a conveyance direction of thermal paper (not shown) from the electrode surface 5a (the x direction shown in FIG. 2A). It is made into the comb-tooth shape provided with the some strip
- Each of the plurality of individual electrodes 8 has a strip shape extending along the transport direction x.
- the plurality of strip electrodes 5 b and the plurality of individual electrodes 8 are alternately arranged in the y direction orthogonal to the transport direction x.
- a linear heating resistor 6 is formed on the common electrode 5 and the plurality of individual electrodes 8 by thick film printing or the like.
- the heating resistor 6 extends along the y direction so as to straddle the plurality of strip electrodes 5b and the plurality of individual electrodes 8.
- the heating resistor 6, for example, made of ruthenium oxide (RuO 2) or the like.
- each individual electrode 8 is connected to a driver IC 11 via a gold wire 10.
- the gold wire 10 and the driver IC 11 are molded with a sealing resin 16 made of an epoxy resin material.
- a driver circuit (not shown) of the driver IC 22 causes a current to flow from the common electrode 5 to each individual electrode 8 via the heating resistor 6.
- FIG. 2A when a current flows through the heating resistor 6 between the strip electrode 5b and the individual electrode 8 in the common electrode 5, the portion generates heat.
- thermal paper (not shown) the thermal paper develops color and a predetermined print image is formed on the thermal paper.
- an insulating protective film 7 is formed on the entire surface of the insulating substrate 12 so as to cover the individual electrodes 8, the common electrode 5, and the heating resistor 6.
- the insulating protective film 7 is made of, for example, a PbO—SiO 2 —ZrO 2 glass material having electrical insulation. Since the heating resistor 6 is covered with the insulating protective film 7, the heat of the heating resistor 6 is transmitted to the thermal paper (not shown) through the insulating protective film 7.
- a low purity gold-containing paste 14 is formed on an insulating substrate 12 using a low-purity gold-containing paste, and a high-purity gold-containing paste is used as an upper layer of the low-purity gold layer 14.
- the wire bonding part 9 which is an electrode terminal of the individual electrode 8 was formed by laminating the formed high purity gold layer 15.
- Gold is a metal that is less prone to migration than silver (Ag), but is very expensive and increases manufacturing costs. Therefore, it is conceivable to use a material that is less expensive than gold, such as silver, instead of gold, but there is a problem that migration is likely to occur compared to gold.
- FIG. 4 is a view similar to FIG. 3, and is a schematic view showing the main part of the thermal head 100A according to the first embodiment.
- 4A is a schematic plan view of the main part of the thermal head 100A
- FIG. 4B is a schematic cross-sectional view of the main part of the thermal head 100A.
- the size of the second conductive layer made of gold is made larger than the size of the first conductive layer made of silver.
- the outermost peripheral part of the wire bonding part 18 became the 2nd conductive layer which consists of gold
- the second conductive layer is protruded to the side of the first conductive layer by one etching process for the two types of conductive layers.
- the step portion 23 or the alloy layer (alloy portion) 24 is formed on the outer peripheral portion of the wire bonding portion 18. Since a fine pattern can be formed by etching, high-density wiring can be realized. Details will be described below.
- the configuration of the individual electrode 17 is different from that of the individual electrode 17 of the conventional thermal head 100, but the other configuration is the same, and the description thereof is omitted.
- the individual electrode 17 of the thermal head 100A according to the first embodiment includes a silver layer (first conductive layer) 20 in which a wiring portion extending in the x direction is made of silver.
- a wire bonding portion 18 to be wire-bonded is provided as an electrode terminal at an end portion of the individual electrode 17 in the x direction.
- an electrode terminal that is an exposed portion of the individual electrode 17 that is not covered with the insulating protective film 7 is referred to as a wire bonding portion 18.
- the wire bonding portion 18 has a laminated structure including a gold layer (second conductive layer) 19 made of gold provided on the insulating substrate 12 via the glaze layer 13 and a silver layer 20 provided on the gold layer 19.
- the gold layer 19 has a size that is slightly larger in area on the xy plane than the silver layer 20, and a stepped portion 23 or an alloy layer 24 is formed on the outer periphery of the boundary between the gold layer 19 and the silver layer 20.
- the wire bonding portion 18 Since the wire bonding portion 18 is not covered with the insulating protective film 7, it is necessary to suppress the occurrence of migration between adjacent wire bonding portions 18.
- the outer peripheral size of the gold layer 19 is made slightly larger than the outer peripheral size of the silver layer 20 in the wire bonding portion 18 as described above.
- a method for forming the wire bonding portion 18 will be described with reference to FIGS. In FIGS. 5 to 7, a simple shape is used for easy understanding. 5 to 7, the glaze layer is omitted.
- FIG. 5A is a schematic plan view of the wiring board before the etching process
- FIG. 5B is a schematic side sectional view of the wiring board before the etching process, taken along the line vb-vb in FIG. A cross section is shown.
- a gold paste composition for example, the gold content is 15 to 100% by weight
- Printing is performed with an existing rectangular pattern.
- a silver paste-like composition (for example, the silver content is 15 to 100% by weight) is a rectangular pattern having a size slightly smaller than that of the insulating substrate 1 so as to cover the pattern of the gold paste-like composition.
- the gold layer 2 and the silver layer 3 are formed by baking the insulating substrate 1 (for example, about 800 ° C.).
- a gold-silver alloy layer 4 is formed at the boundary between the gold layer 2 and the silver layer 3 (not shown in FIG. 5, see FIG. 7). That is, the gold layer 2 and the silver layer 3 are laminated and disposed on the insulating substrate 1 by printing and baking.
- step portion 23 since the above-described step portion 23 is not formed by printing, high accuracy is not required in this step.
- FIG. 5 (Photolithography / etching process)
- a substantially H-shaped pattern as shown by a one-dot chain line is formed by photolithography.
- portions other than the portion 3a (substantially H-shaped pattern) surrounded by the alternate long and short dash line shown in FIG. 5A are dissolved. Remove.
- the gold constituting the gold layer 2 is a material having a smaller ionization tendency than the silver constituting the silver layer 3. For this reason, the dissolution rate (etching rate) of the gold layer 2 is slower than the dissolution rate (etching rate) of the silver layer 3.
- a potassium iodide solution in which the mixing ratio of iodine, potassium iodide, and water is 1: 2: 10 (wt ratio) is used as an etching solution.
- the gold layer 2 and the silver layer 3 have a difference of about three times in the speed (side etching speed) at which the dissolution proceeds toward the side.
- FIG. 6A is a schematic plan view of the wiring board after the etching process
- FIG. 6B is a schematic side sectional view of the wiring board after the etching process, and is cut along the vib-vib line in FIG. 6A.
- a cross section is shown.
- FIG. 7A is a partially enlarged view showing a VII portion in FIG. 6A
- FIG. 7B is a schematic cross-sectional view taken along the line viib-viib in FIG. 7A.
- FIGS. 6 and 7 in the etching process, since the etching proceeds from the outer surface, the upper part of the silver layer 3 is dissolved most and the amount of dissolution is decreased downward. For this reason, as shown in FIG.
- channel 26 between a pair of substantially H-shaped pattern is short toward the lower part from the upper part.
- the upper part is dissolved most, and the amount of dissolution decreases downward. For this reason, the dimension between the side surfaces which oppose in the groove
- the dissolution rate of the silver layer 3 is faster than the dissolution rate of the gold layer 2.
- the interval between the grooves 26 is larger than the interval between the grooves 27.
- the side surface of the groove 26 is an inclined surface that spreads laterally (outward) from the top of the silver layer 3 downward.
- the side surface of the groove 27 is an inclined surface that spreads sideward (outward) from the top of the gold layer 2 toward the lower side. Since the dissolution rate of the gold layer 2 is slower than that of the silver layer 3, a stepped portion 23 is formed at the outer periphery of the boundary between the silver layer 3 and the gold layer 2.
- the gold layer 2 is formed so as to protrude about 1 ⁇ m to the side as compared with the silver layer 3. Further, the alloy layer 4 formed by firing is exposed by the etching process.
- the gold and silver alloy layer 4 is formed on the outer periphery of the boundary between the gold layer 2 and the silver layer 3 by the etching process.
- 8 and 9 are a graph and a table showing experimental results on the migration resistance of the wiring board.
- a pattern having an electrode length of 30 mm and a distance of 100 ⁇ m was formed.
- the gold layer 2 and the silver layer 3 were subjected to photolithography etching processing once (simultaneously).
- the environmental conditions were 85 ° C. and 85% RH. Under this environment, a voltage of DC 32V was applied and energized continuously to measure the time until the insulation resistance value became 10 M ⁇ or less, which is a determination reference value.
- a wiring board in which an electrode is formed only by a gold layer 2 having a film thickness of 0.66 ⁇ m is a first comparative example, and an electrode is formed by only a silver layer 3 having a film thickness of 3.3 ⁇ m
- the wiring board thus obtained is used as a second comparative example.
- Two types of wiring boards of the present embodiment were prepared, and experiments were conducted respectively.
- the gold layer 2 has a thickness of 0.25 ⁇ m and the silver layer 3 has a thickness of 0.80 ⁇ m. That is, in the first wiring board, the thickness of the gold layer 2 is set to about 1/3 of the thickness of the silver layer 3.
- the gold layer 2 has a thickness of 1.00 ⁇ m and the silver layer 3 has a thickness of 1.57 ⁇ m. That is, in the second wiring board, the film thickness of the gold layer 2 is about 2/3 of the film thickness of the silver layer 3.
- the insulation resistance value hardly decreased and a high migration resistance result was obtained.
- the insulation resistance value became 10 M ⁇ (judgment reference value) or less before the continuous energization time was less than 50 hours.
- the electrode is composed only of the gold layer 2, the cost increases.
- Example 803 of the first wiring board of the present embodiment a result that a high insulation resistance value can be maintained until the continuous energization time is 200 hours was obtained. It was confirmed that the migration resistance of the first wiring board was greatly improved as compared with the second comparative example 802. In Example 804 of the second wiring board of the present embodiment, it was found that even when the continuous energization time exceeds 2000 hours, the insulation resistance value hardly decreases and high migration resistance can be obtained. From this experimental result, it was found that the migration resistance can be improved by increasing the ratio of the thickness of the gold layer 2. That is, by changing the ratio of the film thickness of the gold layer 19 and the silver layer 20, the degree of suppression of migration can be adjusted as necessary.
- FIG. 10 is a table showing experimental results on the sulfurization resistance of the wiring board.
- a wiring board in which an electrode is constituted only by a gold layer 2 having a thickness of 0.65 ⁇ m is a third comparative example, and an electrode is constituted only by a silver layer 3 having a thickness of 3.3 ⁇ m.
- the wiring board be a fourth comparative example. Two types of wiring boards of the present embodiment were prepared, and experiments were conducted respectively.
- the gold layer 2 has a thickness of 0.3 ⁇ m and the silver layer 3 has a thickness of 3.3 ⁇ m. That is, in the third wiring board, the thickness of the gold layer 2 is about 1/10 of the thickness of the silver layer 3.
- the gold layer 2 has a thickness of 3.3 ⁇ m and the silver layer 3 has a thickness of 0.3 ⁇ m. That is, in the fourth wiring board, the film thickness of the gold layer 2 is about 10 times the film thickness of the silver layer 3.
- the gold layer 2 is arranged in the upper layer and the silver layer 3 is arranged in the lower layer, which corresponds to a second embodiment to be described later.
- each wiring board is left unattended for a predetermined period.
- a resistance value fluctuation of less than + 1% is marked as very good.
- a resistance value fluctuation of + 1% or more and less than + 20% is marked as good.
- Of + 20% or more and less than + 100% was judged as bad ⁇ , and resistance value fluctuation of + 100% or more was judged as poor x.
- the third wiring board of the present embodiment even when left for 12 months, there was almost no change in resistance value, and it was determined to be very good.
- the third wiring board was judged to be good even after being left for 36 months, and a high sulfidation resistance result was obtained.
- the fourth wiring board even when left for 36 months, there was almost no change in resistance value, and it was determined to be very good. According to this experimental result, regardless of whether the gold layer 2 or the silver layer 3 is arranged on the lower layer side, a high sulfidation resistance can be obtained by forming the gold layer 2 and the silver layer 3 in a laminated structure. I understood.
- the resistance to sulfurization can be improved by increasing the ratio of the thickness of the gold layer 2. That is, by changing the ratio of the film thickness of the gold layer 19 and the silver layer 20, the degree of suppression of sulfidation can be adjusted as necessary.
- the wiring board according to the present embodiment includes an insulating substrate 1 and a silver layer 3 and a gold layer 2 laminated on the insulating substrate 1.
- the gold layer 2 has a smaller ionization tendency than the silver layer 3.
- a step portion 23 in which the gold layer 2 protrudes to the side of the silver layer 3 was provided at the boundary outer peripheral portion between the silver layer 3 and the gold layer 2.
- the migration resistance can be improved.
- the resistance to sulfurization can be improved.
- the step portion 23 in which the gold layer 2 protrudes laterally from the silver layer 3 can be formed by a single etching process, it is possible to prevent the displacement of the gold layer 2 and the silver layer 3 from occurring.
- the positional accuracy between the gold layer 2 and the silver layer 3 (that is, the maximum value of the relative displacement between the gold layer 2 and the silver layer 3) can be 10 ⁇ m or less.
- a fine pattern having a width dimension of 5 ⁇ m or less can be formed by the laminated structure including the gold layer 2 and the silver layer 3.
- the interval between the laminated structures composed of the gold layer 2 and the silver layer 3 can be set to 10 ⁇ m or less. For this reason, compared with the invention described in Patent Document 1, a higher-density wiring board can be provided.
- FIG. 11 is a diagram similar to FIG. 4, and is a schematic diagram illustrating a main part of a thermal head 100 ⁇ / b> B according to the second embodiment.
- the gold layer 19B protrudes to the side of the silver layer 20B, and a stepped portion 23B or an alloy layer 24B is formed on the outer periphery of the boundary between the silver layer 20B and the gold layer 19B.
- a method of forming such a wire bonding portion 18B will be described with reference to FIGS. In FIGS. 12 to 14, a simple shape is used for easy understanding. In FIGS. 12 to 14, the glaze layer is omitted.
- FIG. 12A is a schematic plan view of the wiring board before the etching process
- FIG. 12B is a schematic side sectional view of the wiring board before the etching process, and is cut along the line xiib-xiib in FIG. 12A.
- a cross section is shown.
- a silver paste composition is printed on a rectangular flat plate-like insulating substrate 1 in a rectangular pattern having a size slightly smaller than that of the insulating substrate 1. Thereafter, the gold paste composition is printed in a rectangular pattern extending in parallel with the short direction of the insulating substrate 1 on the upper surface of the central portion of the silver paste composition pattern.
- the gold layer 2 and the silver layer 3 are formed by baking the insulating substrate 1 (for example, about 800 ° C.). By firing, a gold-silver alloy layer 4 is formed at the boundary between the gold layer 2 and the silver layer 3 (not shown in FIG. 12, see FIG. 14).
- FIG. 12 (Photolithography / etching process)
- a substantially H-shaped pattern as shown by a one-dot chain line is formed by photolithography.
- wet etching treatment is performed once, that is, by immersing the wiring board in the etching solution, portions other than the portion (substantially H-shaped pattern) 3a surrounded by the one-dot chain line shown in FIG. Remove.
- FIG. 13A is a schematic plan view of the wiring board after the etching process
- FIG. 13B is a schematic side sectional view of the wiring board after the etching process, and is cut along the xiiib-xiiib line in FIG. 13A.
- a cross section is shown.
- 14A is a partially enlarged view showing the XIV part of FIG. 13A
- FIG. 14B is a schematic cross-sectional view taken along the line xivb-xivb of FIG. 14A.
- etching proceeds from the outer surface, so that the upper part of the gold layer 2 is dissolved most and the amount of dissolution decreases downward. For this reason, as shown in FIG.
- channel 27 between a pair of substantially H-shaped pattern is short toward the lower part from the upper part. Also in the silver layer 3, the upper part is dissolved most, and the amount of dissolution becomes smaller downward. For this reason, the dimension between the side surfaces which oppose in the groove
- the dissolution rate of the silver layer 3 is faster than the dissolution rate of the gold layer 2.
- the interval between the grooves 26 is larger than the interval between the grooves 27.
- the side surface of the groove 26 is an inclined surface that spreads laterally (outward) from the top of the silver layer 3 downward.
- the side surface of the groove 27 is an inclined surface that spreads sideward (outward) from the top of the gold layer 2 toward the lower side. Since the dissolution rate of the gold layer 2 is slower than that of the silver layer 3, a step portion 23 is formed at the outer periphery of the boundary between the silver layer 3 and the gold layer 2.
- the gold layer 2 is formed so as to protrude sideways compared to the silver layer 3.
- the alloy layer 4 formed by firing is exposed by the etching process. That is, the gold and silver alloy layer 4 is formed on the outer periphery of the boundary between the gold layer 2 and the silver layer 3 by the etching process.
- FIG. 15 is a diagram similar to FIG. 4, and is a schematic diagram showing a main part of a thermal head 100 ⁇ / b> C according to the third embodiment.
- the wiring board according to the third embodiment is provided with the insulating substrate 12, the silver layer 20C provided on the insulating substrate 12, and the insulating substrate 12 provided on the same plane as the silver layer 20C. And a gold layer 19C having a smaller ionization tendency.
- the gold layer 19C has an overlapping portion 19a that overlaps the edge of the silver layer 20C and a non-overlapping portion 19b that does not overlap the silver layer 20C, and the non-overlapping portion 19b is configured as a wire bonding portion (electrode terminal) 18C.
- the non-overlapping portions 19b of the silver layer 20C and the gold layer 19 are disposed on the insulating substrate 12 via the glaze layer 13, respectively.
- the overlapping portion 19a of the gold layer 19C and the silver layer 20C have a laminated structure, whereby the gold-silver alloy layer 24C can be formed by firing. Moreover, since the wire bonding part 18C consists only of the gold layer 19C, it has high migration resistance and sulfidation resistance.
- the third embodiment it is possible to provide a wiring board having high migration resistance and high sulfidation resistance, as in the first embodiment.
- the first conductive layer having a large ionization tendency is the silver layers 20, 20B, and 20C and the second conductive layer having a small ionization tendency is the gold layers 19, 19B, and 19C has been described. Is not limited to this.
- the first conductive layer may be a copper layer made of copper or an aluminum layer made of aluminum, and a platinum layer made of platinum or a palladium layer made of palladium may be adopted as the second conductive layer.
- At least the second conductive layer has a smaller ionization tendency than the first conductive layer, and the stepped portion 23 or the alloy layers 24, 24B, and 24C are formed by projecting the second conductive layer to the side of the first conductive layer.
- the present invention can be applied to this wiring board.
- Modification 2 In the first and second embodiments, examples have been described in which the gold layers 19 and 19B and the silver layers 20 and 20B are formed by printing and firing, respectively, but the present invention is not limited to this.
- Each of the gold layers 19 and 19B and the silver layers 20 and 20B is formed by vapor deposition or sputtering, and then the stepped portion 23 is formed by a single etching process on the stacked structure portion of the gold layers 19 and 19B and the silver layers 20 and 20B. May be formed. Note that when the gold layers 19 and 19B and the silver layers 20 and 20B are formed by vapor deposition or sputtering, the above-described alloy layers 24 and 24B are not formed.
- the case where only the step portion 23 is formed and the alloy layers 24 and 24B are not formed is also within the scope of the present invention. Further, the case where only the alloy layers 24 and 24B are formed and the step portion 23 is not formed is also within the scope of the present invention. Even when only the alloy layers 24 and 24B are formed, the migration resistance and the sulfidation resistance can be improved. Since not only the step portion 23 but also the alloy layer 24 is formed, the migration resistance and the sulfidation resistance can be greatly improved. Therefore, it is preferable to form both the step portion 23 and the alloy layer 24.
- the present invention can be applied to substrates of various electronic devices.
- the present invention can be applied to a catalyst substrate in a steam reformer that produces hydrogen from a source gas and steam by catalytic reforming.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electronic Switches (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Structure Of Printed Boards (AREA)
Abstract
A wiring board is provided with an insulating substrate and a first conductive layer and a second conductive layer that are layered on the substrate. The second conductive layer has a lower ionization tendency than the first conductive layer. A stepped section or an alloy section in which the second conductive layer protrudes laterally beyond the first conductive layer is provided to the outer periphery of the boundary between the first conductive layer and the second conductive layer by performing etching processing one time on the first conductive layer and the second conductive layer.
Description
本発明は、配線基板、サーマルヘッドおよび配線基板の製造方法に関する。
The present invention relates to a wiring board, a thermal head, and a manufacturing method of the wiring board.
近年、配線基板の小型、軽量化が強く要望されている。配線基板の小型、軽量化を図るためには、高密度な配線の実現が重要であるが、配線電極におけるマイグレーションの問題がある。なお、マイグレーション(エレクトロケミカルマイグレーション)とは、狭い間隔の電極間で電界が印加される際、金属イオンが陰極側に析出し、それが枝状に陽極側まで延びて導体回路間がショートする現象をいう。
In recent years, there has been a strong demand for smaller and lighter wiring boards. In order to reduce the size and weight of the wiring board, it is important to realize high-density wiring, but there is a problem of migration in the wiring electrode. Migration (electrochemical migration) is a phenomenon in which metal ions are deposited on the cathode side when an electric field is applied between narrowly spaced electrodes, which extend to the anode side in a branch shape and short-circuit between conductor circuits. Say.
従来、配線電極のマイグレーションを抑えることができ、配線電極パターンのショートによる基板の不良を防ぐための技術が提案されている(特許文献1参照)。特許文献1には、基板上に金(Au)のペースト状組成物を所定のパターンで印刷を行い、その形成されたペースト状組成物の厚膜上に、銀(Ag)の粉体を導体材料として含むペースト状組成物を、上記所定のパターンサイズよりも小さいサイズで印刷を行う高密度配線基板の製造方法が記載されている。
Conventionally, there has been proposed a technique that can suppress migration of wiring electrodes and prevent a substrate from being defective due to a short of a wiring electrode pattern (see Patent Document 1). In Patent Document 1, gold (Au) paste-like composition is printed on a substrate in a predetermined pattern, and silver (Ag) powder is conductorized on the thick film of the formed paste-like composition. A method for manufacturing a high-density wiring board is described in which a paste-like composition containing a material is printed with a size smaller than the predetermined pattern size.
しかしながら、上記特許文献1に記載の高密度配線基板は、Auのペースト状組成物による所定のパターンを印刷により形成し、その後、Agのペースト状組成物により上記所定のパターンサイズよりも小さいサイズのパターンを印刷により形成しているので、微細パターンの形成には適しておらず、改善の余地があった。
However, the high-density wiring board described in Patent Document 1 forms a predetermined pattern of Au paste-like composition by printing, and then has a size smaller than the predetermined pattern size of Ag paste-like composition. Since the pattern is formed by printing, it is not suitable for forming a fine pattern, and there is room for improvement.
本発明の第1の態様によると、配線基板は、絶縁性の基板と、前記基板上において積層された第1導電層および第2導電層と、を備え、前記第2導電層は、前記第1導電層よりもイオン化傾向が小さく、前記第1導電層および前記第2導電層に対する一度のエッチング処理により、前記第2導電層が前記第1導電層よりも側方に突出した段差部または合金部を、前記第1導電層と前記第2導電層との境界外周部に設けた。
本発明の第2の態様によると、第1の態様の配線基板において、前記第1導電層は前記第2導電層上に設けられていることが好ましい。
本発明の第3の態様によると、第1の態様の配線基板において、前記第2導電層は前記第1導電層上に設けられていることが好ましい。
本発明の第4の態様によると、第1から第3までのいずれかの態様の配線基板において、前記段差部または前記合金部は露出されていることが好ましい。
本発明の第5の態様によると、配線基板は、第1から第3までのいずれかの態様の配線基板において、絶縁性の基板と、前記基板上において積層された第1導電層および第2導電層と、を備え、前記第2導電層は、前記第1導電層よりもイオン化傾向が小さく、前記第1導電層と前記第2導電層の境界外周部には、前記第2導電層が前記第1導電層よりも側方に突出した段差部または合金部が形成され、前記第1導電層と前記第2導電層との位置精度または前記第1導電層および前記第2導電層からなる積層構造体の幅または間隔が、10μm以下とされている。
本発明の第6の態様によると、第5の態様の配線基板において、前記第1導電層は前記第2導電層上に設けられていることが好ましい。
本発明の第7の態様によると、第5の態様の配線基板において、前記第2導電層は前記第1導電層上に設けられていることが好ましい。
本発明の第8の態様によると、第5から第7までのいずれかの態様の配線基板において、前記段差部または合金部は露出されていることが好ましい。
本発明の第9の態様によると、配線基板は、絶縁性の基板と、前記基板上に設けられた第1導電層と、前記基板上において、前記第1導電層と同一平面上に設けられ、前記第1導電層よりもイオン化傾向が小さい第2導電層と、を備え、前記第2導電層は、前記第1導電層の縁部上に重なる重なり部と、前記第1導電層とは重ならない非重なり部とを有し、前記非重なり部が電極端子として構成されている。
本発明の第10の態様によると、サーマルヘッドは、第1から第4までのいずれかの態様の配線基板と、前記基板上に設けられたグレーズ層と、前記グレーズ層上に設けられた発熱抵抗体と、前記グレーズ層上に設けられた共通電極および複数の個別電極と、前記個別電極の一部を覆う絶縁性の保護膜と、前記個別電極に電流を流すドライバICと、前記保護膜で覆われていない前記個別電極の電極端子と、前記ドライバICとを接続するワイヤとを備え、前記段差部または合金部は、前記複数の個別電極のそれぞれの電極端子に形成されている。
本発明の第11の態様によると、サーマルヘッドは、第5から第8までのいずれかの態様の配線基板と、前記基板上に設けられたグレーズ層と、前記グレーズ層上に設けられた発熱抵抗体と、前記グレーズ層上に設けられた共通電極および複数の個別電極と、前記個別電極の一部を覆う絶縁性の保護膜と、前記個別電極に電流を流すドライバICと、前記保護膜で覆われていない前記個別電極の電極端子と、前記ドライバICとを接続するワイヤとを備え、前記段差部または合金部は、前記複数の個別電極のそれぞれの電極端子に形成されている。
本発明の第12の態様によると、サーマルヘッドは、第9の態様の配線基板と、前記基板上に設けられたグレーズ層と、前記グレーズ層上に設けられた発熱抵抗体と、前記グレーズ層上に設けられた共通電極および複数の個別電極と、前記個別電極の一部を覆う絶縁性の保護膜と、前記個別電極に電流を流すドライバICと、前記保護膜で覆われていない前記個別電極の電極端子と、前記ドライバICとを接続するワイヤとを備え、前記重なり部または非重なり部は、前記複数の個別電極のそれぞれに形成されている。
本発明の第13の態様によると、配線基板の製造方法は、絶縁性の基板上に、第1導電層と前記第1導電層よりもイオン化傾向が小さい第2導電層とを積層して配置し、前記第1導電層および前記第2導電層に対して、一度のエッチング処理により、前記第2導電層が前記第1導電層よりも側方に突出した段差部または合金部を、前記第1導電層と前記第2導電層との境界外周部に形成する。 According to the first aspect of the present invention, the wiring board includes an insulating substrate, and a first conductive layer and a second conductive layer stacked on the substrate, and the second conductive layer includes the first conductive layer. A stepped portion or alloy in which the ionization tendency is smaller than that of one conductive layer, and the second conductive layer protrudes laterally from the first conductive layer by a single etching process on the first conductive layer and the second conductive layer. The portion is provided on the outer periphery of the boundary between the first conductive layer and the second conductive layer.
According to the second aspect of the present invention, in the wiring board of the first aspect, it is preferable that the first conductive layer is provided on the second conductive layer.
According to the third aspect of the present invention, in the wiring substrate according to the first aspect, it is preferable that the second conductive layer is provided on the first conductive layer.
According to the fourth aspect of the present invention, in the wiring board according to any one of the first to third aspects, it is preferable that the stepped portion or the alloy portion is exposed.
According to a fifth aspect of the present invention, there is provided the wiring board according to any one of the first to third aspects, the insulating substrate, the first conductive layer and the second layer laminated on the substrate. A conductive layer, and the second conductive layer has a smaller ionization tendency than the first conductive layer, and the second conductive layer is disposed at a boundary outer peripheral portion of the first conductive layer and the second conductive layer. A stepped portion or an alloy portion protruding laterally from the first conductive layer is formed, and is composed of positional accuracy between the first conductive layer and the second conductive layer or the first conductive layer and the second conductive layer. The width or interval of the laminated structure is set to 10 μm or less.
According to a sixth aspect of the present invention, in the wiring substrate according to the fifth aspect, it is preferable that the first conductive layer is provided on the second conductive layer.
According to a seventh aspect of the present invention, in the wiring substrate according to the fifth aspect, it is preferable that the second conductive layer is provided on the first conductive layer.
According to the eighth aspect of the present invention, in the wiring board according to any one of the fifth to seventh aspects, the stepped portion or the alloy portion is preferably exposed.
According to the ninth aspect of the present invention, the wiring board is provided on the same plane as the first conductive layer on the insulating board, the first conductive layer provided on the board, and the substrate. A second conductive layer having a smaller ionization tendency than the first conductive layer, wherein the second conductive layer overlaps with an edge of the first conductive layer, and the first conductive layer includes: A non-overlapping portion that does not overlap, and the non-overlapping portion is configured as an electrode terminal.
According to a tenth aspect of the present invention, the thermal head includes a wiring board according to any one of the first to fourth aspects, a glaze layer provided on the substrate, and a heat generation provided on the glaze layer. A resistor, a common electrode and a plurality of individual electrodes provided on the glaze layer, an insulating protective film that covers a part of the individual electrodes, a driver IC that allows current to flow through the individual electrodes, and the protective film The stepped portion or the alloy portion is formed on each electrode terminal of the plurality of individual electrodes. The electrode portion of the individual electrode that is not covered with a wire and a wire that connects the driver IC.
According to an eleventh aspect of the present invention, the thermal head includes a wiring board according to any one of the fifth to eighth aspects, a glaze layer provided on the substrate, and a heat generation provided on the glaze layer. A resistor, a common electrode and a plurality of individual electrodes provided on the glaze layer, an insulating protective film that covers a part of the individual electrodes, a driver IC that allows current to flow through the individual electrodes, and the protective film The stepped portion or the alloy portion is formed on each electrode terminal of the plurality of individual electrodes. The electrode portion of the individual electrode that is not covered with a wire and a wire that connects the driver IC.
According to a twelfth aspect of the present invention, a thermal head includes a wiring board according to the ninth aspect, a glaze layer provided on the substrate, a heating resistor provided on the glaze layer, and the glaze layer. A common electrode and a plurality of individual electrodes provided on the top, an insulating protective film covering a part of the individual electrodes, a driver IC for passing a current to the individual electrodes, and the individual not covered with the protective film The electrode terminal of an electrode and the wire which connects the said driver IC are provided, The said overlap part or a non-overlap part is formed in each of these individual electrodes.
According to the thirteenth aspect of the present invention, in the method for manufacturing a wiring board, the first conductive layer and the second conductive layer having a lower ionization tendency than the first conductive layer are stacked on the insulating substrate. The stepped portion or the alloy portion in which the second conductive layer protrudes laterally from the first conductive layer by the etching process once with respect to the first conductive layer and the second conductive layer, Formed on the outer periphery of the boundary between one conductive layer and the second conductive layer.
本発明の第2の態様によると、第1の態様の配線基板において、前記第1導電層は前記第2導電層上に設けられていることが好ましい。
本発明の第3の態様によると、第1の態様の配線基板において、前記第2導電層は前記第1導電層上に設けられていることが好ましい。
本発明の第4の態様によると、第1から第3までのいずれかの態様の配線基板において、前記段差部または前記合金部は露出されていることが好ましい。
本発明の第5の態様によると、配線基板は、第1から第3までのいずれかの態様の配線基板において、絶縁性の基板と、前記基板上において積層された第1導電層および第2導電層と、を備え、前記第2導電層は、前記第1導電層よりもイオン化傾向が小さく、前記第1導電層と前記第2導電層の境界外周部には、前記第2導電層が前記第1導電層よりも側方に突出した段差部または合金部が形成され、前記第1導電層と前記第2導電層との位置精度または前記第1導電層および前記第2導電層からなる積層構造体の幅または間隔が、10μm以下とされている。
本発明の第6の態様によると、第5の態様の配線基板において、前記第1導電層は前記第2導電層上に設けられていることが好ましい。
本発明の第7の態様によると、第5の態様の配線基板において、前記第2導電層は前記第1導電層上に設けられていることが好ましい。
本発明の第8の態様によると、第5から第7までのいずれかの態様の配線基板において、前記段差部または合金部は露出されていることが好ましい。
本発明の第9の態様によると、配線基板は、絶縁性の基板と、前記基板上に設けられた第1導電層と、前記基板上において、前記第1導電層と同一平面上に設けられ、前記第1導電層よりもイオン化傾向が小さい第2導電層と、を備え、前記第2導電層は、前記第1導電層の縁部上に重なる重なり部と、前記第1導電層とは重ならない非重なり部とを有し、前記非重なり部が電極端子として構成されている。
本発明の第10の態様によると、サーマルヘッドは、第1から第4までのいずれかの態様の配線基板と、前記基板上に設けられたグレーズ層と、前記グレーズ層上に設けられた発熱抵抗体と、前記グレーズ層上に設けられた共通電極および複数の個別電極と、前記個別電極の一部を覆う絶縁性の保護膜と、前記個別電極に電流を流すドライバICと、前記保護膜で覆われていない前記個別電極の電極端子と、前記ドライバICとを接続するワイヤとを備え、前記段差部または合金部は、前記複数の個別電極のそれぞれの電極端子に形成されている。
本発明の第11の態様によると、サーマルヘッドは、第5から第8までのいずれかの態様の配線基板と、前記基板上に設けられたグレーズ層と、前記グレーズ層上に設けられた発熱抵抗体と、前記グレーズ層上に設けられた共通電極および複数の個別電極と、前記個別電極の一部を覆う絶縁性の保護膜と、前記個別電極に電流を流すドライバICと、前記保護膜で覆われていない前記個別電極の電極端子と、前記ドライバICとを接続するワイヤとを備え、前記段差部または合金部は、前記複数の個別電極のそれぞれの電極端子に形成されている。
本発明の第12の態様によると、サーマルヘッドは、第9の態様の配線基板と、前記基板上に設けられたグレーズ層と、前記グレーズ層上に設けられた発熱抵抗体と、前記グレーズ層上に設けられた共通電極および複数の個別電極と、前記個別電極の一部を覆う絶縁性の保護膜と、前記個別電極に電流を流すドライバICと、前記保護膜で覆われていない前記個別電極の電極端子と、前記ドライバICとを接続するワイヤとを備え、前記重なり部または非重なり部は、前記複数の個別電極のそれぞれに形成されている。
本発明の第13の態様によると、配線基板の製造方法は、絶縁性の基板上に、第1導電層と前記第1導電層よりもイオン化傾向が小さい第2導電層とを積層して配置し、前記第1導電層および前記第2導電層に対して、一度のエッチング処理により、前記第2導電層が前記第1導電層よりも側方に突出した段差部または合金部を、前記第1導電層と前記第2導電層との境界外周部に形成する。 According to the first aspect of the present invention, the wiring board includes an insulating substrate, and a first conductive layer and a second conductive layer stacked on the substrate, and the second conductive layer includes the first conductive layer. A stepped portion or alloy in which the ionization tendency is smaller than that of one conductive layer, and the second conductive layer protrudes laterally from the first conductive layer by a single etching process on the first conductive layer and the second conductive layer. The portion is provided on the outer periphery of the boundary between the first conductive layer and the second conductive layer.
According to the second aspect of the present invention, in the wiring board of the first aspect, it is preferable that the first conductive layer is provided on the second conductive layer.
According to the third aspect of the present invention, in the wiring substrate according to the first aspect, it is preferable that the second conductive layer is provided on the first conductive layer.
According to the fourth aspect of the present invention, in the wiring board according to any one of the first to third aspects, it is preferable that the stepped portion or the alloy portion is exposed.
According to a fifth aspect of the present invention, there is provided the wiring board according to any one of the first to third aspects, the insulating substrate, the first conductive layer and the second layer laminated on the substrate. A conductive layer, and the second conductive layer has a smaller ionization tendency than the first conductive layer, and the second conductive layer is disposed at a boundary outer peripheral portion of the first conductive layer and the second conductive layer. A stepped portion or an alloy portion protruding laterally from the first conductive layer is formed, and is composed of positional accuracy between the first conductive layer and the second conductive layer or the first conductive layer and the second conductive layer. The width or interval of the laminated structure is set to 10 μm or less.
According to a sixth aspect of the present invention, in the wiring substrate according to the fifth aspect, it is preferable that the first conductive layer is provided on the second conductive layer.
According to a seventh aspect of the present invention, in the wiring substrate according to the fifth aspect, it is preferable that the second conductive layer is provided on the first conductive layer.
According to the eighth aspect of the present invention, in the wiring board according to any one of the fifth to seventh aspects, the stepped portion or the alloy portion is preferably exposed.
According to the ninth aspect of the present invention, the wiring board is provided on the same plane as the first conductive layer on the insulating board, the first conductive layer provided on the board, and the substrate. A second conductive layer having a smaller ionization tendency than the first conductive layer, wherein the second conductive layer overlaps with an edge of the first conductive layer, and the first conductive layer includes: A non-overlapping portion that does not overlap, and the non-overlapping portion is configured as an electrode terminal.
According to a tenth aspect of the present invention, the thermal head includes a wiring board according to any one of the first to fourth aspects, a glaze layer provided on the substrate, and a heat generation provided on the glaze layer. A resistor, a common electrode and a plurality of individual electrodes provided on the glaze layer, an insulating protective film that covers a part of the individual electrodes, a driver IC that allows current to flow through the individual electrodes, and the protective film The stepped portion or the alloy portion is formed on each electrode terminal of the plurality of individual electrodes. The electrode portion of the individual electrode that is not covered with a wire and a wire that connects the driver IC.
According to an eleventh aspect of the present invention, the thermal head includes a wiring board according to any one of the fifth to eighth aspects, a glaze layer provided on the substrate, and a heat generation provided on the glaze layer. A resistor, a common electrode and a plurality of individual electrodes provided on the glaze layer, an insulating protective film that covers a part of the individual electrodes, a driver IC that allows current to flow through the individual electrodes, and the protective film The stepped portion or the alloy portion is formed on each electrode terminal of the plurality of individual electrodes. The electrode portion of the individual electrode that is not covered with a wire and a wire that connects the driver IC.
According to a twelfth aspect of the present invention, a thermal head includes a wiring board according to the ninth aspect, a glaze layer provided on the substrate, a heating resistor provided on the glaze layer, and the glaze layer. A common electrode and a plurality of individual electrodes provided on the top, an insulating protective film covering a part of the individual electrodes, a driver IC for passing a current to the individual electrodes, and the individual not covered with the protective film The electrode terminal of an electrode and the wire which connects the said driver IC are provided, The said overlap part or a non-overlap part is formed in each of these individual electrodes.
According to the thirteenth aspect of the present invention, in the method for manufacturing a wiring board, the first conductive layer and the second conductive layer having a lower ionization tendency than the first conductive layer are stacked on the insulating substrate. The stepped portion or the alloy portion in which the second conductive layer protrudes laterally from the first conductive layer by the etching process once with respect to the first conductive layer and the second conductive layer, Formed on the outer periphery of the boundary between one conductive layer and the second conductive layer.
本発明によれば、マイグレーションが抑制された信頼性の高い配線基板であって、より高密度な配線基板を提供することができる。
According to the present invention, it is possible to provide a highly reliable wiring board which is highly reliable with suppressed migration.
-第1の実施の形態-
図1は、サーマルヘッド100の構成を示す断面模式図である。図2は、従来のサーマルヘッド100の要部を示す模式図である。図2(a)は、サーマルヘッド100の要部平面模式図であり、図2(b)は、サーマルヘッド100の要部断面模式図である。なお、図2(a)の平面模式図では、説明の便宜上、図2(b)において各構成の断面を表すハッチングを付している。図3は、図2のワイヤボンディング部を拡大して示す模式図である。図1に示すように、サーマルヘッド100は、支持板32上に固定された配線基板50およびプリント配線板30を備える。プリント配線板30上には、ドライバIC11と、印刷制御等を行う外部機器にサーマルヘッド100を接続するためのコネクタ31が設けられている。 -First embodiment-
FIG. 1 is a schematic cross-sectional view showing the configuration of thethermal head 100. FIG. 2 is a schematic diagram showing a main part of a conventional thermal head 100. FIG. 2A is a schematic plan view of a main part of the thermal head 100, and FIG. 2B is a schematic cross-sectional view of the main part of the thermal head 100. In addition, in the schematic plan view of FIG. 2A, for convenience of explanation, hatching that represents a cross section of each component in FIG. FIG. 3 is an enlarged schematic view showing the wire bonding portion of FIG. As shown in FIG. 1, the thermal head 100 includes a wiring board 50 and a printed wiring board 30 fixed on a support plate 32. On the printed wiring board 30, a driver IC 11 and a connector 31 for connecting the thermal head 100 to an external device that performs printing control and the like are provided.
図1は、サーマルヘッド100の構成を示す断面模式図である。図2は、従来のサーマルヘッド100の要部を示す模式図である。図2(a)は、サーマルヘッド100の要部平面模式図であり、図2(b)は、サーマルヘッド100の要部断面模式図である。なお、図2(a)の平面模式図では、説明の便宜上、図2(b)において各構成の断面を表すハッチングを付している。図3は、図2のワイヤボンディング部を拡大して示す模式図である。図1に示すように、サーマルヘッド100は、支持板32上に固定された配線基板50およびプリント配線板30を備える。プリント配線板30上には、ドライバIC11と、印刷制御等を行う外部機器にサーマルヘッド100を接続するためのコネクタ31が設けられている。 -First embodiment-
FIG. 1 is a schematic cross-sectional view showing the configuration of the
配線基板50について詳細に説明する。配線基板50は、絶縁基板12上に配線、電極が形成されているものである。絶縁基板12は、電気的絶縁性を有するセラミックなどによって形成される。絶縁基板12の上面全体には、ガラス等からなるグレーズ層13が形成されている。グレーズ層13は、後述の発熱抵抗体6の温度を上昇させるのに必要な時間を短縮して、サーマルヘッド100の熱応答特性を高める蓄熱層としての役割を担っている。
The wiring board 50 will be described in detail. The wiring board 50 has wirings and electrodes formed on the insulating substrate 12. The insulating substrate 12 is formed of an electrically insulating ceramic or the like. A glaze layer 13 made of glass or the like is formed on the entire top surface of the insulating substrate 12. The glaze layer 13 serves as a heat storage layer that shortens the time required to raise the temperature of the heating resistor 6 described later and enhances the thermal response characteristics of the thermal head 100.
グレーズ層13の上面には、共通電極5および複数の個別電極8が形成されている。図2(a)に示すように、共通電極5は、平面視矩形状の電極面5aと、この電極面5aから感熱紙(不図示)の搬送方向(図2(a)に示すx方向)に沿って延びる複数の帯状電極5bを備えた櫛歯状とされている。複数の個別電極8は、それぞれ搬送方向xに沿って延びる帯状とされている。複数の帯状電極5bと複数の個別電極8は、搬送方向xに直交するy方向に交互に配置されている。
A common electrode 5 and a plurality of individual electrodes 8 are formed on the upper surface of the glaze layer 13. As shown in FIG. 2A, the common electrode 5 includes a rectangular electrode surface 5a in a plan view and a conveyance direction of thermal paper (not shown) from the electrode surface 5a (the x direction shown in FIG. 2A). It is made into the comb-tooth shape provided with the some strip | belt-shaped electrode 5b extended along. Each of the plurality of individual electrodes 8 has a strip shape extending along the transport direction x. The plurality of strip electrodes 5 b and the plurality of individual electrodes 8 are alternately arranged in the y direction orthogonal to the transport direction x.
共通電極5および複数の個別電極8の上には、厚膜印刷などにより、直線状の発熱抵抗体6が形成されている。発熱抵抗体6は、複数の帯状電極5bと複数の個別電極8を跨がるように、y方向に沿って延びている。発熱抵抗体6は、たとえば、酸化ルテニウム(RuO2)等からなる。
A linear heating resistor 6 is formed on the common electrode 5 and the plurality of individual electrodes 8 by thick film printing or the like. The heating resistor 6 extends along the y direction so as to straddle the plurality of strip electrodes 5b and the plurality of individual electrodes 8. The heating resistor 6, for example, made of ruthenium oxide (RuO 2) or the like.
図1に示すように、各個別電極8の一端は、金ワイヤ10を介してドライバIC11に接続されている。金ワイヤ10およびドライバIC11は、エポキシ樹脂材からなる封止樹脂16によりモールドされている。ドライバIC22のドライバ回路(不図示)は、共通電極5から発熱抵抗体6を介して各個別電極8に電流を流す。図2(a)に示すように、共通電極5における帯状電極5bと個別電極8との間にある発熱抵抗体6に電流が流れると、その部分が発熱する。この熱が感熱紙(不図示)に伝わると、感熱紙が発色し、感熱紙に所定の印刷画像が形成される。
As shown in FIG. 1, one end of each individual electrode 8 is connected to a driver IC 11 via a gold wire 10. The gold wire 10 and the driver IC 11 are molded with a sealing resin 16 made of an epoxy resin material. A driver circuit (not shown) of the driver IC 22 causes a current to flow from the common electrode 5 to each individual electrode 8 via the heating resistor 6. As shown in FIG. 2A, when a current flows through the heating resistor 6 between the strip electrode 5b and the individual electrode 8 in the common electrode 5, the portion generates heat. When this heat is transmitted to thermal paper (not shown), the thermal paper develops color and a predetermined print image is formed on the thermal paper.
図2に示すように、サーマルヘッド100には、各個別電極8、共通電極5および発熱抵抗体6を覆うように、絶縁基板12の表面全体に絶縁性保護膜7が形成されている。絶縁性保護膜7は、たとえば、電気的絶縁性を有するPbO-SiO2-ZrO2系のガラス材料からなる。発熱抵抗体6が絶縁性保護膜7によって覆われているので、感熱紙(不図示)には、絶縁性保護膜7を介して発熱抵抗体6の熱が伝達される。
As shown in FIG. 2, in the thermal head 100, an insulating protective film 7 is formed on the entire surface of the insulating substrate 12 so as to cover the individual electrodes 8, the common electrode 5, and the heating resistor 6. The insulating protective film 7 is made of, for example, a PbO—SiO 2 —ZrO 2 glass material having electrical insulation. Since the heating resistor 6 is covered with the insulating protective film 7, the heat of the heating resistor 6 is transmitted to the thermal paper (not shown) through the insulating protective film 7.
図2および図3に示すように、従来、絶縁基板12上に低純度金含有ペーストを用いて低純度金層14を形成し、低純度金層14の上層に高純度金含有ペーストを用いて形成された高純度金層15を積層することで個別電極8の電極端子であるワイヤボンディング部9が形成されていた。
As shown in FIGS. 2 and 3, conventionally, a low purity gold-containing paste 14 is formed on an insulating substrate 12 using a low-purity gold-containing paste, and a high-purity gold-containing paste is used as an upper layer of the low-purity gold layer 14. The wire bonding part 9 which is an electrode terminal of the individual electrode 8 was formed by laminating the formed high purity gold layer 15.
金(Au)は、銀(Ag)に比べてマイグレーションが発生しにくい金属であるが、非常に高価で、製造コスト増となる。そこで、金に代えて、銀などの金に比べて低価格の材料を用いることが考えられるが、金に比べてマイグレーションが発生しやすいという課題がある。
Gold (Au) is a metal that is less prone to migration than silver (Ag), but is very expensive and increases manufacturing costs. Therefore, it is conceivable to use a material that is less expensive than gold, such as silver, instead of gold, but there is a problem that migration is likely to occur compared to gold.
図4は、図3と同様の図であり、第1の実施の形態に係るサーマルヘッド100Aの要部を示す模式図である。図4(a)はサーマルヘッド100Aの要部平面模式図であり、図4(b)はサーマルヘッド100Aの要部断面模式図である。
FIG. 4 is a view similar to FIG. 3, and is a schematic view showing the main part of the thermal head 100A according to the first embodiment. 4A is a schematic plan view of the main part of the thermal head 100A, and FIG. 4B is a schematic cross-sectional view of the main part of the thermal head 100A.
本実施の形態では、高価な金の使用量を抑えるために、個別電極8のワイヤボンディング部18の一部に金を使用し、その他の部分には銀を使用することとした。また、y方向に隣接する複数のワイヤボンディング部18のそれぞれにおいて、銀からなる第1導電層のサイズに比べて、金からなる第2導電層のサイズを大きくする。このようにすることで、ワイヤボンディング部18の最外周部が金からなる第2導電層となるようにして、マイグレーションを抑制することとした。さらに、2種類の導電層のエッチング速度が異なるという特性を利用して、2種類の導電層に対して、一度のエッチング処理により、第2導電層を第1導電層よりも側方に突出させてなる段差部23または合金層(合金部)24をワイヤボンディング部18の外周部に形成するようにした。エッチング処理により、微細パターンを形成することができるので、高密度配線を実現できる。以下、詳細に説明する。
In this embodiment, in order to suppress the amount of expensive gold used, gold is used for a part of the wire bonding part 18 of the individual electrode 8 and silver is used for the other part. In each of the plurality of wire bonding portions 18 adjacent in the y direction, the size of the second conductive layer made of gold is made larger than the size of the first conductive layer made of silver. By doing in this way, the outermost peripheral part of the wire bonding part 18 became the 2nd conductive layer which consists of gold | metal | money, and decided to suppress a migration. Further, by utilizing the characteristic that the etching rates of the two types of conductive layers are different, the second conductive layer is protruded to the side of the first conductive layer by one etching process for the two types of conductive layers. The step portion 23 or the alloy layer (alloy portion) 24 is formed on the outer peripheral portion of the wire bonding portion 18. Since a fine pattern can be formed by etching, high-density wiring can be realized. Details will be described below.
本実施の形態に係るサーマルヘッド100Aは、個別電極17の構成が従来のサーマルヘッド100の個別電極17とは異なるが、その他の構成は同じであるので説明を省略する。第1の実施の形態に係るサーマルヘッド100Aの個別電極17は、x方向に延びる配線部が銀からなる銀層(第1導電層)20からなる。個別電極17のx方向端部には、ワイヤボンディングされるワイヤボンディング部18が電極端子として設けられている。
In the thermal head 100A according to the present embodiment, the configuration of the individual electrode 17 is different from that of the individual electrode 17 of the conventional thermal head 100, but the other configuration is the same, and the description thereof is omitted. The individual electrode 17 of the thermal head 100A according to the first embodiment includes a silver layer (first conductive layer) 20 in which a wiring portion extending in the x direction is made of silver. A wire bonding portion 18 to be wire-bonded is provided as an electrode terminal at an end portion of the individual electrode 17 in the x direction.
本明細書では、絶縁性保護膜7で覆われていない個別電極17の露出部である電極端子をワイヤボンディング部18と呼ぶ。ワイヤボンディング部18は、グレーズ層13を介して絶縁基板12上に設けられた金からなる金層(第2導電層)19と、金層19上に設けられた銀層20からなる積層構造とされている。金層19は、銀層20に比べて、xy平面上の面積が一回り大きいサイズであり、金層19と銀層20の境界外周部に段差部23または合金層24が形成されている。
In this specification, an electrode terminal that is an exposed portion of the individual electrode 17 that is not covered with the insulating protective film 7 is referred to as a wire bonding portion 18. The wire bonding portion 18 has a laminated structure including a gold layer (second conductive layer) 19 made of gold provided on the insulating substrate 12 via the glaze layer 13 and a silver layer 20 provided on the gold layer 19. Has been. The gold layer 19 has a size that is slightly larger in area on the xy plane than the silver layer 20, and a stepped portion 23 or an alloy layer 24 is formed on the outer periphery of the boundary between the gold layer 19 and the silver layer 20.
ワイヤボンディング部18は、絶縁性保護膜7で覆われていないので、隣り合うワイヤボンディング部18間でマイグレーションが発生することを抑制する必要が生じる。本実施の形態では、マイグレーションの発生を防止するために、上述のとおり、ワイヤボンディング部18において、金層19の外周サイズを銀層20の外周サイズよりも一回り大きくなるようにした。このようなワイヤボンディング部18の形成方法について、図5~図7を参照して説明する。なお、図5~図7では、説明をわかりやすくするために、単純な形状で説明する。図5~図7では、グレーズ層を省略している。
Since the wire bonding portion 18 is not covered with the insulating protective film 7, it is necessary to suppress the occurrence of migration between adjacent wire bonding portions 18. In the present embodiment, in order to prevent the occurrence of migration, the outer peripheral size of the gold layer 19 is made slightly larger than the outer peripheral size of the silver layer 20 in the wire bonding portion 18 as described above. A method for forming the wire bonding portion 18 will be described with reference to FIGS. In FIGS. 5 to 7, a simple shape is used for easy understanding. 5 to 7, the glaze layer is omitted.
(金層および銀層形成工程)
図5(a)はエッチング処理前の配線基板の平面模式図であり、図5(b)はエッチング処理前の配線基板の側面断面模式図であり、図5(a)のvb-vb線切断断面を示している。図5に示すように、矩形平板状の絶縁基板1の上に、金のペースト状組成物(たとえば金の含有量は15~100重量%)を、絶縁基板1の短手方向に平行に延在する矩形状のパターンで印刷を行う。その後、銀のペースト状組成物(たとえば銀の含有量は15~100重量%)を、金のペースト状組成物のパターンを覆うように、絶縁基板1よりも一回り小さいサイズの矩形状のパターンで印刷を行う。その後、絶縁基板1の焼成(たとえば800℃程度)を行うことで金層2および銀層3を形成する。焼成により、金層2と銀層3の境界部分には、金と銀の合金層4が形成される(図5において不図示、図7参照)。つまり、印刷、焼成により、絶縁基板1上に、金層2と銀層3とを積層して配置する。なお、本実施の形態では、印刷により、上述の段差部23を形成するものではないので、この工程において、高い精度は要求されない。 (Gold layer and silver layer forming process)
FIG. 5A is a schematic plan view of the wiring board before the etching process, and FIG. 5B is a schematic side sectional view of the wiring board before the etching process, taken along the line vb-vb in FIG. A cross section is shown. As shown in FIG. 5, a gold paste composition (for example, the gold content is 15 to 100% by weight) is extended on a rectangular flat plate-like insulatingsubstrate 1 in parallel to the short direction of the insulating substrate 1. Printing is performed with an existing rectangular pattern. Thereafter, a silver paste-like composition (for example, the silver content is 15 to 100% by weight) is a rectangular pattern having a size slightly smaller than that of the insulating substrate 1 so as to cover the pattern of the gold paste-like composition. Print with. Then, the gold layer 2 and the silver layer 3 are formed by baking the insulating substrate 1 (for example, about 800 ° C.). By firing, a gold-silver alloy layer 4 is formed at the boundary between the gold layer 2 and the silver layer 3 (not shown in FIG. 5, see FIG. 7). That is, the gold layer 2 and the silver layer 3 are laminated and disposed on the insulating substrate 1 by printing and baking. In the present embodiment, since the above-described step portion 23 is not formed by printing, high accuracy is not required in this step.
図5(a)はエッチング処理前の配線基板の平面模式図であり、図5(b)はエッチング処理前の配線基板の側面断面模式図であり、図5(a)のvb-vb線切断断面を示している。図5に示すように、矩形平板状の絶縁基板1の上に、金のペースト状組成物(たとえば金の含有量は15~100重量%)を、絶縁基板1の短手方向に平行に延在する矩形状のパターンで印刷を行う。その後、銀のペースト状組成物(たとえば銀の含有量は15~100重量%)を、金のペースト状組成物のパターンを覆うように、絶縁基板1よりも一回り小さいサイズの矩形状のパターンで印刷を行う。その後、絶縁基板1の焼成(たとえば800℃程度)を行うことで金層2および銀層3を形成する。焼成により、金層2と銀層3の境界部分には、金と銀の合金層4が形成される(図5において不図示、図7参照)。つまり、印刷、焼成により、絶縁基板1上に、金層2と銀層3とを積層して配置する。なお、本実施の形態では、印刷により、上述の段差部23を形成するものではないので、この工程において、高い精度は要求されない。 (Gold layer and silver layer forming process)
FIG. 5A is a schematic plan view of the wiring board before the etching process, and FIG. 5B is a schematic side sectional view of the wiring board before the etching process, taken along the line vb-vb in FIG. A cross section is shown. As shown in FIG. 5, a gold paste composition (for example, the gold content is 15 to 100% by weight) is extended on a rectangular flat plate-like insulating
(フォトリソグラフィ・エッチング工程)
図5において一点鎖線で示すような略H字状のパターンをフォトリソグラフィにより形成する。その後、ウエットエッチング処理を一回施すことにより、すなわち配線基板をエッチング液に浸漬させることにより、図5(a)に示す一点鎖線で囲まれる部分3a(略H字状パターン)以外の部分を溶解除去する。 (Photolithography / etching process)
In FIG. 5, a substantially H-shaped pattern as shown by a one-dot chain line is formed by photolithography. Thereafter, by performing wet etching once, that is, by immersing the wiring board in the etching solution, portions other than theportion 3a (substantially H-shaped pattern) surrounded by the alternate long and short dash line shown in FIG. 5A are dissolved. Remove.
図5において一点鎖線で示すような略H字状のパターンをフォトリソグラフィにより形成する。その後、ウエットエッチング処理を一回施すことにより、すなわち配線基板をエッチング液に浸漬させることにより、図5(a)に示す一点鎖線で囲まれる部分3a(略H字状パターン)以外の部分を溶解除去する。 (Photolithography / etching process)
In FIG. 5, a substantially H-shaped pattern as shown by a one-dot chain line is formed by photolithography. Thereafter, by performing wet etching once, that is, by immersing the wiring board in the etching solution, portions other than the
ここで、金層2を構成する金は、銀層3を構成する銀よりもイオン化傾向が小さい材質である。このため、金層2の溶解速度(エッチング速度)は、銀層3の溶解速度(エッチング速度)よりも遅い。本実施の形態では、ヨウ素、ヨウ化カリウム、水の混合割合を、1:2:10(wt比)としたヨウ化カリウム溶液をエッチング液として用いた。この場合、金層2と銀層3とでは、側方にむかって溶解が進む速度(サイドエッチング速度)に3倍程度の差が生じる。
Here, the gold constituting the gold layer 2 is a material having a smaller ionization tendency than the silver constituting the silver layer 3. For this reason, the dissolution rate (etching rate) of the gold layer 2 is slower than the dissolution rate (etching rate) of the silver layer 3. In this embodiment, a potassium iodide solution in which the mixing ratio of iodine, potassium iodide, and water is 1: 2: 10 (wt ratio) is used as an etching solution. In this case, the gold layer 2 and the silver layer 3 have a difference of about three times in the speed (side etching speed) at which the dissolution proceeds toward the side.
図6(a)はエッチング処理後の配線基板の平面模式図であり、図6(b)はエッチング処理後の配線基板の側面断面模式図であり、図6(a)のvib-vib線切断断面を示している。図7(a)は図6(a)のVII部を示す部分拡大図であり、図7(b)は図7(a)のviib-viib線断面模式図である。図6および図7に示すように、エッチング処理では、外表面からエッチングが進行するので、銀層3のうち、上部が最も溶解され、下方に向かって溶解量が小さくなっている。このため、図7に示すように、一対の略H字状パターン間の溝26における対向する側面間寸法は、上部から下部に向かって短くなっている。金層2においても上部が最も溶解され、下方に向かって溶解量が小さくなっている。このため、一対の略H字状パターン間の溝27における対向する側面間寸法は、上部から下部に向かって短くなっている。
6A is a schematic plan view of the wiring board after the etching process, FIG. 6B is a schematic side sectional view of the wiring board after the etching process, and is cut along the vib-vib line in FIG. 6A. A cross section is shown. FIG. 7A is a partially enlarged view showing a VII portion in FIG. 6A, and FIG. 7B is a schematic cross-sectional view taken along the line viib-viib in FIG. 7A. As shown in FIGS. 6 and 7, in the etching process, since the etching proceeds from the outer surface, the upper part of the silver layer 3 is dissolved most and the amount of dissolution is decreased downward. For this reason, as shown in FIG. 7, the dimension between the side surfaces which oppose in the groove | channel 26 between a pair of substantially H-shaped pattern is short toward the lower part from the upper part. In the gold layer 2 as well, the upper part is dissolved most, and the amount of dissolution decreases downward. For this reason, the dimension between the side surfaces which oppose in the groove | channel 27 between a pair of substantially H-shaped patterns is short toward the lower part from the upper part.
なお、上述したように、金層2と銀層3とでは、銀層3の溶解速度の方が金層2の溶解速度よりも速い。このため、溝26の間隔は、溝27の間隔よりも大きい。
As described above, in the gold layer 2 and the silver layer 3, the dissolution rate of the silver layer 3 is faster than the dissolution rate of the gold layer 2. For this reason, the interval between the grooves 26 is larger than the interval between the grooves 27.
溝26の側面は、銀層3の上部から下方に向かうほど側方(外方)に広がる傾斜面とされている。同様に、溝27の側面は、金層2の上部から下方に向かうほど側方(外方)に広がる傾斜面とされている。金層2は、銀層3に比べて溶解速度が遅いので、銀層3と金層2との境界外周部において段差部23が形成される。金層2は、銀層3に比べて側方に1μm程度突出するように形成される。また、焼成により形成された合金層4が、エッチング処理により露出される。つまり、エッチング処理により、金層2と銀層3の境界外周部に、金と銀の合金層4が形成される。積層構造部における外周側に、金層2が配置されること、および、金と銀の合金層4が形成されることにより、マイグレーションの抑制効果が向上し、かつ、硫化を抑制する効果も向上する。
The side surface of the groove 26 is an inclined surface that spreads laterally (outward) from the top of the silver layer 3 downward. Similarly, the side surface of the groove 27 is an inclined surface that spreads sideward (outward) from the top of the gold layer 2 toward the lower side. Since the dissolution rate of the gold layer 2 is slower than that of the silver layer 3, a stepped portion 23 is formed at the outer periphery of the boundary between the silver layer 3 and the gold layer 2. The gold layer 2 is formed so as to protrude about 1 μm to the side as compared with the silver layer 3. Further, the alloy layer 4 formed by firing is exposed by the etching process. That is, the gold and silver alloy layer 4 is formed on the outer periphery of the boundary between the gold layer 2 and the silver layer 3 by the etching process. By arranging the gold layer 2 on the outer peripheral side of the laminated structure and forming the alloy layer 4 of gold and silver, the effect of suppressing migration is improved and the effect of suppressing sulfidation is also improved. To do.
図8~図10を参照して、マイグレーションの抑制効果および硫化の抑制効果について説明する。図8および図9は、配線基板のマイグレーション耐性についての実験結果を示すグラフおよび表である。実験に用いた配線基板には、電極長30mm、電極間を100μmとしたパターンを形成した。金層2の上に銀層3を積層した後、金層2および銀層3に対して一度(同時)にフォトリソグラフィ・エッチング処理を行った。環境条件は、85℃,85%RHとした。この環境下で、直流32Vの電圧を印加し、連続して通電することにより、絶縁抵抗値が判定基準値である10MΩ以下になるまでの時間を計測した。
Referring to FIGS. 8 to 10, the effect of suppressing migration and the effect of suppressing sulfur will be described. 8 and 9 are a graph and a table showing experimental results on the migration resistance of the wiring board. On the wiring board used in the experiment, a pattern having an electrode length of 30 mm and a distance of 100 μm was formed. After the silver layer 3 was laminated on the gold layer 2, the gold layer 2 and the silver layer 3 were subjected to photolithography etching processing once (simultaneously). The environmental conditions were 85 ° C. and 85% RH. Under this environment, a voltage of DC 32V was applied and energized continuously to measure the time until the insulation resistance value became 10 MΩ or less, which is a determination reference value.
本実施の形態との比較例として、膜厚が0.66μmの金層2のみで電極を構成した配線基板を第1の比較例、膜厚が3.3μmの銀層3のみで電極を構成した配線基板を第2の比較例とする。本実施の形態の配線基板は、2種類準備し、それぞれ実験を行った。本実施の形態の第1の配線基板は、金層2の膜厚が0.25μm、銀層3の膜厚が0.80μmとされている。つまり、第1の配線基板は、金層2の膜厚が、銀層3の膜厚の1/3程度とされている。本実施の形態の第2の配線基板は、金層2の膜厚が1.00μm、銀層3の膜厚が1.57μmとされている。つまり、第2の配線基板は、金層2の膜厚が、銀層3の膜厚の2/3程度とされている。
As a comparative example with the present embodiment, a wiring board in which an electrode is formed only by a gold layer 2 having a film thickness of 0.66 μm is a first comparative example, and an electrode is formed by only a silver layer 3 having a film thickness of 3.3 μm The wiring board thus obtained is used as a second comparative example. Two types of wiring boards of the present embodiment were prepared, and experiments were conducted respectively. In the first wiring board of the present embodiment, the gold layer 2 has a thickness of 0.25 μm and the silver layer 3 has a thickness of 0.80 μm. That is, in the first wiring board, the thickness of the gold layer 2 is set to about 1/3 of the thickness of the silver layer 3. In the second wiring board of the present embodiment, the gold layer 2 has a thickness of 1.00 μm and the silver layer 3 has a thickness of 1.57 μm. That is, in the second wiring board, the film thickness of the gold layer 2 is about 2/3 of the film thickness of the silver layer 3.
図8および図9に示すように、第1の比較例801では、連続通電時間が2000時間を超えても絶縁抵抗値の低下はほとんどみられず、高いマイグレーション耐性結果が得られた。第2の比較例802では、連続通電時間が50時間に満たないうちに絶縁抵抗値が10MΩ(判定基準値)以下となった。このように、金層2と銀層3とでは、マイグレーション耐性に大きな差が生じる。ただし、第1の比較例801では、金層2のみで電極を構成しているので、コスト増となる。
As shown in FIGS. 8 and 9, in the first comparative example 801, even when the continuous energization time exceeded 2000 hours, the insulation resistance value hardly decreased and a high migration resistance result was obtained. In the second comparative example 802, the insulation resistance value became 10 MΩ (judgment reference value) or less before the continuous energization time was less than 50 hours. Thus, there is a large difference in migration resistance between the gold layer 2 and the silver layer 3. However, in the first comparative example 801, since the electrode is composed only of the gold layer 2, the cost increases.
図8および図9に示すように、本実施の形態の第1の配線基板の例803では、連続通電時間が200時間までは高い絶縁抵抗値を維持できる結果を得た。第1の配線基板では、第2の比較例802に比べて、マイグレーション耐性が大きく向上していることが確認できた。本実施の形態の第2の配線基板の例804では、連続通電時間が2000時間を超えても絶縁抵抗値の低下はほとんどみられず、高いマイグレーション耐性を得ることができることがわかった。この実験結果により、金層2の膜厚の比率を上げることで、マイグレーション耐性の向上を図ることができることがわかった。つまり、金層19と銀層20の膜厚の比率を変えることで、マイグレーションの抑制の度合いを必要に応じて調整することができる。
As shown in FIGS. 8 and 9, in Example 803 of the first wiring board of the present embodiment, a result that a high insulation resistance value can be maintained until the continuous energization time is 200 hours was obtained. It was confirmed that the migration resistance of the first wiring board was greatly improved as compared with the second comparative example 802. In Example 804 of the second wiring board of the present embodiment, it was found that even when the continuous energization time exceeds 2000 hours, the insulation resistance value hardly decreases and high migration resistance can be obtained. From this experimental result, it was found that the migration resistance can be improved by increasing the ratio of the thickness of the gold layer 2. That is, by changing the ratio of the film thickness of the gold layer 19 and the silver layer 20, the degree of suppression of migration can be adjusted as necessary.
図10は、配線基板の硫化耐性についての実験結果を示す表である。本実施の形態の比較例として、膜厚が0.65μmの金層2のみで電極を構成した配線基板を第3の比較例、膜厚が3.3μmの銀層3のみで電極を構成した配線基板を第4の比較例とする。本実施の形態の配線基板は、2種類準備し、それぞれ実験を行った。本実施の形態の第3の配線基板は、金層2の膜厚が0.3μm、銀層3の膜厚が3.3μmとされている。つまり、第3の配線基板は、金層2の膜厚が、銀層3の膜厚の1/10程度とされている。本実施の形態の第4の配線基板は、金層2の膜厚が3.3μm、銀層3の膜厚が0.3μmとされている。つまり、第4の配線基板は、金層2の膜厚が、銀層3の膜厚の10倍程度とされている。なお、第4の配線基板では、金層2が上層に配置され、銀層3が下層に配置される構成であり、後述の第2の実施の形態に相当するものである。
FIG. 10 is a table showing experimental results on the sulfurization resistance of the wiring board. As a comparative example of the present embodiment, a wiring board in which an electrode is constituted only by a gold layer 2 having a thickness of 0.65 μm is a third comparative example, and an electrode is constituted only by a silver layer 3 having a thickness of 3.3 μm. Let the wiring board be a fourth comparative example. Two types of wiring boards of the present embodiment were prepared, and experiments were conducted respectively. In the third wiring board of the present embodiment, the gold layer 2 has a thickness of 0.3 μm and the silver layer 3 has a thickness of 3.3 μm. That is, in the third wiring board, the thickness of the gold layer 2 is about 1/10 of the thickness of the silver layer 3. In the fourth wiring board of the present embodiment, the gold layer 2 has a thickness of 3.3 μm and the silver layer 3 has a thickness of 0.3 μm. That is, in the fourth wiring board, the film thickness of the gold layer 2 is about 10 times the film thickness of the silver layer 3. In the fourth wiring board, the gold layer 2 is arranged in the upper layer and the silver layer 3 is arranged in the lower layer, which corresponds to a second embodiment to be described later.
実験では、所定期間、各配線基板を放置し、抵抗値変動が+1%未満のものを非常に良好◎とし、抵抗値変動が+1%以上、+20%未満のものを良好○とし、抵抗値変動が+20%以上、+100%未満のものを不良△、抵抗値変動が+100%以上のものを劣悪×として判定した。
In the experiment, each wiring board is left unattended for a predetermined period. A resistance value fluctuation of less than + 1% is marked as very good. A resistance value fluctuation of + 1% or more and less than + 20% is marked as good. Of + 20% or more and less than + 100% was judged as bad Δ, and resistance value fluctuation of + 100% or more was judged as poor x.
図10に示すように、第3の比較例では、36ヶ月放置したとしても抵抗値変動がほとんどなく、非常に良好と判定された。第4の比較例では、1か月程度で不良と判定され、3カ月程度で劣悪と判定された。
As shown in FIG. 10, in the third comparative example, even if it was left for 36 months, there was almost no change in resistance value, and it was determined to be very good. In the fourth comparative example, it was determined to be defective in about one month, and was determined to be inferior in about three months.
本実施の形態の第3の配線基板では、12ヶ月放置したとしても抵抗値変動がほとんどなく、非常に良好と判定された。第3の配線基板では、36ヶ月放置したとしても良好と判定され、高い硫化耐性結果が得られた。第4の配線基板では、36ヶ月放置したとしても抵抗値変動がほとんどなく、非常に良好と判定された。この実験結果により、金層2と銀層3のいずれを下層側に配置するかに関らず、金層2と銀層3とを積層構造とすることで、高い硫化耐性を得ることができることがわかった。また、この実験結果により、金層2の膜厚の比率を上げることで、硫化耐性の向上を図ることができることがわかった。つまり、金層19と銀層20の膜厚の比率を変えることで、硫化の抑制の度合いを必要に応じて調整することができる。
In the third wiring board of the present embodiment, even when left for 12 months, there was almost no change in resistance value, and it was determined to be very good. The third wiring board was judged to be good even after being left for 36 months, and a high sulfidation resistance result was obtained. In the fourth wiring board, even when left for 36 months, there was almost no change in resistance value, and it was determined to be very good. According to this experimental result, regardless of whether the gold layer 2 or the silver layer 3 is arranged on the lower layer side, a high sulfidation resistance can be obtained by forming the gold layer 2 and the silver layer 3 in a laminated structure. I understood. Further, it was found from this experimental result that the resistance to sulfurization can be improved by increasing the ratio of the thickness of the gold layer 2. That is, by changing the ratio of the film thickness of the gold layer 19 and the silver layer 20, the degree of suppression of sulfidation can be adjusted as necessary.
上述した実施の形態によれば、次の作用効果が得られる。
(1)本実施の形態に係る配線基板は、絶縁基板1と、絶縁基板1上において積層された銀層3および金層2と、を備えている。金層2は、銀層3よりもイオン化傾向が小さい。銀層3および金層2に対する一度のエッチング処理により、金層2が銀層3よりも側方に突出した段差部23を、銀層3と金層2との境界外周部に設けた。金層2を銀層3よりも側方に突出させた段差部23または合金層24を設けることで、マイグレーション耐性を向上することができる。さらに、硫化耐性を向上することもできる。 According to the embodiment described above, the following operational effects can be obtained.
(1) The wiring board according to the present embodiment includes an insulatingsubstrate 1 and a silver layer 3 and a gold layer 2 laminated on the insulating substrate 1. The gold layer 2 has a smaller ionization tendency than the silver layer 3. By a single etching process on the silver layer 3 and the gold layer 2, a step portion 23 in which the gold layer 2 protrudes to the side of the silver layer 3 was provided at the boundary outer peripheral portion between the silver layer 3 and the gold layer 2. By providing the stepped portion 23 or the alloy layer 24 in which the gold layer 2 protrudes to the side of the silver layer 3, the migration resistance can be improved. Furthermore, the resistance to sulfurization can be improved.
(1)本実施の形態に係る配線基板は、絶縁基板1と、絶縁基板1上において積層された銀層3および金層2と、を備えている。金層2は、銀層3よりもイオン化傾向が小さい。銀層3および金層2に対する一度のエッチング処理により、金層2が銀層3よりも側方に突出した段差部23を、銀層3と金層2との境界外周部に設けた。金層2を銀層3よりも側方に突出させた段差部23または合金層24を設けることで、マイグレーション耐性を向上することができる。さらに、硫化耐性を向上することもできる。 According to the embodiment described above, the following operational effects can be obtained.
(1) The wiring board according to the present embodiment includes an insulating
(2)一度のエッチング処理により金層2を銀層3よりも側方に突出させた段差部23を形成することができるので、金層2と銀層3の位置ずれが生じることを防止できる。本実施の形態によれば、金層2と銀層3との位置精度(すなわち金層2と銀層3の相対的な位置ずれ量の最大値)を10μm以下とすることができる。また、金層2および銀層3からなる積層構造体により、幅寸法が5μm以下の微細パターンを形成することができる。さらに、金層2および銀層3からなる積層構造体同士の間隔を10μm以下とすることもできる。このため、特許文献1に記載の発明に比べて、より高密度な配線基板を提供することができる。
(2) Since the step portion 23 in which the gold layer 2 protrudes laterally from the silver layer 3 can be formed by a single etching process, it is possible to prevent the displacement of the gold layer 2 and the silver layer 3 from occurring. . According to the present embodiment, the positional accuracy between the gold layer 2 and the silver layer 3 (that is, the maximum value of the relative displacement between the gold layer 2 and the silver layer 3) can be 10 μm or less. Moreover, a fine pattern having a width dimension of 5 μm or less can be formed by the laminated structure including the gold layer 2 and the silver layer 3. Furthermore, the interval between the laminated structures composed of the gold layer 2 and the silver layer 3 can be set to 10 μm or less. For this reason, compared with the invention described in Patent Document 1, a higher-density wiring board can be provided.
(3)エッチング処理を複数回に分けて行う必要が無いので、製造工数を低減できる。
(3) Since there is no need to perform the etching process in multiple steps, the number of manufacturing steps can be reduced.
-第2の実施の形態-
図11~図14を参照して、第2の実施の形態に係るサーマルヘッド100Bについて説明する。図中、第1の実施の形態と同一または相当部分には同一符号を付し、相違点について主に説明する。図11は、図4と同様の図であり、第2の実施の形態に係るサーマルヘッド100Bの要部を示す模式図である。 -Second Embodiment-
Athermal head 100B according to the second embodiment will be described with reference to FIGS. In the figure, the same or corresponding parts as those in the first embodiment are denoted by the same reference numerals, and differences will be mainly described. FIG. 11 is a diagram similar to FIG. 4, and is a schematic diagram illustrating a main part of a thermal head 100 </ b> B according to the second embodiment.
図11~図14を参照して、第2の実施の形態に係るサーマルヘッド100Bについて説明する。図中、第1の実施の形態と同一または相当部分には同一符号を付し、相違点について主に説明する。図11は、図4と同様の図であり、第2の実施の形態に係るサーマルヘッド100Bの要部を示す模式図である。 -Second Embodiment-
A
第1の実施の形態では、ワイヤボンディング部18において、銀層20が金層19上に設けられている例について説明した(図4参照)。これに対して、第2の実施の形態では、ワイヤボンディング部18Bにおいて、金層19Bが銀層20B上に設けられ、金層19の上面にワイヤボンディングがなされる。
1st Embodiment demonstrated the example in which the silver layer 20 was provided on the gold layer 19 in the wire bonding part 18 (refer FIG. 4). In contrast, in the second embodiment, in the wire bonding portion 18B, the gold layer 19B is provided on the silver layer 20B, and wire bonding is performed on the upper surface of the gold layer 19.
ワイヤボンディング部18Bにおいて、金層19Bは、銀層20Bよりも側方に突出しており、銀層20Bと金層19Bとの境界外周部に段差部23Bまたは合金層24Bが形成されている。このようなワイヤボンディング部18Bの形成方法について、図12~図14を参照して説明する。なお、図12~図14では、説明をわかりやすくするために、単純な形状で説明する。図12~図14では、グレーズ層を省略している。
In the wire bonding portion 18B, the gold layer 19B protrudes to the side of the silver layer 20B, and a stepped portion 23B or an alloy layer 24B is formed on the outer periphery of the boundary between the silver layer 20B and the gold layer 19B. A method of forming such a wire bonding portion 18B will be described with reference to FIGS. In FIGS. 12 to 14, a simple shape is used for easy understanding. In FIGS. 12 to 14, the glaze layer is omitted.
(金層および銀層形成工程)
図12(a)はエッチング処理前の配線基板の平面模式図であり、図12(b)はエッチング処理前の配線基板の側面断面模式図であり、図12(a)のxiib-xiib線切断断面を示している。図12に示すように、矩形平板状の絶縁基板1の上に、銀のペースト状組成物を、絶縁基板1よりも一回り小さいサイズの矩形状のパターンで印刷を行う。その後、金のペースト状組成物を、銀のペースト状組成物のパターンの中央部上面において、絶縁基板1の短手方向に平行に延在する矩形状のパターンで印刷を行う。その後、絶縁基板1の焼成(たとえば800℃程度)を行うことで金層2および銀層3を形成する。焼成により、金層2と銀層3の境界部分には、金と銀の合金層4が形成される(図12において不図示、図14参照)。 (Gold layer and silver layer forming process)
12A is a schematic plan view of the wiring board before the etching process, FIG. 12B is a schematic side sectional view of the wiring board before the etching process, and is cut along the line xiib-xiib in FIG. 12A. A cross section is shown. As shown in FIG. 12, a silver paste composition is printed on a rectangular flat plate-like insulatingsubstrate 1 in a rectangular pattern having a size slightly smaller than that of the insulating substrate 1. Thereafter, the gold paste composition is printed in a rectangular pattern extending in parallel with the short direction of the insulating substrate 1 on the upper surface of the central portion of the silver paste composition pattern. Then, the gold layer 2 and the silver layer 3 are formed by baking the insulating substrate 1 (for example, about 800 ° C.). By firing, a gold-silver alloy layer 4 is formed at the boundary between the gold layer 2 and the silver layer 3 (not shown in FIG. 12, see FIG. 14).
図12(a)はエッチング処理前の配線基板の平面模式図であり、図12(b)はエッチング処理前の配線基板の側面断面模式図であり、図12(a)のxiib-xiib線切断断面を示している。図12に示すように、矩形平板状の絶縁基板1の上に、銀のペースト状組成物を、絶縁基板1よりも一回り小さいサイズの矩形状のパターンで印刷を行う。その後、金のペースト状組成物を、銀のペースト状組成物のパターンの中央部上面において、絶縁基板1の短手方向に平行に延在する矩形状のパターンで印刷を行う。その後、絶縁基板1の焼成(たとえば800℃程度)を行うことで金層2および銀層3を形成する。焼成により、金層2と銀層3の境界部分には、金と銀の合金層4が形成される(図12において不図示、図14参照)。 (Gold layer and silver layer forming process)
12A is a schematic plan view of the wiring board before the etching process, FIG. 12B is a schematic side sectional view of the wiring board before the etching process, and is cut along the line xiib-xiib in FIG. 12A. A cross section is shown. As shown in FIG. 12, a silver paste composition is printed on a rectangular flat plate-like insulating
(フォトリソグラフィ・エッチング工程)
図12において一点鎖線で示すような略H字状のパターンをフォトリソグラフィにより形成する。その後、ウエットエッチング処理を一回施すことにより、すなわち配線基板をエッチング液に浸漬させることにより、図12(a)に示す一点鎖線で囲まれる部分(略H字状パターン)3a以外の部分を溶解除去する。 (Photolithography / etching process)
In FIG. 12, a substantially H-shaped pattern as shown by a one-dot chain line is formed by photolithography. Thereafter, wet etching treatment is performed once, that is, by immersing the wiring board in the etching solution, portions other than the portion (substantially H-shaped pattern) 3a surrounded by the one-dot chain line shown in FIG. Remove.
図12において一点鎖線で示すような略H字状のパターンをフォトリソグラフィにより形成する。その後、ウエットエッチング処理を一回施すことにより、すなわち配線基板をエッチング液に浸漬させることにより、図12(a)に示す一点鎖線で囲まれる部分(略H字状パターン)3a以外の部分を溶解除去する。 (Photolithography / etching process)
In FIG. 12, a substantially H-shaped pattern as shown by a one-dot chain line is formed by photolithography. Thereafter, wet etching treatment is performed once, that is, by immersing the wiring board in the etching solution, portions other than the portion (substantially H-shaped pattern) 3a surrounded by the one-dot chain line shown in FIG. Remove.
図13(a)はエッチング処理後の配線基板の平面模式図であり、図13(b)はエッチング処理後の配線基板の側面断面模式図であり、図13(a)のxiiib-xiiib線切断断面を示している。図14(a)は図13(a)のXIV部を示す部分拡大図であり、図14(b)は図14(a)のxivb-xivb線断面模式図である。図13および図14に示すように、エッチング処理では、外表面からエッチングが進行するので、金層2のうち、上部が最も溶解され、下方に向かって溶解量が小さくなっている。このため、図14に示すように、一対の略H字状パターン間の溝27における対向する側面間寸法は、上部から下部に向かって短くなっている。銀層3においても上部が最も溶解され、下方に向かって溶解量が小さくなっている。このため、一対の略H字状パターン間の溝26における対向する側面間寸法は、上部から下部に向かって短くなっている。
13A is a schematic plan view of the wiring board after the etching process, FIG. 13B is a schematic side sectional view of the wiring board after the etching process, and is cut along the xiiib-xiiib line in FIG. 13A. A cross section is shown. 14A is a partially enlarged view showing the XIV part of FIG. 13A, and FIG. 14B is a schematic cross-sectional view taken along the line xivb-xivb of FIG. 14A. As shown in FIG. 13 and FIG. 14, in the etching process, etching proceeds from the outer surface, so that the upper part of the gold layer 2 is dissolved most and the amount of dissolution decreases downward. For this reason, as shown in FIG. 14, the dimension between the side surfaces which oppose in the groove | channel 27 between a pair of substantially H-shaped pattern is short toward the lower part from the upper part. Also in the silver layer 3, the upper part is dissolved most, and the amount of dissolution becomes smaller downward. For this reason, the dimension between the side surfaces which oppose in the groove | channel 26 between a pair of substantially H-shaped patterns is short toward the lower part from the upper part.
なお、上述したように、金層2と銀層3とでは、銀層3の溶解速度の方が金層2の溶解速度よりも速い。このため、溝26の間隔は、溝27の間隔よりも大きい。
As described above, in the gold layer 2 and the silver layer 3, the dissolution rate of the silver layer 3 is faster than the dissolution rate of the gold layer 2. For this reason, the interval between the grooves 26 is larger than the interval between the grooves 27.
溝26の側面は、銀層3の上部から下方に向かうほど側方(外方)に広がる傾斜面とされている。同様に、溝27の側面は、金層2の上部から下方に向かうほど側方(外方)に広がる傾斜面とされている。金層2は、銀層3に比べて溶解速度が遅いので、銀層3と金層2との境界外周部において段差部23が形成されている。金層2は、銀層3に比べて側方に突出するように形成される。また、焼成により形成された合金層4が、エッチング処理により露出される。つまり、エッチング処理により、金層2と銀層3の境界外周部に、金と銀の合金層4が形成される。積層構造部における外周側に、金層2が配置されること、および、金と銀の合金層4が形成されることにより、マイグレーションの抑制効果が向上し、かつ、硫化を抑制する効果も向上する。
The side surface of the groove 26 is an inclined surface that spreads laterally (outward) from the top of the silver layer 3 downward. Similarly, the side surface of the groove 27 is an inclined surface that spreads sideward (outward) from the top of the gold layer 2 toward the lower side. Since the dissolution rate of the gold layer 2 is slower than that of the silver layer 3, a step portion 23 is formed at the outer periphery of the boundary between the silver layer 3 and the gold layer 2. The gold layer 2 is formed so as to protrude sideways compared to the silver layer 3. Further, the alloy layer 4 formed by firing is exposed by the etching process. That is, the gold and silver alloy layer 4 is formed on the outer periphery of the boundary between the gold layer 2 and the silver layer 3 by the etching process. By arranging the gold layer 2 on the outer peripheral side of the laminated structure and forming the alloy layer 4 of gold and silver, the effect of suppressing migration is improved and the effect of suppressing sulfidation is also improved. To do.
このような、第2の実施の形態によれば、第1の実施の形態と同様の作用効果を奏する。
According to the second embodiment as described above, the same operational effects as those of the first embodiment can be obtained.
-第3の実施の形態-
図15を参照して、第3の実施の形態に係るサーマルヘッド100Cついて説明する。図中、第1の実施の形態と同一または相当部分には同一符号を付し、相違点について主に説明する。図15は、図4と同様の図であり、第3の実施の形態に係るサーマルヘッド100Cの要部を示す模式図である。 -Third embodiment-
With reference to FIG. 15, a thermal head 100C according to a third embodiment will be described. In the figure, the same or corresponding parts as those in the first embodiment are denoted by the same reference numerals, and differences will be mainly described. FIG. 15 is a diagram similar to FIG. 4, and is a schematic diagram showing a main part of athermal head 100 </ b> C according to the third embodiment.
図15を参照して、第3の実施の形態に係るサーマルヘッド100Cついて説明する。図中、第1の実施の形態と同一または相当部分には同一符号を付し、相違点について主に説明する。図15は、図4と同様の図であり、第3の実施の形態に係るサーマルヘッド100Cの要部を示す模式図である。 -Third embodiment-
With reference to FIG. 15, a thermal head 100C according to a third embodiment will be described. In the figure, the same or corresponding parts as those in the first embodiment are denoted by the same reference numerals, and differences will be mainly described. FIG. 15 is a diagram similar to FIG. 4, and is a schematic diagram showing a main part of a
第3の実施の形態に係る配線基板は、絶縁基板12と、絶縁基板12上に設けられた銀層20Cと、絶縁基板12上において、銀層20Cと同一平面上に設けられ、銀層20Cよりもイオン化傾向が小さい金層19Cとを備えている。金層19Cは、銀層20Cの縁部上に重なる重なり部19aと、銀層20Cとは重ならない非重なり部19bとを有し、非重なり部19bがワイヤボンディング部(電極端子)18Cとして構成されている。本実施の形態では、銀層20Cおよび金層19の非重なり部19bは、それぞれグレーズ層13を介して絶縁基板12上に配置されている。
The wiring board according to the third embodiment is provided with the insulating substrate 12, the silver layer 20C provided on the insulating substrate 12, and the insulating substrate 12 provided on the same plane as the silver layer 20C. And a gold layer 19C having a smaller ionization tendency. The gold layer 19C has an overlapping portion 19a that overlaps the edge of the silver layer 20C and a non-overlapping portion 19b that does not overlap the silver layer 20C, and the non-overlapping portion 19b is configured as a wire bonding portion (electrode terminal) 18C. Has been. In the present embodiment, the non-overlapping portions 19b of the silver layer 20C and the gold layer 19 are disposed on the insulating substrate 12 via the glaze layer 13, respectively.
第3の実施の形態では、金層19Cの重なり部19aと銀層20Cとを積層構造とすることで、焼成により金と銀の合金層24Cを形成することができる。また、ワイヤボンディング部18Cは、金層19Cのみからなるので、マイグレーション耐性および硫化耐性も高い。
In the third embodiment, the overlapping portion 19a of the gold layer 19C and the silver layer 20C have a laminated structure, whereby the gold-silver alloy layer 24C can be formed by firing. Moreover, since the wire bonding part 18C consists only of the gold layer 19C, it has high migration resistance and sulfidation resistance.
このような第3の実施の形態によれば、第1の実施の形態と同様に、マイグレーション耐性および硫化耐性の高い配線基板を提供できる。
According to the third embodiment, it is possible to provide a wiring board having high migration resistance and high sulfidation resistance, as in the first embodiment.
次のような変形も本発明の範囲内であり、変形例の一つ、もしくは複数を上述の実施形態と組み合わせることも可能である。
(変形例1)
上述した実施形態では、イオン化傾向が大きい第1導電層を銀層20,20B,20Cとし、イオン化傾向が小さい第2導電層を金層19,19B,19Cとした例について説明したが、本発明はこれに限定されない。第1導電層を、銅からなる銅層や、アルミニウムからなるアルミニウム層とし、第2導電層に、白金からなる白金層や、パラジウムからなるパラジウム層を採用してもよい。少なくとも第2導電層が、第1導電層よりもイオン化傾向が小さく、第2導電層を第1導電層よりも側方に突出させて段差部23または合金層24,24B,24Cを形成した種々の配線基板に本発明を適用できる。 The following modifications are also within the scope of the present invention, and one or a plurality of modifications can be combined with the above-described embodiment.
(Modification 1)
In the above-described embodiment, an example in which the first conductive layer having a large ionization tendency is the silver layers 20, 20B, and 20C and the second conductive layer having a small ionization tendency is the gold layers 19, 19B, and 19C has been described. Is not limited to this. The first conductive layer may be a copper layer made of copper or an aluminum layer made of aluminum, and a platinum layer made of platinum or a palladium layer made of palladium may be adopted as the second conductive layer. At least the second conductive layer has a smaller ionization tendency than the first conductive layer, and the steppedportion 23 or the alloy layers 24, 24B, and 24C are formed by projecting the second conductive layer to the side of the first conductive layer. The present invention can be applied to this wiring board.
(変形例1)
上述した実施形態では、イオン化傾向が大きい第1導電層を銀層20,20B,20Cとし、イオン化傾向が小さい第2導電層を金層19,19B,19Cとした例について説明したが、本発明はこれに限定されない。第1導電層を、銅からなる銅層や、アルミニウムからなるアルミニウム層とし、第2導電層に、白金からなる白金層や、パラジウムからなるパラジウム層を採用してもよい。少なくとも第2導電層が、第1導電層よりもイオン化傾向が小さく、第2導電層を第1導電層よりも側方に突出させて段差部23または合金層24,24B,24Cを形成した種々の配線基板に本発明を適用できる。 The following modifications are also within the scope of the present invention, and one or a plurality of modifications can be combined with the above-described embodiment.
(Modification 1)
In the above-described embodiment, an example in which the first conductive layer having a large ionization tendency is the silver layers 20, 20B, and 20C and the second conductive layer having a small ionization tendency is the gold layers 19, 19B, and 19C has been described. Is not limited to this. The first conductive layer may be a copper layer made of copper or an aluminum layer made of aluminum, and a platinum layer made of platinum or a palladium layer made of palladium may be adopted as the second conductive layer. At least the second conductive layer has a smaller ionization tendency than the first conductive layer, and the stepped
(変形例2)
第1および第2の実施の形態では、金層19,19Bおよび銀層20,20Bをそれぞれ印刷し、焼成することにより形成する例について説明したが、本発明はこれに限定されない。蒸着やスパッタリングにより金層19,19Bおよび銀層20,20Bのそれぞれを形成し、その後、金層19,19Bと銀層20,20Bの積層構造部に対して、一度のエッチング処理により段差部23を形成してもよい。なお、蒸着やスパッタリングにより金層19,19Bおよび銀層20,20Bを形成する場合、上述した合金層24,24Bは形成されない。つまり、段差部23のみを形成し、合金層24,24Bを形成しない場合も本発明の範囲内である。また、合金層24,24Bのみを形成し、段差部23を形成しない場合も本発明の範囲内である。合金層24,24Bのみを形成する場合もマイグレーション耐性および硫化耐性を向上することができる。なお、段差部23だけでなく合金層24を形成することで、マイグレーション耐性および硫化耐性を大きく向上できるので、段差部23および合金層24の双方を形成することが好ましい。 (Modification 2)
In the first and second embodiments, examples have been described in which the gold layers 19 and 19B and the silver layers 20 and 20B are formed by printing and firing, respectively, but the present invention is not limited to this. Each of the gold layers 19 and 19B and the silver layers 20 and 20B is formed by vapor deposition or sputtering, and then the steppedportion 23 is formed by a single etching process on the stacked structure portion of the gold layers 19 and 19B and the silver layers 20 and 20B. May be formed. Note that when the gold layers 19 and 19B and the silver layers 20 and 20B are formed by vapor deposition or sputtering, the above-described alloy layers 24 and 24B are not formed. That is, the case where only the step portion 23 is formed and the alloy layers 24 and 24B are not formed is also within the scope of the present invention. Further, the case where only the alloy layers 24 and 24B are formed and the step portion 23 is not formed is also within the scope of the present invention. Even when only the alloy layers 24 and 24B are formed, the migration resistance and the sulfidation resistance can be improved. Since not only the step portion 23 but also the alloy layer 24 is formed, the migration resistance and the sulfidation resistance can be greatly improved. Therefore, it is preferable to form both the step portion 23 and the alloy layer 24.
第1および第2の実施の形態では、金層19,19Bおよび銀層20,20Bをそれぞれ印刷し、焼成することにより形成する例について説明したが、本発明はこれに限定されない。蒸着やスパッタリングにより金層19,19Bおよび銀層20,20Bのそれぞれを形成し、その後、金層19,19Bと銀層20,20Bの積層構造部に対して、一度のエッチング処理により段差部23を形成してもよい。なお、蒸着やスパッタリングにより金層19,19Bおよび銀層20,20Bを形成する場合、上述した合金層24,24Bは形成されない。つまり、段差部23のみを形成し、合金層24,24Bを形成しない場合も本発明の範囲内である。また、合金層24,24Bのみを形成し、段差部23を形成しない場合も本発明の範囲内である。合金層24,24Bのみを形成する場合もマイグレーション耐性および硫化耐性を向上することができる。なお、段差部23だけでなく合金層24を形成することで、マイグレーション耐性および硫化耐性を大きく向上できるので、段差部23および合金層24の双方を形成することが好ましい。 (Modification 2)
In the first and second embodiments, examples have been described in which the gold layers 19 and 19B and the silver layers 20 and 20B are formed by printing and firing, respectively, but the present invention is not limited to this. Each of the gold layers 19 and 19B and the silver layers 20 and 20B is formed by vapor deposition or sputtering, and then the stepped
(変形例3)
上述した実施の形態では、個別電極17のワイヤボンディング部18に段差部23を形成する例について説明したが、本発明はこれに限定されない。絶縁性保護膜7で被覆されていない配線部分に段差部23または合金層24を形成して、マイグレーションの発生を抑制してもよい。 (Modification 3)
In the above-described embodiment, the example in which thestep portion 23 is formed in the wire bonding portion 18 of the individual electrode 17 has been described, but the present invention is not limited to this. The step portion 23 or the alloy layer 24 may be formed in the wiring portion not covered with the insulating protective film 7 to suppress the occurrence of migration.
上述した実施の形態では、個別電極17のワイヤボンディング部18に段差部23を形成する例について説明したが、本発明はこれに限定されない。絶縁性保護膜7で被覆されていない配線部分に段差部23または合金層24を形成して、マイグレーションの発生を抑制してもよい。 (Modification 3)
In the above-described embodiment, the example in which the
(変形例4)
上述した実施の形態では、グレーズ層13を備えたサーマルヘッド100を例に説明したが、グレーズ層13を備えていないサーマルヘッドに本発明を適用してもよい。 (Modification 4)
In the embodiment described above, thethermal head 100 including the glaze layer 13 has been described as an example. However, the present invention may be applied to a thermal head that does not include the glaze layer 13.
上述した実施の形態では、グレーズ層13を備えたサーマルヘッド100を例に説明したが、グレーズ層13を備えていないサーマルヘッドに本発明を適用してもよい。 (Modification 4)
In the embodiment described above, the
(変形例5)
上述した実施の形態では、サーマルヘッドの配線基板に本発明を適用する例について説明したが、本発明はこれに限定されない。種々の電子機器の基板に本発明を適用することができる。たとえば、原料ガスと水蒸気から触媒改質により水素を製造する水蒸気改質器における触媒の基板に本発明を適用することもできる。 (Modification 5)
In the above-described embodiment, the example in which the present invention is applied to the wiring board of the thermal head has been described, but the present invention is not limited to this. The present invention can be applied to substrates of various electronic devices. For example, the present invention can be applied to a catalyst substrate in a steam reformer that produces hydrogen from a source gas and steam by catalytic reforming.
上述した実施の形態では、サーマルヘッドの配線基板に本発明を適用する例について説明したが、本発明はこれに限定されない。種々の電子機器の基板に本発明を適用することができる。たとえば、原料ガスと水蒸気から触媒改質により水素を製造する水蒸気改質器における触媒の基板に本発明を適用することもできる。 (Modification 5)
In the above-described embodiment, the example in which the present invention is applied to the wiring board of the thermal head has been described, but the present invention is not limited to this. The present invention can be applied to substrates of various electronic devices. For example, the present invention can be applied to a catalyst substrate in a steam reformer that produces hydrogen from a source gas and steam by catalytic reforming.
上記では、種々の実施の形態および変形例を説明したが、本発明はこれらの内容に限定されるものではない。本発明の技術的思想の範囲内で考えられるその他の態様も本発明の範囲内に含まれる。
Although various embodiments and modifications have been described above, the present invention is not limited to these contents. Other embodiments conceivable within the scope of the technical idea of the present invention are also included in the scope of the present invention.
次の優先権基礎出願の開示内容は引用文としてここに組み込まれる。
日本国特許出願2015年第131532号(2015年6月30日出願) The disclosure of the following priority application is hereby incorporated by reference.
Japanese Patent Application No. 131532 in 2015 (filed on June 30, 2015)
日本国特許出願2015年第131532号(2015年6月30日出願) The disclosure of the following priority application is hereby incorporated by reference.
Japanese Patent Application No. 131532 in 2015 (filed on June 30, 2015)
1 絶縁基板、2 金層、3 銀層、4 合金層、5 共通電極、5a 電極面、5b 帯状電極、6 発熱抵抗体、7 絶縁性保護膜、8 個別電極、9 ワイヤボンディング部、10 金ワイヤ、11 ドライバIC、12 絶縁基板、13 グレーズ層、14 低純度金層、15 高純度金層、16 封止樹脂、17 個別電極、18 ワイヤボンディング部、19 金層、20 銀層、23 段差部、24、合金層、26 溝、27 溝、30 プリント配線板、31 コネクタ、32 支持板、50 配線基板、100 サーマルヘッド
1 insulating substrate, 2 gold layer, 3 silver layer, 4 alloy layer, 5 common electrode, 5a electrode surface, 5b strip electrode, 6 heating resistor, 7 insulating protective film, 8 individual electrode, 9 wire bonding part, 10 gold Wire, 11 Driver IC, 12 Insulating substrate, 13 Glaze layer, 14 Low purity gold layer, 15 High purity gold layer, 16 Sealing resin, 17 Individual electrode, 18 Wire bonding part, 19 Gold layer, 20 Silver layer, 23 Step Part, 24, alloy layer, 26 groove, 27 groove, 30 printed wiring board, 31 connector, 32 support plate, 50 wiring board, 100 thermal head
Claims (13)
- 絶縁性の基板と、
前記基板上において積層された第1導電層および第2導電層と、を備え、
前記第2導電層は、前記第1導電層よりもイオン化傾向が小さく、
前記第1導電層および前記第2導電層に対する一度のエッチング処理により、前記第2導電層が前記第1導電層よりも側方に突出した段差部または合金部を、前記第1導電層と前記第2導電層との境界外周部に設けた、配線基板。 An insulating substrate;
A first conductive layer and a second conductive layer laminated on the substrate,
The second conductive layer has a smaller ionization tendency than the first conductive layer,
The step portion or the alloy portion in which the second conductive layer protrudes to the side of the first conductive layer by one etching process on the first conductive layer and the second conductive layer is formed between the first conductive layer and the first conductive layer. A wiring board provided on the outer periphery of the boundary with the second conductive layer. - 請求項1に記載の配線基板において、
前記第1導電層は前記第2導電層上に設けられている、配線基板。 The wiring board according to claim 1,
The wiring board, wherein the first conductive layer is provided on the second conductive layer. - 請求項1に記載の配線基板において、
前記第2導電層は前記第1導電層上に設けられている、配線基板。 The wiring board according to claim 1,
The wiring board, wherein the second conductive layer is provided on the first conductive layer. - 請求項1から3までのいずれか一項に記載の配線基板において、
前記段差部または前記合金部は露出されている、配線基板。 In the wiring board as described in any one of Claim 1 to 3,
The wiring board, wherein the stepped portion or the alloy portion is exposed. - 絶縁性の基板と、
前記基板上において積層された第1導電層および第2導電層と、を備え、
前記第2導電層は、前記第1導電層よりもイオン化傾向が小さく、
前記第1導電層と前記第2導電層の境界外周部には、前記第2導電層が前記第1導電層よりも側方に突出した段差部または合金部が形成され、
前記第1導電層と前記第2導電層との位置精度または前記第1導電層および前記第2導電層からなる積層構造体の幅または間隔が、10μm以下とされている、配線基板。 An insulating substrate;
A first conductive layer and a second conductive layer laminated on the substrate,
The second conductive layer has a smaller ionization tendency than the first conductive layer,
A stepped portion or an alloy portion in which the second conductive layer protrudes laterally from the first conductive layer is formed at the outer periphery of the boundary between the first conductive layer and the second conductive layer.
The wiring board, wherein the positional accuracy between the first conductive layer and the second conductive layer or the width or interval of the laminated structure composed of the first conductive layer and the second conductive layer is 10 μm or less. - 請求項5に記載の配線基板において、
前記第1導電層は前記第2導電層上に設けられている、配線基板。 The wiring board according to claim 5,
The wiring board, wherein the first conductive layer is provided on the second conductive layer. - 請求項5に記載の配線基板において、
前記第2導電層は前記第1導電層上に設けられている、配線基板。 The wiring board according to claim 5,
The wiring board, wherein the second conductive layer is provided on the first conductive layer. - 請求項5から7までのいずれか一項に記載の配線基板において、
前記段差部または合金部は露出されている、配線基板。 In the wiring board according to any one of claims 5 to 7,
The wiring board, wherein the stepped portion or the alloy portion is exposed. - 絶縁性の基板と、
前記基板上に設けられた第1導電層と、
前記基板上において、前記第1導電層と同一平面上に設けられ、前記第1導電層よりもイオン化傾向が小さい第2導電層と、を備え、
前記第2導電層は、前記第1導電層の縁部上に重なる重なり部と、前記第1導電層とは重ならない非重なり部とを有し、前記非重なり部が電極端子として構成されている、配線基板。 An insulating substrate;
A first conductive layer provided on the substrate;
A second conductive layer provided on the same plane as the first conductive layer and having a smaller ionization tendency than the first conductive layer on the substrate;
The second conductive layer has an overlapping portion that overlaps with an edge of the first conductive layer and a non-overlapping portion that does not overlap with the first conductive layer, and the non-overlapping portion is configured as an electrode terminal. Wiring board. - 請求項1から4までのいずれか一項に記載の配線基板と、
前記基板上に設けられたグレーズ層と、
前記グレーズ層上に設けられた発熱抵抗体と、
前記グレーズ層上に設けられた共通電極および複数の個別電極と、
前記個別電極の一部を覆う絶縁性の保護膜と、
前記個別電極に電流を流すドライバICと、
前記保護膜で覆われていない前記個別電極の電極端子と、前記ドライバICとを接続するワイヤとを備え、
前記段差部または合金部は、前記複数の個別電極のそれぞれの電極端子に形成されている、サーマルヘッド。 A wiring board according to any one of claims 1 to 4,
A glaze layer provided on the substrate;
A heating resistor provided on the glaze layer;
A common electrode and a plurality of individual electrodes provided on the glaze layer;
An insulating protective film covering a part of the individual electrode;
A driver IC for supplying current to the individual electrodes;
An electrode terminal of the individual electrode not covered with the protective film, and a wire connecting the driver IC,
The stepped portion or the alloy portion is a thermal head formed at each electrode terminal of the plurality of individual electrodes. - 請求項5から8までのいずれか一項に記載の配線基板と、
前記基板上に設けられたグレーズ層と、
前記グレーズ層上に設けられた発熱抵抗体と、
前記グレーズ層上に設けられた共通電極および複数の個別電極と、
前記個別電極の一部を覆う絶縁性の保護膜と、
前記個別電極に電流を流すドライバICと、
前記保護膜で覆われていない前記個別電極の電極端子と、前記ドライバICとを接続するワイヤとを備え、
前記段差部または合金部は、前記複数の個別電極のそれぞれの電極端子に形成されている、サーマルヘッド。 A wiring board according to any one of claims 5 to 8,
A glaze layer provided on the substrate;
A heating resistor provided on the glaze layer;
A common electrode and a plurality of individual electrodes provided on the glaze layer;
An insulating protective film covering a part of the individual electrode;
A driver IC for supplying current to the individual electrodes;
An electrode terminal of the individual electrode not covered with the protective film, and a wire connecting the driver IC,
The stepped portion or the alloy portion is a thermal head formed at each electrode terminal of the plurality of individual electrodes. - 請求項9に記載の配線基板と、
前記基板上に設けられたグレーズ層と、
前記グレーズ層上に設けられた発熱抵抗体と、
前記グレーズ層上に設けられた共通電極および複数の個別電極と、
前記個別電極の一部を覆う絶縁性の保護膜と、
前記個別電極に電流を流すドライバICと、
前記保護膜で覆われていない前記個別電極の電極端子と、前記ドライバICとを接続するワイヤとを備え、
前記重なり部または非重なり部は、前記複数の個別電極のそれぞれに形成されている、サーマルヘッド。 The wiring board according to claim 9,
A glaze layer provided on the substrate;
A heating resistor provided on the glaze layer;
A common electrode and a plurality of individual electrodes provided on the glaze layer;
An insulating protective film covering a part of the individual electrode;
A driver IC for supplying current to the individual electrodes;
An electrode terminal of the individual electrode not covered with the protective film, and a wire connecting the driver IC,
The overlapping portion or the non-overlapping portion is a thermal head formed on each of the plurality of individual electrodes. - 絶縁性の基板上に、第1導電層と前記第1導電層よりもイオン化傾向が小さい第2導電層とを積層して配置し、
前記第1導電層および前記第2導電層に対して、一度のエッチング処理により、前記第2導電層が前記第1導電層よりも側方に突出した段差部または合金部を、前記第1導電層と前記第2導電層との境界外周部に形成する、配線基板の製造方法。 On the insulating substrate, the first conductive layer and the second conductive layer having a smaller ionization tendency than the first conductive layer are stacked and arranged,
The first conductive layer and the second conductive layer are subjected to a single etching process so that the stepped portion or alloy portion in which the second conductive layer protrudes to the side of the first conductive layer is formed as the first conductive layer. A method of manufacturing a wiring board, which is formed on the outer periphery of the boundary between a layer and the second conductive layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201680038327.5A CN107710886B (en) | 2015-06-30 | 2016-06-08 | Wiring board, thermal head, and method for manufacturing wiring board |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015131532A JP2017017156A (en) | 2015-06-30 | 2015-06-30 | Wiring board, thermal head, and method for producing wiring board |
JP2015-131532 | 2015-06-30 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2017002565A1 true WO2017002565A1 (en) | 2017-01-05 |
Family
ID=57608446
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2016/067116 WO2017002565A1 (en) | 2015-06-30 | 2016-06-08 | Wiring board, thermal head, and method for producing wiring board |
Country Status (3)
Country | Link |
---|---|
JP (1) | JP2017017156A (en) |
CN (1) | CN107710886B (en) |
WO (1) | WO2017002565A1 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6767296B2 (en) * | 2017-03-29 | 2020-10-14 | 京セラ株式会社 | Thermal head and thermal printer |
JP7031205B2 (en) | 2017-09-29 | 2022-03-08 | 株式会社ニデック | OCT device |
JP7181839B2 (en) * | 2019-06-05 | 2022-12-01 | 日本特殊陶業株式会社 | Wiring board and method for manufacturing wiring board |
JP2022133080A (en) * | 2021-03-01 | 2022-09-13 | アオイ電子株式会社 | Manufacturing method for thermal head and thermal head |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57170543A (en) * | 1981-04-14 | 1982-10-20 | Murata Mfg Co Ltd | Thick film printed circuit board |
JPH02277649A (en) * | 1989-04-20 | 1990-11-14 | Seiko Epson Corp | Manufacture of thermal head |
JPH10209611A (en) * | 1997-01-24 | 1998-08-07 | Matsushita Electric Ind Co Ltd | Manufacture of high-density wiring board |
JP2005243793A (en) * | 2004-02-25 | 2005-09-08 | Tohoku Pioneer Corp | Wiring board, wiring board forming method, and organic el panel |
JP2005317566A (en) * | 2004-04-26 | 2005-11-10 | Kyocera Corp | Wiring board and manufacturing method thereof |
JP2008166479A (en) * | 2006-12-28 | 2008-07-17 | Kobe Steel Ltd | Wiring board and method for forming wiring |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2012086558A1 (en) * | 2010-12-25 | 2012-06-28 | 京セラ株式会社 | Thermal head and thermal printer comprising same |
JP5952089B2 (en) * | 2012-01-25 | 2016-07-13 | ローム株式会社 | Manufacturing method of fine wiring pattern and thermal print head |
JP6202721B2 (en) * | 2013-04-08 | 2017-09-27 | アオイ電子株式会社 | Circuit board and thermal print head using the same |
-
2015
- 2015-06-30 JP JP2015131532A patent/JP2017017156A/en active Pending
-
2016
- 2016-06-08 WO PCT/JP2016/067116 patent/WO2017002565A1/en active Application Filing
- 2016-06-08 CN CN201680038327.5A patent/CN107710886B/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57170543A (en) * | 1981-04-14 | 1982-10-20 | Murata Mfg Co Ltd | Thick film printed circuit board |
JPH02277649A (en) * | 1989-04-20 | 1990-11-14 | Seiko Epson Corp | Manufacture of thermal head |
JPH10209611A (en) * | 1997-01-24 | 1998-08-07 | Matsushita Electric Ind Co Ltd | Manufacture of high-density wiring board |
JP2005243793A (en) * | 2004-02-25 | 2005-09-08 | Tohoku Pioneer Corp | Wiring board, wiring board forming method, and organic el panel |
JP2005317566A (en) * | 2004-04-26 | 2005-11-10 | Kyocera Corp | Wiring board and manufacturing method thereof |
JP2008166479A (en) * | 2006-12-28 | 2008-07-17 | Kobe Steel Ltd | Wiring board and method for forming wiring |
Also Published As
Publication number | Publication date |
---|---|
CN107710886B (en) | 2020-06-12 |
CN107710886A (en) | 2018-02-16 |
JP2017017156A (en) | 2017-01-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9358804B2 (en) | Fine wiring pattern, manufacturing method thereof, and thermal print head | |
WO2017002565A1 (en) | Wiring board, thermal head, and method for producing wiring board | |
WO2017002566A1 (en) | Wiring board and thermal head | |
CN107914472B (en) | Thermal print head and method of manufacturing thermal print head | |
JP7107478B2 (en) | Resistive elements and resistive element assemblies | |
JP5706186B2 (en) | Chip resistor and manufacturing method thereof | |
JP6763008B2 (en) | Wiring board manufacturing method and thermal head manufacturing method | |
JP2007194399A (en) | Chip resistor and its manufacturing method | |
JP2024015453A (en) | Resistor | |
JP2006310277A (en) | Chip type fuse | |
US9668348B2 (en) | Multi-terminal electronic component, method of manufacturing the same, and board having the same | |
JP2008182128A (en) | Chip resistor | |
JP6754335B2 (en) | Thermal head | |
JP5489836B2 (en) | Thermal head | |
JP7016642B2 (en) | Manufacturing method of thermal print head and thermal print head | |
WO2020170750A1 (en) | Resistor | |
US20140022047A1 (en) | Electric power fuse | |
US20160332456A1 (en) | Thermal print head | |
JP2007095926A (en) | Chip resistor | |
JP4295202B2 (en) | Chip component and chip component manufacturing method | |
KR20180054273A (en) | Chip resistor and chip resistor assembly | |
JP2022100748A (en) | Thermal print head and manufacturing method of the same | |
JP2000188204A (en) | Resistor and its manufacture | |
CN114475011A (en) | Thermal print head and method of manufacturing the same | |
JP6075606B2 (en) | Wiring board and electronic device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 16817674 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 16817674 Country of ref document: EP Kind code of ref document: A1 |