WO2016203644A1 - Power amplifier - Google Patents

Power amplifier Download PDF

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Publication number
WO2016203644A1
WO2016203644A1 PCT/JP2015/067743 JP2015067743W WO2016203644A1 WO 2016203644 A1 WO2016203644 A1 WO 2016203644A1 JP 2015067743 W JP2015067743 W JP 2015067743W WO 2016203644 A1 WO2016203644 A1 WO 2016203644A1
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WO
WIPO (PCT)
Prior art keywords
terminal
transistor
circuit board
power amplifier
harmonic
Prior art date
Application number
PCT/JP2015/067743
Other languages
French (fr)
Japanese (ja)
Inventor
和宏 弥政
拓真 鳥居
政毅 半谷
山中　宏治
Original Assignee
三菱電機株式会社
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Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to PCT/JP2015/067743 priority Critical patent/WO2016203644A1/en
Publication of WO2016203644A1 publication Critical patent/WO2016203644A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages

Definitions

  • the present invention relates to a power amplifier that operates with high efficiency.
  • a communication device, a radar device, or the like is equipped with a power amplifier that amplifies the power of a transmission signal to a desired level.
  • a power amplifier that amplifies the power of a transmission signal to a desired level.
  • a semiconductor device such as a high electron mobility transistor (HEMT) that is a high electron mobility transistor or a field effect transistor (FET) that is a field effect transistor is used.
  • HEMT high electron mobility transistor
  • FET field effect transistor
  • the self-heating of the semiconductor element increases.
  • high efficiency is required for the power amplifier, and if the impedance of the second harmonic at the gate terminal of the semiconductor element is set to a load condition close to a short circuit. It is also known that the power amplifier operates with high efficiency by setting the second harmonic impedance at the drain terminal of the semiconductor element to a load condition that is short-circuited or opened. To set the second harmonic of the operating frequency to a load condition close to a short circuit at the gate terminal or the drain terminal, a harmonic processing circuit having a very low impedance is added to the second harmonic of the operating frequency. There is a need.
  • Patent Document 1 discloses a power amplifier in which a resonance circuit and a band-pass filter are arranged on the external substrate side of a semiconductor substrate as a harmonic processing circuit having a low impedance with respect to the second harmonic of the operating frequency. It is disclosed.
  • This harmonic processing circuit is connected to a transistor on the semiconductor substrate by wire bonding or the like.
  • the harmonic processing circuit is connected to the transistor on the semiconductor substrate by wire bonding or the like, the length of the bonding wire connecting the semiconductor substrate and the external substrate varies due to the variation due to the mounting accuracy of the external substrate.
  • the inductance component forming the harmonic processing circuit changes, so that the impedance with respect to the harmonic also varies.
  • the load with respect to the harmonics cannot be set to a desired impedance, resulting in variations in the characteristics of the power amplifier, such as deterioration in output and efficiency of the power amplifier. For this reason, it may cause a decrease in yield and increase the cost.
  • Patent Document 2 a harmonic processing circuit including a spiral inductor and a MIM (Metal Insulation Metal) capacitor is formed on a semiconductor chip in order to avoid variations in impedance due to variations in bonding wire length.
  • a power amplifier is disclosed.
  • the conventional power amplifier is configured as described above, if a harmonic processing circuit including a spiral inductor and an MIM capacitor is formed on a semiconductor chip, impedance variation due to bonding wire length variation can be avoided. Can do. However, by forming such a harmonic processing circuit on a semiconductor chip, there is a problem that the area of the semiconductor chip is increased and the cost is increased.
  • the present invention has been made in order to solve the above-described problems, and can avoid variations in impedance with respect to harmonics without forming a harmonic processing circuit including a spiral inductor and an MIM capacitor on a semiconductor substrate.
  • An object is to obtain a small and low-cost power amplifier.
  • the power amplifier according to the present invention has a first terminal to which a signal to be amplified is input, a second terminal connected to the constant potential terminal, and a third terminal for outputting the amplified signal.
  • An input matching circuit that matches the impedance on the input side of the terminal and the input impedance of the transistor, and is connected to the third terminal of the transistor, and matches the impedance on the output side of the third terminal and the output impedance of the transistor.
  • An output matching circuit connected between the first terminal and the constant potential end of the transistor, and a second harmonic or a third or higher harmonic of the operating frequency of the transistor In which the first resonant circuit resonating is so formed in the multilayer circuit board.
  • the first resonance circuit connected between the first terminal and the constant potential end of the transistor and resonating at the second harmonic or the third harmonic or higher of the operating frequency of the transistor is a multilayer. Since it is configured to be formed on a circuit board, it is possible to avoid variations in impedance with respect to harmonics without forming a harmonic processing circuit consisting of a spiral inductor and MIM capacitor on a semiconductor substrate. There is an effect that a simple power amplifier can be obtained.
  • FIG. 1 is a circuit diagram showing a power amplifier according to a first embodiment of the present invention. It is sectional drawing which shows the power amplifier by Embodiment 1 of this invention.
  • FIG. 3 is a plan view of a semiconductor substrate 2 and a transistor 1 as viewed from above. 3 is a plan view of a circuit board 3a forming a first layer in the multilayer circuit board 3 as viewed from above.
  • FIG. 3 is a plan view of a circuit board 3b forming a second layer in the multilayer circuit board 3 as viewed from above.
  • FIG. 3 is a plan view of a circuit board 3c forming a third layer in the multilayer circuit board 3 as viewed from above.
  • FIG. 5 is a plan view of a circuit board 3d forming a fourth layer in the multilayer circuit board 3 as viewed from above. It is the top view which looked at the circuit board 3e which forms the 5th layer in the multilayer circuit board 3 from the upper surface. It is sectional drawing which shows the power amplifier by Embodiment 2 of this invention.
  • FIG. 3 is a plan view of a semiconductor substrate 2 and a transistor 1 as viewed from above. It is the top view which looked at the circuit board 3f which has formed the 1st layer in the multilayer circuit board 3 from the upper surface.
  • FIG. 4 is a plan view of a back surface of a circuit board 3f forming a first layer in the multilayer circuit board 3.
  • FIG. FIG. 5 is a plan view of a circuit board 3g forming a second layer in the multilayer circuit board 3 as viewed from above.
  • FIG. 5 is a plan view of a circuit board 3h forming a third layer in the multilayer circuit board 3 as viewed from above. It is sectional drawing which shows the power amplifier by Embodiment 3 of this invention.
  • 4 is a plan view of a back surface of a circuit board 3i forming a first layer in the multilayer circuit board 3.
  • FIG. FIG. 3 is a plan view of a circuit board 3i forming a first layer in the multilayer circuit board 3 as viewed from above.
  • FIG. 3 is a plan view of a semiconductor substrate 2 and a transistor 1 as viewed from above. It is the top view which looked at the circuit board 3j which forms the 1st layer in the multilayer circuit board 3 from the upper surface. It is the top view which looked at the circuit board 3k which has formed the 2nd layer in the multilayer circuit board 3 from the upper surface. It is a circuit diagram which shows the power amplifier by Embodiment 5 of this invention. It is sectional drawing which shows the power amplifier by Embodiment 5 of this invention.
  • FIG. 3 is a plan view of a circuit board 3m forming a first layer in the multilayer circuit board 3 as viewed from above.
  • FIG. 4 is a plan view of a back surface of a circuit board 3m forming a first layer in the multilayer circuit board 3.
  • FIG. 3 is a plan view of a circuit board 3n forming a second layer in the multilayer circuit board 3 as viewed from above.
  • FIG. 3 is a plan view of a circuit board 3p forming a third layer in the multilayer circuit board 3 as viewed from above.
  • It is a circuit diagram which shows the power amplifier by Embodiment 6 of this invention. It is the top view which looked at the circuit board 3e which forms the 5th layer in the multilayer circuit board 3 from the upper surface.
  • It is a circuit diagram which shows the power amplifier by Embodiment 7 of this invention.
  • FIG. 3 is a plan view of a circuit board 3p forming a third layer in the multilayer circuit board 3 as viewed from above. It is sectional drawing which shows the power amplifier by Embodiment 8 of this invention.
  • FIG. 1 is a cross-sectional view showing a connection relationship between a multilayer circuit board constituting a power amplifier according to Embodiment 1 of the present invention and a transistor on a semiconductor substrate.
  • FIG. 2 is a circuit diagram showing a power amplifier according to Embodiment 1 of the present invention
  • FIG. 3 is a cross-sectional view showing the power amplifier according to Embodiment 1 of the present invention.
  • a transistor 1 includes a gate terminal 1a that is a first terminal to which a high-frequency signal that is a signal to be amplified is input, and a source terminal 1b that is a second terminal connected to a constant potential terminal.
  • a FET field effect transistor having a drain terminal 1c which is a third terminal for outputting a high-frequency signal after amplification.
  • the transistor 1 is formed on a semiconductor substrate 2.
  • the multilayer circuit board 3 is a board formed of a plurality of circuit boards 3a to 3e.
  • the multilayer circuit board 3 is disposed at a position that forms a layer with the semiconductor substrate 2, and is electrically connected to the semiconductor substrate 2.
  • a board formed of low temperature co-fired ceramics (LTCC) can be used as the multilayer circuit board 3.
  • the input terminal 4 is a terminal connected to a signal source that oscillates a high-frequency signal, and inputs a high-frequency signal oscillated from the signal source.
  • the output terminal 5 is a terminal to which a load is connected, and outputs a high-frequency signal amplified by the transistor 1.
  • the input matching circuit 6 is connected between the input terminal 4 and the gate terminal 1a of the transistor 1, and is a circuit for matching the input impedance of the transistor 1 and the impedance of the signal source.
  • the output matching circuit 7 is connected between the drain terminal 1c and the output terminal 5 of the transistor 1, and is a circuit for matching the output impedance of the transistor 1 and the impedance of the load.
  • the metal carrier 8 forms a ground plane of the power amplifier, and the semiconductor substrate 2, the input matching circuit 6, and the output matching circuit 7 are mounted thereon.
  • the vias 11a, 11b, and 11c are formed in the multilayer circuit board 3, and the vias 11a, 11b, and 11c are electrically connected to the pads 12a, 12b, and 12c arranged on the circuit board 3e that is the uppermost layer of the multilayer circuit board 3.
  • the connection terminal 13 is a first connection terminal that electrically connects the drain terminal 1 c of the transistor 1 and the via 11 c formed in the multilayer circuit board 3.
  • the connection terminal 14 electrically connects the gate terminal 1a of the transistor 1 and the series resonant circuit 19 formed in the multilayer circuit board 3 via the via 11a formed in the multilayer circuit board 3.
  • the second connection terminal is a first connection terminal that electrically connects the drain terminal 1 c of the transistor 1 and the via 11 c formed in the multilayer circuit board 3.
  • connection terminal 15 is a third connection terminal that electrically connects the source terminal 1 b of the transistor 1 and the ground, which is a constant potential terminal, via a via 11 b formed in the multilayer circuit board 3. .
  • the connection terminals 13, 14, and 15 are mounted by flip chip mounting.
  • the pattern structure 16 is a structure formed between the semiconductor substrate 2 and the multilayer circuit board 3.
  • the bonding wire 17 electrically connects the input matching circuit 6 and the pad 12a.
  • the input matching circuit 6 is electrically connected to the gate terminal 1a of the transistor 1 through the bonding wire 17, the pad 12a, the via 11a, and the connection terminal 14.
  • the bonding wire 18 electrically connects the output matching circuit 7 and the pad 12c.
  • the output matching circuit 7 is electrically connected to the drain terminal 1c of the transistor 1 via the bonding wire 18, the pad 12c, the via 11c, and the connection terminal 13.
  • a series resonance circuit 19 which is a harmonic processing circuit is connected between the gate terminal 1a of the transistor 1 and the ground which is a constant potential end, and a second harmonic or a third or higher harmonic of the operating frequency of the transistor 1.
  • the series resonance circuit 19 is formed on the multilayer circuit board 3.
  • the series resonance circuit 19 includes a series circuit of an inductor 20 that is a first inductor and a capacitor 21 that is a first capacitor.
  • FIG. 4 is a plan view of the semiconductor substrate 2 and the transistor 1 as viewed from above.
  • the semiconductor substrate 2 includes a gate terminal 1a, a source terminal 1b, and a drain terminal 1c of the transistor 1, and a via 31 that connects the source terminal 1b and the metal carrier 8 that is a constant potential end.
  • the source terminal 1b of the transistor 1 is connected to the constant potential terminal via the via 31 and grounded.
  • FIG. 5 is a plan view of the circuit board 3a forming the first layer in the multilayer circuit board 3, as viewed from above.
  • the circuit board 3 a includes vias 41 to 44 and electrode patterns 45 and 46 that form part of the capacitor 21 that constitutes the series resonance circuit 19.
  • FIG. 6 is a plan view of the circuit board 3b forming the second layer in the multilayer circuit board 3, as viewed from above.
  • the circuit board 3 b includes vias 51 and 52 and electrode patterns 53 and 54 that form part of the capacitor 21 that constitutes the series resonant circuit 19.
  • FIG. 7 is a plan view of the circuit board 3c forming the third layer in the multilayer circuit board 3 as viewed from above.
  • the circuit board 3 c includes vias 61 to 64 and wiring patterns 65 and 66 forming part of the inductor 20 constituting the series resonant circuit 19.
  • FIG. 8 is a plan view of the circuit board 3d forming the fourth layer in the multilayer circuit board 3 as viewed from above.
  • the circuit board 3 d includes vias 71 to 74 and wiring patterns 75 and 76 that form part of the inductor 20 that constitutes the series resonant circuit 19.
  • FIG. 9 is a plan view of the circuit board 3e forming the fifth layer in the multilayer circuit board 3 as viewed from above.
  • the circuit board 3 e includes vias 81 to 84 and wiring patterns 85 and 86 forming part of the inductor 20 constituting the series resonant circuit 19.
  • the electrode patterns 45 and 46 forming a part of the capacitor 21 are grounded by being connected to the constant potential terminal via the vias 42 and 43 and the connection terminal 15.
  • the electrode patterns 53 and 54 that form part of the capacitor 21 are connected to the wiring patterns 65 and 66 that form part of the inductor 20 via the vias 62 and 63.
  • the wiring patterns 65 and 66 that form part of the inductor 20 are connected to the wiring patterns 75 and 76 that form part of the inductor 20 via the vias 72 and 73.
  • the wiring patterns 75 and 76 that form part of the inductor 20 are connected to the wiring patterns 85 and 86 that form part of the inductor 20 via the vias 82 and 83.
  • the wiring patterns 85 and 86 are connected to the gate terminal 1 a of the transistor 1 through the vias 84, 74, 64, 52 and 44 and the connection terminal 14.
  • the vias 81, 71, 61, 51, 41 are connected to the drain terminal 1 c of the transistor 1 through the connection terminal 13.
  • Electric charges are stored in the electrode patterns 53 and 54 forming a part of the capacitor 21 via the wiring patterns 65, 66, 75, 76, 85 and 86.
  • the grounded electrode patterns 45 and 46 charges having different signs from the charges stored in the electrode patterns 53 and 54 are stored. Since the dielectric which comprises the circuit board 3b is arrange
  • the wiring patterns 65, 66, 75, 76, 85, 86 can be regarded as inductors by the magnetic field generated around the wiring pattern, and the inductor 20 is formed.
  • the series resonance circuit 19 in which the inductor 20 and the capacitor 21 are connected in series is formed in the multilayer circuit board 3, and the series resonance circuit 19 is connected to the gate terminal 1 a of the transistor 1 in a shunt.
  • the constants of the inductor 20 and the capacitor 21 are selected so that the series resonance circuit 19 performs series resonance at the second harmonic of the fundamental frequency that is the operating frequency of the transistor 1 or the third harmonic or higher.
  • the impedance with respect to the second harmonic or the third harmonic or higher is short-circuited.
  • the impedance with respect to the second harmonic or the third or higher harmonic is short-circuited, so that the power amplifier operates with high efficiency.
  • a method of connecting the series resonant circuit 19 and the gate terminal 1a of the transistor 1 by wire bonding or a wiring pattern on a semiconductor substrate is used, there is an excess between the series resonant circuit 19 and the gate terminal 1a of the transistor 1. Since the inductance component is formed, the minimum value of the inductor forming the series resonance circuit 19 is limited by the wire bonding and the wiring pattern on the semiconductor substrate.
  • the multilayer circuit board 3 arranged at a position that forms a layer with the semiconductor substrate 2 is formed of a plurality of circuit boards 3a to 3e, and the plurality of circuit boards 3a to 3e are formed as shown in FIGS.
  • the series resonant circuit 19 and the gate terminal 1a of the transistor 1 are connected without using wire bonding or a wiring pattern on the semiconductor substrate.
  • the multilayer circuit board 3 is disposed at a position that forms a layer with the semiconductor substrate 2, an increase in the area of the semiconductor substrate 2 can be suppressed. For this reason, cost reduction can be realized.
  • the second harmonic or the third or higher harmonic of the operating frequency of the transistor 1 is connected between the gate terminal 1a of the transistor 1 and the constant potential terminal. Since the series resonant circuit 19 that resonates with a wave is formed on the multilayer circuit board 3, the harmonic processing circuit composed of the spiral inductor and the MIM capacitor is not formed on the semiconductor substrate 2. There is an effect that a small and low-cost power amplifier capable of avoiding the variation of the above can be obtained.
  • the example in which the multilayer circuit board 3 on which the series resonance circuit 19 is formed is applied to one transistor 1 is shown.
  • the series resonance circuit 19 is applied to a plurality of transistors 1.
  • a multilayer circuit board 3 on which is formed may be applied.
  • the transistor 1 is an FET type semiconductor.
  • the present invention is not limited to this, and the transistor 1 may be a semiconductor other than an FET.
  • the multilayer circuit board 3 is formed of five layers of circuit boards 3a to 3e.
  • the multilayer circuit board 3 may be a single-layer single-layer circuit board, or two to four layers or A multilayer circuit board 3 formed of six or more circuit boards may be used.
  • the electrode patterns 45, 46, 53, and 54 that form the capacitor 21 are arranged between the circuit board 3a that forms the multilayer circuit board 3 and the circuit board 3b. Although shown, the electrode patterns 45, 46, 53, and 54 forming the capacitor 21 may be disposed in addition to the area between the circuit board 3a and the circuit board 3b.
  • the circuit boards 3c to 3e forming the multilayer circuit board 3 are arranged with the wiring patterns 65, 66, 75, 76, 85, 86 forming the inductor 20 shown therein. However, the wiring patterns 65, 66, 75, 76, 85, 86 may be arranged on circuit boards other than the circuit boards 3c to 3e.
  • Embodiment 2 FIG. In the first embodiment, the inductor 20 and the capacitor 21 constituting the series resonant circuit 19 are all formed in the multilayer circuit board 3. However, the inductor constituting the series resonant circuit 19 is shown. Of the capacitors 20 and 21, the capacitor 21 may be formed in the semiconductor substrate 2.
  • the multilayer circuit board 3 is a board formed of a plurality of circuit boards 3f to 3h.
  • the multilayer circuit board 3 is disposed at a position that forms a layer with the semiconductor substrate 2 and is electrically connected to the semiconductor substrate 2.
  • the connection terminal 15a is a terminal for connecting the multilayer circuit board 3 and the MIM capacitor 91 shown in FIG.
  • the connection terminal 15 b is a terminal for connecting the back surface of the circuit board 3 f forming the multilayer circuit board 3 and the source terminal 1 b of the transistor 1.
  • the connection terminals 15a and 15b are mounted by flip chip mounting.
  • the semiconductor substrate 2 includes a gate terminal 1 a, a source terminal 1 b and a drain terminal 1 c of the transistor 1, a via 31 connecting the source terminal 1 b and the metal carrier 8 which is a constant potential end, and an MIM capacitor 91.
  • the source terminal 1b of the transistor 1 is connected to the constant potential terminal via the via 31 and grounded.
  • One end of the electrode of the MIM capacitor 91 is connected to the source terminal 1b and grounded.
  • FIG. 12 is a plan view of the circuit board 3f forming the first layer in the multilayer circuit board 3 as viewed from above.
  • the circuit board 3 f includes vias 101 to 104 and wiring patterns 105 and 106 that form part of the inductor 20 that constitutes the series resonant circuit 19.
  • FIG. 13 is a plan view of the back surface of the circuit board 3 f forming the first layer in the multilayer circuit board 3.
  • the back surface of the circuit board 3 f includes vias 101 to 104 and a wiring pattern 107.
  • FIG. 14 is a plan view of the circuit board 3g forming the second layer in the multilayer circuit board 3 as viewed from above.
  • the circuit board 3 g includes vias 111 to 114 and wiring patterns 115 and 116 that form part of the inductor 20 that constitutes the series resonant circuit 19.
  • FIG. 15 is a plan view of the circuit board 3h forming the third layer in the multilayer circuit board 3 as viewed from above.
  • the circuit board 3 h includes vias 121 to 124 and wiring patterns 125 and 126 forming part of the inductor 20 constituting the series resonant circuit 19.
  • the wiring pattern 107 formed on the back surface of the circuit board 3f is connected to the source terminal 1b of the transistor 1 via the connection terminal 15b and grounded, thereby forming the ground surface of the multilayer circuit board 3.
  • the MIM capacitor 91 formed on the semiconductor substrate 2 forms the capacitor 21 constituting the series resonance circuit 19.
  • the inductor 20 constituting the series resonance circuit 19 is formed by connecting the wiring patterns 105, 106, 115, 116, 125, 126 via the vias 112, 113, 122, 123.
  • the inductor 20 is connected to the other end of the electrode of the MIM capacitor 91 through the vias 102 and 103 and the connection terminal 15a, whereby the series resonance circuit 19 is formed. Further, the inductor 20 is connected to the gate terminal 1a of the transistor 1 through the vias 124, 114, 104 and the connection terminal 14, so that the series resonant circuit 19 is connected to the gate terminal 1a of the transistor 1 in a shunt. Yes.
  • the constants of the inductor 20 and the capacitor 21 are selected so that the series resonance circuit 19 performs series resonance at the second harmonic of the fundamental frequency that is the operating frequency of the transistor 1 or the third harmonic or higher.
  • the impedance with respect to the second harmonic or the third harmonic or higher is short-circuited. Even when the capacitor 21 is formed in the semiconductor substrate 2 by short-circuiting the impedance to the second harmonic or the third harmonic or higher at the gate terminal 1a of the transistor 1, the same as in the first embodiment.
  • the power amplifier operates with high efficiency.
  • the example in which the multilayer circuit board 3 in which the series resonant circuit 19 is formed is applied to one transistor 1 is shown, but the series resonant circuit 19 is applied to a plurality of transistors 1.
  • a multilayer circuit board 3 on which is formed may be applied.
  • the transistor 1 is an FET type semiconductor.
  • the present invention is not limited to this, and the transistor 1 may be a semiconductor other than an FET.
  • the multilayer circuit board 3 is formed of the three-layer circuit boards 3f to 3h is shown.
  • a single-layer single-layer circuit board may be used, and a circuit having two or more layers may be used. It may be a multilayer circuit board 3 formed of a substrate.
  • Embodiment 3 FIG. In the second embodiment, the example in which the multilayer circuit board 3 is formed of the three-layer circuit boards 3f to 3h has been described. However, the multilayer circuit board 3 may be formed of a single-layer one-layer circuit board. 16 is a sectional view showing a power amplifier according to Embodiment 3 of the present invention. In FIG. 16, the same reference numerals as those in FIG. The multilayer circuit board 3 is a board formed from the circuit board 3 i, and the multilayer circuit board 3 is disposed at a position forming a layer with the semiconductor substrate 2 and is electrically connected to the semiconductor substrate 2.
  • FIG. 17 is a plan view of the back surface of the circuit board 3 i forming the first layer in the multilayer circuit board 3.
  • the back surface of the circuit board 3i includes vias 131 to 134 and wiring patterns 135a and 135b.
  • FIG. 18 is a plan view of the circuit board 3 i forming the first layer in the multilayer circuit board 3 as viewed from above.
  • the circuit board 3 i includes vias 131 to 134 and a wiring pattern 136.
  • the wiring pattern 136 is grounded by being connected to the source terminal 1b of the transistor 1 via the vias 133 and 134 and the connection terminal 15b, and forms a ground plane of the circuit board 3i.
  • the inductor 20 constituting the series resonance circuit 19 is formed by wiring patterns 135a and 135b.
  • the capacitor 21 constituting the series resonance circuit 19 is carried by the MIM capacitor 91 formed on the semiconductor substrate 2 as in the second embodiment. One end of the electrode of the MIM capacitor 91 is connected to the source terminal 1b of the transistor 1 and grounded.
  • the series resonance circuit 19 is formed by connecting the inductor 20 to the capacitor 21 via the connection terminal 15a. Further, the inductor 20 is connected to the gate terminal 1 a of the transistor 1 through the via 132 and the connection terminal 14, so that the series resonance circuit 19 is connected to the gate terminal 1 a of the transistor 1 in a shunt.
  • the input matching circuit 6 and the gate terminal 1a of the transistor 1 are connected through a bonding wire 17, a pad 12a, and a via 132.
  • the output matching circuit 7 and the drain terminal 1c of the transistor 1 are connected via a bonding wire 18, a pad 12c, and a via 131.
  • the constants of the inductor 20 and the capacitor 21 are selected so that the series resonance circuit 19 performs series resonance at the second harmonic of the fundamental frequency that is the operating frequency of the transistor 1 or the third harmonic or higher.
  • the impedance with respect to the second harmonic or the third harmonic or higher is short-circuited.
  • the capacitor 21 is formed in the semiconductor substrate 2 by short-circuiting the impedance to the second harmonic or the third harmonic or higher at the gate terminal 1a of the transistor 1, the same as in the second embodiment.
  • the power amplifier operates with high efficiency.
  • the inductor 20 since the inductor 20 is formed without vias between the multilayer circuit boards 3, the variation in inductance due to the manufacturing variation of vias can be reduced, and the production yield can be improved. it can.
  • Embodiment 4 FIG.
  • the inductor 20 and the capacitor 21 constituting the series resonant circuit 19 are all formed in the multilayer circuit board 3.
  • the inductor constituting the series resonant circuit 19 is shown.
  • the capacitors 20 and 21 may be formed in the semiconductor substrate 2.
  • the multilayer circuit board 3 is a board formed of a plurality of circuit boards 3j and 3k.
  • the multilayer circuit board 3 is disposed at a position that forms a layer with the semiconductor substrate 2 and is electrically connected to the semiconductor substrate 2.
  • the connection terminals 15c and 15d are terminals for connecting the multilayer circuit board 3 and the semiconductor substrate 2, and are mounted by flip chip mounting.
  • the semiconductor substrate 2 includes a gate terminal 1a, a source terminal 1b, a drain terminal 1c of the transistor 1, a via 31 that connects the source terminal 1b and the metal carrier 8 that is a constant potential end, and a spiral inductor 141. .
  • the source terminal 1b of the transistor 1 is connected to the constant potential terminal via the via 31 and grounded.
  • the gate terminal 1 a of the transistor 1 is connected to the spiral inductor 141.
  • FIG. 21 is a plan view of the circuit board 3j forming the first layer in the multilayer circuit board 3 as viewed from above.
  • the circuit board 3 j includes vias 151 to 156 and electrode patterns 157 and 158 that form part of the capacitor 21 constituting the series resonant circuit 19.
  • FIG. 22 is a plan view of the circuit board 3k forming the second layer in the multilayer circuit board 3 as viewed from above.
  • the circuit board 3 k includes vias 161 to 164 and electrode patterns 165 and 166 that form part of the capacitor 21 that constitutes the series resonance circuit 19.
  • the electrode patterns 157 and 158 are grounded by being connected to the source terminal 1b of the transistor 1 via the vias 152 and 153 and the connection terminal 15d.
  • the electrode patterns 165 and 166 are connected to the spiral inductor 141 through the vias 162, 163, 154, and 155 and the connection terminal 15c.
  • Electric charges are stored in the electrode patterns 165 and 166 forming a part of the capacitor 21 through the spiral inductor 141, the connection terminal 15 c and the vias 154, 155, 162 and 163.
  • the grounded electrode patterns 157 and 158 store charges having a sign different from the charges stored in the electrode patterns 165 and 166. Since the dielectric constituting the circuit board 3k is disposed between the electrode patterns 165 and 166 and the electrode patterns 157 and 158, the electrode patterns 165 and 166 and the electrode patterns 157 and 158 are parallel to each other. A plate capacity is formed. That is, the capacitor 21 is formed.
  • the electrode patterns 165 and 166 are connected to the spiral inductor 141 through the vias 162, 163, 154, and 155 and the connection terminal 15c, whereby the series resonance circuit 19 is formed.
  • the constants of the inductor 20 and the capacitor 21 are selected so that the series resonance circuit 19 performs series resonance at the second harmonic of the fundamental frequency that is the operating frequency of the transistor 1 or the third harmonic or higher.
  • the impedance with respect to the second harmonic or the third harmonic or higher is short-circuited. Even when the inductor 20 is formed in the semiconductor substrate 2 by short-circuiting the impedance with respect to the second harmonic or the third harmonic or higher at the gate terminal 1a of the transistor 1, the same as in the first embodiment.
  • the power amplifier operates with high efficiency.
  • Embodiment 5 FIG.
  • the series resonant circuit 19 that resonates at the second harmonic or the third harmonic or higher of the operating frequency of the transistor 1 is formed on the multilayer circuit board 3.
  • One end is connected to the gate terminal 1a of the transistor 1, and an open stub having a quarter wavelength line length is formed on the multilayer circuit board 3 at the second harmonic or third harmonic of the operating frequency of the transistor 1 You may be made to do.
  • FIG. 23 is a circuit diagram showing a power amplifier according to the fifth embodiment of the present invention.
  • the harmonic processing circuit 171 includes an open stub 172 having one end connected to the gate terminal 1 a of the transistor 1.
  • the open stub 172 is a first open stub having a line length of ⁇ / 4 (quarter wavelength) at the second harmonic or the third harmonic or higher of the operating frequency of the transistor 1, and the open stub 172 is It is formed on the multilayer circuit board 3.
  • the multilayer circuit board 3 is a board formed from a plurality of circuit boards 3m, 3n, and 3p.
  • the multilayer circuit board 3 is disposed at a position that forms a layer with the semiconductor substrate 2, and is electrically connected to the semiconductor substrate 2.
  • the connection terminal 15e is a terminal for connecting the multilayer circuit board 3 and the semiconductor substrate 2, and is mounted by flip chip mounting.
  • FIG. 25 is a plan view of the circuit board 3m forming the first layer in the multilayer circuit board 3 as viewed from above.
  • the circuit board 3 m includes vias 181 and 182 and wiring patterns 183 and 184.
  • FIG. 26 is a plan view of the back surface of the circuit board 3m forming the first layer in the multilayer circuit board 3.
  • the back surface of the circuit board 3m includes vias 181 and 182 and a wiring pattern 185.
  • FIG. 27 is a plan view of the circuit board 3n forming the second layer in the multilayer circuit board 3 as viewed from above.
  • the circuit board 3n includes vias 191 to 194 and wiring patterns 195 and 196 that form part of an open stub 172 that constitutes the harmonic processing circuit 171.
  • FIG. 28 is a plan view of the circuit board 3p forming the third layer in the multilayer circuit board 3 as viewed from above.
  • the circuit board 3p includes vias 201 to 204 and wiring patterns 205 and 206 forming part of an open stub 172 constituting the harmonic processing circuit 171.
  • the wiring pattern 185 is grounded by being connected to the source terminal 1b of the transistor 1 via the connection terminal 15e, and forms a ground plane of the multilayer circuit board 3.
  • the open stub 172 constituting the harmonic processing circuit 171 is formed by connecting wiring patterns 183, 184, 195, 196, 205, 206 via vias 192, 193, 202, 203.
  • the open stub 172 is connected to the gate terminal 1 a of the transistor 1 through the vias 182, 194 and 204 and the connection terminal 14.
  • the open stub 172 has a line length of ⁇ / 4 at the second harmonic or the third or higher harmonic of the operating frequency of the transistor 1, the second harmonic or the third harmonic at the gate terminal 1 a of the transistor 1.
  • the impedance with respect to the above harmonics becomes a short circuit. Since the impedance to the second harmonic or the third harmonic or higher is short-circuited at the gate terminal 1a of the transistor 1, the power amplifier operates with high efficiency as in the first to fourth embodiments.
  • the series resonant circuit 19 is connected to the gate terminal 1a of the transistor 1. However, the series resonant circuit 19 is connected to the drain terminal 1c of the transistor 1. Alternatively, the series resonant circuit 19 may be connected to both the gate terminal 1a and the drain terminal 1c of the transistor 1.
  • FIG. 29 is a circuit diagram showing a power amplifier according to Embodiment 6 of the present invention.
  • a series resonance circuit 211 which is a harmonic processing circuit, is connected between the drain terminal 1c of the transistor 1 and the constant potential end, and resonates at the second harmonic or the third or higher harmonic of the operating frequency of the transistor 1.
  • the series resonance circuit 211 is formed on the multilayer circuit board 3.
  • the series resonance circuit 211 includes a series circuit including an inductor 212 that is a second inductor and a capacitor 213 that is a second capacitor.
  • FIG. 30 is a plan view of the circuit board 3e forming the fifth layer in the multilayer circuit board 3 as viewed from above.
  • the circuit board 3 e includes vias 221 to 224 and wiring patterns 225 and 226 that form part of the inductors 20 and 212.
  • the series resonant circuit 19 is formed by electrode patterns 45 and 53, wiring patterns 65, 75 and 225 and vias 62, 72 and 222.
  • One end of the series resonance circuit 19 is connected to the gate terminal 1a of the transistor 1 through the vias 44, 52, 64, 74, and 224 and the connection terminal 14, and the other end of the series resonance circuit 19 is connected to the via 42.
  • the source terminal 1b of the transistor 1 via the terminal 15 it is grounded.
  • the series resonance circuit 211 is formed by electrode patterns 46 and 54, wiring patterns 66, 76 and 226, and vias 63, 73 and 223. One end of the series resonance circuit 211 is connected to the drain terminal 1 c of the transistor 1 via the vias 41, 51, 61, 71, and 221 and the connection terminal 13, and the other end of the series resonance circuit 211 is connected to the via 43. By being connected to the source terminal 1b of the transistor 1 via the terminal 15, it is grounded.
  • the drain of the transistor 1 is selected by selecting constants of the inductor 212 and the capacitor 213 so that the series resonant circuit 211 performs series resonance at the second harmonic of the fundamental frequency, which is the operating frequency of the transistor 1, or the third harmonic or higher.
  • the impedance with respect to the second harmonic or the third harmonic or higher becomes low impedance.
  • the impedance with respect to the second harmonic or the third harmonic or higher becomes low impedance, so that the power amplifier operates with high efficiency.
  • the power amplifier operates more efficiently than in the first to fourth embodiments.
  • Embodiment 7 FIG.
  • the open stub 172 is connected to the gate terminal 1a of the transistor 1.
  • the open stub 172 may be connected to the drain terminal 1c of the transistor 1
  • the open stub 172 may be connected to both the gate terminal 1a and the drain terminal 1c of the transistor 1.
  • FIG. 31 is a circuit diagram showing a power amplifier according to Embodiment 7 of the present invention.
  • the harmonic processing circuit 231 includes an open stub 232 having one end connected to the drain terminal 1 c of the transistor 1.
  • the open stub 232 is a second open stub having a line length of ⁇ / 4 at the second harmonic or the third harmonic or higher of the operating frequency of the transistor 1.
  • the open stub 232 is formed on the multilayer circuit board 3. ing.
  • FIG. 32 is a plan view of the circuit board 3p forming the third layer in the multilayer circuit board 3 as viewed from above. 32, the circuit board 3p includes vias 241 to 244 and wiring patterns 245 and 246 that form part of the open stubs 172 and 232.
  • the open stub 172 is formed by wiring patterns 183, 195, 245 and vias 192, 242. One end of the open stub 172 is connected to the gate terminal 1 a of the transistor 1 through the vias 182, 194, 244 and the connection terminal 14.
  • the open stub 232 is formed by wiring patterns 184, 196, 246 and vias 193, 243. One end of the open stub 232 is connected to the drain terminal 1 c of the transistor 1 through the vias 181, 191 and 241 and the connection terminal 13.
  • the open stub 232 has a line length of ⁇ / 4 at the second harmonic or the third or higher harmonic of the operating frequency of the transistor 1, the second harmonic or the third harmonic at the drain terminal 1 c of the transistor 1.
  • the impedance with respect to the above harmonics becomes low impedance.
  • the impedance with respect to the second harmonic or the third harmonic or higher becomes low impedance, so that the power amplifier operates with high efficiency.
  • the power amplifier operates more efficiently than the fifth embodiment.
  • Embodiment 8 FIG.
  • the output matching circuit 7 is electrically connected to the drain terminal 1c of the transistor 1 through the bonding wire 18, the pad 12c, the via 11c, and the connection terminal 13.
  • the connection between the drain terminal 1c of the transistor 1 and the output matching circuit 7 may be connected only by a bonding wire.
  • FIG. 33 is a cross-sectional view showing a power amplifier according to Embodiment 8 of the present invention.
  • the bonding wire 250 connects between the drain terminal 1 c of the transistor 1 and the output matching circuit 7.
  • the multilayer circuit board 3 is disposed so as not to overlap the drain terminal 1 c of the transistor 1, and is connected between the drain terminal 1 c of the transistor 1 and the output matching circuit 7 by the bonding wire 250. Is connected.
  • the drain terminal 1c of the transistor 1 and the output matching circuit 7 can be connected without via the via 11c, the via connected in series between the drain terminal 1c of the transistor 1 and the output matching circuit 7
  • the parasitic inductance component due to the bonding wire can be reduced. Therefore, it is possible to avoid narrowing the bandwidth of the power amplifier.
  • the power amplifier according to the present invention is suitable for a high necessity for realizing a high-efficiency operation.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

The present invention is configured such that a serial resonance circuit 19 is formed on a multilayer circuit substrate 3, the serial resonance circuit 19 being connected between the fixed-potential terminal and the gate terminal 1a of a transistor 1, and the serial resonance circuit 19 resonating at a second or a higher harmonic of the operating frequency of the transistor 1. This produces the effect of yielding a small, inexpensive power amplifier in which variation in impedance at a harmonic can be avoided without forming a harmonic processing circuit comprising a spiral inductor and an MIM capacitor on a semiconductor substrate 2.

Description

電力増幅器Power amplifier
　この発明は、高効率で動作する電力増幅器に関するものである。 The present invention relates to a power amplifier that operates with high efficiency.
　通信装置やレーダ装置などには、送信信号の電力を所望のレベルまで増幅する電力増幅器が実装される。
　このような電力増幅器には、高電子移動度トランジスタであるＨＥＭＴ（Ｈｉｇｈ　Ｅｌｅｃｔｒｏｎ　Ｍｏｂｉｌｉｔｙ　Ｔｒａｎｓｉｓｔｏｒ）や、電界効果トランジスタであるＦＥＴ（Ｆｉｅｌｄ　Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ）などの半導体素子が使用される。 A communication device, a radar device, or the like is equipped with a power amplifier that amplifies the power of a transmission signal to a desired level.
For such a power amplifier, a semiconductor device such as a high electron mobility transistor (HEMT) that is a high electron mobility transistor or a field effect transistor (FET) that is a field effect transistor is used.
　電力増幅器の高出力化に伴って半導体素子の自己発熱が増加する。半導体素子の自己発熱による性能劣化を軽減するため、電力増幅器に対する高効率化が要求されており、半導体素子のゲート端子での２次高調波のインピーダンスを短絡に近い負荷条件に設定すれば、電力増幅器が高効率で動作をすることが知られている。
　また、半導体素子のドレイン端子での２次高調波のインピーダンスを短絡もしくは開放となる負荷条件に設定することでも、電力増幅器が高効率で動作することが知られている。
　動作周波数の２次高調波をゲート端子又はドレイン端子で、短絡に近い負荷条件に設定するには、動作周波数の２次高調波に対して、非常に低インピーダンスとなる高調波処理回路を付加する必要がある。 As the output of the power amplifier increases, the self-heating of the semiconductor element increases. In order to reduce performance degradation due to self-heating of the semiconductor element, high efficiency is required for the power amplifier, and if the impedance of the second harmonic at the gate terminal of the semiconductor element is set to a load condition close to a short circuit, It is known that amplifiers operate with high efficiency.
It is also known that the power amplifier operates with high efficiency by setting the second harmonic impedance at the drain terminal of the semiconductor element to a load condition that is short-circuited or opened.
To set the second harmonic of the operating frequency to a load condition close to a short circuit at the gate terminal or the drain terminal, a harmonic processing circuit having a very low impedance is added to the second harmonic of the operating frequency. There is a need.
　以下の特許文献１には、動作周波数の２次高調波に対して低インピーダンスとなる高調波処理回路として、共振回路やバンドパスフィルタが、半導体基板の外部基板側に配置されている電力増幅器が開示されている。この高調波処理回路は、ワイヤボンディング等によって、その半導体基板上のトランジスタと接続されている。
　高調波処理回路をワイヤボンディング等によって半導体基板上のトランジスタと接続する場合、外部基板の実装精度によるばらつきに起因して、半導体基板と外部基板とを接続するボンディングワイヤの長さにばらつきが生じる。ボンディングワイヤの長さにばらつきが生じると、高調波処理回路を形成するインダクタンス成分が変化するため、高調波に対するインピーダンスもばらつきが生じる。
　高調波に対するインピーダンスにばらつきが生じると、高調波に対する負荷を所望のインピーダンスにすることができず、電力増幅器の出力や効率が劣化するなど、電力増幅器の特性にばらつきが生じる。このため、歩留まりの低下を引き起こして、高コスト化を招く可能性がある。 Patent Document 1 below discloses a power amplifier in which a resonance circuit and a band-pass filter are arranged on the external substrate side of a semiconductor substrate as a harmonic processing circuit having a low impedance with respect to the second harmonic of the operating frequency. It is disclosed. This harmonic processing circuit is connected to a transistor on the semiconductor substrate by wire bonding or the like.
When the harmonic processing circuit is connected to the transistor on the semiconductor substrate by wire bonding or the like, the length of the bonding wire connecting the semiconductor substrate and the external substrate varies due to the variation due to the mounting accuracy of the external substrate. When the length of the bonding wire varies, the inductance component forming the harmonic processing circuit changes, so that the impedance with respect to the harmonic also varies.
When the impedance with respect to the harmonics varies, the load with respect to the harmonics cannot be set to a desired impedance, resulting in variations in the characteristics of the power amplifier, such as deterioration in output and efficiency of the power amplifier. For this reason, it may cause a decrease in yield and increase the cost.
　以下の特許文献２には、ボンディングワイヤの長さのばらつきによるインピーダンスのばらつきを回避するために、スパイラルインダクタとＭＩＭ（Ｍｅｔａｌ　Ｉｎｓｕｌａｔｉｏｎ　Ｍｅｔａｌ）キャパシタからなる高調波処理回路を半導体チップ上に形成している電力増幅器が開示されている。 In Patent Document 2 below, a harmonic processing circuit including a spiral inductor and a MIM (Metal Insulation Metal) capacitor is formed on a semiconductor chip in order to avoid variations in impedance due to variations in bonding wire length. A power amplifier is disclosed.
国際公開第２０１２／１６０７５５号International Publication No. 2012/160755 特開２００８－１０９２２７号公報JP 2008-109227 A
　従来の電力増幅器は以上のように構成されているので、スパイラルインダクタとＭＩＭキャパシタからなる高調波処理回路を半導体チップ上に形成すれば、ボンディングワイヤの長さのばらつきによるインピーダンスのばらつきを回避することができる。しかし、このような高調波処理回路を半導体チップ上に形成することで、半導体チップの面積が大きくなり、また、コスト高になってしまうという課題があった。 Since the conventional power amplifier is configured as described above, if a harmonic processing circuit including a spiral inductor and an MIM capacitor is formed on a semiconductor chip, impedance variation due to bonding wire length variation can be avoided. Can do. However, by forming such a harmonic processing circuit on a semiconductor chip, there is a problem that the area of the semiconductor chip is increased and the cost is increased.
　この発明は上記のような課題を解決するためになされたもので、スパイラルインダクタとＭＩＭキャパシタからなる高調波処理回路を半導体基板上に形成することなく、高調波に対するインピーダンスのばらつきを回避することができる小型で低コストな電力増幅器を得ることを目的とする。 The present invention has been made in order to solve the above-described problems, and can avoid variations in impedance with respect to harmonics without forming a harmonic processing circuit including a spiral inductor and an MIM capacitor on a semiconductor substrate. An object is to obtain a small and low-cost power amplifier.
　この発明に係る電力増幅器は、増幅対象の信号が入力される第１の端子と、定電位端と接続されている第２の端子と、増幅後の信号を出力する第３の端子とを有するトランジスタが形成されている半導体基板と、半導体基板と層をなす位置に配置され、その半導体基板と電気的に接続されている多層回路基板と、トランジスタの第１の端子に接続され、第１の端子の入力側のインピーダンスとトランジスタの入力インピーダンスとの整合を図る入力整合回路と、トランジスタの第３の端子に接続され、第３の端子の出力側のインピーダンスとトランジスタの出力インピーダンスとの整合を図る出力整合回路とを備え、トランジスタの第１の端子と定電位端との間に接続され、トランジスタの動作周波数の２次の高調波又は３次以上の高調波で共振する第１の共振回路が多層回路基板に形成されているようにしたものである。 The power amplifier according to the present invention has a first terminal to which a signal to be amplified is input, a second terminal connected to the constant potential terminal, and a third terminal for outputting the amplified signal. A semiconductor substrate on which a transistor is formed; a multilayer circuit substrate that is disposed at a position that forms a layer with the semiconductor substrate; and that is electrically connected to the semiconductor substrate; a first terminal of the transistor; An input matching circuit that matches the impedance on the input side of the terminal and the input impedance of the transistor, and is connected to the third terminal of the transistor, and matches the impedance on the output side of the third terminal and the output impedance of the transistor. An output matching circuit, connected between the first terminal and the constant potential end of the transistor, and a second harmonic or a third or higher harmonic of the operating frequency of the transistor In which the first resonant circuit resonating is so formed in the multilayer circuit board.
　この発明によれば、トランジスタの第１の端子と定電位端との間に接続され、トランジスタの動作周波数の２次の高調波又は３次以上の高調波で共振する第１の共振回路が多層回路基板に形成されているように構成したので、スパイラルインダクタとＭＩＭキャパシタからなる高調波処理回路を半導体基板上に形成することなく、高調波に対するインピーダンスのばらつきを回避することができる小型で低コストな電力増幅器が得られる効果がある。 According to the present invention, the first resonance circuit connected between the first terminal and the constant potential end of the transistor and resonating at the second harmonic or the third harmonic or higher of the operating frequency of the transistor is a multilayer. Since it is configured to be formed on a circuit board, it is possible to avoid variations in impedance with respect to harmonics without forming a harmonic processing circuit consisting of a spiral inductor and MIM capacitor on a semiconductor substrate. There is an effect that a simple power amplifier can be obtained.
この発明の実施の形態１による電力増幅器を構成する多層回路基板と半導体基板上のトランジスタとの接続関係を示す断面図である。It is sectional drawing which shows the connection relation of the multilayer circuit board which comprises the power amplifier by Embodiment 1 of this invention, and the transistor on a semiconductor substrate. この発明の実施の形態１による電力増幅器を示す回路図である。1 is a circuit diagram showing a power amplifier according to a first embodiment of the present invention. この発明の実施の形態１による電力増幅器を示す断面図である。It is sectional drawing which shows the power amplifier by Embodiment 1 of this invention. 半導体基板２及びトランジスタ１を上面から見た平面図である。FIG. 3 is a plan view of a semiconductor substrate 2 and a transistor 1 as viewed from above. 多層回路基板３における第１層を形成している回路基板３ａを上面から見た平面図である。3 is a plan view of a circuit board 3a forming a first layer in the multilayer circuit board 3 as viewed from above. FIG. 多層回路基板３における第２層を形成している回路基板３ｂを上面から見た平面図である。FIG. 3 is a plan view of a circuit board 3b forming a second layer in the multilayer circuit board 3 as viewed from above. 多層回路基板３における第３層を形成している回路基板３ｃを上面から見た平面図である。FIG. 3 is a plan view of a circuit board 3c forming a third layer in the multilayer circuit board 3 as viewed from above. 多層回路基板３における第４層を形成している回路基板３ｄを上面から見た平面図である。FIG. 5 is a plan view of a circuit board 3d forming a fourth layer in the multilayer circuit board 3 as viewed from above. 多層回路基板３における第５層を形成している回路基板３ｅを上面から見た平面図である。It is the top view which looked at the circuit board 3e which forms the 5th layer in the multilayer circuit board 3 from the upper surface. この発明の実施の形態２による電力増幅器を示す断面図である。It is sectional drawing which shows the power amplifier by Embodiment 2 of this invention. 半導体基板２及びトランジスタ１を上面から見た平面図である。FIG. 3 is a plan view of a semiconductor substrate 2 and a transistor 1 as viewed from above. 多層回路基板３における第１層を形成している回路基板３ｆを上面から見た平面図である。It is the top view which looked at the circuit board 3f which has formed the 1st layer in the multilayer circuit board 3 from the upper surface. 多層回路基板３における第１層を形成している回路基板３ｆの裏面を見た平面図である。4 is a plan view of a back surface of a circuit board 3f forming a first layer in the multilayer circuit board 3. FIG. 多層回路基板３における第２層を形成している回路基板３ｇを上面から見た平面図である。FIG. 5 is a plan view of a circuit board 3g forming a second layer in the multilayer circuit board 3 as viewed from above. 多層回路基板３における第３層を形成している回路基板３ｈを上面から見た平面図である。FIG. 5 is a plan view of a circuit board 3h forming a third layer in the multilayer circuit board 3 as viewed from above. この発明の実施の形態３による電力増幅器を示す断面図である。It is sectional drawing which shows the power amplifier by Embodiment 3 of this invention. 多層回路基板３における第１層を形成している回路基板３ｉの裏面を見た平面図である。4 is a plan view of a back surface of a circuit board 3i forming a first layer in the multilayer circuit board 3. FIG. 多層回路基板３における第１層を形成している回路基板３ｉを上面から見た平面図である。FIG. 3 is a plan view of a circuit board 3i forming a first layer in the multilayer circuit board 3 as viewed from above. この発明の実施の形態４による電力増幅器を示す断面図である。It is sectional drawing which shows the power amplifier by Embodiment 4 of this invention. 半導体基板２及びトランジスタ１を上面から見た平面図である。FIG. 3 is a plan view of a semiconductor substrate 2 and a transistor 1 as viewed from above. 多層回路基板３における第１層を形成している回路基板３ｊを上面から見た平面図である。It is the top view which looked at the circuit board 3j which forms the 1st layer in the multilayer circuit board 3 from the upper surface. 多層回路基板３における第２層を形成している回路基板３ｋを上面から見た平面図である。It is the top view which looked at the circuit board 3k which has formed the 2nd layer in the multilayer circuit board 3 from the upper surface. この発明の実施の形態５による電力増幅器を示す回路図である。It is a circuit diagram which shows the power amplifier by Embodiment 5 of this invention. この発明の実施の形態５による電力増幅器を示す断面図である。It is sectional drawing which shows the power amplifier by Embodiment 5 of this invention. 多層回路基板３における第１層を形成している回路基板３ｍを上面から見た平面図である。FIG. 3 is a plan view of a circuit board 3m forming a first layer in the multilayer circuit board 3 as viewed from above. 多層回路基板３における第１層を形成している回路基板３ｍの裏面を見た平面図である。4 is a plan view of a back surface of a circuit board 3m forming a first layer in the multilayer circuit board 3. FIG. 多層回路基板３における第２層を形成している回路基板３ｎを上面から見た平面図である。FIG. 3 is a plan view of a circuit board 3n forming a second layer in the multilayer circuit board 3 as viewed from above. 多層回路基板３における第３層を形成している回路基板３ｐを上面から見た平面図である。FIG. 3 is a plan view of a circuit board 3p forming a third layer in the multilayer circuit board 3 as viewed from above. この発明の実施の形態６による電力増幅器を示す回路図である。It is a circuit diagram which shows the power amplifier by Embodiment 6 of this invention. 多層回路基板３における第５層を形成している回路基板３ｅを上面から見た平面図である。It is the top view which looked at the circuit board 3e which forms the 5th layer in the multilayer circuit board 3 from the upper surface. この発明の実施の形態７による電力増幅器を示す回路図である。It is a circuit diagram which shows the power amplifier by Embodiment 7 of this invention. 多層回路基板３における第３層を形成している回路基板３ｐを上面から見た平面図である。FIG. 3 is a plan view of a circuit board 3p forming a third layer in the multilayer circuit board 3 as viewed from above. この発明の実施の形態８による電力増幅器を示す断面図である。It is sectional drawing which shows the power amplifier by Embodiment 8 of this invention.
　以下、この発明をより詳細に説明するために、この発明を実施するための形態について、添付の図面にしたがって説明する。 Hereinafter, in order to explain the present invention in more detail, modes for carrying out the present invention will be described with reference to the accompanying drawings.
実施の形態１．
　図１はこの発明の実施の形態１による電力増幅器を構成する多層回路基板と半導体基板上のトランジスタとの接続関係を示す断面図である。
　また、図２はこの発明の実施の形態１による電力増幅器を示す回路図であり、図３はこの発明の実施の形態１による電力増幅器を示す断面図である。
　図１から図３において、トランジスタ１は増幅対象の信号である高周波信号が入力される第１の端子であるゲート端子１ａと、定電位端と接続されている第２の端子であるソース端子１ｂと、増幅後の高周波信号を出力する第３の端子であるドレイン端子１ｃとを有しているＦＥＴ（電界効果トランジスタ）であり、トランジスタ１は半導体基板２上に形成されている。 Embodiment 1 FIG.
FIG. 1 is a cross-sectional view showing a connection relationship between a multilayer circuit board constituting a power amplifier according to Embodiment 1 of the present invention and a transistor on a semiconductor substrate.
FIG. 2 is a circuit diagram showing a power amplifier according to Embodiment 1 of the present invention, and FIG. 3 is a cross-sectional view showing the power amplifier according to Embodiment 1 of the present invention.
1 to 3, a transistor 1 includes a gate terminal 1a that is a first terminal to which a high-frequency signal that is a signal to be amplified is input, and a source terminal 1b that is a second terminal connected to a constant potential terminal. And a FET (field effect transistor) having a drain terminal 1c which is a third terminal for outputting a high-frequency signal after amplification. The transistor 1 is formed on a semiconductor substrate 2.
　多層回路基板３は複数の回路基板３ａ～３ｅから形成されている基板であり、多層回路基板３は半導体基板２と層をなす位置に配置され、その半導体基板２と電気的に接続されている。
　多層回路基板３として、例えば、低温焼成セラミックス（ＬＴＣＣ：Ｌｏｗ　Ｔｅｍｐｅｒａｔｕｒｅ　Ｃｏ－ｆｉｒｅｄ　Ｃｅｒａｍｉｃｓ）で形成されているものを用いることができる。
　入力端子４は高周波信号を発振する信号源と接続されている端子であり、信号源から発振された高周波信号を入力する。
　出力端子５は負荷が接続されている端子であり、トランジスタ１により増幅された高周波信号を出力する。 The multilayer circuit board 3 is a board formed of a plurality of circuit boards 3a to 3e. The multilayer circuit board 3 is disposed at a position that forms a layer with the semiconductor substrate 2, and is electrically connected to the semiconductor substrate 2. .
As the multilayer circuit board 3, for example, a board formed of low temperature co-fired ceramics (LTCC) can be used.
The input terminal 4 is a terminal connected to a signal source that oscillates a high-frequency signal, and inputs a high-frequency signal oscillated from the signal source.
The output terminal 5 is a terminal to which a load is connected, and outputs a high-frequency signal amplified by the transistor 1.
　入力整合回路６は入力端子４とトランジスタ１のゲート端子１ａとの間に接続され、トランジスタ１の入力インピーダンスと、信号源のインピーダンスとの整合を図る回路である。
　出力整合回路７はトランジスタ１のドレイン端子１ｃと出力端子５との間に接続され、トランジスタ１の出力インピーダンスと、負荷のインピーダンスとの整合を図る回路である。
　金属キャリア８は電力増幅器の接地面を形成しており、半導体基板２、入力整合回路６及び出力整合回路７を実装している。 The input matching circuit 6 is connected between the input terminal 4 and the gate terminal 1a of the transistor 1, and is a circuit for matching the input impedance of the transistor 1 and the impedance of the signal source.
The output matching circuit 7 is connected between the drain terminal 1c and the output terminal 5 of the transistor 1, and is a circuit for matching the output impedance of the transistor 1 and the impedance of the load.
The metal carrier 8 forms a ground plane of the power amplifier, and the semiconductor substrate 2, the input matching circuit 6, and the output matching circuit 7 are mounted thereon.
　ビア１１ａ，１１ｂ，１１ｃは多層回路基板３内に形成されており、ビア１１ａ，１１ｂ，１１ｃは多層回路基板３の最上層である回路基板３ｅに配置されているパッド１２ａ，１２ｂ，１２ｃと電気的に接続されている。
　接続端子１３はトランジスタ１のドレイン端子１ｃと多層回路基板３内に形成されているビア１１ｃとを電気的に接続している第１の接続端子である。
　接続端子１４は多層回路基板３内に形成されているビア１１ａを介して、トランジスタ１のゲート端子１ａと、多層回路基板３内に形成されている直列共振回路１９とを電気的に接続している第２の接続端子である。
　接続端子１５は多層回路基板３内に形成されているビア１１ｂを介して、トランジスタ１のソース端子１ｂと、定電位端であるグランドとを電気的に接続している第３の接続端子である。
　接続端子１３，１４，１５はフリップチップ実装によって実装されている。 The vias 11a, 11b, and 11c are formed in the multilayer circuit board 3, and the vias 11a, 11b, and 11c are electrically connected to the pads 12a, 12b, and 12c arranged on the circuit board 3e that is the uppermost layer of the multilayer circuit board 3. Connected.
The connection terminal 13 is a first connection terminal that electrically connects the drain terminal 1 c of the transistor 1 and the via 11 c formed in the multilayer circuit board 3.
The connection terminal 14 electrically connects the gate terminal 1a of the transistor 1 and the series resonant circuit 19 formed in the multilayer circuit board 3 via the via 11a formed in the multilayer circuit board 3. The second connection terminal.
The connection terminal 15 is a third connection terminal that electrically connects the source terminal 1 b of the transistor 1 and the ground, which is a constant potential terminal, via a via 11 b formed in the multilayer circuit board 3. .
The connection terminals 13, 14, and 15 are mounted by flip chip mounting.
　パターン構造１６は半導体基板２と多層回路基板３との間に形成されている構造体である。
　ボンディングワイヤ１７は入力整合回路６とパッド１２ａを電気的に接続している。これにより、入力整合回路６が、ボンディングワイヤ１７、パッド１２ａ、ビア１１ａ及び接続端子１４を介して、トランジスタ１のゲート端子１ａと電気的に接続されている。
　ボンディングワイヤ１８は出力整合回路７とパッド１２ｃを電気的に接続している。これにより、出力整合回路７が、ボンディングワイヤ１８、パッド１２ｃ、ビア１１ｃ及び接続端子１３を介して、トランジスタ１のドレイン端子１ｃと電気的に接続されている。 The pattern structure 16 is a structure formed between the semiconductor substrate 2 and the multilayer circuit board 3.
The bonding wire 17 electrically connects the input matching circuit 6 and the pad 12a. Thereby, the input matching circuit 6 is electrically connected to the gate terminal 1a of the transistor 1 through the bonding wire 17, the pad 12a, the via 11a, and the connection terminal 14.
The bonding wire 18 electrically connects the output matching circuit 7 and the pad 12c. Thereby, the output matching circuit 7 is electrically connected to the drain terminal 1c of the transistor 1 via the bonding wire 18, the pad 12c, the via 11c, and the connection terminal 13.
　高調波処理回路である直列共振回路１９はトランジスタ１のゲート端子１ａと、定電位端であるグランドとの間に接続され、トランジスタ１の動作周波数の２次の高調波又は３次以上の高調波で共振する第１の共振回路であり、直列共振回路１９は多層回路基板３に形成されている。
　直列共振回路１９は第１のインダクタであるインダクタ２０と、第１のキャパシタであるキャパシタ２１との直列回路で構成されている。 A series resonance circuit 19 which is a harmonic processing circuit is connected between the gate terminal 1a of the transistor 1 and the ground which is a constant potential end, and a second harmonic or a third or higher harmonic of the operating frequency of the transistor 1. The series resonance circuit 19 is formed on the multilayer circuit board 3.
The series resonance circuit 19 includes a series circuit of an inductor 20 that is a first inductor and a capacitor 21 that is a first capacitor.
　図４は半導体基板２及びトランジスタ１を上面から見た平面図である。
　図４において、半導体基板２は、トランジスタ１のゲート端子１ａ、ソース端子１ｂ及びドレイン端子１ｃと、ソース端子１ｂと定電位端である金属キャリア８を接続しているビア３１とを備えている。
　トランジスタ１のソース端子１ｂは、ビア３１によって定電位端と接続されて接地されている。 FIG. 4 is a plan view of the semiconductor substrate 2 and the transistor 1 as viewed from above.
In FIG. 4, the semiconductor substrate 2 includes a gate terminal 1a, a source terminal 1b, and a drain terminal 1c of the transistor 1, and a via 31 that connects the source terminal 1b and the metal carrier 8 that is a constant potential end.
The source terminal 1b of the transistor 1 is connected to the constant potential terminal via the via 31 and grounded.
　図５は多層回路基板３における第１層を形成している回路基板３ａを上面から見た平面図である。
　図５において、回路基板３ａは、ビア４１～４４と、直列共振回路１９を構成しているキャパシタ２１の一部を形成する電極パターン４５，４６とを備えている。 FIG. 5 is a plan view of the circuit board 3a forming the first layer in the multilayer circuit board 3, as viewed from above.
In FIG. 5, the circuit board 3 a includes vias 41 to 44 and electrode patterns 45 and 46 that form part of the capacitor 21 that constitutes the series resonance circuit 19.
　図６は多層回路基板３における第２層を形成している回路基板３ｂを上面から見た平面図である。
　図６において、回路基板３ｂは、ビア５１，５２と、直列共振回路１９を構成しているキャパシタ２１の一部を形成する電極パターン５３，５４とを備えている。 FIG. 6 is a plan view of the circuit board 3b forming the second layer in the multilayer circuit board 3, as viewed from above.
In FIG. 6, the circuit board 3 b includes vias 51 and 52 and electrode patterns 53 and 54 that form part of the capacitor 21 that constitutes the series resonant circuit 19.
　図７は多層回路基板３における第３層を形成している回路基板３ｃを上面から見た平面図である。
　図７において、回路基板３ｃは、ビア６１～６４と、直列共振回路１９を構成しているインダクタ２０の一部を形成する配線パターン６５，６６とを備えている。 FIG. 7 is a plan view of the circuit board 3c forming the third layer in the multilayer circuit board 3 as viewed from above.
In FIG. 7, the circuit board 3 c includes vias 61 to 64 and wiring patterns 65 and 66 forming part of the inductor 20 constituting the series resonant circuit 19.
　図８は多層回路基板３における第４層を形成している回路基板３ｄを上面から見た平面図である。
　図８において、回路基板３ｄは、ビア７１～７４と、直列共振回路１９を構成しているインダクタ２０の一部を形成する配線パターン７５，７６とを備えている。 FIG. 8 is a plan view of the circuit board 3d forming the fourth layer in the multilayer circuit board 3 as viewed from above.
In FIG. 8, the circuit board 3 d includes vias 71 to 74 and wiring patterns 75 and 76 that form part of the inductor 20 that constitutes the series resonant circuit 19.
　図９は多層回路基板３における第５層を形成している回路基板３ｅを上面から見た平面図である。
　図９において、回路基板３ｅは、ビア８１～８４と、直列共振回路１９を構成しているインダクタ２０の一部を形成する配線パターン８５，８６とを備えている。 FIG. 9 is a plan view of the circuit board 3e forming the fifth layer in the multilayer circuit board 3 as viewed from above.
In FIG. 9, the circuit board 3 e includes vias 81 to 84 and wiring patterns 85 and 86 forming part of the inductor 20 constituting the series resonant circuit 19.
　キャパシタ２１の一部を形成している電極パターン４５，４６は、ビア４２，４３及び接続端子１５を介して、定電位端と接続されることで接地されている。
　キャパシタ２１の一部を形成している電極パターン５３，５４は、ビア６２，６３を介して、インダクタ２０の一部を形成している配線パターン６５，６６と接続されている。
　インダクタ２０の一部を形成している配線パターン６５，６６は、ビア７２，７３を介して、インダクタ２０の一部を形成している配線パターン７５，７６と接続されている。
　インダクタ２０の一部を形成している配線パターン７５，７６は、ビア８２，８３を介して、インダクタ２０の一部を形成している配線パターン８５，８６と接続されている。
　配線パターン８５，８６は、ビア８４，７４，６４，５２，４４及び接続端子１４を介して、トランジスタ１のゲート端子１ａと接続されている。
　ビア８１，７１，６１，５１，４１は、接続端子１３を介して、トランジスタ１のドレイン端子１ｃと接続されている。 The electrode patterns 45 and 46 forming a part of the capacitor 21 are grounded by being connected to the constant potential terminal via the vias 42 and 43 and the connection terminal 15.
The electrode patterns 53 and 54 that form part of the capacitor 21 are connected to the wiring patterns 65 and 66 that form part of the inductor 20 via the vias 62 and 63.
The wiring patterns 65 and 66 that form part of the inductor 20 are connected to the wiring patterns 75 and 76 that form part of the inductor 20 via the vias 72 and 73.
The wiring patterns 75 and 76 that form part of the inductor 20 are connected to the wiring patterns 85 and 86 that form part of the inductor 20 via the vias 82 and 83.
The wiring patterns 85 and 86 are connected to the gate terminal 1 a of the transistor 1 through the vias 84, 74, 64, 52 and 44 and the connection terminal 14.
The vias 81, 71, 61, 51, 41 are connected to the drain terminal 1 c of the transistor 1 through the connection terminal 13.
　次に動作について説明する。
　キャパシタ２１の一部を形成している電極パターン５３，５４には、配線パターン６５，６６，７５，７６，８５，８６を介して電荷が蓄えられる。
　接地されている電極パターン４５，４６には、電極パターン５３，５４に蓄えられる電荷とは異符号の電荷が蓄えられる。
　電極パターン５３，５４と、電極パターン４５，４６との間には、回路基板３ｂを構成している誘電体が配置されているため、電極パターン４５，４６と、電極パターン５３，５４とによって平行平板容量が形成される。即ち、キャパシタ２１が形成される。 Next, the operation will be described.
Electric charges are stored in the electrode patterns 53 and 54 forming a part of the capacitor 21 via the wiring patterns 65, 66, 75, 76, 85 and 86.
In the grounded electrode patterns 45 and 46, charges having different signs from the charges stored in the electrode patterns 53 and 54 are stored.
Since the dielectric which comprises the circuit board 3b is arrange | positioned between the electrode patterns 53 and 54 and the electrode patterns 45 and 46, it is parallel by the electrode patterns 45 and 46 and the electrode patterns 53 and 54. A plate capacity is formed. That is, the capacitor 21 is formed.
　配線パターン６５，６６，７５，７６，８５，８６は、配線パターンの周囲に発生する磁場によってインダクタとみなすことができ、インダクタ２０が形成される。
　以上により、多層回路基板３内にインダクタ２０とキャパシタ２１が直列に接続されている直列共振回路１９が形成され、この直列共振回路１９がトランジスタ１のゲート端子１ａに対してシャントに接続される。 The wiring patterns 65, 66, 75, 76, 85, 86 can be regarded as inductors by the magnetic field generated around the wiring pattern, and the inductor 20 is formed.
As a result, the series resonance circuit 19 in which the inductor 20 and the capacitor 21 are connected in series is formed in the multilayer circuit board 3, and the series resonance circuit 19 is connected to the gate terminal 1 a of the transistor 1 in a shunt.
　この直列共振回路１９がトランジスタ１の動作周波数である基本周波数の２次の高調波又は３次以上の高調波で直列共振するように、インダクタ２０とキャパシタ２１の定数を選ぶことで、トランジスタ１のゲート端子１ａにおいて、２次の高調波又は３次以上の高調波に対するインピーダンスが短絡になる。 The constants of the inductor 20 and the capacitor 21 are selected so that the series resonance circuit 19 performs series resonance at the second harmonic of the fundamental frequency that is the operating frequency of the transistor 1 or the third harmonic or higher. In the gate terminal 1a, the impedance with respect to the second harmonic or the third harmonic or higher is short-circuited.
　トランジスタ１のゲート端子１ａにおいて、２次の高調波又は３次以上の高調波に対するインピーダンスが短絡になることで、電力増幅器が高効率に動作する。
　ここで、直列共振回路１９とトランジスタ１のゲート端子１ａとをワイヤボンディングや半導体基板上の配線パターンで接続する方法を用いる場合、直列共振回路１９とトランジスタ１のゲート端子１ａとの間に余剰なインダクタンス成分が形成されるために、直列共振回路１９を形成するインダクタの最小値が、このワイヤボンディングや半導体基板上の配線パターンによって制限される。 In the gate terminal 1a of the transistor 1, the impedance with respect to the second harmonic or the third or higher harmonic is short-circuited, so that the power amplifier operates with high efficiency.
Here, when a method of connecting the series resonant circuit 19 and the gate terminal 1a of the transistor 1 by wire bonding or a wiring pattern on a semiconductor substrate is used, there is an excess between the series resonant circuit 19 and the gate terminal 1a of the transistor 1. Since the inductance component is formed, the minimum value of the inductor forming the series resonance circuit 19 is limited by the wire bonding and the wiring pattern on the semiconductor substrate.
　この実施の形態１では、半導体基板２と層をなす位置に配置されている多層回路基板３が複数の回路基板３ａ～３ｅで形成され、複数の回路基板３ａ～３ｅが図５～図９のように構成されているので、ワイヤボンディングや半導体基板上の配線パターンを用いずに、直列共振回路１９とトランジスタ１のゲート端子１ａとが接続されている。
　このため、ワイヤボンディングや半導体基板上の配線パターンで接続する方法を用いる場合より、小さいインダクタ２０を形成することができ、より高い周波数で直列共振する直列共振回路１９を形成することができる。
　半導体基板２と層をなす位置に多層回路基板３が配置されているので、半導体基板２の面積の増加を抑えることができる。このため、低コスト化を実現することができる。 In the first embodiment, the multilayer circuit board 3 arranged at a position that forms a layer with the semiconductor substrate 2 is formed of a plurality of circuit boards 3a to 3e, and the plurality of circuit boards 3a to 3e are formed as shown in FIGS. Thus, the series resonant circuit 19 and the gate terminal 1a of the transistor 1 are connected without using wire bonding or a wiring pattern on the semiconductor substrate.
For this reason, it is possible to form a smaller inductor 20 and to form a series resonant circuit 19 that resonates in series at a higher frequency than when wire bonding or a connection method using a wiring pattern on a semiconductor substrate is used.
Since the multilayer circuit board 3 is disposed at a position that forms a layer with the semiconductor substrate 2, an increase in the area of the semiconductor substrate 2 can be suppressed. For this reason, cost reduction can be realized.
　以上で明らかなように、この実施の形態１によれば、トランジスタ１のゲート端子１ａと定電位端との間に接続され、トランジスタ１の動作周波数の２次の高調波又は３次以上の高調波で共振する直列共振回路１９が多層回路基板３に形成されているように構成したので、スパイラルインダクタとＭＩＭキャパシタからなる高調波処理回路を半導体基板２上に形成することなく、高調波に対するインピーダンスのばらつきを回避することができる小型で低コストな電力増幅器が得られる効果を奏する。 As is apparent from the above, according to the first embodiment, the second harmonic or the third or higher harmonic of the operating frequency of the transistor 1 is connected between the gate terminal 1a of the transistor 1 and the constant potential terminal. Since the series resonant circuit 19 that resonates with a wave is formed on the multilayer circuit board 3, the harmonic processing circuit composed of the spiral inductor and the MIM capacitor is not formed on the semiconductor substrate 2. There is an effect that a small and low-cost power amplifier capable of avoiding the variation of the above can be obtained.
　この実施の形態１では、１個のトランジスタ１に対して、直列共振回路１９が形成されている多層回路基板３を適用する例を示したが、複数のトランジスタ１に対して、直列共振回路１９が形成されている多層回路基板３を適用するようにしてもよい。
　また、この実施の形態１では、トランジスタ１がＦＥＴ型の半導体である例を示したが、これに限るものではなく、トランジスタ１がＦＥＴ以外の半導体であってもよい。
　この実施の形態１では、多層回路基板３が５層の回路基板３ａ～３ｅで形成されている例を示したが、単層の１層回路基板であってもよいし、２～４層又は６層以上の回路基板で形成されている多層回路基板３であってもよい。 In the first embodiment, the example in which the multilayer circuit board 3 on which the series resonance circuit 19 is formed is applied to one transistor 1 is shown. However, the series resonance circuit 19 is applied to a plurality of transistors 1. A multilayer circuit board 3 on which is formed may be applied.
In the first embodiment, the transistor 1 is an FET type semiconductor. However, the present invention is not limited to this, and the transistor 1 may be a semiconductor other than an FET.
In the first embodiment, the multilayer circuit board 3 is formed of five layers of circuit boards 3a to 3e. However, the multilayer circuit board 3 may be a single-layer single-layer circuit board, or two to four layers or A multilayer circuit board 3 formed of six or more circuit boards may be used.
　また、この実施の形態１では、多層回路基板３を形成している回路基板３ａと回路基板３ｂの間に、キャパシタ２１を形成する電極パターン４５，４６，５３，５４を配置しているものを示したが、回路基板３ａと回路基板３ｂの間以外に、キャパシタ２１を形成する電極パターン４５，４６，５３，５４を配置するようにしてもよい。
　この実施の形態１では、多層回路基板３を形成している回路基板３ｃ～３ｅに、インダクタ２０を形成する配線パターン６５，６６，７５，７６，８５，８６を配置しているものを示したが、回路基板３ｃ～３ｅ以外の回路基板に配線パターン６５，６６，７５，７６，８５，８６を配置するようにしてもよい。 In the first embodiment, the electrode patterns 45, 46, 53, and 54 that form the capacitor 21 are arranged between the circuit board 3a that forms the multilayer circuit board 3 and the circuit board 3b. Although shown, the electrode patterns 45, 46, 53, and 54 forming the capacitor 21 may be disposed in addition to the area between the circuit board 3a and the circuit board 3b.
In the first embodiment, the circuit boards 3c to 3e forming the multilayer circuit board 3 are arranged with the wiring patterns 65, 66, 75, 76, 85, 86 forming the inductor 20 shown therein. However, the wiring patterns 65, 66, 75, 76, 85, 86 may be arranged on circuit boards other than the circuit boards 3c to 3e.
実施の形態２．
　上記実施の形態１では、直列共振回路１９を構成しているインダクタ２０とキャパシタ２１の全てが多層回路基板３内に形成されているものを示したが、直列共振回路１９を構成しているインダクタ２０とキャパシタ２１のうち、キャパシタ２１が半導体基板２内に形成されているものであってもよい。 Embodiment 2. FIG.
In the first embodiment, the inductor 20 and the capacitor 21 constituting the series resonant circuit 19 are all formed in the multilayer circuit board 3. However, the inductor constituting the series resonant circuit 19 is shown. Of the capacitors 20 and 21, the capacitor 21 may be formed in the semiconductor substrate 2.
　図１０はこの発明の実施の形態２による電力増幅器を示す断面図であり、図１０において、図３と同一符号は同一または相当部分を示すので説明を省略する。
　多層回路基板３は複数の回路基板３ｆ～３ｈから形成されている基板であり、多層回路基板３は半導体基板２と層をなす位置に配置され、その半導体基板２と電気的に接続されている。
　接続端子１５ａは多層回路基板３と図１１に示すＭＩＭキャパシタ９１を接続する端子である。
　接続端子１５ｂは多層回路基板３を形成している回路基板３ｆの裏面とトランジスタ１のソース端子１ｂとを接続する端子である。
　接続端子１５ａ，１５ｂはフリップチップ実装によって実装されている。 10 is a sectional view showing a power amplifier according to Embodiment 2 of the present invention. In FIG. 10, the same reference numerals as those in FIG.
The multilayer circuit board 3 is a board formed of a plurality of circuit boards 3f to 3h. The multilayer circuit board 3 is disposed at a position that forms a layer with the semiconductor substrate 2 and is electrically connected to the semiconductor substrate 2. .
The connection terminal 15a is a terminal for connecting the multilayer circuit board 3 and the MIM capacitor 91 shown in FIG.
The connection terminal 15 b is a terminal for connecting the back surface of the circuit board 3 f forming the multilayer circuit board 3 and the source terminal 1 b of the transistor 1.
The connection terminals 15a and 15b are mounted by flip chip mounting.
　図１１は半導体基板２及びトランジスタ１を上面から見た平面図であり、図１１において、図４と同一符号は同一または相当部分を示している。
　半導体基板２は、トランジスタ１のゲート端子１ａ、ソース端子１ｂ及びドレイン端子１ｃと、ソース端子１ｂと定電位端である金属キャリア８を接続しているビア３１と、ＭＩＭキャパシタ９１とを備えている。
　トランジスタ１のソース端子１ｂは、ビア３１によって定電位端と接続されて接地されている。
　ＭＩＭキャパシタ９１の電極の一端は、ソース端子１ｂと接続されて接地されている。 11 is a plan view of the semiconductor substrate 2 and the transistor 1 as viewed from above. In FIG. 11, the same reference numerals as those in FIG. 4 denote the same or corresponding parts.
The semiconductor substrate 2 includes a gate terminal 1 a, a source terminal 1 b and a drain terminal 1 c of the transistor 1, a via 31 connecting the source terminal 1 b and the metal carrier 8 which is a constant potential end, and an MIM capacitor 91. .
The source terminal 1b of the transistor 1 is connected to the constant potential terminal via the via 31 and grounded.
One end of the electrode of the MIM capacitor 91 is connected to the source terminal 1b and grounded.
　図１２は多層回路基板３における第１層を形成している回路基板３ｆを上面から見た平面図である。
　図１２において、回路基板３ｆは、ビア１０１～１０４と、直列共振回路１９を構成しているインダクタ２０の一部を形成する配線パターン１０５，１０６とを備えている。 FIG. 12 is a plan view of the circuit board 3f forming the first layer in the multilayer circuit board 3 as viewed from above.
In FIG. 12, the circuit board 3 f includes vias 101 to 104 and wiring patterns 105 and 106 that form part of the inductor 20 that constitutes the series resonant circuit 19.
　図１３は多層回路基板３における第１層を形成している回路基板３ｆの裏面を見た平面図である。
　図１３において、回路基板３ｆの裏面は、ビア１０１～１０４と、配線パターン１０７とを備えている。 FIG. 13 is a plan view of the back surface of the circuit board 3 f forming the first layer in the multilayer circuit board 3.
In FIG. 13, the back surface of the circuit board 3 f includes vias 101 to 104 and a wiring pattern 107.
　図１４は多層回路基板３における第２層を形成している回路基板３ｇを上面から見た平面図である。
　図１４において、回路基板３ｇは、ビア１１１～１１４と、直列共振回路１９を構成しているインダクタ２０の一部を形成する配線パターン１１５，１１６とを備えている。 FIG. 14 is a plan view of the circuit board 3g forming the second layer in the multilayer circuit board 3 as viewed from above.
In FIG. 14, the circuit board 3 g includes vias 111 to 114 and wiring patterns 115 and 116 that form part of the inductor 20 that constitutes the series resonant circuit 19.
　図１５は多層回路基板３における第３層を形成している回路基板３ｈを上面から見た平面図である。
　図１５において、回路基板３ｈは、ビア１２１～１２４と、直列共振回路１９を構成しているインダクタ２０の一部を形成する配線パターン１２５，１２６とを備えている。 FIG. 15 is a plan view of the circuit board 3h forming the third layer in the multilayer circuit board 3 as viewed from above.
In FIG. 15, the circuit board 3 h includes vias 121 to 124 and wiring patterns 125 and 126 forming part of the inductor 20 constituting the series resonant circuit 19.
　回路基板３ｆの裏面に形成されている配線パターン１０７は、接続端子１５ｂを介して、トランジスタ１のソース端子１ｂと接続されて接地されており、多層回路基板３の接地面を形成している。
　半導体基板２に形成されているＭＩＭキャパシタ９１は、直列共振回路１９を構成しているキャパシタ２１を形成している。
　直列共振回路１９を構成しているインダクタ２０は、配線パターン１０５，１０６，１１５，１１６，１２５，１２６がビア１１２，１１３，１２２，１２３を介して接続されることにより形成されている。 The wiring pattern 107 formed on the back surface of the circuit board 3f is connected to the source terminal 1b of the transistor 1 via the connection terminal 15b and grounded, thereby forming the ground surface of the multilayer circuit board 3.
The MIM capacitor 91 formed on the semiconductor substrate 2 forms the capacitor 21 constituting the series resonance circuit 19.
The inductor 20 constituting the series resonance circuit 19 is formed by connecting the wiring patterns 105, 106, 115, 116, 125, 126 via the vias 112, 113, 122, 123.
　インダクタ２０がビア１０２，１０３及び接続端子１５ａを介してＭＩＭキャパシタ９１の電極の他端と接続されることで、直列共振回路１９が形成されている。
　また、インダクタ２０がビア１２４，１１４，１０４及び接続端子１４を介してトランジスタ１のゲート端子１ａと接続されることで、直列共振回路１９がトランジスタ１のゲート端子１ａに対してシャントに接続されている。 The inductor 20 is connected to the other end of the electrode of the MIM capacitor 91 through the vias 102 and 103 and the connection terminal 15a, whereby the series resonance circuit 19 is formed.
Further, the inductor 20 is connected to the gate terminal 1a of the transistor 1 through the vias 124, 114, 104 and the connection terminal 14, so that the series resonant circuit 19 is connected to the gate terminal 1a of the transistor 1 in a shunt. Yes.
　この直列共振回路１９がトランジスタ１の動作周波数である基本周波数の２次の高調波又は３次以上の高調波で直列共振するように、インダクタ２０とキャパシタ２１の定数を選ぶことで、トランジスタ１のゲート端子１ａにおいて、２次の高調波又は３次以上の高調波に対するインピーダンスが短絡になる。
　トランジスタ１のゲート端子１ａにおいて、２次の高調波又は３次以上の高調波に対するインピーダンスが短絡になることで、キャパシタ２１が半導体基板２内に形成される場合でも、上記実施の形態１と同様に、電力増幅器が高効率に動作する。 The constants of the inductor 20 and the capacitor 21 are selected so that the series resonance circuit 19 performs series resonance at the second harmonic of the fundamental frequency that is the operating frequency of the transistor 1 or the third harmonic or higher. In the gate terminal 1a, the impedance with respect to the second harmonic or the third harmonic or higher is short-circuited.
Even when the capacitor 21 is formed in the semiconductor substrate 2 by short-circuiting the impedance to the second harmonic or the third harmonic or higher at the gate terminal 1a of the transistor 1, the same as in the first embodiment. In addition, the power amplifier operates with high efficiency.
　この実施の形態２では、１個のトランジスタ１に対して、直列共振回路１９が形成されている多層回路基板３を適用する例を示したが、複数のトランジスタ１に対して、直列共振回路１９が形成されている多層回路基板３を適用するようにしてもよい。
　また、この実施の形態２では、トランジスタ１がＦＥＴ型の半導体である例を示したが、これに限るものではなく、トランジスタ１がＦＥＴ以外の半導体であってもよい。
　この実施の形態２では、多層回路基板３が３層の回路基板３ｆ～３ｈで形成されている例を示したが、単層の１層回路基板でもよいし、２層又は４層以上の回路基板で形成されている多層回路基板３であってもよい。 In the second embodiment, the example in which the multilayer circuit board 3 in which the series resonant circuit 19 is formed is applied to one transistor 1 is shown, but the series resonant circuit 19 is applied to a plurality of transistors 1. A multilayer circuit board 3 on which is formed may be applied.
In the second embodiment, the transistor 1 is an FET type semiconductor. However, the present invention is not limited to this, and the transistor 1 may be a semiconductor other than an FET.
In the second embodiment, an example in which the multilayer circuit board 3 is formed of the three-layer circuit boards 3f to 3h is shown. However, a single-layer single-layer circuit board may be used, and a circuit having two or more layers may be used. It may be a multilayer circuit board 3 formed of a substrate.
実施の形態３．
　上記実施の形態２では、多層回路基板３が３層の回路基板３ｆ～３ｈで形成されている例を示したが、単層の１層回路基板で形成されているものであってもよい。
　図１６はこの発明の実施の形態３による電力増幅器を示す断面図であり、図１６において、図１０と同一符号は同一または相当部分を示すので説明を省略する。
　多層回路基板３は回路基板３ｉから形成されている基板であり、多層回路基板３は半導体基板２と層をなす位置に配置され、その半導体基板２と電気的に接続されている。 Embodiment 3 FIG.
In the second embodiment, the example in which the multilayer circuit board 3 is formed of the three-layer circuit boards 3f to 3h has been described. However, the multilayer circuit board 3 may be formed of a single-layer one-layer circuit board.
16 is a sectional view showing a power amplifier according to Embodiment 3 of the present invention. In FIG. 16, the same reference numerals as those in FIG.
The multilayer circuit board 3 is a board formed from the circuit board 3 i, and the multilayer circuit board 3 is disposed at a position forming a layer with the semiconductor substrate 2 and is electrically connected to the semiconductor substrate 2.
　図１７は多層回路基板３における第１層を形成している回路基板３ｉの裏面を見た平面図である。
　図１７において、回路基板３ｉの裏面は、ビア１３１～１３４と、配線パターン１３５ａ，１３５ｂとを備えている。 FIG. 17 is a plan view of the back surface of the circuit board 3 i forming the first layer in the multilayer circuit board 3.
In FIG. 17, the back surface of the circuit board 3i includes vias 131 to 134 and wiring patterns 135a and 135b.
　図１８は多層回路基板３における第１層を形成している回路基板３ｉを上面から見た平面図である。
　図１８において、回路基板３ｉは、ビア１３１～１３４と、配線パターン１３６とを備えている。
　配線パターン１３６は、ビア１３３，１３４と接続端子１５ｂを介してトランジスタ１のソース端子１ｂと接続されることで接地となり、回路基板３ｉの接地面を形成している。 FIG. 18 is a plan view of the circuit board 3 i forming the first layer in the multilayer circuit board 3 as viewed from above.
In FIG. 18, the circuit board 3 i includes vias 131 to 134 and a wiring pattern 136.
The wiring pattern 136 is grounded by being connected to the source terminal 1b of the transistor 1 via the vias 133 and 134 and the connection terminal 15b, and forms a ground plane of the circuit board 3i.
　直列共振回路１９を構成しているインダクタ２０は、配線パターン１３５ａ，１３５ｂにより形成されている。
　また、直列共振回路１９を構成しているキャパシタ２１は、上記実施の形態２と同様に、半導体基板２に形成されているＭＩＭキャパシタ９１が担っている。ＭＩＭキャパシタ９１の電極の一端は、トランジスタ１のソース端子１ｂと接続されて接地されている。 The inductor 20 constituting the series resonance circuit 19 is formed by wiring patterns 135a and 135b.
The capacitor 21 constituting the series resonance circuit 19 is carried by the MIM capacitor 91 formed on the semiconductor substrate 2 as in the second embodiment. One end of the electrode of the MIM capacitor 91 is connected to the source terminal 1b of the transistor 1 and grounded.
　インダクタ２０が接続端子１５ａを介してキャパシタ２１と接続されることで、直列共振回路１９が形成されている。
　また、インダクタ２０がビア１３２及び接続端子１４を介してトランジスタ１のゲート端子１ａと接続されることで、直列共振回路１９がトランジスタ１のゲート端子１ａに対してシャントに接続されている。 The series resonance circuit 19 is formed by connecting the inductor 20 to the capacitor 21 via the connection terminal 15a.
Further, the inductor 20 is connected to the gate terminal 1 a of the transistor 1 through the via 132 and the connection terminal 14, so that the series resonance circuit 19 is connected to the gate terminal 1 a of the transistor 1 in a shunt.
　入力整合回路６とトランジスタ１のゲート端子１ａは、ボンディングワイヤ１７、パッド１２ａ、ビア１３２を介して接続されている。
　出力整合回路７とトランジスタ１のドレイン端子１ｃは、ボンディングワイヤ１８、パッド１２ｃ、ビア１３１を介して接続されている。 The input matching circuit 6 and the gate terminal 1a of the transistor 1 are connected through a bonding wire 17, a pad 12a, and a via 132.
The output matching circuit 7 and the drain terminal 1c of the transistor 1 are connected via a bonding wire 18, a pad 12c, and a via 131.
　この直列共振回路１９がトランジスタ１の動作周波数である基本周波数の２次の高調波又は３次以上の高調波で直列共振するように、インダクタ２０とキャパシタ２１の定数を選ぶことで、トランジスタ１のゲート端子１ａにおいて、２次の高調波又は３次以上の高調波に対するインピーダンスが短絡になる。
　トランジスタ１のゲート端子１ａにおいて、２次の高調波又は３次以上の高調波に対するインピーダンスが短絡になることで、キャパシタ２１が半導体基板２内に形成される場合でも、上記実施の形態２と同様に、電力増幅器が高効率に動作する。
　この実施の形態３では、多層回路基板３間のビアを介することなく、インダクタ２０が形成されるため、ビアの製造ばらつきによるインダクタンスのばらつきを軽減することができ、生産の歩留まりを向上させることができる。 The constants of the inductor 20 and the capacitor 21 are selected so that the series resonance circuit 19 performs series resonance at the second harmonic of the fundamental frequency that is the operating frequency of the transistor 1 or the third harmonic or higher. In the gate terminal 1a, the impedance with respect to the second harmonic or the third harmonic or higher is short-circuited.
Even when the capacitor 21 is formed in the semiconductor substrate 2 by short-circuiting the impedance to the second harmonic or the third harmonic or higher at the gate terminal 1a of the transistor 1, the same as in the second embodiment. In addition, the power amplifier operates with high efficiency.
In the third embodiment, since the inductor 20 is formed without vias between the multilayer circuit boards 3, the variation in inductance due to the manufacturing variation of vias can be reduced, and the production yield can be improved. it can.
実施の形態４．
　上記実施の形態１では、直列共振回路１９を構成しているインダクタ２０とキャパシタ２１の全てが多層回路基板３内に形成されているものを示したが、直列共振回路１９を構成しているインダクタ２０とキャパシタ２１のうち、インダクタ２０が半導体基板２内に形成されているものであってもよい。 Embodiment 4 FIG.
In the first embodiment, the inductor 20 and the capacitor 21 constituting the series resonant circuit 19 are all formed in the multilayer circuit board 3. However, the inductor constituting the series resonant circuit 19 is shown. Among the capacitors 20 and 21, the inductor 20 may be formed in the semiconductor substrate 2.
　図１９はこの発明の実施の形態４による電力増幅器を示す断面図であり、図１９において、図３と同一符号は同一または相当部分を示すので説明を省略する。
　多層回路基板３は複数の回路基板３ｊ，３ｋから形成されている基板であり、多層回路基板３は半導体基板２と層をなす位置に配置され、その半導体基板２と電気的に接続されている。
　接続端子１５ｃ，１５ｄは多層回路基板３と半導体基板２を接続する端子であり、フリップチップ実装によって実装されている。 19 is a sectional view showing a power amplifier according to Embodiment 4 of the present invention. In FIG. 19, the same reference numerals as those in FIG.
The multilayer circuit board 3 is a board formed of a plurality of circuit boards 3j and 3k. The multilayer circuit board 3 is disposed at a position that forms a layer with the semiconductor substrate 2 and is electrically connected to the semiconductor substrate 2. .
The connection terminals 15c and 15d are terminals for connecting the multilayer circuit board 3 and the semiconductor substrate 2, and are mounted by flip chip mounting.
　図２０は半導体基板２及びトランジスタ１を上面から見た平面図であり、図２０において、図１１と同一符号は同一または相当部分を示している。
　半導体基板２は、トランジスタ１のゲート端子１ａ、ソース端子１ｂ及びドレイン端子１ｃと、ソース端子１ｂと定電位端である金属キャリア８を接続しているビア３１と、スパイラルインダクタ１４１とを備えている。
　トランジスタ１のソース端子１ｂは、ビア３１によって定電位端と接続されて接地されている。
　また、トランジスタ１のゲート端子１ａは、スパイラルインダクタ１４１と接続されている。 20 is a plan view of the semiconductor substrate 2 and the transistor 1 as viewed from above. In FIG. 20, the same reference numerals as those in FIG. 11 denote the same or corresponding parts.
The semiconductor substrate 2 includes a gate terminal 1a, a source terminal 1b, a drain terminal 1c of the transistor 1, a via 31 that connects the source terminal 1b and the metal carrier 8 that is a constant potential end, and a spiral inductor 141. .
The source terminal 1b of the transistor 1 is connected to the constant potential terminal via the via 31 and grounded.
The gate terminal 1 a of the transistor 1 is connected to the spiral inductor 141.
　図２１は多層回路基板３における第１層を形成している回路基板３ｊを上面から見た平面図である。
　図２１において、回路基板３ｊは、ビア１５１～１５６と、直列共振回路１９を構成しているキャパシタ２１の一部を形成する電極パターン１５７，１５８とを備えている。 FIG. 21 is a plan view of the circuit board 3j forming the first layer in the multilayer circuit board 3 as viewed from above.
In FIG. 21, the circuit board 3 j includes vias 151 to 156 and electrode patterns 157 and 158 that form part of the capacitor 21 constituting the series resonant circuit 19.
　図２２は多層回路基板３における第２層を形成している回路基板３ｋを上面から見た平面図である。
　図２２において、回路基板３ｋは、ビア１６１～１６４と、直列共振回路１９を構成しているキャパシタ２１の一部を形成する電極パターン１６５，１６６とを備えている。 FIG. 22 is a plan view of the circuit board 3k forming the second layer in the multilayer circuit board 3 as viewed from above.
In FIG. 22, the circuit board 3 k includes vias 161 to 164 and electrode patterns 165 and 166 that form part of the capacitor 21 that constitutes the series resonance circuit 19.
　電極パターン１５７，１５８は、ビア１５２，１５３と接続端子１５ｄを介してトランジスタ１のソース端子１ｂと接続されることで接地となっている。
　電極パターン１６５，１６６は、ビア１６２，１６３，１５４，１５５と接続端子１５ｃを介してスパイラルインダクタ１４１と接続されている。 The electrode patterns 157 and 158 are grounded by being connected to the source terminal 1b of the transistor 1 via the vias 152 and 153 and the connection terminal 15d.
The electrode patterns 165 and 166 are connected to the spiral inductor 141 through the vias 162, 163, 154, and 155 and the connection terminal 15c.
　次に動作について説明する。
　キャパシタ２１の一部を形成している電極パターン１６５，１６６には、スパイラルインダクタ１４１、接続端子１５ｃ及びビア１５４，１５５，１６２，１６３を介して電荷が蓄えられる。
　接地されている電極パターン１５７，１５８には、電極パターン１６５，１６６に蓄えられる電荷とは異符号の電荷が蓄えられる。
　電極パターン１６５，１６６と、電極パターン１５７，１５８との間には、回路基板３ｋを構成している誘電体が配置されているため、電極パターン１６５，１６６と、電極パターン１５７，１５８とによって平行平板容量が形成される。即ち、キャパシタ２１が形成される。
　電極パターン１６５，１６６がビア１６２，１６３，１５４，１５５と接続端子１５ｃを介してスパイラルインダクタ１４１と接続されることで、直列共振回路１９が形成されている。 Next, the operation will be described.
Electric charges are stored in the electrode patterns 165 and 166 forming a part of the capacitor 21 through the spiral inductor 141, the connection terminal 15 c and the vias 154, 155, 162 and 163.
The grounded electrode patterns 157 and 158 store charges having a sign different from the charges stored in the electrode patterns 165 and 166.
Since the dielectric constituting the circuit board 3k is disposed between the electrode patterns 165 and 166 and the electrode patterns 157 and 158, the electrode patterns 165 and 166 and the electrode patterns 157 and 158 are parallel to each other. A plate capacity is formed. That is, the capacitor 21 is formed.
The electrode patterns 165 and 166 are connected to the spiral inductor 141 through the vias 162, 163, 154, and 155 and the connection terminal 15c, whereby the series resonance circuit 19 is formed.
　この直列共振回路１９がトランジスタ１の動作周波数である基本周波数の２次の高調波又は３次以上の高調波で直列共振するように、インダクタ２０とキャパシタ２１の定数を選ぶことで、トランジスタ１のゲート端子１ａにおいて、２次の高調波又は３次以上の高調波に対するインピーダンスが短絡になる。
　トランジスタ１のゲート端子１ａにおいて、２次の高調波又は３次以上の高調波に対するインピーダンスが短絡になることで、インダクタ２０が半導体基板２内に形成される場合でも、上記実施の形態１と同様に、電力増幅器が高効率に動作する。 The constants of the inductor 20 and the capacitor 21 are selected so that the series resonance circuit 19 performs series resonance at the second harmonic of the fundamental frequency that is the operating frequency of the transistor 1 or the third harmonic or higher. In the gate terminal 1a, the impedance with respect to the second harmonic or the third harmonic or higher is short-circuited.
Even when the inductor 20 is formed in the semiconductor substrate 2 by short-circuiting the impedance with respect to the second harmonic or the third harmonic or higher at the gate terminal 1a of the transistor 1, the same as in the first embodiment. In addition, the power amplifier operates with high efficiency.
実施の形態５．
　上記実施の形態１～４では、トランジスタ１の動作周波数の２次の高調波又は３次以上の高調波で共振する直列共振回路１９が多層回路基板３に形成されているものを示したが、一端がトランジスタ１のゲート端子１ａと接続され、トランジスタ１の動作周波数の２次の高調波又は３次以上の高調波で４分の１波長の線路長を有するオープンスタブが多層回路基板３に形成されているようにしてもよい。 Embodiment 5 FIG.
In the first to fourth embodiments, the series resonant circuit 19 that resonates at the second harmonic or the third harmonic or higher of the operating frequency of the transistor 1 is formed on the multilayer circuit board 3. One end is connected to the gate terminal 1a of the transistor 1, and an open stub having a quarter wavelength line length is formed on the multilayer circuit board 3 at the second harmonic or third harmonic of the operating frequency of the transistor 1 You may be made to do.
　図２３はこの発明の実施の形態５による電力増幅器を示す回路図であり、図２３において、図２と同一符号は同一または相当部分を示すので説明を省略する。
　高調波処理回路１７１は一端がトランジスタ１のゲート端子１ａと接続されているオープンスタブ１７２から構成されている。
　オープンスタブ１７２はトランジスタ１の動作周波数の２次の高調波又は３次以上の高調波でλ／４（４分の１波長）の線路長を有する第１のオープンスタブであり、オープンスタブ１７２は多層回路基板３に形成されている。 FIG. 23 is a circuit diagram showing a power amplifier according to the fifth embodiment of the present invention. In FIG. 23, the same reference numerals as those in FIG.
The harmonic processing circuit 171 includes an open stub 172 having one end connected to the gate terminal 1 a of the transistor 1.
The open stub 172 is a first open stub having a line length of λ / 4 (quarter wavelength) at the second harmonic or the third harmonic or higher of the operating frequency of the transistor 1, and the open stub 172 is It is formed on the multilayer circuit board 3.
　図２４はこの発明の実施の形態５による電力増幅器を示す断面図であり、図２４において、図３と同一符号は同一または相当部分を示すので説明を省略する。
　多層回路基板３は複数の回路基板３ｍ，３ｎ，３ｐから形成されている基板であり、多層回路基板３は半導体基板２と層をなす位置に配置され、その半導体基板２と電気的に接続されている。
　接続端子１５ｅは多層回路基板３と半導体基板２を接続する端子であり、フリップチップ実装によって実装されている。 24 is a cross-sectional view showing a power amplifier according to Embodiment 5 of the present invention. In FIG. 24, the same reference numerals as those in FIG.
The multilayer circuit board 3 is a board formed from a plurality of circuit boards 3m, 3n, and 3p. The multilayer circuit board 3 is disposed at a position that forms a layer with the semiconductor substrate 2, and is electrically connected to the semiconductor substrate 2. ing.
The connection terminal 15e is a terminal for connecting the multilayer circuit board 3 and the semiconductor substrate 2, and is mounted by flip chip mounting.
　図２５は多層回路基板３における第１層を形成している回路基板３ｍを上面から見た平面図である。
　図２５において、回路基板３ｍは、ビア１８１，１８２と、配線パターン１８３，１８４とを備えている。 FIG. 25 is a plan view of the circuit board 3m forming the first layer in the multilayer circuit board 3 as viewed from above.
In FIG. 25, the circuit board 3 m includes vias 181 and 182 and wiring patterns 183 and 184.
　図２６は多層回路基板３における第１層を形成している回路基板３ｍの裏面を見た平面図である。
　図２６において、回路基板３ｍの裏面は、ビア１８１，１８２と、配線パターン１８５とを備えている。 FIG. 26 is a plan view of the back surface of the circuit board 3m forming the first layer in the multilayer circuit board 3. FIG.
In FIG. 26, the back surface of the circuit board 3m includes vias 181 and 182 and a wiring pattern 185.
　図２７は多層回路基板３における第２層を形成している回路基板３ｎを上面から見た平面図である。
　図２７において、回路基板３ｎは、ビア１９１～１９４と、高調波処理回路１７１を構成するオープンスタブ１７２の一部を形成する配線パターン１９５，１９６とを備えている。 FIG. 27 is a plan view of the circuit board 3n forming the second layer in the multilayer circuit board 3 as viewed from above.
In FIG. 27, the circuit board 3n includes vias 191 to 194 and wiring patterns 195 and 196 that form part of an open stub 172 that constitutes the harmonic processing circuit 171.
　図２８は多層回路基板３における第３層を形成している回路基板３ｐを上面から見た平面図である。
　図２８において、回路基板３ｐは、ビア２０１～２０４と、高調波処理回路１７１を構成するオープンスタブ１７２の一部を形成する配線パターン２０５，２０６とを備えている。 FIG. 28 is a plan view of the circuit board 3p forming the third layer in the multilayer circuit board 3 as viewed from above.
In FIG. 28, the circuit board 3p includes vias 201 to 204 and wiring patterns 205 and 206 forming part of an open stub 172 constituting the harmonic processing circuit 171.
　次に動作について説明する。
　配線パターン１８５は、接続端子１５ｅを介してトランジスタ１のソース端子１ｂと接続されることで接地となり、多層回路基板３の接地面を形成している。
　高調波処理回路１７１を構成するオープンスタブ１７２は、配線パターン１８３，１８４，１９５，１９６，２０５，２０６が、ビア１９２，１９３，２０２，２０３を介して接続されることで形成されている。
　オープンスタブ１７２は、ビア１８２，１９４，２０４と接続端子１４を介してトランジスタ１のゲート端子１ａと接続されている。 Next, the operation will be described.
The wiring pattern 185 is grounded by being connected to the source terminal 1b of the transistor 1 via the connection terminal 15e, and forms a ground plane of the multilayer circuit board 3.
The open stub 172 constituting the harmonic processing circuit 171 is formed by connecting wiring patterns 183, 184, 195, 196, 205, 206 via vias 192, 193, 202, 203.
The open stub 172 is connected to the gate terminal 1 a of the transistor 1 through the vias 182, 194 and 204 and the connection terminal 14.
　オープンスタブ１７２は、トランジスタ１の動作周波数の２次の高調波又は３次以上の高調波でλ／４の線路長を有するため、トランジスタ１のゲート端子１ａにおいて、２次の高調波又は３次以上の高調波に対するインピーダンスが短絡になる。
　トランジスタ１のゲート端子１ａにおいて、２次の高調波又は３次以上の高調波に対するインピーダンスが短絡になることで、上記実施の形態１～４と同様に、電力増幅器が高効率に動作する。 Since the open stub 172 has a line length of λ / 4 at the second harmonic or the third or higher harmonic of the operating frequency of the transistor 1, the second harmonic or the third harmonic at the gate terminal 1 a of the transistor 1. The impedance with respect to the above harmonics becomes a short circuit.
Since the impedance to the second harmonic or the third harmonic or higher is short-circuited at the gate terminal 1a of the transistor 1, the power amplifier operates with high efficiency as in the first to fourth embodiments.
実施の形態６．
　上記実施の形態１～４では、直列共振回路１９がトランジスタ１のゲート端子１ａに接続されているものを示したが、直列共振回路１９がトランジスタ１のドレイン端子１ｃに接続されているようにしてもよいし、直列共振回路１９がトランジスタ１のゲート端子１ａとドレイン端子１ｃの双方に接続されているようにしてもよい。 Embodiment 6 FIG.
In the first to fourth embodiments, the series resonant circuit 19 is connected to the gate terminal 1a of the transistor 1. However, the series resonant circuit 19 is connected to the drain terminal 1c of the transistor 1. Alternatively, the series resonant circuit 19 may be connected to both the gate terminal 1a and the drain terminal 1c of the transistor 1.
　図２９はこの発明の実施の形態６による電力増幅器を示す回路図であり、図２９において、図２と同一符号は同一または相当部分を示すので説明を省略する。
　高調波処理回路である直列共振回路２１１はトランジスタ１のドレイン端子１ｃと定電位端との間に接続され、トランジスタ１の動作周波数の２次の高調波又は３次以上の高調波で共振する第２の共振回路であり、直列共振回路２１１は多層回路基板３に形成されている。
　直列共振回路２１１は第２のインダクタであるインダクタ２１２と、第２のキャパシタであるキャパシタ２１３との直列回路で構成されている。 FIG. 29 is a circuit diagram showing a power amplifier according to Embodiment 6 of the present invention. In FIG. 29, the same reference numerals as those in FIG.
A series resonance circuit 211, which is a harmonic processing circuit, is connected between the drain terminal 1c of the transistor 1 and the constant potential end, and resonates at the second harmonic or the third or higher harmonic of the operating frequency of the transistor 1. The series resonance circuit 211 is formed on the multilayer circuit board 3.
The series resonance circuit 211 includes a series circuit including an inductor 212 that is a second inductor and a capacitor 213 that is a second capacitor.
　この実施の形態６では、上記実施の形態１における多層回路基板３内の配線パターンの一部を変更して、直列共振回路２１１を多層回路基板３内に形成している。
　ここでは、多層回路基板３の回路基板３ｅの配線パターンを変更して、直列共振回路２１１を多層回路基板３内に形成する例を説明する。
　図３０は多層回路基板３における第５層を形成している回路基板３ｅを上面から見た平面図である。
　図３０において、回路基板３ｅは、ビア２２１～２２４と、インダクタ２０，２１２の一部を形成する配線パターン２２５，２２６とを備えている。 In the sixth embodiment, a part of the wiring pattern in the multilayer circuit board 3 in the first embodiment is changed, and the series resonance circuit 211 is formed in the multilayer circuit board 3.
Here, an example in which the wiring pattern of the circuit board 3e of the multilayer circuit board 3 is changed to form the series resonance circuit 211 in the multilayer circuit board 3 will be described.
FIG. 30 is a plan view of the circuit board 3e forming the fifth layer in the multilayer circuit board 3 as viewed from above.
In FIG. 30, the circuit board 3 e includes vias 221 to 224 and wiring patterns 225 and 226 that form part of the inductors 20 and 212.
　直列共振回路１９は、電極パターン４５，５３、配線パターン６５，７５，２２５及びビア６２，７２，２２２によって形成されている。
　直列共振回路１９の一端は、ビア４４，５２，６４，７４，２２４と接続端子１４を介してトランジスタ１のゲート端子１ａと接続されており、直列共振回路１９の他端は、ビア４２と接続端子１５を介してトランジスタ１のソース端子１ｂと接続されることで接地となっている。 The series resonant circuit 19 is formed by electrode patterns 45 and 53, wiring patterns 65, 75 and 225 and vias 62, 72 and 222.
One end of the series resonance circuit 19 is connected to the gate terminal 1a of the transistor 1 through the vias 44, 52, 64, 74, and 224 and the connection terminal 14, and the other end of the series resonance circuit 19 is connected to the via 42. By being connected to the source terminal 1b of the transistor 1 via the terminal 15, it is grounded.
　直列共振回路２１１は、電極パターン４６，５４、配線パターン６６，７６，２２６及びビア６３，７３，２２３によって形成されている。
　直列共振回路２１１の一端は、ビア４１，５１，６１，７１，２２１と接続端子１３を介してトランジスタ１のドレイン端子１ｃと接続されており、直列共振回路２１１の他端は、ビア４３と接続端子１５を介してトランジスタ１のソース端子１ｂと接続されることで接地となっている。 The series resonance circuit 211 is formed by electrode patterns 46 and 54, wiring patterns 66, 76 and 226, and vias 63, 73 and 223.
One end of the series resonance circuit 211 is connected to the drain terminal 1 c of the transistor 1 via the vias 41, 51, 61, 71, and 221 and the connection terminal 13, and the other end of the series resonance circuit 211 is connected to the via 43. By being connected to the source terminal 1b of the transistor 1 via the terminal 15, it is grounded.
　直列共振回路２１１がトランジスタ１の動作周波数である基本周波数の２次の高調波又は３次以上の高調波で直列共振するように、インダクタ２１２とキャパシタ２１３の定数を選ぶことで、トランジスタ１のドレイン端子１ｃにおいて、２次の高調波又は３次以上の高調波に対するインピーダンスが低インピーダンスになる。
　トランジスタ１のドレイン端子１ｃにおいて、２次の高調波又は３次以上の高調波に対するインピーダンスが低インピーダンスになることで、電力増幅器が高効率に動作する。
　これにより、この実施の形態６によれば、上記実施の形態１～４よりも更に電力増幅器が高効率に動作するようになる。 The drain of the transistor 1 is selected by selecting constants of the inductor 212 and the capacitor 213 so that the series resonant circuit 211 performs series resonance at the second harmonic of the fundamental frequency, which is the operating frequency of the transistor 1, or the third harmonic or higher. In the terminal 1c, the impedance with respect to the second harmonic or the third harmonic or higher becomes low impedance.
In the drain terminal 1c of the transistor 1, the impedance with respect to the second harmonic or the third harmonic or higher becomes low impedance, so that the power amplifier operates with high efficiency.
As a result, according to the sixth embodiment, the power amplifier operates more efficiently than in the first to fourth embodiments.
実施の形態７．
　上記実施の形態５では、オープンスタブ１７２がトランジスタ１のゲート端子１ａに接続されているものを示したが、オープンスタブ１７２がトランジスタ１のドレイン端子１ｃに接続されているようにしてもよいし、オープンスタブ１７２がトランジスタ１のゲート端子１ａとドレイン端子１ｃの双方に接続されているようにしてもよい。 Embodiment 7 FIG.
In the fifth embodiment, the open stub 172 is connected to the gate terminal 1a of the transistor 1. However, the open stub 172 may be connected to the drain terminal 1c of the transistor 1, The open stub 172 may be connected to both the gate terminal 1a and the drain terminal 1c of the transistor 1.
　図３１はこの発明の実施の形態７による電力増幅器を示す回路図であり、図３１において、図２３と同一符号は同一または相当部分を示すので説明を省略する。
　高調波処理回路２３１は一端がトランジスタ１のドレイン端子１ｃと接続されているオープンスタブ２３２から構成されている。
　オープンスタブ２３２はトランジスタ１の動作周波数の２次の高調波又は３次以上の高調波でλ／４の線路長を有する第２のオープンスタブであり、オープンスタブ２３２は多層回路基板３に形成されている。 FIG. 31 is a circuit diagram showing a power amplifier according to Embodiment 7 of the present invention. In FIG. 31, the same reference numerals as those in FIG.
The harmonic processing circuit 231 includes an open stub 232 having one end connected to the drain terminal 1 c of the transistor 1.
The open stub 232 is a second open stub having a line length of λ / 4 at the second harmonic or the third harmonic or higher of the operating frequency of the transistor 1. The open stub 232 is formed on the multilayer circuit board 3. ing.
　この実施の形態７では、上記実施の形態５における多層回路基板３内の配線パターンの一部を変更して、高調波処理回路２３１を多層回路基板３内に形成している。
　ここでは、多層回路基板３の回路基板３ｐの配線パターンを変更して、高調波処理回路２３１を多層回路基板３内に形成する例を説明する。
　図３２は多層回路基板３における第３層を形成している回路基板３ｐを上面から見た平面図である。
　図３２において、回路基板３ｐは、ビア２４１～２４４と、オープンスタブ１７２，２３２の一部を形成する配線パターン２４５，２４６とを備えている。 In the seventh embodiment, a harmonic processing circuit 231 is formed in the multilayer circuit board 3 by changing a part of the wiring pattern in the multilayer circuit board 3 in the fifth embodiment.
Here, an example in which the wiring pattern of the circuit board 3p of the multilayer circuit board 3 is changed to form the harmonic processing circuit 231 in the multilayer circuit board 3 will be described.
FIG. 32 is a plan view of the circuit board 3p forming the third layer in the multilayer circuit board 3 as viewed from above.
32, the circuit board 3p includes vias 241 to 244 and wiring patterns 245 and 246 that form part of the open stubs 172 and 232.
　オープンスタブ１７２は、配線パターン１８３，１９５，２４５とビア１９２，２４２によって形成されている。
　オープンスタブ１７２の一端は、ビア１８２，１９４，２４４と接続端子１４を介してトランジスタ１のゲート端子１ａと接続されている。 The open stub 172 is formed by wiring patterns 183, 195, 245 and vias 192, 242.
One end of the open stub 172 is connected to the gate terminal 1 a of the transistor 1 through the vias 182, 194, 244 and the connection terminal 14.
　オープンスタブ２３２は、配線パターン１８４，１９６，２４６とビア１９３，２４３によって形成されている。
　オープンスタブ２３２の一端は、ビア１８１，１９１，２４１と接続端子１３を介してトランジスタ１のドレイン端子１ｃと接続されている。 The open stub 232 is formed by wiring patterns 184, 196, 246 and vias 193, 243.
One end of the open stub 232 is connected to the drain terminal 1 c of the transistor 1 through the vias 181, 191 and 241 and the connection terminal 13.
　オープンスタブ２３２は、トランジスタ１の動作周波数の２次の高調波又は３次以上の高調波でλ／４の線路長を有するため、トランジスタ１のドレイン端子１ｃにおいて、２次の高調波又は３次以上の高調波に対するインピーダンスが低インピーダンスになる。
　トランジスタ１のドレイン端子１ｃにおいて、２次の高調波又は３次以上の高調波に対するインピーダンスが低インピーダンスになることで、電力増幅器が高効率に動作する。
　これにより、この実施の形態７によれば、上記実施の形態５よりも更に電力増幅器が高効率に動作するようになる。 Since the open stub 232 has a line length of λ / 4 at the second harmonic or the third or higher harmonic of the operating frequency of the transistor 1, the second harmonic or the third harmonic at the drain terminal 1 c of the transistor 1. The impedance with respect to the above harmonics becomes low impedance.
In the drain terminal 1c of the transistor 1, the impedance with respect to the second harmonic or the third harmonic or higher becomes low impedance, so that the power amplifier operates with high efficiency.
As a result, according to the seventh embodiment, the power amplifier operates more efficiently than the fifth embodiment.
実施の形態８．
　上記実施の形態１では、出力整合回路７が、ボンディングワイヤ１８、パッド１２ｃ、ビア１１ｃ及び接続端子１３を介して、トランジスタ１のドレイン端子１ｃと電気的に接続されているものを示したが、トランジスタ１のドレイン端子１ｃと出力整合回路７との間の接続がボンディングワイヤだけで接続されているものであってもよい。 Embodiment 8 FIG.
In the first embodiment, the output matching circuit 7 is electrically connected to the drain terminal 1c of the transistor 1 through the bonding wire 18, the pad 12c, the via 11c, and the connection terminal 13. The connection between the drain terminal 1c of the transistor 1 and the output matching circuit 7 may be connected only by a bonding wire.
　図３３はこの発明の実施の形態８による電力増幅器を示す断面図であり、図３３において、図３と同一符号は同一または相当部分を示すので説明を省略する。
　ボンディングワイヤ２５０はトランジスタ１のドレイン端子１ｃと出力整合回路７との間を接続している。
　この実施の形態８では、多層回路基板３が、トランジスタ１のドレイン端子１ｃの上部に重ならないように配置されており、ボンディングワイヤ２５０によって、トランジスタ１のドレイン端子１ｃと出力整合回路７との間が接続されている。
　これにより、ビア１１ｃを介することなく、トランジスタ１のドレイン端子１ｃと出力整合回路７を接続することができるため、トランジスタ１のドレイン端子１ｃと出力整合回路７との間に直列に接続されるビアとボンディングワイヤによる寄生インダクタンス成分を軽減することができる。したがって、電力増幅器の狭帯域化を避けることができる。 FIG. 33 is a cross-sectional view showing a power amplifier according to Embodiment 8 of the present invention. In FIG. 33, the same reference numerals as those in FIG.
The bonding wire 250 connects between the drain terminal 1 c of the transistor 1 and the output matching circuit 7.
In the eighth embodiment, the multilayer circuit board 3 is disposed so as not to overlap the drain terminal 1 c of the transistor 1, and is connected between the drain terminal 1 c of the transistor 1 and the output matching circuit 7 by the bonding wire 250. Is connected.
Thus, since the drain terminal 1c of the transistor 1 and the output matching circuit 7 can be connected without via the via 11c, the via connected in series between the drain terminal 1c of the transistor 1 and the output matching circuit 7 The parasitic inductance component due to the bonding wire can be reduced. Therefore, it is possible to avoid narrowing the bandwidth of the power amplifier.
　なお、本願発明はその発明の範囲内において、各実施の形態の自由な組み合わせ、あるいは各実施の形態の任意の構成要素の変形、もしくは各実施の形態において任意の構成要素の省略が可能である。 In the present invention, within the scope of the invention, free combinations of the respective embodiments, modifications of arbitrary components of the respective embodiments, or omission of arbitrary components of the respective embodiments are possible. .
　この発明に係る電力増幅器は、高効率な動作を実現する必要性が高いものに適している。 The power amplifier according to the present invention is suitable for a high necessity for realizing a high-efficiency operation.
　１　トランジスタ、１ａ　ゲート端子（第１の端子）、１ｂ　ソース端子（第２の端子）、１ｃ　ドレイン端子（第３の端子）、２　半導体基板、３　多層回路基板、３ａ～３ｋ，３ｍ，３ｎ，３ｐ　回路基板、４　入力端子、５　出力端子、６　入力整合回路、７　出力整合回路、８　金属キャリア、１１ａ，１１ｂ，１１ｃ　ビア、１２ａ，１２ｂ，１２ｃ　パッド、１３　接続端子（第１の接続端子）、１４　接続端子（第２の接続端子）、１５，１５ａ，１５ｂ，１５ｃ，１５ｄ，１５ｅ　接続端子（第３の接続端子）、１６　パターン構造、１７，１８　ボンディングワイヤ、１９　直列共振回路（第１の共振回路）、２０　インダクタ（第１のインダクタ）、２１　キャパシタ（第１のキャパシタ）、３１　ビア、４１～４４　ビア、４５，４６　電極パターン、５１，５２　ビア、５３，５４　電極パターン、６１～６４　ビア、６５，６６　配線パターン、７１～７４　ビア、７５，７６　配線パターン、８１～８４　ビア、８５，８６　配線パターン、９１　ＭＩＭキャパシタ、１０１～１０４　ビア、１０５，１０６　配線パターン、１０７　配線パターン、１１１～１１４　ビア、１１５，１１６　配線パターン、１２１～１２４　ビア、１２５，１２６　配線パターン、１３１～１３４　ビア、１３５ａ，１３５ｂ，１３６　配線パターン、１４１　スパイラルインダクタ、１５１～１５６　ビア、１５７，１５８　電極パターン、１６１～１６４　ビア、１６５，１６６　電極パターン、１７１　高調波処理回路、１７２　オープンスタブ（第１のオープンスタブ）、１８１，１８２　ビア、１８３，１８４　配線パターン、１９１～１９４　ビア、１９５，１９６　配線パターン、２０１～２０４　ビア、２０５，２０６　配線パターン、２１１　直列共振回路（第２の共振回路）、２１２　インダクタ（第２のインダクタ）、２１３　キャパシタ（第２のキャパシタ）、２２１～２２４　ビア、２２５，２２６　配線パターン、２３１　高調波処理回路、２３２　オープンスタブ（第２のオープンスタブ）、２４１～２４４　ビア、２４５，２４６　配線パターン、２５０　ボンディングワイヤ。 1 transistor, 1a gate terminal (first terminal), 1b source terminal (second terminal), 1c drain terminal (third terminal), 2 semiconductor substrate, 3 multilayer circuit board, 3a-3k, 3m, 3n, 3p circuit board, 4 input terminal, 5 output terminal, 6 input matching circuit, 7 output matching circuit, 8 metal carrier, 11a, 11b, 11c via, 12a, 12b, 12c pad, 13 connection terminal (first connection terminal) , 14 connection terminal (second connection terminal), 15, 15a, 15b, 15c, 15d, 15e connection terminal (third connection terminal), 16 pattern structure, 17, 18 bonding wire, 19 series resonant circuit (first Resonance circuit), 20 inductor (first inductor), 21 capacitor (first capacitor), 31 via, 41 to 44 Via, 45, 46 electrode pattern, 51, 52 via, 53, 54 electrode pattern, 61-64 via, 65, 66 wiring pattern, 71-74 via, 75, 76 wiring pattern, 81-84 via, 85, 86 wiring Pattern, 91 MIM capacitor, 101-104 via, 105, 106 wiring pattern, 107 wiring pattern, 111-114 via, 115, 116 wiring pattern, 121-124 via, 125, 126 wiring pattern, 131-134 via, 135a, 135b, 136 wiring pattern, 141 spiral inductor, 151 to 156 vias, 157 and 158 electrode patterns, 161 to 164 vias, 165 and 166 electrode patterns, 171 harmonic processing circuit, 172 open stub (first open stub) Punchtab), 181, 182 via, 183, 184 wiring pattern, 191 to 194 via, 195, 196 wiring pattern, 201 to 204 via, 205, 206 wiring pattern, 211 series resonance circuit (second resonance circuit), 212 inductor (Second inductor), 213 capacitor (second capacitor), 221 to 224 via, 225, 226 wiring pattern, 231 harmonic processing circuit, 232 open stub (second open stub), 241 to 244 via, 245 246 wiring pattern, 250 bonding wire.

Claims (12)

  1. 　増幅対象の信号が入力される第１の端子と、定電位端と接続されている第２の端子と、増幅後の信号を出力する第３の端子とを有するトランジスタが形成されている半導体基板と、
    　前記半導体基板と層をなす位置に配置され、前記半導体基板と電気的に接続されている多層回路基板と、
    　前記トランジスタの第１の端子に接続され、前記第１の端子の入力側のインピーダンスと前記トランジスタの入力インピーダンスとの整合を図る入力整合回路と、
    　前記トランジスタの第３の端子に接続され、前記第３の端子の出力側のインピーダンスと前記トランジスタの出力インピーダンスとの整合を図る出力整合回路とを備え、
    　前記トランジスタの第１の端子と定電位端との間に接続され、前記トランジスタの動作周波数の２次の高調波又は３次以上の高調波で共振する第１の共振回路が前記多層回路基板に形成されていることを特徴とする電力増幅器。     A semiconductor substrate on which a transistor having a first terminal to which a signal to be amplified is input, a second terminal connected to a constant potential terminal, and a third terminal for outputting the amplified signal is formed When,
    A multilayer circuit board disposed in a position forming a layer with the semiconductor substrate and electrically connected to the semiconductor substrate;
    An input matching circuit connected to the first terminal of the transistor and configured to match the impedance on the input side of the first terminal and the input impedance of the transistor;
    An output matching circuit connected to the third terminal of the transistor and configured to match the impedance on the output side of the third terminal with the output impedance of the transistor;
    A first resonance circuit connected between the first terminal of the transistor and a constant potential end and resonating at a second harmonic or a third harmonic or higher of the operating frequency of the transistor is provided on the multilayer circuit board. A power amplifier which is formed.
  2. 　前記第１の共振回路は、第１のインダクタと第１のキャパシタの直列回路で構成されていることを特徴とする請求項１記載の電力増幅器。 2. The power amplifier according to claim 1, wherein the first resonance circuit includes a series circuit of a first inductor and a first capacitor.
  3. 　前記第１の共振回路を構成している第１のインダクタが前記多層回路基板に形成されており、前記第１の共振回路を構成している第１のキャパシタが前記半導体基板に形成されていることを特徴とする請求項２記載の電力増幅器。 A first inductor constituting the first resonance circuit is formed on the multilayer circuit board, and a first capacitor constituting the first resonance circuit is formed on the semiconductor substrate. The power amplifier according to claim 2.
  4. 　前記第１の共振回路を構成している第１のキャパシタが前記多層回路基板に形成されており、前記第１の共振回路を構成している第１のインダクタが前記半導体基板に形成されていることを特徴とする請求項２記載の電力増幅器。 A first capacitor constituting the first resonance circuit is formed on the multilayer circuit board, and a first inductor constituting the first resonance circuit is formed on the semiconductor substrate. The power amplifier according to claim 2.
  5. 　前記トランジスタの第３の端子と定電位端との間に接続され、前記トランジスタの動作周波数の２次の高調波又は３次以上の高調波で共振する第２の共振回路が前記多層回路基板に形成されていることを特徴とする請求項１記載の電力増幅器。 A second resonance circuit connected between the third terminal of the transistor and a constant potential end and resonating at the second harmonic or the third harmonic or higher of the operating frequency of the transistor is provided on the multilayer circuit board. The power amplifier according to claim 1, wherein the power amplifier is formed.
  6. 　前記第２の共振回路は、第２のインダクタと第２のキャパシタの直列回路で構成されていることを特徴とする請求項５記載の電力増幅器。 6. The power amplifier according to claim 5, wherein the second resonance circuit comprises a series circuit of a second inductor and a second capacitor.
  7. 　前記多層回路基板が低温焼成セラミックスで形成されていることを特徴とする請求項１記載の電力増幅器。 2. The power amplifier according to claim 1, wherein the multilayer circuit board is made of low-temperature fired ceramics.
  8. 　前記トランジスタの第３の端子と前記多層回路基板を接続する第１の接続端子と、
    　前記トランジスタの第１の端子と前記第１の共振回路を接続する第２の接続端子と、
    　前記トランジスタの第２の端子と定電位端を接続する第３の接続端子とを備え、
    　前記第１から第３の接続端子がフリップチップ実装によって実装されていることを特徴とする請求項１記載の電力増幅器。     A first connection terminal connecting the third terminal of the transistor and the multilayer circuit board;
    A second connection terminal connecting the first terminal of the transistor and the first resonant circuit;
    A third connection terminal for connecting a second terminal of the transistor and a constant potential terminal;
    2. The power amplifier according to claim 1, wherein the first to third connection terminals are mounted by flip chip mounting.
  9. 　増幅対象の信号が入力される第１の端子と、定電位端と接続されている第２の端子と、増幅後の信号を出力する第３の端子とを有するトランジスタが形成されている半導体基板と、
    　前記半導体基板と層をなす位置に配置され、前記半導体基板と電気的に接続されている多層回路基板と、
    　前記トランジスタの第１の端子に接続され、前記第１の端子の入力側のインピーダンスと前記トランジスタの入力インピーダンスとの整合を図る入力整合回路と、
    　前記トランジスタの第３の端子に接続され、前記第３の端子の出力側のインピーダンスと前記トランジスタの出力インピーダンスとの整合を図る出力整合回路とを備え、
    　一端が前記トランジスタの第１の端子と接続され、前記トランジスタの動作周波数の２次の高調波又は３次以上の高調波で４分の１波長の線路長を有する第１のオープンスタブが前記多層回路基板に形成されていることを特徴とする電力増幅器。     A semiconductor substrate on which a transistor having a first terminal to which a signal to be amplified is input, a second terminal connected to a constant potential terminal, and a third terminal for outputting the amplified signal is formed When,
    A multilayer circuit board disposed in a position forming a layer with the semiconductor substrate and electrically connected to the semiconductor substrate;
    An input matching circuit connected to the first terminal of the transistor and configured to match the impedance on the input side of the first terminal and the input impedance of the transistor;
    An output matching circuit connected to the third terminal of the transistor and configured to match the impedance on the output side of the third terminal with the output impedance of the transistor;
    A first open stub having one end connected to the first terminal of the transistor and having a line length of a quarter wavelength at a second harmonic or a third or higher harmonic of the operating frequency of the transistor is the multilayer. A power amplifier formed on a circuit board.
  10. 　一端が前記トランジスタの第３の端子と接続され、前記トランジスタの動作周波数の２次の高調波又は３次以上の高調波で４分の１波長の線路長を有する第２のオープンスタブが前記多層回路基板に形成されていることを特徴とする請求項９記載の電力増幅器。 One end is connected to the third terminal of the transistor, and a second open stub having a line length of a quarter wavelength at the second harmonic or the third harmonic or higher of the operating frequency of the transistor is the multilayer. The power amplifier according to claim 9, wherein the power amplifier is formed on a circuit board.
  11. 　前記多層回路基板が低温焼成セラミックスで形成されていることを特徴とする請求項９記載の電力増幅器。 10. The power amplifier according to claim 9, wherein the multilayer circuit board is made of low-temperature fired ceramics.
  12. 　前記トランジスタの第３の端子と前記多層回路基板を接続する第１の接続端子と、
    　前記トランジスタの第１の端子と前記第１のオープンスタブを接続する第２の接続端子とを備え、
    　前記第１及び第２の接続端子がフリップチップ実装によって実装されていることを特徴とする請求項９記載の電力増幅器。     A first connection terminal connecting the third terminal of the transistor and the multilayer circuit board;
    A first connection terminal for connecting the first open stub to the first terminal of the transistor;
    The power amplifier according to claim 9, wherein the first and second connection terminals are mounted by flip chip mounting.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019200532A1 (en) * 2018-04-17 2019-10-24 Telefonaktiebolaget Lm Ericsson (Publ) Radio frequency power amplifier with harmonic control circuit as well as method for manufacturing the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0837433A (en) * 1994-05-19 1996-02-06 Matsushita Electric Ind Co Ltd High frequency power amplifier
US20130113117A1 (en) * 2011-11-04 2013-05-09 Nikolaos Haralabidis Wireless Communication Devices With In-Package Integrated Passive Components
JP2013141291A (en) * 2007-06-22 2013-07-18 Cree Inc Rf power transistor package accompanying harmonic frequency reduction inside and formation method of the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0837433A (en) * 1994-05-19 1996-02-06 Matsushita Electric Ind Co Ltd High frequency power amplifier
JP2013141291A (en) * 2007-06-22 2013-07-18 Cree Inc Rf power transistor package accompanying harmonic frequency reduction inside and formation method of the same
US20130113117A1 (en) * 2011-11-04 2013-05-09 Nikolaos Haralabidis Wireless Communication Devices With In-Package Integrated Passive Components

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019200532A1 (en) * 2018-04-17 2019-10-24 Telefonaktiebolaget Lm Ericsson (Publ) Radio frequency power amplifier with harmonic control circuit as well as method for manufacturing the same
US11533028B2 (en) 2018-04-17 2022-12-20 Telefonaktiebolaget Lm Ericsson (Publ) Radio frequency power amplifier with harmonic control circuit as well as method for manufacturing the same

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