WO2016203341A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2016203341A1
WO2016203341A1 PCT/IB2016/053315 IB2016053315W WO2016203341A1 WO 2016203341 A1 WO2016203341 A1 WO 2016203341A1 IB 2016053315 W IB2016053315 W IB 2016053315W WO 2016203341 A1 WO2016203341 A1 WO 2016203341A1
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Prior art keywords
insulator
conductor
transistor
semiconductor
oxide semiconductor
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PCT/IB2016/053315
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French (fr)
Japanese (ja)
Inventor
山崎舜平
松田慎平
鈴木陽夫
Original Assignee
株式会社半導体エネルギー研究所
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Application filed by 株式会社半導体エネルギー研究所 filed Critical 株式会社半導体エネルギー研究所
Priority to JP2017524138A priority Critical patent/JP6698649B2/en
Publication of WO2016203341A1 publication Critical patent/WO2016203341A1/en

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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/08—Oxides
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/42—Bombardment with radiation
    • H01L21/423—Bombardment with radiation with high-energy radiation
    • H01L21/425—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/477—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present invention relates to a transistor and a semiconductor device, for example.
  • the present invention relates to a method for manufacturing a transistor and a semiconductor device, for example.
  • the present invention relates to, for example, a display device, a light-emitting device, a lighting device, a power storage device, a storage device, a processor, and an electronic device.
  • the present invention relates to a method for manufacturing a display device, a liquid crystal display device, a light-emitting device, a memory device, or an electronic device.
  • the present invention relates to a display device, a liquid crystal display device, a light-emitting device, a memory device, and a driving method of an electronic device.
  • one embodiment of the present invention is not limited to the above technical field.
  • the technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method.
  • one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).
  • a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics.
  • a display device, a light-emitting device, a lighting device, an electro-optical device, a semiconductor circuit, and an electronic device may include a semiconductor device.
  • Transistors made of silicon are widely used in various integrated circuits (ICs) such as CPUs and memories constituting electronic devices. As electronic devices become more sophisticated, smaller, and lighter, integrated circuits are highly integrated and transistors are becoming smaller in size. In accordance with this, process rules for manufacturing transistors are also decreasing year by year, such as 45 nm, 32 nm, and 22 nm.
  • the short channel effect is a deterioration in electrical characteristics that becomes apparent as a transistor is miniaturized (channel length (L) is reduced), and is caused by the effect of the electric field of the drain electrode reaching the source electrode. is there.
  • Specific examples of the short channel effect include a decrease in threshold voltage, an increase in subthreshold swing value, and an increase in leakage current.
  • a nanowire transistor is a transistor using an extremely thin cylindrical silicon having a diameter of several nm to several tens of nm as an active layer.
  • the gate surrounds the silicon so as to intersect the extending direction of the silicon, and the gate electrode surrounding the entire periphery can prevent the electric field of the drain electrode from affecting the source electrode.
  • the leakage current of non-conducting nanowire transistors using silicon is about several ⁇ A / ⁇ m, and it is required to further reduce the leakage current at a gate voltage of 0V.
  • an object of one embodiment of the present invention is to provide a transistor having resistance to a short channel effect. Another object is to provide a transistor having normally-off electrical characteristics. Another object is to provide a transistor with low leakage current during non-conduction. Another object is to provide a transistor with a small subthreshold swing value. Another object is to provide a transistor having stable electrical characteristics in a microstructure with a short channel length.
  • Another object is to provide a semiconductor device including the transistor. Another object is to provide a module including the semiconductor device. Another object is to provide an electronic device including the semiconductor device or the module. Another object is to provide a novel semiconductor device. Another object is to provide a new module. Another object is to provide a novel electronic device.
  • One embodiment of the present invention includes a first conductor provided in a ring shape, an oxide semiconductor including a region extending through the inside of the ring of the first conductor, the first conductor, and the oxide semiconductor.
  • the first insulator provided between the first insulator, the first conductor, the second insulator provided between the first insulator, and the inside of the ring of the first conductor.
  • a second conductor, and the second conductor is a semiconductor device provided in the second insulator.
  • Another embodiment of the present invention includes the third conductor and the fourth conductor which are in contact with the oxide semiconductor and are provided with the first conductor interposed therebetween, in the above invention.
  • the semiconductor device is characterized in that the distance between the third conductor and the fourth conductor is 2 nm or more and 30 nm or less.
  • One embodiment of the present invention is the semiconductor device according to the above invention, in which a cross-sectional shape in a plane substantially perpendicular to the extending direction of the oxide semiconductor is a substantially circular shape.
  • Another embodiment of the present invention is the semiconductor device according to the above invention, in which a cross-sectional shape in a plane substantially perpendicular to the extending direction of the oxide semiconductor is a substantially polygonal shape.
  • Another embodiment of the present invention is the semiconductor device according to the above invention, wherein the semiconductor device is provided over a substrate, and an upper surface of the substrate is substantially parallel to an extension direction of the oxide semiconductor. .
  • Another embodiment of the present invention is the semiconductor device according to the above invention, wherein the semiconductor device is provided over a substrate, and the top surface of the substrate is substantially perpendicular to the extending direction of the oxide semiconductor. .
  • the first insulator is at least one of indium, an element M (Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf) and zinc.
  • an element M Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf
  • a first conductor provided to extend in a first direction over a substrate, a first insulator provided over the first conductor, A second insulator having an opening provided on the first insulator and an opening formed in the second insulator extending in a second direction substantially perpendicular to the first direction.
  • a second conductor provided; a second insulator; a third insulator provided on the second conductor; a fourth insulator provided on the third insulator; A third conductor and a fourth conductor provided on the third insulator with a fourth insulator interposed therebetween, and a fourth insulator, a third conductor, and a fourth conductor.
  • An oxide semiconductor provided in contact with the upper surface of the oxide semiconductor layer and extending in the second direction; an upper surface and side surfaces of the oxide semiconductor; and a side surface of the third conductor; Sixth conductor sandwiched between The fifth conductor provided in opposition, the upper surface and side surfaces of the oxide semiconductor, and the side surfaces of the fourth conductor are opposed to the fifth conductor with the fifth insulator interposed therebetween.
  • a sixth conductor provided on the fifth conductor and the sixth conductor, and a sixth insulator having an opening between the fifth conductor and the sixth conductor; A top surface of the oxide semiconductor; a side surface of the fifth conductor and the sixth conductor; a fifth insulator provided in contact with the side surface of the sixth insulator; and a top surface of the fifth insulator.
  • a seventh conductor provided in contact with the upper surface of the seventh insulator, and in a cross section of a plane substantially perpendicular to the first direction, the fourth insulator
  • the insulator and the fifth insulator are provided so as to surround the oxide semiconductor
  • the third insulator and the seventh insulator include the fourth insulator, the oxide semiconductor, and the fifth insulator.
  • conductor of the first conductor and the seventh is a semiconductor device which is characterized in that it is provided to surround the first through third insulator and the seventh insulator.
  • Another embodiment of the present invention is the above invention, wherein the fourth insulator and the fifth insulator are indium, an element M (Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf). And a semiconductor device having at least one of zinc.
  • the oxide semiconductor includes indium, an element M (Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf), zinc, and oxygen. This is a featured semiconductor device.
  • a transistor having resistance to the short channel effect can be provided.
  • a transistor having normally-off electrical characteristics can be provided.
  • a transistor with low leakage current when not conducting can be provided.
  • a transistor with a small subthreshold swing value can be provided.
  • a transistor having stable electrical characteristics can be provided in a microstructure with a short channel length.
  • a semiconductor device including the transistor can be provided.
  • a module including the semiconductor device can be provided.
  • an electronic device including the semiconductor device or the module can be provided.
  • a novel semiconductor device can be provided.
  • a new module can be provided.
  • a novel electronic device can be provided.
  • 4A and 4B are a top view and cross-sectional views illustrating a transistor according to one embodiment of the present invention.
  • 6A and 6B are cross-sectional views illustrating a transistor according to one embodiment of the present invention.
  • 6A and 6B are cross-sectional views illustrating a transistor according to one embodiment of the present invention.
  • 6A and 6B are cross-sectional views illustrating a transistor according to one embodiment of the present invention.
  • 6A and 6B are cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention.
  • 6A and 6B are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention.
  • FIGS. 4A to 4C illustrate structural analysis by XRD of a CAAC-OS and a single crystal oxide semiconductor, and FIGS. Sectional TEM image of CAAC-OS, planar TEM image and image analysis image thereof. The figure which shows the electron diffraction pattern of nc-OS, and the cross-sectional TEM image of nc-OS. Cross-sectional TEM image of a-like OS.
  • FIG. 4A to 4C illustrate structural analysis by XRD of a CAAC-OS and a single crystal oxide semiconductor
  • FIG. 10 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention.
  • FIG. 10 is a circuit diagram illustrating a memory device according to one embodiment of the present invention.
  • FIG. 10 is a circuit diagram illustrating a memory device according to one embodiment of the present invention.
  • 6A and 6B are a circuit diagram and a timing chart for illustrating one embodiment of the present invention.
  • 5A and 5B are a graph and a circuit diagram for illustrating one embodiment of the present invention.
  • 6A and 6B are a circuit diagram and a timing chart for illustrating one embodiment of the present invention.
  • FIGS. 6A and 6B are a circuit diagram and a timing chart for illustrating one embodiment of the present invention.
  • 1 is a block diagram illustrating a semiconductor device according to one embodiment of the present invention.
  • FIG. 10 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention.
  • FIG. 11 is a perspective view illustrating an electronic device according to one embodiment of the present invention.
  • FIG. 5 is a schematic diagram illustrating a model of a transistor used in this example. The graph which shows the calculation result of a present Example.
  • the voltage often indicates a potential difference between a certain potential and a reference potential (for example, a ground potential (GND) or a source potential).
  • a voltage can be rephrased as a potential.
  • the potential (voltage) is relative and is determined by a relative magnitude from a reference potential. Therefore, even when “ground potential” is described, the potential is not always 0V.
  • the lowest potential in the circuit may be the “ground potential”.
  • an intermediate potential in the circuit may be a “ground potential”. In that case, a positive potential and a negative potential are defined based on the potential.
  • the semiconductor device may have characteristics as an “insulator”.
  • the boundary between “semiconductor” and “insulator” is ambiguous and may not be strictly discriminated. Therefore, a “semiconductor” in this specification can be called an “insulator” in some cases.
  • an “insulator” in this specification can be called a “semiconductor” in some cases.
  • semiconductor even when “semiconductor” is described, for example, when the conductivity is sufficiently high, it may have a characteristic as a “conductor”. In addition, the boundary between “semiconductor” and “conductor” is ambiguous, and there are cases where it cannot be strictly distinguished. Therefore, a “semiconductor” in this specification can be called a “conductor” in some cases. Similarly, a “conductor” in this specification can be called a “semiconductor” in some cases.
  • the impurity of a semiconductor means the thing other than the main component which comprises a semiconductor, for example.
  • an element having a concentration of less than 0.1 atomic% is an impurity.
  • impurities for example, DOS (Density of State) may be formed in a semiconductor, carrier mobility may be reduced, and crystallinity may be reduced.
  • examples of impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 14 elements, Group 15 elements, and transition metals other than the main component.
  • hydrogen also included in water
  • lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen and the like are examples of impurities that change the characteristics of the semiconductor.
  • oxygen vacancies may be formed by mixing impurities such as hydrogen, for example.
  • impurities such as hydrogen, for example.
  • examples of impurities that change the characteristics of the semiconductor include group 1 elements, group 2 elements, group 13 elements, and group 15 elements excluding oxygen and hydrogen.
  • the channel length refers to, for example, a region where a semiconductor (or a portion where current flows in the semiconductor when the transistor is on) and a gate electrode overlap with each other in a top view of the transistor, or a region where a channel is formed
  • the channel length is not necessarily the same in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.
  • the channel width is, for example, a region in which a semiconductor (or a portion in which a current flows in the semiconductor when the transistor is on) and a gate electrode overlap each other, or a source and a drain in a region where a channel is formed. This is the length of the part. Note that in one transistor, the channel width is not necessarily the same in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in this specification, the channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.
  • the channel width in a region where a channel is actually formed (hereinafter referred to as an effective channel width) and the channel width shown in a top view of the transistor (hereinafter, apparent channel width). May be different).
  • the effective channel width is larger than the apparent channel width shown in the top view of the transistor, and the influence may not be negligible.
  • the ratio of channel regions formed on the side surface and the bottom surface of a semiconductor may increase. In that case, the effective channel width in which the channel is actually formed is larger than the apparent channel width shown in the top view.
  • parallel means a state in which two straight lines are arranged at an angle of ⁇ 10 ° to 10 °. Therefore, the case of ⁇ 5 ° to 5 ° is also included.
  • substantially parallel means a state in which two straight lines are arranged at an angle of ⁇ 30 ° to 30 °.
  • Vertical refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included.
  • substantially vertical means a state in which two straight lines are arranged at an angle of 60 ° to 120 °.
  • FIG. 1A is a top view of the transistor 10.
  • FIG. 1B is a cross-sectional view corresponding to one-dot chain line A1-A2 in FIG. 1A
  • FIG. 1C is a cross-sectional view corresponding to one-dot chain line A3-A4 in FIG.
  • a region indicated by an alternate long and short dash line A1-A2 indicates a structure in the channel length direction of the transistor 10
  • a region indicated by an alternate long and short dash line A3-A4 indicates a structure in a direction perpendicular to the alternate long and short dashed line A1-A2. .
  • the channel length direction of a transistor means a direction in which carriers move between a source (source region or source electrode) and a drain (drain region or drain electrode). Further, in FIGS. 1A and 1B, some structures such as the insulator 112 are omitted in order to avoid complexity.
  • the transistor 10 includes a conductor 114 provided in a ring shape, a semiconductor 106b having a region extending through the inside of the ring of the conductor 114, an insulator 106a provided between the conductor 114 and the semiconductor 106b, An insulator 112 provided between the body 114 and the insulator 106a, and a conductor 102 provided through the inside of the ring of the conductor 114.
  • the conductor 102 is provided in the insulator 112.
  • a conductor 108a and a conductor 108b are provided to be in contact with the semiconductor 106b and face each other with the conductor 114 interposed therebetween.
  • the insulator 106a and the insulator 112 can also be referred to as insulating films or insulating layers.
  • the conductor 102, the conductor 108a, the conductor 108b, and the conductor 114 can also be referred to as conductive films or conductive layers.
  • the semiconductor 106b can also be referred to as a semiconductor film or a semiconductor layer.
  • the insulator 106a when used alone, a substance that can function as a conductor, a semiconductor, or an insulator may be used. However, when a transistor is formed in contact with the semiconductor 106b, electrons flow in the vicinity of the semiconductor 106b and the interface between the semiconductor 106b and the insulator 106a, and the insulator 106a has a region that does not function as a channel of the transistor. Therefore, in this specification and the like, the insulator 106a is not described as a conductor and a semiconductor but is described as an insulator.
  • the semiconductor 106b functions as an active layer
  • the conductor 114 functions as a gate electrode
  • the insulator 112 functions as a gate insulating film
  • the conductor 108a and the conductor 108b function as a source electrode or a drain electrode.
  • the semiconductor 106b is provided to extend at least in a portion passing through the inside of the ring of the conductor 114, and takes a shape such as a string shape, a rod shape, or a column shape.
  • the cross-sectional shape in a cross section substantially perpendicular to the extending direction of the semiconductor 106b is preferably a substantially circular shape.
  • the width of the semiconductor 106b in FIG. 1C (also referred to as a diameter if the semiconductor 106b is circular) is approximately several nm to several tens of nm, for example, 1 nm to 50 nm, preferably 2 nm to 30 nm. That's fine.
  • the substantially circular shape includes not only a perfect circle but also a circle deviated from a true circle such as an ellipse.
  • the semiconductor 106b is an elongated wire-like structure having a width of several nanometers to several tens of nanometers, it can be called a nanowire.
  • the insulator 106a, the conductor 108a, the conductor 108b, the insulator 112, the conductor 102, and the conductor 114 are included in an elongated wire-like structure. These can also be called nanowires.
  • the transistor 10 is a transistor using nanowires, it can also be called a nanowire transistor.
  • the insulator 106a is provided in contact with the semiconductor 106b in at least part of a region where the semiconductor 106b and the conductor 114 overlap.
  • the insulator 106a is provided concentrically in contact with the semiconductor 106b in a cross section substantially perpendicular to the extending direction (A1-A2 direction) of the semiconductor 106b.
  • the conductor 108a and the conductor 108b are preferably provided so that the side surfaces are in contact with the insulator 106a and face each other.
  • the conductor 108a and the conductor 108b are preferably provided so as to surround the semiconductor 106b in a cross section substantially perpendicular to the extending direction (A1-A2 direction) of the semiconductor 106b.
  • the channel length L of the transistor 10 is the distance between the conductor 108a and the conductor 108b.
  • the distance between the conductor 108a and the conductor 108b, that is, the channel length L of the transistor 10 may be several nanometers to several tens of nanometers, for example, preferably 2 nm to 30 nm.
  • side end portions of the conductor 108a and the conductor 108b have a tapered shape.
  • the inclination angle ⁇ of the side end portions of the conductors 108a and 108b is 30 ° or more and less than 90 °, preferably 45 ° or more and less than 80 °, more preferably 45 ° or more and less than 60 °.
  • the side end portions of the conductor 108a and the conductor 108b are tapered, whereby the distance between the conductor 108a and the conductor 108b can be further shortened, and the channel length L of the transistor 10 can be shortened. Can do.
  • the conductor 114 is provided in an annular shape so as to surround at least a part of the semiconductor 106b, the insulator 106a, and the conductor 102.
  • the term “annular” includes not only a ring but also a shape such as a polygonal ring.
  • the conductor 114 only needs to surround at least part of the semiconductor 106b, the insulator 106a, and the conductor 102.
  • the conductor 114 may have a structure including a closed circuit structure.
  • the conductor 114 is formed so as to overlap with at least part of a region between the conductor 108a and the conductor 108b of the semiconductor 106b (also referred to as a channel formation region of the semiconductor 106b). preferable.
  • the insulator 112 is preferably formed so as to fill a space between the insulator 106a and the conductor 114. Further, it is preferable that the semiconductor 106b, the conductor 102, and the conductor 114 are insulated from each other by the insulator 112. Therefore, the insulator 112 may be formed by combining a plurality of insulators. For example, the insulator 112 may be formed by combining an insulator formed between the insulator 106a and the conductor 102 and an insulator formed between the conductor 102 and the conductor 114.
  • the conductor 102 is provided through the inside of the ring of the conductor 114, and is formed between the insulator 106 a and the conductor 114 via the insulator 112.
  • the width of the conductor 102 may be approximately the same as the width of the semiconductor 106b, for example, in a cross section substantially perpendicular to the extending direction (A1-A2 direction) of the semiconductor 106b.
  • the width of the conductor 102 is not limited to this, and can be set as appropriate.
  • the shape of the conductor 102 may be a shape having a concentric arc with the semiconductor 106b.
  • the shape of the conductor 102 is not limited to this, and can be set as appropriate.
  • the transistor 10 is provided over a substrate, but the transistor 10 may be formed so that the extending direction (A1-A2 direction) of the semiconductor 106b is substantially parallel to the upper surface of the substrate. Alternatively, the transistor 10 may be formed so that the extending direction (A1-A2 direction) of the semiconductor 106b is substantially perpendicular to the upper surface of the substrate.
  • the semiconductor 106b is an oxide semiconductor containing indium, for example.
  • the semiconductor 106b preferably contains an element M.
  • the element M preferably represents Ti, Ga, Y, Zr, La, Ce, Nd, Sn or Hf. However, the element M may be a combination of a plurality of the aforementioned elements.
  • the element M is an element having a high binding energy with oxygen, for example. For example, it is an element whose binding energy with oxygen is higher than that of indium. Alternatively, the element M is an element having a function of increasing the energy gap of the oxide semiconductor, for example.
  • the semiconductor 106b preferably contains zinc. An oxide semiconductor may be easily crystallized when it contains zinc.
  • the semiconductor 106b is not limited to an oxide semiconductor containing indium.
  • the semiconductor 106b may be an oxide semiconductor containing zinc, an oxide semiconductor containing gallium, an oxide semiconductor containing tin, or the like that does not contain indium, such as zinc tin oxide and gallium tin oxide.
  • the insulator 106a is an oxide semiconductor including one or more elements other than oxygen constituting the semiconductor 106b, or two or more elements. Since the insulator 106a includes one or more elements other than oxygen included in the semiconductor 106b, or two or more elements, a defect level is hardly formed at the interface between the insulator 106a and the semiconductor 106b.
  • the insulator 106a and the semiconductor 106b preferably contain at least indium.
  • the insulator 106a is an In—M—Zn oxide
  • In is preferably less than 50 atomic%
  • M is higher than 50 atomic%
  • more preferably In is 25 atomic%
  • M is higher than 75 atomic%.
  • the semiconductor 106b is an In-M-Zn oxide
  • the In is preferably higher than 25 atomic%
  • the M is less than 75 atomic%, and more preferably, In is more than 34 atomic%.
  • High, and M is less than 66 atomic%.
  • the insulator 106a may not contain indium in some cases.
  • the insulator 106a may be gallium oxide.
  • the number of atoms of each element included in the insulator 106a and the semiconductor 106b may not be a simple integer ratio.
  • an oxide having a large energy gap is used for the semiconductor 106b.
  • the energy gap of the semiconductor 106b is, for example, 2.5 eV to 4.2 eV, preferably 2.8 eV to 3.8 eV, and more preferably 3 eV to 3.5 eV.
  • the energy gap of the insulator 106a is larger than the energy gap of the semiconductor 106b.
  • an oxide having an electron affinity higher than that of the insulator 106a is used.
  • an oxide having an electron affinity higher than that of the insulator 106a by 0.07 eV to 1.3 eV, preferably 0.1 eV to 0.7 eV, more preferably 0.15 eV to 0.4 eV is used.
  • the electron affinity is the difference between the vacuum level and the energy at the bottom of the conduction band. In other words, the energy level at the lower end of the conduction band of the insulator 106a is closer to the vacuum level than the energy level at the lower end of the conduction band of the semiconductor 106b.
  • the insulator 106a is made of a substance that can function as a conductor, a semiconductor, or an insulator when used alone.
  • the insulator 106a is not described as a semiconductor but is described as an insulator.
  • the insulator 106a is described as an insulator because it has a function similar to that of an insulator compared to the semiconductor 106b, and thus a substance that can be used for the semiconductor 106b is used as the insulator 106a. In some cases.
  • the mixed region may be a mixed region of the insulator 106a and the semiconductor 106b between the insulator 106a and the semiconductor 106b.
  • the mixed region has a low density of defect states. Therefore, energy continuously changes (also referred to as a continuous junction) in the vicinity of the interface between the insulator 106a and the semiconductor 106b (see FIG. 8). Note that in some cases, the interface between the insulator 106a and the semiconductor 106b cannot be clearly distinguished.
  • the insulator 106a and the semiconductor 106b, particularly the semiconductor 106b described in this embodiment are oxide semiconductors with low impurity concentration and low defect state density (low oxygen vacancies), and have high purity intrinsic or substantially high purity. It can be called an intrinsic oxide semiconductor.
  • a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has few carrier generation sources, and thus can have a low carrier density. Therefore, a transistor in which a channel region is formed in the oxide semiconductor rarely has electrical characteristics (also referred to as normally-on) in which the threshold voltage is negative.
  • a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has a low density of defect states, and thus may have a low density of trap states.
  • a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has an extremely small off-state current, an element having a channel width W of 1 ⁇ 10 6 ⁇ m and a channel length L of 10 ⁇ m.
  • the voltage between the drain electrodes is in the range of 1V to 10V, it is possible to obtain a characteristic that the off-current is less than the measurement limit of the semiconductor parameter analyzer, that is, 1 ⁇ 10 ⁇ 13 A or less.
  • a transistor in which a channel region is formed in the high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor can have a small variation in electrical characteristics and be a highly reliable transistor.
  • the charge trapped in the trap level of the oxide semiconductor takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel region is formed in an oxide semiconductor with a high trap state density may have unstable electrical characteristics.
  • impurities include hydrogen, nitrogen, alkali metals, and alkaline earth metals.
  • Hydrogen contained in the insulator 106a and the semiconductor 106b reacts with oxygen bonded to a metal atom to be water, and forms oxygen vacancies in a lattice from which oxygen is released (or a portion from which oxygen is released). When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. In addition, a part of hydrogen may be combined with oxygen bonded to a metal atom to generate electrons as carriers. In particular, hydrogen trapped in oxygen vacancies may form a shallow donor level with respect to a semiconductor band structure. Therefore, a transistor including an oxide semiconductor containing hydrogen is likely to be normally on. Therefore, the insulator 106a and the semiconductor 106b are preferably reduced as much as possible.
  • the hydrogen concentration obtained by secondary ion mass spectrometry is 2 ⁇ 10 20 atoms / cm 3 or less, preferably 5 ⁇ 10 19. atoms / cm 3 or lower, more preferably 1 ⁇ 10 19 atoms / cm 3 or lower, 5 ⁇ 10 18 atoms / cm 3 or lower, preferably 1 ⁇ 10 18 atoms / cm 3 or lower, more preferably 5 ⁇ 10 17 atoms / cm 3 or lower. cm 3 or less, more preferably 1 ⁇ 10 16 atoms / cm 3 or less.
  • the concentration of silicon or carbon in the insulator 106a and the semiconductor 106b and the concentration of silicon or carbon in the vicinity of the interface between the insulator 106a and the semiconductor 106b are 2 ⁇ 10 18 atoms / cm 3.
  • it is preferably 2 ⁇ 10 17 atoms / cm 3 or less.
  • the concentration of alkali metal or alkaline earth metal obtained by SIMS analysis is set to 1 ⁇ 10 18 atoms / cm 3 or lower, preferably 2 ⁇ 10 16 atoms / cm 3 or lower.
  • concentration of alkali metal or alkaline earth metal in the insulator 106a and the semiconductor 106b is set to 1 ⁇ 10 18 atoms / cm 3 or lower, preferably 2 ⁇ 10 16 atoms / cm 3 or lower.
  • the insulator 106a and the semiconductor 106b contain nitrogen, electrons as carriers are generated, the carrier density is increased, and the n-type is easily obtained. As a result, a transistor including an oxide semiconductor film containing nitrogen is likely to be normally on. Therefore, in the semiconductor 106b, nitrogen is preferably reduced as much as possible.
  • the nitrogen concentration obtained by SIMS analysis is preferably 5 ⁇ 10 18 atoms / cm 3 or less.
  • a low resistance region may be formed in the vicinity of the interface in contact with the conductor 108a or the conductor 108b such as the semiconductor 106b.
  • the low-resistance region is mainly formed by oxygen being extracted from the conductor 108a or the conductor 108b with which the semiconductor 106b is in contact or a conductive material contained in the conductor 108a or the conductor 108b is bonded to an element in the semiconductor 106b. It is formed.
  • the above two-layer structure of the insulator 106a and the semiconductor 106b is an example.
  • a single-layer structure without the insulator 106a may be used, or an n-layer structure (n is an integer of 3 or more) further including any of the insulators, semiconductors, and conductors exemplified as the insulator 106a or the semiconductor 106b. It doesn't matter.
  • FIG. 9 is a schematic diagram of a transistor model used for numerical calculation.
  • a semiconductor film is formed between the source electrode and the drain electrode, a gate insulating film is formed on the source electrode, the semiconductor film, and the drain electrode.
  • a gate electrode is formed on the substrate.
  • ⁇ S is the dielectric constant of the semiconductor film
  • ⁇ OX is the dielectric constant of the gate insulating film
  • t S is the thickness of the semiconductor film
  • t OX is the thickness of the gate insulating film.
  • the relative dielectric constant of ⁇ S was 15, the relative dielectric constant of ⁇ ox was 4.1, and the dielectric constant of vacuum was 8.854187817 ⁇ 10 ⁇ 12 F / m. Further, t S was set to 15 nm and t OX was set to 10 nm. Further, L is the distance (channel length) between the source electrode and the drain electrode.
  • a transistor including an oxide semiconductor film is an n-channel storage transistor and is represented by the following formula (1).
  • ⁇ (x) is the potential at the position x (surface potential)
  • ⁇ (x + dx) is the potential at the position x + dx (surface potential)
  • V G is the gate voltage
  • V FB is the flat band voltage
  • e is the elementary charge
  • N C is the effective state density
  • k B is the Boltzmann constant
  • T is the absolute temperature.
  • V G 0V
  • V FB 0.4V
  • N C 5.00 ⁇ 10 18 pieces / cm 3
  • T 300K.
  • the transistor Assuming an n-channel inversion transistor as a comparison target, the transistor is represented by the following formula (2).
  • Poisson's equation can be obtained by transforming the above equations (1) and (2).
  • the Poisson equation was numerically calculated to analyze the channel potential.
  • FIG. 10A and FIG. 10B show the results of numerical calculation of the potential of the storage channel portion and the potential of the inversion channel portion.
  • the horizontal axis represents x [nm] and the vertical axis represents ⁇ e ⁇ (x) [eV].
  • 10C and 10D show graphs obtained by normalizing the horizontal axis x in FIGS. 10A and 10B with L.
  • the potential of the accumulation type model is larger than the potential of the inversion type model, and this tendency becomes more prominent as L becomes shorter.
  • the carrier density can be further reduced by reducing the impurity concentration in the OS film and making it highly purified intrinsic or substantially highly purified intrinsic. It is possible to increase the resistance to.
  • a transistor having a structure in which an oxide semiconductor film is surrounded by a gate electrode by forming a transistor having a structure in which an oxide semiconductor film is surrounded by a gate electrode, a transistor having resistance to a short channel effect can be formed. For example, it is estimated that good off-current characteristics can be obtained even when the channel length is about 2 nm to 30 nm.
  • the conductor 102 preferably overlaps at least partially in a region sandwiched between the conductor 108a and the conductor 108b of the semiconductor 106b.
  • the conductor 102 functions as a back gate of the transistor 10.
  • the threshold voltage of the transistor 10 can be controlled.
  • the transistor 10 is prevented from becoming conductive when the voltage applied to the gate (conductor 114) of the transistor 10 is low, for example, when the applied voltage is 0 V or less. be able to. That is, it becomes easier to shift the electrical characteristics of the transistor 10 in a normally-off direction.
  • Examples of the conductor 102 include boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium,
  • a conductor containing one or more of tin, tantalum, and tungsten may be used in a single layer or a stacked layer.
  • it may be an alloy or a compound, a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin and oxygen, a conductor containing titanium and nitrogen Etc. may be used.
  • the insulator 112 functions as a gate insulating film with respect to the conductor 114 and the conductor 102 in the transistor 10.
  • the insulator 112 is preferably an insulator having excess oxygen.
  • the insulator 112 includes, for example, an insulating material including boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum.
  • the body may be used in a single layer or a stack.
  • the insulator 112 aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or oxide Tantalum may be used.
  • silicon oxide or silicon oxynitride is used.
  • oxygen can be supplied from the insulator 112 to the insulator 106a and the semiconductor 106b.
  • oxygen vacancies that are defects in the insulator 106a and the semiconductor 106b can be reduced. Accordingly, the density of defect states in the insulator 106a and the semiconductor 106b can be reduced.
  • excess oxygen means the oxygen contained exceeding a stoichiometric composition, for example.
  • excess oxygen refers to, for example, oxygen released from a film or layer containing excess oxygen by heating. Excess oxygen can move, for example, inside a film or layer. Excess oxygen may be moved between atoms of a film or layer, or may be moved in a rushing manner while replacing oxygen constituting the film or layer.
  • the insulator 112 having excess oxygen has a desorption amount of oxygen molecules in a surface temperature range of 100 ° C. to 700 ° C. or 100 ° C. to 500 ° C. in a temperature-programmed desorption gas spectroscopy analysis (TDS analysis).
  • TDS analysis temperature-programmed desorption gas spectroscopy analysis
  • the total amount of gas released when the measurement sample is subjected to TDS analysis is proportional to the integrated value of the ionic strength of the released gas.
  • the total amount of gas released can be calculated by comparison with a standard sample.
  • the amount of released oxygen molecules (N O2 ) of the measurement sample is obtained by the following formula: Can do.
  • the mass to charge ratio of CH 3 OH is 32 but is not considered here as it is unlikely to exist.
  • oxygen molecules containing oxygen atoms with a mass number of 17 and oxygen atoms with a mass number of 18 which are isotopes of oxygen atoms are not considered because the existence ratio in nature is extremely small.
  • N O2 N H2 / S H2 ⁇ S O2 ⁇ ⁇
  • N H2 is a value obtained by converting hydrogen molecules desorbed from the standard sample by density.
  • SH2 is an integral value of ion intensity when the standard sample is subjected to TDS analysis.
  • the reference value of the standard sample is N H2 / SH 2 .
  • S O2 is an integrated value of ion intensity when the measurement sample is subjected to TDS analysis.
  • ⁇ is a coefficient that affects the ionic strength in the TDS analysis.
  • the amount of released oxygen is measured using a temperature-programmed desorption analyzer EMD-WA1000S / W manufactured by Electronic Science Co., Ltd. and using a silicon substrate containing a certain amount of hydrogen atoms as a standard sample.
  • part of oxygen is detected as oxygen atoms.
  • the ratio of oxygen molecules to oxygen atoms can be calculated from the ionization rate of oxygen molecules. Note that since the above ⁇ includes the ionization rate of oxygen molecules, the amount of released oxygen atoms can be estimated by evaluating the amount of released oxygen molecules.
  • N 2 O 2 is the amount of released oxygen molecules.
  • the amount of release when converted to oxygen atoms is twice the amount of release of oxygen molecules.
  • the insulator from which oxygen is released by heat treatment may contain a peroxide radical.
  • a peroxide radical means that the spin density resulting from the peroxide radical is 5 ⁇ 10 17 spins / cm 3 or more.
  • an insulator containing a peroxide radical may have an asymmetric signal with a g value near 2.01 by an electron spin resonance (ESR) method.
  • the insulator 112 may have a function of preventing diffusion of impurities from the outside of the insulator 112.
  • the conductor 108a and the conductor 108b function as either a source electrode or a drain electrode of the transistor 10, respectively.
  • Examples of the conductor 108a and the conductor 108b include boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium,
  • a conductor including one or more of silver, indium, tin, tantalum, and tungsten may be used in a single layer or a stacked layer.
  • it may be an alloy or a compound, a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin and oxygen, a conductor containing titanium and nitrogen Etc. may be used.
  • the conductor 114 functions as a gate electrode of the transistor 10.
  • a conductor that can be used as the conductor 102 may be used.
  • the conductor 114 surrounds the semiconductor 106b, whereby a gate electric field can be applied from the entire periphery of the semiconductor 106b. Thereby, generation
  • DIBL Drain Induced Barrier Lowering
  • the DIBL effect is an effect of deterioration of subthreshold characteristics due to the influence of the application of the drain voltage and the reduction of the energy barrier at the junction between the source and the semiconductor. As the depletion layer width in the drain side region increases, the voltage drop in the source side region increases. In particular, when the channel length is short as in the transistor described in this embodiment, the effect is more significant and is sometimes referred to as a single-channel effect.
  • the spread of the drain-side depletion layer can be suppressed by applying a gate electric field from the entire periphery of the semiconductor 106b.
  • the transistor 10 can reduce the leakage current at the time of non-conduction, reduce the subthreshold swing value, and have normally-off electrical characteristics.
  • the oxide semiconductor used for the semiconductor 106b is a storage type, and the threshold voltage can be easily increased from 0 V even in a structure with a short channel length.
  • the transistor 10 described in this embodiment is provided with a conductor 102 functioning as a back gate, so that the threshold voltage can be easily controlled.
  • a transistor having resistance to a short channel effect can be provided.
  • a transistor having normally-off electrical characteristics can be provided.
  • a transistor with low leakage current when not conducting can be provided.
  • a transistor with a small subthreshold swing value can be provided.
  • a transistor having stable electrical characteristics can be provided in a microstructure with a short channel length.
  • FIGS. 2A to 2F and FIGS. 3A and 3B are similar to FIGS. 1B and 1C in which the cross-sectional view of the transistor in the channel length direction and the channel width of the transistor are shown. It becomes sectional drawing of a direction.
  • the cross-sectional shape in a cross section substantially perpendicular to the extending direction (A1-A2 direction) of the semiconductor 106b is a substantially circular shape; however, the semiconductor device described in this embodiment is not limited thereto.
  • the cross-sectional shape in a cross section substantially perpendicular to the extending direction (A1-A2 direction) of the semiconductor 106b may be a substantially polygonal shape.
  • a substantially polygon includes not only a strict polygon, such as a triangle and a quadrangle, but also a shape with rounded corners in a polygon, for example.
  • the cross-sectional shape in a cross section substantially perpendicular to the extending direction (A1-A2 direction) of the semiconductor 106b is a quadrangular shape with rounded corners.
  • the shapes of the insulator 106a, the insulator 112, and the conductor 114 in the same cross section correspond to the cross sectional shape of the semiconductor 106b.
  • the cross-sectional shape in a cross section substantially perpendicular to the extending direction (A1-A2 direction) of the semiconductor 106b is a triangular shape with rounded corners.
  • the shapes of the insulator 106a, the insulator 112, and the conductor 114 in the same cross section correspond to the cross sectional shape of the semiconductor 106b.
  • the transistor 10a and the transistor 10b an example in which a cross-sectional shape in a cross section substantially perpendicular to the extending direction (A1-A2 direction) of the semiconductor 106b is close to a regular polygon is shown; however, the semiconductor device described in this embodiment Is not limited to this.
  • the cross-sectional shape in a cross section substantially perpendicular to the extending direction (A1-A2 direction) of the semiconductor 106b is a hexagonal shape with rounded corners. You may make it a shape different from a regular hexagon.
  • the shapes of the insulator 106a, the insulator 112, and the conductor 114 in the same cross section correspond to the cross sectional shape of the semiconductor 106b.
  • the conductor 102 may be provided outside the conductor 114.
  • a plurality of nanowires including the semiconductor 106b, the insulator 106a, the insulator 112, and the conductor 102 are arranged so that the extending directions of the semiconductor 106b are parallel to each other.
  • the nanowires may be surrounded by one conductor 114. With such a configuration, a small on-current can be sufficiently increased with one nanowire.
  • FIG. 4A is a top view of the transistor 50.
  • 4B is a cross-sectional view corresponding to the dashed-dotted line B1-B2 in FIG. 4A
  • FIG. 4C is a cross-sectional view corresponding to the dashed-dotted line B3-B4 in FIG.
  • a region indicated by a dashed-dotted line B1-B2 indicates a structure in the channel length direction of the transistor 50
  • a region indicated by a dashed-dotted line B3-B4 indicates a structure in a direction perpendicular to the dashed-dotted line B1-B2.
  • part of the structure such as the insulator 162 is omitted in order to avoid the drawing from being complicated.
  • the transistor 50 includes an insulator 151 provided over the substrate 150. Further, an insulator 157 having an opening provided over the insulator 151 is provided. Further, a conductor 164a is provided in the opening so as to extend in the B3-B4 direction. Further, an insulator 162a is provided over the conductor 164a. Further, an insulator 162b having an opening provided over the insulator 162a is provided. Further, a conductor 152 provided to extend in the B1-B2 direction is provided in the opening formed in the insulator 162b. Further, an insulator 162c provided over the insulator 162b and the conductor 152 is provided. Further, an insulator 156a provided over the insulator 162c is provided.
  • the conductor 162c and the conductor 158d are provided over the insulator 162c with the insulator 156a interposed therebetween.
  • a semiconductor 156b provided in contact with the top surfaces of the insulator 156a, the conductor 158c, and the conductor 158d and extending in the B1-B2 direction is provided.
  • the semiconductor 156b includes a conductor 158a provided in contact with the top surface and side surfaces of the semiconductor 156b and the side surfaces of the conductor 158c so as to face the conductor 158b with the insulator 156c interposed therebetween.
  • the semiconductor 156b includes a conductor 158b which is in contact with the top surface and the side surface of the semiconductor 156b and the side surface of the conductor 158d and faces the conductor 158a with the insulator 156c interposed therebetween. Further, an insulator 167 is provided over the conductor 158a and the conductor 158b and has an opening between the conductor 158a and the conductor 158b. Further, the semiconductor 156b includes an insulator 156c provided in contact with an upper surface of the semiconductor 156b, side surfaces of the conductor 158a and the conductor 158b, and a side surface of the insulator 167. Further, an insulator 162d provided in contact with the upper surface of the insulator 156c is provided. Further, a conductor 164b provided in contact with the upper surface of the insulator 162d is provided.
  • the insulator 156a and the insulator 156c are provided so as to surround the semiconductor 156b, and the side end portions of the insulator 156a and the insulator 156c are substantially coincident with each other.
  • the insulator 162c and the insulator 162d are provided so as to surround the insulator 156a, the semiconductor 156b, and the insulator 156c, and the side edges of the insulator 162c and the insulator 162d are approximately one. I'm doing it.
  • the conductor 164a and the conductor 164b are provided so as to surround the insulators 162a to 162d.
  • the transistor 50 is provided corresponding to the transistor 10.
  • the semiconductor 156b corresponds to the semiconductor 106b, and a semiconductor that can be used as the above-described semiconductor 106b may be used.
  • the insulator 156a and the insulator 156c correspond to the insulator 106a, and an insulator or a semiconductor that can be used as the above-described insulator 106a may be used.
  • the insulators 162a to 162d correspond to the insulator 112, and an insulator that can be used as the above-described insulator 112 may be used.
  • the conductor 152 corresponds to the conductor 102, and a conductor that can be used as the above-described conductor 102 may be used.
  • the conductor 164a and the conductor 164b correspond to the conductor 114, and a conductor that can be used as the above-described conductor 114 may be used.
  • Transistor 50a is in that the inclination angle theta 2 of the end face portion of the inclined angle theta 1 and the insulator 167 of the side end portion of the conductor 158a (or conductor 158b) it does not match, different from the transistor 50.
  • the conductors 158a and a side end portion inclination angle ⁇ less than 1 30 ° or 90 ° of the conductor 158b is preferably preferably less than 45 ° or 80 °, more preferably to less than 45 ° or more and 60 ° or .
  • the inclination angle ⁇ 2 of the side surface end portion of the insulator 167 is larger than the inclination angle ⁇ 1 .
  • the distance between the conductors 158a and 158b can be further shortened, and the channel length L of the transistor 50a can be shortened. Can do.
  • the semiconductor 156b may have a region between the conductor 158a and the conductor 158b that is thinner than a region overlapping with the conductor 158a and the conductor 158b. This is formed by removing a part of the upper surface of the semiconductor 156b when the conductor 158a and the conductor 158b are formed. A low resistance region may be formed over the top surface of the semiconductor 156b when a conductor to be the conductor 158a and the conductor 158b is formed. In this manner, by removing the region located between the conductors 158a and 158b on the top surface of the semiconductor 156b, a channel can be prevented from being formed in the low resistance region on the top surface of the semiconductor 156b. Further, in the subsequent drawings, even when the thin region is not shown in an enlarged view or the like, a similar thin region may be formed.
  • the substrate 150 is prepared.
  • an insulator substrate, a semiconductor substrate, or a conductor substrate may be used.
  • the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria stabilized zirconia substrate), and a resin substrate.
  • the semiconductor substrate include a single semiconductor substrate such as silicon and germanium, or a semiconductor substrate such as silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide.
  • there is a semiconductor substrate having an insulator region inside the semiconductor substrate for example, an SOI (Silicon On Insulator) substrate.
  • the conductor substrate examples include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate.
  • a substrate having a metal nitride examples include a substrate having a metal oxide, and the like.
  • a substrate in which a conductor or a semiconductor is provided on an insulator substrate examples include a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate, and the like.
  • a substrate in which an element is provided may be used.
  • the element provided on the substrate include a capacitor element, a resistor element, a switch element, a light emitting element, and a memory element.
  • the substrate 150 a flexible substrate that can withstand heat treatment at the time of manufacturing the transistor may be used.
  • a method for providing a transistor over a flexible substrate there is a method in which after a transistor is manufactured over a non-flexible substrate, the transistor is peeled and transferred to the substrate 150 which is a flexible substrate.
  • a separation layer is preferably provided between the non-flexible substrate and the transistor.
  • the substrate 150 may be a sheet, a film, a foil, or the like in which fibers are knitted.
  • the substrate 150 may have elasticity.
  • the substrate 150 may have a property of returning to its original shape when bending or pulling is stopped. Or you may have a property which does not return to an original shape.
  • the thickness of the substrate 150 is, for example, 5 ⁇ m to 700 ⁇ m, preferably 10 ⁇ m to 500 ⁇ m, and more preferably 15 ⁇ m to 300 ⁇ m.
  • the semiconductor device can be reduced in weight.
  • the substrate 150 may have elasticity even when glass or the like is used, or may have a property of returning to its original shape when bending or pulling is stopped. Therefore, an impact applied to the semiconductor device on the substrate 150 due to a drop or the like can be reduced. That is, a durable semiconductor device can be provided.
  • the substrate 150 that is a flexible substrate for example, a metal, an alloy, a resin, glass, or fiber thereof can be used.
  • the substrate 150, which is a flexible substrate is preferable as the linear expansion coefficient is lower because deformation due to the environment is suppressed.
  • a material having a linear expansion coefficient of 1 ⁇ 10 ⁇ 3 / K or less, 5 ⁇ 10 ⁇ 5 / K or less, or 1 ⁇ 10 ⁇ 5 / K or less is used as the substrate 150 that is a flexible substrate.
  • the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic.
  • aramid has a low coefficient of linear expansion, it is suitable for the substrate 150 that is a flexible substrate.
  • the insulator 151 is formed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD: Pulsed Laser Deposition) method, or an atomic layer.
  • the deposition can be performed using an ALD (Atomic Layer Deposition) method or the like.
  • an insulator having a function of blocking hydrogen or water is used as the insulator 151.
  • Hydrogen or water in the insulator provided in the vicinity of the insulator 156a and the semiconductor 156b is one of the factors that generate carriers in the insulator 156a and the semiconductor 156b.
  • the reliability of the transistor 50 may be reduced.
  • a substrate provided with a silicon-based semiconductor element such as a switch element is used as the substrate 150
  • hydrogen is used to terminate dangling bonds of the semiconductor element, and the hydrogen may diffuse to the transistor 50.
  • the insulator 151 having a function of blocking hydrogen or water diffusion of hydrogen or water from the lower layer of the transistor 10 can be suppressed, and the reliability of the transistor 50 can be improved.
  • the insulator 151 preferably has a function of blocking oxygen.
  • oxygen can be effectively supplied from the insulator 162c and the insulator 162d to the insulator 156a and the semiconductor 156b.
  • the insulator 151 for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, or the like can be used. By using these as the insulator 151, the insulator 151 can function as an insulating film having an effect of blocking diffusion of oxygen, hydrogen, or water. As the insulator 151 , for example, silicon nitride, silicon nitride oxide, or the like can be used. By using these as the insulator 151, the insulator 151 can function as an insulating film having an effect of blocking diffusion of hydrogen and water.
  • an insulator to be the insulator 157 is formed.
  • an insulator that can be used as the above-described insulator 112 may be used.
  • the insulator can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a resist or the like is formed over the insulator and processed using the resist or the like to form the insulator 157 having an opening.
  • the resist is removed after the object is processed by etching or the like.
  • plasma treatment and / or wet etching is used for the removal of the resist. Note that plasma ashing is preferable as the plasma treatment. If the removal of the resist or the like is insufficient, the remaining resist or the like may be removed with hydrofluoric acid or / and ozone water having a concentration of 0.001 volume% or more and 1 volume% or less.
  • a conductor to be the conductor 164a is formed.
  • the conductor to be the conductor 164a the above-described conductor can be used.
  • the conductor can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.
  • polishing can be performed by a CMP process or the like.
  • an insulator 162e to be an insulator 162a in a later step is formed.
  • an insulator that can be used as the above-described insulator 112 may be used.
  • the insulator 162e can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • an insulator to be an insulator 162b is formed in a later step.
  • an insulator that can be used as the above-described insulator 112 may be used.
  • the insulator can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a resist or the like is formed over the insulator and processed using the resist or the like to form an insulator 162f having an opening.
  • a conductor to be the conductor 152 is formed.
  • a conductor that can be used as the above-described conductor 102 may be used.
  • the conductor can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.
  • polishing can be performed by a CMP process or the like.
  • an insulator 162g which becomes an insulator 162c in a later step, is formed.
  • an insulator that can be used as the above-described insulator 112 may be used.
  • the insulator 162g can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Alternatively, film formation may be performed while heating the substrate in order to reduce water or hydrogen contained in the insulator 162g.
  • the heat treatment By performing the heat treatment, water or hydrogen contained in the insulator 162g or the like can be further reduced. In some cases, the insulator 162g can be provided with excess oxygen.
  • the heat treatment may be performed at 250 ° C to 650 ° C, preferably 450 ° C to 600 ° C, more preferably 520 ° C to 570 ° C.
  • the heat treatment is performed in an inert gas atmosphere or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more.
  • the heat treatment may be performed in a reduced pressure state.
  • the heat treatment may be performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more in order to supplement the desorbed oxygen after the heat treatment in an inert gas atmosphere.
  • an RTA apparatus using lamp heating can also be used. The heat treatment by the RTA apparatus is effective for improving productivity because it takes a shorter time than a furnace.
  • an insulator to be the insulator 156a is formed in a later step and processed using a resist or the like to form the insulator 156d (see FIGS. 5E and 5F).
  • an insulator, a semiconductor, or the like that can be used as the above-described insulator 106a may be used.
  • the insulator can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a conductor to be the conductor 158c and the conductor 158d is formed in a later step, and the conductor is polished until the insulator 156d is exposed, so that the conductor 158e and the conductor 158f are formed (FIG. 5).
  • G See (H).
  • Polishing can be performed by a CMP process or the like.
  • As the conductor 158e and the conductor 158f a conductor that can be used for the conductor 108a and the conductor 108b described above may be used.
  • the conductor can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.
  • a semiconductor to be the semiconductor 156b is formed.
  • a semiconductor that can be used as the above-described semiconductor 106b may be used.
  • the semiconductor can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • heat treatment By performing heat treatment, water or hydrogen in the semiconductor to be the semiconductor 156b, the insulator 156d, or the insulator 162g can be further reduced. In some cases, the insulator 162g can be provided with excess oxygen.
  • the heat treatment may be performed at 250 ° C to 650 ° C, preferably 450 ° C to 600 ° C, more preferably 520 ° C to 570 ° C.
  • the heat treatment is performed in an inert gas atmosphere or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more.
  • the heat treatment may be performed in a reduced pressure state.
  • the heat treatment may be performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more in order to supplement the desorbed oxygen after the heat treatment in an inert gas atmosphere.
  • an oxidizing gas 10 ppm or more, 1% or more, or 10% or more
  • the crystallinity of the semiconductor to be the insulator 156d and the semiconductor 156b can be increased, or impurities such as hydrogen and water can be removed.
  • an RTA apparatus using lamp heating can also be used. The heat treatment by the RTA apparatus is effective for improving productivity because it takes a shorter time than a furnace.
  • a resist or the like is formed over the semiconductor, and the semiconductor 156b is formed by processing using the resist or the like. Then, a resist or the like is formed over the conductor 158e and the conductor 158f and processed using the resist or the like to form the conductor 158c and the conductor 158d (see FIGS. 6A and 6B).
  • the semiconductor 156b it is preferable to perform heat treatment after the semiconductor 156b is formed.
  • heat treatment water or hydrogen in the semiconductor 156b, the insulator 156d, or the insulator 162g can be further reduced.
  • the insulator 162g can be provided with excess oxygen.
  • the heat treatment may be performed at 250 ° C to 650 ° C, preferably 450 ° C to 600 ° C, more preferably 520 ° C to 570 ° C.
  • the heat treatment is performed in an inert gas atmosphere or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more.
  • the heat treatment may be performed in a reduced pressure state.
  • the heat treatment may be performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more in order to supplement the desorbed oxygen after the heat treatment in an inert gas atmosphere.
  • an oxidizing gas 10 ppm or more, 1% or more, or 10% or more
  • crystallinity of the insulator 156d and the semiconductor 156b can be increased, impurities such as hydrogen and water can be removed, and the like.
  • an RTA apparatus using lamp heating can also be used. The heat treatment by the RTA apparatus is effective for improving productivity because it takes a shorter time than a furnace.
  • high-density plasma treatment may be performed.
  • the high density plasma may be generated using microwaves.
  • an oxidizing gas such as oxygen or nitrous oxide may be used.
  • a mixed gas of an oxidizing gas and a rare gas such as He, Ar, Kr, or Xe may be used.
  • a bias may be applied to the substrate.
  • oxygen ions or the like in the plasma can be drawn to the substrate side.
  • the high density plasma treatment may be performed while heating the substrate.
  • high-density plasma treatment may be performed before the formation of the insulator 156d, may be performed after the opening of the insulator 167 described later, or may be performed after the formation of the insulator 156f described later.
  • a conductor to be the conductor 158a and the conductor 158b is formed.
  • a resist or the like is formed over the conductor and processed using the resist or the like to form the conductor in an island shape.
  • a conductor that can be used as the conductor 108a and the conductor 108b described above may be used.
  • the conductor can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.
  • an insulator to be the insulator 167 is formed.
  • an insulator that can be used as the above-described insulator 112 may be used.
  • the insulator can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a resist or the like is formed over the insulator and processed using the resist or the like to form the insulator 167, the conductor 158a, and the conductor 158b (see FIGS. 6C and 6D).
  • an insulator 156e to be an insulator 156c in a later step is formed (see FIGS. 6E and 6F).
  • an insulator, a semiconductor, or the like that can be used as the above-described insulator 106a may be used.
  • the insulator 156e can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a resist or the like is formed over the insulator 156e and processed using the resist or the like to form the insulator 156f and the insulator 156a (see FIGS. 7A and 7B).
  • the side end portions in the B3-B4 direction of the insulator 156f and the insulator 156a are formed so as to substantially coincide with each other.
  • an insulator to be an insulator 162d is formed in a later step.
  • an insulator, a semiconductor, or the like that can be used as the above-described insulator 112 may be used.
  • the insulator can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a resist or the like is formed over the insulator and processed using the resist or the like to form the insulator 162a, the insulator 162b, the insulator 162c, and the insulator 162h (see FIGS. 7C and 7D). .)
  • the side end portions in the B3-B4 direction of the insulator 162a, the insulator 162b, the insulator 162c, and the insulator 162h are formed so as to substantially coincide with each other.
  • a conductor to be the conductor 164b is formed.
  • a conductor that can be used as the above-described conductor 114 may be used.
  • the conductor can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.
  • the conductor 164b and the insulator 162d function as a gate electrode and a gate insulator of the transistor 50, respectively.
  • the conductor 164b and the insulator 162d can be formed in a self-aligning manner.
  • an insulator that functions as a protective insulating film may be formed.
  • An insulator that can be used as the above-described insulator 151 may be used as the insulator.
  • the insulator can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • oxygen can be added to the vicinity of the surfaces of the insulator 162d and the insulator 167 at the same time as the film formation.
  • oxygen added to the insulator 162c, the insulator 162d, and the insulator 167 can be diffused and supplied to the insulator 156a, the semiconductor 156b, and the insulator 156c.
  • the transistor according to one embodiment of the present invention can be manufactured.
  • An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single crystal oxide semiconductor.
  • a CAAC-OS c-axis-aligned crystal oxide semiconductor
  • a polycrystalline oxide semiconductor a polycrystalline oxide semiconductor
  • an nc-OS nanocrystalline oxide semiconductor
  • a pseudo-amorphous oxide semiconductor a-like oxide OS
  • amorphous oxide semiconductor amorphous-like oxide semiconductor
  • oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxide semiconductors.
  • a crystalline oxide semiconductor include a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and an nc-OS.
  • Amorphous structures are generally isotropic, have no heterogeneous structure, are metastable, have no fixed atomic arrangement, have a flexible bond angle, have short-range order, but long-range order It is said that it does not have.
  • a stable oxide semiconductor cannot be called a complete amorphous oxide semiconductor.
  • an oxide semiconductor that is not isotropic (for example, has a periodic structure in a minute region) cannot be called a complete amorphous oxide semiconductor.
  • an a-like OS is not isotropic but has an unstable structure having a void (also referred to as a void). In terms of being unstable, a-like OS is physically similar to an amorphous oxide semiconductor.
  • CAAC-OS First, the CAAC-OS will be described.
  • CAAC-OS is a kind of oxide semiconductor having a plurality of c-axis aligned crystal parts (also referred to as pellets).
  • CAAC-OS is analyzed by X-ray diffraction (XRD: X-Ray Diffraction)
  • XRD X-ray Diffraction
  • CAAC-OS having an InGaZnO 4 crystal classified into the space group R-3m is subjected to structural analysis by an out-of-plane method
  • a diffraction angle (2 ⁇ ) as illustrated in FIG. Shows a peak near 31 °. Since this peak is attributed to the (009) plane of the InGaZnO 4 crystal, in CAAC-OS, the crystal has a c-axis orientation, and the plane on which the c-axis forms a CAAC-OS film (formation target) It can also be confirmed that it faces a direction substantially perpendicular to the upper surface.
  • a peak may also appear when 2 ⁇ is around 36 °.
  • the peak where 2 ⁇ is around 36 ° is attributed to the crystal structure classified into the space group Fd-3m. Therefore, the CAAC-OS preferably does not show the peak.
  • FIG. 11E shows a diffraction pattern obtained when an electron beam with a probe diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample surface. From FIG. 11E, a ring-shaped diffraction pattern is confirmed. Therefore, it can be seen that the a-axis and the b-axis of the pellet included in the CAAC-OS have no orientation even by electron diffraction using an electron beam with a probe diameter of 300 nm. Note that the first ring in FIG. 11E is considered to originate from the (010) plane and the (100) plane of the InGaZnO 4 crystal. Further, it is considered that the second ring in FIG. 11E is caused by the (110) plane or the like.
  • a composite analysis image also referred to as a high-resolution TEM image
  • TEM Transmission Electron Microscope
  • a plurality of pellets are confirmed. Can do.
  • the boundary between pellets that is, a crystal grain boundary (also referred to as a grain boundary) may not be clearly confirmed. Therefore, it can be said that the CAAC-OS does not easily lower the electron mobility due to the crystal grain boundary.
  • FIG. 12A shows a high-resolution TEM image of a cross section of the CAAC-OS observed from a direction substantially parallel to the sample surface.
  • a spherical aberration correction function was used for observation of the high-resolution TEM image.
  • a high-resolution TEM image using the spherical aberration correction function is particularly referred to as a Cs-corrected high-resolution TEM image.
  • the Cs-corrected high resolution TEM image can be observed, for example, with an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.
  • a pellet which is a region where metal atoms are arranged in layers can be confirmed. It can be seen that the size of one pellet is 1 nm or more and 3 nm or more. Therefore, the pellet can also be referred to as a nanocrystal (nc).
  • the CAAC-OS can also be referred to as an oxide semiconductor including CANC (C-Axis aligned nanocrystals).
  • CANC C-Axis aligned nanocrystals.
  • the pellet reflects the unevenness of the surface or top surface of the CAAC-OS film, and is parallel to the surface or top surface of the CAAC-OS.
  • FIGS. 12B and 12C show Cs-corrected high-resolution TEM images of the plane of the CAAC-OS observed from a direction substantially perpendicular to the sample surface.
  • FIGS. 12D and 12E are images obtained by performing image processing on FIGS. 12B and 12C, respectively.
  • an image processing method will be described.
  • an FFT image is acquired by performing a Fast Fourier Transform (FFT) process on FIG.
  • FFT-processed mask image is subjected to an inverse fast Fourier transform (IFFT) process to obtain an image-processed image.
  • IFFT inverse fast Fourier transform
  • the image acquired in this way is called an FFT filtered image.
  • the FFT filtered image is an image obtained by extracting periodic components from the Cs-corrected high-resolution TEM image, and shows a lattice arrangement.
  • FIG. 12D the portion where the lattice arrangement is disturbed is indicated by a broken line.
  • a region surrounded by a broken line is one pellet.
  • the location shown with the broken line is the connection part of a pellet and a pellet. Since the broken line has a hexagonal shape, it can be seen that the pellet has a hexagonal shape.
  • the shape of a pellet is not necessarily a regular hexagonal shape, and is often a non-regular hexagonal shape.
  • FIG. 12 (E) a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangement is aligned and a region where another lattice arrangement is aligned is indicated by a dotted line, and the change in the orientation of the lattice arrangement is shown. It is indicated by a broken line.
  • a clear crystal grain boundary cannot be confirmed even in the vicinity of the dotted line.
  • the CAAC-OS has a c-axis orientation and a crystal structure in which a plurality of pellets (nanocrystals) are connected in the ab plane direction and have a strain. Therefore, the CAAC-OS can also be referred to as CAA crystal (c-axis-aligned ab-plane-anchored crystal).
  • CAAC-OS is an oxide semiconductor with high crystallinity. Since the crystallinity of an oxide semiconductor may be deteriorated by entry of impurities, generation of defects, or the like, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies).
  • the impurity means an element other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element.
  • an element such as silicon which has a stronger bonding force with oxygen than a metal element included in an oxide semiconductor, disturbs the atomic arrangement of the oxide semiconductor by depriving the oxide semiconductor of oxygen, thereby reducing crystallinity. It becomes a factor.
  • heavy metals such as iron and nickel, argon, carbon dioxide, and the like have large atomic radii (or molecular radii), which disturbs the atomic arrangement of the oxide semiconductor and decreases crystallinity.
  • an impurity contained in the oxide semiconductor might serve as a carrier trap or a carrier generation source.
  • oxygen vacancies in the oxide semiconductor may serve as carrier traps or may serve as carrier generation sources by capturing hydrogen.
  • a CAAC-OS with few impurities and oxygen vacancies is an oxide semiconductor with low carrier density. Specifically, it is less than 8 ⁇ 10 11 pieces / cm 3 , preferably less than 1 ⁇ 10 11 pieces / cm 3 , more preferably less than 1 ⁇ 10 10 pieces / cm 3 , and 1 ⁇ 10 ⁇ 9 pieces / cm 3.
  • An oxide semiconductor having a carrier density of 3 or more can be obtained. Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.
  • the CAAC-OS has a low impurity concentration and a low density of defect states. That is, it can be said that the oxide semiconductor has stable characteristics.
  • nc-OS is analyzed by XRD.
  • XRD X-ray diffraction
  • FIG. 13B shows a diffraction pattern (nanobeam electron diffraction pattern) when an electron beam with a probe diameter of 1 nm is incident on the same sample. From FIG. 13B, a plurality of spots are observed in the ring-shaped region. Therefore, nc-OS does not confirm order when an electron beam with a probe diameter of 50 nm is incident, but confirms order when an electron beam with a probe diameter of 1 nm is incident.
  • the nc-OS has a highly ordered region, that is, a crystal in a thickness range of less than 10 nm. Note that there are some regions where a regular electron diffraction pattern is not observed because the crystal faces in various directions.
  • FIG. 13D shows a Cs-corrected high-resolution TEM image of a cross section of the nc-OS observed from a direction substantially parallel to the formation surface.
  • the nc-OS has a region in which a crystal part can be confirmed, such as a portion indicated by an auxiliary line, and a region in which a clear crystal part cannot be confirmed in a high-resolution TEM image.
  • a crystal part included in the nc-OS has a size of 1 nm to 10 nm, particularly a size of 1 nm to 3 nm in many cases. Note that an oxide semiconductor in which the size of a crystal part is greater than 10 nm and less than or equal to 100 nm is sometimes referred to as a microcrystalline oxide semiconductor.
  • the nc-OS may not be able to clearly confirm a crystal grain boundary in a high-resolution TEM image.
  • the nanocrystal may have the same origin as the pellet in the CAAC-OS. Therefore, the crystal part of nc-OS is sometimes referred to as a pellet below.
  • nc-OS has periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm).
  • the nc-OS has no regularity in crystal orientation between different pellets. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS may not be distinguished from an a-like OS or an amorphous oxide semiconductor depending on an analysis method.
  • nc-OS is an oxide semiconductor having RANC (Random Aligned nanocrystals), or an oxide having NANC (Non-Aligned nanocrystals). It can also be called a semiconductor.
  • Nc-OS is an oxide semiconductor having higher regularity than an amorphous oxide semiconductor. Therefore, the nc-OS has a lower density of defect states than an a-like OS or an amorphous oxide semiconductor. Note that the nc-OS does not have regularity in crystal orientation between different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.
  • the a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor.
  • FIG. 14 shows a high-resolution cross-sectional TEM image of the a-like OS.
  • FIG. 14A is a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation.
  • FIG. 14B is a high-resolution cross-sectional TEM image of the a-like OS after irradiation with electrons (e ⁇ ) of 4.3 ⁇ 10 8 e ⁇ / nm 2 .
  • electrons (e ⁇ ) of 4.3 ⁇ 10 8 e ⁇ / nm 2 .
  • the a-like OS Since it has a void, the a-like OS has an unstable structure.
  • the a-like OS has an unstable structure as compared with the CAAC-OS and the nc-OS, a change in structure due to electron irradiation is shown.
  • Each sample is an In—Ga—Zn oxide.
  • a high-resolution cross-sectional TEM image of each sample is acquired.
  • Each sample has a crystal part by a high-resolution cross-sectional TEM image.
  • a unit cell of an InGaZnO 4 crystal has a structure in which three In—O layers and six Ga—Zn—O layers have a total of nine layers stacked in the c-axis direction.
  • the spacing between these adjacent layers is about the same as the lattice spacing (also referred to as d value) of the (009) plane, and the value is determined to be 0.29 nm from crystal structure analysis. Therefore, in the following, a portion where the interval between lattice fringes is 0.28 nm or more and 0.30 nm or less is regarded as a crystal part of InGaZnO 4 .
  • the lattice fringes correspond to the ab plane of the InGaZnO 4 crystal.
  • FIG. 15 is an example in which the average size of the crystal parts (from 22 to 30) of each sample was examined. Note that the length of the lattice stripes described above is the size of the crystal part. From FIG. 15, it can be seen that in the a-like OS, the crystal part becomes larger in accordance with the cumulative dose of electrons related to acquisition of the TEM image or the like. From FIG. 15, the crystal part (also referred to as the initial nucleus), which was about 1.2 nm in the initial observation by TEM, has a cumulative electron (e ⁇ ) irradiation dose of 4.2 ⁇ 10 8 e ⁇ / nm. In FIG. 2 , it can be seen that the crystal has grown to a size of about 1.9 nm.
  • FIG. 15 shows that the crystal part sizes of the nc-OS and the CAAC-OS are approximately 1.3 nm and 1.8 nm, respectively, regardless of the cumulative electron dose.
  • a Hitachi transmission electron microscope H-9000NAR was used for electron beam irradiation and TEM observation.
  • the electron beam irradiation conditions were an acceleration voltage of 300 kV, a current density of 6.7 ⁇ 10 5 e ⁇ / (nm 2 ⁇ s), and an irradiation region diameter of 230 nm.
  • the crystal part may be grown by electron irradiation.
  • the crystal part is hardly grown by electron irradiation. That is, it can be seen that the a-like OS has an unstable structure as compared with the nc-OS and the CAAC-OS.
  • the a-like OS has a structure with a lower density than the nc-OS and the CAAC-OS. Specifically, the density of the a-like OS is 78.6% or more and less than 92.3% of the density of the single crystal having the same composition. Further, the density of the nc-OS and the density of the CAAC-OS are 92.3% or more and less than 100% of the density of the single crystal having the same composition. An oxide semiconductor having a density of less than 78% of the single crystal is difficult to form.
  • the density of single crystal InGaZnO 4 having a rhombohedral structure is 6.357 g / cm 3 .
  • the density of a-like OS is 5.0 g / cm 3 or more and less than 5.9 g / cm 3.
  • the density of the nc-OS and the density of the CAAC-OS is 5.9 g / cm 3 or more and 6.3 g / less than cm 3 .
  • the density corresponding to the single crystal having a desired composition can be estimated by combining single crystals having different compositions at an arbitrary ratio. What is necessary is just to estimate the density corresponding to the single crystal of a desired composition using a weighted average with respect to the ratio which combines the single crystal from which a composition differs. However, the density is preferably estimated by combining as few kinds of single crystals as possible.
  • oxide semiconductors have various structures and various properties.
  • the oxide semiconductor may be a stacked film including two or more of an amorphous oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS, for example.
  • FIG. 16A shows a structure of a so-called CMOS inverter in which a p-channel transistor 2200 and an n-channel transistor 2100 are connected in series and their gates are connected.
  • a p-channel transistor is manufactured using a semiconductor substrate, and an n-channel transistor is formed thereabove, whereby the area occupied by the element can be reduced. That is, the degree of integration of the semiconductor device can be increased. Further, since the process can be simplified as compared with the case where an n-channel transistor and a p-channel transistor are formed using the same semiconductor substrate, the productivity of the semiconductor device can be increased. In addition, the yield of the semiconductor device can be increased. In addition, a p-channel transistor can sometimes omit complicated processes such as an LDD (Lightly Doped Drain) region, a shallow trench structure, and a strain design. Therefore, productivity and yield may be increased as compared with the case where an n-channel transistor is manufactured using a semiconductor substrate.
  • LDD Lightly Doped Drain
  • FIG. 16B illustrates a structure in which the sources and drains of the transistors 2100 and 2200 are connected to each other. With such a configuration, it can function as a so-called CMOS analog switch.
  • FIG. 17 illustrates an example of a semiconductor device (memory device) using the transistor according to one embodiment of the present invention, which can hold stored data even in a state where power is not supplied and has no limitation on the number of writing times.
  • the semiconductor device illustrated in FIG. 17A includes a transistor 3200 using a first semiconductor, a transistor 3300 using a second semiconductor, and a capacitor 3400. Note that as the transistor 3300, a transistor similar to the above-described transistor 2100 can be used.
  • the transistor 3300 is preferably a transistor with a low off-state current.
  • a transistor including an oxide semiconductor can be used. Since the off-state current of the transistor 3300 is small, stored data can be held in a specific node of the semiconductor device for a long time. That is, a refresh operation is not required or the frequency of the refresh operation can be extremely low, so that the semiconductor device with low power consumption is obtained.
  • the first wiring 3001 is electrically connected to the source of the transistor 3200
  • the second wiring 3002 is electrically connected to the drain of the transistor 3200
  • the third wiring 3003 is electrically connected to one of a source and a drain of the transistor 3300
  • the fourth wiring 3004 is electrically connected to the gate of the transistor 3300.
  • the gate of the transistor 3200 and the other of the source and the drain of the transistor 3300 are electrically connected to one of the electrodes of the capacitor 3400
  • the fifth wiring 3005 is electrically connected to the other of the electrodes of the capacitor 3400.
  • the semiconductor device illustrated in FIG. 17A has a characteristic that the potential of the gate of the transistor 3200 can be held, so that information can be written, held, and read as described below.
  • the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned on, so that the transistor 3300 is turned on. Accordingly, the potential of the third wiring 3003 is supplied to the node FG electrically connected to one of the gate of the transistor 3200 and the electrode of the capacitor 3400. That is, predetermined charge is supplied to the gate of the transistor 3200 (writing).
  • predetermined charge is supplied to the gate of the transistor 3200 (writing).
  • the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned off and the transistor 3300 is turned off, so that charge is held at the node FG (holding).
  • the second wiring 3002 has a charge held in the node FG. Take a potential according to the amount. This is because, when the transistor 3200 is an n-channel type, the apparent threshold voltage V th_H when a high level charge is applied to the gate of the transistor 3200 is the low level charge applied to the gate of the transistor 3200. This is because it becomes lower than the apparent threshold voltage V th_L in the case of being present.
  • the apparent threshold voltage refers to the potential of the fifth wiring 3005 necessary for bringing the transistor 3200 into a “conducting state”.
  • the potential of the fifth wiring 3005 can be set to a potential V 0 between V th_H and V th_L .
  • the transistor 3200 is in a “conducting state” if the potential of the fifth wiring 3005 is V 0 (> V th_H ).
  • the transistor 3200 remains in the “non-conductive state” even when the potential of the fifth wiring 3005 becomes V 0 ( ⁇ V th_L ). Therefore, by determining the potential of the second wiring 3002, information held in the node FG can be read.
  • the fifth wiring 3005 is supplied with a potential at which the transistor 3200 is in a “non-conducting state” regardless of the charge applied to the node FG, that is, a potential lower than V th_H. Thus, only a desired memory cell information may be read.
  • the fifth wiring 3005 is supplied with a potential at which the transistor 3200 becomes “conductive” regardless of the charge applied to the node FG, that is, a potential higher than V th_L. Thus, only the desired memory cell information may be read.
  • the semiconductor device according to the present invention is not limited to this.
  • a structure in which three or more kinds of electric charges can be held in the node FG of the semiconductor device may be employed. With such a structure, the semiconductor device can be multi-valued and the storage capacity can be increased.
  • the semiconductor device illustrated in FIG. 17B is different from the semiconductor device illustrated in FIG. 17A in that the transistor 3200 is not provided. In this case as well, information writing and holding operations can be performed by operations similar to those of the semiconductor device illustrated in FIG.
  • the potential of one electrode of the capacitor 3400 is V
  • the capacitance of the capacitor 3400 is C
  • the capacitance component of the third wiring 3003 is CB
  • the potential of the third wiring 3003 before the charge is redistributed is (CB ⁇ VB0 + CV) / (CB + C). Therefore, if the potential of one of the electrodes of the capacitor 3400 assumes two states of V1 and V0 (V1> V0) as the state of the memory cell, the third wiring 3003 in the case where the potential V1 is held.
  • information can be read by comparing the potential of the third wiring 3003 with a predetermined potential.
  • a transistor to which the first semiconductor is applied is used as a driver circuit for driving the memory cell, and a transistor to which the second semiconductor is applied is stacked over the driver circuit as the transistor 3300. do it.
  • memory contents can be held for a long time by using a transistor with an off-state current that is formed using an oxide semiconductor. That is, a refresh operation is unnecessary or the frequency of the refresh operation can be extremely low, so that a semiconductor device with low power consumption can be realized.
  • stored data can be held for a long time even when power is not supplied (note that a potential is preferably fixed).
  • the semiconductor device since the semiconductor device does not require a high voltage for writing information, the element is hardly deteriorated.
  • the semiconductor device according to one embodiment of the present invention is a semiconductor device in which the number of rewritable times which is a problem in the conventional nonvolatile memory is not limited and the reliability is drastically improved. Further, since data is written depending on the conductive state and non-conductive state of the transistor, high-speed operation is possible.
  • ⁇ Storage device 3> A modified example of the semiconductor device (memory device) illustrated in FIG. 17A is described with reference to a circuit diagram illustrated in FIG.
  • the semiconductor device illustrated in FIG. 18 includes transistors 4100 to 4400, a capacitor 4500, and a capacitor 4600.
  • the transistor 4100 can be a transistor similar to the above-described transistor 3200, and the transistors 4200 to 4400 can be the same transistor as the above-described transistor 3300.
  • the semiconductor device illustrated in FIG. 18 is not illustrated in FIG. 18, but a plurality of semiconductor devices are provided in a matrix.
  • the semiconductor device illustrated in FIG. 18 can control writing and reading of a data voltage in accordance with a signal or a potential supplied to the wiring 4001, the wiring 4003, and the wirings 4005 to 4009.
  • One of the source and the drain of the transistor 4100 is connected to the wiring 4003.
  • the other of the source and the drain of the transistor 4100 is connected to the wiring 4001. Note that although the conductivity type of the transistor 4100 is shown as a p-channel type in FIG. 18, it may be an n-channel type.
  • the semiconductor device shown in FIG. 18 has two data holding units.
  • the first data holding portion holds charge between one of a source and a drain of the transistor 4400 connected to the node FG1, one electrode of the capacitor 4600, and one of the source and the drain of the transistor 4200.
  • the second data holding portion is between the gate of the transistor 4100 connected to the node FG2, the other of the source and the drain of the transistor 4200, one of the source and the drain of the transistor 4300, and one electrode of the capacitor 4500. Holds charge.
  • the other of the source and the drain of the transistor 4300 is connected to the wiring 4003.
  • the other of the source and the drain of the transistor 4400 is connected to the wiring 4001.
  • a gate of the transistor 4400 is connected to the wiring 4005.
  • a gate of the transistor 4200 is connected to the wiring 4006.
  • a gate of the transistor 4300 is connected to the wiring 4007.
  • the other electrode of the capacitor 4600 is connected to the wiring 4008.
  • the other electrode of the capacitor 4500 is connected to the wiring 4009.
  • the transistors 4200 to 4400 have a function as a switch for controlling data voltage writing and charge holding.
  • transistors with low current (off-state current) flowing between the source and the drain in a non-conduction state are preferably used as the transistors 4200 to 4400.
  • the transistor with low off-state current is preferably a transistor having an oxide semiconductor in a channel formation region (OS transistor).
  • An OS transistor has advantages such as low off-state current and that it can be formed over a transistor including silicon.
  • the conductivity types of the transistors 4200 to 14 are illustrated as n-channel types, but may be p-channel types.
  • the transistor 4200, the transistor 4300, and the transistor 4400 are preferably provided in different layers even if a transistor including an oxide semiconductor is used. That is, the semiconductor device illustrated in FIG. 18 includes a first layer 4021 including a transistor 4100, a second layer 4022 including a transistor 4200 and a transistor 4300, and a third layer including a transistor 4400 as illustrated in FIG. 4023. By stacking layers including transistors, the circuit area can be reduced and the semiconductor device can be downsized.
  • a data voltage write operation (hereinafter referred to as a write operation 1) to the data holding portion connected to the node FG1 will be described. Note that in the following description, the data voltage written to the data holding portion connected to the node FG1 is V D1, and the threshold voltage of the transistor 4100 is Vth.
  • the wiring 4001 is electrically floated.
  • the wirings 4005 and 4006 are set to a high level.
  • the wirings 4007 to 4009 are set to a low level. Then, the potential of the node FG2 which is in an electrically floating state is increased, and a current flows through the transistor 4100. When the current flows, the potential of the wiring 4001 increases. In addition, the transistors 4400 and 4200 are turned on. Therefore, the potentials of the nodes FG1 and FG2 increase as the potential of the wiring 4001 increases.
  • V D1 applied to the wiring 4003 is supplied to the wiring 4001 when current flows through the transistor 4100, so that the potentials of the nodes FG1 and FG2 are increased.
  • Vgs of the transistor 4100 becomes Vth, so that the current stops.
  • writing operation 2 a data voltage writing operation (hereinafter referred to as writing operation 2) to the data holding portion connected to the node FG2 will be described.
  • writing operation 2 illustrating a data voltage to be written to the data holding unit connected to the node FG2 as V D2.
  • the wiring 4001 is electrically floated. Further, the wiring 4007 is set to a high level. In addition, the wirings 4005, 4006, 4008, and 4009 are set to a low level.
  • the transistor 4300 is turned on and the wiring 4003 is set to a low level. Therefore, the potential of the node FG2 also decreases to a low level, and a current flows through the transistor 4100. When the current flows, the potential of the wiring 4003 increases. In addition, the transistor 4300 is turned on. Therefore, the potential of the node FG2 increases as the potential of the wiring 4003 increases.
  • V D2 applied to the wiring 4001 is supplied to the wiring 4003 when a current flows through the transistor 4100, so that the potential of the node FG2 increases.
  • Vgs of the transistor 4100 becomes Vth, so that the current stops.
  • the potential of the node FG1 is non-conductive in the transistors 4200 and 4400, and “V D1 ⁇ Vth” written in the writing operation 1 is held.
  • the wiring 4009 is set to a high level and the potentials of the nodes FG1 and FG2 are increased. Then, each transistor is brought into a non-conducting state to eliminate the movement of electric charges and to hold the written data voltage.
  • V D1 ⁇ Vth and “V D2 ⁇ Vth” have been described as examples of potentials to be written, these are data voltages corresponding to multi-value data. Therefore, when 4-bit data is held in each data holding unit, 16 values of “V D1 ⁇ Vth” and “V D2 ⁇ Vth” can be taken.
  • read operation 1 a data voltage read operation (hereinafter referred to as read operation 1) to the data holding unit connected to the node FG2 will be described.
  • the wiring 4003 that has been electrically floated after precharging is discharged.
  • the wirings 4005 to 4008 are set to a low level.
  • the wiring 4009 is set to a low level, and the potential of the node FG2 in an electrically floating state is set to “V D2 ⁇ Vth”.
  • a current flows through the transistor 4100 when the potential of the node FG2 is decreased.
  • the potential of the electrically floating wiring 4003 is decreased.
  • Vgs of the transistor 4100 decreases.
  • Vgs of the transistor 4100 becomes Vth of the transistor 4100, a current flowing through the transistor 4100 is reduced.
  • the potential of the wiring 4003 becomes “V D2 ” that is a value larger by Vth than the potential “V D2 ⁇ Vth” of the node FG2.
  • the potential of the wiring 4003 corresponds to the data voltage of the data holding portion connected to the node FG2.
  • the read data voltage of the analog value is subjected to A / D conversion, and data of a data holding unit connected to the node FG2 is acquired.
  • a current flows through the transistor 4100 when the wiring 4003 after precharging is in a floating state and the potential of the wiring 4009 is switched from a high level to a low level.
  • the potential of the wiring 4003 in the floating state is decreased to “V D2 ”.
  • Vgs between “V D2 ⁇ Vth” of the node FG2 becomes Vth, so that the current stops.
  • V D2 ” written in the writing operation 2 is read out to the wiring 4003.
  • the transistor 4300 When data in the data holding portion connected to the node FG2 is acquired, the transistor 4300 is turned on to discharge “V D2 ⁇ Vth” of the node FG2.
  • the charge held in the node FG1 is distributed to the node FG2, and the data voltage of the data holding unit connected to the node FG1 is transferred to the data holding unit connected to the node FG2.
  • the wirings 4001 and 4003 are set to a low level.
  • the wiring 4006 is set to a high level.
  • the wiring 4005 and the wirings 4007 to 4009 are set to a low level.
  • the capacitance value of the capacitor 4600 is preferably larger than the capacitance value of the capacitor 4500.
  • the potential “V D1 ⁇ Vth” written to the node FG1 is preferably higher than the potential “V D2 ⁇ Vth” representing the same data. In this way, by changing the ratio of the capacitance values and increasing the potential to be written in advance, it is possible to suppress a decrease in potential after the charge is distributed. The fluctuation of the potential due to the charge distribution will be described later.
  • a data voltage read operation to the data holding unit connected to the node FG1 (hereinafter referred to as a read operation 2) will be described.
  • the wiring 4003 that has been electrically floated after precharging is discharged.
  • the wirings 4005 to 4008 are set to a low level.
  • the wiring 4009 is set to a high level at the time of precharging and then set to a low level.
  • the node FG2 in an electrically floating state is set to a potential “V D1 ⁇ Vth”.
  • the potential of the electrically floating wiring 4003 is decreased.
  • Vgs of the transistor 4100 decreases.
  • Vgs of the transistor 4100 becomes Vth of the transistor 4100
  • a current flowing through the transistor 4100 is reduced. That is, the potential of the wiring 4003 becomes “V D1 ” that is a value larger by Vth than the potential “V D1 ⁇ Vth” of the node FG2.
  • the potential of the wiring 4003 corresponds to the data voltage of the data holding portion connected to the node FG1.
  • the read data voltage of the analog value performs A / D conversion, and acquires data of the data holding unit connected to the node FG1. The above is the data voltage reading operation to the data holding portion connected to the node FG1.
  • a current flows through the transistor 4100 when the wiring 4003 after precharging is in a floating state and the potential of the wiring 4009 is switched from a high level to a low level.
  • the potential of the wiring 4003 in the floating state is lowered to “V D1 ”.
  • the current stops because Vgs between the node FG2 and “V D1 ⁇ Vth” becomes Vth. Then, “V D1 ” written in the writing operation 1 is read out to the wiring 4003.
  • the data voltage can be read from the plurality of data holding units by the data voltage reading operation from the nodes FG1 and FG2 described above. For example, a total of 8 bits (256 values) of data can be held by holding 4 bits (16 values) of data in each of the nodes FG1 and FG2.
  • the first layer 4021 to the third layer 4023 are used. However, by forming additional layers, the storage capacity can be increased without increasing the area of the semiconductor device. .
  • the read potential can be read as a voltage higher than the written data voltage by Vth. Therefore, it is possible to adopt a configuration in which Vth of “V D1 ⁇ Vth” or “V D2 ⁇ Vth” written by the write operation is canceled and read. As a result, the storage capacity per memory cell can be improved and the read data can be brought close to the correct data, so that the data reliability can be improved.
  • the semiconductor device illustrated in FIG. 17C is different from the semiconductor device illustrated in FIG. 17A in that the transistor 3500 and the sixth wiring 3006 are provided. In this case as well, information writing and holding operations can be performed by operations similar to those of the semiconductor device illustrated in FIG.
  • the transistor 3500 may be a transistor similar to the transistor 3200 described above.
  • the sixth wiring 3006 is electrically connected to the gate of the transistor 3500, one of the source and the drain of the transistor 3500 is electrically connected to the drain of the transistor 3200, and the other of the source and the drain of the transistor 3500 is the third It is electrically connected to the wiring 3003.
  • FIG. 19A shows a circuit diagram of the inverter.
  • the inverter 800 outputs a signal obtained by inverting the logic of the input terminal IN to the output terminal OUT.
  • the inverter 800 includes a plurality of OS transistors.
  • the signal SBG is a signal that can switch the electrical characteristics of the OS transistor.
  • FIG. 19B is a circuit diagram as an example of the inverter 800.
  • the inverter 800 includes an OS transistor 810 and an OS transistor 820. Since the inverter 800 can be manufactured using an n-channel transistor, the inverter 800 can be manufactured at a lower cost than a case where an inverter (CMOS inverter) is manufactured using a complementary metal oxide semiconductor (CMOS).
  • CMOS inverter complementary metal oxide semiconductor
  • the inverter 800 having an OS transistor can be arranged on a CMOS formed of Si transistors. Since the inverter 800 can be arranged so as to overlap the CMOS circuit configuration, an increase in circuit area corresponding to the addition of the inverter 800 can be suppressed.
  • the OS transistors 810 and 820 include a first gate that functions as a front gate, a second gate that functions as a back gate, a first terminal that functions as one of a source and a drain, and a second terminal that functions as the other of a source and a drain.
  • the first gate of the OS transistor 810 is connected to the second terminal.
  • a second gate of the OS transistor 810 is connected to a wiring for supplying the signal SBG .
  • a first terminal of the OS transistor 810 is connected to a wiring that supplies the voltage VDD.
  • the second terminal of the OS transistor 810 is connected to the output terminal OUT.
  • the first gate of the OS transistor 820 is connected to the input terminal IN.
  • a second gate of the OS transistor 820 is connected to the input terminal IN.
  • the first terminal of the OS transistor 820 is connected to the output terminal OUT.
  • a second terminal of the OS transistor 820 is connected to a wiring that supplies the voltage VSS.
  • FIG. 19C is a timing chart for explaining the operation of the inverter 800.
  • FIG. 19 (C) shows the signal waveform of the input terminal IN, the signal waveform of the output terminal OUT, and the change in the threshold voltage of the signal waveform of the signal S BG and OS transistor 810, (FET810).
  • the threshold voltage of the OS transistor 810 can be controlled.
  • Signal S BG has a voltage V BG_B for voltage V BG_A for causing negative shift of the threshold voltage, the threshold voltage is positive shift.
  • the OS transistor 810 can be negatively shifted to the threshold voltage V TH_A .
  • the OS transistor 810 can be positively shifted to the threshold voltage V TH_B .
  • FIG. 20A shows a Vg-Id curve which is one of the electrical characteristics of the transistor.
  • the above-described electrical characteristics of the OS transistor 810 can be shifted to a curve represented by a broken line 840 in FIG. 20A by increasing the voltage of the second gate as the voltage V BG_A . Further, the above-described electrical characteristics of the OS transistor 810 can be shifted to a curve represented by a solid line 841 in FIG. 20A by reducing the voltage of the second gate as the voltage V BG_B . As shown in FIG. 20 (A), OS transistor 810, by switching the signal S BG and so the voltage V BG_A or voltage V BG_B, can be shifted in the positive or negative shift of the threshold voltage.
  • the OS transistor 810 By positively shifting the threshold voltage to the threshold voltage VTH_B , the OS transistor 810 can be in a state in which current does not easily flow.
  • FIG. 20B visualizes this state. As shown in FIG. 20 (B), it can be extremely small current I B flowing through the OS transistor 810. Therefore, when the signal applied to the input terminal IN is at a high level and the OS transistor 820 is in an on state (ON), the voltage at the output terminal OUT can be sharply decreased.
  • the OS transistor 810 can be in a state in which a current easily flows by shifting the threshold voltage to the threshold voltage V TH_A minus. In FIG. 20C, this state is visualized. As shown in FIG. 20 (C), it can be larger than at least the current I B of the current I A flowing at this time. Therefore, when the signal supplied to the input terminal IN is at a low level and the OS transistor 820 is in an off state (OFF), the voltage of the output terminal OUT can be rapidly increased.
  • the control of the threshold voltage of the OS transistor 810 by the signal S BG previously where the state of the OS transistor 820 is switched i.e. it is preferably performed before time T1 and T2.
  • the threshold voltage of the OS transistor 810 is switched from the threshold voltage V TH_A to the threshold voltage V TH_B before the time T1 when the signal applied to the input terminal IN switches to the high level. Is preferred.
  • the threshold voltage of the OS transistor 810 is switched from the threshold voltage V TH_B to the threshold voltage V TH_A before the time T2 when the signal applied to the input terminal IN is switched to the low level. Is preferred.
  • FIG. 21A illustrates an example of a circuit configuration that can realize this configuration.
  • FIG. 21A includes an OS transistor 850 in addition to the circuit configuration illustrated in FIG.
  • the first terminal of the OS transistor 850 is connected to the second gate of the OS transistor 810.
  • the second terminal of the OS transistor 850 is connected to a wiring for applying the voltage V BG_B (or voltage V BG_A ).
  • the first gate of the OS transistor 850 is connected to a wiring for providing signal S F.
  • a second gate of the OS transistor 850 is connected to a wiring that supplies the voltage V BG_B (or the voltage V BG_A ).
  • FIG. 21A The operation in FIG. 21A will be described with reference to the timing chart in FIG.
  • the voltage for controlling the threshold voltage of the OS transistor 810 is applied to the second gate of the OS transistor 810 before time T3 when the signal applied to the input terminal IN switches to the high level.
  • the OS transistor 850 is turned on the signal S F to the high level, providing a voltage V BG_B for controlling a threshold voltage in the node N BG.
  • FIGS. 19B and 21A a configuration in which the voltage applied to the second gate of the OS transistor 810 is given by external control is shown, but another configuration may be used.
  • a voltage for controlling the threshold voltage may be generated based on a signal supplied to the input terminal IN and supplied to the second gate of the OS transistor 810.
  • FIG. 19A An example of a circuit configuration that can realize this configuration is illustrated in FIG. 19A
  • a CMOS inverter 860 is provided between the input terminal IN and the second gate of the OS transistor 810 in the circuit configuration shown in FIG. 19B.
  • the input terminal of the CMOS inverter 860 is connected to the input terminal IN.
  • the output terminal of the CMOS inverter 860 is connected to the second gate of the OS transistor 810.
  • FIG. 22A The operation in FIG. 22A will be described with reference to the timing chart in FIG.
  • the timing chart in FIG. 22B shows changes in the signal waveform of the input terminal IN, the signal waveform of the output terminal OUT, the output waveform IN_B of the CMOS inverter 860, and the threshold voltage of the OS transistor 810 (FET 810).
  • the output waveform IN_B which is a signal obtained by inverting the logic of the signal applied to the input terminal IN, can be a signal for controlling the threshold voltage of the OS transistor 810. Therefore, as described with reference to FIGS. 20A to 20C, the threshold voltage of the OS transistor 810 can be controlled. For example, at time T4 in FIG. 22B, the signal applied to the input terminal IN is at a high level and the OS transistor 820 is turned on. At this time, the output waveform IN_B is at a low level. Therefore, the OS transistor 810 can be in a state in which current does not easily flow, and the voltage of the output terminal OUT can be sharply decreased.
  • the signal applied to the input terminal IN is at a low level, so that the OS transistor 820 is turned off.
  • the output waveform IN_B is at a high level. Therefore, the OS transistor 810 can be in a state in which current easily flows, and the voltage of the output terminal OUT can be rapidly increased.
  • the voltage of the back gate in the inverter having the OS transistor is switched in accordance with the signal logic of the input terminal IN.
  • the threshold voltage of the OS transistor can be controlled.
  • the voltage of the output terminal OUT can be changed abruptly.
  • the through current between the wirings supplying the power supply voltage can be reduced. Therefore, low power consumption can be achieved.
  • FIG. 23 is a block diagram illustrating a configuration example of a CPU that partially uses the above-described transistor.
  • ALU 1191 Arithmetic logic unit, arithmetic circuit
  • ALU controller 1192 an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, and a bus interface 1198.
  • a rewritable ROM 1199 and a ROM interface 1189 As the substrate 1190, a semiconductor substrate, an SOI substrate, a glass substrate, or the like is used.
  • the ROM 1199 and the ROM interface 1189 may be provided in separate chips.
  • the CPU illustrated in FIG. 23 is just an example in which the configuration is simplified, and an actual CPU may have various configurations depending on the application.
  • the configuration including the CPU or the arithmetic circuit illustrated in FIG. 23 may be a single core, and a plurality of the cores may be included, and each core may operate in parallel.
  • the number of bits that the CPU can handle with the internal arithmetic circuit or the data bus can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, or the like.
  • Instructions input to the CPU via the bus interface 1198 are input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195.
  • the ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates a signal for controlling the operation of the ALU 1191.
  • the interrupt controller 1194 determines and processes an interrupt request from an external input / output device or a peripheral circuit from the priority or mask state during execution of the CPU program.
  • the register controller 1197 generates an address of the register 1196, and reads and writes the register 1196 according to the state of the CPU.
  • the timing controller 1195 generates a signal for controlling the operation timing of the ALU 1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197.
  • the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal CLK2 based on the reference clock signal CLK1, and supplies the internal clock signal CLK2 to the various circuits.
  • the register 1196 is provided with a memory cell.
  • the memory cell of the register 1196 the above-described transistor, memory device, or the like can be used.
  • the register controller 1197 selects a holding operation in the register 1196 in accordance with an instruction from the ALU 1191. That is, whether to hold data by a flip-flop or to hold data by a capacitor in a memory cell included in the register 1196 is selected. When data retention by the flip-flop is selected, the power supply voltage is supplied to the memory cell in the register 1196. When holding of data in the capacitor is selected, data is rewritten to the capacitor and supply of power supply voltage to the memory cells in the register 1196 can be stopped.
  • FIG. 24 is an example of a circuit diagram of a memory element 1200 that can be used as the register 1196.
  • the memory element 1200 includes a circuit 1201 in which stored data is volatilized by power-off, a circuit 1202 in which stored data is not volatilized by power-off, a switch 1203, a switch 1204, a logic element 1206, a capacitor 1207, and a selection function.
  • Circuit 1220 having.
  • the circuit 1202 includes a capacitor 1208, a transistor 1209, and a transistor 1210.
  • the memory element 1200 may further include other elements such as a diode, a resistance element, and an inductor, as necessary.
  • the memory device described above can be used for the circuit 1202.
  • GND (0 V) or a potential at which the transistor 1209 is turned off is continuously input to the gate of the transistor 1209 of the circuit 1202.
  • the gate of the transistor 1209 is grounded through a load such as a resistor.
  • the switch 1203 is configured using a transistor 1213 of one conductivity type (eg, n-channel type), and the switch 1204 is configured using a transistor 1214 of conductivity type (eg, p-channel type) opposite to the one conductivity type.
  • a transistor 1213 of one conductivity type eg, n-channel type
  • the switch 1204 is configured using a transistor 1214 of conductivity type (eg, p-channel type) opposite to the one conductivity type.
  • the first terminal of the switch 1203 corresponds to one of the source and the drain of the transistor 1213
  • the second terminal of the switch 1203 corresponds to the other of the source and the drain of the transistor 1213
  • the switch 1203 corresponds to the gate of the transistor 1213.
  • conduction or non-conduction between the first terminal and the second terminal that is, the conduction state or non-conduction state of the transistor 1213 is selected.
  • the first terminal of the switch 1204 corresponds to one of the source and the drain of the transistor 1214
  • the second terminal of the switch 1204 corresponds to the other of the source and the drain of the transistor 1214
  • the switch 1204 is input to the gate of the transistor 1214.
  • the control signal RD selects the conduction or non-conduction between the first terminal and the second terminal (that is, the conduction state or non-conduction state of the transistor 1214).
  • One of the source and the drain of the transistor 1209 is electrically connected to one of the pair of electrodes of the capacitor 1208 and the gate of the transistor 1210.
  • the connection part is referred to as a node M2.
  • One of a source and a drain of the transistor 1210 is electrically connected to a wiring that can supply a low power supply potential (eg, a GND line), and the other is connected to the first terminal of the switch 1203 (the source and the drain of the transistor 1213 On the other hand).
  • a second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is electrically connected to a first terminal of the switch 1204 (one of the source and the drain of the transistor 1214).
  • a second terminal of the switch 1204 (the other of the source and the drain of the transistor 1214) is electrically connected to a wiring that can supply the power supply potential VDD.
  • a second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213), a first terminal of the switch 1204 (one of a source and a drain of the transistor 1214), an input terminal of the logic element 1206, and the capacitor 1207
  • One of the pair of electrodes is electrically connected.
  • the connection part is referred to as a node M1.
  • the other of the pair of electrodes of the capacitor 1207 can be configured to receive a constant potential. For example, a low power supply potential (such as GND) or a high power supply potential (such as VDD) can be input.
  • the other of the pair of electrodes of the capacitor 1207 is electrically connected to a wiring (eg, a GND line) that can supply a low power supply potential.
  • the other of the pair of electrodes of the capacitor 1208 can have a constant potential.
  • a low power supply potential such as GND
  • a high power supply potential such as VDD
  • the other of the pair of electrodes of the capacitor 1208 is electrically connected to a wiring (eg, a GND line) that can supply a low power supply potential.
  • capacitor 1207 and the capacitor 1208 can be omitted by actively using parasitic capacitances of transistors and wirings.
  • the control signal WE is input to the gate of the transistor 1209.
  • the switch 1203 and the switch 1204 are selected to be in a conductive state or a non-conductive state between the first terminal and the second terminal by a control signal RD different from the control signal WE.
  • the terminals of the other switch are in a conductive state, the first terminal and the second terminal of the other switch are in a non-conductive state.
  • FIG. 24 illustrates an example in which the signal output from the circuit 1201 is input to the other of the source and the drain of the transistor 1209.
  • a signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is an inverted signal obtained by inverting the logic value by the logic element 1206 and is input to the circuit 1201 through the circuit 1220. .
  • FIG. 24 illustrates an example in which a signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is input to the circuit 1201 through the logic element 1206 and the circuit 1220. It is not limited to. A signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) may be input to the circuit 1201 without inversion of the logical value. For example, when there is a node in the circuit 1201 that holds a signal in which the logical value of the signal input from the input terminal is inverted, the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) An output signal can be input to the node.
  • a transistor other than the transistor 1209 among the transistors used in the memory element 1200 can be a film formed of a semiconductor other than an oxide semiconductor or a channel in the substrate 1190.
  • a transistor in which a channel is formed in a silicon film or a silicon substrate can be used.
  • all the transistors used for the memory element 1200 can be transistors whose channels are formed using an oxide semiconductor.
  • the memory element 1200 may include a transistor whose channel is formed using an oxide semiconductor in addition to the transistor 1209, and the remaining transistors are formed using a semiconductor layer other than the oxide semiconductor or the substrate 1190. It can also be a transistor.
  • a flip-flop circuit can be used for the circuit 1201 in FIG.
  • the logic element 1206 for example, an inverter, a clocked inverter, or the like can be used.
  • data stored in the circuit 1201 can be held by the capacitor 1208 provided in the circuit 1202 while the power supply voltage is not supplied to the memory element 1200.
  • a transistor in which a channel is formed in an oxide semiconductor has extremely low off-state current.
  • the off-state current of a transistor in which a channel is formed in an oxide semiconductor is significantly lower than the off-state current of a transistor in which a channel is formed in crystalline silicon. Therefore, by using the transistor as the transistor 1209, the signal held in the capacitor 1208 is maintained for a long time even when the power supply voltage is not supplied to the memory element 1200. In this manner, the memory element 1200 can hold stored data (data) even while the supply of power supply voltage is stopped.
  • the memory element is characterized by performing a precharge operation; therefore, after the supply of power supply voltage is resumed, the time until the circuit 1201 retains the original data again is shortened. be able to.
  • the signal held by the capacitor 1208 is input to the gate of the transistor 1210. Therefore, after the supply of the power supply voltage to the memory element 1200 is restarted, the signal held by the capacitor 1208 is converted into the state of the transistor 1210 (a conductive state or a non-conductive state) and read from the circuit 1202 Can do. Therefore, the original signal can be accurately read even if the potential corresponding to the signal held in the capacitor 1208 slightly fluctuates.
  • a storage element 1200 for a storage device such as a register or a cache memory included in the processor, it is possible to prevent data in the storage device from being lost due to the supply of power supply voltage being stopped.
  • the state before the power supply stop can be restored in a short time. Accordingly, power can be stopped in a short time in the entire processor or in one or a plurality of logic circuits constituting the processor, so that power consumption can be suppressed.
  • the memory element 1200 has been described as an example of use for a CPU, the memory element 1200 can be applied to an LSI such as a DSP (Digital Signal Processor), a custom LSI, a PLD (Programmable Logic Device), and an RF (Radio Frequency) device.
  • an LSI such as a DSP (Digital Signal Processor), a custom LSI, a PLD (Programmable Logic Device), and an RF (Radio Frequency) device.
  • a semiconductor device includes a display device, a personal computer, and an image reproducing device including a recording medium (typically a display that can reproduce a recording medium such as a DVD: Digital Versatile Disc and display the image) Device).
  • a recording medium typically a display that can reproduce a recording medium such as a DVD: Digital Versatile Disc and display the image
  • a mobile phone in which the semiconductor device according to one embodiment of the present invention can be used, a mobile phone, a game machine including a portable type, a portable data terminal, an electronic book terminal, a video camera, a digital still camera, or the like, goggles Type displays (head-mounted displays), navigation systems, sound playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, multifunction printers, automated teller machines (ATMs), vending machines, etc. It is done. Specific examples of these electronic devices are shown in FIGS.
  • FIG. 25A shows a portable game machine, which includes a housing 901, a housing 902, a display portion 903, a display portion 904, a microphone 905, a speaker 906, operation keys 907, a stylus 908, and the like. Note that the portable game machine illustrated in FIG. 25A includes two display portions 903 and 904; however, the number of display portions included in the portable game device is not limited thereto.
  • FIG. 25B shows a portable data terminal, which includes a first housing 911, a second housing 912, a first display portion 913, a second display portion 914, a connection portion 915, operation keys 916, and the like.
  • the first display unit 913 is provided in the first housing 911
  • the second display unit 914 is provided in the second housing 912.
  • the first housing 911 and the second housing 912 are connected by the connection portion 915, and the angle between the first housing 911 and the second housing 912 can be changed by the connection portion 915. is there. It is good also as a structure which switches the image
  • a display device in which a function as a position input device is added to at least one of the first display portion 913 and the second display portion 914 may be used.
  • the function as a position input device can be added by providing a touch panel on the display device.
  • the function as a position input device can be added by providing a photoelectric conversion element called a photosensor in a pixel portion of a display device.
  • FIG. 25C illustrates a laptop personal computer, which includes a housing 921, a display portion 922, a keyboard 923, a pointing device 924, and the like.
  • FIG. 25D illustrates an electric refrigerator-freezer, which includes a housing 931, a refrigerator door 932, a refrigerator door 933, and the like.
  • FIG. 25E illustrates a video camera, which includes a first housing 941, a second housing 942, a display portion 943, operation keys 944, a lens 945, a connection portion 946, and the like.
  • the operation key 944 and the lens 945 are provided in the first housing 941, and the display portion 943 is provided in the second housing 942.
  • the first housing 941 and the second housing 942 are connected by a connection portion 946, and the angle between the first housing 941 and the second housing 942 can be changed by the connection portion 946. is there. It is good also as a structure which switches the image
  • FIG. 25F illustrates an automobile, which includes a vehicle body 951, wheels 952, a dashboard 953, lights 954, and the like.
  • a channel formation region, a source / drain region, and the like of a transistor include an oxide semiconductor
  • a channel formation region of the transistor, a source / drain region of the transistor, or the like may include various semiconductors.
  • a channel formation region of the transistor, a source / drain region of the transistor, and the like can be formed using, for example, silicon, germanium, silicon germanium, silicon carbide, or gallium. At least one of arsenic, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor may be included. Alternatively, for example, depending on circumstances or circumstances, a variety of transistors, channel formation regions of the transistors, source and drain regions of the transistors, and the like of the transistor may not include an oxide semiconductor. Good.
  • FIG. 26A and 26B are cross-sectional views of the model 11.
  • FIG. FIG. 26A corresponds to FIG. 1B described in the above embodiment and is a cross-sectional view of the model 11 in the channel length direction.
  • FIG. 26B corresponds to FIG. 1C described in the above embodiment, and is a cross-sectional view perpendicular to the channel length direction of the model 11.
  • a low resistance region 106c and a low resistance region 106d are provided at both ends of the semiconductor 106b in the channel length direction, and further outside the low resistance region 106c.
  • a conductor 108a is provided, and a conductor 108b is provided outside the low resistance region 106d.
  • the insulator 112 is continuously provided on the inside and outside of the conductor 114, and the portion provided on the inside of the conductor 114 is the conductor 114 and the conductor. It functions as a gate insulating film for 102.
  • the insulator 106a assumed IGZO (134), and the semiconductor 106b assumed IGZO (111).
  • the low resistance region 106c and the low resistance region 106d were assumed to have a donor density of 1.0 ⁇ 10 19 / cm 3 by adding a donor to the semiconductor.
  • the channel length L (the width of the conductor 114 shown in FIG. 26) is 30 nm
  • the radius of the semiconductor 106b is 10 nm
  • the thickness of the insulator 106a is 5 nm
  • the thickness of the conductor 114 is The thickness of the conductor 102 was 2 nm.
  • the thickness between the insulator 106a and the conductor 114 is 12 nm
  • the thickness between the insulator 106a and the conductor 102 is 5 nm
  • the thickness outside the conductor 114 is 10 nm. did.
  • Table 1 below shows detailed parameters used in the calculation.
  • the conduction band state density (Nc) indicates the state density at the lower end of the conduction band
  • the valence band state density (Nc) indicates the state density at the upper end of the valence band.
  • the model 11 includes a semiconductor 106b, an insulator 106a, an insulator 112, a conductor 102, a conductor 114, a conductor 108a, and a conductor 108b.
  • the semiconductor 106b functions as an active layer
  • the insulator 112 functions as a gate insulating film for the conductor 104 and the conductor 102
  • the conductor 114 functions as a gate electrode
  • the conductor 102 functions as a back gate electrode.
  • the conductor 108a functions as a source electrode
  • the conductor 108b functions as a drain electrode.
  • FIG. 27 shows Id-Vg characteristics (drain current-gate voltage characteristics) obtained by performing device simulation.
  • the horizontal axis represents the gate voltage Vg [V]
  • the vertical axis represents the drain current Id [A].
  • the calculation of the Id-Vg characteristic was performed when the back gate voltage Vbg was set to -3V and when Vbg was set to 0V. In each case, the drain voltage is set to 0.1 V, and the gate voltage is swept from ⁇ 3.0 V to 3.0 V.

Abstract

To provide a transistor resistant to short channel effects. This semiconductor device includes: a first electrical conductor provided in the shape of a ring; an oxide semiconductor having an elongated region which passes through to the inside of the first electrical conductor ring; a first insulator provided between the first electrical conductor and the oxide semiconductor; a second insulator provided between the first electrical conductor and the first insulator; and a second electrical conductor provided passing through to the inside of the first electrical conductor ring; wherein the second electrical conductor is provided in the second insulator.

Description

半導体装置Semiconductor device
　本発明は、例えば、トランジスタおよび半導体装置に関する。または、本発明は、例えば、トランジスタおよび半導体装置の製造方法に関する。または、本発明は、例えば、表示装置、発光装置、照明装置、蓄電装置、記憶装置、プロセッサ、電子機器に関する。または、表示装置、液晶表示装置、発光装置、記憶装置、電子機器の製造方法に関する。または、表示装置、液晶表示装置、発光装置、記憶装置、電子機器の駆動方法に関する。 The present invention relates to a transistor and a semiconductor device, for example. Alternatively, the present invention relates to a method for manufacturing a transistor and a semiconductor device, for example. Alternatively, the present invention relates to, for example, a display device, a light-emitting device, a lighting device, a power storage device, a storage device, a processor, and an electronic device. Alternatively, the present invention relates to a method for manufacturing a display device, a liquid crystal display device, a light-emitting device, a memory device, or an electronic device. Alternatively, the present invention relates to a display device, a liquid crystal display device, a light-emitting device, a memory device, and a driving method of an electronic device.
　なお、本発明の一態様は、上記の技術分野に限定されない。本明細書等で開示する発明の一態様の技術分野は、物、方法、または、製造方法に関するものである。または、本発明の一態様は、プロセス、マシン、マニュファクチャ、または、組成物（コンポジション・オブ・マター）に関するものである。 Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).
　なお、本明細書等において半導体装置とは、半導体特性を利用することで機能しうる装置全般を指す。表示装置、発光装置、照明装置、電気光学装置、半導体回路および電子機器は、半導体装置を有する場合がある。 Note that in this specification and the like, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. A display device, a light-emitting device, a lighting device, an electro-optical device, a semiconductor circuit, and an electronic device may include a semiconductor device.
　電子機器を構成するＣＰＵ、メモリなどの様々な集積回路（ＩＣ）において、シリコンからなるトランジスタが広く用いられている。電子機器の高性能化、小型化、軽量化に伴い、集積回路は高集積化され、トランジスタのサイズは微細化している。これに従って、トランジスタ作製のプロセスルールも、４５ｎｍ、３２ｎｍ、２２ｎｍと年々小さくなっている。 Transistors made of silicon are widely used in various integrated circuits (ICs) such as CPUs and memories constituting electronic devices. As electronic devices become more sophisticated, smaller, and lighter, integrated circuits are highly integrated and transistors are becoming smaller in size. In accordance with this, process rules for manufacturing transistors are also decreasing year by year, such as 45 nm, 32 nm, and 22 nm.
　このように、トランジスタの微細化が進むことで、短チャネル効果と呼ばれる問題が生じている。短チャネル効果とは、トランジスタの微細化（チャネル長（Ｌ）の縮小）に伴って顕在化する電気特性の劣化であり、ドレイン電極の電界の効果がソース電極にまでおよぶことに起因するものである。短チャネル効果の具体例としては、しきい値電圧の低下、サブスレッショルドスイング値の増大、漏れ電流の増大などがある。 As described above, the progress of miniaturization of transistors causes a problem called a short channel effect. The short channel effect is a deterioration in electrical characteristics that becomes apparent as a transistor is miniaturized (channel length (L) is reduced), and is caused by the effect of the electric field of the drain electrode reaching the source electrode. is there. Specific examples of the short channel effect include a decrease in threshold voltage, an increase in subthreshold swing value, and an increase in leakage current.
　短チャネル効果への対策の一つとして、ナノワイヤトランジスタが挙げられる（特許文献１参照。）。ナノワイヤトランジスタとは、直径数ｎｍ乃至数十ｎｍ程度の極めて細い円柱状のシリコンを活性層に用いたトランジスタである。シリコンの延伸方向と交差してゲートがシリコンを囲む構造をしており、全周囲を囲んだゲート電極によってドレイン電極の電界がソース電極まで影響することを防ぐことができる。 As one of countermeasures against the short channel effect, there is a nanowire transistor (see Patent Document 1). A nanowire transistor is a transistor using an extremely thin cylindrical silicon having a diameter of several nm to several tens of nm as an active layer. The gate surrounds the silicon so as to intersect the extending direction of the silicon, and the gate electrode surrounding the entire periphery can prevent the electric field of the drain electrode from affecting the source electrode.
特開２０１１−２１１１２７号公報JP 2011-2111127 A
　しかしながら、シリコンを用いたナノワイヤトランジスタの、非導通時のリーク電流は、数μＡ／μｍ程度であり、さらにゲート電圧０Ｖにおけるリーク電流を低減することが求められている。 However, the leakage current of non-conducting nanowire transistors using silicon is about several μA / μm, and it is required to further reduce the leakage current at a gate voltage of 0V.
　そこで、本発明の一態様は、短チャネル効果に耐性を有するトランジスタを提供することを課題の一とする。または、ノーマリーオフの電気特性を有するトランジスタを提供することを課題の一とする。または、非導通時のリーク電流の小さいトランジスタを提供することを課題の一とする。または、サブスレッショルドスイング値の小さいトランジスタを提供することを課題の一とする。または、チャネル長の短い微細構造において、安定した電気特性を有するトランジスタを提供することを課題の一とする。 Therefore, an object of one embodiment of the present invention is to provide a transistor having resistance to a short channel effect. Another object is to provide a transistor having normally-off electrical characteristics. Another object is to provide a transistor with low leakage current during non-conduction. Another object is to provide a transistor with a small subthreshold swing value. Another object is to provide a transistor having stable electrical characteristics in a microstructure with a short channel length.
　または、該トランジスタを有する半導体装置を提供することを課題の一とする。または、該半導体装置を有するモジュールを提供することを課題の一とする。または、該半導体装置、または該モジュールを有する電子機器を提供することを課題の一とする。または、新規な半導体装置を提供することを課題の一とする。または、新規なモジュールを提供することを課題の一とする。または、新規な電子機器を提供することを課題の一とする。 Another object is to provide a semiconductor device including the transistor. Another object is to provide a module including the semiconductor device. Another object is to provide an electronic device including the semiconductor device or the module. Another object is to provide a novel semiconductor device. Another object is to provide a new module. Another object is to provide a novel electronic device.
　なお、これらの課題の記載は、他の課題の存在を妨げるものではない。なお、本発明の一態様は、これらの課題の全てを解決する必要はないものとする。なお、これら以外の課題は、明細書、図面、請求項などの記載から、自ずと明らかとなるものであり、明細書、図面、請求項などの記載から、これら以外の課題を抽出することが可能である。 Note that the description of these issues does not disturb the existence of other issues. Note that one embodiment of the present invention does not have to solve all of these problems. Issues other than these will be apparent from the description of the specification, drawings, claims, etc., and other issues can be extracted from the descriptions of the specification, drawings, claims, etc. It is.
　本発明の一態様は、環状に設けられた第１の導電体と、第１の導電体の環の内側を通して伸長した領域を有する酸化物半導体と、第１の導電体と、酸化物半導体との間に設けられた第１の絶縁体と、第１の導電体と、第１の絶縁体との間に設けられた第２の絶縁体と、第１の導電体の環の内側を通して設けられた第２の導電体と、を有し、第２の導電体は、第２の絶縁体中に設けられる半導体装置である。 One embodiment of the present invention includes a first conductor provided in a ring shape, an oxide semiconductor including a region extending through the inside of the ring of the first conductor, the first conductor, and the oxide semiconductor. The first insulator provided between the first insulator, the first conductor, the second insulator provided between the first insulator, and the inside of the ring of the first conductor. A second conductor, and the second conductor is a semiconductor device provided in the second insulator.
　また、本発明の一態様は、上記の発明において、酸化物半導体に接して、第１の導電体を間に挟んで設けられた第３の導電体及び第４の導電体と、を有し、第３の導電体と第４の導電体の間の距離は２ｎｍ以上３０ｎｍ以下であることを特徴とする半導体装置である。 Another embodiment of the present invention includes the third conductor and the fourth conductor which are in contact with the oxide semiconductor and are provided with the first conductor interposed therebetween, in the above invention. The semiconductor device is characterized in that the distance between the third conductor and the fourth conductor is 2 nm or more and 30 nm or less.
　また、本発明の一態様は、上記の発明において、酸化物半導体の伸長方向に略垂直な面における断面形状は、略円形状であることを特徴とする半導体装置である。 One embodiment of the present invention is the semiconductor device according to the above invention, in which a cross-sectional shape in a plane substantially perpendicular to the extending direction of the oxide semiconductor is a substantially circular shape.
　また、本発明の一態様は、上記の発明において、酸化物半導体の伸長方向に略垂直な面における断面形状は、略多角形状であることを特徴とする半導体装置である。 Another embodiment of the present invention is the semiconductor device according to the above invention, in which a cross-sectional shape in a plane substantially perpendicular to the extending direction of the oxide semiconductor is a substantially polygonal shape.
　また、本発明の一態様は、上記の発明において、半導体装置は、基板上に設けられており、基板の上面は酸化物半導体の伸長方向に略平行であることを特徴とする半導体装置である。 Another embodiment of the present invention is the semiconductor device according to the above invention, wherein the semiconductor device is provided over a substrate, and an upper surface of the substrate is substantially parallel to an extension direction of the oxide semiconductor. .
　また、本発明の一態様は、上記の発明において、半導体装置は、基板上に設けられており、基板の上面は酸化物半導体の伸長方向に略垂直であることを特徴とする半導体装置である。 Another embodiment of the present invention is the semiconductor device according to the above invention, wherein the semiconductor device is provided over a substrate, and the top surface of the substrate is substantially perpendicular to the extending direction of the oxide semiconductor. .
　また、本発明の一態様は、上記の発明において、第１の絶縁体は、インジウム、元素Ｍ（Ｔｉ、Ｇａ、Ｙ、Ｚｒ、Ｌａ、Ｃｅ、Ｎｄ、ＳｎまたはＨｆ）及び亜鉛のうち少なくとも一以上を有する半導体装置である。 In one embodiment of the present invention, in the above invention, the first insulator is at least one of indium, an element M (Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf) and zinc. A semiconductor device having the above.
　また、本発明の一態様は、基板上に、第１の方向に伸長して設けられた第１の導電体と、第１の導電体上に設けられた第１の絶縁体と、第１の絶縁体上に設けられた、開口を有する第２の絶縁体と、第２の絶縁体に形成された開口の中に、第１の方向に略垂直である第２の方向に伸長して設けられた第２の導電体と第２の絶縁体及び第２の導電体上に設けられた第３の絶縁体と、第３の絶縁体上に設けられた第４の絶縁体と、第３の絶縁体上に、第４の絶縁体を間に挟んで設けられた第３の導電体及び第４の導電体と、第４の絶縁体、第３の導電体及び第４の導電体の上面に接して、第２の方向に伸長して設けられた酸化物半導体と、酸化物半導体の上面及び側面と、第３の導電体の側面に接して、第５の絶縁体を間に挟んで第６の導電体と対向して設けられた第５の導電体と、酸化物半導体の上面及び側面と、第４の導電体の側面に接して、第５の絶縁体を間に挟んで第５導電体と対向して設けられた第６の導電体と、第５の導電体及び第６の導電体上に設けられ、第５の導電体と第６の導電体の間に開口を有する第６の絶縁体と、酸化物半導体の上面、第５の導電体及び第６の導電体の側面、第６の絶縁体の側面と接して設けられた第５の絶縁体と、第５の絶縁体の上面に接して設けられた第７の絶縁体と、第７の絶縁体の上面に接して設けられた第７の導電体と、を有し、第１の方向に略垂直な面の断面において、第４の絶縁体と第５の絶縁体は、酸化物半導体を囲むように設けられ、第３の絶縁体と第７の絶縁体は、第４の絶縁体、酸化物半導体及び第５の絶縁体を囲むように設けられ、第１の導電体と第７の導電体は、第１乃至第３の絶縁体及び第７の絶縁体を囲むように設けられることを特徴とする半導体装置である。 According to one embodiment of the present invention, a first conductor provided to extend in a first direction over a substrate, a first insulator provided over the first conductor, A second insulator having an opening provided on the first insulator and an opening formed in the second insulator extending in a second direction substantially perpendicular to the first direction. A second conductor provided; a second insulator; a third insulator provided on the second conductor; a fourth insulator provided on the third insulator; A third conductor and a fourth conductor provided on the third insulator with a fourth insulator interposed therebetween, and a fourth insulator, a third conductor, and a fourth conductor. An oxide semiconductor provided in contact with the upper surface of the oxide semiconductor layer and extending in the second direction; an upper surface and side surfaces of the oxide semiconductor; and a side surface of the third conductor; Sixth conductor sandwiched between The fifth conductor provided in opposition, the upper surface and side surfaces of the oxide semiconductor, and the side surfaces of the fourth conductor are opposed to the fifth conductor with the fifth insulator interposed therebetween. A sixth conductor provided on the fifth conductor and the sixth conductor, and a sixth insulator having an opening between the fifth conductor and the sixth conductor; A top surface of the oxide semiconductor; a side surface of the fifth conductor and the sixth conductor; a fifth insulator provided in contact with the side surface of the sixth insulator; and a top surface of the fifth insulator. And a seventh conductor provided in contact with the upper surface of the seventh insulator, and in a cross section of a plane substantially perpendicular to the first direction, the fourth insulator The insulator and the fifth insulator are provided so as to surround the oxide semiconductor, and the third insulator and the seventh insulator include the fourth insulator, the oxide semiconductor, and the fifth insulator. Enclose Provided cormorants, conductor of the first conductor and the seventh is a semiconductor device which is characterized in that it is provided to surround the first through third insulator and the seventh insulator.
　また、本発明の一態様は、上記の発明において、第４の絶縁体及び第５の絶縁体は、インジウム、元素Ｍ（Ｔｉ、Ｇａ、Ｙ、Ｚｒ、Ｌａ、Ｃｅ、Ｎｄ、ＳｎまたはＨｆ）及び亜鉛のうち少なくとも一以上を有する半導体装置である。 Another embodiment of the present invention is the above invention, wherein the fourth insulator and the fifth insulator are indium, an element M (Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf). And a semiconductor device having at least one of zinc.
　また、本発明の一態様は、上記の発明において、酸化物半導体は、インジウム、元素Ｍ（Ｔｉ、Ｇａ、Ｙ、Ｚｒ、Ｌａ、Ｃｅ、Ｎｄ、ＳｎまたはＨｆ）、亜鉛および酸素を有することを特徴とする半導体装置である。 Another embodiment of the present invention is the above invention, in which the oxide semiconductor includes indium, an element M (Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf), zinc, and oxygen. This is a featured semiconductor device.
　短チャネル効果に耐性を有するトランジスタを提供することができる。または、ノーマリーオフの電気特性を有するトランジスタを提供することができる。または、非導通時のリーク電流の小さいトランジスタを提供することができる。または、サブスレッショルドスイング値の小さいトランジスタを提供することができる。または、チャネル長の短い微細構造において、安定した電気特性を有するトランジスタを提供することができる。 A transistor having resistance to the short channel effect can be provided. Alternatively, a transistor having normally-off electrical characteristics can be provided. Alternatively, a transistor with low leakage current when not conducting can be provided. Alternatively, a transistor with a small subthreshold swing value can be provided. Alternatively, a transistor having stable electrical characteristics can be provided in a microstructure with a short channel length.
　または、該トランジスタを有する半導体装置を提供することができる。または、該半導体装置を有するモジュールを提供することができる。または、該半導体装置、または該モジュールを有する電子機器を提供することができる。または、新規な半導体装置を提供することができる。または、新規なモジュールを提供することができる。または、新規な電子機器を提供することができる。 Alternatively, a semiconductor device including the transistor can be provided. Alternatively, a module including the semiconductor device can be provided. Alternatively, an electronic device including the semiconductor device or the module can be provided. Alternatively, a novel semiconductor device can be provided. Alternatively, a new module can be provided. Alternatively, a novel electronic device can be provided.
　なお、これらの効果の記載は、他の効果の存在を妨げるものではない。なお、本発明の一態様は、これらの効果の全てを有する必要はない。なお、これら以外の効果は、明細書、図面、請求項などの記載から、自ずと明らかとなるものであり、明細書、図面、請求項などの記載から、これら以外の効果を抽出することが可能である。 Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention need not have all of these effects. It should be noted that the effects other than these are naturally obvious from the description of the specification, drawings, claims, etc., and it is possible to extract the other effects from the descriptions of the specification, drawings, claims, etc. It is.
本発明の一態様に係るトランジスタを説明する上面図および断面図。4A and 4B are a top view and cross-sectional views illustrating a transistor according to one embodiment of the present invention. 本発明の一態様に係るトランジスタを説明する断面図。6A and 6B are cross-sectional views illustrating a transistor according to one embodiment of the present invention. 本発明の一態様に係るトランジスタを説明する断面図。6A and 6B are cross-sectional views illustrating a transistor according to one embodiment of the present invention. 本発明の一態様に係るトランジスタを説明する断面図。6A and 6B are cross-sectional views illustrating a transistor according to one embodiment of the present invention. 本発明の一態様に係るトランジスタの作製方法を説明する断面図。6A and 6B are cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention. 本発明の一態様に係るトランジスタの作製方法を説明する断面図。6A and 6B are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. 本発明の一態様に係るトランジスタの作製方法を説明する断面図。6A and 6B are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. 本発明の一態様に係るトランジスタに係るバンド図。FIG. 13 is a band diagram of a transistor according to one embodiment of the present invention. 数値計算に用いたトランジスタのモデルを示す模式図。The schematic diagram which shows the model of the transistor used for the numerical calculation. 数値計算で求めたポテンシャルを表す図。The figure showing the potential calculated | required by the numerical calculation. ＣＡＡＣ−ＯＳおよび単結晶酸化物半導体のＸＲＤによる構造解析を説明する図、ならびにＣＡＡＣ−ＯＳの制限視野電子回折パターンを示す図。FIGS. 4A to 4C illustrate structural analysis by XRD of a CAAC-OS and a single crystal oxide semiconductor, and FIGS. ＣＡＡＣ−ＯＳの断面ＴＥＭ像、ならびに平面ＴＥＭ像およびその画像解析像。Sectional TEM image of CAAC-OS, planar TEM image and image analysis image thereof. ｎｃ−ＯＳの電子回折パターンを示す図、およびｎｃ−ＯＳの断面ＴＥＭ像。The figure which shows the electron diffraction pattern of nc-OS, and the cross-sectional TEM image of nc-OS. ａ−ｌｉｋｅ　ＯＳの断面ＴＥＭ像。Cross-sectional TEM image of a-like OS. Ｉｎ−Ｇａ−Ｚｎ酸化物の電子照射による結晶部の変化を示す図。FIG. 6 shows changes in crystal parts of an In—Ga—Zn oxide due to electron irradiation. 本発明の一態様に係る半導体装置を示す回路図。FIG. 10 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る記憶装置を示す回路図。FIG. 10 is a circuit diagram illustrating a memory device according to one embodiment of the present invention. 本発明の一態様に係る記憶装置を示す回路図。FIG. 10 is a circuit diagram illustrating a memory device according to one embodiment of the present invention. 本発明の一態様を説明するための回路図およびタイミングチャート。6A and 6B are a circuit diagram and a timing chart for illustrating one embodiment of the present invention. 本発明の一態様を説明するためのグラフおよび回路図。5A and 5B are a graph and a circuit diagram for illustrating one embodiment of the present invention. 本発明の一態様を説明するための回路図およびタイミングチャート。6A and 6B are a circuit diagram and a timing chart for illustrating one embodiment of the present invention. 本発明の一態様を説明するための回路図およびタイミングチャート。6A and 6B are a circuit diagram and a timing chart for illustrating one embodiment of the present invention. 本発明の一態様に係る半導体装置を示すブロック図。1 is a block diagram illustrating a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る半導体装置を示す回路図。FIG. 10 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る電子機器を示す斜視図。FIG. 11 is a perspective view illustrating an electronic device according to one embodiment of the present invention. 本実施例に用いたトランジスタのモデルを示す模式図。FIG. 5 is a schematic diagram illustrating a model of a transistor used in this example. 本実施例の計算結果を示すグラフ。The graph which shows the calculation result of a present Example.
　本発明の実施の形態について、図面を用いて詳細に説明する。ただし、本発明は以下の説明に限定されず、その形態および詳細を様々に変更し得ることは、当業者であれば容易に理解される。また、本発明は以下に示す実施の形態の記載内容に限定して解釈されるものではない。なお、図面を用いて発明の構成を説明するにあたり、同じものを指す符号は異なる図面間でも共通して用いる。なお、同様のものを指す際にはハッチパターンを同じくし、特に符号を付さない場合がある。 Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that modes and details can be variously changed. In addition, the present invention is not construed as being limited to the description of the embodiments below. Note that in describing the structure of the present invention with reference to drawings, the same portions are denoted by the same reference numerals in different drawings. In addition, when referring to the same thing, a hatch pattern is made the same and there is a case where it does not attach a code in particular.
　以下の実施の形態に示す構成は、実施の形態に示す他の構成に対して適宜、適用、組み合わせ、又は置き換えなどを行って、本発明の一態様とすることができる。 The structures described in the following embodiments can be applied to, combined with, or replaced with the other structures described in the embodiments as appropriate, according to one embodiment of the present invention.
　なお、図において、大きさ、膜（層）の厚さ、または領域は、明瞭化のために誇張されている場合がある。 Note that the size, the thickness of films (layers), or regions in drawings is sometimes exaggerated for simplicity.
　なお、本明細書において、「膜」という表記と、「層」という表記と、を互いに入れ替えることが可能である。 In the present specification, the expression “film” and the expression “layer” can be interchanged.
　また、電圧は、ある電位と、基準の電位（例えば接地電位（ＧＮＤ）またはソース電位）との電位差のことを示す場合が多い。よって、電圧を電位と言い換えることが可能である。一般的に、電位（電圧）は、相対的なものであり、基準の電位からの相対的な大きさによって決定される。したがって、「接地電位」などと記載されている場合であっても、電位が０Ｖであるとは限らない。例えば、回路で最も低い電位が、「接地電位」となる場合もある。または、回路で中間くらいの電位が、「接地電位」となる場合もある。その場合には、その電位を基準として、正の電位と負の電位が規定される。 In addition, the voltage often indicates a potential difference between a certain potential and a reference potential (for example, a ground potential (GND) or a source potential). Thus, a voltage can be rephrased as a potential. Generally, the potential (voltage) is relative and is determined by a relative magnitude from a reference potential. Therefore, even when “ground potential” is described, the potential is not always 0V. For example, the lowest potential in the circuit may be the “ground potential”. Alternatively, an intermediate potential in the circuit may be a “ground potential”. In that case, a positive potential and a negative potential are defined based on the potential.
　なお、第１、第２として付される序数詞は便宜的に用いるものであり、工程順または積層順を示すものではない。そのため、例えば、「第１の」を「第２の」または「第３の」などと適宜置き換えて説明することができる。また、本明細書などに記載されている序数詞と、本発明の一態様を特定するために用いられる序数詞は一致しない場合がある。 The ordinal numbers attached as the first and second are used for convenience, and do not indicate the order of steps or the order of lamination. Therefore, for example, the description can be made by appropriately replacing “first” with “second” or “third”. In addition, the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one embodiment of the present invention.
　なお、「半導体」と表記した場合でも、例えば、導電性が十分低い場合は「絶縁体」としての特性を有する場合がある。また、「半導体」と「絶縁体」は境界が曖昧であり、厳密に区別できない場合がある。したがって、本明細書に記載の「半導体」は、「絶縁体」と言い換えることができる場合がある。同様に、本明細書に記載の「絶縁体」は、「半導体」と言い換えることができる場合がある。 Note that even when “semiconductor” is described, for example, when the conductivity is sufficiently low, the semiconductor device may have characteristics as an “insulator”. In addition, the boundary between “semiconductor” and “insulator” is ambiguous and may not be strictly discriminated. Therefore, a “semiconductor” in this specification can be called an “insulator” in some cases. Similarly, an “insulator” in this specification can be called a “semiconductor” in some cases.
　また、「半導体」と表記した場合でも、例えば、導電性が十分高い場合は「導電体」としての特性を有する場合がある。また、「半導体」と「導電体」は境界が曖昧であり、厳密に区別できない場合がある。したがって、本明細書に記載の「半導体」は、「導電体」と言い換えることができる場合がある。同様に、本明細書に記載の「導電体」は、「半導体」と言い換えることができる場合がある。 In addition, even when “semiconductor” is described, for example, when the conductivity is sufficiently high, it may have a characteristic as a “conductor”. In addition, the boundary between “semiconductor” and “conductor” is ambiguous, and there are cases where it cannot be strictly distinguished. Therefore, a “semiconductor” in this specification can be called a “conductor” in some cases. Similarly, a “conductor” in this specification can be called a “semiconductor” in some cases.
　なお、半導体の不純物とは、例えば、半導体を構成する主成分以外をいう。例えば、濃度が０．１原子％未満の元素は不純物である。不純物が含まれることにより、例えば、半導体にＤＯＳ（Ｄｅｎｓｉｔｙ　ｏｆ　Ｓｔａｔｅ）が形成されることや、キャリア移動度が低下することや、結晶性が低下することなどが起こる場合がある。半導体が酸化物半導体である場合、半導体の特性を変化させる不純物としては、例えば、第１族元素、第２族元素、第１４族元素、第１５族元素、主成分以外の遷移金属などがあり、特に、例えば、水素（水にも含まれる）、リチウム、ナトリウム、シリコン、ホウ素、リン、炭素、窒素などがある。酸化物半導体の場合、例えば水素などの不純物の混入によって酸素欠損を形成する場合がある。また、半導体がシリコン層である場合、半導体の特性を変化させる不純物としては、例えば、酸素、水素を除く第１族元素、第２族元素、第１３族元素、第１５族元素などがある。 In addition, the impurity of a semiconductor means the thing other than the main component which comprises a semiconductor, for example. For example, an element having a concentration of less than 0.1 atomic% is an impurity. By including impurities, for example, DOS (Density of State) may be formed in a semiconductor, carrier mobility may be reduced, and crystallinity may be reduced. When the semiconductor is an oxide semiconductor, examples of impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 14 elements, Group 15 elements, and transition metals other than the main component. In particular, for example, hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen and the like. In the case of an oxide semiconductor, oxygen vacancies may be formed by mixing impurities such as hydrogen, for example. In the case where the semiconductor is a silicon layer, examples of impurities that change the characteristics of the semiconductor include group 1 elements, group 2 elements, group 13 elements, and group 15 elements excluding oxygen and hydrogen.
　なお、チャネル長とは、例えば、トランジスタの上面図において、半導体（またはトランジスタがオン状態のときに半導体の中で電流の流れる部分）とゲート電極とが互いに重なる領域、またはチャネルが形成される領域における、ソース（ソース領域またはソース電極）とドレイン（ドレイン領域またはドレイン電極）との間の距離をいう。なお、一つのトランジスタにおいて、チャネル長が全ての領域で同じ値をとるとは限らない。即ち、一つのトランジスタのチャネル長は、一つの値に定まらない場合がある。そのため、本明細書では、チャネル長は、チャネルの形成される領域における、いずれか一の値、最大値、最小値または平均値とする。 Note that the channel length refers to, for example, a region where a semiconductor (or a portion where current flows in the semiconductor when the transistor is on) and a gate electrode overlap with each other in a top view of the transistor, or a region where a channel is formed The distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in FIG. Note that in one transistor, the channel length is not necessarily the same in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.
　チャネル幅とは、例えば、半導体（またはトランジスタがオン状態のときに半導体の中で電流の流れる部分）とゲート電極とが互いに重なる領域、またはチャネルが形成される領域における、ソースとドレインとが向かい合っている部分の長さをいう。なお、一つのトランジスタにおいて、チャネル幅がすべての領域で同じ値をとるとは限らない。即ち、一つのトランジスタのチャネル幅は、一つの値に定まらない場合がある。そのため、本明細書では、チャネル幅は、チャネルの形成される領域における、いずれか一の値、最大値、最小値または平均値とする。 The channel width is, for example, a region in which a semiconductor (or a portion in which a current flows in the semiconductor when the transistor is on) and a gate electrode overlap each other, or a source and a drain in a region where a channel is formed. This is the length of the part. Note that in one transistor, the channel width is not necessarily the same in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in this specification, the channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.
　なお、トランジスタの構造によっては、実際にチャネルの形成される領域におけるチャネル幅（以下、実効的なチャネル幅と呼ぶ。）と、トランジスタの上面図において示されるチャネル幅（以下、見かけ上のチャネル幅と呼ぶ。）と、が異なる場合がある。例えば、立体的な構造を有するトランジスタでは、実効的なチャネル幅が、トランジスタの上面図において示される見かけ上のチャネル幅よりも大きくなり、その影響が無視できなくなる場合がある。例えば、微細かつ立体的な構造を有するトランジスタでは、半導体の側面及び下面に形成されるチャネル領域の割合が大きくなる場合がある。その場合は、上面図において示される見かけ上のチャネル幅よりも、実際にチャネルの形成される実効的なチャネル幅の方が大きくなる。 Note that depending on the structure of the transistor, the channel width in a region where a channel is actually formed (hereinafter referred to as an effective channel width) and the channel width shown in a top view of the transistor (hereinafter, apparent channel width). May be different). For example, in a transistor having a three-dimensional structure, the effective channel width is larger than the apparent channel width shown in the top view of the transistor, and the influence may not be negligible. For example, in a transistor having a fine and three-dimensional structure, the ratio of channel regions formed on the side surface and the bottom surface of a semiconductor may increase. In that case, the effective channel width in which the channel is actually formed is larger than the apparent channel width shown in the top view.
　本明細書において、「平行」とは、二つの直線が−１０°以上１０°以下の角度で配置されている状態をいう。したがって、−５°以上５°以下の場合も含まれる。また、「略平行」とは、二つの直線が−３０°以上３０°以下の角度で配置されている状態をいう。また、「垂直」とは、二つの直線が８０°以上１００°以下の角度で配置されている状態をいう。したがって、８５°以上９５°以下の場合も含まれる。また、「略垂直」とは、二つの直線が６０°以上１２０°以下の角度で配置されている状態をいう。 In this specification, “parallel” means a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. Further, “substantially parallel” means a state in which two straight lines are arranged at an angle of −30 ° to 30 °. “Vertical” refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included. Further, “substantially vertical” means a state in which two straight lines are arranged at an angle of 60 ° to 120 °.
　また、本明細書において、結晶が三方晶または菱面体晶である場合、六方晶系として表す。 In this specification, when a crystal is a trigonal or rhombohedral crystal, it is expressed as a hexagonal system.
（実施の形態１）
　本実施の形態では、本発明の一態様に係る半導体装置の構成について、図１乃至図７を用いて説明する。 (Embodiment 1)
In this embodiment, a structure of a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS.
＜トランジスタの構成＞
　以下では、本発明の一態様に係る半導体装置の一例としてトランジスタの構成について説明する。 <Structure of transistor>
The structure of a transistor is described below as an example of a semiconductor device according to one embodiment of the present invention.
　図１（Ａ）乃至図１（Ｃ）を用いてトランジスタ１０の構成について説明する。図１（Ａ）はトランジスタ１０の上面図である。図１（Ｂ）は図１（Ａ）の一点鎖線Ａ１−Ａ２に対応する断面図であり、図１（Ｃ）は図１（Ａ）の一点鎖線Ａ３−Ａ４に対応する断面図である。なお、一点鎖線Ａ１−Ａ２で示す領域では、トランジスタ１０のチャネル長方向における構造を示しており、一点鎖線Ａ３−Ａ４で示す領域では、一点鎖線Ａ１−Ａ２に垂直な方向における構造を示している。なお、トランジスタのチャネル長方向とは、ソース（ソース領域またはソース電極）及びドレイン（ドレイン領域またはドレイン電極）間において、キャリアが移動する方向を意味する。また、図１（Ａ）、図１（Ｂ）において、図面が煩雑になることを避けるため、絶縁体１１２など一部の構造を省略して表現している。 1A to 1C, the structure of the transistor 10 is described. FIG. 1A is a top view of the transistor 10. 1B is a cross-sectional view corresponding to one-dot chain line A1-A2 in FIG. 1A, and FIG. 1C is a cross-sectional view corresponding to one-dot chain line A3-A4 in FIG. Note that a region indicated by an alternate long and short dash line A1-A2 indicates a structure in the channel length direction of the transistor 10, and a region indicated by an alternate long and short dash line A3-A4 indicates a structure in a direction perpendicular to the alternate long and short dashed line A1-A2. . Note that the channel length direction of a transistor means a direction in which carriers move between a source (source region or source electrode) and a drain (drain region or drain electrode). Further, in FIGS. 1A and 1B, some structures such as the insulator 112 are omitted in order to avoid complexity.
　トランジスタ１０は、環状に設けられた導電体１１４と、導電体１１４の環の内側を通して伸長した領域を有する半導体１０６ｂと、導電体１１４と半導体１０６ｂとの間に設けられた絶縁体１０６ａと、導電体１１４と絶縁体１０６ａとの間に設けられた絶縁体１１２と、導電体１１４の環の内側を通して設けられた導電体１０２と、を有する。ここで、導電体１０２は絶縁体１１２中に設けられている。また、半導体１０６ｂに接して、導電体１１４を間に挟んで対向して設けられた導電体１０８ａ及び導電体１０８ｂと、を有する。 The transistor 10 includes a conductor 114 provided in a ring shape, a semiconductor 106b having a region extending through the inside of the ring of the conductor 114, an insulator 106a provided between the conductor 114 and the semiconductor 106b, An insulator 112 provided between the body 114 and the insulator 106a, and a conductor 102 provided through the inside of the ring of the conductor 114. Here, the conductor 102 is provided in the insulator 112. In addition, a conductor 108a and a conductor 108b are provided to be in contact with the semiconductor 106b and face each other with the conductor 114 interposed therebetween.
　ここで、絶縁体１０６ａ及び絶縁体１１２は、絶縁膜又は絶縁層ということもできる。また、導電体１０２、導電体１０８ａ、導電体１０８ｂ及び導電体１１４は、導電膜又は導電層ということもできる。また、半導体１０６ｂは、半導体膜又は半導体層ということもできる。 Here, the insulator 106a and the insulator 112 can also be referred to as insulating films or insulating layers. The conductor 102, the conductor 108a, the conductor 108b, and the conductor 114 can also be referred to as conductive films or conductive layers. The semiconductor 106b can also be referred to as a semiconductor film or a semiconductor layer.
　なお、詳細は後述するが、絶縁体１０６ａは、単独で用いる場合、導電体、半導体または絶縁体として機能させることができる物質を用いる場合がある。しかしながら、半導体１０６ｂと接してトランジスタを形成する場合、電子は半導体１０６ｂ、および半導体１０６ｂと絶縁体１０６ａの界面近傍を流れ、絶縁体１０６ａは当該トランジスタのチャネルとして機能しない領域を有する。このため、本明細書などにおいては、絶縁体１０６ａを導電体及び半導体と記載せず、絶縁体と記載するものとする。 Note that although details will be described later, when the insulator 106a is used alone, a substance that can function as a conductor, a semiconductor, or an insulator may be used. However, when a transistor is formed in contact with the semiconductor 106b, electrons flow in the vicinity of the semiconductor 106b and the interface between the semiconductor 106b and the insulator 106a, and the insulator 106a has a region that does not function as a channel of the transistor. Therefore, in this specification and the like, the insulator 106a is not described as a conductor and a semiconductor but is described as an insulator.
　トランジスタ１０において、半導体１０６ｂは活性層として機能し、導電体１１４はゲート電極として機能し、絶縁体１１２はゲート絶縁膜として機能し、導電体１０８ａと導電体１０８ｂはソース電極またはドレイン電極として機能する。 In the transistor 10, the semiconductor 106b functions as an active layer, the conductor 114 functions as a gate electrode, the insulator 112 functions as a gate insulating film, and the conductor 108a and the conductor 108b function as a source electrode or a drain electrode. .
　半導体１０６ｂは、図１（Ｂ）に示すように、少なくとも導電体１１４の環の内側を通る部分において、伸長して設けられており、例えば紐状、棒状又は柱状などの形状をとる。また、図１（Ｃ）に示すように、半導体１０６ｂの伸長方向に略垂直な断面における断面形状は略円形状であることが好ましい。図１（Ｃ）における半導体１０６ｂの幅（半導体１０６ｂが円形なら直径と呼ぶこともできる）は、数ｎｍ乃至数十ｎｍ程度であり、例えば、１ｎｍ以上５０ｎｍ以下、好ましくは２ｎｍ以上３０ｎｍ以下とすればよい。なお、本明細書等において、略円形とは、真円だけでなく、楕円などの真円から外れた円形も含むものとする。 As shown in FIG. 1B, the semiconductor 106b is provided to extend at least in a portion passing through the inside of the ring of the conductor 114, and takes a shape such as a string shape, a rod shape, or a column shape. In addition, as illustrated in FIG. 1C, the cross-sectional shape in a cross section substantially perpendicular to the extending direction of the semiconductor 106b is preferably a substantially circular shape. The width of the semiconductor 106b in FIG. 1C (also referred to as a diameter if the semiconductor 106b is circular) is approximately several nm to several tens of nm, for example, 1 nm to 50 nm, preferably 2 nm to 30 nm. That's fine. Note that in this specification and the like, the substantially circular shape includes not only a perfect circle but also a circle deviated from a true circle such as an ellipse.
　このように、半導体１０６ｂは幅数ｎｍ乃至数十ｎｍ程度の細長いワイヤー状の構造体なので、ナノワイヤと呼ぶことができる。また、図１（Ａ）乃至（Ｃ）に示すように、絶縁体１０６ａ、導電体１０８ａ、導電体１０８ｂ、絶縁体１１２、導電体１０２及び導電体１１４を含めても細長いワイヤー状の構造体なので、これらを含めてナノワイヤと呼ぶこともできる。また、トランジスタ１０はナノワイヤを用いたトランジスタなので、ナノワイヤトランジスタと呼ぶこともできる。 Thus, since the semiconductor 106b is an elongated wire-like structure having a width of several nanometers to several tens of nanometers, it can be called a nanowire. Further, as shown in FIGS. 1A to 1C, the insulator 106a, the conductor 108a, the conductor 108b, the insulator 112, the conductor 102, and the conductor 114 are included in an elongated wire-like structure. These can also be called nanowires. Further, since the transistor 10 is a transistor using nanowires, it can also be called a nanowire transistor.
　絶縁体１０６ａは、図１（Ｂ）に示すように、半導体１０６ｂと導電体１１４が重なる領域の少なくとも一部において、半導体１０６ｂに接して設けられる。また、図１（Ｃ）に示すように、半導体１０６ｂの伸長方向（Ａ１−Ａ２方向）に略垂直な断面において、絶縁体１０６ａは半導体１０６ｂに接して同心円状に設けられる。 As shown in FIG. 1B, the insulator 106a is provided in contact with the semiconductor 106b in at least part of a region where the semiconductor 106b and the conductor 114 overlap. In addition, as illustrated in FIG. 1C, the insulator 106a is provided concentrically in contact with the semiconductor 106b in a cross section substantially perpendicular to the extending direction (A1-A2 direction) of the semiconductor 106b.
　導電体１０８ａ及び導電体１０８ｂは、図１（Ｂ）に示すように、側面が絶縁体１０６ａと接して、互いに対向して設けられることが好ましい。また、図示していないが、半導体１０６ｂの伸長方向（Ａ１−Ａ２方向）に略垂直な断面において、導電体１０８ａ及び導電体１０８ｂは半導体１０６ｂを包み込むように設けられることが好ましい。 As shown in FIG. 1B, the conductor 108a and the conductor 108b are preferably provided so that the side surfaces are in contact with the insulator 106a and face each other. Although not illustrated, the conductor 108a and the conductor 108b are preferably provided so as to surround the semiconductor 106b in a cross section substantially perpendicular to the extending direction (A1-A2 direction) of the semiconductor 106b.
　また、図１（Ｂ）に示すように、トランジスタ１０のチャネル長Ｌは、導電体１０８ａと導電体１０８ｂの距離となっている。導電体１０８ａと導電体１０８ｂの距離、すなわちトランジスタ１０のチャネル長Ｌは、数ｎｍ乃至数十ｎｍ程度とすればよく、例えば、２ｎｍ以上３０ｎｍ以下とすることが好ましい。 As shown in FIG. 1B, the channel length L of the transistor 10 is the distance between the conductor 108a and the conductor 108b. The distance between the conductor 108a and the conductor 108b, that is, the channel length L of the transistor 10 may be several nanometers to several tens of nanometers, for example, preferably 2 nm to 30 nm.
　また、図１（Ｂ）に示すように、導電体１０８ａ及び導電体１０８ｂの側面端部がテーパー形状を有することが好ましい。具体的には導電体１０８ａ及び導電体１０８ｂの側面端部の傾斜角θを３０°以上９０°未満、好ましくは４５°以上８０°未満、より好ましくは４５°以上６０°未満とする。このように、導電体１０８ａ及び導電体１０８ｂの側面端部をテーパー形状とすることで、より導電体１０８ａと導電体１０８ｂの距離を短くすることができ、トランジスタ１０のチャネル長Ｌを短くすることができる。 Further, as shown in FIG. 1B, it is preferable that side end portions of the conductor 108a and the conductor 108b have a tapered shape. Specifically, the inclination angle θ of the side end portions of the conductors 108a and 108b is 30 ° or more and less than 90 °, preferably 45 ° or more and less than 80 °, more preferably 45 ° or more and less than 60 °. In this manner, the side end portions of the conductor 108a and the conductor 108b are tapered, whereby the distance between the conductor 108a and the conductor 108b can be further shortened, and the channel length L of the transistor 10 can be shortened. Can do.
　導電体１１４は、図１（Ｂ）（Ｃ）に示すように、半導体１０６ｂ、絶縁体１０６ａ及び導電体１０２の少なくとも一部を囲むように環状に設けられている。なお、本明細書等において、環状とは、輪環だけでなく、多角環などの形状も含むものとする。または、導電体１１４は半導体１０６ｂ、絶縁体１０６ａ及び導電体１０２の少なくとも一部の周囲を囲むことができればよい。例えば、導電体１１４が閉路状の構造を含む構造とすればよい。ここで、導電体１１４は、半導体１０６ｂの導電体１０８ａと導電体１０８ｂに挟まれた領域（半導体１０６ｂのチャネル形成領域と呼ぶこともできる。）の少なくとも一部と重なるように形成されることが好ましい。 As shown in FIGS. 1B and 1C, the conductor 114 is provided in an annular shape so as to surround at least a part of the semiconductor 106b, the insulator 106a, and the conductor 102. In the present specification and the like, the term “annular” includes not only a ring but also a shape such as a polygonal ring. Alternatively, the conductor 114 only needs to surround at least part of the semiconductor 106b, the insulator 106a, and the conductor 102. For example, the conductor 114 may have a structure including a closed circuit structure. Here, the conductor 114 is formed so as to overlap with at least part of a region between the conductor 108a and the conductor 108b of the semiconductor 106b (also referred to as a channel formation region of the semiconductor 106b). preferable.
　絶縁体１１２は、絶縁体１０６ａと導電体１１４の間を埋めるように形成されることが好ましい。また、絶縁体１１２によって、半導体１０６ｂ、導電体１０２及び導電体１１４がそれぞれ絶縁されていることが好ましい。このため、絶縁体１１２を複数の絶縁体を組み合わせて形成してもよい。例えば、絶縁体１０６ａと導電体１０２の間に形成された絶縁体と、導電体１０２と導電体１１４の間に形成された絶縁体と、を組み合わせて絶縁体１１２としてもよい。 The insulator 112 is preferably formed so as to fill a space between the insulator 106a and the conductor 114. Further, it is preferable that the semiconductor 106b, the conductor 102, and the conductor 114 are insulated from each other by the insulator 112. Therefore, the insulator 112 may be formed by combining a plurality of insulators. For example, the insulator 112 may be formed by combining an insulator formed between the insulator 106a and the conductor 102 and an insulator formed between the conductor 102 and the conductor 114.
　導電体１０２は、導電体１１４の環の内側を通して設けられており、絶縁体１１２を介して絶縁体１０６ａと導電体１１４との間に形成されている。また、図１（Ｃ）に示すように、半導体１０６ｂの伸長方向（Ａ１−Ａ２方向）に略垂直な断面において、導電体１０２の幅は、例えば半導体１０６ｂの幅と同程度にすればよい。ただし、導電体１０２の幅はこれに限られず、適宜設定することができる。また、半導体１０６ｂの伸長方向（Ａ１−Ａ２方向）に略垂直な断面において、導電体１０２の形状は、半導体１０６ｂと同心円状の弧を有する形状としてもよい。ただし、導電体１０２の形状はこれに限られず、適宜設定することができる。 The conductor 102 is provided through the inside of the ring of the conductor 114, and is formed between the insulator 106 a and the conductor 114 via the insulator 112. In addition, as illustrated in FIG. 1C, the width of the conductor 102 may be approximately the same as the width of the semiconductor 106b, for example, in a cross section substantially perpendicular to the extending direction (A1-A2 direction) of the semiconductor 106b. However, the width of the conductor 102 is not limited to this, and can be set as appropriate. In the cross section substantially perpendicular to the extending direction (A1-A2 direction) of the semiconductor 106b, the shape of the conductor 102 may be a shape having a concentric arc with the semiconductor 106b. However, the shape of the conductor 102 is not limited to this, and can be set as appropriate.
　トランジスタ１０は基板上に設けられるが、基板の上面に対して半導体１０６ｂの伸長方向（Ａ１−Ａ２方向）が略平行になるようにトランジスタ１０を形成してもよい。また、基板の上面に対して半導体１０６ｂの伸長方向（Ａ１−Ａ２方向）が略垂直になるようにトランジスタ１０を形成してもよい。 The transistor 10 is provided over a substrate, but the transistor 10 may be formed so that the extending direction (A1-A2 direction) of the semiconductor 106b is substantially parallel to the upper surface of the substrate. Alternatively, the transistor 10 may be formed so that the extending direction (A1-A2 direction) of the semiconductor 106b is substantially perpendicular to the upper surface of the substrate.
＜半導体＞
　以下、半導体１０６ｂの詳細な構成について説明する。 <Semiconductor>
Hereinafter, a detailed configuration of the semiconductor 106b will be described.
　なお、本項目においては、半導体１０６ｂとともに絶縁体１０６ａの詳細な構成についても説明する。 In this item, the detailed structure of the insulator 106a as well as the semiconductor 106b will be described.
　半導体１０６ｂは、例えば、インジウムを含む酸化物半導体である。半導体１０６ｂは、例えば、インジウムを含むと、キャリア移動度（電子移動度）が高くなる。また、半導体１０６ｂは、元素Ｍを含むと好ましい。元素Ｍは、好ましくは、Ｔｉ、Ｇａ、Ｙ、Ｚｒ、Ｌａ、Ｃｅ、Ｎｄ、ＳｎまたはＨｆを表すとする。ただし、元素Ｍとして、前述の元素を複数組み合わせても構わない場合がある。元素Ｍは、例えば、酸素との結合エネルギーが高い元素である。例えば、酸素との結合エネルギーがインジウムよりも高い元素である。または、元素Ｍは、例えば、酸化物半導体のエネルギーギャップを大きくする機能を有する元素である。また、半導体１０６ｂは、亜鉛を含むと好ましい。酸化物半導体は、亜鉛を含むと結晶化しやすくなる場合がある。 The semiconductor 106b is an oxide semiconductor containing indium, for example. For example, when the semiconductor 106b contains indium, carrier mobility (electron mobility) increases. The semiconductor 106b preferably contains an element M. The element M preferably represents Ti, Ga, Y, Zr, La, Ce, Nd, Sn or Hf. However, the element M may be a combination of a plurality of the aforementioned elements. The element M is an element having a high binding energy with oxygen, for example. For example, it is an element whose binding energy with oxygen is higher than that of indium. Alternatively, the element M is an element having a function of increasing the energy gap of the oxide semiconductor, for example. The semiconductor 106b preferably contains zinc. An oxide semiconductor may be easily crystallized when it contains zinc.
　ただし、半導体１０６ｂは、インジウムを含む酸化物半導体に限定されない。半導体１０６ｂは、例えば、亜鉛スズ酸化物、ガリウムスズ酸化物などの、インジウムを含まず、亜鉛を含む酸化物半導体、ガリウムを含む酸化物半導体、スズを含む酸化物半導体などであっても構わない。 However, the semiconductor 106b is not limited to an oxide semiconductor containing indium. The semiconductor 106b may be an oxide semiconductor containing zinc, an oxide semiconductor containing gallium, an oxide semiconductor containing tin, or the like that does not contain indium, such as zinc tin oxide and gallium tin oxide.
　例えば、絶縁体１０６ａは、半導体１０６ｂを構成する酸素以外の元素一種以上、または二種以上から構成される酸化物半導体である。半導体１０６ｂを構成する酸素以外の元素一種以上、または二種以上から絶縁体１０６ａが構成されるため、絶縁体１０６ａと半導体１０６ｂとの界面において、欠陥準位が形成されにくい。 For example, the insulator 106a is an oxide semiconductor including one or more elements other than oxygen constituting the semiconductor 106b, or two or more elements. Since the insulator 106a includes one or more elements other than oxygen included in the semiconductor 106b, or two or more elements, a defect level is hardly formed at the interface between the insulator 106a and the semiconductor 106b.
　絶縁体１０６ａ及び半導体１０６ｂは、少なくともインジウムを含むと好ましい。なお、絶縁体１０６ａがＩｎ−Ｍ−Ｚｎ酸化物のとき、ＩｎおよびＭの和を１００ａｔｏｍｉｃ％としたとき、好ましくはＩｎが５０ａｔｏｍｉｃ％未満、Ｍが５０ａｔｏｍｉｃ％より高く、さらに好ましくはＩｎが２５ａｔｏｍｉｃ％未満、Ｍが７５ａｔｏｍｉｃ％より高いとする。また、半導体１０６ｂがＩｎ−Ｍ−Ｚｎ酸化物のとき、ＩｎおよびＭの和を１００ａｔｏｍｉｃ％としたとき、好ましくはＩｎが２５ａｔｏｍｉｃ％より高く、Ｍが７５ａｔｏｍｉｃ％未満、さらに好ましくはＩｎが３４ａｔｏｍｉｃ％より高く、Ｍが６６ａｔｏｍｉｃ％未満とする。ただし、絶縁体１０６ａがインジウムを含まなくても構わない場合がある。例えば、絶縁体１０６ａが酸化ガリウムであっても構わない。なお、絶縁体１０６ａ及び半導体１０６ｂに含まれる各元素の原子数が、簡単な整数比にならなくても構わない。 The insulator 106a and the semiconductor 106b preferably contain at least indium. Note that when the insulator 106a is an In—M—Zn oxide, when the sum of In and M is 100 atomic%, In is preferably less than 50 atomic%, M is higher than 50 atomic%, and more preferably In is 25 atomic%. And M is higher than 75 atomic%. In the case where the semiconductor 106b is an In-M-Zn oxide, when the sum of In and M is 100 atomic%, the In is preferably higher than 25 atomic%, the M is less than 75 atomic%, and more preferably, In is more than 34 atomic%. High, and M is less than 66 atomic%. Note that the insulator 106a may not contain indium in some cases. For example, the insulator 106a may be gallium oxide. Note that the number of atoms of each element included in the insulator 106a and the semiconductor 106b may not be a simple integer ratio.
　例えば、スパッタリング法を用いて成膜する場合、絶縁体１０６ａに用いるターゲットの金属元素の原子数比の代表例としては、Ｉｎ：Ｍ：Ｚｎ＝１：２：４、Ｉｎ：Ｍ：Ｚｎ＝１：３：２、Ｉｎ：Ｍ：Ｚｎ＝１：３：４、Ｉｎ：Ｍ：Ｚｎ＝１：３：６、Ｉｎ：Ｍ：Ｚｎ＝１：３：８、Ｉｎ：Ｍ：Ｚｎ＝１：４：３、Ｉｎ：Ｍ：Ｚｎ＝１：４：４、Ｉｎ：Ｍ：Ｚｎ＝１：４：５、Ｉｎ：Ｍ：Ｚｎ＝１：４：６、Ｉｎ：Ｍ：Ｚｎ＝１：６：３、Ｉｎ：Ｍ：Ｚｎ＝１：６：４、Ｉｎ：Ｍ：Ｚｎ＝１：６：５、Ｉｎ：Ｍ：Ｚｎ＝１：６：６、Ｉｎ：Ｍ：Ｚｎ＝１：６：７、Ｉｎ：Ｍ：Ｚｎ＝１：６：８、Ｉｎ：Ｍ：Ｚｎ＝１：６：９等がある。 For example, in the case where a film is formed by a sputtering method, typical examples of the atomic ratio of the metal element of the target used for the insulator 106a include In: M: Zn = 1: 2: 4, In: M: Zn = 1. : 3: 2, In: M: Zn = 1: 3: 4, In: M: Zn = 1: 3: 6, In: M: Zn = 1: 3: 8, In: M: Zn = 1: 4. : 3, In: M: Zn = 1: 4: 4, In: M: Zn = 1: 4: 5, In: M: Zn = 1: 4: 6, In: M: Zn = 1: 6: 3 In: M: Zn = 1: 6: 4, In: M: Zn = 1: 6: 5, In: M: Zn = 1: 6: 6, In: M: Zn = 1: 6: 7, In : M: Zn = 1: 6: 8, In: M: Zn = 1: 6: 9, and the like.
　また、例えば、スパッタリング法を用いて成膜する場合、半導体１０６ｂに用いるターゲットの金属元素の原子数比の代表例としては、Ｉｎ：Ｍ：Ｚｎ＝１：１：１、Ｉｎ：Ｍ：Ｚｎ＝１：１：１．２、Ｉｎ：Ｍ：Ｚｎ＝２：１：１．５、Ｉｎ：Ｍ：Ｚｎ＝２：１：２．３、Ｉｎ：Ｍ：Ｚｎ＝２：１：３、Ｉｎ：Ｍ：Ｚｎ＝３：１：２、Ｉｎ：Ｍ：Ｚｎ＝４：２：４．１等がある。特に、スパッタリングターゲットとして、原子数比がＩｎ：Ｇａ：Ｚｎ＝４：２：４．１を用いる場合、成膜される半導体１０６ｂの原子数比は、Ｉｎ：Ｇａ：Ｚｎ＝４：２：３近傍となる場合がある。 For example, when a film is formed by a sputtering method, typical examples of the atomic ratio of the metal element of the target used for the semiconductor 106b are In: M: Zn = 1: 1: 1, In: M: Zn = 1: 1: 1.2, In: M: Zn = 2: 1: 1.5, In: M: Zn = 2: 1: 2.3, In: M: Zn = 2: 1: 3, In: M: Zn = 3: 1: 2, In: M: Zn = 4: 2: 4.1, and the like. In particular, when an atomic ratio of In: Ga: Zn = 4: 2: 4.1 is used as a sputtering target, the atomic ratio of the semiconductor 106b to be formed is In: Ga: Zn = 4: 2: 3. May be near.
　半導体１０６ｂは、例えば、エネルギーギャップが大きい酸化物を用いる。半導体１０６ｂのエネルギーギャップは、例えば、２．５ｅＶ以上４．２ｅＶ以下、好ましくは２．８ｅＶ以上３．８ｅＶ以下、さらに好ましくは３ｅＶ以上３．５ｅＶ以下とする。ここで、絶縁体１０６ａのエネルギーギャップは、半導体１０６ｂのエネルギーギャップより大きい。 For example, an oxide having a large energy gap is used for the semiconductor 106b. The energy gap of the semiconductor 106b is, for example, 2.5 eV to 4.2 eV, preferably 2.8 eV to 3.8 eV, and more preferably 3 eV to 3.5 eV. Here, the energy gap of the insulator 106a is larger than the energy gap of the semiconductor 106b.
　半導体１０６ｂは、絶縁体１０６ａよりも電子親和力の大きい酸化物を用いる。例えば、半導体１０６ｂとして、絶縁体１０６ａよりも電子親和力の０．０７ｅＶ以上１．３ｅＶ以下、好ましくは０．１ｅＶ以上０．７ｅＶ以下、さらに好ましくは０．１５ｅＶ以上０．４ｅＶ以下大きい酸化物を用いる。なお、電子親和力は、真空準位と伝導帯下端のエネルギーとの差である。言い換えると、絶縁体１０６ａの伝導帯下端のエネルギー準位は、半導体１０６ｂの伝導帯下端のエネルギー準位より真空準位に近い。 As the semiconductor 106b, an oxide having an electron affinity higher than that of the insulator 106a is used. For example, as the semiconductor 106b, an oxide having an electron affinity higher than that of the insulator 106a by 0.07 eV to 1.3 eV, preferably 0.1 eV to 0.7 eV, more preferably 0.15 eV to 0.4 eV is used. . Note that the electron affinity is the difference between the vacuum level and the energy at the bottom of the conduction band. In other words, the energy level at the lower end of the conduction band of the insulator 106a is closer to the vacuum level than the energy level at the lower end of the conduction band of the semiconductor 106b.
　このとき、ゲート電圧を印加すると、絶縁体１０６ａ及び半導体１０６ｂのうち、電子親和力の大きい半導体１０６ｂにチャネルが形成される。なお、高いゲート電圧を印加すると、絶縁体１０６ａの半導体１０６ｂとの界面近傍においても電流が流れる場合がある。 At this time, when a gate voltage is applied, a channel is formed in the semiconductor 106b having a high electron affinity among the insulator 106a and the semiconductor 106b. Note that when a high gate voltage is applied, current may flow also in the vicinity of the interface between the insulator 106a and the semiconductor 106b.
　上記の通り、絶縁体１０６ａは、単独で用いる場合、導電体、半導体または絶縁体として機能させることができる物質からなる。しかしながら、半導体１０６ｂと積層させてトランジスタを形成する場合、電子は半導体１０６ｂ、または半導体１０６ｂと絶縁体１０６ａの界面近傍を流れ、絶縁体１０６ａは当該トランジスタのチャネルとして機能しない領域を有する。このため、本明細書などにおいては、絶縁体１０６ａを半導体と記載せず、絶縁体と記載するものとする。なお、絶縁体１０６ａを絶縁体と記載するのは、あくまで半導体１０６ｂと比較してトランジスタの機能上絶縁体に近い機能を有するためなので、絶縁体１０６ａとして、半導体１０６ｂに用いることができる物質を用いる場合もある。 As described above, the insulator 106a is made of a substance that can function as a conductor, a semiconductor, or an insulator when used alone. However, when a transistor is formed by stacking with the semiconductor 106b, electrons flow in the vicinity of the semiconductor 106b or the interface between the semiconductor 106b and the insulator 106a, and the insulator 106a has a region that does not function as a channel of the transistor. Therefore, in this specification and the like, the insulator 106a is not described as a semiconductor but is described as an insulator. Note that the insulator 106a is described as an insulator because it has a function similar to that of an insulator compared to the semiconductor 106b, and thus a substance that can be used for the semiconductor 106b is used as the insulator 106a. In some cases.
　ここで、絶縁体１０６ａと半導体１０６ｂとの間には、絶縁体１０６ａと半導体１０６ｂとの混合領域を有する場合がある。混合領域は、欠陥準位密度が低くなる。そのため、絶縁体１０６ａと半導体１０６ｂの界面近傍において、エネルギーが連続的に変化する（連続接合ともいう。）バンド図となる（図８参照。）。なお、絶縁体１０６ａと半導体１０６ｂは、それぞれの界面を明確に判別できない場合がある。 Here, there may be a mixed region of the insulator 106a and the semiconductor 106b between the insulator 106a and the semiconductor 106b. The mixed region has a low density of defect states. Therefore, energy continuously changes (also referred to as a continuous junction) in the vicinity of the interface between the insulator 106a and the semiconductor 106b (see FIG. 8). Note that in some cases, the interface between the insulator 106a and the semiconductor 106b cannot be clearly distinguished.
　このとき、電子は、絶縁体１０６ａ中ではなく、半導体１０６ｂ中を主として移動する。上述したように、絶縁体１０６ａと半導体１０６ｂとの界面における欠陥準位密度を低くすることによって、半導体１０６ｂ中で電子の移動が阻害されることが少なく、トランジスタのオン電流を高くすることができる。 At this time, electrons move mainly in the semiconductor 106b, not in the insulator 106a. As described above, by reducing the defect level density at the interface between the insulator 106a and the semiconductor 106b, electron movement is hardly inhibited in the semiconductor 106b, and the on-state current of the transistor can be increased. .
　本実施の形態に示す絶縁体１０６ａ及び半導体１０６ｂ、特に半導体１０６ｂは、不純物濃度が低く、欠陥準位密度の低い（酸素欠損の少ない）酸化物半導体であり、高純度真性または実質的に高純度真性な酸化物半導体と呼ぶことができる。高純度真性または実質的に高純度真性である酸化物半導体は、キャリア発生源が少ないため、キャリア密度を低くすることができる。従って、該酸化物半導体にチャネル領域が形成されるトランジスタは、しきい値電圧がマイナスとなる電気特性（ノーマリーオンともいう。）になることが少ない。また、高純度真性または実質的に高純度真性である酸化物半導体は、欠陥準位密度が低いため、トラップ準位密度も低くなる場合がある。さらに、高純度真性または実質的に高純度真性である酸化物半導体は、オフ電流が著しく小さく、チャネル幅Ｗが１×１０６μｍでチャネル長Ｌが１０μｍの素子であっても、ソース電極とドレイン電極間の電圧（ドレイン電圧）が１Ｖから１０Ｖの範囲において、オフ電流が、半導体パラメータアナライザの測定限界以下、すなわち１×１０−１３Ａ以下という特性を得ることができる。 The insulator 106a and the semiconductor 106b, particularly the semiconductor 106b described in this embodiment are oxide semiconductors with low impurity concentration and low defect state density (low oxygen vacancies), and have high purity intrinsic or substantially high purity. It can be called an intrinsic oxide semiconductor. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has few carrier generation sources, and thus can have a low carrier density. Therefore, a transistor in which a channel region is formed in the oxide semiconductor rarely has electrical characteristics (also referred to as normally-on) in which the threshold voltage is negative. In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has a low density of defect states, and thus may have a low density of trap states. Further, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has an extremely small off-state current, an element having a channel width W of 1 × 10 6 μm and a channel length L of 10 μm. When the voltage between the drain electrodes (drain voltage) is in the range of 1V to 10V, it is possible to obtain a characteristic that the off-current is less than the measurement limit of the semiconductor parameter analyzer, that is, 1 × 10 −13 A or less.
　したがって、上記高純度真性、または実質的に高純度真性の酸化物半導体にチャネル領域が形成されるトランジスタは、電気特性の変動が小さく、信頼性の高いトランジスタとすることができる。なお、酸化物半導体のトラップ準位に捕獲された電荷は、消失するまでに要する時間が長く、あたかも固定電荷のように振る舞うことがある。そのため、トラップ準位密度の高い酸化物半導体にチャネル領域が形成されるトランジスタは、電気特性が不安定となる場合がある。不純物としては、水素、窒素、アルカリ金属、またはアルカリ土類金属等がある。 Therefore, a transistor in which a channel region is formed in the high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor can have a small variation in electrical characteristics and be a highly reliable transistor. Note that the charge trapped in the trap level of the oxide semiconductor takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel region is formed in an oxide semiconductor with a high trap state density may have unstable electrical characteristics. Examples of impurities include hydrogen, nitrogen, alkali metals, and alkaline earth metals.
　絶縁体１０６ａ及び半導体１０６ｂに含まれる水素は、金属原子と結合する酸素と反応して水になると共に、酸素が脱離した格子（または酸素が脱離した部分）に酸素欠損を形成する。該酸素欠損に水素が入ることで、キャリアである電子が生成される場合がある。また、水素の一部が金属原子と結合する酸素と結合して、キャリアである電子を生成することがある。特に酸素欠損にトラップされた水素は、半導体のバンド構造に対して浅いドナー準位を形成することがある。従って、水素が含まれている酸化物半導体を用いたトランジスタはノーマリーオン特性となりやすい。このため、絶縁体１０６ａ及び半導体１０６ｂは水素ができる限り低減されていることが好ましい。具体的には、絶縁体１０６ａ及び半導体１０６ｂにおいて、二次イオン質量分析法（ＳＩＭＳ：Ｓｅｃｏｎｄａｒｙ　Ｉｏｎ　Ｍａｓｓ　Ｓｐｅｃｔｒｏｍｅｔｒｙ）により得られる水素濃度を、２×１０２０ａｔｏｍｓ／ｃｍ３以下、好ましくは５×１０１９ａｔｏｍｓ／ｃｍ３以下、より好ましくは１×１０１９ａｔｏｍｓ／ｃｍ３以下、５×１０１８ａｔｏｍｓ／ｃｍ３以下、好ましくは１×１０１８ａｔｏｍｓ／ｃｍ３以下、より好ましくは５×１０１７ａｔｏｍｓ／ｃｍ３以下、さらに好ましくは１×１０１６ａｔｏｍｓ／ｃｍ３以下とする。 Hydrogen contained in the insulator 106a and the semiconductor 106b reacts with oxygen bonded to a metal atom to be water, and forms oxygen vacancies in a lattice from which oxygen is released (or a portion from which oxygen is released). When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. In addition, a part of hydrogen may be combined with oxygen bonded to a metal atom to generate electrons as carriers. In particular, hydrogen trapped in oxygen vacancies may form a shallow donor level with respect to a semiconductor band structure. Therefore, a transistor including an oxide semiconductor containing hydrogen is likely to be normally on. Therefore, the insulator 106a and the semiconductor 106b are preferably reduced as much as possible. Specifically, in the insulator 106a and the semiconductor 106b, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) is 2 × 10 20 atoms / cm 3 or less, preferably 5 × 10 19. atoms / cm 3 or lower, more preferably 1 × 10 19 atoms / cm 3 or lower, 5 × 10 18 atoms / cm 3 or lower, preferably 1 × 10 18 atoms / cm 3 or lower, more preferably 5 × 10 17 atoms / cm 3 or lower. cm 3 or less, more preferably 1 × 10 16 atoms / cm 3 or less.
　絶縁体１０６ａ及び半導体１０６ｂにおいて、第１４族元素の一つであるシリコンや炭素が含まれると、絶縁体１０６ａ及び半導体１０６ｂにおいて酸素欠損が増加し、ｎ型化してしまう。このため、絶縁体１０６ａ及び半導体１０６ｂにおけるシリコンや炭素の濃度と絶縁体１０６ａ及び半導体１０６ｂとの界面近傍のシリコンや炭素の濃度（ＳＩＭＳ分析により得られる濃度）を、２×１０１８ａｔｏｍｓ／ｃｍ３以下、好ましくは２×１０１７ａｔｏｍｓ／ｃｍ３以下とする。 If the insulator 106a and the semiconductor 106b contain silicon or carbon which is one of Group 14 elements, oxygen vacancies increase in the insulator 106a and the semiconductor 106b, and the n-type structure is obtained. Therefore, the concentration of silicon or carbon in the insulator 106a and the semiconductor 106b and the concentration of silicon or carbon in the vicinity of the interface between the insulator 106a and the semiconductor 106b (concentration obtained by SIMS analysis) are 2 × 10 18 atoms / cm 3. Hereinafter, it is preferably 2 × 10 17 atoms / cm 3 or less.
　また、絶縁体１０６ａ及び半導体１０６ｂにおいて、ＳＩＭＳ分析により得られるアルカリ金属またはアルカリ土類金属の濃度を、１×１０１８ａｔｏｍｓ／ｃｍ３以下、好ましくは２×１０１６ａｔｏｍｓ／ｃｍ３以下にする。アルカリ金属及びアルカリ土類金属は、酸化物半導体と結合するとキャリアを生成する場合があり、トランジスタのオフ電流が増大してしまうことがある。このため、絶縁体１０６ａ及び半導体１０６ｂのアルカリ金属またはアルカリ土類金属の濃度を低減することが好ましい。 In the insulator 106a and the semiconductor 106b, the concentration of alkali metal or alkaline earth metal obtained by SIMS analysis is set to 1 × 10 18 atoms / cm 3 or lower, preferably 2 × 10 16 atoms / cm 3 or lower. When an alkali metal and an alkaline earth metal are combined with an oxide semiconductor, carriers may be generated, and the off-state current of the transistor may be increased. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the insulator 106a and the semiconductor 106b.
　また、絶縁体１０６ａ及び半導体１０６ｂに窒素が含まれていると、キャリアである電子が生じ、キャリア密度が増加し、ｎ型化しやすい。この結果、窒素が含まれている酸化物半導体膜を用いたトランジスタはノーマリーオン特性となりやすい。従って、半導体１０６ｂにおいて、窒素はできる限り低減されていることが好ましい、例えば、ＳＩＭＳ分析により得られる窒素濃度は、５×１０１８ａｔｏｍｓ／ｃｍ３以下にすることが好ましい。 In addition, when the insulator 106a and the semiconductor 106b contain nitrogen, electrons as carriers are generated, the carrier density is increased, and the n-type is easily obtained. As a result, a transistor including an oxide semiconductor film containing nitrogen is likely to be normally on. Therefore, in the semiconductor 106b, nitrogen is preferably reduced as much as possible. For example, the nitrogen concentration obtained by SIMS analysis is preferably 5 × 10 18 atoms / cm 3 or less.
　また、半導体１０６ｂなどの導電体１０８ａ又は導電体１０８ｂと接する界面近傍に低抵抗領域が形成されることがある。低抵抗領域は、主に、半導体１０６ｂが接した導電体１０８ａ又は導電体１０８ｂに酸素を引き抜かれる、または導電体１０８ａ又は導電体１０８ｂに含まれる導電材料が半導体１０６ｂ中の元素と結合することにより形成される。このような低抵抗領域が形成されることにより、導電体１０８ａ又は導電体１０８ｂと半導体１０６ｂとの接触抵抗を低減することが可能となるのでトランジスタ１０のオン電流を増大させることができる。 In addition, a low resistance region may be formed in the vicinity of the interface in contact with the conductor 108a or the conductor 108b such as the semiconductor 106b. The low-resistance region is mainly formed by oxygen being extracted from the conductor 108a or the conductor 108b with which the semiconductor 106b is in contact or a conductive material contained in the conductor 108a or the conductor 108b is bonded to an element in the semiconductor 106b. It is formed. By forming such a low-resistance region, the contact resistance between the conductor 108a or 108b and the semiconductor 106b can be reduced, so that the on-state current of the transistor 10 can be increased.
　なお、上述の絶縁体１０６ａ及び半導体１０６ｂの２層構造は一例である。例えば、絶縁体１０６ａを設けない単層構造としてもよいし、絶縁体１０６ａまたは半導体１０６ｂとして例示した絶縁体、半導体又は導電体のいずれかをさらに有するｎ層構造（ｎは３以上の整数）としても構わない。 Note that the above two-layer structure of the insulator 106a and the semiconductor 106b is an example. For example, a single-layer structure without the insulator 106a may be used, or an n-layer structure (n is an integer of 3 or more) further including any of the insulators, semiconductors, and conductors exemplified as the insulator 106a or the semiconductor 106b. It doesn't matter.
　なお、酸化物半導体の構造については、後述する実施の形態において詳細に説明を行う。 Note that the structure of the oxide semiconductor will be described in detail in an embodiment described later.
＜チャネル部のポテンシャルの計算＞
　ここで、酸化物半導体膜を用いたトランジスタのモデルについて数値計算を行って、チャネル部のポテンシャル障壁の高さについて評価した結果について説明する。 <Calculation of channel potential>
Here, the result of evaluating the height of the potential barrier in the channel portion by performing numerical calculation on a transistor model using an oxide semiconductor film will be described.
　図９に数値計算に用いたトランジスタのモデルの模式図を示す。図９に示すように、数値計算に用いたモデルでは、ソース電極とドレイン電極の間に半導体膜が形成され、ソース電極、半導体膜及びドレイン電極の上にゲート絶縁膜が形成され、ゲート絶縁膜の上にゲート電極が形成される。なお、図９中の、εＳは半導体膜の誘電率、εＯＸはゲート絶縁膜の誘電率、ｔＳは半導体膜の厚さ、ｔＯＸはゲート絶縁膜の厚さである。数値計算では、εＳの比誘電率を１５、εｏｘの比誘電率を４．１とし、真空の誘電率を８．８５４１８７８１７×１０−１２Ｆ／ｍとした。また、ｔＳを１５ｎｍ、ｔＯＸを１０ｎｍとした。また、ソース電極とドレイン電極の距離（チャネル長）をＬとする。 FIG. 9 is a schematic diagram of a transistor model used for numerical calculation. As shown in FIG. 9, in the model used for the numerical calculation, a semiconductor film is formed between the source electrode and the drain electrode, a gate insulating film is formed on the source electrode, the semiconductor film, and the drain electrode. A gate electrode is formed on the substrate. In FIG. 9, ε S is the dielectric constant of the semiconductor film, ε OX is the dielectric constant of the gate insulating film, t S is the thickness of the semiconductor film, and t OX is the thickness of the gate insulating film. In the numerical calculation, the relative dielectric constant of ε S was 15, the relative dielectric constant of ε ox was 4.1, and the dielectric constant of vacuum was 8.854187817 × 10 −12 F / m. Further, t S was set to 15 nm and t OX was set to 10 nm. Further, L is the distance (channel length) between the source electrode and the drain electrode.
　図９に示すトランジスタについて、図中に斜線で示した、チャネル部となる半導体膜中の微小な区間ｘ乃至ｘ＋ｄｘにガウスの法則を適用する。ここで酸化物半導体膜を用いたトランジスタは、ｎチャネル型の蓄積型のトランジスタであり、以下の式（１）で表される。 For the transistor shown in FIG. 9, Gauss's law is applied to the minute sections x to x + dx in the semiconductor film to be the channel portion, which are indicated by hatching in the drawing. Here, a transistor including an oxide semiconductor film is an n-channel storage transistor and is represented by the following formula (1).
Figure JPOXMLDOC01-appb-M000001
Figure JPOXMLDOC01-appb-M000001
　ここで、φ（ｘ）は位置ｘにおけるポテンシャル（表面ポテンシャル）、φ（ｘ＋ｄｘ）は位置ｘ＋ｄｘにおけるポテンシャル（表面ポテンシャル）、ＶＧはゲート電圧、ＶＦＢはフラット・バンド電圧、ｅは素電荷、ＮＣは実効状態密度、ｋＢはボルツマン定数、Ｔは絶対温度である。数値計算では、ＶＧ＝０Ｖ、ＶＦＢ＝０．４Ｖ、ＮＣ＝５．００×１０１８個／ｃｍ３、Ｔ＝３００Ｋとした。 Where φ (x) is the potential at the position x (surface potential), φ (x + dx) is the potential at the position x + dx (surface potential), V G is the gate voltage, V FB is the flat band voltage, e is the elementary charge, N C is the effective state density, k B is the Boltzmann constant, and T is the absolute temperature. In the numerical calculation, V G = 0V, V FB = 0.4V, N C = 5.00 × 10 18 pieces / cm 3 , and T = 300K.
　また、比較対象として、ｎチャネル型の反転型のトランジスタを想定すると、当該トランジスタでは、以下の式（２）で表される。 Assuming an n-channel inversion transistor as a comparison target, the transistor is represented by the following formula (2).
Figure JPOXMLDOC01-appb-M000002
Figure JPOXMLDOC01-appb-M000002
　ここで、ＮＡはアクセプター密度であり、数値計算ではＮＡ＝１．００×１０８個／ｃｍ３とした。 Here, N A is the acceptor density, was N A = 1.00 × 10 8 pieces / cm 3 is numerically.
　以上の式（１）及び式（２）を変形するとポアソン方程式が得られる。当該ポアソン方程式を数値計算してチャネル部分のポテンシャルを解析した。蓄積型の式（１）及び反転型の式（２）それぞれにおいて、Ｌ＝１μｍ、３００ｎｍ、１００ｎｍ、６０ｎｍ、３０ｎｍ及び１０ｎｍのモデルについて数値計算を行った。なお、ガウス・ザイデル法に従って、数値計算を行った。 Poisson's equation can be obtained by transforming the above equations (1) and (2). The Poisson equation was numerically calculated to analyze the channel potential. In the accumulation type equation (1) and the inversion type equation (2), numerical calculations were performed for models of L = 1 μm, 300 nm, 100 nm, 60 nm, 30 nm, and 10 nm. The numerical calculation was performed according to the Gauss-Seidel method.
　図１０（Ａ）及び図１０（Ｂ）に蓄積型のチャネル部のポテンシャル及び反転型のチャネル部のポテンシャルの数値計算の結果を示す。図１０（Ａ）及び図１０（Ｂ）は、横軸にｘ［ｎｍ］をとり、縦軸に−ｅφ（ｘ）［ｅＶ］をとる。また、図１０（Ｃ）及び図１０（Ｄ）に、図１０（Ａ）及び図１０（Ｂ）の横軸ｘをＬで規格化したグラフを示す。 FIG. 10A and FIG. 10B show the results of numerical calculation of the potential of the storage channel portion and the potential of the inversion channel portion. 10A and 10B, the horizontal axis represents x [nm] and the vertical axis represents −eφ (x) [eV]. 10C and 10D show graphs obtained by normalizing the horizontal axis x in FIGS. 10A and 10B with L. FIG.
　図１０（Ａ）（Ｃ）と図１０（Ｂ）（Ｄ）を比較すると、Ｌ＝１μｍ、３００ｎｍ及び１００ｎｍのモデルでは、ポテンシャルがほぼ同程度である。これに対して、Ｌ＝６０ｎｍ、３０ｎｍ及び１０ｎｍのモデルでは、蓄積型のモデルのポテンシャルが反転型のモデルのポテンシャルより大きくなっており、Ｌが短くなるにつれてその傾向が顕著に表れている。 10A, 10C, 10B, and 10D, the potentials are almost the same in the models of L = 1 μm, 300 nm, and 100 nm. On the other hand, in the models with L = 60 nm, 30 nm, and 10 nm, the potential of the accumulation type model is larger than the potential of the inversion type model, and this tendency becomes more prominent as L becomes shorter.
　このように、Ｌ＝１００ｎｍ未満のチャネル長が短いトランジスタにおいて、酸化物半導体膜を用いた蓄積型トランジスタは、シリコンなどの反転型トランジスタよりも、ＶＧ＝０Ｖでのバリア障壁が高いことが示された。よって、酸化物半導体膜を用いた蓄積型トランジスタでは、Ｌ＝１００ｎｍ未満のチャネル長が短い構造においても、しきい値電圧を０Ｖより大きくすることができる。つまり、酸化物半導体膜を用いた蓄積型トランジスタは、シリコンなどの反転型トランジスタよりも、短チャネル効果に対する耐性を有しているということができる。 Thus, in a transistor with a short channel length of less than L = 100 nm, an accumulation type transistor using an oxide semiconductor film has a higher barrier barrier at V G = 0 V than an inversion type transistor such as silicon. It was done. Therefore, in a storage transistor using an oxide semiconductor film, the threshold voltage can be higher than 0 V even in a structure with a short channel length of L = 100 nm. That is, it can be said that a storage transistor using an oxide semiconductor film has higher resistance to a short channel effect than an inversion transistor such as silicon.
　また、上記実施の形態に示すように、ＯＳ膜中の不純物濃度を低減し、高純度真性または実質的に高純度真性にことで、さらにキャリア密度を低減させることができるので、より短チャネル効果に対する耐性を強くすることができる。 Further, as shown in the above embodiment mode, the carrier density can be further reduced by reducing the impurity concentration in the OS film and making it highly purified intrinsic or substantially highly purified intrinsic. It is possible to increase the resistance to.
　さらに、本実施の形態に示すように、酸化物半導体膜をゲート電極で囲む構造のトランジスタを形成することで、より短チャネル効果に耐性を有するトランジスタを形成することができる。例えば、チャネル長を２ｎｍ乃至３０ｎｍ程度としても、良好なオフ電流特性を得られることが推測される。 Further, as shown in this embodiment, by forming a transistor having a structure in which an oxide semiconductor film is surrounded by a gate electrode, a transistor having resistance to a short channel effect can be formed. For example, it is estimated that good off-current characteristics can be obtained even when the channel length is about 2 nm to 30 nm.
＜絶縁体、導電体＞
　以下に、トランジスタ１０の半導体以外の各構成要素について詳細な説明を行う。 <Insulator, conductor>
Hereinafter, each component other than the semiconductor of the transistor 10 will be described in detail.
　導電体１０２は、半導体１０６ｂの導電体１０８ａと導電体１０８ｂに挟まれる領域において、少なくとも一部が重なることが好ましい。導電体１０２は、トランジスタ１０のバックゲートとして機能する。このような導電体１０２を設けることにより、トランジスタ１０のしきい値電圧の制御を行うことができる。しきい値電圧の制御を行うことによって、トランジスタ１０のゲート（導電体１１４）に印加された電圧が低い、例えば印加された電圧が０Ｖ以下のときに、トランジスタ１０が導通状態となることを防ぐことができる。つまり、トランジスタ１０の電気特性を、よりノーマリーオフの方向にシフトさせることが容易になる。 The conductor 102 preferably overlaps at least partially in a region sandwiched between the conductor 108a and the conductor 108b of the semiconductor 106b. The conductor 102 functions as a back gate of the transistor 10. By providing such a conductor 102, the threshold voltage of the transistor 10 can be controlled. By controlling the threshold voltage, the transistor 10 is prevented from becoming conductive when the voltage applied to the gate (conductor 114) of the transistor 10 is low, for example, when the applied voltage is 0 V or less. be able to. That is, it becomes easier to shift the electrical characteristics of the transistor 10 in a normally-off direction.
　導電体１０２としては、例えば、ホウ素、窒素、酸素、フッ素、シリコン、リン、アルミニウム、チタン、クロム、マンガン、コバルト、ニッケル、銅、亜鉛、ガリウム、イットリウム、ジルコニウム、モリブデン、ルテニウム、銀、インジウム、スズ、タンタルおよびタングステンを一種以上含む導電体を、単層で、または積層で用いればよい。例えば、合金や化合物であってもよく、アルミニウムを含む導電体、銅およびチタンを含む導電体、銅およびマンガンを含む導電体、インジウム、スズおよび酸素を含む導電体、チタンおよび窒素を含む導電体などを用いてもよい。 Examples of the conductor 102 include boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, A conductor containing one or more of tin, tantalum, and tungsten may be used in a single layer or a stacked layer. For example, it may be an alloy or a compound, a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin and oxygen, a conductor containing titanium and nitrogen Etc. may be used.
　絶縁体１１２は、トランジスタ１０において、導電体１１４及び導電体１０２に対してゲート絶縁膜として機能する。絶縁体１１２は過剰酸素を有する絶縁体であることが好ましい。例えば、絶縁体１１２としては、例えば、ホウ素、炭素、窒素、酸素、フッ素、マグネシウム、アルミニウム、シリコン、リン、塩素、アルゴン、ガリウム、ゲルマニウム、イットリウム、ジルコニウム、ランタン、ネオジム、ハフニウムまたはタンタルを含む絶縁体を、単層で、または積層で用いればよい。例えば、絶縁体１１２としては、酸化アルミニウム、酸化マグネシウム、酸化シリコン、酸化窒化シリコン、窒化酸化シリコン、窒化シリコン、酸化ガリウム、酸化ゲルマニウム、酸化イットリウム、酸化ジルコニウム、酸化ランタン、酸化ネオジム、酸化ハフニウムまたは酸化タンタルを用いればよい。好ましくは、酸化シリコンまたは酸化窒化シリコンを用いる。 The insulator 112 functions as a gate insulating film with respect to the conductor 114 and the conductor 102 in the transistor 10. The insulator 112 is preferably an insulator having excess oxygen. For example, the insulator 112 includes, for example, an insulating material including boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. The body may be used in a single layer or a stack. For example, as the insulator 112, aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or oxide Tantalum may be used. Preferably, silicon oxide or silicon oxynitride is used.
　過剰酸素を有する絶縁体１１２を設けることにより、絶縁体１１２から絶縁体１０６ａ及び半導体１０６ｂに酸素を供給することができる。当該酸素により、絶縁体１０６ａ及び半導体１０６ｂの欠陥となる酸素欠損を低減することができる。これにより、絶縁体１０６ａ及び半導体１０６ｂの欠陥準位密度を低減することができる。 By providing the insulator 112 having excess oxygen, oxygen can be supplied from the insulator 112 to the insulator 106a and the semiconductor 106b. With this oxygen, oxygen vacancies that are defects in the insulator 106a and the semiconductor 106b can be reduced. Accordingly, the density of defect states in the insulator 106a and the semiconductor 106b can be reduced.
　なお、本明細書などにおいて、過剰酸素とは、例えば、化学量論的組成を超えて含まれる酸素をいう。または、過剰酸素とは、例えば、加熱することで当該過剰酸素が含まれる膜又は層から放出される酸素をいう。過剰酸素は、例えば、膜や層の内部を移動することができる。過剰酸素の移動は、膜や層の原子間を移動する場合や、膜や層を構成する酸素と置き換わりながら玉突き的に移動する場合などがある。 In addition, in this specification etc., excess oxygen means the oxygen contained exceeding a stoichiometric composition, for example. Alternatively, excess oxygen refers to, for example, oxygen released from a film or layer containing excess oxygen by heating. Excess oxygen can move, for example, inside a film or layer. Excess oxygen may be moved between atoms of a film or layer, or may be moved in a rushing manner while replacing oxygen constituting the film or layer.
　過剰酸素を有する絶縁体１１２は、昇温脱離ガス分光法分析（ＴＤＳ分析）にて、１００℃以上７００℃以下または１００℃以上５００℃以下の表面温度の範囲で、酸素分子の脱離量が１．０×１０１４ｍｏｌｅｃｕｌｅ／ｃｍ２以上１．０×１０１６ｍｏｌｅｃｕｌｅ／ｃｍ２以下、より好ましくは、１．０×１０１５ｍｏｌｅｃｕｌｅ／ｃｍ２以上５．０×１０１５ｍｏｌｅｃｕｌｅ／ｃｍ２以下となる。 The insulator 112 having excess oxygen has a desorption amount of oxygen molecules in a surface temperature range of 100 ° C. to 700 ° C. or 100 ° C. to 500 ° C. in a temperature-programmed desorption gas spectroscopy analysis (TDS analysis). Is 1.0 × 10 14 molecule / cm 2 or more and 1.0 × 10 16 molecule / cm 2 or less, more preferably 1.0 × 10 15 molecule / cm 2 or more and 5.0 × 10 15 molecule / cm 2 or less. It becomes.
　ＴＤＳ分析を用いた分子の放出量の測定方法について、酸素の放出量を例として、以下に説明する。 A method for measuring the amount of released molecules using TDS analysis will be described below, taking oxygen released as an example.
　測定試料をＴＤＳ分析したときの気体の全放出量は、放出ガスのイオン強度の積分値に比例する。そして標準試料との比較により、気体の全放出量を計算することができる。 The total amount of gas released when the measurement sample is subjected to TDS analysis is proportional to the integrated value of the ionic strength of the released gas. The total amount of gas released can be calculated by comparison with a standard sample.
　例えば、標準試料である所定の密度の水素を含むシリコン基板のＴＤＳ分析結果、および測定試料のＴＤＳ分析結果から、測定試料の酸素分子の放出量（ＮＯ２）は、下に示す式で求めることができる。ここで、ＴＤＳ分析で得られる質量電荷比３２で検出されるガスの全てが酸素分子由来と仮定する。ＣＨ３ＯＨの質量電荷比は３２であるが、存在する可能性が低いものとしてここでは考慮しない。また、酸素原子の同位体である質量数１７の酸素原子および質量数１８の酸素原子を含む酸素分子についても、自然界における存在比率が極微量であるため考慮しない。 For example, from the TDS analysis result of a silicon substrate containing a predetermined density of hydrogen, which is a standard sample, and the TDS analysis result of the measurement sample, the amount of released oxygen molecules (N O2 ) of the measurement sample is obtained by the following formula: Can do. Here, it is assumed that all the gases detected by the mass-to-charge ratio 32 obtained by TDS analysis are derived from oxygen molecules. The mass to charge ratio of CH 3 OH is 32 but is not considered here as it is unlikely to exist. In addition, oxygen molecules containing oxygen atoms with a mass number of 17 and oxygen atoms with a mass number of 18 which are isotopes of oxygen atoms are not considered because the existence ratio in nature is extremely small.
　ＮＯ２＝ＮＨ２／ＳＨ２×ＳＯ２×α N O2 = N H2 / S H2 × S O2 × α
　ＮＨ２は、標準試料から脱離した水素分子を密度で換算した値である。ＳＨ２は、標準試料をＴＤＳ分析したときのイオン強度の積分値である。ここで、標準試料の基準値を、ＮＨ２／ＳＨ２とする。ＳＯ２は、測定試料をＴＤＳ分析したときのイオン強度の積分値である。αは、ＴＤＳ分析におけるイオン強度に影響する係数である。上に示す式の詳細に関しては、特開平６−２７５６９７公報を参照する。なお、上記酸素の放出量は、電子科学株式会社製の昇温脱離分析装置ＥＭＤ−ＷＡ１０００Ｓ／Ｗを用い、標準試料として一定量の水素原子を含むシリコン基板を用いて測定する。 N H2 is a value obtained by converting hydrogen molecules desorbed from the standard sample by density. SH2 is an integral value of ion intensity when the standard sample is subjected to TDS analysis. Here, the reference value of the standard sample is N H2 / SH 2 . S O2 is an integrated value of ion intensity when the measurement sample is subjected to TDS analysis. α is a coefficient that affects the ionic strength in the TDS analysis. For details of the above formula, refer to JP-A-6-275697. The amount of released oxygen is measured using a temperature-programmed desorption analyzer EMD-WA1000S / W manufactured by Electronic Science Co., Ltd. and using a silicon substrate containing a certain amount of hydrogen atoms as a standard sample.
　また、ＴＤＳ分析において、酸素の一部は酸素原子として検出される。酸素分子と酸素原子の比率は、酸素分子のイオン化率から算出することができる。なお、上述のαは酸素分子のイオン化率を含むため、酸素分子の放出量を評価することで、酸素原子の放出量についても見積もることができる。 Also, in TDS analysis, part of oxygen is detected as oxygen atoms. The ratio of oxygen molecules to oxygen atoms can be calculated from the ionization rate of oxygen molecules. Note that since the above α includes the ionization rate of oxygen molecules, the amount of released oxygen atoms can be estimated by evaluating the amount of released oxygen molecules.
　なお、ＮＯ２は酸素分子の放出量である。酸素原子に換算したときの放出量は、酸素分子の放出量の２倍となる。 Note that N 2 O 2 is the amount of released oxygen molecules. The amount of release when converted to oxygen atoms is twice the amount of release of oxygen molecules.
　または、加熱処理によって酸素を放出する絶縁体は、過酸化ラジカルを含むこともある。具体的には、過酸化ラジカルに起因するスピン密度が、５×１０１７ｓｐｉｎｓ／ｃｍ３以上であることをいう。なお、過酸化ラジカルを含む絶縁体は、電子スピン共鳴法（ＥＳＲ：Ｅｌｅｃｔｒｏｎ　Ｓｐｉｎ　Ｒｅｓｏｎａｎｃｅ）にて、ｇ値が２．０１近傍に非対称の信号を有することもある。 Alternatively, the insulator from which oxygen is released by heat treatment may contain a peroxide radical. Specifically, it means that the spin density resulting from the peroxide radical is 5 × 10 17 spins / cm 3 or more. Note that an insulator containing a peroxide radical may have an asymmetric signal with a g value near 2.01 by an electron spin resonance (ESR) method.
　また、絶縁体１１２は、絶縁体１１２の外側からの不純物の拡散を防止する機能を有してもよい。 Further, the insulator 112 may have a function of preventing diffusion of impurities from the outside of the insulator 112.
　導電体１０８ａ及び導電体１０８ｂは、それぞれトランジスタ１０のソース電極またはドレイン電極のいずれかとして機能する。 The conductor 108a and the conductor 108b function as either a source electrode or a drain electrode of the transistor 10, respectively.
　導電体１０８ａ及び導電体１０８ｂとしては、例えば、ホウ素、窒素、酸素、フッ素、シリコン、リン、アルミニウム、チタン、クロム、マンガン、コバルト、ニッケル、銅、亜鉛、ガリウム、イットリウム、ジルコニウム、モリブデン、ルテニウム、銀、インジウム、スズ、タンタルおよびタングステンを一種以上含む導電体を、単層で、または積層で用いればよい。例えば、合金や化合物であってもよく、アルミニウムを含む導電体、銅およびチタンを含む導電体、銅およびマンガンを含む導電体、インジウム、スズおよび酸素を含む導電体、チタンおよび窒素を含む導電体などを用いてもよい。 Examples of the conductor 108a and the conductor 108b include boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, A conductor including one or more of silver, indium, tin, tantalum, and tungsten may be used in a single layer or a stacked layer. For example, it may be an alloy or a compound, a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin and oxygen, a conductor containing titanium and nitrogen Etc. may be used.
　導電体１１４はトランジスタ１０のゲート電極として機能する。導電体１１４としては、導電体１０２として用いることができる導電体を用いればよい。 The conductor 114 functions as a gate electrode of the transistor 10. As the conductor 114, a conductor that can be used as the conductor 102 may be used.
　ここで、図１（Ｃ）に示すように、チャネル長方向に垂直な断面において、導電体１１４が半導体１０６ｂを取り囲む構造とすることにより、半導体１０６ｂの全周囲からゲート電界を掛けることができる。これにより、ＤＩＢＬ（Ｄｒａｉｎ　Ｉｎｄｕｃｅｄ　Ｂａｒｒｉｅｒ　Ｌｏｗｅｒｉｎｇ）効果による非導通時のリーク電流の発生を低減することができる。 Here, as shown in FIG. 1C, in a cross section perpendicular to the channel length direction, the conductor 114 surrounds the semiconductor 106b, whereby a gate electric field can be applied from the entire periphery of the semiconductor 106b. Thereby, generation | occurrence | production of the leakage current at the time of the non-conduction by the DIBL (Drain Induced Barrier Lowering) effect can be reduced.
　ＤＩＢＬ効果とは、ドレイン電圧の印加による影響で、ソースと半導体との接合部におけるエネルギー障壁が減少するために、サブスレッショルド特性が劣化する効果である。ドレイン側領域の空乏層幅が広がることでソース側領域の電圧降下が大きくなる。特に本実施の形態に示すトランジスタのようにチャネル長が短い場合、より顕著に効果が現れ、単チャネル効果と呼ばれる場合もある。 The DIBL effect is an effect of deterioration of subthreshold characteristics due to the influence of the application of the drain voltage and the reduction of the energy barrier at the junction between the source and the semiconductor. As the depletion layer width in the drain side region increases, the voltage drop in the source side region increases. In particular, when the channel length is short as in the transistor described in this embodiment, the effect is more significant and is sometimes referred to as a single-channel effect.
　これに対して、本実施の形態に示すトランジスタ１０では、半導体１０６ｂの全周囲からゲート電界を掛けることでドレイン側の空乏層の広がりを抑制することができる。これにより、トランジスタ１０は、非導通時のリーク電流を低減し、サブスレッショルドスイング値を小さくし、ノーマリーオフの電気特性とすることができる。 On the other hand, in the transistor 10 described in this embodiment, the spread of the drain-side depletion layer can be suppressed by applying a gate electric field from the entire periphery of the semiconductor 106b. Thereby, the transistor 10 can reduce the leakage current at the time of non-conduction, reduce the subthreshold swing value, and have normally-off electrical characteristics.
　さらに、上述のように半導体１０６ｂに用いる酸化物半導体は蓄積型であり、チャネル長が短い構造においても、しきい値電圧を０Ｖより大きくさせやすい。 Furthermore, as described above, the oxide semiconductor used for the semiconductor 106b is a storage type, and the threshold voltage can be easily increased from 0 V even in a structure with a short channel length.
　さらに、本実施の形態に示すトランジスタ１０はバックゲートとして機能する導電体１０２が設けられており、容易にしきい値電圧の制御を行うことができる。 Further, the transistor 10 described in this embodiment is provided with a conductor 102 functioning as a back gate, so that the threshold voltage can be easily controlled.
　以上のような構成とすることにより、短チャネル効果に耐性を有するトランジスタを提供することができる。または、ノーマリーオフの電気特性を有するトランジスタを提供することができる。または、非導通時のリーク電流の小さいトランジスタを提供することができる。または、サブスレッショルドスイング値の小さいトランジスタを提供することができる。または、チャネル長の短い微細構造において、安定した電気特性を有するトランジスタを提供することができる。 With the above configuration, a transistor having resistance to a short channel effect can be provided. Alternatively, a transistor having normally-off electrical characteristics can be provided. Alternatively, a transistor with low leakage current when not conducting can be provided. Alternatively, a transistor with a small subthreshold swing value can be provided. Alternatively, a transistor having stable electrical characteristics can be provided in a microstructure with a short channel length.
＜トランジスタ変形例＞
　以下、トランジスタ１０の変形例について図２乃至図４を用いて説明する。なお、図２（Ａ）乃至（Ｆ）、図３（Ａ）（Ｂ）は、図１（Ｂ）及び図１（Ｃ）と同様に、トランジスタのチャネル長方向の断面図とトランジスタのチャネル幅方向の断面図になる。 <Transistor modification>
Hereinafter, modified examples of the transistor 10 will be described with reference to FIGS. Note that FIGS. 2A to 2F and FIGS. 3A and 3B are similar to FIGS. 1B and 1C in which the cross-sectional view of the transistor in the channel length direction and the channel width of the transistor are shown. It becomes sectional drawing of a direction.
　上記トランジスタ１０において、半導体１０６ｂの伸長方向（Ａ１−Ａ２方向）に略垂直な断面における断面形状は略円形状としたが、本実施の形態に示す半導体装置はこれに限られるものではない。例えば、半導体１０６ｂの伸長方向（Ａ１−Ａ２方向）に略垂直な断面における断面形状を略多角形状としてもよい。なお、本明細書等において、略多角形とは、三角形、四角形などの厳密な多角形だけでなく、例えば多角形において角が丸みを帯びた形状も含むものとする。 In the transistor 10, the cross-sectional shape in a cross section substantially perpendicular to the extending direction (A1-A2 direction) of the semiconductor 106b is a substantially circular shape; however, the semiconductor device described in this embodiment is not limited thereto. For example, the cross-sectional shape in a cross section substantially perpendicular to the extending direction (A1-A2 direction) of the semiconductor 106b may be a substantially polygonal shape. In addition, in this specification etc., a substantially polygon includes not only a strict polygon, such as a triangle and a quadrangle, but also a shape with rounded corners in a polygon, for example.
　例えば、図２（Ａ）（Ｂ）に示すトランジスタ１０ａは、半導体１０６ｂの伸長方向（Ａ１−Ａ２方向）に略垂直な断面における断面形状が、角が丸みを帯びた四角形状である点において、トランジスタ１０と異なる。また、絶縁体１０６ａ、絶縁体１１２及び導電体１１４の同断面における形状が半導体１０６ｂの断面形状に対応している。 For example, in the transistor 10a illustrated in FIGS. 2A and 2B, the cross-sectional shape in a cross section substantially perpendicular to the extending direction (A1-A2 direction) of the semiconductor 106b is a quadrangular shape with rounded corners. Different from the transistor 10. The shapes of the insulator 106a, the insulator 112, and the conductor 114 in the same cross section correspond to the cross sectional shape of the semiconductor 106b.
　また、例えば、図２（Ｃ）（Ｄ）に示すトランジスタ１０ｂは、半導体１０６ｂの伸長方向（Ａ１−Ａ２方向）に略垂直な断面における断面形状が、角が丸みを帯びた三角形状である点において、トランジスタ１０と異なる。また、絶縁体１０６ａ、絶縁体１１２及び導電体１１４の同断面における形状が半導体１０６ｂの断面形状に対応している。 For example, in the transistor 10b illustrated in FIGS. 2C and 2D, the cross-sectional shape in a cross section substantially perpendicular to the extending direction (A1-A2 direction) of the semiconductor 106b is a triangular shape with rounded corners. In FIG. The shapes of the insulator 106a, the insulator 112, and the conductor 114 in the same cross section correspond to the cross sectional shape of the semiconductor 106b.
　また、トランジスタ１０ａ及びトランジスタ１０ｂでは、半導体１０６ｂの伸長方向（Ａ１−Ａ２方向）に略垂直な断面における断面形状が正多角形に近い形状の例を示したが、本実施の形態に示す半導体装置はこれに限られるものではない。例えば、図２（Ｅ）（Ｆ）に示すトランジスタ１０ｃのように、半導体１０６ｂの伸長方向（Ａ１−Ａ２方向）に略垂直な断面における断面形状が、角が丸みを帯びた六角形状であり、正六角形と異なる形状にしてもよい。また、絶縁体１０６ａ、絶縁体１１２及び導電体１１４の同断面における形状が半導体１０６ｂの断面形状に対応している。 In the transistor 10a and the transistor 10b, an example in which a cross-sectional shape in a cross section substantially perpendicular to the extending direction (A1-A2 direction) of the semiconductor 106b is close to a regular polygon is shown; however, the semiconductor device described in this embodiment Is not limited to this. For example, like the transistor 10c shown in FIGS. 2E and 2F, the cross-sectional shape in a cross section substantially perpendicular to the extending direction (A1-A2 direction) of the semiconductor 106b is a hexagonal shape with rounded corners. You may make it a shape different from a regular hexagon. The shapes of the insulator 106a, the insulator 112, and the conductor 114 in the same cross section correspond to the cross sectional shape of the semiconductor 106b.
　また、図３（Ａ）（Ｂ）に示すトランジスタ１０ｄのように、導電体１０２が導電体１１４の外側に設けられている構成としてもよい。 Alternatively, as in the transistor 10d illustrated in FIGS. 3A and 3B, the conductor 102 may be provided outside the conductor 114.
　また、図３（Ｃ）に示すトランジスタ１０ｅのように、半導体１０６ｂ、絶縁体１０６ａ、絶縁体１１２及び導電体１０２を含む複数のナノワイヤを、半導体１０６ｂの伸長方向が平行になるように配置して、一つの導電体１１４で各ナノワイヤを囲む構成としてもよい。このような構成とすることにより、１本のナノワイヤでは小さいオン電流を、十分に大きくすることができる。 Further, as in the transistor 10e illustrated in FIG. 3C, a plurality of nanowires including the semiconductor 106b, the insulator 106a, the insulator 112, and the conductor 102 are arranged so that the extending directions of the semiconductor 106b are parallel to each other. The nanowires may be surrounded by one conductor 114. With such a configuration, a small on-current can be sufficiently increased with one nanowire.
　また、基板の上面に対してナノワイヤの伸長方向が略平行になるようにトランジスタ５０を設ける例について図４（Ａ）乃至（Ｅ）を用いて説明する。図４（Ａ）はトランジスタ５０の上面図である。図４（Ｂ）は図４（Ａ）の一点鎖線Ｂ１−Ｂ２に対応する断面図であり、図４（Ｃ）は図４（Ａ）の一点鎖線Ｂ３−Ｂ４に対応する断面図である。なお、一点鎖線Ｂ１−Ｂ２で示す領域では、トランジスタ５０のチャネル長方向における構造を示しており、一点鎖線Ｂ３−Ｂ４で示す領域では、一点鎖線Ｂ１−Ｂ２に垂直な方向における構造を示している。また、図４（Ａ）において、図面が煩雑になることを避けるため、絶縁体１６２など一部の構造を省略して表現している。 Further, an example in which the transistor 50 is provided so that the extending direction of the nanowire is substantially parallel to the upper surface of the substrate will be described with reference to FIGS. FIG. 4A is a top view of the transistor 50. 4B is a cross-sectional view corresponding to the dashed-dotted line B1-B2 in FIG. 4A, and FIG. 4C is a cross-sectional view corresponding to the dashed-dotted line B3-B4 in FIG. Note that a region indicated by a dashed-dotted line B1-B2 indicates a structure in the channel length direction of the transistor 50, and a region indicated by a dashed-dotted line B3-B4 indicates a structure in a direction perpendicular to the dashed-dotted line B1-B2. . In FIG. 4A, part of the structure such as the insulator 162 is omitted in order to avoid the drawing from being complicated.
　トランジスタ５０は、基板１５０上に設けられた絶縁体１５１を有する。さらに、絶縁体１５１上に設けられた開口を有する絶縁体１５７を有する。さらに、当該開口中にＢ３−Ｂ４方向に伸長して設けられた導電体１６４ａを有する。さらに、導電体１６４ａ上に設けられた絶縁体１６２ａを有する。さらに、絶縁体１６２ａ上に設けられた開口を有する絶縁体１６２ｂを有する。さらに、絶縁体１６２ｂに形成された開口の中に、Ｂ１−Ｂ２方向に伸長して設けられた導電体１５２を有する。さらに、絶縁体１６２ｂ及び導電体１５２上に設けられた絶縁体１６２ｃを有する。さらに、絶縁体１６２ｃ上に設けられた絶縁体１５６ａを有する。さらに、絶縁体１６２ｃ上に、絶縁体１５６ａを間に挟んで設けられた導電体１５８ｃ及び導電体１５８ｄを有する。さらに、絶縁体１５６ａ、導電体１５８ｃ及び導電体１５８ｄの上面に接して、Ｂ１−Ｂ２方向に伸長して設けられた半導体１５６ｂを有する。さらに、半導体１５６ｂの上面及び側面と、導電体１５８ｃの側面に接して、絶縁体１５６ｃを間に挟んで導電体１５８ｂと対向して設けられた導電体１５８ａを有する。さらに、半導体１５６ｂの上面及び側面と、導電体１５８ｄの側面に接して、絶縁体１５６ｃを間に挟んで導電体１５８ａと対向して設けられた導電体１５８ｂを有する。さらに、導電体１５８ａ及び導電体１５８ｂ上に設けられ、導電体１５８ａと導電体１５８ｂの間に開口を有する絶縁体１６７を有する。さらに、半導体１５６ｂの上面、導電体１５８ａ及び導電体１５８ｂの側面、絶縁体１６７の側面と接して設けられた絶縁体１５６ｃを有する。さらに、絶縁体１５６ｃの上面に接して設けられた絶縁体１６２ｄを有する。さらに、絶縁体１６２ｄの上面に接して設けられた導電体１６４ｂを有する。 The transistor 50 includes an insulator 151 provided over the substrate 150. Further, an insulator 157 having an opening provided over the insulator 151 is provided. Further, a conductor 164a is provided in the opening so as to extend in the B3-B4 direction. Further, an insulator 162a is provided over the conductor 164a. Further, an insulator 162b having an opening provided over the insulator 162a is provided. Further, a conductor 152 provided to extend in the B1-B2 direction is provided in the opening formed in the insulator 162b. Further, an insulator 162c provided over the insulator 162b and the conductor 152 is provided. Further, an insulator 156a provided over the insulator 162c is provided. Furthermore, the conductor 162c and the conductor 158d are provided over the insulator 162c with the insulator 156a interposed therebetween. Further, a semiconductor 156b provided in contact with the top surfaces of the insulator 156a, the conductor 158c, and the conductor 158d and extending in the B1-B2 direction is provided. Further, the semiconductor 156b includes a conductor 158a provided in contact with the top surface and side surfaces of the semiconductor 156b and the side surfaces of the conductor 158c so as to face the conductor 158b with the insulator 156c interposed therebetween. Further, the semiconductor 156b includes a conductor 158b which is in contact with the top surface and the side surface of the semiconductor 156b and the side surface of the conductor 158d and faces the conductor 158a with the insulator 156c interposed therebetween. Further, an insulator 167 is provided over the conductor 158a and the conductor 158b and has an opening between the conductor 158a and the conductor 158b. Further, the semiconductor 156b includes an insulator 156c provided in contact with an upper surface of the semiconductor 156b, side surfaces of the conductor 158a and the conductor 158b, and a side surface of the insulator 167. Further, an insulator 162d provided in contact with the upper surface of the insulator 156c is provided. Further, a conductor 164b provided in contact with the upper surface of the insulator 162d is provided.
　Ｂ３−Ｂ４方向の断面において、絶縁体１５６ａと絶縁体１５６ｃは、半導体１５６ｂを囲むように設けられており、絶縁体１５６ａと絶縁体１５６ｃの側面端部は概略一致している。Ｂ３−Ｂ４方向の断面において、絶縁体１６２ｃと絶縁体１６２ｄは、絶縁体１５６ａ、半導体１５６ｂ及び絶縁体１５６ｃを囲むように設けられており、絶縁体１６２ｃと絶縁体１６２ｄの側面端部は概略一致している。Ｂ３−Ｂ４方向の断面において、導電体１６４ａと導電体１６４ｂは、絶縁体１６２ａ乃至絶縁体１６２ｄを囲むように設けられる。 In the cross section in the B3-B4 direction, the insulator 156a and the insulator 156c are provided so as to surround the semiconductor 156b, and the side end portions of the insulator 156a and the insulator 156c are substantially coincident with each other. In the cross section in the B3-B4 direction, the insulator 162c and the insulator 162d are provided so as to surround the insulator 156a, the semiconductor 156b, and the insulator 156c, and the side edges of the insulator 162c and the insulator 162d are approximately one. I'm doing it. In the cross section in the B3-B4 direction, the conductor 164a and the conductor 164b are provided so as to surround the insulators 162a to 162d.
　トランジスタ５０は、トランジスタ１０と対応して設けられている。半導体１５６ｂは半導体１０６ｂに対応し、上述の半導体１０６ｂとして用いることができる半導体を用いればよい。絶縁体１５６ａ及び絶縁体１５６ｃは絶縁体１０６ａに対応し、上述の絶縁体１０６ａとして用いることができる絶縁体または半導体を用いればよい。絶縁体１６２ａ乃至絶縁体１６２ｄは絶縁体１１２に対応し、上述の絶縁体１１２として用いることができる絶縁体を用いればよい。導電体１５２は導電体１０２に対応し、上述の導電体１０２として用いることができる導電体を用いればよい。導電体１６４ａ及び導電体１６４ｂは導電体１１４に対応し、上述の導電体１１４として用いることができる導電体を用いればよい。 The transistor 50 is provided corresponding to the transistor 10. The semiconductor 156b corresponds to the semiconductor 106b, and a semiconductor that can be used as the above-described semiconductor 106b may be used. The insulator 156a and the insulator 156c correspond to the insulator 106a, and an insulator or a semiconductor that can be used as the above-described insulator 106a may be used. The insulators 162a to 162d correspond to the insulator 112, and an insulator that can be used as the above-described insulator 112 may be used. The conductor 152 corresponds to the conductor 102, and a conductor that can be used as the above-described conductor 102 may be used. The conductor 164a and the conductor 164b correspond to the conductor 114, and a conductor that can be used as the above-described conductor 114 may be used.
　また、トランジスタ５０の変形例としてトランジスタ５０ａを図４（Ｄ）（Ｅ）に示す。図４（Ｄ）は図４（Ｂ）に対応しており、図４（Ｅ）は図４（Ｃ）に対応している。トランジスタ５０ａは、導電体１５８ａ（または導電体１５８ｂ）の側面端部の傾斜角θ１と絶縁体１６７の側面端部の傾斜角θ２が一致していない点において、トランジスタ５０と異なる。ここで、導電体１５８ａ及び導電体１５８ｂの側面端部の傾斜角θ１を３０°以上９０°未満、好ましくは４５°以上８０°未満、より好ましくは４５°以上６０°未満とすることが好ましい。また、絶縁体１６７の側面端部の傾斜角θ２は、傾斜角θ１より大きいことが好ましい。このように、導電体１５８ａ及び導電体１５８ｂの側面端部をテーパー形状とすることで、より導電体１５８ａと導電体１５８ｂの距離を短くすることができ、トランジスタ５０ａのチャネル長Ｌを短くすることができる。 As a modification of the transistor 50, a transistor 50a is illustrated in FIGS. 4D corresponds to FIG. 4B, and FIG. 4E corresponds to FIG. 4C. Transistor 50a is in that the inclination angle theta 2 of the end face portion of the inclined angle theta 1 and the insulator 167 of the side end portion of the conductor 158a (or conductor 158b) it does not match, different from the transistor 50. Here, the conductors 158a and a side end portion inclination angle θ less than 1 30 ° or 90 ° of the conductor 158b, is preferably preferably less than 45 ° or 80 °, more preferably to less than 45 ° or more and 60 ° or . Moreover, it is preferable that the inclination angle θ 2 of the side surface end portion of the insulator 167 is larger than the inclination angle θ 1 . In this manner, by making the side end portions of the conductors 158a and 158b tapered, the distance between the conductors 158a and 158b can be further shortened, and the channel length L of the transistor 50a can be shortened. Can do.
　また、図４（Ｄ）に示すように、半導体１５６ｂは、導電体１５８ａと導電体１５８ｂの間に導電体１５８ａ及び導電体１５８ｂと重なった領域より膜厚の薄い領域を有することがある。これは、導電体１５８ａ及び導電体１５８ｂを形成する際に、半導体１５６ｂの上面の一部を除去することにより形成される。半導体１５６ｂの上面には、導電体１５８ａ及び導電体１５８ｂとなる導電体を成膜した際に、低抵抗領域が形成される場合がある。このように、半導体１５６ｂの上面の導電体１５８ａと導電体１５８ｂの間に位置する領域を除去することにより、半導体１５６ｂの上面の低抵抗領域にチャネルが形成されることを防ぐことができる。また、以降の図面において、拡大図などで膜厚の薄い領域を示さない場合でも、同様の膜厚の薄い領域が形成されている場合がある。 As shown in FIG. 4D, the semiconductor 156b may have a region between the conductor 158a and the conductor 158b that is thinner than a region overlapping with the conductor 158a and the conductor 158b. This is formed by removing a part of the upper surface of the semiconductor 156b when the conductor 158a and the conductor 158b are formed. A low resistance region may be formed over the top surface of the semiconductor 156b when a conductor to be the conductor 158a and the conductor 158b is formed. In this manner, by removing the region located between the conductors 158a and 158b on the top surface of the semiconductor 156b, a channel can be prevented from being formed in the low resistance region on the top surface of the semiconductor 156b. Further, in the subsequent drawings, even when the thin region is not shown in an enlarged view or the like, a similar thin region may be formed.
＜トランジスタの作製方法＞
　以下において、図５乃至図７を用いてトランジスタ５０の作製方法について説明する。 <Method for Manufacturing Transistor>
A method for manufacturing the transistor 50 will be described below with reference to FIGS.
　まずは、基板１５０を準備する。基板１５０は、例えば、絶縁体基板、半導体基板または導電体基板を用いればよい。絶縁体基板としては、例えば、ガラス基板、石英基板、サファイア基板、安定化ジルコニア基板（イットリア安定化ジルコニア基板など）、樹脂基板などがある。また、半導体基板としては、例えば、シリコン、ゲルマニウムなどの単体半導体基板、または炭化シリコン、シリコンゲルマニウム、ヒ化ガリウム、リン化インジウム、酸化亜鉛、酸化ガリウムなどの半導体基板などがある。さらには、前述の半導体基板内部に絶縁体領域を有する半導体基板、例えばＳＯＩ（Ｓｉｌｉｃｏｎ　Ｏｎ　Ｉｎｓｕｌａｔｏｒ）基板などがある。導電体基板としては、黒鉛基板、金属基板、合金基板、導電性樹脂基板などがある。または、金属の窒化物を有する基板、金属の酸化物を有する基板などがある。さらには、絶縁体基板に導電体または半導体が設けられた基板、半導体基板に導電体または絶縁体が設けられた基板、導電体基板に半導体または絶縁体が設けられた基板などがある。または、これらの基板に素子が設けられたものを用いてもよい。基板に設けられる素子としては、容量素子、抵抗素子、スイッチ素子、発光素子、記憶素子などがある。 First, the substrate 150 is prepared. As the substrate 150, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria stabilized zirconia substrate), and a resin substrate. Examples of the semiconductor substrate include a single semiconductor substrate such as silicon and germanium, or a semiconductor substrate such as silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Furthermore, there is a semiconductor substrate having an insulator region inside the semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Alternatively, there are a substrate having a metal nitride, a substrate having a metal oxide, and the like. Further, there are a substrate in which a conductor or a semiconductor is provided on an insulator substrate, a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate, and the like. Alternatively, a substrate in which an element is provided may be used. Examples of the element provided on the substrate include a capacitor element, a resistor element, a switch element, a light emitting element, and a memory element.
　また、基板１５０として、トランジスタ作製時の加熱処理に耐えうる可とう性基板を用いてもよい。なお、可とう性基板上にトランジスタを設ける方法としては、非可とう性の基板上にトランジスタを作製した後、トランジスタを剥離し、可とう性基板である基板１５０に転置する方法もある。その場合には、非可とう性基板とトランジスタとの間に剥離層を設けるとよい。なお、基板１５０として、繊維を編みこんだシート、フィルムまたは箔などを用いてもよい。また、基板１５０が伸縮性を有してもよい。また、基板１５０は、折り曲げや引っ張りをやめた際に、元の形状に戻る性質を有してもよい。または、元の形状に戻らない性質を有してもよい。基板１５０の厚さは、例えば、５μｍ以上７００μｍ以下、好ましくは１０μｍ以上５００μｍ以下、さらに好ましくは１５μｍ以上３００μｍ以下とする。基板１５０を薄くすると、半導体装置を軽量化することができる。また、基板１５０を薄くすることで、ガラスなどを用いた場合にも伸縮性を有する場合や、折り曲げや引っ張りをやめた際に、元の形状に戻る性質を有する場合がある。そのため、落下などによって基板１５０上の半導体装置に加わる衝撃などを緩和することができる。即ち、丈夫な半導体装置を提供することができる。 Alternatively, as the substrate 150, a flexible substrate that can withstand heat treatment at the time of manufacturing the transistor may be used. Note that as a method for providing a transistor over a flexible substrate, there is a method in which after a transistor is manufactured over a non-flexible substrate, the transistor is peeled and transferred to the substrate 150 which is a flexible substrate. In that case, a separation layer is preferably provided between the non-flexible substrate and the transistor. Note that the substrate 150 may be a sheet, a film, a foil, or the like in which fibers are knitted. Further, the substrate 150 may have elasticity. Further, the substrate 150 may have a property of returning to its original shape when bending or pulling is stopped. Or you may have a property which does not return to an original shape. The thickness of the substrate 150 is, for example, 5 μm to 700 μm, preferably 10 μm to 500 μm, and more preferably 15 μm to 300 μm. When the substrate 150 is thinned, the semiconductor device can be reduced in weight. In addition, by making the substrate 150 thin, it may have elasticity even when glass or the like is used, or may have a property of returning to its original shape when bending or pulling is stopped. Therefore, an impact applied to the semiconductor device on the substrate 150 due to a drop or the like can be reduced. That is, a durable semiconductor device can be provided.
　可とう性基板である基板１５０としては、例えば、金属、合金、樹脂もしくはガラス、またはそれらの繊維などを用いることができる。可とう性基板である基板１５０は、線膨張率が低いほど環境による変形が抑制されて好ましい。可とう性基板である基板１５０としては、例えば、線膨張率が１×１０−３／Ｋ以下、５×１０−５／Ｋ以下、または１×１０−５／Ｋ以下である材質を用いればよい。樹脂としては、例えば、ポリエステル、ポリオレフィン、ポリアミド（ナイロン、アラミドなど）、ポリイミド、ポリカーボネート、アクリルなどがある。特に、アラミドは、線膨張率が低いため、可とう性基板である基板１５０として好適である。 As the substrate 150 that is a flexible substrate, for example, a metal, an alloy, a resin, glass, or fiber thereof can be used. The substrate 150, which is a flexible substrate, is preferable as the linear expansion coefficient is lower because deformation due to the environment is suppressed. For example, a material having a linear expansion coefficient of 1 × 10 −3 / K or less, 5 × 10 −5 / K or less, or 1 × 10 −5 / K or less is used as the substrate 150 that is a flexible substrate. Good. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic. In particular, since aramid has a low coefficient of linear expansion, it is suitable for the substrate 150 that is a flexible substrate.
　次に、絶縁体１５１を成膜する。絶縁体１５１の成膜は、スパッタリング法、化学気相成長（ＣＶＤ：Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）法、分子線エピタキシー（ＭＢＥ：Ｍｏｌｅｃｕｌａｒ　Ｂｅａｍ　Ｅｐｉｔａｘｙ）法またはパルスレーザ堆積（ＰＬＤ：Ｐｕｌｓｅｄ　Ｌａｓｅｒ　Ｄｅｐｏｓｉｔｉｏｎ）法、原子層堆積（ＡＬＤ：Ａｔｏｍｉｃ　Ｌａｙｅｒ　Ｄｅｐｏｓｉｔｉｏｎ）法などを用いて行うことができる。 Next, an insulator 151 is formed. The insulator 151 is formed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD: Pulsed Laser Deposition) method, or an atomic layer. The deposition can be performed using an ALD (Atomic Layer Deposition) method or the like.
　絶縁体１５１は、水素又は水をブロックする機能を有する絶縁体を用いる。絶縁体１５６ａ及び半導体１５６ｂ近傍に設けられる絶縁体中の水素や水は、絶縁体１５６ａ及び半導体１５６ｂ中にキャリアを生成する要因の一つとなる。これによりトランジスタ５０の信頼性が低下するおそれがある。特に基板１５０としてスイッチ素子などのシリコン系半導体素子を設けた基板を用いる場合、当該半導体素子のダングリングボンドを終端するために水素が用いられ、当該水素がトランジスタ５０まで拡散するおそれがある。これに対して水素又は水をブロックする機能を有する絶縁体１５１を設けることによりトランジスタ１０の下層から水素又は水が拡散するのを抑制し、トランジスタ５０の信頼性を向上させることができる。 As the insulator 151, an insulator having a function of blocking hydrogen or water is used. Hydrogen or water in the insulator provided in the vicinity of the insulator 156a and the semiconductor 156b is one of the factors that generate carriers in the insulator 156a and the semiconductor 156b. As a result, the reliability of the transistor 50 may be reduced. In particular, when a substrate provided with a silicon-based semiconductor element such as a switch element is used as the substrate 150, hydrogen is used to terminate dangling bonds of the semiconductor element, and the hydrogen may diffuse to the transistor 50. In contrast, by providing the insulator 151 having a function of blocking hydrogen or water, diffusion of hydrogen or water from the lower layer of the transistor 10 can be suppressed, and the reliability of the transistor 50 can be improved.
　また、絶縁体１５１は酸素をブロックする機能も有することが好ましい。絶縁体１５１が絶縁体１６２ｃ及び絶縁体１６２ｄから拡散する酸素をブロックすることにより、絶縁体１６２ｃ及び絶縁体１６２ｄから絶縁体１５６ａ及び半導体１５６ｂに効果的に酸素を供給することができる。 In addition, the insulator 151 preferably has a function of blocking oxygen. When the insulator 151 blocks oxygen diffused from the insulator 162c and the insulator 162d, oxygen can be effectively supplied from the insulator 162c and the insulator 162d to the insulator 156a and the semiconductor 156b.
　絶縁体１５１としては、例えば、酸化アルミニウム、酸化窒化アルミニウム、酸化ガリウム、酸化窒化ガリウム、酸化イットリウム、酸化窒化イットリウム、酸化ハフニウム、酸化窒化ハフニウム等を用いることができる。これらを絶縁体１５１として用いることにより、酸素、水素又は水の拡散をブロックする効果を示す絶縁膜として機能することができる。また、絶縁体１５１としては、例えば、窒化シリコン、窒化酸化シリコン等を用いることができる。これらを絶縁体１５１として用いることにより、水素、水の拡散をブロックする効果を示す絶縁膜として機能することができる。 As the insulator 151, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, or the like can be used. By using these as the insulator 151, the insulator 151 can function as an insulating film having an effect of blocking diffusion of oxygen, hydrogen, or water. As the insulator 151, for example, silicon nitride, silicon nitride oxide, or the like can be used. By using these as the insulator 151, the insulator 151 can function as an insulating film having an effect of blocking diffusion of hydrogen and water.
　次に、絶縁体１５７となる絶縁体を成膜する。絶縁体としては上述の絶縁体１１２として用いることができる絶縁体を用いればよい。絶縁体の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法またはＰＬＤ法、ＡＬＤ法などを用いて行うことができる。 Next, an insulator to be the insulator 157 is formed. As the insulator, an insulator that can be used as the above-described insulator 112 may be used. The insulator can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
　次に、絶縁体上にレジストなどを形成し、該レジストなどを用いて加工し、開口部を有する絶縁体１５７を形成する。 Next, a resist or the like is formed over the insulator and processed using the resist or the like to form the insulator 157 having an opening.
　レジストは、対象物をエッチングなどによって加工した後で除去する。レジストの除去には、プラズマ処理または／およびウェットエッチングを用いる。なお、プラズマ処理としては、プラズマアッシングが好適である。レジストなどの除去が不十分な場合、０．００１ｖｏｌｕｍｅ％以上１ｖｏｌｕｍｅ％以下の濃度のフッ化水素酸または／およびオゾン水などによって取り残したレジストなどを除去しても構わない。 The resist is removed after the object is processed by etching or the like. For the removal of the resist, plasma treatment and / or wet etching is used. Note that plasma ashing is preferable as the plasma treatment. If the removal of the resist or the like is insufficient, the remaining resist or the like may be removed with hydrofluoric acid or / and ozone water having a concentration of 0.001 volume% or more and 1 volume% or less.
　次に、導電体１６４ａとなる導電体を成膜する。導電体１６４ａとなる導電体としては、上述の導電体を用いることができる。導電体の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法またはＰＬＤ法、ＡＬＤ法などを用いて行うことができる。 Next, a conductor to be the conductor 164a is formed. As the conductor to be the conductor 164a, the above-described conductor can be used. The conductor can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.
　次に、絶縁体１５７が露出するまで導電体を研磨し、導電体１６４ａを形成する（図５（Ａ）（Ｂ）参照。）。研磨は、ＣＭＰ処理などによって行うことができる。 Next, the conductor is polished until the insulator 157 is exposed to form a conductor 164a (see FIGS. 5A and 5B). Polishing can be performed by a CMP process or the like.
　次に、後の工程で絶縁体１６２ａとなる絶縁体１６２ｅを成膜する。絶縁体１６２ｅとしては上述の絶縁体１１２として用いることができる絶縁体を用いればよい。絶縁体１６２ｅの成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法またはＰＬＤ法、ＡＬＤ法などを用いて行うことができる。 Next, an insulator 162e to be an insulator 162a in a later step is formed. As the insulator 162e, an insulator that can be used as the above-described insulator 112 may be used. The insulator 162e can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
　次に、後の工程で絶縁体１６２ｂとなる絶縁体を成膜する。絶縁体としては上述の絶縁体１１２として用いることができる絶縁体を用いればよい。絶縁体の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法またはＰＬＤ法、ＡＬＤ法などを用いて行うことができる。 Next, an insulator to be an insulator 162b is formed in a later step. As the insulator, an insulator that can be used as the above-described insulator 112 may be used. The insulator can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
　次に、絶縁体上にレジストなどを形成し、該レジストなどを用いて加工し、開口部を有する絶縁体１６２ｆを形成する。 Next, a resist or the like is formed over the insulator and processed using the resist or the like to form an insulator 162f having an opening.
　次に、導電体１５２となる導電体を成膜する。導電体１５２となる導電体としては、上述の導電体１０２として用いることができる導電体を用いればよい。導電体の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法またはＰＬＤ法、ＡＬＤ法などを用いて行うことができる。 Next, a conductor to be the conductor 152 is formed. As the conductor to be the conductor 152, a conductor that can be used as the above-described conductor 102 may be used. The conductor can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.
　次に、絶縁体１６２ｆが露出するまで導電体を研磨し、導電体１５２を形成する（図５（Ｃ）（Ｄ）参照。）。研磨は、ＣＭＰ処理などによって行うことができる。 Next, the conductor is polished until the insulator 162f is exposed to form the conductor 152 (see FIGS. 5C and 5D). Polishing can be performed by a CMP process or the like.
　次に、後の工程で絶縁体１６２ｃとなる絶縁体１６２ｇを成膜する。絶縁体１６２ｇとしては上述の絶縁体１１２として用いることができる絶縁体を用いればよい。絶縁体１６２ｇの成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法またはＰＬＤ法、ＡＬＤ法などを用いて行うことができる。また、絶縁体１６２ｇ中に含まれる水、または水素を低減するために基板を加熱しながら成膜を行ってもよい。 Next, an insulator 162g, which becomes an insulator 162c in a later step, is formed. As the insulator 162g, an insulator that can be used as the above-described insulator 112 may be used. The insulator 162g can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Alternatively, film formation may be performed while heating the substrate in order to reduce water or hydrogen contained in the insulator 162g.
　次に、加熱処理を行うことが好ましい。加熱処理を行うことで、絶縁体１６２ｇなどに含まれる水、または水素をさらに低減させることができる。また、絶縁体１６２ｇに過剰酸素を有せしめることができる場合がある。加熱処理は、２５０℃以上６５０℃以下、好ましくは４５０℃以上６００℃以下、さらに好ましくは５２０℃以上５７０℃以下で行えばよい。加熱処理は、不活性ガス雰囲気、または酸化性ガスを１０ｐｐｍ以上、１％以上もしくは１０％以上含む雰囲気で行う。加熱処理は減圧状態で行ってもよい。または、加熱処理は、不活性ガス雰囲気で加熱処理した後に、脱離した酸素を補うために酸化性ガスを１０ｐｐｍ以上、１％以上または１０％以上含む雰囲気で加熱処理を行ってもよい。加熱処理は、ランプ加熱によるＲＴＡ装置を用いることもできる。ＲＴＡ装置による加熱処理は、炉と比べて短時間で済むため、生産性を高めるために有効である。 Next, it is preferable to perform heat treatment. By performing the heat treatment, water or hydrogen contained in the insulator 162g or the like can be further reduced. In some cases, the insulator 162g can be provided with excess oxygen. The heat treatment may be performed at 250 ° C to 650 ° C, preferably 450 ° C to 600 ° C, more preferably 520 ° C to 570 ° C. The heat treatment is performed in an inert gas atmosphere or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. The heat treatment may be performed in a reduced pressure state. Alternatively, the heat treatment may be performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more in order to supplement the desorbed oxygen after the heat treatment in an inert gas atmosphere. For the heat treatment, an RTA apparatus using lamp heating can also be used. The heat treatment by the RTA apparatus is effective for improving productivity because it takes a shorter time than a furnace.
　次に、後の工程で絶縁体１５６ａとなる絶縁体を成膜して、レジストなどを用いて加工し、絶縁体１５６ｄを形成する（図５（Ｅ）（Ｆ）参照。）。絶縁体１５６ｄとしては上述の絶縁体１０６ａとして用いることができる絶縁体または半導体などを用いればよい。絶縁体の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法またはＰＬＤ法、ＡＬＤ法などを用いて行うことができる。 Next, an insulator to be the insulator 156a is formed in a later step and processed using a resist or the like to form the insulator 156d (see FIGS. 5E and 5F). As the insulator 156d, an insulator, a semiconductor, or the like that can be used as the above-described insulator 106a may be used. The insulator can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
　次に、後の工程で導電体１５８ｃ及び導電体１５８ｄとなる導電体を成膜して、絶縁体１５６ｄが露出するまで導電体を研磨し、導電体１５８ｅ及び導電体１５８ｆを形成する（図５（Ｇ）（Ｈ）参照。）。研磨は、ＣＭＰ処理などによって行うことができる。導電体１５８ｅ及び導電体１５８ｆとしては上述の導電体１０８ａ及び導電体１０８ｂとして用いることができる導電体を用いればよい。導電体の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法またはＰＬＤ法、ＡＬＤ法などを用いて行うことができる。 Next, a conductor to be the conductor 158c and the conductor 158d is formed in a later step, and the conductor is polished until the insulator 156d is exposed, so that the conductor 158e and the conductor 158f are formed (FIG. 5). (G) See (H).) Polishing can be performed by a CMP process or the like. As the conductor 158e and the conductor 158f, a conductor that can be used for the conductor 108a and the conductor 108b described above may be used. The conductor can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.
　次に、半導体１５６ｂとなる半導体を成膜する。半導体としては上述の半導体１０６ｂとして用いることができる半導体を用いればよい。半導体の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法またはＰＬＤ法、ＡＬＤ法などを用いて行うことができる。 Next, a semiconductor to be the semiconductor 156b is formed. As the semiconductor, a semiconductor that can be used as the above-described semiconductor 106b may be used. The semiconductor can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
　次に、加熱処理を行うことが好ましい。加熱処理を行うことで、半導体１５６ｂとなる半導体、絶縁体１５６ｄまたは絶縁体１６２ｇ中の水、または水素をさらに低減させることができる。また、絶縁体１６２ｇに過剰酸素を有せしめることができる場合がある。加熱処理は、２５０℃以上６５０℃以下、好ましくは４５０℃以上６００℃以下、さらに好ましくは５２０℃以上５７０℃以下で行えばよい。加熱処理は、不活性ガス雰囲気、または酸化性ガスを１０ｐｐｍ以上、１％以上もしくは１０％以上含む雰囲気で行う。加熱処理は減圧状態で行ってもよい。または、加熱処理は、不活性ガス雰囲気で加熱処理した後に、脱離した酸素を補うために酸化性ガスを１０ｐｐｍ以上、１％以上または１０％以上含む雰囲気で加熱処理を行ってもよい。加熱処理によって、絶縁体１５６ｄ、半導体１５６ｂとなる半導体の結晶性を高めることや、水素や水などの不純物を除去することなどができる。加熱処理は、ランプ加熱によるＲＴＡ装置を用いることもできる。ＲＴＡ装置による加熱処理は、炉と比べて短時間で済むため、生産性を高めるために有効である。 Next, it is preferable to perform heat treatment. By performing heat treatment, water or hydrogen in the semiconductor to be the semiconductor 156b, the insulator 156d, or the insulator 162g can be further reduced. In some cases, the insulator 162g can be provided with excess oxygen. The heat treatment may be performed at 250 ° C to 650 ° C, preferably 450 ° C to 600 ° C, more preferably 520 ° C to 570 ° C. The heat treatment is performed in an inert gas atmosphere or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. The heat treatment may be performed in a reduced pressure state. Alternatively, the heat treatment may be performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more in order to supplement the desorbed oxygen after the heat treatment in an inert gas atmosphere. By the heat treatment, the crystallinity of the semiconductor to be the insulator 156d and the semiconductor 156b can be increased, or impurities such as hydrogen and water can be removed. For the heat treatment, an RTA apparatus using lamp heating can also be used. The heat treatment by the RTA apparatus is effective for improving productivity because it takes a shorter time than a furnace.
　次に、半導体上にレジストなどを形成し、該レジストなどを用いて加工し、半導体１５６ｂを形成する。それから、導電体１５８ｅ及び導電体１５８ｆの上にレジストなどを形成し、該レジストなどを用いて加工し、導電体１５８ｃ及び導電体１５８ｄを形成する（図６（Ａ）（Ｂ）参照。）。 Next, a resist or the like is formed over the semiconductor, and the semiconductor 156b is formed by processing using the resist or the like. Then, a resist or the like is formed over the conductor 158e and the conductor 158f and processed using the resist or the like to form the conductor 158c and the conductor 158d (see FIGS. 6A and 6B).
　さらに半導体１５６ｂ形成後に、加熱処理を行うことが好ましい。加熱処理を行うことで、半導体１５６ｂ、絶縁体１５６ｄまたは絶縁体１６２ｇ中の水、または水素をさらに低減させることができる。また、絶縁体１６２ｇに過剰酸素を有せしめることができる場合がある。加熱処理は、２５０℃以上６５０℃以下、好ましくは４５０℃以上６００℃以下、さらに好ましくは５２０℃以上５７０℃以下で行えばよい。加熱処理は、不活性ガス雰囲気、または酸化性ガスを１０ｐｐｍ以上、１％以上もしくは１０％以上含む雰囲気で行う。加熱処理は減圧状態で行ってもよい。または、加熱処理は、不活性ガス雰囲気で加熱処理した後に、脱離した酸素を補うために酸化性ガスを１０ｐｐｍ以上、１％以上または１０％以上含む雰囲気で加熱処理を行ってもよい。加熱処理によって、絶縁体１５６ｄ、半導体１５６ｂの結晶性を高めることや、水素や水などの不純物を除去することなどができる。加熱処理は、ランプ加熱によるＲＴＡ装置を用いることもできる。ＲＴＡ装置による加熱処理は、炉と比べて短時間で済むため、生産性を高めるために有効である。 Further, it is preferable to perform heat treatment after the semiconductor 156b is formed. By performing heat treatment, water or hydrogen in the semiconductor 156b, the insulator 156d, or the insulator 162g can be further reduced. In some cases, the insulator 162g can be provided with excess oxygen. The heat treatment may be performed at 250 ° C to 650 ° C, preferably 450 ° C to 600 ° C, more preferably 520 ° C to 570 ° C. The heat treatment is performed in an inert gas atmosphere or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. The heat treatment may be performed in a reduced pressure state. Alternatively, the heat treatment may be performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more in order to supplement the desorbed oxygen after the heat treatment in an inert gas atmosphere. By the heat treatment, crystallinity of the insulator 156d and the semiconductor 156b can be increased, impurities such as hydrogen and water can be removed, and the like. For the heat treatment, an RTA apparatus using lamp heating can also be used. The heat treatment by the RTA apparatus is effective for improving productivity because it takes a shorter time than a furnace.
　また、高密度プラズマ処理などを行ってもよい。高密度プラズマは、マイクロ波を用いて生成すればよい。高密度プラズマ処理では、例えば、酸素、亜酸化窒素などの酸化性ガスを用いればよい。または、酸化性ガスと、Ｈｅ、Ａｒ、Ｋｒ、Ｘｅなどの希ガスと、の混合ガスを用いてもよい。高密度プラズマ処理において、基板にバイアスを印加してもよい。これにより、プラズマ中の酸素イオンなどを基板側に引き込むことができる。高密度プラズマ処理は基板を加熱しながら行ってもよい。例えば、上記加熱処理の代わりに高密度プラズマ処理を行う場合、上記加熱処理の温度より低温で同様の効果を得ることができる。高密度プラズマ処理は、絶縁体１５６ｄの成膜前に行ってもよいし、後述する絶縁体１６７の開口形成後に行ってもよいし、後述する絶縁体１５６ｆ形成後などに行ってもよい。 Further, high-density plasma treatment may be performed. The high density plasma may be generated using microwaves. In the high-density plasma treatment, for example, an oxidizing gas such as oxygen or nitrous oxide may be used. Alternatively, a mixed gas of an oxidizing gas and a rare gas such as He, Ar, Kr, or Xe may be used. In high-density plasma processing, a bias may be applied to the substrate. Thereby, oxygen ions or the like in the plasma can be drawn to the substrate side. The high density plasma treatment may be performed while heating the substrate. For example, when high-density plasma treatment is performed instead of the heat treatment, the same effect can be obtained at a temperature lower than the temperature of the heat treatment. The high-density plasma treatment may be performed before the formation of the insulator 156d, may be performed after the opening of the insulator 167 described later, or may be performed after the formation of the insulator 156f described later.
　次に、導電体１５８ａ及び導電体１５８ｂとなる導電体を成膜する。導電体上にレジストなどを形成し、該レジストなどを用いて加工し、導電体を島状に形成する。導電体としては上述の導電体１０８ａ及び導電体１０８ｂとして用いることができる導電体を用いればよい。導電体の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法またはＰＬＤ法、ＡＬＤ法などを用いて行うことができる。 Next, a conductor to be the conductor 158a and the conductor 158b is formed. A resist or the like is formed over the conductor and processed using the resist or the like to form the conductor in an island shape. As the conductor, a conductor that can be used as the conductor 108a and the conductor 108b described above may be used. The conductor can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.
　次に、絶縁体１６７となる絶縁体を成膜する。絶縁体としては上述の絶縁体１１２として用いることができる絶縁体を用いればよい。絶縁体の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法またはＰＬＤ法、ＡＬＤ法などを用いて行うことができる。 Next, an insulator to be the insulator 167 is formed. As the insulator, an insulator that can be used as the above-described insulator 112 may be used. The insulator can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
　次に、絶縁体上にレジストなどを形成し、該レジストなどを用いて加工し、絶縁体１６７、導電体１５８ａ及び導電体１５８ｂを形成する（図６（Ｃ）（Ｄ）参照。）。 Next, a resist or the like is formed over the insulator and processed using the resist or the like to form the insulator 167, the conductor 158a, and the conductor 158b (see FIGS. 6C and 6D).
　次に、後の工程で絶縁体１５６ｃとなる絶縁体１５６ｅを成膜する（図６（Ｅ）（Ｆ）参照。）。絶縁体１５６ｅとしては上述の絶縁体１０６ａとして用いることができる絶縁体または半導体などを用いればよい。絶縁体１５６ｅの成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法またはＰＬＤ法、ＡＬＤ法などを用いて行うことができる。 Next, an insulator 156e to be an insulator 156c in a later step is formed (see FIGS. 6E and 6F). As the insulator 156e, an insulator, a semiconductor, or the like that can be used as the above-described insulator 106a may be used. The insulator 156e can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
　次に、絶縁体１５６ｅ上にレジストなどを形成し、該レジストなどを用いて加工し、絶縁体１５６ｆ及び絶縁体１５６ａを形成する（図７（Ａ）（Ｂ）参照。）。ここで、絶縁体１５６ｆと絶縁体１５６ａのＢ３−Ｂ４方向の側面端部は概略一致するように形成される。 Next, a resist or the like is formed over the insulator 156e and processed using the resist or the like to form the insulator 156f and the insulator 156a (see FIGS. 7A and 7B). Here, the side end portions in the B3-B4 direction of the insulator 156f and the insulator 156a are formed so as to substantially coincide with each other.
　次に、後の工程で絶縁体１６２ｄとなる絶縁体を成膜する。絶縁体としては上述の絶縁体１１２として用いることができる絶縁体または半導体などを用いればよい。絶縁体の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法またはＰＬＤ法、ＡＬＤ法などを用いて行うことができる。 Next, an insulator to be an insulator 162d is formed in a later step. As the insulator, an insulator, a semiconductor, or the like that can be used as the above-described insulator 112 may be used. The insulator can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
　次に、絶縁体上にレジストなどを形成し、該レジストなどを用いて加工し、絶縁体１６２ａ、絶縁体１６２ｂ、絶縁体１６２ｃ及び絶縁体１６２ｈを形成する（図７（Ｃ）（Ｄ）参照。）。ここで、絶縁体１６２ａ、絶縁体１６２ｂ、絶縁体１６２ｃ及び絶縁体１６２ｈのＢ３−Ｂ４方向の側面端部は概略一致するように形成される。 Next, a resist or the like is formed over the insulator and processed using the resist or the like to form the insulator 162a, the insulator 162b, the insulator 162c, and the insulator 162h (see FIGS. 7C and 7D). .) Here, the side end portions in the B3-B4 direction of the insulator 162a, the insulator 162b, the insulator 162c, and the insulator 162h are formed so as to substantially coincide with each other.
　次に、導電体１６４ｂとなる導電体を成膜する。導電体としては、上述の導電体１１４として用いることができる導電体を用いればよい。導電体の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法またはＰＬＤ法、ＡＬＤ法などを用いて行うことができる。 Next, a conductor to be the conductor 164b is formed. As the conductor, a conductor that can be used as the above-described conductor 114 may be used. The conductor can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.
　次に、導電体上から絶縁体１６７が露出するまで研磨をすることで、導電体１６４ｂ、絶縁体１６２ｄおよび絶縁体１５６ｃを形成する（図７（Ｅ）（Ｆ）参照。）。導電体１６４ｂおよび絶縁体１６２ｄは、それぞれトランジスタ５０のゲート電極およびゲート絶縁体としての機能を有する。上述した方法によって、導電体１６４ｂおよび絶縁体１６２ｄを自己整合的に形成することができる。 Next, polishing is performed from above the conductor until the insulator 167 is exposed, whereby the conductor 164b, the insulator 162d, and the insulator 156c are formed (see FIGS. 7E and 7F). The conductor 164b and the insulator 162d function as a gate electrode and a gate insulator of the transistor 50, respectively. By the above-described method, the conductor 164b and the insulator 162d can be formed in a self-aligning manner.
　さらに、保護絶縁膜として機能する絶縁体を成膜してもよい。絶縁体としては上述の絶縁体１５１として用いることができる絶縁体を用いればよい。絶縁体の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法またはＰＬＤ法、ＡＬＤ法などを用いて行うことができる。ここで、酸素を含む雰囲気でスパッタリング法を用いて絶縁体の成膜をおこなうことにより、成膜と同時に絶縁体１６２ｄ及び絶縁体１６７の表面近傍に酸素を添加することができる。 Further, an insulator that functions as a protective insulating film may be formed. An insulator that can be used as the above-described insulator 151 may be used as the insulator. The insulator can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Here, by forming an insulator using a sputtering method in an atmosphere containing oxygen, oxygen can be added to the vicinity of the surfaces of the insulator 162d and the insulator 167 at the same time as the film formation.
　次に、加熱処理を行うことが好ましい。加熱処理を行うことにより、絶縁体１６２ｃ、絶縁体１６２ｄ及び絶縁体１６７に添加した酸素を拡散させ、絶縁体１５６ａ、半導体１５６ｂ、絶縁体１５６ｃに供給することができる。 Next, it is preferable to perform heat treatment. By performing heat treatment, oxygen added to the insulator 162c, the insulator 162d, and the insulator 167 can be diffused and supplied to the insulator 156a, the semiconductor 156b, and the insulator 156c.
　以上の工程により、本発明の一態様に係るトランジスタを作製することができる。 Through the above process, the transistor according to one embodiment of the present invention can be manufactured.
　以上、本実施の形態で示す構成、方法は、他の実施の形態で示す構成、方法と適宜組み合わせて用いることができる。 As described above, the structures and methods described in this embodiment can be combined as appropriate with any of the structures and methods described in the other embodiments.
（実施の形態２）
　本実施の形態では、本発明の一態様の半導体装置に含まれる酸化物半導体の詳細について、以下説明する。 (Embodiment 2)
In this embodiment, details of an oxide semiconductor included in the semiconductor device of one embodiment of the present invention are described below.
＜酸化物半導体の構造＞
　以下では、酸化物半導体の構造について説明する。 <Structure of oxide semiconductor>
Hereinafter, the structure of the oxide semiconductor is described.
　酸化物半導体は、単結晶酸化物半導体と、それ以外の非単結晶酸化物半導体と、に分けられる。非単結晶酸化物半導体としては、ＣＡＡＣ−ＯＳ（ｃ−ａｘｉｓ−ａｌｉｇｎｅｄ　ｃｒｙｓｔａｌｌｉｎｅ　ｏｘｉｄｅ　ｓｅｍｉｃｏｎｄｕｃｔｏｒ）、多結晶酸化物半導体、ｎｃ−ＯＳ（ｎａｎｏｃｒｙｓｔａｌｌｉｎｅ　ｏｘｉｄｅ　ｓｅｍｉｃｏｎｄｕｃｔｏｒ）、擬似非晶質酸化物半導体（ａ−ｌｉｋｅ　ＯＳ：ａｍｏｒｐｈｏｕｓ−ｌｉｋｅ　ｏｘｉｄｅ　ｓｅｍｉｃｏｎｄｕｃｔｏｒ）および非晶質酸化物半導体などがある。 An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single crystal oxide semiconductor. As the non-single-crystal oxide semiconductor, a CAAC-OS (c-axis-aligned crystal oxide semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline oxide semiconductor), a pseudo-amorphous oxide semiconductor (a-like oxide OS) : Amorphous-like oxide semiconductor) and amorphous oxide semiconductor.
　また別の観点では、酸化物半導体は、非晶質酸化物半導体と、それ以外の結晶性酸化物半導体と、に分けられる。結晶性酸化物半導体としては、単結晶酸化物半導体、ＣＡＡＣ−ＯＳ、多結晶酸化物半導体およびｎｃ−ＯＳなどがある。 From another point of view, oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxide semiconductors. Examples of a crystalline oxide semiconductor include a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and an nc-OS.
　非晶質構造は、一般に、等方的であって不均質構造を持たない、準安定状態で原子の配置が固定化していない、結合角度が柔軟である、短距離秩序は有するが長距離秩序を有さない、などといわれている。 Amorphous structures are generally isotropic, have no heterogeneous structure, are metastable, have no fixed atomic arrangement, have a flexible bond angle, have short-range order, but long-range order It is said that it does not have.
　即ち、安定な酸化物半導体を完全な非晶質（ｃｏｍｐｌｅｔｅｌｙ　ａｍｏｒｐｈｏｕｓ）酸化物半導体とは呼べない。また、等方的でない（例えば、微小な領域において周期構造を有する）酸化物半導体を、完全な非晶質酸化物半導体とは呼べない。一方、ａ−ｌｉｋｅ　ＯＳは、等方的でないが、鬆（ボイドともいう。）を有する不安定な構造である。不安定であるという点では、ａ−ｌｉｋｅ　ＯＳは、物性的に非晶質酸化物半導体に近い。 That is, a stable oxide semiconductor cannot be called a complete amorphous oxide semiconductor. In addition, an oxide semiconductor that is not isotropic (for example, has a periodic structure in a minute region) cannot be called a complete amorphous oxide semiconductor. On the other hand, an a-like OS is not isotropic but has an unstable structure having a void (also referred to as a void). In terms of being unstable, a-like OS is physically similar to an amorphous oxide semiconductor.
＜ＣＡＡＣ−ＯＳ＞
　まずは、ＣＡＡＣ−ＯＳについて説明する。 <CAAC-OS>
First, the CAAC-OS will be described.
　ＣＡＡＣ−ＯＳは、ｃ軸配向した複数の結晶部（ペレットともいう。）を有する酸化物半導体の一種である。 CAAC-OS is a kind of oxide semiconductor having a plurality of c-axis aligned crystal parts (also referred to as pellets).
　ＣＡＡＣ−ＯＳをＸ線回折（ＸＲＤ：Ｘ−Ｒａｙ　Ｄｉｆｆｒａｃｔｉｏｎ）によって解析した場合について説明する。例えば、空間群Ｒ−３ｍに分類されるＩｎＧａＺｎＯ４の結晶を有するＣＡＡＣ−ＯＳに対し、ｏｕｔ−ｏｆ−ｐｌａｎｅ法による構造解析を行うと、図１１（Ａ）に示すように回折角（２θ）が３１°近傍にピークが現れる。このピークは、ＩｎＧａＺｎＯ４の結晶の（００９）面に帰属されることから、ＣＡＡＣ−ＯＳでは、結晶がｃ軸配向性を有し、ｃ軸がＣＡＡＣ−ＯＳの膜を形成する面（被形成面ともいう。）、または上面に略垂直な方向を向いていることが確認できる。なお、２θが３１°近傍のピークの他に、２θが３６°近傍にもピークが現れる場合がある。２θが３６°近傍のピークは、空間群Ｆｄ−３ｍに分類される結晶構造に起因する。そのため、ＣＡＡＣ−ＯＳは、該ピークを示さないことが好ましい。 A case where the CAAC-OS is analyzed by X-ray diffraction (XRD: X-Ray Diffraction) is described. For example, when CAAC-OS having an InGaZnO 4 crystal classified into the space group R-3m is subjected to structural analysis by an out-of-plane method, a diffraction angle (2θ) as illustrated in FIG. Shows a peak near 31 °. Since this peak is attributed to the (009) plane of the InGaZnO 4 crystal, in CAAC-OS, the crystal has a c-axis orientation, and the plane on which the c-axis forms a CAAC-OS film (formation target) It can also be confirmed that it faces a direction substantially perpendicular to the upper surface. In addition to the peak where 2θ is around 31 °, a peak may also appear when 2θ is around 36 °. The peak where 2θ is around 36 ° is attributed to the crystal structure classified into the space group Fd-3m. Therefore, the CAAC-OS preferably does not show the peak.
　一方、ＣＡＡＣ−ＯＳに対し、被形成面に平行な方向からＸ線を入射させるｉｎ−ｐｌａｎｅ法による構造解析を行うと、２θが５６°近傍にピークが現れる。このピークは、ＩｎＧａＺｎＯ４の結晶の（１１０）面に帰属される。そして、２θを５６°近傍に固定し、試料面の法線ベクトルを軸（φ軸）として試料を回転させながら分析（φスキャン）を行っても、図１１（Ｂ）に示すように明瞭なピークは現れない。一方、単結晶ＩｎＧａＺｎＯ４に対し、２θを５６°近傍に固定してφスキャンした場合、図１１（Ｃ）に示すように（１１０）面と等価な結晶面に帰属されるピークが６本観察される。したがって、ＸＲＤを用いた構造解析から、ＣＡＡＣ−ＯＳは、ａ軸およびｂ軸の配向が不規則であることが確認できる。 On the other hand, when structural analysis is performed on the CAAC-OS by an in-plane method in which X-rays are incident from a direction parallel to a formation surface, a peak appears at 2θ of around 56 °. This peak is attributed to the (110) plane of the InGaZnO 4 crystal. Further, even when 2θ is fixed in the vicinity of 56 ° and the analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis), as shown in FIG. No peak appears. On the other hand, when φ scan is performed with 2θ fixed at around 56 ° with respect to single crystal InGaZnO 4 , six peaks attributed to a crystal plane equivalent to the (110) plane are observed as shown in FIG. Is done. Therefore, structural analysis using XRD can confirm that the CAAC-OS has irregular orientations in the a-axis and the b-axis.
　次に、電子回折によって解析したＣＡＡＣ−ＯＳについて説明する。例えば、ＩｎＧａＺｎＯ４の結晶を有するＣＡＡＣ−ＯＳに対し、ＣＡＡＣ−ＯＳの被形成面に平行にプローブ径が３００ｎｍの電子線を入射させると、図１１（Ｄ）に示すような回折パターン（制限視野電子回折パターンともいう。）が現れる場合がある。この回折パターンには、ＩｎＧａＺｎＯ４の結晶の（００９）面に起因するスポットが含まれる。したがって、電子回折によっても、ＣＡＡＣ−ＯＳに含まれるペレットがｃ軸配向性を有し、ｃ軸が被形成面または上面に略垂直な方向を向いていることがわかる。一方、同じ試料に対し、試料面に垂直にプローブ径が３００ｎｍの電子線を入射させたときの回折パターンを図１１（Ｅ）に示す。図１１（Ｅ）より、リング状の回折パターンが確認される。したがって、プローブ径が３００ｎｍの電子線を用いた電子回折によっても、ＣＡＡＣ−ＯＳに含まれるペレットのａ軸およびｂ軸は配向性を有さないことがわかる。なお、図１１（Ｅ）における第１リングは、ＩｎＧａＺｎＯ４の結晶の（０１０）面および（１００）面などに起因すると考えられる。また、図１１（Ｅ）における第２リングは（１１０）面などに起因すると考えられる。 Next, a CAAC-OS analyzed by electron diffraction will be described. For example, when an electron beam with a probe diameter of 300 nm is incident on a CAAC-OS including an InGaZnO 4 crystal in parallel with a formation surface of the CAAC-OS, a diffraction pattern (restricted field of view) illustrated in FIG. Sometimes referred to as an electron diffraction pattern). This diffraction pattern includes spots caused by the (009) plane of the InGaZnO 4 crystal. Therefore, electron diffraction shows that the pellets included in the CAAC-OS have c-axis alignment, and the c-axis is in a direction substantially perpendicular to the formation surface or the top surface. On the other hand, FIG. 11E shows a diffraction pattern obtained when an electron beam with a probe diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample surface. From FIG. 11E, a ring-shaped diffraction pattern is confirmed. Therefore, it can be seen that the a-axis and the b-axis of the pellet included in the CAAC-OS have no orientation even by electron diffraction using an electron beam with a probe diameter of 300 nm. Note that the first ring in FIG. 11E is considered to originate from the (010) plane and the (100) plane of the InGaZnO 4 crystal. Further, it is considered that the second ring in FIG. 11E is caused by the (110) plane or the like.
　また、透過型電子顕微鏡（ＴＥＭ：Ｔｒａｎｓｍｉｓｓｉｏｎ　Ｅｌｅｃｔｒｏｎ　Ｍｉｃｒｏｓｃｏｐｅ）によって、ＣＡＡＣ−ＯＳの明視野像と回折パターンとの複合解析像（高分解能ＴＥＭ像ともいう。）を観察すると、複数のペレットを確認することができる。一方、高分解能ＴＥＭ像であってもペレット同士の境界、即ち結晶粒界（グレインバウンダリーともいう。）を明確に確認することができない場合がある。そのため、ＣＡＡＣ−ＯＳは、結晶粒界に起因する電子移動度の低下が起こりにくいといえる。 In addition, when a composite analysis image (also referred to as a high-resolution TEM image) of a bright-field image and a diffraction pattern of a CAAC-OS is observed with a transmission electron microscope (TEM: Transmission Electron Microscope), a plurality of pellets are confirmed. Can do. On the other hand, even in a high-resolution TEM image, the boundary between pellets, that is, a crystal grain boundary (also referred to as a grain boundary) may not be clearly confirmed. Therefore, it can be said that the CAAC-OS does not easily lower the electron mobility due to the crystal grain boundary.
　図１２（Ａ）に、試料面と略平行な方向から観察したＣＡＡＣ−ＯＳの断面の高分解能ＴＥＭ像を示す。高分解能ＴＥＭ像の観察には、球面収差補正（Ｓｐｈｅｒｉｃａｌ　Ａｂｅｒｒａｔｉｏｎ　Ｃｏｒｒｅｃｔｏｒ）機能を用いた。球面収差補正機能を用いた高分解能ＴＥＭ像を、特にＣｓ補正高分解能ＴＥＭ像と呼ぶ。Ｃｓ補正高分解能ＴＥＭ像は、例えば、日本電子株式会社製原子分解能分析電子顕微鏡ＪＥＭ−ＡＲＭ２００Ｆなどによって観察することができる。 FIG. 12A shows a high-resolution TEM image of a cross section of the CAAC-OS observed from a direction substantially parallel to the sample surface. For observation of the high-resolution TEM image, a spherical aberration correction function was used. A high-resolution TEM image using the spherical aberration correction function is particularly referred to as a Cs-corrected high-resolution TEM image. The Cs-corrected high resolution TEM image can be observed, for example, with an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.
　図１２（Ａ）より、金属原子が層状に配列している領域であるペレットを確認することができる。ペレット一つの大きさは１ｎｍ以上のものや、３ｎｍ以上のものがあることがわかる。したがって、ペレットを、ナノ結晶（ｎｃ：ｎａｎｏｃｒｙｓｔａｌ）と呼ぶこともできる。また、ＣＡＡＣ−ＯＳを、ＣＡＮＣ（Ｃ−Ａｘｉｓ　Ａｌｉｇｎｅｄ　ｎａｎｏｃｒｙｓｔａｌｓ）を有する酸化物半導体と呼ぶこともできる。ペレットは、ＣＡＡＣ−ＯＳの膜を被形成面または上面の凹凸を反映しており、ＣＡＡＣ−ＯＳの被形成面または上面と平行となる。 From FIG. 12A, a pellet which is a region where metal atoms are arranged in layers can be confirmed. It can be seen that the size of one pellet is 1 nm or more and 3 nm or more. Therefore, the pellet can also be referred to as a nanocrystal (nc). The CAAC-OS can also be referred to as an oxide semiconductor including CANC (C-Axis aligned nanocrystals). The pellet reflects the unevenness of the surface or top surface of the CAAC-OS film, and is parallel to the surface or top surface of the CAAC-OS.
　また、図１２（Ｂ）および図１２（Ｃ）に、試料面と略垂直な方向から観察したＣＡＡＣ−ＯＳの平面のＣｓ補正高分解能ＴＥＭ像を示す。図１２（Ｄ）および図１２（Ｅ）は、それぞれ図１２（Ｂ）および図１２（Ｃ）を画像処理した像である。以下では、画像処理の方法について説明する。まず、図１２（Ｂ）を高速フーリエ変換（ＦＦＴ：Ｆａｓｔ　Ｆｏｕｒｉｅｒ　Ｔｒａｎｓｆｏｒｍ）処理することでＦＦＴ像を取得する。次に、取得したＦＦＴ像において原点を基準に、２．８ｎｍ−１から５．０ｎｍ−１の間の範囲を残すマスク処理する。次に、マスク処理したＦＦＴ像を、逆高速フーリエ変換（ＩＦＦＴ：Ｉｎｖｅｒｓｅ　Ｆａｓｔ　Ｆｏｕｒｉｅｒ　Ｔｒａｎｓｆｏｒｍ）処理することで画像処理した像を取得する。こうして取得した像をＦＦＴフィルタリング像と呼ぶ。ＦＦＴフィルタリング像は、Ｃｓ補正高分解能ＴＥＭ像から周期成分を抜き出した像であり、格子配列を示している。 FIGS. 12B and 12C show Cs-corrected high-resolution TEM images of the plane of the CAAC-OS observed from a direction substantially perpendicular to the sample surface. FIGS. 12D and 12E are images obtained by performing image processing on FIGS. 12B and 12C, respectively. Hereinafter, an image processing method will be described. First, an FFT image is acquired by performing a Fast Fourier Transform (FFT) process on FIG. Then, relative to the origin in the FFT image acquired, for masking leaves a range between 5.0 nm -1 from 2.8 nm -1. Next, the FFT-processed mask image is subjected to an inverse fast Fourier transform (IFFT) process to obtain an image-processed image. The image acquired in this way is called an FFT filtered image. The FFT filtered image is an image obtained by extracting periodic components from the Cs-corrected high-resolution TEM image, and shows a lattice arrangement.
　図１２（Ｄ）では、格子配列の乱れた箇所を破線で示している。破線で囲まれた領域が、一つのペレットである。そして、破線で示した箇所がペレットとペレットとの連結部である。破線は、六角形状であるため、ペレットが六角形状であることがわかる。なお、ペレットの形状は、正六角形状とは限らず、非正六角形状である場合が多い。 In FIG. 12D, the portion where the lattice arrangement is disturbed is indicated by a broken line. A region surrounded by a broken line is one pellet. And the location shown with the broken line is the connection part of a pellet and a pellet. Since the broken line has a hexagonal shape, it can be seen that the pellet has a hexagonal shape. In addition, the shape of a pellet is not necessarily a regular hexagonal shape, and is often a non-regular hexagonal shape.
　図１２（Ｅ）では、格子配列の揃った領域と、別の格子配列の揃った領域と、の間で格子配列の向きが変化している箇所を点線で示し、格子配列の向きの変化を破線で示している。点線近傍においても、明確な結晶粒界を確認することはできない。点線近傍の格子点を中心に周囲の格子点を繋ぐと、歪んだ六角形や、五角形または／および七角形などが形成できる。即ち、格子配列を歪ませることによって結晶粒界の形成を抑制していることがわかる。これは、ＣＡＡＣ−ＯＳが、ａ−ｂ面方向において原子配列が稠密でないことや、金属元素が置換することで原子間の結合距離が変化することなどによって、歪みを許容することができるためと考えられる。 In FIG. 12 (E), a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangement is aligned and a region where another lattice arrangement is aligned is indicated by a dotted line, and the change in the orientation of the lattice arrangement is shown. It is indicated by a broken line. A clear crystal grain boundary cannot be confirmed even in the vicinity of the dotted line. By connecting the surrounding lattice points around the lattice points in the vicinity of the dotted line, a distorted hexagon, pentagon, and / or heptagon can be formed. That is, it can be seen that the formation of crystal grain boundaries is suppressed by distorting the lattice arrangement. This is because the CAAC-OS can tolerate distortion due to the fact that the atomic arrangement is not dense in the ab plane direction and the bond distance between atoms changes due to substitution of metal elements. Conceivable.
　以上に示すように、ＣＡＡＣ−ＯＳは、ｃ軸配向性を有し、かつａ−ｂ面方向において複数のペレット（ナノ結晶）が連結し、歪みを有した結晶構造となっている。よって、ＣＡＡＣ−ＯＳを、ＣＡＡ　ｃｒｙｓｔａｌ（ｃ−ａｘｉｓ−ａｌｉｇｎｅｄ　ａ−ｂ−ｐｌａｎｅ−ａｎｃｈｏｒｅｄ　ｃｒｙｓｔａｌ）と称することもできる。 As described above, the CAAC-OS has a c-axis orientation and a crystal structure in which a plurality of pellets (nanocrystals) are connected in the ab plane direction and have a strain. Therefore, the CAAC-OS can also be referred to as CAA crystal (c-axis-aligned ab-plane-anchored crystal).
　ＣＡＡＣ−ＯＳは結晶性の高い酸化物半導体である。酸化物半導体の結晶性は不純物の混入や欠陥の生成などによって低下する場合があるため、ＣＡＡＣ−ＯＳは不純物や欠陥（酸素欠損など）の少ない酸化物半導体ともいえる。 CAAC-OS is an oxide semiconductor with high crystallinity. Since the crystallinity of an oxide semiconductor may be deteriorated by entry of impurities, generation of defects, or the like, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies).
　なお、不純物は、酸化物半導体の主成分以外の元素で、水素、炭素、シリコン、遷移金属元素などがある。例えば、シリコンなどの、酸化物半導体を構成する金属元素よりも酸素との結合力の強い元素は、酸化物半導体から酸素を奪うことで酸化物半導体の原子配列を乱し、結晶性を低下させる要因となる。また、鉄やニッケルなどの重金属、アルゴン、二酸化炭素などは、原子半径（または分子半径）が大きいため、酸化物半導体の原子配列を乱し、結晶性を低下させる要因となる。 Note that the impurity means an element other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element. For example, an element such as silicon, which has a stronger bonding force with oxygen than a metal element included in an oxide semiconductor, disturbs the atomic arrangement of the oxide semiconductor by depriving the oxide semiconductor of oxygen, thereby reducing crystallinity. It becomes a factor. In addition, heavy metals such as iron and nickel, argon, carbon dioxide, and the like have large atomic radii (or molecular radii), which disturbs the atomic arrangement of the oxide semiconductor and decreases crystallinity.
　酸化物半導体が不純物や欠陥を有する場合、光や熱などによって特性が変動する場合がある。例えば、酸化物半導体に含まれる不純物は、キャリアトラップとなる場合や、キャリア発生源となる場合がある。例えば、酸化物半導体中の酸素欠損は、キャリアトラップとなる場合や、水素を捕獲することによってキャリア発生源となる場合がある。 When an oxide semiconductor has impurities or defects, characteristics may fluctuate due to light or heat. For example, an impurity contained in the oxide semiconductor might serve as a carrier trap or a carrier generation source. For example, oxygen vacancies in the oxide semiconductor may serve as carrier traps or may serve as carrier generation sources by capturing hydrogen.
　不純物および酸素欠損の少ないＣＡＡＣ−ＯＳは、キャリア密度の低い酸化物半導体である。具体的には、８×１０１１個／ｃｍ３未満、好ましくは１×１０１１個／ｃｍ３未満、さらに好ましくは１×１０１０個／ｃｍ３未満であり、１×１０−９個／ｃｍ３以上のキャリア密度の酸化物半導体とすることができる。そのような酸化物半導体を、高純度真性または実質的に高純度真性な酸化物半導体と呼ぶ。ＣＡＡＣ−ＯＳは、不純物濃度が低く、欠陥準位密度が低い。即ち、安定な特性を有する酸化物半導体であるといえる。 A CAAC-OS with few impurities and oxygen vacancies is an oxide semiconductor with low carrier density. Specifically, it is less than 8 × 10 11 pieces / cm 3 , preferably less than 1 × 10 11 pieces / cm 3 , more preferably less than 1 × 10 10 pieces / cm 3 , and 1 × 10 −9 pieces / cm 3. An oxide semiconductor having a carrier density of 3 or more can be obtained. Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. The CAAC-OS has a low impurity concentration and a low density of defect states. That is, it can be said that the oxide semiconductor has stable characteristics.
＜ｎｃ−ＯＳ＞
　次に、ｎｃ−ＯＳについて説明する。 <Nc-OS>
Next, the nc-OS will be described.
　ｎｃ−ＯＳをＸＲＤによって解析した場合について説明する。例えば、ｎｃ−ＯＳに対し、ｏｕｔ−ｏｆ−ｐｌａｎｅ法による構造解析を行うと、配向性を示すピークが現れない。即ち、ｎｃ−ＯＳの結晶は配向性を有さない。 A case where nc-OS is analyzed by XRD will be described. For example, when structural analysis is performed on the nc-OS by an out-of-plane method, a peak indicating orientation does not appear. That is, the nc-OS crystal has no orientation.
　また、例えば、ＩｎＧａＺｎＯ４の結晶を有するｎｃ−ＯＳを薄片化し、厚さが３４ｎｍの領域に対し、被形成面に平行にプローブ径が５０ｎｍの電子線を入射させると、図１３（Ａ）に示すようなリング状の回折パターン（ナノビーム電子回折パターン）が観測される。また、同じ試料にプローブ径が１ｎｍの電子線を入射させたときの回折パターン（ナノビーム電子回折パターン）を図１３（Ｂ）に示す。図１３（Ｂ）より、リング状の領域内に複数のスポットが観測される。したがって、ｎｃ−ＯＳは、プローブ径が５０ｎｍの電子線を入射させることでは秩序性が確認されないが、プローブ径が１ｎｍの電子線を入射させることでは秩序性が確認される。 For example, when an nc-OS including an InGaZnO 4 crystal is thinned and an electron beam with a probe diameter of 50 nm is incident on a region with a thickness of 34 nm in parallel to the formation surface, FIG. A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown is observed. FIG. 13B shows a diffraction pattern (nanobeam electron diffraction pattern) when an electron beam with a probe diameter of 1 nm is incident on the same sample. From FIG. 13B, a plurality of spots are observed in the ring-shaped region. Therefore, nc-OS does not confirm order when an electron beam with a probe diameter of 50 nm is incident, but confirms order when an electron beam with a probe diameter of 1 nm is incident.
　また、厚さが１０ｎｍ未満の領域に対し、プローブ径が１ｎｍの電子線を入射させると、図１３（Ｃ）に示すように、スポットが略正六角状に配置された電子回折パターンを観測される場合がある。したがって、厚さが１０ｎｍ未満の範囲において、ｎｃ−ＯＳが秩序性の高い領域、即ち結晶を有することがわかる。なお、結晶が様々な方向を向いているため、規則的な電子回折パターンが観測されない領域もある。 Further, when an electron beam having a probe diameter of 1 nm is incident on a region having a thickness of less than 10 nm, an electron diffraction pattern in which spots are arranged in a substantially regular hexagonal shape is observed as shown in FIG. There is a case. Therefore, it can be seen that the nc-OS has a highly ordered region, that is, a crystal in a thickness range of less than 10 nm. Note that there are some regions where a regular electron diffraction pattern is not observed because the crystal faces in various directions.
　図１３（Ｄ）に、被形成面と略平行な方向から観察したｎｃ−ＯＳの断面のＣｓ補正高分解能ＴＥＭ像を示す。ｎｃ−ＯＳは、高分解能ＴＥＭ像において、補助線で示す箇所などのように結晶部を確認することのできる領域と、明確な結晶部を確認することのできない領域と、を有する。ｎｃ−ＯＳに含まれる結晶部は、１ｎｍ以上１０ｎｍ以下の大きさであり、特に１ｎｍ以上３ｎｍ以下の大きさであることが多い。なお、結晶部の大きさが１０ｎｍより大きく１００ｎｍ以下である酸化物半導体を微結晶酸化物半導体（ｍｉｃｒｏ　ｃｒｙｓｔａｌｌｉｎｅ　ｏｘｉｄｅ　ｓｅｍｉｃｏｎｄｕｃｔｏｒ）と呼ぶことがある。ｎｃ−ＯＳは、例えば、高分解能ＴＥＭ像では、結晶粒界を明確に確認できない場合がある。なお、ナノ結晶は、ＣＡＡＣ−ＯＳにおけるペレットと起源を同じくする可能性がある。そのため、以下ではｎｃ−ＯＳの結晶部をペレットと呼ぶ場合がある。 FIG. 13D shows a Cs-corrected high-resolution TEM image of a cross section of the nc-OS observed from a direction substantially parallel to the formation surface. The nc-OS has a region in which a crystal part can be confirmed, such as a portion indicated by an auxiliary line, and a region in which a clear crystal part cannot be confirmed in a high-resolution TEM image. A crystal part included in the nc-OS has a size of 1 nm to 10 nm, particularly a size of 1 nm to 3 nm in many cases. Note that an oxide semiconductor in which the size of a crystal part is greater than 10 nm and less than or equal to 100 nm is sometimes referred to as a microcrystalline oxide semiconductor. For example, the nc-OS may not be able to clearly confirm a crystal grain boundary in a high-resolution TEM image. Note that the nanocrystal may have the same origin as the pellet in the CAAC-OS. Therefore, the crystal part of nc-OS is sometimes referred to as a pellet below.
　このように、ｎｃ−ＯＳは、微小な領域（例えば、１ｎｍ以上１０ｎｍ以下の領域、特に１ｎｍ以上３ｎｍ以下の領域）において原子配列に周期性を有する。また、ｎｃ−ＯＳは、異なるペレット間で結晶方位に規則性が見られない。そのため、膜全体で配向性が見られない。したがって、ｎｃ−ＯＳは、分析方法によっては、ａ−ｌｉｋｅ　ＯＳや非晶質酸化物半導体と区別が付かない場合がある。 Thus, nc-OS has periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS has no regularity in crystal orientation between different pellets. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS may not be distinguished from an a-like OS or an amorphous oxide semiconductor depending on an analysis method.
　なお、ペレット（ナノ結晶）間で結晶方位が規則性を有さないことから、ｎｃ−ＯＳを、ＲＡＮＣ（Ｒａｎｄｏｍ　Ａｌｉｇｎｅｄ　ｎａｎｏｃｒｙｓｔａｌｓ）を有する酸化物半導体、またはＮＡＮＣ（Ｎｏｎ−Ａｌｉｇｎｅｄ　ｎａｎｏｃｒｙｓｔａｌｓ）を有する酸化物半導体と呼ぶこともできる。 Note that since the crystal orientation is not regular between pellets (nanocrystals), nc-OS is an oxide semiconductor having RANC (Random Aligned nanocrystals), or an oxide having NANC (Non-Aligned nanocrystals). It can also be called a semiconductor.
　ｎｃ−ＯＳは、非晶質酸化物半導体よりも規則性の高い酸化物半導体である。そのため、ｎｃ−ＯＳは、ａ−ｌｉｋｅ　ＯＳや非晶質酸化物半導体よりも欠陥準位密度が低くなる。ただし、ｎｃ−ＯＳは、異なるペレット間で結晶方位に規則性が見られない。そのため、ｎｃ−ＯＳは、ＣＡＡＣ−ＯＳと比べて欠陥準位密度が高くなる。 Nc-OS is an oxide semiconductor having higher regularity than an amorphous oxide semiconductor. Therefore, the nc-OS has a lower density of defect states than an a-like OS or an amorphous oxide semiconductor. Note that the nc-OS does not have regularity in crystal orientation between different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.
＜ａ−ｌｉｋｅ　ＯＳ＞
　ａ−ｌｉｋｅ　ＯＳは、ｎｃ−ＯＳと非晶質酸化物半導体との間の構造を有する酸化物半導体である。 <A-like OS>
The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor.
　図１４に、ａ−ｌｉｋｅ　ＯＳの高分解能断面ＴＥＭ像を示す。ここで、図１４（Ａ）は電子照射開始時におけるａ−ｌｉｋｅ　ＯＳの高分解能断面ＴＥＭ像である。図１４（Ｂ）は４．３×１０８ｅ−／ｎｍ２の電子（ｅ−）照射後におけるａ−ｌｉｋｅ　ＯＳの高分解能断面ＴＥＭ像である。図１４（Ａ）および図１４（Ｂ）より、ａ−ｌｉｋｅ　ＯＳは電子照射開始時から、縦方向に延伸する縞状の明領域が観察されることがわかる。また、明領域は、電子照射後に形状が変化することがわかる。なお、明領域は、鬆または低密度領域と推測される。 FIG. 14 shows a high-resolution cross-sectional TEM image of the a-like OS. Here, FIG. 14A is a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation. FIG. 14B is a high-resolution cross-sectional TEM image of the a-like OS after irradiation with electrons (e − ) of 4.3 × 10 8 e − / nm 2 . From FIG. 14A and FIG. 14B, it can be seen that in the a-like OS, a striped bright region extending in the vertical direction is observed from the start of electron irradiation. It can also be seen that the shape of the bright region changes after electron irradiation. The bright region is assumed to be a void or a low density region.
　鬆を有するため、ａ−ｌｉｋｅ　ＯＳは、不安定な構造である。以下では、ａ−ｌｉｋｅ　ＯＳが、ＣＡＡＣ−ＯＳおよびｎｃ−ＯＳと比べて不安定な構造であることを示すため、電子照射による構造の変化を示す。 Since it has a void, the a-like OS has an unstable structure. Hereinafter, in order to show that the a-like OS has an unstable structure as compared with the CAAC-OS and the nc-OS, a change in structure due to electron irradiation is shown.
　試料として、ａ−ｌｉｋｅ　ＯＳ、ｎｃ−ＯＳおよびＣＡＡＣ−ＯＳを準備する。いずれの試料もＩｎ−Ｇａ−Ｚｎ酸化物である。 Prepare a-like OS, nc-OS, and CAAC-OS as samples. Each sample is an In—Ga—Zn oxide.
　まず、各試料の高分解能断面ＴＥＭ像を取得する。高分解能断面ＴＥＭ像により、各試料は、いずれも結晶部を有する。 First, a high-resolution cross-sectional TEM image of each sample is acquired. Each sample has a crystal part by a high-resolution cross-sectional TEM image.
　なお、ＩｎＧａＺｎＯ４の結晶の単位格子は、Ｉｎ−Ｏ層を３層有し、またＧａ−Ｚｎ−Ｏ層を６層有する、計９層がｃ軸方向に層状に重なった構造を有することが知られている。これらの近接する層同士の間隔は、（００９）面の格子面間隔（ｄ値ともいう。）と同程度であり、結晶構造解析からその値は０．２９ｎｍと求められている。したがって、以下では、格子縞の間隔が０．２８ｎｍ以上０．３０ｎｍ以下である箇所を、ＩｎＧａＺｎＯ４の結晶部と見なした。なお、格子縞は、ＩｎＧａＺｎＯ４の結晶のａ−ｂ面に対応する。 Note that a unit cell of an InGaZnO 4 crystal has a structure in which three In—O layers and six Ga—Zn—O layers have a total of nine layers stacked in the c-axis direction. Are known. The spacing between these adjacent layers is about the same as the lattice spacing (also referred to as d value) of the (009) plane, and the value is determined to be 0.29 nm from crystal structure analysis. Therefore, in the following, a portion where the interval between lattice fringes is 0.28 nm or more and 0.30 nm or less is regarded as a crystal part of InGaZnO 4 . Note that the lattice fringes correspond to the ab plane of the InGaZnO 4 crystal.
　図１５は、各試料の結晶部（２２箇所から３０箇所）の平均の大きさを調査した例である。なお、上述した格子縞の長さを結晶部の大きさとしている。図１５より、ａ−ｌｉｋｅ　ＯＳは、ＴＥＭ像の取得などに係る電子の累積照射量に応じて結晶部が大きくなっていくことがわかる。図１５より、ＴＥＭによる観察初期においては１．２ｎｍ程度の大きさだった結晶部（初期核ともいう。）が、電子（ｅ−）の累積照射量が４．２×１０８ｅ−／ｎｍ２においては１．９ｎｍ程度の大きさまで成長していることがわかる。一方、ｎｃ−ＯＳおよびＣＡＡＣ−ＯＳは、電子照射開始時から電子の累積照射量が４．２×１０８ｅ−／ｎｍ２までの範囲で、結晶部の大きさに変化が見られないことがわかる。図１５より、電子の累積照射量によらず、ｎｃ−ＯＳおよびＣＡＡＣ−ＯＳの結晶部の大きさは、それぞれ１．３ｎｍ程度および１．８ｎｍ程度であることがわかる。なお、電子線照射およびＴＥＭの観察は、日立透過電子顕微鏡Ｈ−９０００ＮＡＲを用いた。電子線照射条件は、加速電圧を３００ｋＶ、電流密度を６．７×１０５ｅ−／（ｎｍ２・ｓ）、照射領域の直径を２３０ｎｍとした。 FIG. 15 is an example in which the average size of the crystal parts (from 22 to 30) of each sample was examined. Note that the length of the lattice stripes described above is the size of the crystal part. From FIG. 15, it can be seen that in the a-like OS, the crystal part becomes larger in accordance with the cumulative dose of electrons related to acquisition of the TEM image or the like. From FIG. 15, the crystal part (also referred to as the initial nucleus), which was about 1.2 nm in the initial observation by TEM, has a cumulative electron (e − ) irradiation dose of 4.2 × 10 8 e − / nm. In FIG. 2 , it can be seen that the crystal has grown to a size of about 1.9 nm. On the other hand, in the nc-OS and the CAAC-OS, there is no change in the size of the crystal part in the range of the cumulative electron dose from the start of electron irradiation to 4.2 × 10 8 e − / nm 2. I understand. FIG. 15 shows that the crystal part sizes of the nc-OS and the CAAC-OS are approximately 1.3 nm and 1.8 nm, respectively, regardless of the cumulative electron dose. Note that a Hitachi transmission electron microscope H-9000NAR was used for electron beam irradiation and TEM observation. The electron beam irradiation conditions were an acceleration voltage of 300 kV, a current density of 6.7 × 10 5 e − / (nm 2 · s), and an irradiation region diameter of 230 nm.
　このように、ａ−ｌｉｋｅ　ＯＳは、電子照射によって結晶部の成長が見られる場合がある。一方、ｎｃ−ＯＳおよびＣＡＡＣ−ＯＳは、電子照射による結晶部の成長がほとんど見られない。即ち、ａ−ｌｉｋｅ　ＯＳは、ｎｃ−ＯＳおよびＣＡＡＣ−ＯＳと比べて、不安定な構造であることがわかる。 As described above, in the a-like OS, the crystal part may be grown by electron irradiation. On the other hand, in the nc-OS and the CAAC-OS, the crystal part is hardly grown by electron irradiation. That is, it can be seen that the a-like OS has an unstable structure as compared with the nc-OS and the CAAC-OS.
　また、鬆を有するため、ａ−ｌｉｋｅ　ＯＳは、ｎｃ−ＯＳおよびＣＡＡＣ−ＯＳと比べて密度の低い構造である。具体的には、ａ−ｌｉｋｅ　ＯＳの密度は、同じ組成の単結晶の密度の７８．６％以上９２．３％未満である。また、ｎｃ−ＯＳの密度およびＣＡＡＣ−ＯＳの密度は、同じ組成の単結晶の密度の９２．３％以上１００％未満である。単結晶の密度の７８％未満である酸化物半導体は、成膜すること自体が困難である。 Further, since it has a void, the a-like OS has a structure with a lower density than the nc-OS and the CAAC-OS. Specifically, the density of the a-like OS is 78.6% or more and less than 92.3% of the density of the single crystal having the same composition. Further, the density of the nc-OS and the density of the CAAC-OS are 92.3% or more and less than 100% of the density of the single crystal having the same composition. An oxide semiconductor having a density of less than 78% of the single crystal is difficult to form.
　例えば、Ｉｎ：Ｇａ：Ｚｎ＝１：１：１［原子数比］を満たす酸化物半導体において、菱面体晶構造を有する単結晶ＩｎＧａＺｎＯ４の密度は６．３５７ｇ／ｃｍ３である。よって、例えば、Ｉｎ：Ｇａ：Ｚｎ＝１：１：１［原子数比］を満たす酸化物半導体において、ａ−ｌｉｋｅ　ＯＳの密度は５．０ｇ／ｃｍ３以上５．９ｇ／ｃｍ３未満である。また、例えば、Ｉｎ：Ｇａ：Ｚｎ＝１：１：１［原子数比］を満たす酸化物半導体において、ｎｃ−ＯＳの密度およびＣＡＡＣ−ＯＳの密度は５．９ｇ／ｃｍ３以上６．３ｇ／ｃｍ３未満である。 For example, in an oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of single crystal InGaZnO 4 having a rhombohedral structure is 6.357 g / cm 3 . Thus, for example, in an oxide semiconductor that satisfies In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of a-like OS is 5.0 g / cm 3 or more and less than 5.9 g / cm 3. . For example, in the oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of the nc-OS and the density of the CAAC-OS is 5.9 g / cm 3 or more and 6.3 g / less than cm 3 .
　なお、同じ組成の単結晶が存在しない場合、任意の割合で組成の異なる単結晶を組み合わせることにより、所望の組成における単結晶に相当する密度を見積もることができる。所望の組成の単結晶に相当する密度は、組成の異なる単結晶を組み合わせる割合に対して、加重平均を用いて見積もればよい。ただし、密度は、可能な限り少ない種類の単結晶を組み合わせて見積もることが好ましい。 In addition, when single crystals having the same composition do not exist, the density corresponding to the single crystal having a desired composition can be estimated by combining single crystals having different compositions at an arbitrary ratio. What is necessary is just to estimate the density corresponding to the single crystal of a desired composition using a weighted average with respect to the ratio which combines the single crystal from which a composition differs. However, the density is preferably estimated by combining as few kinds of single crystals as possible.
　以上のように、酸化物半導体は、様々な構造をとり、それぞれが様々な特性を有する。なお、酸化物半導体は、例えば、非晶質酸化物半導体、ａ−ｌｉｋｅ　ＯＳ、ｎｃ−ＯＳ、ＣＡＡＣ−ＯＳのうち、二種以上を有する積層膜であってもよい。 As described above, oxide semiconductors have various structures and various properties. Note that the oxide semiconductor may be a stacked film including two or more of an amorphous oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS, for example.
　以上、本実施の形態で示す構成、方法は、他の実施の形態で示す構成、方法と適宜組み合わせて用いることができる。 As described above, the structures and methods described in this embodiment can be combined as appropriate with any of the structures and methods described in the other embodiments.
（実施の形態３）
　本実施の形態においては、本発明の一態様に係るトランジスタなどを利用した半導体装置の回路の一例について説明する。
＜回路＞
　以下では、本発明の一態様に係るトランジスタなどを利用した半導体装置の回路の一例について説明する。 (Embodiment 3)
In this embodiment, an example of a circuit of a semiconductor device using a transistor or the like according to one embodiment of the present invention will be described.
<Circuit>
An example of a circuit of a semiconductor device using a transistor or the like according to one embodiment of the present invention is described below.
＜ＣＭＯＳインバータ＞
　図１６（Ａ）に示す回路図は、ｐチャネル型のトランジスタ２２００とｎチャネル型のトランジスタ２１００を直列に接続し、かつそれぞれのゲートを接続した、いわゆるＣＭＯＳインバータの構成を示している。 <CMOS inverter>
The circuit diagram shown in FIG. 16A shows a structure of a so-called CMOS inverter in which a p-channel transistor 2200 and an n-channel transistor 2100 are connected in series and their gates are connected.
　図１６（Ａ）に示した半導体装置は、半導体基板を用いてｐチャネル型トランジスタを作製し、その上方にｎチャネル型トランジスタを作製することにより、素子の占有面積を縮小することができる。即ち、半導体装置の集積度を高くすることができる。また、ｎチャネル型トランジスタと、ｐチャネル型トランジスタとを同一の半導体基板を用いて作製した場合と比べて、工程を簡略化することができるため、半導体装置の生産性を高くすることができる。また、半導体装置の歩留まりを高くすることができる。また、ｐチャネル型トランジスタは、ＬＤＤ（Ｌｉｇｈｔｌｙ　Ｄｏｐｅｄ　Ｄｒａｉｎ）領域、シャロートレンチ構造、歪み設計などの複雑な工程を省略できる場合がある。そのため、ｎチャネル型トランジスタを、半導体基板を用いて作製する場合と比べて、生産性および歩留まりを高くすることができる場合がある。 In the semiconductor device illustrated in FIG. 16A, a p-channel transistor is manufactured using a semiconductor substrate, and an n-channel transistor is formed thereabove, whereby the area occupied by the element can be reduced. That is, the degree of integration of the semiconductor device can be increased. Further, since the process can be simplified as compared with the case where an n-channel transistor and a p-channel transistor are formed using the same semiconductor substrate, the productivity of the semiconductor device can be increased. In addition, the yield of the semiconductor device can be increased. In addition, a p-channel transistor can sometimes omit complicated processes such as an LDD (Lightly Doped Drain) region, a shallow trench structure, and a strain design. Therefore, productivity and yield may be increased as compared with the case where an n-channel transistor is manufactured using a semiconductor substrate.
＜ＣＭＯＳアナログスイッチ＞
　また図１６（Ｂ）に示す回路図は、トランジスタ２１００とトランジスタ２２００のそれぞれのソースとドレインを接続した構成を示している。このような構成とすることで、いわゆるＣＭＯＳアナログスイッチとして機能させることができる。 <CMOS analog switch>
In addition, the circuit diagram illustrated in FIG. 16B illustrates a structure in which the sources and drains of the transistors 2100 and 2200 are connected to each other. With such a configuration, it can function as a so-called CMOS analog switch.
＜記憶装置１＞
　本発明の一態様に係るトランジスタを用いた、電力が供給されない状況でも記憶内容の保持が可能で、かつ、書き込み回数にも制限が無い半導体装置（記憶装置）の一例を図１７に示す。 <Storage device 1>
FIG. 17 illustrates an example of a semiconductor device (memory device) using the transistor according to one embodiment of the present invention, which can hold stored data even in a state where power is not supplied and has no limitation on the number of writing times.
　図１７（Ａ）に示す半導体装置は、第１の半導体を用いたトランジスタ３２００と第２の半導体を用いたトランジスタ３３００、および容量素子３４００を有している。なお、トランジスタ３３００としては、上述のトランジスタ２１００と同様のトランジスタを用いることができる。 The semiconductor device illustrated in FIG. 17A includes a transistor 3200 using a first semiconductor, a transistor 3300 using a second semiconductor, and a capacitor 3400. Note that as the transistor 3300, a transistor similar to the above-described transistor 2100 can be used.
　トランジスタ３３００は、オフ電流の小さいトランジスタが好ましい。トランジスタ３３００は、例えば、酸化物半導体を用いたトランジスタを用いることができる。トランジスタ３３００のオフ電流が小さいことにより、半導体装置の特定のノードに長期にわたり記憶内容を保持することが可能である。つまり、リフレッシュ動作を必要としない、またはリフレッシュ動作の頻度が極めて少なくすることが可能となるため、消費電力の低い半導体装置となる。 The transistor 3300 is preferably a transistor with a low off-state current. As the transistor 3300, for example, a transistor including an oxide semiconductor can be used. Since the off-state current of the transistor 3300 is small, stored data can be held in a specific node of the semiconductor device for a long time. That is, a refresh operation is not required or the frequency of the refresh operation can be extremely low, so that the semiconductor device with low power consumption is obtained.
　図１７（Ａ）において、第１の配線３００１はトランジスタ３２００のソースと電気的に接続され、第２の配線３００２はトランジスタ３２００のドレインと電気的に接続される。また、第３の配線３００３はトランジスタ３３００のソース、ドレインの一方と電気的に接続され、第４の配線３００４はトランジスタ３３００のゲートと電気的に接続されている。そして、トランジスタ３２００のゲート、およびトランジスタ３３００のソース、ドレインの他方は、容量素子３４００の電極の一方と電気的に接続され、第５の配線３００５は容量素子３４００の電極の他方と電気的に接続されている。 17A, the first wiring 3001 is electrically connected to the source of the transistor 3200, and the second wiring 3002 is electrically connected to the drain of the transistor 3200. The third wiring 3003 is electrically connected to one of a source and a drain of the transistor 3300, and the fourth wiring 3004 is electrically connected to the gate of the transistor 3300. The gate of the transistor 3200 and the other of the source and the drain of the transistor 3300 are electrically connected to one of the electrodes of the capacitor 3400, and the fifth wiring 3005 is electrically connected to the other of the electrodes of the capacitor 3400. Has been.
　図１７（Ａ）に示す半導体装置は、トランジスタ３２００のゲートの電位が保持可能という特性を有することで、以下に示すように、情報の書き込み、保持、読み出しが可能である。 The semiconductor device illustrated in FIG. 17A has a characteristic that the potential of the gate of the transistor 3200 can be held, so that information can be written, held, and read as described below.
　情報の書き込みおよび保持について説明する。まず、第４の配線３００４の電位を、トランジスタ３３００が導通状態となる電位にして、トランジスタ３３００を導通状態とする。これにより、第３の配線３００３の電位が、トランジスタ３２００のゲート、および容量素子３４００の電極の一方と電気的に接続するノードＦＧに与えられる。即ち、トランジスタ３２００のゲートには、所定の電荷が与えられる（書き込み）。ここでは、異なる二つの電位レベルを与える電荷（以下Ｌｏｗレベル電荷、Ｈｉｇｈレベル電荷という。）のどちらかが与えられるものとする。その後、第４の配線３００４の電位を、トランジスタ３３００が非導通状態となる電位にして、トランジスタ３３００を非導通状態とすることにより、ノードＦＧに電荷が保持される（保持）。 Describes the writing and holding of information. First, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned on, so that the transistor 3300 is turned on. Accordingly, the potential of the third wiring 3003 is supplied to the node FG electrically connected to one of the gate of the transistor 3200 and the electrode of the capacitor 3400. That is, predetermined charge is supplied to the gate of the transistor 3200 (writing). Here, it is assumed that one of two charges that give two different potential levels (hereinafter referred to as a Low level charge and a High level charge) is given. After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned off and the transistor 3300 is turned off, so that charge is held at the node FG (holding).
　トランジスタ３３００のオフ電流が小さいため、ノードＦＧの電荷は長期間にわたって保持される。 Since the off-state current of the transistor 3300 is small, the charge of the node FG is held for a long time.
　次に情報の読み出しについて説明する。第１の配線３００１に所定の電位（定電位）を与えた状態で、第５の配線３００５に適切な電位（読み出し電位）を与えると、第２の配線３００２は、ノードＦＧに保持された電荷量に応じた電位をとる。これは、トランジスタ３２００をｎチャネル型とすると、トランジスタ３２００のゲートにＨｉｇｈレベル電荷が与えられている場合の見かけ上のしきい値電圧Ｖｔｈ＿Ｈは、トランジスタ３２００のゲートにＬｏｗレベル電荷が与えられている場合の見かけ上のしきい値電圧Ｖｔｈ＿Ｌより低くなるためである。ここで、見かけ上のしきい値電圧とは、トランジスタ３２００を「導通状態」とするために必要な第５の配線３００５の電位をいうものとする。したがって、第５の配線３００５の電位をＶｔｈ＿ＨとＶｔｈ＿Ｌの間の電位Ｖ０とすることにより、ノードＦＧに与えられた電荷を判別できる。例えば、書き込みにおいて、ノードＦＧにＨｉｇｈレベル電荷が与えられていた場合には、第５の配線３００５の電位がＶ０（＞Ｖｔｈ＿Ｈ）となれば、トランジスタ３２００は「導通状態」となる。一方、ノードＦＧにＬｏｗレベル電荷が与えられていた場合には、第５の配線３００５の電位がＶ０（＜Ｖｔｈ＿Ｌ）となっても、トランジスタ３２００は「非導通状態」のままである。このため、第２の配線３００２の電位を判別することで、ノードＦＧに保持されている情報を読み出すことができる。 Next, reading of information will be described. When an appropriate potential (reading potential) is applied to the fifth wiring 3005 in a state where a predetermined potential (constant potential) is applied to the first wiring 3001, the second wiring 3002 has a charge held in the node FG. Take a potential according to the amount. This is because, when the transistor 3200 is an n-channel type, the apparent threshold voltage V th_H when a high level charge is applied to the gate of the transistor 3200 is the low level charge applied to the gate of the transistor 3200. This is because it becomes lower than the apparent threshold voltage V th_L in the case of being present. Here, the apparent threshold voltage refers to the potential of the fifth wiring 3005 necessary for bringing the transistor 3200 into a “conducting state”. Therefore, by setting the potential of the fifth wiring 3005 to a potential V 0 between V th_H and V th_L , the charge given to the node FG can be determined. For example, in the case where a high-level charge is applied to the node FG in writing, the transistor 3200 is in a “conducting state” if the potential of the fifth wiring 3005 is V 0 (> V th_H ). On the other hand, when a low-level charge is supplied to the node FG, the transistor 3200 remains in the “non-conductive state” even when the potential of the fifth wiring 3005 becomes V 0 (<V th_L ). Therefore, by determining the potential of the second wiring 3002, information held in the node FG can be read.
　なお、メモリセルをアレイ状に配置する場合、読み出し時には、所望のメモリセルの情報を読み出さなくてはならない。例えば、情報を読み出さないメモリセルにおいては、ノードＦＧに与えられた電荷によらずトランジスタ３２００が「非導通状態」となるような電位、つまり、Ｖｔｈ＿Ｈより低い電位を第５の配線３００５に与えることで所望のメモリセルの情報のみを読み出せる構成とすればよい。または、情報を読み出さないメモリセルにおいては、ノードＦＧに与えられた電荷によらずトランジスタ３２００が「導通状態」となるような電位、つまり、Ｖｔｈ＿Ｌより高い電位を第５の配線３００５に与えることで所望のメモリセルの情報のみを読み出せる構成とすればよい。 Note that when memory cells are arranged in an array, information of a desired memory cell must be read at the time of reading. For example, in a memory cell from which information is not read, the fifth wiring 3005 is supplied with a potential at which the transistor 3200 is in a “non-conducting state” regardless of the charge applied to the node FG, that is, a potential lower than V th_H. Thus, only a desired memory cell information may be read. Alternatively , in the memory cell from which information is not read, the fifth wiring 3005 is supplied with a potential at which the transistor 3200 becomes “conductive” regardless of the charge applied to the node FG, that is, a potential higher than V th_L. Thus, only the desired memory cell information may be read.
　なお、上記においては、２種類の電荷をノードＦＧに保持する例について示したが、本発明に係る半導体装置はこれに限られるものではない。例えば、半導体装置のノードＦＧに３種類以上の電荷をノードに保持できる構成としてもよい。このような構成とすることにより、当該半導体装置を多値化して記憶容量の増大を図ることができる。 In the above description, an example in which two types of charges are held in the node FG has been described. However, the semiconductor device according to the present invention is not limited to this. For example, a structure in which three or more kinds of electric charges can be held in the node FG of the semiconductor device may be employed. With such a structure, the semiconductor device can be multi-valued and the storage capacity can be increased.
＜記憶装置２＞
　図１７（Ｂ）に示す半導体装置は、トランジスタ３２００を有さない点で図１７（Ａ）に示した半導体装置と異なる。この場合も図１７（Ａ）に示した半導体装置と同様の動作により情報の書き込みおよび保持動作が可能である。 <Storage device 2>
The semiconductor device illustrated in FIG. 17B is different from the semiconductor device illustrated in FIG. 17A in that the transistor 3200 is not provided. In this case as well, information writing and holding operations can be performed by operations similar to those of the semiconductor device illustrated in FIG.
　図１７（Ｂ）に示す半導体装置における、情報の読み出しについて説明する。トランジスタ３３００が導通状態になると、浮遊状態である第３の配線３００３と容量素子３４００とが導通し、第３の配線３００３と容量素子３４００の間で電荷が再分配される。その結果、第３の配線３００３の電位が変化する。第３の配線３００３の電位の変化量は、容量素子３４００の電極の一方の電位（または容量素子３４００に蓄積された電荷）によって、異なる値をとる。 Reading of information in the semiconductor device illustrated in FIG. When the transistor 3300 is turned on, the floating third wiring 3003 and the capacitor 3400 are turned on, and charge is redistributed between the third wiring 3003 and the capacitor 3400. As a result, the potential of the third wiring 3003 changes. The amount of change in potential of the third wiring 3003 varies depending on one potential of the electrode of the capacitor 3400 (or charge accumulated in the capacitor 3400).
　例えば、容量素子３４００の電極の一方の電位をＶ、容量素子３４００の容量をＣ、第３の配線３００３が有する容量成分をＣＢ、電荷が再分配される前の第３の配線３００３の電位をＶＢ０とすると、電荷が再分配された後の第３の配線３００３の電位は、（ＣＢ×ＶＢ０＋ＣＶ）／（ＣＢ＋Ｃ）となる。したがって、メモリセルの状態として、容量素子３４００の電極の一方の電位がＶ１とＶ０（Ｖ１＞Ｖ０）の２つの状態をとるとすると、電位Ｖ１を保持している場合の第３の配線３００３の電位（＝（ＣＢ×ＶＢ０＋ＣＶ１）／（ＣＢ＋Ｃ））は、電位Ｖ０を保持している場合の第３の配線３００３の電位（＝（ＣＢ×ＶＢ０＋ＣＶ０）／（ＣＢ＋Ｃ））よりも高くなることがわかる。 For example, the potential of one electrode of the capacitor 3400 is V, the capacitance of the capacitor 3400 is C, the capacitance component of the third wiring 3003 is CB, and the potential of the third wiring 3003 before the charge is redistributed. Assuming VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB × VB0 + CV) / (CB + C). Therefore, if the potential of one of the electrodes of the capacitor 3400 assumes two states of V1 and V0 (V1> V0) as the state of the memory cell, the third wiring 3003 in the case where the potential V1 is held. It can be seen that the potential (= (CB × VB0 + CV1) / (CB + C)) is higher than the potential of the third wiring 3003 when the potential V0 is held (= (CB × VB0 + CV0) / (CB + C)). .
　そして、第３の配線３００３の電位を所定の電位と比較することで、情報を読み出すことができる。 Then, information can be read by comparing the potential of the third wiring 3003 with a predetermined potential.
　この場合、メモリセルを駆動させるための駆動回路に上記第１の半導体が適用されたトランジスタを用い、トランジスタ３３００として第２の半導体が適用されたトランジスタを駆動回路上に積層して配置する構成とすればよい。 In this case, a transistor to which the first semiconductor is applied is used as a driver circuit for driving the memory cell, and a transistor to which the second semiconductor is applied is stacked over the driver circuit as the transistor 3300. do it.
　以上に示した半導体装置は、酸化物半導体を用いたオフ電流の小さいトランジスタを適用することで、長期にわたって記憶内容を保持することが可能となる。つまり、リフレッシュ動作が不要となるか、またはリフレッシュ動作の頻度を極めて低くすることが可能となるため、消費電力の低い半導体装置を実現することができる。また、電力の供給がない場合（ただし、電位は固定されていることが好ましい）であっても、長期にわたって記憶内容を保持することが可能である。 In the semiconductor device described above, memory contents can be held for a long time by using a transistor with an off-state current that is formed using an oxide semiconductor. That is, a refresh operation is unnecessary or the frequency of the refresh operation can be extremely low, so that a semiconductor device with low power consumption can be realized. In addition, stored data can be held for a long time even when power is not supplied (note that a potential is preferably fixed).
　また、該半導体装置は、情報の書き込みに高い電圧が不要であるため、素子の劣化が起こりにくい。例えば、従来の不揮発性メモリのように、フローティングゲートへの電子の注入や、フローティングゲートからの電子の引き抜きを行わないため、絶縁体の劣化といった問題が生じない。即ち、本発明の一態様に係る半導体装置は、従来の不揮発性メモリで問題となっている書き換え可能回数に制限はなく、信頼性が飛躍的に向上した半導体装置である。さらに、トランジスタの導通状態、非導通状態によって、情報の書き込みが行われるため、高速な動作が可能となる。 In addition, since the semiconductor device does not require a high voltage for writing information, the element is hardly deteriorated. For example, unlike the conventional nonvolatile memory, since electrons are not injected into the floating gate and electrons are not extracted from the floating gate, there is no problem of deterioration of the insulator. In other words, the semiconductor device according to one embodiment of the present invention is a semiconductor device in which the number of rewritable times which is a problem in the conventional nonvolatile memory is not limited and the reliability is drastically improved. Further, since data is written depending on the conductive state and non-conductive state of the transistor, high-speed operation is possible.
＜記憶装置３＞
　図１７（Ａ）に示す半導体装置（記憶装置）の変形例について、図１８に示す回路図を用いて説明する。 <Storage device 3>
A modified example of the semiconductor device (memory device) illustrated in FIG. 17A is described with reference to a circuit diagram illustrated in FIG.
　図１８に示す半導体装置は、トランジスタ４１００乃至トランジスタ４４００と、容量素子４５００及び容量素子４６００と、を有する。ここでトランジスタ４１００は、上述のトランジスタ３２００と同様のトランジスタを用いることができ、トランジスタ４２００乃至４４００は、上述のトランジスタ３３００と同様のトランジスタを用いることができる。なお、図１８に示す半導体装置は、図１８では図示を省略したが、マトリクス状に複数設けられる。図１８に示す半導体装置は、配線４００１、配線４００３、配線４００５乃至４００９に与える信号又は電位に従って、データ電圧の書き込み、読み出しを制御することができる。 The semiconductor device illustrated in FIG. 18 includes transistors 4100 to 4400, a capacitor 4500, and a capacitor 4600. Here, the transistor 4100 can be a transistor similar to the above-described transistor 3200, and the transistors 4200 to 4400 can be the same transistor as the above-described transistor 3300. Note that the semiconductor device illustrated in FIG. 18 is not illustrated in FIG. 18, but a plurality of semiconductor devices are provided in a matrix. The semiconductor device illustrated in FIG. 18 can control writing and reading of a data voltage in accordance with a signal or a potential supplied to the wiring 4001, the wiring 4003, and the wirings 4005 to 4009.
　トランジスタ４１００のソース又はドレインの一方は、配線４００３に接続される。トランジスタ４１００のソース又はドレインの他方は、配線４００１に接続される。なお図１８では、トランジスタ４１００の導電型をｐチャネル型として示すが、ｎチャネル型でもよい。 One of the source and the drain of the transistor 4100 is connected to the wiring 4003. The other of the source and the drain of the transistor 4100 is connected to the wiring 4001. Note that although the conductivity type of the transistor 4100 is shown as a p-channel type in FIG. 18, it may be an n-channel type.
　図１８に示す半導体装置は、２つのデータ保持部を有する。例えば第１のデータ保持部は、ノードＦＧ１に接続されるトランジスタ４４００のソース又はドレインの一方、容量素子４６００の一方の電極、及びトランジスタ４２００のソース又はドレインの一方の間で電荷を保持する。また、第２のデータ保持部は、ノードＦＧ２に接続されるトランジスタ４１００のゲート、トランジスタ４２００のソース又はドレインの他方、トランジスタ４３００のソース又はドレインの一方、及び容量素子４５００の一方の電極の間で電荷を保持する。 The semiconductor device shown in FIG. 18 has two data holding units. For example, the first data holding portion holds charge between one of a source and a drain of the transistor 4400 connected to the node FG1, one electrode of the capacitor 4600, and one of the source and the drain of the transistor 4200. The second data holding portion is between the gate of the transistor 4100 connected to the node FG2, the other of the source and the drain of the transistor 4200, one of the source and the drain of the transistor 4300, and one electrode of the capacitor 4500. Holds charge.
　トランジスタ４３００のソース又はドレインの他方は、配線４００３に接続される。トランジスタ４４００のソース又はドレインの他方は、配線４００１に接続される。トランジスタ４４００のゲートは、配線４００５に接続される。トランジスタ４２００のゲートは、配線４００６に接続される。トランジスタ４３００のゲートは、配線４００７に接続される。容量素子４６００の他方の電極は、配線４００８に接続される。容量素子４５００の他方の電極は、配線４００９に接続される。 The other of the source and the drain of the transistor 4300 is connected to the wiring 4003. The other of the source and the drain of the transistor 4400 is connected to the wiring 4001. A gate of the transistor 4400 is connected to the wiring 4005. A gate of the transistor 4200 is connected to the wiring 4006. A gate of the transistor 4300 is connected to the wiring 4007. The other electrode of the capacitor 4600 is connected to the wiring 4008. The other electrode of the capacitor 4500 is connected to the wiring 4009.
　トランジスタ４２００乃至４４００は、データ電圧の書き込みと電荷の保持を制御するスイッチとしての機能を有する。なおトランジスタ４２００乃至４４００は、非導通状態においてソースとドレインとの間を流れる電流（オフ電流）が低いトランジスタが用いられることが好適である。オフ電流が少ないトランジスタとしては、チャネル形成領域に酸化物半導体を有するトランジスタ（ＯＳトランジスタ）であることが好ましい。ＯＳトランジスタは、オフ電流が低い、シリコンを有するトランジスタと重ねて作製できる等の利点がある。なお図１８では、トランジスタ４２００乃至１４の導電型をｎチャネル型として示すが、ｐチャネル型でもよい。 The transistors 4200 to 4400 have a function as a switch for controlling data voltage writing and charge holding. Note that as the transistors 4200 to 4400, transistors with low current (off-state current) flowing between the source and the drain in a non-conduction state are preferably used. The transistor with low off-state current is preferably a transistor having an oxide semiconductor in a channel formation region (OS transistor). An OS transistor has advantages such as low off-state current and that it can be formed over a transistor including silicon. Note that in FIG. 18, the conductivity types of the transistors 4200 to 14 are illustrated as n-channel types, but may be p-channel types.
　トランジスタ４２００及びトランジスタ４３００と、トランジスタ４４００とは、酸化物半導体を用いたトランジスタであっても別層に設けることが好ましい。すなわち、図１８に示す半導体装置は、図１８に示すように、トランジスタ４１００を有する第１の層４０２１と、トランジスタ４２００及びトランジスタ４３００を有する第２の層４０２２と、トランジスタ４４００を有する第３の層４０２３と、で構成されることが好ましい。トランジスタを有する層を積層して設けることで、回路面積を縮小することができ、半導体装置の小型化を図ることができる。 The transistor 4200, the transistor 4300, and the transistor 4400 are preferably provided in different layers even if a transistor including an oxide semiconductor is used. That is, the semiconductor device illustrated in FIG. 18 includes a first layer 4021 including a transistor 4100, a second layer 4022 including a transistor 4200 and a transistor 4300, and a third layer including a transistor 4400 as illustrated in FIG. 4023. By stacking layers including transistors, the circuit area can be reduced and the semiconductor device can be downsized.
　次いで、図１８に示す半導体装置への情報の書き込み動作について説明する。 Next, an operation of writing information to the semiconductor device shown in FIG. 18 will be described.
　最初に、ノードＦＧ１に接続されるデータ保持部へのデータ電圧の書き込み動作（以下、書き込み動作１とよぶ。）について説明する。なお、以下において、ノードＦＧ１に接続されるデータ保持部に書きこむデータ電圧をＶＤ１とし、トランジスタ４１００の閾値電圧をＶｔｈとする。 First, a data voltage write operation (hereinafter referred to as a write operation 1) to the data holding portion connected to the node FG1 will be described. Note that in the following description, the data voltage written to the data holding portion connected to the node FG1 is V D1, and the threshold voltage of the transistor 4100 is Vth.
　書き込み動作１では、配線４００３をＶＤ１とし、配線４００１を接地電位とした後に、電気的に浮遊状態とする。また配線４００５、４００６をハイレベルにする。また配線４００７乃至４００９をローレベルにする。すると、電気的に浮遊状態にあるノードＦＧ２の電位が上昇し、トランジスタ４１００に電流が流れる。電流が流れることで、配線４００１の電位が上昇する。またトランジスタ４４００、トランジスタ４２００が導通状態となる。そのため、配線４００１の電位の上昇につれて、ノードＦＧ１、ＦＧ２の電位が上昇する。ノードＦＧ２の電位が上昇し、トランジスタ４１００でゲートとソースとの間の電圧（Ｖｇｓ）がトランジスタ４１００の閾値電圧Ｖｔｈになると、トランジスタ４１００を流れる電流が小さくなる。そのため、配線４００１、ノードＦＧ１、ＦＧ２の電位の上昇は止まり、ＶＤ１からＶｔｈだけ下がった「ＶＤ１−Ｖｔｈ」で一定となる。 In the writing operation 1, after the wiring 4003 is set to V D1 and the wiring 4001 is set to the ground potential, the wiring 4001 is electrically floated. In addition, the wirings 4005 and 4006 are set to a high level. In addition, the wirings 4007 to 4009 are set to a low level. Then, the potential of the node FG2 which is in an electrically floating state is increased, and a current flows through the transistor 4100. When the current flows, the potential of the wiring 4001 increases. In addition, the transistors 4400 and 4200 are turned on. Therefore, the potentials of the nodes FG1 and FG2 increase as the potential of the wiring 4001 increases. When the potential of the node FG2 rises and the voltage (Vgs) between the gate and the source in the transistor 4100 becomes the threshold voltage Vth of the transistor 4100, the current flowing through the transistor 4100 decreases. Therefore, the potential increase of the wiring 4001 and the nodes FG1 and FG2 stops and becomes constant at “V D1 −Vth” which is lower than V D1 by Vth.
　つまり、配線４００３に与えたＶＤ１は、トランジスタ４１００に電流が流れることで、配線４００１に与えられ、ノードＦＧ１、ＦＧ２の電位が上昇する。電位の上昇によって、ノードＦＧ２の電位が「ＶＤ１−Ｖｔｈ」となると、トランジスタ４１００のＶｇｓがＶｔｈとなるため、電流が止まる。 That is, V D1 applied to the wiring 4003 is supplied to the wiring 4001 when current flows through the transistor 4100, so that the potentials of the nodes FG1 and FG2 are increased. When the potential of the node FG2 becomes “V D1 −Vth” due to the rise in potential, Vgs of the transistor 4100 becomes Vth, so that the current stops.
　次に、ノードＦＧ２に接続されるデータ保持部へのデータ電圧の書き込み動作（以下、書き込み動作２とよぶ。）について説明する。なお、ノードＦＧ２に接続されるデータ保持部に書きこむデータ電圧をＶＤ２として説明する。 Next, a data voltage writing operation (hereinafter referred to as writing operation 2) to the data holding portion connected to the node FG2 will be described. Incidentally, illustrating a data voltage to be written to the data holding unit connected to the node FG2 as V D2.
　書き込み動作２では、配線４００１をＶＤ２とし、配線４００３を接地電位とした後に、電気的に浮遊状態とする。また配線４００７をハイレベルにする。また配線４００５、４００６、４００８、４００９をローレベルにする。トランジスタ４３００を導通状態として配線４００３をローレベルにする。そのため、ノードＦＧ２の電位もローレベルにまで低下し、トランジスタ４１００に電流が流れる。電流が流れることで、配線４００３の電位が上昇する。またトランジスタ４３００が導通状態となる。そのため、配線４００３の電位の上昇につれて、ノードＦＧ２の電位が上昇する。ノードＦＧ２の電位が上昇し、トランジスタ４１００でＶｇｓがトランジスタ４１００のＶｔｈになると、トランジスタ４１００を流れる電流が小さくなる。そのため、配線４００３、ＦＧ２の電位の上昇は止まり、ＶＤ２からＶｔｈだけ下がった「ＶＤ２−Ｖｔｈ」で一定となる。 In the write operation 2, after the wiring 4001 is set to V D2 and the wiring 4003 is set to the ground potential, the wiring 4001 is electrically floated. Further, the wiring 4007 is set to a high level. In addition, the wirings 4005, 4006, 4008, and 4009 are set to a low level. The transistor 4300 is turned on and the wiring 4003 is set to a low level. Therefore, the potential of the node FG2 also decreases to a low level, and a current flows through the transistor 4100. When the current flows, the potential of the wiring 4003 increases. In addition, the transistor 4300 is turned on. Therefore, the potential of the node FG2 increases as the potential of the wiring 4003 increases. When the potential of the node FG2 rises and Vgs becomes Vth of the transistor 4100 in the transistor 4100, the current flowing through the transistor 4100 decreases. Therefore, the increase in the potentials of the wirings 4003 and FG2 stops and becomes constant at “V D2 −Vth”, which is lower than V D2 by Vth.
　つまり、配線４００１に与えたＶＤ２は、トランジスタ４１００に電流が流れることで、配線４００３に与えられ、ノードＦＧ２の電位が上昇する。電位の上昇によって、ノードＦＧ２の電位が「ＶＤ２−Ｖｔｈ」となると、トランジスタ４１００のＶｇｓがＶｔｈとなるため、電流が止まる。このとき、ノードＦＧ１の電位は、トランジスタ４２００、４４００共に非導通状態であり、書き込み動作１で書きこんだ「ＶＤ１−Ｖｔｈ」が保持される。 That is, V D2 applied to the wiring 4001 is supplied to the wiring 4003 when a current flows through the transistor 4100, so that the potential of the node FG2 increases. When the potential of the node FG2 becomes “V D2 −Vth” due to the rise in potential, Vgs of the transistor 4100 becomes Vth, so that the current stops. At this time, the potential of the node FG1 is non-conductive in the transistors 4200 and 4400, and “V D1 −Vth” written in the writing operation 1 is held.
　図１８に示す半導体装置では、複数のデータ保持部にデータ電圧を書きこんだのち、配線４００９をハイレベルにして、ノードＦＧ１、ＦＧ２の電位を上昇させる。そして、各トランジスタを非導通状態として、電荷の移動をなくし、書きこんだデータ電圧を保持する。 In the semiconductor device shown in FIG. 18, after data voltages are written in a plurality of data holding portions, the wiring 4009 is set to a high level and the potentials of the nodes FG1 and FG2 are increased. Then, each transistor is brought into a non-conducting state to eliminate the movement of electric charges and to hold the written data voltage.
　以上説明したノードＦＧ１、ＦＧ２へのデータ電圧の書き込み動作によって、複数のデータ保持部にデータ電圧を保持させることができる。なお書きこまれる電位として、「ＶＤ１−Ｖｔｈ」や「ＶＤ２−Ｖｔｈ」を一例として挙げて説明したが、これらは多値のデータに対応するデータ電圧である。そのため、それぞれのデータ保持部で４ビットのデータを保持する場合、１６値の「ＶＤ１−Ｖｔｈ」や「ＶＤ２−Ｖｔｈ」を取り得る。 By the data voltage writing operation to the nodes FG1 and FG2 described above, the data voltages can be held in the plurality of data holding units. Note that although “V D1 −Vth” and “V D2 −Vth” have been described as examples of potentials to be written, these are data voltages corresponding to multi-value data. Therefore, when 4-bit data is held in each data holding unit, 16 values of “V D1 −Vth” and “V D2 −Vth” can be taken.
　次いで、図１８に示す半導体装置からの情報の読み出し動作について説明する。 Next, an operation of reading information from the semiconductor device shown in FIG. 18 will be described.
　最初に、ノードＦＧ２に接続されるデータ保持部へのデータ電圧の読み出し動作（以下、読み出し動作１とよぶ。）について説明する。 First, a data voltage read operation (hereinafter referred to as read operation 1) to the data holding unit connected to the node FG2 will be described.
　読み出し動作１では、プリチャージを行ってから電気的に浮遊状態とした、配線４００３を放電させる。配線４００５乃至４００８をローレベルにする。また、配線４００９をローレベルとして、電気的に浮遊状態にあるノードＦＧ２の電位を「ＶＤ２−Ｖｔｈ」とする。ノードＦＧ２の電位が下がることで、トランジスタ４１００に電流が流れる。電流が流れることで、電気的に浮遊状態の配線４００３の電位が低下する。配線４００３の電位の低下につれて、トランジスタ４１００のＶｇｓが小さくなる。トランジスタ４１００のＶｇｓがトランジスタ４１００のＶｔｈになると、トランジスタ４１００を流れる電流が小さくなる。すなわち、配線４００３の電位が、ノードＦＧ２の電位「ＶＤ２−Ｖｔｈ」からＶｔｈだけ大きい値である「ＶＤ２」となる。この配線４００３の電位は、ノードＦＧ２に接続されるデータ保持部のデータ電圧に対応する。読み出されたアナログ値のデータ電圧はＡ／Ｄ変換を行い、ノードＦＧ２に接続されるデータ保持部のデータを取得する。 In the reading operation 1, the wiring 4003 that has been electrically floated after precharging is discharged. The wirings 4005 to 4008 are set to a low level. Further, the wiring 4009 is set to a low level, and the potential of the node FG2 in an electrically floating state is set to “V D2 −Vth”. A current flows through the transistor 4100 when the potential of the node FG2 is decreased. When the current flows, the potential of the electrically floating wiring 4003 is decreased. As the potential of the wiring 4003 decreases, Vgs of the transistor 4100 decreases. When Vgs of the transistor 4100 becomes Vth of the transistor 4100, a current flowing through the transistor 4100 is reduced. That is, the potential of the wiring 4003 becomes “V D2 ” that is a value larger by Vth than the potential “V D2 −Vth” of the node FG2. The potential of the wiring 4003 corresponds to the data voltage of the data holding portion connected to the node FG2. The read data voltage of the analog value is subjected to A / D conversion, and data of a data holding unit connected to the node FG2 is acquired.
　つまり、プリチャージ後の配線４００３を浮遊状態とし、配線４００９の電位をハイレベルからローレベルに切り替えることで、トランジスタ４１００に電流が流れる。電流が流れることで、浮遊状態にあった配線４００３の電位は低下して「ＶＤ２」となる。トランジスタ４１００では、ノードＦＧ２の「ＶＤ２−Ｖｔｈ」との間のＶｇｓがＶｔｈとなるため、電流が止まる。そして、配線４００３には、書き込み動作２で書きこんだ「ＶＤ２」が読み出される。 In other words, a current flows through the transistor 4100 when the wiring 4003 after precharging is in a floating state and the potential of the wiring 4009 is switched from a high level to a low level. When the current flows, the potential of the wiring 4003 in the floating state is decreased to “V D2 ”. In the transistor 4100, Vgs between “V D2 −Vth” of the node FG2 becomes Vth, so that the current stops. Then, “V D2 ” written in the writing operation 2 is read out to the wiring 4003.
　ノードＦＧ２に接続されるデータ保持部のデータを取得したら、トランジスタ４３００を導通状態として、ノードＦＧ２の「ＶＤ２−Ｖｔｈ」を放電させる。 When data in the data holding portion connected to the node FG2 is acquired, the transistor 4300 is turned on to discharge “V D2 −Vth” of the node FG2.
　次に、ノードＦＧ１に保持される電荷をノードＦＧ２に分配し、ノードＦＧ１に接続されるデータ保持部のデータ電圧を、ノードＦＧ２に接続されるデータ保持部に移す。ここで、配線４００１、４００３をローレベルとする。配線４００６をハイレベルにする。また、配線４００５、配線４００７乃至４００９をローレベルにする。トランジスタ４２００が導通状態となることで、ノードＦＧ１の電荷が、ノードＦＧ２との間で分配される。 Next, the charge held in the node FG1 is distributed to the node FG2, and the data voltage of the data holding unit connected to the node FG1 is transferred to the data holding unit connected to the node FG2. Here, the wirings 4001 and 4003 are set to a low level. The wiring 4006 is set to a high level. In addition, the wiring 4005 and the wirings 4007 to 4009 are set to a low level. When the transistor 4200 is turned on, the charge of the node FG1 is distributed to and from the node FG2.
　ここで、電荷の分配後の電位は、書きこんだ電位「ＶＤ１−Ｖｔｈ」から低下する。そのため、容量素子４６００の容量値は、容量素子４５００の容量値よりも大きくしておくことが好ましい。あるいは、ノードＦＧ１に書きこむ電位「ＶＤ１−Ｖｔｈ」は、同じデータを表す電位「ＶＤ２−Ｖｔｈ」よりも大きくすることが好ましい。このように、容量値の比を変えること、予め書きこむ電位を大きくしておくことで、電荷の分配後の電位の低下を抑制することができる。電荷の分配による電位の変動については、後述する。 Here, the potential after the charge distribution is lowered from the written potential “V D1 −Vth”. Therefore, the capacitance value of the capacitor 4600 is preferably larger than the capacitance value of the capacitor 4500. Alternatively, the potential “V D1 −Vth” written to the node FG1 is preferably higher than the potential “V D2 −Vth” representing the same data. In this way, by changing the ratio of the capacitance values and increasing the potential to be written in advance, it is possible to suppress a decrease in potential after the charge is distributed. The fluctuation of the potential due to the charge distribution will be described later.
　次に、ノードＦＧ１に接続されるデータ保持部へのデータ電圧の読み出し動作（以下、読み出し動作２とよぶ。）について説明する。 Next, a data voltage read operation to the data holding unit connected to the node FG1 (hereinafter referred to as a read operation 2) will be described.
　読み出し動作２では、プリチャージを行ってから電気的に浮遊状態とした、配線４００３を放電させる。配線４００５乃至４００８をローレベルにする。また、配線４００９は、プリチャージ時にハイレベルとして、その後ローレベルとする。配線４００９をローレベルとすることで、電気的に浮遊状態にあるノードＦＧ２を電位「ＶＤ１−Ｖｔｈ」とする。ノードＦＧ２の電位が下がることで、トランジスタ４１００に電流が流れる。電流が流れることで、電気的に浮遊状態の配線４００３の電位が低下する。配線４００３の電位の低下につれて、トランジスタ４１００のＶｇｓが小さくなる。トランジスタ４１００のＶｇｓがトランジスタ４１００のＶｔｈになると、トランジスタ４１００を流れる電流が小さくなる。すなわち、配線４００３の電位が、ノードＦＧ２の電位「ＶＤ１−Ｖｔｈ」からＶｔｈだけ大きい値である「ＶＤ１」となる。この配線４００３の電位は、ノードＦＧ１に接続されるデータ保持部のデータ電圧に対応する。読み出されたアナログ値のデータ電圧はＡ／Ｄ変換を行い、ノードＦＧ１に接続されるデータ保持部のデータを取得する。以上が、ノードＦＧ１に接続されるデータ保持部へのデータ電圧の読み出し動作である。 In the reading operation 2, the wiring 4003 that has been electrically floated after precharging is discharged. The wirings 4005 to 4008 are set to a low level. Further, the wiring 4009 is set to a high level at the time of precharging and then set to a low level. By setting the wiring 4009 to a low level, the node FG2 in an electrically floating state is set to a potential “V D1 −Vth”. A current flows through the transistor 4100 when the potential of the node FG2 is decreased. When the current flows, the potential of the electrically floating wiring 4003 is decreased. As the potential of the wiring 4003 decreases, Vgs of the transistor 4100 decreases. When Vgs of the transistor 4100 becomes Vth of the transistor 4100, a current flowing through the transistor 4100 is reduced. That is, the potential of the wiring 4003 becomes “V D1 ” that is a value larger by Vth than the potential “V D1 −Vth” of the node FG2. The potential of the wiring 4003 corresponds to the data voltage of the data holding portion connected to the node FG1. The read data voltage of the analog value performs A / D conversion, and acquires data of the data holding unit connected to the node FG1. The above is the data voltage reading operation to the data holding portion connected to the node FG1.
　つまり、プリチャージ後の配線４００３を浮遊状態とし、配線４００９の電位をハイレベルからローレベルに切り替えることで、トランジスタ４１００に電流が流れる。電流が流れることで、浮遊状態にあった配線４００３の電位は低して「ＶＤ１」となる。トランジスタ４１００では、ノードＦＧ２の「ＶＤ１−Ｖｔｈ」との間のＶｇｓがＶｔｈとなるため、電流が止まる。そして、配線４００３には、書き込み動作１で書きこんだ「ＶＤ１」が読み出される。 In other words, a current flows through the transistor 4100 when the wiring 4003 after precharging is in a floating state and the potential of the wiring 4009 is switched from a high level to a low level. When the current flows, the potential of the wiring 4003 in the floating state is lowered to “V D1 ”. In the transistor 4100, the current stops because Vgs between the node FG2 and “V D1 −Vth” becomes Vth. Then, “V D1 ” written in the writing operation 1 is read out to the wiring 4003.
　以上説明したノードＦＧ１、ＦＧ２からのデータ電圧の読み出し動作によって、複数のデータ保持部からデータ電圧を読み出すことができる。例えば、ノードＦＧ１及びノードＦＧ２にそれぞれ４ビット（１６値）のデータを保持することで計８ビット（２５６値）のデータを保持することができる。また、図１８においては、第１の層４０２１乃至第３の層４０２３からなる構成としたが、さらに層を形成することによって、半導体装置の面積を増大させず記憶容量の増加を図ることができる。 The data voltage can be read from the plurality of data holding units by the data voltage reading operation from the nodes FG1 and FG2 described above. For example, a total of 8 bits (256 values) of data can be held by holding 4 bits (16 values) of data in each of the nodes FG1 and FG2. In FIG. 18, the first layer 4021 to the third layer 4023 are used. However, by forming additional layers, the storage capacity can be increased without increasing the area of the semiconductor device. .
　なお読み出される電位は、書きこんだデータ電圧よりＶｔｈだけ大きい電圧として読み出すことができる。そのため、書き込み動作で書きこんだ「ＶＤ１−Ｖｔｈ」や「ＶＤ２−Ｖｔｈ」のＶｔｈを相殺して読み出す構成とすることができる。その結果、メモリセルあたりの記憶容量を向上させるとともに、読み出されるデータを正しいデータに近づけることができるため、データの信頼性に優れたものとすることができる。 Note that the read potential can be read as a voltage higher than the written data voltage by Vth. Therefore, it is possible to adopt a configuration in which Vth of “V D1 −Vth” or “V D2 −Vth” written by the write operation is canceled and read. As a result, the storage capacity per memory cell can be improved and the read data can be brought close to the correct data, so that the data reliability can be improved.
＜記憶装置４＞
　図１７（Ｃ）に示す半導体装置は、トランジスタ３５００、第６の配線３００６を有する点で図１７（Ａ）に示した半導体装置と異なる。この場合も図１７（Ａ）に示した半導体装置と同様の動作により情報の書き込みおよび保持動作が可能である。また、トランジスタ３５００としては上記のトランジスタ３２００と同様のトランジスタを用いればよい。 <Storage device 4>
The semiconductor device illustrated in FIG. 17C is different from the semiconductor device illustrated in FIG. 17A in that the transistor 3500 and the sixth wiring 3006 are provided. In this case as well, information writing and holding operations can be performed by operations similar to those of the semiconductor device illustrated in FIG. The transistor 3500 may be a transistor similar to the transistor 3200 described above.
　第６の配線３００６は、トランジスタ３５００のゲートと電気的に接続され、トランジスタ３５００のソース、ドレインの一方はトランジスタ３２００のドレインと電気的に接続され、トランジスタ３５００のソース、ドレインの他方は第３の配線３００３と電気的に接続される。 The sixth wiring 3006 is electrically connected to the gate of the transistor 3500, one of the source and the drain of the transistor 3500 is electrically connected to the drain of the transistor 3200, and the other of the source and the drain of the transistor 3500 is the third It is electrically connected to the wiring 3003.
　本実施の形態に示す構成は、他の実施の形態に示す構成と適宜組み合わせて用いることができる。 The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.
（実施の形態４）
　本実施の形態では、上述の実施の形態で説明したＯＳトランジスタを適用可能な回路構成の一例について、図１９乃至図２２を用いて説明する。 (Embodiment 4)
In this embodiment, an example of a circuit configuration to which the OS transistor described in the above embodiments can be applied will be described with reference to FIGS.
　図１９（Ａ）にインバータの回路図を示す。インバータ８００は、入力端子ＩＮの論理を反転した信号を出力端子ＯＵＴに出力する。インバータ８００は、複数のＯＳトランジスタを有する。信号ＳＢＧは、ＯＳトランジスタの電気特性を切り替えることができる信号である。 FIG. 19A shows a circuit diagram of the inverter. The inverter 800 outputs a signal obtained by inverting the logic of the input terminal IN to the output terminal OUT. The inverter 800 includes a plurality of OS transistors. The signal SBG is a signal that can switch the electrical characteristics of the OS transistor.
　図１９（Ｂ）は、インバータ８００の一例となる回路図である。インバータ８００は、ＯＳトランジスタ８１０、およびＯＳトランジスタ８２０を有する。インバータ８００は、ｎチャネル型トランジスタで作製することができるため、ＣＭＯＳ（Ｃｏｍｐｌｅｍｅｎｔａｒｙ　Ｍｅｔａｌ　Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ）でインバータ（ＣＭＯＳインバータ）を作製する場合と比較して、低コストで作製することが可能である。 FIG. 19B is a circuit diagram as an example of the inverter 800. The inverter 800 includes an OS transistor 810 and an OS transistor 820. Since the inverter 800 can be manufactured using an n-channel transistor, the inverter 800 can be manufactured at a lower cost than a case where an inverter (CMOS inverter) is manufactured using a complementary metal oxide semiconductor (CMOS).
　なおＯＳトランジスタを有するインバータ８００は、Ｓｉトランジスタで構成されるＣＭＯＳ上に配置することもできる。インバータ８００は、ＣＭＯＳの回路構成に重ねて配置できるため、インバータ８００を追加する分の回路面積の増加を抑えることができる。 Note that the inverter 800 having an OS transistor can be arranged on a CMOS formed of Si transistors. Since the inverter 800 can be arranged so as to overlap the CMOS circuit configuration, an increase in circuit area corresponding to the addition of the inverter 800 can be suppressed.
　ＯＳトランジスタ８１０、８２０は、フロントゲートとして機能する第１ゲートと、バックゲートとして機能する第２ゲートと、ソースまたはドレインの一方として機能する第１端子、ソースまたはドレインの他方として機能する第２端子を有する。 The OS transistors 810 and 820 include a first gate that functions as a front gate, a second gate that functions as a back gate, a first terminal that functions as one of a source and a drain, and a second terminal that functions as the other of a source and a drain. Have
　ＯＳトランジスタ８１０の第１ゲートは、第２端子に接続される。ＯＳトランジスタ８１０の第２ゲートは、信号ＳＢＧを供給する配線に接続される。ＯＳトランジスタ８１０の第１端子は、電圧ＶＤＤを与える配線に接続される。ＯＳトランジスタ８１０の第２端子は、出力端子ＯＵＴに接続される。 The first gate of the OS transistor 810 is connected to the second terminal. A second gate of the OS transistor 810 is connected to a wiring for supplying the signal SBG . A first terminal of the OS transistor 810 is connected to a wiring that supplies the voltage VDD. The second terminal of the OS transistor 810 is connected to the output terminal OUT.
　ＯＳトランジスタ８２０の第１ゲートは、入力端子ＩＮに接続される。ＯＳトランジスタ８２０の第２ゲートは、入力端子ＩＮに接続される。ＯＳトランジスタ８２０の第１端子は、出力端子ＯＵＴに接続される。ＯＳトランジスタ８２０の第２端子は、電圧ＶＳＳを与える配線に接続される。 The first gate of the OS transistor 820 is connected to the input terminal IN. A second gate of the OS transistor 820 is connected to the input terminal IN. The first terminal of the OS transistor 820 is connected to the output terminal OUT. A second terminal of the OS transistor 820 is connected to a wiring that supplies the voltage VSS.
　図１９（Ｃ）は、インバータ８００の動作を説明するためのタイミングチャートである。図１９（Ｃ）のタイミングチャートでは、入力端子ＩＮの信号波形、出力端子ＯＵＴの信号波形、信号ＳＢＧの信号波形、およびＯＳトランジスタ８１０（ＦＥＴ８１０）の閾値電圧の変化について示している。 FIG. 19C is a timing chart for explaining the operation of the inverter 800. In the timing chart of FIG. 19 (C), it shows the signal waveform of the input terminal IN, the signal waveform of the output terminal OUT, and the change in the threshold voltage of the signal waveform of the signal S BG and OS transistor 810, (FET810).
　信号ＳＢＧはＯＳトランジスタ８１０の第２ゲートに与えることで、ＯＳトランジスタ８１０の閾値電圧を制御することができる。 By supplying the signal SBG to the second gate of the OS transistor 810, the threshold voltage of the OS transistor 810 can be controlled.
　信号ＳＢＧは、閾値電圧をマイナスシフトさせるための電圧ＶＢＧ＿Ａ、閾値電圧をプラスシフトさせるための電圧ＶＢＧ＿Ｂを有する。第２ゲートに電圧ＶＢＧ＿Ａを与えることで、ＯＳトランジスタ８１０は閾値電圧ＶＴＨ＿Ａにマイナスシフトさせることができる。また、第２ゲートに電圧ＶＢＧ＿Ｂを与えることで、ＯＳトランジスタ８１０は閾値電圧ＶＴＨ＿Ｂにプラスシフトさせることができる。 Signal S BG has a voltage V BG_B for voltage V BG_A for causing negative shift of the threshold voltage, the threshold voltage is positive shift. By applying the voltage V BG_A to the second gate, the OS transistor 810 can be negatively shifted to the threshold voltage V TH_A . Further, by applying the voltage V BG_B to the second gate, the OS transistor 810 can be positively shifted to the threshold voltage V TH_B .
　前述の説明を可視化するために、図２０（Ａ）には、トランジスタの電気特性の一つである、Ｖｇ−Ｉｄカーブを示す。 In order to visualize the above description, FIG. 20A shows a Vg-Id curve which is one of the electrical characteristics of the transistor.
　上述したＯＳトランジスタ８１０の電気特性は、第２ゲートの電圧を電圧ＶＢＧ＿Ａのように大きくすることで、図２０（Ａ）中の破線８４０で表される曲線にシフトさせることができる。また、上述したＯＳトランジスタ８１０の電気特性は、第２ゲートの電圧を電圧ＶＢＧ＿Ｂのように小さくすることで、図２０（Ａ）中の実線８４１で表される曲線にシフトさせることができる。図２０（Ａ）に示すように、ＯＳトランジスタ８１０は、信号ＳＢＧを電圧ＶＢＧ＿Ａあるいは電圧ＶＢＧ＿Ｂというように切り替えることで、閾値電圧をプラスシフトあるいはマイナスシフトさせることができる。 The above-described electrical characteristics of the OS transistor 810 can be shifted to a curve represented by a broken line 840 in FIG. 20A by increasing the voltage of the second gate as the voltage V BG_A . Further, the above-described electrical characteristics of the OS transistor 810 can be shifted to a curve represented by a solid line 841 in FIG. 20A by reducing the voltage of the second gate as the voltage V BG_B . As shown in FIG. 20 (A), OS transistor 810, by switching the signal S BG and so the voltage V BG_A or voltage V BG_B, can be shifted in the positive or negative shift of the threshold voltage.
　閾値電圧を閾値電圧ＶＴＨ＿Ｂにプラスシフトさせることで、ＯＳトランジスタ８１０は電流が流れにくい状態とすることができる。図２０（Ｂ）には、この状態を可視化して示す。図２０（Ｂ）に図示するように、ＯＳトランジスタ８１０に流れる電流ＩＢを極めて小さくすることができる。そのため、入力端子ＩＮに与える信号がハイレベルでＯＳトランジスタ８２０はオン状態（ＯＮ）のとき、出力端子ＯＵＴの電圧を急峻に下降させることができる。 By positively shifting the threshold voltage to the threshold voltage VTH_B , the OS transistor 810 can be in a state in which current does not easily flow. FIG. 20B visualizes this state. As shown in FIG. 20 (B), it can be extremely small current I B flowing through the OS transistor 810. Therefore, when the signal applied to the input terminal IN is at a high level and the OS transistor 820 is in an on state (ON), the voltage at the output terminal OUT can be sharply decreased.
　図２０（Ｂ）に図示したように、ＯＳトランジスタ８１０に流れる電流が流れにくい状態とすることができるため、図１９（Ｃ）に示すタイミングチャートにおける出力端子の信号波形８３１を急峻に変化させることができる。電圧ＶＤＤを与える配線と、電圧ＶＳＳを与える配線との間に流れる貫通電流を少なくすることができるため、低消費電力での動作を行うことができる。 As shown in FIG. 20B, since the current flowing through the OS transistor 810 can be made difficult to flow, the signal waveform 831 at the output terminal in the timing chart shown in FIG. Can do. Since the through current flowing between the wiring for applying the voltage VDD and the wiring for supplying the voltage VSS can be reduced, an operation with low power consumption can be performed.
　また、閾値電圧を閾値電圧ＶＴＨ＿Ａにマイナスシフトさせることで、ＯＳトランジスタ８１０は電流が流れやすい状態とすることができる。図２０（Ｃ）には、この状態を可視化して示す。図２０（Ｃ）に図示するように、このとき流れる電流ＩＡを少なくとも電流ＩＢよりも大きくすることができる。そのため、入力端子ＩＮに与える信号がローレベルでＯＳトランジスタ８２０はオフ状態（ＯＦＦ）のとき、出力端子ＯＵＴの電圧を急峻に上昇させることができる。 In addition, the OS transistor 810 can be in a state in which a current easily flows by shifting the threshold voltage to the threshold voltage V TH_A minus. In FIG. 20C, this state is visualized. As shown in FIG. 20 (C), it can be larger than at least the current I B of the current I A flowing at this time. Therefore, when the signal supplied to the input terminal IN is at a low level and the OS transistor 820 is in an off state (OFF), the voltage of the output terminal OUT can be rapidly increased.
　図２０（Ｃ）に図示したように、ＯＳトランジスタ８１０に流れる電流が流れやすい状態とすることができるため、図１９（Ｃ）に示すタイミングチャートにおける出力端子の信号波形８３２を急峻に変化させることができる。 As shown in FIG. 20C, since the current flowing through the OS transistor 810 can easily flow, the signal waveform 832 at the output terminal in the timing chart shown in FIG. Can do.
　なお、信号ＳＢＧによるＯＳトランジスタ８１０の閾値電圧の制御は、ＯＳトランジスタ８２０の状態が切り替わる以前、すなわち時刻Ｔ１やＴ２よりも前に行うことが好ましい。例えば、図１９（Ｃ）に図示するように、入力端子ＩＮに与える信号がハイレベルに切り替わる時刻Ｔ１よりも前に、閾値電圧ＶＴＨ＿Ａから閾値電圧ＶＴＨ＿ＢにＯＳトランジスタ８１０の閾値電圧を切り替えることが好ましい。また、図１９（Ｃ）に図示するように、入力端子ＩＮに与える信号がローレベルに切り替わる時刻Ｔ２よりも前に、閾値電圧ＶＴＨ＿Ｂから閾値電圧ＶＴＨ＿ＡにＯＳトランジスタ８１０の閾値電圧を切り替えることが好ましい。 The control of the threshold voltage of the OS transistor 810 by the signal S BG previously where the state of the OS transistor 820 is switched, i.e. it is preferably performed before time T1 and T2. For example, as illustrated in FIG. 19C , the threshold voltage of the OS transistor 810 is switched from the threshold voltage V TH_A to the threshold voltage V TH_B before the time T1 when the signal applied to the input terminal IN switches to the high level. Is preferred. In addition, as illustrated in FIG. 19C , the threshold voltage of the OS transistor 810 is switched from the threshold voltage V TH_B to the threshold voltage V TH_A before the time T2 when the signal applied to the input terminal IN is switched to the low level. Is preferred.
　なお図１９（Ｃ）のタイミングチャートでは、入力端子ＩＮに与える信号に応じて信号ＳＢＧを切り替える構成を示したが、別の構成としてもよい。たとえば閾値電圧を制御するための電圧は、フローティング状態としたＯＳトランジスタ８１０の第２ゲートに保持させる構成としてもよい。当該構成を実現可能な回路構成の一例について、図２１（Ａ）に示す。 Note that although the structure in which the signal SBG is switched in accordance with the signal applied to the input terminal IN is illustrated in the timing chart in FIG. 19C , another structure may be employed. For example, the voltage for controlling the threshold voltage may be held in the second gate of the OS transistor 810 in a floating state. FIG. 21A illustrates an example of a circuit configuration that can realize this configuration.
　図２１（Ａ）では、図１９（Ｂ）で示した回路構成に加えて、ＯＳトランジスタ８５０を有する。ＯＳトランジスタ８５０の第１端子は、ＯＳトランジスタ８１０の第２ゲートに接続される。またＯＳトランジスタ８５０の第２端子は、電圧ＶＢＧ＿Ｂ（あるいは電圧ＶＢＧ＿Ａ）を与える配線に接続される。ＯＳトランジスタ８５０の第１ゲートは、信号ＳＦを与える配線に接続される。ＯＳトランジスタ８５０の第２ゲートは、電圧ＶＢＧ＿Ｂ（あるいは電圧ＶＢＧ＿Ａ）を与える配線に接続される。 FIG. 21A includes an OS transistor 850 in addition to the circuit configuration illustrated in FIG. The first terminal of the OS transistor 850 is connected to the second gate of the OS transistor 810. The second terminal of the OS transistor 850 is connected to a wiring for applying the voltage V BG_B (or voltage V BG_A ). The first gate of the OS transistor 850 is connected to a wiring for providing signal S F. A second gate of the OS transistor 850 is connected to a wiring that supplies the voltage V BG_B (or the voltage V BG_A ).
　図２１（Ａ）の動作について、図２１（Ｂ）のタイミングチャートを用いて説明する。 The operation in FIG. 21A will be described with reference to the timing chart in FIG.
　ＯＳトランジスタ８１０の閾値電圧を制御するための電圧は、入力端子ＩＮに与える信号がハイレベルに切り替わる時刻Ｔ３よりも前に、ＯＳトランジスタ８１０の第２ゲートに与える構成とする。信号ＳＦをハイレベルとしてＯＳトランジスタ８５０をオン状態とし、ノードＮＢＧに閾値電圧を制御するための電圧ＶＢＧ＿Ｂを与える。 The voltage for controlling the threshold voltage of the OS transistor 810 is applied to the second gate of the OS transistor 810 before time T3 when the signal applied to the input terminal IN switches to the high level. The OS transistor 850 is turned on the signal S F to the high level, providing a voltage V BG_B for controlling a threshold voltage in the node N BG.
　ノードＮＢＧが電圧ＶＢＧ＿Ｂとなった後は、ＯＳトランジスタ８５０をオフ状態とする。ＯＳトランジスタ８５０は、オフ電流が極めて小さいため、オフ状態にし続けることで、一旦ノードＮＢＧに保持させた電圧ＶＢＧ＿Ｂを保持することができる。そのため、ＯＳトランジスタ８５０の第２ゲートに電圧ＶＢＧ＿Ｂを与える動作の回数が減るため、電圧ＶＢＧ＿Ｂの書き換えに要する分の消費電力を小さくすることができる。 After the node N BG becomes voltage V BG_B is turned off the OS transistor 850. Since the off-state current of the OS transistor 850 is extremely small, the voltage V BG_B once held at the node N BG can be held by continuing the off state. Therefore, the number of operations for applying the voltage V BG_B to the second gate of the OS transistor 850 is reduced, so that power consumption required for rewriting the voltage V BG_B can be reduced.
　なお図１９（Ｂ）および図２１（Ａ）の回路構成では、ＯＳトランジスタ８１０の第２ゲートに与える電圧を外部からの制御によって与える構成について示したが、別の構成としてもよい。たとえば閾値電圧を制御するための電圧を、入力端子ＩＮに与える信号を基に生成し、ＯＳトランジスタ８１０の第２ゲートに与える構成としてもよい。当該構成を実現可能な回路構成の一例について、図２２（Ａ）に示す。 Note that in the circuit configurations in FIGS. 19B and 21A, a configuration in which the voltage applied to the second gate of the OS transistor 810 is given by external control is shown, but another configuration may be used. For example, a voltage for controlling the threshold voltage may be generated based on a signal supplied to the input terminal IN and supplied to the second gate of the OS transistor 810. An example of a circuit configuration that can realize this configuration is illustrated in FIG.
　図２２（Ａ）では、図１９（Ｂ）で示した回路構成において、入力端子ＩＮとＯＳトランジスタ８１０の第２ゲートとの間にＣＭＯＳインバータ８６０を有する。ＣＭＯＳインバータ８６０の入力端子は、入力端子ＩＮに接続さえる。ＣＭＯＳインバータ８６０の出力端子は、ＯＳトランジスタ８１０の第２ゲートに接続される。 22A, a CMOS inverter 860 is provided between the input terminal IN and the second gate of the OS transistor 810 in the circuit configuration shown in FIG. 19B. The input terminal of the CMOS inverter 860 is connected to the input terminal IN. The output terminal of the CMOS inverter 860 is connected to the second gate of the OS transistor 810.
　図２２（Ａ）の動作について、図２２（Ｂ）のタイミングチャートを用いて説明する。図２２（Ｂ）のタイミングチャートでは、入力端子ＩＮの信号波形、出力端子ＯＵＴの信号波形、ＣＭＯＳインバータ８６０の出力波形ＩＮ＿Ｂ、およびＯＳトランジスタ８１０（ＦＥＴ８１０）の閾値電圧の変化について示している。 The operation in FIG. 22A will be described with reference to the timing chart in FIG. The timing chart in FIG. 22B shows changes in the signal waveform of the input terminal IN, the signal waveform of the output terminal OUT, the output waveform IN_B of the CMOS inverter 860, and the threshold voltage of the OS transistor 810 (FET 810).
　入力端子ＩＮに与える信号の論理を反転した信号である出力波形ＩＮ＿Ｂは、ＯＳトランジスタ８１０の閾値電圧を制御する信号とすることができる。したがって、図２０（Ａ）乃至（Ｃ）で説明したように、ＯＳトランジスタ８１０の閾値電圧を制御できる。例えば、図２２（Ｂ）における時刻Ｔ４となるとき、入力端子ＩＮに与える信号がハイレベルでＯＳトランジスタ８２０はオン状態となる。このとき、出力波形ＩＮ＿Ｂはローレベルとなる。そのため、ＯＳトランジスタ８１０は電流が流れにくい状態とすることができ、出力端子ＯＵＴの電圧を急峻に下降させることができる。 The output waveform IN_B, which is a signal obtained by inverting the logic of the signal applied to the input terminal IN, can be a signal for controlling the threshold voltage of the OS transistor 810. Therefore, as described with reference to FIGS. 20A to 20C, the threshold voltage of the OS transistor 810 can be controlled. For example, at time T4 in FIG. 22B, the signal applied to the input terminal IN is at a high level and the OS transistor 820 is turned on. At this time, the output waveform IN_B is at a low level. Therefore, the OS transistor 810 can be in a state in which current does not easily flow, and the voltage of the output terminal OUT can be sharply decreased.
　また図２２（Ｂ）における時刻Ｔ５となるとき、入力端子ＩＮに与える信号がローレベルでＯＳトランジスタ８２０はオフ状態となる。このとき、出力波形ＩＮ＿Ｂはハイレベルとなる。そのため、ＯＳトランジスタ８１０は電流が流れやすい状態とすることができ、出力端子ＯＵＴの電圧のを急峻に上昇させることができる。 Further, at time T5 in FIG. 22B, the signal applied to the input terminal IN is at a low level, so that the OS transistor 820 is turned off. At this time, the output waveform IN_B is at a high level. Therefore, the OS transistor 810 can be in a state in which current easily flows, and the voltage of the output terminal OUT can be rapidly increased.
　以上説明したように本実施の形態の構成では、ＯＳトランジスタを有するインバータにおける、バックゲートの電圧を入力端子ＩＮの信号の論理にしたがって切り替える。当該構成とすることで、ＯＳトランジスタの閾値電圧を制御することができる。ＯＳトランジスタの閾値電圧の制御を入力端子ＩＮに与える信号によって制御することで、出力端子ＯＵＴの電圧を急峻に変化させることができる。また、電源電圧を与える配線間の貫通電流を小さくすることができる。そのため、低消費電力化を図ることができる。 As described above, in the configuration of the present embodiment, the voltage of the back gate in the inverter having the OS transistor is switched in accordance with the signal logic of the input terminal IN. With this structure, the threshold voltage of the OS transistor can be controlled. By controlling the threshold voltage of the OS transistor with a signal applied to the input terminal IN, the voltage of the output terminal OUT can be changed abruptly. In addition, the through current between the wirings supplying the power supply voltage can be reduced. Therefore, low power consumption can be achieved.
（実施の形態５）
　本実施の形態においては、本発明の一態様に係るトランジスタや上述した記憶装置などの半導体装置を含むＣＰＵの一例について説明する。 (Embodiment 5)
In this embodiment, an example of a CPU including a transistor according to one embodiment of the present invention and a semiconductor device such as the memory device described above will be described.
＜ＣＰＵの構成＞
　図２３は、上述したトランジスタを一部に用いたＣＰＵの一例の構成を示すブロック図である。 <Configuration of CPU>
FIG. 23 is a block diagram illustrating a configuration example of a CPU that partially uses the above-described transistor.
　図２３に示すＣＰＵは、基板１１９０上に、ＡＬＵ１１９１（ＡＬＵ：Ａｒｉｔｈｍｅｔｉｃ　ｌｏｇｉｃ　ｕｎｉｔ、演算回路）、ＡＬＵコントローラ１１９２、インストラクションデコーダ１１９３、インタラプトコントローラ１１９４、タイミングコントローラ１１９５、レジスタ１１９６、レジスタコントローラ１１９７、バスインターフェース１１９８、書き換え可能なＲＯＭ１１９９、およびＲＯＭインターフェース１１８９を有している。基板１１９０は、半導体基板、ＳＯＩ基板、ガラス基板などを用いる。ＲＯＭ１１９９およびＲＯＭインターフェース１１８９は、別チップに設けてもよい。もちろん、図２３に示すＣＰＵは、その構成を簡略化して示した一例にすぎず、実際のＣＰＵはその用途によって多種多様な構成を有している。例えば、図２３に示すＣＰＵまたは演算回路を含む構成を一つのコアとし、当該コアを複数含み、それぞれのコアが並列で動作するような構成としてもよい。また、ＣＰＵが内部演算回路やデータバスで扱えるビット数は、例えば８ビット、１６ビット、３２ビット、６４ビットなどとすることができる。 23 includes an ALU 1191 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, and a bus interface 1198. A rewritable ROM 1199 and a ROM interface 1189. As the substrate 1190, a semiconductor substrate, an SOI substrate, a glass substrate, or the like is used. The ROM 1199 and the ROM interface 1189 may be provided in separate chips. Needless to say, the CPU illustrated in FIG. 23 is just an example in which the configuration is simplified, and an actual CPU may have various configurations depending on the application. For example, the configuration including the CPU or the arithmetic circuit illustrated in FIG. 23 may be a single core, and a plurality of the cores may be included, and each core may operate in parallel. Further, the number of bits that the CPU can handle with the internal arithmetic circuit or the data bus can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, or the like.
　バスインターフェース１１９８を介してＣＰＵに入力された命令は、インストラクションデコーダ１１９３に入力され、デコードされた後、ＡＬＵコントローラ１１９２、インタラプトコントローラ１１９４、レジスタコントローラ１１９７、タイミングコントローラ１１９５に入力される。 Instructions input to the CPU via the bus interface 1198 are input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195.
　ＡＬＵコントローラ１１９２、インタラプトコントローラ１１９４、レジスタコントローラ１１９７、タイミングコントローラ１１９５は、デコードされた命令に基づき、各種制御を行なう。具体的にＡＬＵコントローラ１１９２は、ＡＬＵ１１９１の動作を制御するための信号を生成する。また、インタラプトコントローラ１１９４は、ＣＰＵのプログラム実行中に、外部の入出力装置や、周辺回路からの割り込み要求を、その優先度やマスク状態から判断し、処理する。レジスタコントローラ１１９７は、レジスタ１１９６のアドレスを生成し、ＣＰＵの状態に応じてレジスタ１１９６の読み出しや書き込みを行なう。 The ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates a signal for controlling the operation of the ALU 1191. The interrupt controller 1194 determines and processes an interrupt request from an external input / output device or a peripheral circuit from the priority or mask state during execution of the CPU program. The register controller 1197 generates an address of the register 1196, and reads and writes the register 1196 according to the state of the CPU.
　また、タイミングコントローラ１１９５は、ＡＬＵ１１９１、ＡＬＵコントローラ１１９２、インストラクションデコーダ１１９３、インタラプトコントローラ１１９４、およびレジスタコントローラ１１９７の動作のタイミングを制御する信号を生成する。例えばタイミングコントローラ１１９５は、基準クロック信号ＣＬＫ１を元に、内部クロック信号ＣＬＫ２を生成する内部クロック生成部を備えており、内部クロック信号ＣＬＫ２を上記各種回路に供給する。 Also, the timing controller 1195 generates a signal for controlling the operation timing of the ALU 1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal CLK2 based on the reference clock signal CLK1, and supplies the internal clock signal CLK2 to the various circuits.
　図２３に示すＣＰＵでは、レジスタ１１９６に、メモリセルが設けられている。レジスタ１１９６のメモリセルとして、上述したトランジスタや記憶装置などを用いることができる。 In the CPU shown in FIG. 23, the register 1196 is provided with a memory cell. As the memory cell of the register 1196, the above-described transistor, memory device, or the like can be used.
　図２３に示すＣＰＵにおいて、レジスタコントローラ１１９７は、ＡＬＵ１１９１からの指示に従い、レジスタ１１９６における保持動作の選択を行う。即ち、レジスタ１１９６が有するメモリセルにおいて、フリップフロップによるデータの保持を行うか、容量素子によるデータの保持を行うかを、選択する。フリップフロップによるデータの保持が選択されている場合、レジスタ１１９６内のメモリセルへの、電源電圧の供給が行われる。容量素子におけるデータの保持が選択されている場合、容量素子へのデータの書き換えが行われ、レジスタ１１９６内のメモリセルへの電源電圧の供給を停止することができる。 In the CPU shown in FIG. 23, the register controller 1197 selects a holding operation in the register 1196 in accordance with an instruction from the ALU 1191. That is, whether to hold data by a flip-flop or to hold data by a capacitor in a memory cell included in the register 1196 is selected. When data retention by the flip-flop is selected, the power supply voltage is supplied to the memory cell in the register 1196. When holding of data in the capacitor is selected, data is rewritten to the capacitor and supply of power supply voltage to the memory cells in the register 1196 can be stopped.
　図２４は、レジスタ１１９６として用いることのできる記憶素子１２００の回路図の一例である。記憶素子１２００は、電源遮断で記憶データが揮発する回路１２０１と、電源遮断で記憶データが揮発しない回路１２０２と、スイッチ１２０３と、スイッチ１２０４と、論理素子１２０６と、容量素子１２０７と、選択機能を有する回路１２２０と、を有する。回路１２０２は、容量素子１２０８と、トランジスタ１２０９と、トランジスタ１２１０と、を有する。なお、記憶素子１２００は、必要に応じて、ダイオード、抵抗素子、インダクタなどのその他の素子をさらに有していてもよい。 FIG. 24 is an example of a circuit diagram of a memory element 1200 that can be used as the register 1196. The memory element 1200 includes a circuit 1201 in which stored data is volatilized by power-off, a circuit 1202 in which stored data is not volatilized by power-off, a switch 1203, a switch 1204, a logic element 1206, a capacitor 1207, and a selection function. Circuit 1220 having. The circuit 1202 includes a capacitor 1208, a transistor 1209, and a transistor 1210. Note that the memory element 1200 may further include other elements such as a diode, a resistance element, and an inductor, as necessary.
　ここで、回路１２０２には、上述した記憶装置を用いることができる。記憶素子１２００への電源電圧の供給が停止した際、回路１２０２のトランジスタ１２０９のゲートにはＧＮＤ（０Ｖ）、またはトランジスタ１２０９がオフする電位が入力され続ける構成とする。例えば、トランジスタ１２０９のゲートが抵抗等の負荷を介して接地される構成とする。 Here, the memory device described above can be used for the circuit 1202. When supply of power supply voltage to the memory element 1200 is stopped, GND (0 V) or a potential at which the transistor 1209 is turned off is continuously input to the gate of the transistor 1209 of the circuit 1202. For example, the gate of the transistor 1209 is grounded through a load such as a resistor.
　スイッチ１２０３は、一導電型（例えば、ｎチャネル型）のトランジスタ１２１３を用いて構成され、スイッチ１２０４は、一導電型とは逆の導電型（例えば、ｐチャネル型）のトランジスタ１２１４を用いて構成した例を示す。ここで、スイッチ１２０３の第１の端子はトランジスタ１２１３のソースとドレインの一方に対応し、スイッチ１２０３の第２の端子はトランジスタ１２１３のソースとドレインの他方に対応し、スイッチ１２０３はトランジスタ１２１３のゲートに入力される制御信号ＲＤによって、第１の端子と第２の端子の間の導通または非導通（つまり、トランジスタ１２１３の導通状態または非導通状態）が選択される。スイッチ１２０４の第１の端子はトランジスタ１２１４のソースとドレインの一方に対応し、スイッチ１２０４の第２の端子はトランジスタ１２１４のソースとドレインの他方に対応し、スイッチ１２０４はトランジスタ１２１４のゲートに入力される制御信号ＲＤによって、第１の端子と第２の端子の間の導通または非導通（つまり、トランジスタ１２１４の導通状態または非導通状態）が選択される。 The switch 1203 is configured using a transistor 1213 of one conductivity type (eg, n-channel type), and the switch 1204 is configured using a transistor 1214 of conductivity type (eg, p-channel type) opposite to the one conductivity type. An example is shown. Here, the first terminal of the switch 1203 corresponds to one of the source and the drain of the transistor 1213, the second terminal of the switch 1203 corresponds to the other of the source and the drain of the transistor 1213, and the switch 1203 corresponds to the gate of the transistor 1213. In accordance with the control signal RD input to the second terminal, conduction or non-conduction between the first terminal and the second terminal (that is, the conduction state or non-conduction state of the transistor 1213) is selected. The first terminal of the switch 1204 corresponds to one of the source and the drain of the transistor 1214, the second terminal of the switch 1204 corresponds to the other of the source and the drain of the transistor 1214, and the switch 1204 is input to the gate of the transistor 1214. The control signal RD selects the conduction or non-conduction between the first terminal and the second terminal (that is, the conduction state or non-conduction state of the transistor 1214).
　トランジスタ１２０９のソースとドレインの一方は、容量素子１２０８の一対の電極のうちの一方、およびトランジスタ１２１０のゲートと電気的に接続される。ここで、接続部分をノードＭ２とする。トランジスタ１２１０のソースとドレインの一方は、低電源電位を供給することのできる配線（例えばＧＮＤ線）に電気的に接続され、他方は、スイッチ１２０３の第１の端子（トランジスタ１２１３のソースとドレインの一方）と電気的に接続される。スイッチ１２０３の第２の端子（トランジスタ１２１３のソースとドレインの他方）はスイッチ１２０４の第１の端子（トランジスタ１２１４のソースとドレインの一方）と電気的に接続される。スイッチ１２０４の第２の端子（トランジスタ１２１４のソースとドレインの他方）は電源電位ＶＤＤを供給することのできる配線と電気的に接続される。スイッチ１２０３の第２の端子（トランジスタ１２１３のソースとドレインの他方）と、スイッチ１２０４の第１の端子（トランジスタ１２１４のソースとドレインの一方）と、論理素子１２０６の入力端子と、容量素子１２０７の一対の電極のうちの一方と、は電気的に接続される。ここで、接続部分をノードＭ１とする。容量素子１２０７の一対の電極のうちの他方は、一定の電位が入力される構成とすることができる。例えば、低電源電位（ＧＮＤ等）または高電源電位（ＶＤＤ等）が入力される構成とすることができる。容量素子１２０７の一対の電極のうちの他方は、低電源電位を供給することのできる配線（例えばＧＮＤ線）と電気的に接続される。容量素子１２０８の一対の電極のうちの他方は、一定の電位が入力される構成とすることができる。例えば、低電源電位（ＧＮＤ等）または高電源電位（ＶＤＤ等）が入力される構成とすることができる。容量素子１２０８の一対の電極のうちの他方は、低電源電位を供給することのできる配線（例えばＧＮＤ線）と電気的に接続される。 One of the source and the drain of the transistor 1209 is electrically connected to one of the pair of electrodes of the capacitor 1208 and the gate of the transistor 1210. Here, the connection part is referred to as a node M2. One of a source and a drain of the transistor 1210 is electrically connected to a wiring that can supply a low power supply potential (eg, a GND line), and the other is connected to the first terminal of the switch 1203 (the source and the drain of the transistor 1213 On the other hand). A second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is electrically connected to a first terminal of the switch 1204 (one of the source and the drain of the transistor 1214). A second terminal of the switch 1204 (the other of the source and the drain of the transistor 1214) is electrically connected to a wiring that can supply the power supply potential VDD. A second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213), a first terminal of the switch 1204 (one of a source and a drain of the transistor 1214), an input terminal of the logic element 1206, and the capacitor 1207 One of the pair of electrodes is electrically connected. Here, the connection part is referred to as a node M1. The other of the pair of electrodes of the capacitor 1207 can be configured to receive a constant potential. For example, a low power supply potential (such as GND) or a high power supply potential (such as VDD) can be input. The other of the pair of electrodes of the capacitor 1207 is electrically connected to a wiring (eg, a GND line) that can supply a low power supply potential. The other of the pair of electrodes of the capacitor 1208 can have a constant potential. For example, a low power supply potential (such as GND) or a high power supply potential (such as VDD) can be input. The other of the pair of electrodes of the capacitor 1208 is electrically connected to a wiring (eg, a GND line) that can supply a low power supply potential.
　なお、容量素子１２０７および容量素子１２０８は、トランジスタや配線の寄生容量等を積極的に利用することによって省略することも可能である。 Note that the capacitor 1207 and the capacitor 1208 can be omitted by actively using parasitic capacitances of transistors and wirings.
　トランジスタ１２０９のゲートには、制御信号ＷＥが入力される。スイッチ１２０３およびスイッチ１２０４は、制御信号ＷＥとは異なる制御信号ＲＤによって第１の端子と第２の端子の間の導通状態または非導通状態を選択され、一方のスイッチの第１の端子と第２の端子の間が導通状態のとき他方のスイッチの第１の端子と第２の端子の間は非導通状態となる。 The control signal WE is input to the gate of the transistor 1209. The switch 1203 and the switch 1204 are selected to be in a conductive state or a non-conductive state between the first terminal and the second terminal by a control signal RD different from the control signal WE. When the terminals of the other switch are in a conductive state, the first terminal and the second terminal of the other switch are in a non-conductive state.
　トランジスタ１２０９のソースとドレインの他方には、回路１２０１に保持されたデータに対応する信号が入力される。図２４では、回路１２０１から出力された信号が、トランジスタ１２０９のソースとドレインの他方に入力される例を示した。スイッチ１２０３の第２の端子（トランジスタ１２１３のソースとドレインの他方）から出力される信号は、論理素子１２０６によってその論理値が反転された反転信号となり、回路１２２０を介して回路１２０１に入力される。 A signal corresponding to data held in the circuit 1201 is input to the other of the source and the drain of the transistor 1209. FIG. 24 illustrates an example in which the signal output from the circuit 1201 is input to the other of the source and the drain of the transistor 1209. A signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is an inverted signal obtained by inverting the logic value by the logic element 1206 and is input to the circuit 1201 through the circuit 1220. .
　なお、図２４では、スイッチ１２０３の第２の端子（トランジスタ１２１３のソースとドレインの他方）から出力される信号は、論理素子１２０６および回路１２２０を介して回路１２０１に入力する例を示したがこれに限定されない。スイッチ１２０３の第２の端子（トランジスタ１２１３のソースとドレインの他方）から出力される信号が、論理値を反転させられることなく、回路１２０１に入力されてもよい。例えば、回路１２０１内に、入力端子から入力された信号の論理値が反転した信号が保持されるノードが存在する場合に、スイッチ１２０３の第２の端子（トランジスタ１２１３のソースとドレインの他方）から出力される信号を当該ノードに入力することができる。 Note that FIG. 24 illustrates an example in which a signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is input to the circuit 1201 through the logic element 1206 and the circuit 1220. It is not limited to. A signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) may be input to the circuit 1201 without inversion of the logical value. For example, when there is a node in the circuit 1201 that holds a signal in which the logical value of the signal input from the input terminal is inverted, the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) An output signal can be input to the node.
　また、図２４において、記憶素子１２００に用いられるトランジスタのうち、トランジスタ１２０９以外のトランジスタは、酸化物半導体以外の半導体でなる膜または基板１１９０にチャネルが形成されるトランジスタとすることができる。例えば、シリコン膜またはシリコン基板にチャネルが形成されるトランジスタとすることができる。また、記憶素子１２００に用いられるトランジスタ全てを、チャネルが酸化物半導体で形成されるトランジスタとすることもできる。または、記憶素子１２００は、トランジスタ１２０９以外にも、チャネルが酸化物半導体で形成されるトランジスタを含んでいてもよく、残りのトランジスタは酸化物半導体以外の半導体でなる層または基板１１９０にチャネルが形成されるトランジスタとすることもできる。 24, a transistor other than the transistor 1209 among the transistors used in the memory element 1200 can be a film formed of a semiconductor other than an oxide semiconductor or a channel in the substrate 1190. For example, a transistor in which a channel is formed in a silicon film or a silicon substrate can be used. Further, all the transistors used for the memory element 1200 can be transistors whose channels are formed using an oxide semiconductor. Alternatively, the memory element 1200 may include a transistor whose channel is formed using an oxide semiconductor in addition to the transistor 1209, and the remaining transistors are formed using a semiconductor layer other than the oxide semiconductor or the substrate 1190. It can also be a transistor.
　図２４における回路１２０１には、例えばフリップフロップ回路を用いることができる。また、論理素子１２０６としては、例えばインバータやクロックドインバータ等を用いることができる。 For example, a flip-flop circuit can be used for the circuit 1201 in FIG. As the logic element 1206, for example, an inverter, a clocked inverter, or the like can be used.
　本発明の一態様に係る半導体装置では、記憶素子１２００に電源電圧が供給されない間は、回路１２０１に記憶されていたデータを、回路１２０２に設けられた容量素子１２０８によって保持することができる。 In the semiconductor device according to one embodiment of the present invention, data stored in the circuit 1201 can be held by the capacitor 1208 provided in the circuit 1202 while the power supply voltage is not supplied to the memory element 1200.
　また、酸化物半導体にチャネルが形成されるトランジスタはオフ電流が極めて小さい。例えば、酸化物半導体にチャネルが形成されるトランジスタのオフ電流は、結晶性を有するシリコンにチャネルが形成されるトランジスタのオフ電流に比べて著しく低い。そのため、当該トランジスタをトランジスタ１２０９として用いることによって、記憶素子１２００に電源電圧が供給されない間も容量素子１２０８に保持された信号は長期間にわたり保たれる。こうして、記憶素子１２００は電源電圧の供給が停止した間も記憶内容（データ）を保持することが可能である。 In addition, a transistor in which a channel is formed in an oxide semiconductor has extremely low off-state current. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor is significantly lower than the off-state current of a transistor in which a channel is formed in crystalline silicon. Therefore, by using the transistor as the transistor 1209, the signal held in the capacitor 1208 is maintained for a long time even when the power supply voltage is not supplied to the memory element 1200. In this manner, the memory element 1200 can hold stored data (data) even while the supply of power supply voltage is stopped.
　また、スイッチ１２０３およびスイッチ１２０４を設けることによって、プリチャージ動作を行うことを特徴とする記憶素子であるため、電源電圧供給再開後に、回路１２０１が元のデータを保持しなおすまでの時間を短くすることができる。 Further, by providing the switch 1203 and the switch 1204, the memory element is characterized by performing a precharge operation; therefore, after the supply of power supply voltage is resumed, the time until the circuit 1201 retains the original data again is shortened. be able to.
　また、回路１２０２において、容量素子１２０８によって保持された信号はトランジスタ１２１０のゲートに入力される。そのため、記憶素子１２００への電源電圧の供給が再開された後、容量素子１２０８によって保持された信号を、トランジスタ１２１０の状態（導通状態、または非導通状態）に変換して、回路１２０２から読み出すことができる。それ故、容量素子１２０８に保持された信号に対応する電位が多少変動していても、元の信号を正確に読み出すことが可能である。 In the circuit 1202, the signal held by the capacitor 1208 is input to the gate of the transistor 1210. Therefore, after the supply of the power supply voltage to the memory element 1200 is restarted, the signal held by the capacitor 1208 is converted into the state of the transistor 1210 (a conductive state or a non-conductive state) and read from the circuit 1202 Can do. Therefore, the original signal can be accurately read even if the potential corresponding to the signal held in the capacitor 1208 slightly fluctuates.
　このような記憶素子１２００を、プロセッサが有するレジスタやキャッシュメモリなどの記憶装置に用いることで、電源電圧の供給停止による記憶装置内のデータの消失を防ぐことができる。また、電源電圧の供給を再開した後、短時間で電源供給停止前の状態に復帰することができる。よって、プロセッサ全体、もしくはプロセッサを構成する一つ、または複数の論理回路において、短い時間でも電源停止を行うことができるため、消費電力を抑えることができる。 By using such a storage element 1200 for a storage device such as a register or a cache memory included in the processor, it is possible to prevent data in the storage device from being lost due to the supply of power supply voltage being stopped. In addition, after the supply of the power supply voltage is resumed, the state before the power supply stop can be restored in a short time. Accordingly, power can be stopped in a short time in the entire processor or in one or a plurality of logic circuits constituting the processor, so that power consumption can be suppressed.
　記憶素子１２００をＣＰＵに用いる例として説明したが、記憶素子１２００は、ＤＳＰ（Ｄｉｇｉｔａｌ　Ｓｉｇｎａｌ　Ｐｒｏｃｅｓｓｏｒ）、カスタムＬＳＩ、ＰＬＤ（Ｐｒｏｇｒａｍｍａｂｌｅ　Ｌｏｇｉｃ　Ｄｅｖｉｃｅ）等のＬＳＩ、ＲＦ（Ｒａｄｉｏ　Ｆｒｅｑｕｅｎｃｙ）デバイスにも応用可能である。 Although the memory element 1200 has been described as an example of use for a CPU, the memory element 1200 can be applied to an LSI such as a DSP (Digital Signal Processor), a custom LSI, a PLD (Programmable Logic Device), and an RF (Radio Frequency) device. .
　本実施の形態に示す構成は、他の実施の形態に示す構成と適宜組み合わせて用いることができる。 The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.
（実施の形態６）
　本実施の形態においては、本発明の一態様に係るトランジスタなどを利用した電子機器について説明する。 (Embodiment 6)
In this embodiment, electronic devices using a transistor or the like according to one embodiment of the present invention will be described.
＜電子機器＞
　本発明の一態様に係る半導体装置は、表示機器、パーソナルコンピュータ、記録媒体を備えた画像再生装置（代表的にはＤＶＤ：Ｄｉｇｉｔａｌ　Ｖｅｒｓａｔｉｌｅ　Ｄｉｓｃ等の記録媒体を再生し、その画像を表示しうるディスプレイを有する装置）に用いることができる。その他に、本発明の一態様に係る半導体装置を用いることができる電子機器として、携帯電話、携帯型を含むゲーム機、携帯データ端末、電子書籍端末、ビデオカメラ、デジタルスチルカメラ等のカメラ、ゴーグル型ディスプレイ（ヘッドマウントディスプレイ）、ナビゲーションシステム、音響再生装置（カーオーディオ、デジタルオーディオプレイヤー等）、複写機、ファクシミリ、プリンタ、プリンタ複合機、現金自動預け入れ払い機（ＡＴＭ）、自動販売機などが挙げられる。これら電子機器の具体例を図２５に示す。 <Electronic equipment>
A semiconductor device according to one embodiment of the present invention includes a display device, a personal computer, and an image reproducing device including a recording medium (typically a display that can reproduce a recording medium such as a DVD: Digital Versatile Disc and display the image) Device). In addition, as an electronic device in which the semiconductor device according to one embodiment of the present invention can be used, a mobile phone, a game machine including a portable type, a portable data terminal, an electronic book terminal, a video camera, a digital still camera, or the like, goggles Type displays (head-mounted displays), navigation systems, sound playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, multifunction printers, automated teller machines (ATMs), vending machines, etc. It is done. Specific examples of these electronic devices are shown in FIGS.
　図２５（Ａ）は携帯型ゲーム機であり、筐体９０１、筐体９０２、表示部９０３、表示部９０４、マイクロフォン９０５、スピーカー９０６、操作キー９０７、スタイラス９０８等を有する。なお、図２５（Ａ）に示した携帯型ゲーム機は、２つの表示部９０３と表示部９０４とを有しているが、携帯型ゲーム機が有する表示部の数は、これに限定されない。 FIG. 25A shows a portable game machine, which includes a housing 901, a housing 902, a display portion 903, a display portion 904, a microphone 905, a speaker 906, operation keys 907, a stylus 908, and the like. Note that the portable game machine illustrated in FIG. 25A includes two display portions 903 and 904; however, the number of display portions included in the portable game device is not limited thereto.
　図２５（Ｂ）は携帯データ端末であり、第１筐体９１１、第２筐体９１２、第１表示部９１３、第２表示部９１４、接続部９１５、操作キー９１６等を有する。第１表示部９１３は第１筐体９１１に設けられており、第２表示部９１４は第２筐体９１２に設けられている。そして、第１筐体９１１と第２筐体９１２とは、接続部９１５により接続されており、第１筐体９１１と第２筐体９１２の間の角度は、接続部９１５により変更が可能である。第１表示部９１３における映像を、接続部９１５における第１筐体９１１と第２筐体９１２との間の角度にしたがって、切り替える構成としてもよい。また、第１表示部９１３および第２表示部９１４の少なくとも一方に、位置入力装置としての機能が付加された表示装置を用いるようにしてもよい。なお、位置入力装置としての機能は、表示装置にタッチパネルを設けることで付加することができる。または、位置入力装置としての機能は、フォトセンサとも呼ばれる光電変換素子を表示装置の画素部に設けることでも、付加することができる。 FIG. 25B shows a portable data terminal, which includes a first housing 911, a second housing 912, a first display portion 913, a second display portion 914, a connection portion 915, operation keys 916, and the like. The first display unit 913 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by the connection portion 915, and the angle between the first housing 911 and the second housing 912 can be changed by the connection portion 915. is there. It is good also as a structure which switches the image | video in the 1st display part 913 according to the angle between the 1st housing | casing 911 and the 2nd housing | casing 912 in the connection part 915. FIG. In addition, a display device in which a function as a position input device is added to at least one of the first display portion 913 and the second display portion 914 may be used. Note that the function as a position input device can be added by providing a touch panel on the display device. Alternatively, the function as a position input device can be added by providing a photoelectric conversion element called a photosensor in a pixel portion of a display device.
　図２５（Ｃ）はノート型パーソナルコンピュータであり、筐体９２１、表示部９２２、キーボード９２３、ポインティングデバイス９２４等を有する。 FIG. 25C illustrates a laptop personal computer, which includes a housing 921, a display portion 922, a keyboard 923, a pointing device 924, and the like.
　図２５（Ｄ）は電気冷凍冷蔵庫であり、筐体９３１、冷蔵室用扉９３２、冷凍室用扉９３３等を有する。 FIG. 25D illustrates an electric refrigerator-freezer, which includes a housing 931, a refrigerator door 932, a refrigerator door 933, and the like.
　図２５（Ｅ）はビデオカメラであり、第１筐体９４１、第２筐体９４２、表示部９４３、操作キー９４４、レンズ９４５、接続部９４６等を有する。操作キー９４４およびレンズ９４５は第１筐体９４１に設けられており、表示部９４３は第２筐体９４２に設けられている。そして、第１筐体９４１と第２筐体９４２とは、接続部９４６により接続されており、第１筐体９４１と第２筐体９４２の間の角度は、接続部９４６により変更が可能である。表示部９４３における映像を、接続部９４６における第１筐体９４１と第２筐体９４２との間の角度にしたがって切り替える構成としてもよい。 FIG. 25E illustrates a video camera, which includes a first housing 941, a second housing 942, a display portion 943, operation keys 944, a lens 945, a connection portion 946, and the like. The operation key 944 and the lens 945 are provided in the first housing 941, and the display portion 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connection portion 946, and the angle between the first housing 941 and the second housing 942 can be changed by the connection portion 946. is there. It is good also as a structure which switches the image | video in the display part 943 according to the angle between the 1st housing | casing 941 and the 2nd housing | casing 942 in the connection part 946. FIG.
　図２５（Ｆ）は自動車であり、車体９５１、車輪９５２、ダッシュボード９５３、ライト９５４等を有する。 FIG. 25F illustrates an automobile, which includes a vehicle body 951, wheels 952, a dashboard 953, lights 954, and the like.
　なお、本実施の形態において、本発明の一態様について述べた。ただし、本発明の一態様は、これらに限定されない。つまり、本実施の形態などでは、様々な発明の態様が記載されているため、本発明の一態様は、特定の態様に限定されない。例えば、本発明の一態様として、トランジスタのチャネル形成領域、ソースドレイン領域などが、酸化物半導体を有する場合の例を示したが、本発明の一態様は、これに限定されない。場合によっては、または、状況に応じて、本発明の一態様における様々なトランジスタ、トランジスタのチャネル形成領域、または、トランジスタのソースドレイン領域などは、様々な半導体を有していてもよい。場合によっては、または、状況に応じて、本発明の一態様における様々なトランジスタ、トランジスタのチャネル形成領域、または、トランジスタのソースドレイン領域などは、例えば、シリコン、ゲルマニウム、シリコンゲルマニウム、炭化シリコン、ガリウムヒ素、アルミニウムガリウムヒ素、インジウムリン、窒化ガリウム、または、有機半導体などの少なくとも一つを有していてもよい。または例えば、場合によっては、または、状況に応じて、本発明の一態様における様々なトランジスタ、トランジスタのチャネル形成領域、または、トランジスタのソースドレイン領域などは、酸化物半導体を有していなくてもよい。 Note that one embodiment of the present invention has been described in this embodiment. Note that one embodiment of the present invention is not limited thereto. In other words, in the present embodiment and the like, various aspects of the invention are described, and thus one embodiment of the present invention is not limited to a particular embodiment. For example, although an example in which a channel formation region, a source / drain region, and the like of a transistor include an oxide semiconductor is described as one embodiment of the present invention, one embodiment of the present invention is not limited thereto. In some cases or depending on circumstances, various transistors in one embodiment of the present invention, a channel formation region of the transistor, a source / drain region of the transistor, or the like may include various semiconductors. Depending on circumstances or circumstances, various transistors in one embodiment of the present invention, a channel formation region of the transistor, a source / drain region of the transistor, and the like can be formed using, for example, silicon, germanium, silicon germanium, silicon carbide, or gallium. At least one of arsenic, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor may be included. Alternatively, for example, depending on circumstances or circumstances, a variety of transistors, channel formation regions of the transistors, source and drain regions of the transistors, and the like of the transistor may not include an oxide semiconductor. Good.
　本実施例では、本発明の一態様に係るトランジスタについてデバイスシミュレーションを行い、トランジスタの電気特性の確認を行った。 In this example, device simulation was performed on the transistor according to one embodiment of the present invention, and the electrical characteristics of the transistor were confirmed.
　本実施例では、上記実施の形態で示した、トランジスタ１０に対応させてモデル１１を作成し、モデル１１に対してデバイスシミュレーションを行う。図２６（Ａ）（Ｂ）にモデル１１の断面図を示す。図２６（Ａ）は上記実施の形態に示す図１（Ｂ）に対応しており、モデル１１のチャネル長方向の断面図である。また、図２６（Ｂ）は上記実施の形態に示す図１（Ｃ）に対応しており、モデル１１のチャネル長方向に垂直な断面図である。 In this example, a model 11 is created corresponding to the transistor 10 shown in the above embodiment, and a device simulation is performed on the model 11. 26A and 26B are cross-sectional views of the model 11. FIG. FIG. 26A corresponds to FIG. 1B described in the above embodiment and is a cross-sectional view of the model 11 in the channel length direction. FIG. 26B corresponds to FIG. 1C described in the above embodiment, and is a cross-sectional view perpendicular to the channel length direction of the model 11.
　ただし、トランジスタ１０とは異なり、図２６（Ａ）に示すように、半導体１０６ｂのチャネル長方向の両端に低抵抗領域１０６ｃ及び低抵抗領域１０６ｄが設けられており、さらに低抵抗領域１０６ｃの外側に導電体１０８ａが設けられ、低抵抗領域１０６ｄの外側に導電体１０８ｂが設けられている。また、絶縁体１１２は、図２６（Ｂ）に示すように、導電体１１４の内側及び外側に連続して設けられており、導電体１１４の内側に設けられた部分は導電体１１４及び導電体１０２に対するゲート絶縁膜として機能する。 However, unlike the transistor 10, as illustrated in FIG. 26A, a low resistance region 106c and a low resistance region 106d are provided at both ends of the semiconductor 106b in the channel length direction, and further outside the low resistance region 106c. A conductor 108a is provided, and a conductor 108b is provided outside the low resistance region 106d. As shown in FIG. 26B, the insulator 112 is continuously provided on the inside and outside of the conductor 114, and the portion provided on the inside of the conductor 114 is the conductor 114 and the conductor. It functions as a gate insulating film for 102.
　ここで、絶縁体１０６ａはＩＧＺＯ（１３４）を想定し、半導体１０６ｂはＩＧＺＯ（１１１）を想定した。また、低抵抗領域１０６ｃ及び低抵抗領域１０６ｄは半導体にドナーを添加してドナー密度１．０×１０１９／ｃｍ３としたものを想定した。 Here, the insulator 106a assumed IGZO (134), and the semiconductor 106b assumed IGZO (111). The low resistance region 106c and the low resistance region 106d were assumed to have a donor density of 1.0 × 10 19 / cm 3 by adding a donor to the semiconductor.
　計算は、Ｓｉｌｖａｃｏ社デバイスシミュレータＡＴＬＡＳ３Ｄを用いた。主な計算条件としては、チャネル長Ｌ（図２６に示す導電体１１４の幅）を３０ｎｍとし、半導体１０６ｂの半径を１０ｎｍとし、絶縁体１０６ａの膜厚を５ｎｍとし、導電体１１４の膜厚を１０ｎｍとし、導電体１０２の膜厚を２ｎｍとした。また、絶縁体１１２において、絶縁体１０６ａと導電体１１４の間の膜厚は１２ｎｍとし、絶縁体１０６ａと導電体１０２の間の膜厚は５ｎｍとし、導電体１１４より外側の膜厚は１０ｎｍとした。また、以下の表１に、計算に用いた詳細なパラメータを示す。なお、表１において、伝導帯状態密度（Ｎｃ）は伝導帯下端における状態密度を示し、価電子帯状態密度（Ｎｃ）は価電子帯上端における状態密度を示す。 Calculation used Silvaco device simulator ATLAS3D. The main calculation conditions are that the channel length L (the width of the conductor 114 shown in FIG. 26) is 30 nm, the radius of the semiconductor 106b is 10 nm, the thickness of the insulator 106a is 5 nm, and the thickness of the conductor 114 is The thickness of the conductor 102 was 2 nm. In the insulator 112, the thickness between the insulator 106a and the conductor 114 is 12 nm, the thickness between the insulator 106a and the conductor 102 is 5 nm, and the thickness outside the conductor 114 is 10 nm. did. Table 1 below shows detailed parameters used in the calculation. In Table 1, the conduction band state density (Nc) indicates the state density at the lower end of the conduction band, and the valence band state density (Nc) indicates the state density at the upper end of the valence band.
Figure JPOXMLDOC01-appb-T000003
Figure JPOXMLDOC01-appb-T000003
　モデル１１は、トランジスタ１０と同様に、半導体１０６ｂ、絶縁体１０６ａ、絶縁体１１２、導電体１０２、導電体１１４、導電体１０８ａ及び導電体１０８ｂを有する。ここで、半導体１０６ｂは活性層として機能し、絶縁体１１２は導電体１０４及び導電体１０２に対するゲート絶縁膜として機能し、導電体１１４はゲート電極として機能し、導電体１０２はバックゲート電極として機能し、導電体１０８ａはソース電極として機能し、導電体１０８ｂはドレイン電極として機能する。 Similar to the transistor 10, the model 11 includes a semiconductor 106b, an insulator 106a, an insulator 112, a conductor 102, a conductor 114, a conductor 108a, and a conductor 108b. Here, the semiconductor 106b functions as an active layer, the insulator 112 functions as a gate insulating film for the conductor 104 and the conductor 102, the conductor 114 functions as a gate electrode, and the conductor 102 functions as a back gate electrode. The conductor 108a functions as a source electrode, and the conductor 108b functions as a drain electrode.
　デバイスシミュレーションを行って得たＩｄ−Ｖｇ特性（ドレイン電流−ゲート電圧特性）を図２７に示す。図２７において、横軸にゲート電圧Ｖｇ［Ｖ］、縦軸にドレイン電流Ｉｄ［Ａ］をとる。Ｉｄ−Ｖｇ特性の計算は、バックゲート電圧Ｖｂｇを−３Ｖにした場合と、Ｖｂｇを０Ｖにした場合について行った。それぞれにおいて、ドレイン電圧を０．１Ｖとし、ゲート電圧を−３．０Ｖから３．０Ｖまで掃引させている。 FIG. 27 shows Id-Vg characteristics (drain current-gate voltage characteristics) obtained by performing device simulation. In FIG. 27, the horizontal axis represents the gate voltage Vg [V], and the vertical axis represents the drain current Id [A]. The calculation of the Id-Vg characteristic was performed when the back gate voltage Vbg was set to -3V and when Vbg was set to 0V. In each case, the drain voltage is set to 0.1 V, and the gate voltage is swept from −3.0 V to 3.0 V.
　図２７に示すように、バックゲート電圧を印加していない（Ｖｂｇ＝０Ｖ）ときは、Ｖｇ＝０Ｖにおいてトランジスタが導通状態となっているが、Ｖｂｇ＝−３Ｖにしたときは、Ｖｇ＝０Ｖにおいてトランジスタが非導通状態となっている。このように、バックゲート電圧を印加することにより、ノーマリーオフ型のＩｄ−Ｖｇ特性が得られることが示された。 As shown in FIG. 27, when no back gate voltage is applied (Vbg = 0V), the transistor is in a conductive state at Vg = 0V, but when Vbg = -3V, Vg = 0V. The transistor is nonconductive. Thus, it was shown that a normally-off type Id-Vg characteristic can be obtained by applying the back gate voltage.
　このように、半導体１０６ｂを囲むようにゲート電極としての機能を有する導電体１１４を設け、バックゲートとして機能する導電体１０２を設けることにより、チャネル長が短い構造のトランジスタにおいても、ノーマリーオフの電気特性を与えることができる。 In this manner, by providing the conductor 114 functioning as a gate electrode so as to surround the semiconductor 106b and providing the conductor 102 functioning as a back gate, a transistor with a short channel length can be normally off. Electric characteristics can be given.
１０　　トランジスタ
１０ａ　　トランジスタ
１０ｂ　　トランジスタ
１０ｃ　　トランジスタ
１０ｄ　　トランジスタ
１０ｅ　　トランジスタ
１１　　モデル
１４　　トランジスタ
５０　　トランジスタ
５０ａ　　トランジスタ
１０２　　導電体
１０４　　導電体
１０６ａ　　絶縁体
１０６ｂ　　半導体
１０６ｃ　　低抵抗領域
１０６ｄ　　低抵抗領域
１０８ａ　　導電体
１０８ｂ　　導電体
１１２　　絶縁体
１１４　　導電体
１５０　　基板
１５１　　絶縁体
１５２　　導電体
１５６ａ　　絶縁体
１５６ｂ　　半導体
１５６ｃ　　絶縁体
１５６ｄ　　絶縁体
１５６ｅ　　絶縁体
１５６ｆ　　絶縁体
１５７　　絶縁体
１５８ａ　　導電体
１５８ｂ　　導電体
１５８ｃ　　導電体
１５８ｄ　　導電体
１５８ｅ　　導電体
１５８ｆ　　導電体
１６２　　絶縁体
１６２ａ　　絶縁体
１６２ｂ　　絶縁体
１６２ｃ　　絶縁体
１６２ｄ　　絶縁体
１６２ｅ　　絶縁体
１６２ｆ　　絶縁体
１６２ｇ　　絶縁体
１６２ｈ　　絶縁体
１６４ａ　　導電体
１６４ｂ　　導電体
１６７　　絶縁体
８００　　インバータ
８１０　　ＯＳトランジスタ
８２０　　ＯＳトランジスタ
８３１　　信号波形
８３２　　信号波形
８４０　　破線
８４１　　実線
８５０　　ＯＳトランジスタ
８６０　　ＣＭＯＳインバータ
９０１　　筐体
９０２　　筐体
９０３　　表示部
９０４　　表示部
９０５　　マイクロフォン
９０６　　スピーカー
９０７　　操作キー
９０８　　スタイラス
９１１　　筐体
９１２　　筐体
９１３　　表示部
９１４　　表示部
９１５　　接続部
９１６　　操作キー
９２１　　筐体
９２２　　表示部
９２３　　キーボード
９２４　　ポインティングデバイス
９３１　　筐体
９３２　　冷蔵室用扉
９３３　　冷凍室用扉
９４１　　筐体
９４２　　筐体
９４３　　表示部
９４４　　操作キー
９４５　　レンズ
９４６　　接続部
９５１　　車体
９５２　　車輪
９５３　　ダッシュボード
９５４　　ライト
１１８９　　ＲＯＭインターフェース
１１９０　　基板
１１９１　　ＡＬＵ
１１９２　　ＡＬＵコントローラ
１１９３　　インストラクションデコーダ
１１９４　　インタラプトコントローラ
１１９５　　タイミングコントローラ
１１９６　　レジスタ
１１９７　　レジスタコントローラ
１１９８　　バスインターフェース
１１９９　　ＲＯＭ
１２００　　記憶素子
１２０１　　回路
１２０２　　回路
１２０３　　スイッチ
１２０４　　スイッチ
１２０６　　論理素子
１２０７　　容量素子
１２０８　　容量素子
１２０９　　トランジスタ
１２１０　　トランジスタ
１２１３　　トランジスタ
１２１４　　トランジスタ
１２２０　　回路
２１００　　トランジスタ
２２００　　トランジスタ
３００１　　配線
３００２　　配線
３００３　　配線
３００４　　配線
３００５　　配線
３００６　　配線
３２００　　トランジスタ
３３００　　トランジスタ
３４００　　容量素子
３５００　　トランジスタ
４００１　　配線
４００３　　配線
４００５　　配線
４００６　　配線
４００７　　配線
４００８　　配線
４００９　　配線
４０２１　　層
４０２２　　層
４０２３　　層
４１００　　トランジスタ
４２００　　トランジスタ
４３００　　トランジスタ
４４００　　トランジスタ
４５００　　容量素子
４６００　　容量素子 10 transistor 10a transistor 10b transistor 10c transistor 10d transistor 10e transistor 11 model 14 transistor 50 transistor 50a transistor 102 conductor 104 conductor 106a insulator 106b semiconductor 106c low resistance area 106d low resistance area 108a conductor 108b conductor 112 insulator 114 conduction Body 150 substrate 151 insulator 152 conductor 156a insulator 156b semiconductor 156c insulator 156d insulator 156e insulator 156f insulator 157 insulator 158a conductor 158b conductor 158c conductor 158d conductor 158e conductor 158f conductor 162 insulator 162a Insulator 162b Insulator 162c Insulator 162d Insulator 162e Insulator 162f Insulator 162g Insulator 162h Insulator 164a Conductor 164b Conductor 167 Insulator 800 Inverter 810 OS transistor 820 OS transistor 831 Signal waveform 832 Signal waveform 840 Dashed line 841 Solid line 850 OS transistor 860 CMOS inverter 901 Case 902 Case 903 Display portion 904 Display portion 905 Microphone 906 Speaker 907 Operation key 908 Stylus 911 Case 912 Case 913 Display portion 914 Display portion 915 Connection portion 916 Operation key 921 Case 922 Display portion 923 Keyboard 924 Pointing device 931 Case 932 Cold room door 933 Freezer compartment door 941 Case 942 Case 943 Display portion 944 Operation key 945 Lens 946 Connection portion 951 Car body 952 Wheel 9 3 Dashboard 954 Light 1189 ROM interface 1190 substrate 1191 ALU
1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Register 1197 Register Controller 1198 Bus Interface 1199 ROM
1200 memory element 1201 circuit 1202 circuit 1203 switch 1204 switch 1206 logic element 1207 capacitor element 1208 capacitor element 1209 transistor 1210 transistor 1213 transistor 1214 transistor 1220 circuit 2100 transistor 2200 transistor 3001 wiring 3002 wiring 3003 wiring 3004 wiring 3005 wiring 3006 wiring 3200 transistor 3300 transistor 3400 Capacitor 3500 Transistor 4001 Wiring 4003 Wiring 4005 Wiring 4006 Wiring 4007 Wiring 4008 Wiring 4009 Wiring 4021 Layer 4022 Layer 4023 Layer 4100 Transistor 4200 Transistor 4300 Transistor 4400 Transistor 4500 Capacitance element 4 00 capacitive element

Claims (10)

  1. 　環状に設けられた第１の導電体と、
    　前記第１の導電体の環の内側を通して伸長した領域を有する酸化物半導体と、
    　前記第１の導電体と、前記酸化物半導体との間に設けられた第１の絶縁体と、
    　前記第１の導電体と、前記第１の絶縁体との間に設けられた第２の絶縁体と、
    　前記第１の導電体の環の内側を通して設けられた第２の導電体と、を有し、
    　前記第２の導電体は、前記第２の絶縁体中に設けられる半導体装置。     A first conductor provided in an annular shape;
    An oxide semiconductor having a region extending through the inside of the ring of the first conductor;
    A first insulator provided between the first conductor and the oxide semiconductor;
    A second insulator provided between the first conductor and the first insulator;
    A second conductor provided through the inside of the ring of the first conductor,
    The second conductor is a semiconductor device provided in the second insulator.
  2. 　請求項１において、
    　前記酸化物半導体に接して、前記第１の導電体を間に挟んで設けられた第３の導電体及び第４の導電体と、をさらに有し、
    　前記第３の導電体と前記第４の導電体の間の距離は２ｎｍ以上３０ｎｍ以下であることを特徴とする半導体装置。     In claim 1,
    A third conductor and a fourth conductor provided in contact with the oxide semiconductor and sandwiching the first conductor therebetween;
    A distance between the third conductor and the fourth conductor is 2 nm or more and 30 nm or less.
  3. 　請求項１または請求項２において、
    　前記酸化物半導体の伸長方向に略垂直な面における断面形状は、略円形状であることを特徴とする半導体装置。     In claim 1 or claim 2,
    The semiconductor device according to claim 1, wherein a cross-sectional shape in a plane substantially perpendicular to the extending direction of the oxide semiconductor is a substantially circular shape.
  4. 　請求項１または請求項２において、
    　前記酸化物半導体の伸長方向に略垂直な面における断面形状は、略多角形状であることを特徴とする半導体装置。     In claim 1 or claim 2,
    The semiconductor device according to claim 1, wherein a cross-sectional shape in a plane substantially perpendicular to the extending direction of the oxide semiconductor is a substantially polygonal shape.
  5. 　請求項１または請求項２において、
    　前記半導体装置は、基板上に設けられており、
    　前記基板の上面は、前記酸化物半導体の伸長方向に略平行であることを特徴とする半導体装置。     In claim 1 or claim 2,
    The semiconductor device is provided on a substrate,
    The semiconductor device according to claim 1, wherein an upper surface of the substrate is substantially parallel to an extending direction of the oxide semiconductor.
  6. 　請求項１または請求項２において、
    　前記半導体装置は、基板上に設けられており、
    　前記基板の上面は、前記酸化物半導体の伸長方向に略垂直であることを特徴とする半導体装置。     In claim 1 or claim 2,
    The semiconductor device is provided on a substrate,
    The semiconductor device according to claim 1, wherein an upper surface of the substrate is substantially perpendicular to an extending direction of the oxide semiconductor.
  7. 　請求項１または請求項２において、
    　前記第１の絶縁体は、インジウム、元素Ｍ（Ｔｉ、Ｇａ、Ｙ、Ｚｒ、Ｌａ、Ｃｅ、Ｎｄ、ＳｎまたはＨｆ）及び亜鉛のうち少なくとも一以上を有することを特徴とする半導体装置。     In claim 1 or claim 2,
    The semiconductor device is characterized in that the first insulator includes at least one of indium, element M (Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf) and zinc.
  8. 　基板上に、第１の方向に伸長して設けられた第１の導電体と、
    　前記第１の導電体上に設けられた第１の絶縁体と、
    　前記第１の絶縁体上に設けられた、開口を有する第２の絶縁体と、
    　前記第２の絶縁体に形成された開口の中に、前記第１の方向に略垂直である第２の方向に伸長して設けられた第２の導電体と
    　前記第２の絶縁体及び前記第２の導電体上に設けられた第３の絶縁体と、
    　前記第３の絶縁体上に設けられた第４の絶縁体と、
    　前記第３の絶縁体上に、前記第４の絶縁体を間に挟んで設けられた第３の導電体及び第４の導電体と、
    　前記第４の絶縁体、前記第３の導電体及び前記第４の導電体の上面に接して、第２の方向に伸長して設けられた酸化物半導体と、
    　前記酸化物半導体の上面及び側面と、前記第３の導電体の側面に接して、第５の絶縁体を間に挟んで第６の導電体と対向して設けられた第５の導電体と、
    　前記酸化物半導体の上面及び側面と、前記第４の導電体の側面に接して、第５の絶縁体を間に挟んで前記第５導電体と対向して設けられた前記第６の導電体と、
    　前記第５の導電体及び前記第６の導電体上に設けられ、前記第５の導電体と前記第６の導電体の間に開口を有する第６の絶縁体と、
    　前記酸化物半導体の上面、前記第５の導電体及び前記第６の導電体の側面、前記第６の絶縁体の側面と接して設けられた前記第５の絶縁体と、
    前記第５の絶縁体の上面に接して設けられた第７の絶縁体と、
    前記第７の絶縁体の上面に接して設けられた第７の導電体と、を有し、
    　前記第１の方向に略垂直な面の断面において、
    　前記第４の絶縁体と前記第５の絶縁体は、前記酸化物半導体を囲むように設けられ、
    　前記第３の絶縁体と前記第７の絶縁体は、前記第４の絶縁体、前記酸化物半導体及び前記第５の絶縁体を囲むように設けられ、
    　前記第１の導電体と前記第７の導電体は、前記第１乃至第３の絶縁体及び前記第７の絶縁体を囲むように設けられることを特徴とする半導体装置。     A first conductor provided extending on the substrate in a first direction;
    A first insulator provided on the first conductor;
    A second insulator having an opening provided on the first insulator;
    A second conductor provided in an opening formed in the second insulator and extending in a second direction substantially perpendicular to the first direction; the second insulator; and A third insulator provided on the second conductor;
    A fourth insulator provided on the third insulator;
    A third conductor and a fourth conductor provided on the third insulator with the fourth insulator interposed therebetween;
    An oxide semiconductor provided in contact with the top surface of the fourth insulator, the third conductor, and the fourth conductor and extending in a second direction;
    A fifth conductor provided in contact with the top surface and side surface of the oxide semiconductor and the side surface of the third conductor and facing the sixth conductor with a fifth insulator interposed therebetween; ,
    The sixth conductor provided in contact with the upper surface and the side surface of the oxide semiconductor and the side surface of the fourth conductor and facing the fifth conductor with a fifth insulator interposed therebetween When,
    A sixth insulator provided on the fifth conductor and the sixth conductor and having an opening between the fifth conductor and the sixth conductor;
    The upper surface of the oxide semiconductor, the side surfaces of the fifth conductor and the sixth conductor, the fifth insulator provided in contact with the side surface of the sixth insulator;
    A seventh insulator provided in contact with the upper surface of the fifth insulator;
    A seventh conductor provided in contact with the upper surface of the seventh insulator;
    In a cross section of a plane substantially perpendicular to the first direction,
    The fourth insulator and the fifth insulator are provided so as to surround the oxide semiconductor,
    The third insulator and the seventh insulator are provided so as to surround the fourth insulator, the oxide semiconductor, and the fifth insulator,
    The semiconductor device, wherein the first conductor and the seventh conductor are provided so as to surround the first to third insulators and the seventh insulator.
  9. 　請求項８において、
    　前記第４の絶縁体及び前記第５の絶縁体は、インジウム、元素Ｍ（Ｔｉ、Ｇａ、Ｙ、Ｚｒ、Ｌａ、Ｃｅ、Ｎｄ、ＳｎまたはＨｆ）及び亜鉛のうち少なくとも一以上を有することを特徴とする半導体装置。     In claim 8,
    The fourth insulator and the fifth insulator include at least one of indium, element M (Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf) and zinc. A semiconductor device.
  10. 　請求項１、請求項２、請求項８及び請求項９のいずれか一において、
    　前記酸化物半導体は、インジウム、元素Ｍ（Ｔｉ、Ｇａ、Ｙ、Ｚｒ、Ｌａ、Ｃｅ、Ｎｄ、ＳｎまたはＨｆ）、亜鉛および酸素を有することを特徴とする半導体装置。     In any one of Claim 1, Claim 2, Claim 8, and Claim 9,
    The semiconductor device, wherein the oxide semiconductor includes indium, an element M (Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf), zinc, and oxygen.
PCT/IB2016/053315 2015-06-18 2016-06-07 Semiconductor device WO2016203341A1 (en)

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