WO2016201981A1 - 数据缓存处理方法及装置 - Google Patents

数据缓存处理方法及装置 Download PDF

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Publication number
WO2016201981A1
WO2016201981A1 PCT/CN2016/071624 CN2016071624W WO2016201981A1 WO 2016201981 A1 WO2016201981 A1 WO 2016201981A1 CN 2016071624 W CN2016071624 W CN 2016071624W WO 2016201981 A1 WO2016201981 A1 WO 2016201981A1
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data
cache
cached
request message
read
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PCT/CN2016/071624
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English (en)
French (fr)
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蒋平
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中兴通讯股份有限公司
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Publication of WO2016201981A1 publication Critical patent/WO2016201981A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems

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  • the present invention relates to the field of logic design, and in particular to a data cache processing method and apparatus.
  • the present invention provides a data cache processing method and apparatus to at least solve the problem that the external cache cannot replace the internal cache in the related art.
  • a data cache processing method including: receiving a write request message for writing data to be cached, and buffering the data to be cached to an external cache of the chip according to the write request message in.
  • the method includes: receiving a read request message for reading the specified data in the external cache, according to the The read request message reads the specified data from the external cache.
  • the buffering the data to be cached to the external cache of the chip according to the write request message includes: acquiring cache state information of the currently cached data in the external cache, according to the cache state. The information allocates a cache space for the data to be cached, and caches the data to be cached into the cache space.
  • the method before receiving the write request message for writing data to be cached, the method includes: comparing the data to be cached with the read data, and determining, when the comparison result is consistent, determining the external cache The status is normal, The read data is data corresponding to the data to be cached.
  • buffering the data to be cached into an external cache of the chip according to the write request message includes: buffering the data to be cached into the external cache according to a first predetermined timing signal; And/or reading the specified data from the external cache according to the read request message includes: reading the specified data from the external cache according to a second predetermined timing signal.
  • a data buffer processing apparatus including: a first receiving module configured to receive a write request message for writing data to be cached, and a cache module configured to be according to the write request The message caches the data to be cached into an external cache of the chip.
  • the apparatus further includes: a second receiving module configured to receive a read request message for reading specified data in the external cache, and a reading module configured to be according to the read request A message reads the specified data from the external cache.
  • the cache module further includes: an obtaining unit, configured to acquire cache state information of the currently cached data in the external cache, and an allocating unit configured to set the Cache data allocation cache space, a cache unit, configured to cache the data to be cached into the cache space.
  • the apparatus further includes: a comparison module, configured to compare the data to be cached with the read data, and determine that the state of the external cache is normal if the comparison result is consistent a state, wherein the read data is data corresponding to the data to be cached.
  • a comparison module configured to compare the data to be cached with the read data, and determine that the state of the external cache is normal if the comparison result is consistent a state, wherein the read data is data corresponding to the data to be cached.
  • the apparatus further includes: the cache module, configured to buffer the data to be cached into the external cache according to a first predetermined timing signal; and/or, the reading module And setting to read the specified data from the external cache according to a second predetermined timing signal.
  • the write request message for writing data to be cached is received, and the data to be cached is cached in the external cache of the chip according to the write request message, which solves the problem that the external cache cannot replace the internal cache.
  • the problem in turn, achieves small changes to existing designs when using external caching, short development cycles, and the difficulty of citing unknown problems.
  • FIG. 1 is a flowchart of a data buffer processing method according to an embodiment of the present invention.
  • FIG. 2 is a structural block diagram (1) of a data buffer processing apparatus according to an embodiment of the present invention.
  • FIG. 3 is a structural block diagram (2) of a data buffer processing apparatus according to an embodiment of the present invention.
  • FIG. 4 is a structural block diagram (3) of a data buffer processing apparatus according to an embodiment of the present invention.
  • FIG. 5 is a structural block diagram (4) of a data buffer processing apparatus according to an embodiment of the present invention.
  • FIG. 6 is a block diagram of an external cache implementation method according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of cache partitioning according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of cache management according to an embodiment of the present invention.
  • FIG. 9 is a flow chart of an external cache control method in accordance with an embodiment of the present invention.
  • FIG. 1 is a flowchart of a data cache processing method according to an embodiment of the present invention. As shown in FIG. 1, the process includes the following steps:
  • Step S102 receiving a write request message for writing data to be cached
  • Step S104 buffering the data to be cached into an external cache of the chip according to the write request message.
  • the write request message for writing the data to be cached is received, and the data to be cached is cached in the external cache of the chip according to the write request message, which is directly used when the internal cache is insufficient to solve the problem.
  • the external cache requires a lot of changes to the existing design code, and the development cycle is extended.
  • the above steps solve the problem in the related art that the external cache cannot be replaced by the internal cache, thereby achieving the existing design when using the external cache. Small changes, short development cycles and the difficulty of citing unknown problems.
  • step S104 involves caching the data to be cached into the external cache of the chip according to the write request message.
  • the receiving is performed after the cache data is cached in the external cache of the chip according to the write request message.
  • a read request message for reading the specified data in the external cache is read, and the specified data is read from the external cache according to the read request message. Therefore, the read and write operations on the data can be realized through the external cache, and the storage space of the chip is expanded.
  • the storage space needs to be allocated for the data to be cached.
  • the cache state information of the currently cached data in the external cache is obtained, and the cache state information is used as the The cache data allocates a cache space, and the data to be cached is cached into the cache space. Therefore, a reasonable storage space is allocated for the data to be cached, and the storage space is optimized.
  • the state of the external cache may be abnormal. Therefore, the external cache needs to be detected. When the detection result is normal, the external cache is used to read and write data.
  • the data to be cached is compared with the read data, and if the comparison result is consistent, the state of the external cache is determined to be a normal state.
  • the read data is data corresponding to the data to be cached.
  • the data to be cached may be buffered into the external cache according to the first predetermined timing signal, or the designated data may be read from the external cache according to the second predetermined timing signal.
  • This method can achieve efficient conversion of data writing and reading, ensuring the validity of data writing to the external cache and reading data from the external cache.
  • the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, by hardware, but in many cases, the former is A better implementation.
  • the technical solution of the present invention which is essential or contributes to the prior art, may be embodied in the form of a software product stored in a storage medium (such as ROM/RAM, disk,
  • the optical disc includes a plurality of instructions for causing a terminal device (which may be a mobile phone, a computer, a server, or a network device, etc.) to perform the above-described methods of various embodiments of the present invention.
  • a data cache processing device is also provided, which is used to implement the foregoing embodiments and preferred embodiments, and has not been described again.
  • the term "module” may implement a combination of software and/or hardware of a predetermined function.
  • the apparatus described in the following embodiments is preferably implemented in software, hardware, or a combination of software and hardware, is also possible and contemplated.
  • the apparatus includes: a first receiving module 22 configured to receive a write request message for writing data to be cached.
  • the cache module 24 is configured to cache the data to be cached into an external cache of the chip according to the write request message.
  • FIG. 3 is a block diagram (2) of a data cache processing apparatus according to an embodiment of the present invention.
  • the apparatus further includes: a second receiving module 32 configured to receive a read of the specified data in the read external cache.
  • the request message, read module 34 is configured to read the specified data from the external cache in accordance with the read request message.
  • the cache module 24 in the apparatus further includes: an obtaining unit 42 configured to acquire data currently cached in the external cache. Cache status information.
  • the allocating unit 44 is configured to allocate a buffer space for the data to be cached according to the cache state information, and the cache unit 46 is configured to cache the data to be cached into the cache space.
  • FIG. 5 is a structural block diagram (4) of a data cache processing apparatus according to an embodiment of the present invention.
  • the apparatus further includes: a comparison module 52 configured to compare data to be cached with read data, and compare If the result is consistent, it is determined that the state of the external cache is a normal state, wherein the read data is data corresponding to the data to be cached.
  • the cache module 24 in the apparatus is configured to buffer the data to be cached into the external cache according to the first predetermined timing signal; and/or the read module 34 in the apparatus is further configured to follow The second predetermined timing signal reads the specified data from the external cache.
  • each of the above modules may be implemented by software or hardware.
  • the foregoing may be implemented by, but not limited to, the foregoing modules are all located in the same processor; or, the modules are located in multiple In the processor.
  • Embodiments of the present invention also provide a storage medium.
  • the foregoing storage medium may be configured to store program code for performing the following steps:
  • the data to be cached is buffered into an external cache of the chip according to the write request message.
  • the foregoing storage medium may include, but not limited to, a USB flash drive, a Read-Only Memory (ROM), a Random Access Memory (RAM), a mobile hard disk, and a magnetic memory.
  • ROM Read-Only Memory
  • RAM Random Access Memory
  • a mobile hard disk e.g., a hard disk
  • magnetic memory e.g., a hard disk
  • the processor performs the above steps S1 and S2 according to the stored program code in the storage medium.
  • the optional embodiment is directed to the design implementation in the related art, and the replacement of the internal small-capacity cache by the external large-capacity cache is implemented in the simplest method.
  • the cache interface control module implements interface control for reading and writing external caches
  • the cache management module divides and manages the external cache according to actual needs, and provides a read/write interface similar to the internal cache of the chip for internal access;
  • a buffer status indication module indicating data storage status of each divided module
  • the external cache self-test module (equivalent to the comparison module 52 above) implements a self-test function for the external cache, including a simple self-test and all spatial traversal self-tests.
  • module A completes access control to an external cache interface, and is directly connected to an external cache chip through a physical line; and module B implements a cache management function.
  • the buffer space is allocated according to the buffer status and the specific data situation, the read data control signal is generated according to the information, and the read/write operation is time-shifted to meet the requirements of module A;
  • module C calculates the data storage of each divided interval according to the read/write buffer situation. Status and related information;
  • Module D implements self-test function control, including starting self-test function, outputting self-test result, and selecting self-test mode.
  • FIG. 7 is a schematic diagram of cache partitioning according to an embodiment of the present invention.
  • the address space is divided into n equal parts according to a specific use case, and each aliquot is regarded as a large-capacity RAM. Then, for each RAM, according to the actual data length that needs to be stored, it is divided into k CHUNKs.
  • the principle of dividing the CHUNK size is to ensure that the most similar data can be stored in a CHUNK.
  • FIG. 8 is a schematic diagram of cache management according to an embodiment of the present invention, and FIG. 8 illustrates storage and read control of four data packets.
  • Use Bi-jn(s, m, e) to represent a slice where the letter i represents the i-th arriving slice, j indicates that the slice needs to be stored in the RAM j, and n represents the n-th slice in the RAM j.
  • s in parentheses indicates that the fragment contains a packet
  • m indicates that the fragment is a packet intermediate fragment
  • e indicates that the fragment is the end of containing a packet.
  • B0-0-0(s) in the figure is the first fragment of RAM0, and contains the beginning of the data packet, stored in the CHUNK0 position of RAM0; B1-1-0(s, e) is the first of RAM1 Fragmentation, and contains the beginning and end of the data, so B1-1-0(s, e) is a complete packet, stored in the CHUNK0 position of RAM1; B2-0-1(m) is the second of RAM0 Fragmentation, the slice is the middle slice of the data packet, stored in the CHUNK1 position of RAM0; B4-0-2(e) is the 5th slice, belonging to the 3rd slice of RAM0, stored in RAM0 CHUNK2, including the end of the data packet, so B0-0-0 (s), B2-0-1 (m), B4-0-2 (e) three fragments constitute a complete package in RAM0, B1-1-0(s,e) is a complete packet in RAM1, B3-2-0(s) and B-5-2-1(e) are a complete packet in RAM2, B6-3-0 (s
  • the example in the figure is performed in the whole packet reading mode, so in principle, the RAM with the entire packet will be read first, so that the packet of RAM1 will be read first by B1-1-0(s, e). , then RAM0 package B0-0-0(s), B2-0-1(m), B4-0-2(e), then RAM2, RAM3.
  • FIG. 9 is a flowchart of an external cache control method according to an embodiment of the present invention. As shown in FIG. 9, the method includes the following steps:
  • Step 902 Determine whether a self-test is required for the external cache. If a self-test is required, go to step 904; if the self-test is not required, go to step 906.
  • Step 904 Start a self-test state, and according to the self-test mode, generate data that needs to be written into the external cache by the self-test.
  • Step 906 There is data that needs to be cached normally, and can be stored in an external cache.
  • Step 908 According to the incoming data and the current cache state information, allocate corresponding buffer space to the data, and generate a timing signal required by the interface module according to the requirements of the interface control module.
  • Step 910 Access the external cache through the interface control module, and write the data into the corresponding cache space.
  • Step 912 Access the external cache through the interface control module, and read out the required stored data.
  • Step 914 Calculate data storage state information of the corresponding buffer interval according to the related information of steps 91010 and 912.
  • Step 916 Determine whether the current processing flow is in the self-test state, if in the self-test state, proceed to step 918; if not in the self-test state, proceed to step 90A.
  • Step 918 In the self-test state, compare the read cache data with the write cache data to determine whether the external cache state is normal.
  • Step 90A In the non-self-test state, the data read from the external buffer is output to the lower-level module for use.
  • Step 90B According to the comparison result, it is judged whether the self-test passes. If the comparison result meets the requirements, the self-test passes, and if it is not satisfied, the self-test fails, and the corresponding status indication is given respectively.
  • the external cache is introduced by the present invention, and the write request message for writing the data to be cached is received, and the data to be cached is cached in the external cache of the chip according to the write request message, which solves the related art. It is not enough to rely on the internal cache of the chip. Direct use of the external cache requires a major change to the existing design code, resulting in the development week. The problem of long period of time, and the invention achieves the effect of small changes to the existing design, short development cycle and difficulty in quoting unknown problems when using the external cache by using the external cache indirectly without the technical means of making major changes to the existing ones. .
  • modules or steps of the present invention described above can be implemented by a general-purpose computing device that can be centralized on a single computing device or distributed across a network of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device such that they may be stored in the storage device by the computing device and, in some cases, may be different from the order herein.
  • the steps shown or described are performed, or they are separately fabricated into individual integrated circuit modules, or a plurality of modules or steps thereof are fabricated as a single integrated circuit module.
  • the invention is not limited to any specific combination of hardware and software.
  • a write request message for writing data to be cached is received, and the data to be cached is cached in an external cache of the chip according to the write request message, which solves the related art and cannot be implemented.
  • the external cache replaces the problem of the internal cache, which in turn achieves small changes to existing designs when using external caches, short development cycles, and difficulty in quoting unknown problems.

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Abstract

本发明提供了一种数据缓存处理方法及装置，其中，该方法包括：接收写入待缓存数据的写入请求消息，根据该写入请求消息将待缓存数据缓存至芯片的外部缓存中。通过本发明解决了相关技术中，无法实现外部缓存替换内部缓存的问题，进而达到了在使用外部缓存时对现有设计改动小，开发周期短和不易引用未知问题的效果。

Description

数据缓存处理方法及装置 技术领域
本发明涉及逻辑设计领域，具体而言，涉及一种数据缓存处理方法及装置。
背景技术
在芯片设计中，内部缓存经常被用来存储数据，但是内部缓存的容量和数量都很有限，只能对少量内容进行存储。随着电信级网络的发展，网络设备中物理接口的汇聚和分发的应用场景会越来越多，涉及的端口数量也会越来越多，根据不同的使用场景，也会提出不同的要求。如果现有的设计是用芯片实现端口汇聚功能，则需要增加流量管理(QoS)功能；或者是实现端口分发功能，则要靠缓存吸收对物理端口的突发，防止突发时的溢出丢包。
要实现类似功能的增加，光靠芯片的内部缓存是远远不够的，需要采用外部缓存替换内部缓存。
直接用外部缓存(如双倍速率同步动态随机存储器(Double Data Rate SDRAM，简称DDR SDRAM)、四倍数据传输静态随机存储器(Quad Data rate SRAM，简称QDR SRAM))等，那么就需要对现有设计代码进行很大的改动，这种改动会延长开发周期，也容易引入未知问题。
针对相关技术中，如何实现外部缓存替换内部缓存的问题，还未提出有效的解决方案。
发明内容
本发明提供了一种数据缓存处理方法及装置，以至少解决相关技术中无法实现外部缓存替换内部缓存的问题。
根据本发明的一个实施例，提供了一种数据缓存处理方法，包括：接收写入待缓存数据的写入请求消息，根据所述写入请求消息将所述待缓存数据缓存至芯片的外部缓存中。
在本发明的实施例中，根据所述写入请求消息将所述待缓存数据缓存至芯片的外部缓存中之后包括：接收读取所述外部缓存中的指定数据的读取请求消息，根据所述读取请求消息从所述外部缓存中读取所述指定数据。
在本发明的实施例中，根据所述写入请求消息将所述待缓存数据缓存至芯片的外部缓存中包括：获取所述外部缓存中当前缓存的数据的缓存状态信息，根据所述缓存状态信息为所述待缓存数据分配缓存空间，将所述待缓存数据缓存至所述缓存空间中。
在本发明的实施例中，接收写入待缓存数据的写入请求消息之前包括：将所述待缓存数据与读取的数据进行对比，在对比结果一致的情况下，确定所述外部缓存的状态为正常状态， 其中，所述读取的数据是与所述待缓存数据对应的数据。
在本发明的实施例中，根据所述写入请求消息将所述待缓存数据缓存至芯片的外部缓存中包括：按照第一预定时序信号将所述待缓存数据缓存至所述外部缓存中；和/或，根据所述读取请求消息从所述外部缓存中读取所述指定数据包括：按照第二预定时序信号从所述外部缓存中读取所述指定数据。
根据本发明的另一个实施例，提供了一种数据缓存处理装置，包括：第一接收模块，设置为接收写入待缓存数据的写入请求消息，缓存模块，设置为根据所述写入请求消息将所述待缓存数据缓存至芯片的外部缓存中。
在本发明的实施例中，所述装置还包括：第二接收模块，设置为接收读取所述外部缓存中的指定数据的读取请求消息，读取模块，设置为根据所述读取请求消息从所述外部缓存中读取所述指定数据。
在本发明的实施例中，所述缓存模块还包括：获取单元，设置为获取所述外部缓存中当前缓存的数据的缓存状态信息，分配单元，设置为根据所述缓存状态信息为所述待缓存数据分配缓存空间，缓存单元，设置为将所述待缓存数据缓存至所述缓存空间中。
在本发明的实施例中，所述装置还包括：对比模块，设置为将所述待缓存数据与读取的数据进行对比，在对比结果一致的情况下，确定所述外部缓存的状态为正常状态，其中，所述读取的数据是与所述待缓存数据对应的数据。
在本发明的实施例中，所述装置还包括：所述缓存模块，设置为按照第一预定时序信号将所述待缓存数据缓存至所述外部缓存中；和/或，所述读取模块，设置为按照第二预定时序信号从所述外部缓存中读取所述指定数据。
通过本发明，采用接收写入待缓存数据的写入请求消息，根据该写入请求消息将该待缓存数据缓存至芯片的外部缓存中，解决了相关技术中，无法实现外部缓存替换内部缓存的问题，进而达到了在使用外部缓存时对现有设计改动小，开发周期短和不易引用未知问题的效果。
附图说明
此处所说明的附图用来提供对本发明的进一步理解，构成本申请的一部分，本发明的示意性实施例及其说明用于解释本发明，并不构成对本发明的不当限定。在附图中：
图1是根据本发明实施例的数据缓存处理方法流程图；
图2是根据本发明实施例的数据缓存处理装置结构框图(一)；
图3是根据本发明实施例的数据缓存处理装置结构框图(二)；
图4是根据本发明实施例的数据缓存处理装置结构框图(三)；
图5是根据本发明实施例的数据缓存处理装置结构框图(四)；
图6是根据本发明实施例的外部缓存实现方法框图；
图7是根据本发明实施例的缓存划分示意图；
图8是根据本发明实施例的缓存管理示意图；
图9是根据本发明实施例的外部缓存控制方法流程图。
具体实施方式
下文中将参考附图并结合实施例来详细说明本发明。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
需要说明的是，本发明的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。
在本实施例中提供了一种数据缓存处理方法，图1是根据本发明实施例的数据缓存处理方法流程图，如图1所示，该流程包括如下步骤：
步骤S102，接收写入待缓存数据的写入请求消息；
步骤S104，根据写入请求消息将该待缓存数据缓存至芯片的外部缓存中。
通过上述步骤，采用接收写入待缓存数据的写入请求消息，根据该写入请求消息将该待缓存数据缓存至芯片的外部缓存中，相比于现有技术在解决内部缓存不够用时直接用外部缓存，需要对现有设计代码进行很大改动，延长开发周期等问题，上述步骤解决了相关技术中，无法实现外部缓存替换内部缓存的问题，进而达到了在使用外部缓存时对现有设计改动小，开发周期短和不易引用未知问题的效果。
上述步骤S104涉及根据写入请求消息将该待缓存数据缓存至芯片的外部缓存中，在一个可选实施例中，根据该写入请求消息将该缓存数据缓存至芯片的外部缓存中之后，接收读取该外部缓存中的指定数据的读取请求消息，根据该读取请求消息从该外部缓存中读取指定数据。从而可以通过外部缓存实现了对数据的读写操作，扩大了芯片的存储空间。
在将待缓存数据缓存至上述外部缓存时，需要为待缓存数据分配存储空间，在一个可选实施例中，通过获取外部缓存中当前缓存的数据的缓存状态信息，根据该缓存状态信息为待缓存数据分配缓存空间，将待缓存数据缓存至该缓存空间中。从而合理的为待缓存数据分配了存储空间，实现了存储空间的优化。外部缓存的状态可能存在不正常的情况，因此需要对外部缓存进行检测，在检测结果为正常的情况下，才使用该外部缓存进行数据的读写操作。在一个可选实施例中，接收写入待缓存数据的写入请求消息之前，将该待缓存数据与读取的数据进行对比，在对比结果一致的情况下，确定外部缓存的状态为正常状态，其中，该读取的数据是与该待缓存数据对应的数据。通过该方法可以保证将数据写入芯片外部缓存的有效 性，避免了数据的丢失，提高了数据缓存的高效性。
在一个可选实施例中，可以按照第一预定时序信号将待缓存数据缓存至外部缓存中，或者按照第二预定时序信号从该外部缓存中读取指定数据。通过该方法可以实现数据的写入和读取的有效转换，保证了数据写入外部缓存和从外部缓存读取数据的有效性。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到根据上述实施例的方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。基于这样的理解，本发明的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质(如ROM/RAM、磁碟、光盘)中，包括若干指令用以使得一台终端设备(可以是手机，计算机，服务器，或者网络设备等)执行本发明各个实施例上述的方法。
在本实施例中还提供了一种数据缓存处理装置，该装置用于实现上述实施例及优选实施方式，已经进行过说明的不再赘述。如以下所使用的，术语“模块”可以实现预定功能的软件和/或硬件的组合。尽管以下实施例所描述的装置较佳地以软件来实现，但是硬件，或者软件和硬件的组合的实现也是可能并被构想的。
图2是根据本发明实施例的数据缓存处理装置结构框图(一)，如图2所示，该装置包括：第一接收模块22，设置为接收写入待缓存数据的写入请求消息。缓存模块24，设置为根据该写入请求消息将待缓存数据缓存至芯片的外部缓存中。
图3是根据本发明实施例的数据缓存处理装置结构框图(二)，如图3所示，该装置还包括：第二接收模块32，设置为接收读取外部缓存中的指定数据的读取请求消息，读取模块34，设置为根据该读取请求消息从该外部缓存中读取上述指定数据。
图4是根据本发明实施例的数据缓存处理装置结构框图(三)，如图4所示，该装置中的缓存模块24还包括：获取单元42，设置为获取外部缓存中当前缓存的数据的缓存状态信息。分配单元44，设置为根据该缓存状态信息为该待缓存数据分配缓存空间，缓存单元46，设置为将待缓存数据缓存至该缓存空间中。
图5是根据本发明实施例的数据缓存处理装置结构框图(四)，如图5所示，该装置还包括：对比模块52，设置为将待缓存数据与读取的数据进行对比，在对比结果一致的情况下，确定外部缓存的状态为正常状态，其中，该读取的数据是与该待缓存数据对应的数据。
在本发明的实施例中，该装置中的缓存模块24设置为按照第一预定时序信号将待缓存数据缓存至外部缓存中；和/或，该装置中的读取模块34还设置为按照第二预定时序信号从该外部缓存中读取指定数据。
需要说明的是，上述各个模块是可以通过软件或硬件来实现的，对于后者，可以通过以下方式实现，但不限于此：上述模块均位于同一处理器中；或者，上述模块分别位于多个处理器中。
本发明的实施例还提供了一种存储介质。可选地，在本实施例中，上述存储介质可以被设置为存储用于执行以下步骤的程序代码：
S1，接收写入待缓存数据的写入请求消息；
S2，根据写入请求消息将该待缓存数据缓存至芯片的外部缓存中。
可选地，在本实施例中，上述存储介质可以包括但不限于：U盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、移动硬盘、磁碟或者光盘等各种可以存储程序代码的介质。
可选地，在本实施例中，处理器根据存储介质中已存储的程序代码执行上述步骤S1和S2。
针对相关技术中存在的上述问题，下面结合具体的可选实施例进行说明，在下述可选实施例中结合了上述可选实施例及其可选实施方式。
本可选实施例针对相关技术中的的设计实现方案，用最简单的方法实现外部大容量缓存对内部小容量缓存的替换。
本发明可选实施例的外部缓存控制的实现方法和装置包含以下模块：
缓存接口控制模块，实现对外部缓存读写的接口控制；
缓存管理模块，按照实际需要对外部缓存进行划分管理，并提供类似芯片内部缓存的读写接口供内部访问；
缓存状态指示模块，指示各个划分后模块的数据存储状态；
外部缓存自检模块(相当于上述对比模块52)，实现对外部缓存的自检功能，包括简单自检和所有空间遍历自检。
图6是根据本发明实施例的外部缓存实现方法框图，如图6所示，模块A完成对外部缓存接口的访问控制，与外部缓存芯片通过物理线路直接连接；模块B实现缓存的管理功能，包括根据缓存状态以及具体数据情况分配缓存空间，根据信息产生读数据控制信号，对读写操作进行时序转换，以满足模块A的要求；模块C根据读写缓存情况，计算各个划分区间的数据存储状态及相关信息；模块D实现自检功能控制，包括启动自检功能，输出自检结果，选择自检模式。
图7是根据本发明实施例的缓存划分示意图，根据具体使用情况，把地址空间分成n等份，每个等份看成一个大容量的RAM。然后对每个RAM，根据实际需要存储的数据长度情况，再分成k个CHUNK，划分CHUNK大小的原则是保证最多同类长度的数据能正好存储在一个CHUNK里面。
图8是根据本发明实施例的缓存管理示意图，图8中示意了4个数据包的存储和读取控制情况。用Bi-j-n(s,m,e)表示一个分片，其中字母i表示第i个到达的分片，j表示该分片需要存储到RAM j里面，n表示RAM j里面第n个分片，括号中的s表示该分片包含一个数据包 的开始，m表示该分片是一个数据包中间分片，e表示该分片是包含一个数据包的结束。图中的B0-0-0(s)是RAM0第一个分片，并且包含所在数据包的开始，存储在RAM0的CHUNK0位置；B1-1-0(s,e)是RAM1的第一个分片，并且包含数据的开始和结束，所以B1-1-0(s,e)是一个完整的数据包，存储在RAM1的CHUNK0位置；B2-0-1(m)是RAM0的第2个分片，该分片是所在数据包的中间一个分片，存储在RAM0的CHUNK1位置；B4-0-2(e)是第5个分片，属于RAM0的第3个分片，存储在RAM0的CHUNK2，包含所在数据包的结束，所以B0-0-0(s)，B2-0-1(m)，B4-0-2(e)三个分片组成了RAM0里面完整的一个包，B1-1-0(s,e)是RAM1中完整的一个包，B3-2-0(s)和B-5-2-1(e)是RAM2中完整的一个包，B6-3-0(s,e)是RAM3中完整的一个包。图中示例是按照整包读取方式进行的，所以原则上是先有整包的RAM将被优先读取，这样RAM1的包会B1-1-0(s,e)第一个被读出，然后是RAM0的包B0-0-0(s)，B2-0-1(m)，B4-0-2(e)，然后是RAM2，RAM3。
图9是根据本发明实施例的外部缓存控制方法流程图，如图9所示，该方法包括以下步骤：
步骤902：判定是否需要对外部缓存进行自检，如果需要自检，则转到步骤904；如果不需要自检，则转到步骤906。
步骤904：启动自检状态，根据自检模式，产生自检需要写入外部缓存的数据。
步骤906：有正常需要缓存的数据，可以存储到外部缓存。
步骤908：根据进来的数据以及当前缓存状态信息，给数据分配对应的缓存空间，并根据接口控制模块要求，产生接口模块要求的时序信号。
步骤910：通过接口控制模块访问外部缓存，并把数据写入对应缓存空间。
步骤912：通过接口控制模块访问外部缓存，读出需要的已存储数据。
步骤914：根据步骤91010和912的相关信息，计算对应缓存区间的数据存储状态信息。
步骤916：判断当前处理流程是否在自检状态下，如果在自检状态，则转入步骤918；如果不在自检状态，则转入步骤90A。
步骤918：在自检状态下，对读出缓存的数据和写入缓存数据进行对比，判断外部缓存状态是否正常。
步骤90A：在非自检状态，把从外部缓存读出的数据，输出给下级模块使用。
步骤90B：根据对比结果，判断自检是否通过。如果对比结果满足要求，则自检通过，如果不满足，则自检失败，分别会给出对应的状态指示。
综上所述，通过本发明引入外部缓存，并且采用接收写入待缓存数据的写入请求消息，根据该写入请求消息将该待缓存数据缓存至芯片的外部缓存中，解决了相关技术中，光靠芯片内部缓存远远不够，直接使用外部缓存又必须对现有设计代码进行很大改动，导致开发周 期长的问题，而且本发明通过间接使用外部缓存又不对现有涉及做很大改动的技术手段，达到了在使用外部缓存时对现有设计改动小，开发周期短和不易引用未知问题的效果。
显然，本领域的技术人员应该明白，上述的本发明的各模块或各步骤可以用通用的计算装置来实现，它们可以集中在单个的计算装置上，或者分布在多个计算装置所组成的网络上，可选地，它们可以用计算装置可执行的程序代码来实现，从而，可以将它们存储在存储装置中由计算装置来执行，并且在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤，或者将它们分别制作成各个集成电路模块，或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。这样，本发明不限制于任何特定的硬件和软件结合。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。
工业实用性
基于本发明实施例提供的上述技术方案，接收写入待缓存数据的写入请求消息，根据该写入请求消息将该待缓存数据缓存至芯片的外部缓存中，解决了相关技术中，无法实现外部缓存替换内部缓存的问题，进而达到了在使用外部缓存时对现有设计改动小，开发周期短和不易引用未知问题的效果。

Claims (10)

  1. 一种数据缓存处理方法，包括：
    接收写入待缓存数据的写入请求消息；
    根据所述写入请求消息将所述待缓存数据缓存至芯片的外部缓存中。
  2. 根据权利要求1所述的方法，其中，根据所述写入请求消息将所述待缓存数据缓存至芯片的外部缓存中之后包括：
    接收读取所述外部缓存中的指定数据的读取请求消息；
    根据所述读取请求消息从所述外部缓存中读取所述指定数据。
  3. 根据权利要求1所述的方法，其中，根据所述写入请求消息将所述待缓存数据缓存至芯片的外部缓存中包括：
    获取所述外部缓存中当前缓存的数据的缓存状态信息；
    根据所述缓存状态信息为所述待缓存数据分配缓存空间；
    将所述待缓存数据缓存至所述缓存空间中。
  4. 根据权利要求2所述的方法，其中，接收写入待缓存数据的写入请求消息之前包括：
    将所述待缓存数据与读取的数据进行对比，在对比结果一致的情况下，确定所述外部缓存的状态为正常状态，其中，所述读取的数据是与所述待缓存数据对应的数据。
  5. 根据权利要求1至4中任一项所述的方法，其中，根据所述写入请求消息将所述待缓存数据缓存至芯片的外部缓存中包括：按照第一预定时序信号将所述待缓存数据缓存至所述外部缓存中；和/或，根据所述读取请求消息从所述外部缓存中读取所述指定数据包括：按照第二预定时序信号从所述外部缓存中读取所述指定数据。
  6. 一种数据缓存处理装置，所述装置包括：
    第一接收模块，设置为接收写入待缓存数据的写入请求消息；
    缓存模块，设置为根据所述写入请求消息将所述待缓存数据缓存至芯片的外部缓存中。
  7. 根据权利要求6所述的装置，其中，所述装置还包括：
    第二接收模块，设置为接收读取所述外部缓存中的指定数据的读取请求消息；
    读取模块，设置为根据所述读取请求消息从所述外部缓存中读取所述指定数据。
  8. 根据权利要求6所述的装置，其中，所述缓存模块包括：
    获取单元，设置为获取所述外部缓存中当前缓存的数据的缓存状态信息；
    分配单元，设置为根据所述缓存状态信息为所述待缓存数据分配缓存空间；
    缓存单元，设置为将所述待缓存数据缓存至所述缓存空间中。
  9. 根据权利要求7所述的装置，其中，所述装置还包括：
    对比模块，设置为将所述待缓存数据与读取的数据进行对比，在对比结果一致的情况下，确定所述外部缓存的状态为正常状态，其中，所述读取的数据是与所述待缓存数据对应的数据。
  10. 根据权利要求6至9中任一项所述的装置，其中，还包括：
    所述缓存模块，设置为按照第一预定时序信号将所述待缓存数据缓存至所述外部缓存中；和/或，所述读取模块，设置为按照第二预定时序信号从所述外部缓存中读取所述指定数据。
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