WO2016197766A1 - Method for manufacturing nanowire - Google Patents

Method for manufacturing nanowire Download PDF

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Publication number
WO2016197766A1
WO2016197766A1 PCT/CN2016/081236 CN2016081236W WO2016197766A1 WO 2016197766 A1 WO2016197766 A1 WO 2016197766A1 CN 2016081236 W CN2016081236 W CN 2016081236W WO 2016197766 A1 WO2016197766 A1 WO 2016197766A1
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WO
WIPO (PCT)
Prior art keywords
spacer
substrate
sacrificial
outer surfaces
hard mask
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PCT/CN2016/081236
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French (fr)
Chinese (zh)
Inventor
杨喜超
吴昊
赵静
张臣雄
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华为技术有限公司
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Publication of WO2016197766A1 publication Critical patent/WO2016197766A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02603—Nanowires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor

Definitions

  • the present invention relates to the field of semiconductor device design and fabrication, and more particularly to a method of fabricating nanowires.
  • transistor sizes have shrunk, resulting in improvements in speed, integration, power, and cost.
  • the size of the transistor approaches the physical limit, the power density of the chip increases, and it becomes a bottleneck limiting the evolution of the semiconductor process.
  • the reasons include: (1) the transistor supply voltage cannot be reduced like a critical size; (2) the device is short. The leakage current caused by the channel effect or the like increases.
  • the integration of the device gradually evolved from a planar single-gate MOSFET (Metal Oxide Semiconductor Field Effect Transistor) to a stereo double-gate or triple-gate FinFET (Fin Field).
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • Nanowires are the basic unit of future micro-nano electronics construction circuits. Planar nanowires require more time and cost to assemble into functional circuits, while vertical nanowires can reduce device fabrication and assembly costs, and device architectures want to extend in three dimensions for higher density integration.
  • the chemical preparation method of silicon nanowires mainly includes VLS (Vapor-liquid-solid) CVD (Chemical Vapor Deposition) growth method.
  • the chemical method can grow a large number of vertical single crystal nanowires on a silicon substrate, but the prepared nanowires have uniformity (nanowire diameter, nanowire sidewall roughness, etc.), controllability (nanowire pitch, There are defects in the height of the nanowires, etc., and only the nanowires of a specific region can be screened for transistor fabrication, which cannot meet the high uniformity requirement of the large-scale integrated circuit for the substrate, and the chip-level functional circuit integration and assembly cannot be performed. Therefore, it is not suitable for the application of large-scale integration of micro-nanoelectronics in the future.
  • the industry also uses lithography to prepare silicon nanowires. That is, a hard mask of silicon nanowires is formed on the surface of the single crystal silicon substrate by photolithography, and then the substrate is etched by etching to form a silicon nanowire structure, but due to limitations of lithography precision, nanowires are required. A cutting or stress limiting oxidation process is performed to reduce the diameter of the nanowires.
  • This preparation method is limited by lithography precision and volatility. Specifically, (1) the precision of the lithography technique limits the diameter of the nanowire, and the diameter distribution is tens of nanometers or even hundreds of nanometers, which is a "thick nanowire".
  • Embodiments of the present invention provide a method for fabricating nanowires, which can produce nanowires with high uniformity, low critical dimension jitter, and high process stability.
  • a first aspect of the embodiments of the present invention provides a method for fabricating a nanowire, including:
  • first sacrificial shape of a predetermined template shape on the surface of the substrate, the first sacrificial body being a solid and comprising M outer surfaces perpendicular to the substrate, the M being greater than 1;
  • N outer surfaces according to a predetermined rule in the outer surfaces perpendicular to the substrate for providing a template for growth of the first spacer, the N being greater than 1 and less than or equal to M;
  • the etched portion of the substrate with a filler such that the filled substrate is not etched
  • the shape of the substrate is the same, the filler and the substrate can be etched by the same predetermined etching material;
  • Y Selecting Y outer surfaces according to a predetermined rule in the X outer surfaces perpendicular to the filled substrate for providing a template for growth of the second spacer, the Y being greater than 1 and less than or equal to X;
  • the Y outer surfaces of the two sacrificial bodies respectively form a predetermined intersection angle with each of the semiconductor fins of the first group of semiconductor fins;
  • the filler is removed to obtain nanowires.
  • the substrate comprises a bulk silicon substrate, an SOI substrate, a silicon germanium substrate, and a tri-five material substrate. Or a plurality of semiconductor material thin films stack any one of the semiconductor substrates.
  • the depositing a preset template shape on the surface of the substrate include:
  • a first sacrificial film is deposited on the surface of the substrate, and the first sacrificial film is defined as a first sacrificial shape of a predetermined template shape by photolithography and etching techniques.
  • a second sacrifice for depositing a predetermined template shape on the surface of the filled substrate includes:
  • a second sacrificial film is deposited on the surface of the filled substrate, and the second sacrificial film is defined by a photolithography and etching technique as a second sacrificial of a predetermined template shape.
  • the depositing the first spacers of the predetermined thickness along the N outer surfaces of the first sacrificial includes:
  • first spacer film Depositing a first spacer film of a predetermined thickness along the N outer surfaces of the first sacrificial, the thickness of the first spacer film being used to define a width of the first set of semiconductor fins such that The width of the first set of semiconductor fins is equal to the thickness of the first spacer film;
  • the first spacer film is etched by an anisotropic etching technique to form a first spacer of a predetermined thickness.
  • the depositing the second spacers along the Y outer surfaces of the second sacrificial by the predetermined thickness comprises:
  • the second spacer film is etched by an anisotropic etching technique to form a second spacer of a predetermined thickness.
  • the method further includes:
  • the filled substrate is polished to expose the top of the first set of semiconductor fins.
  • the first aspect of the embodiment of the present invention the first implementation manner of the first aspect, the second implementation manner of the first aspect, the third implementation manner of the first aspect, and the fourth implementation manner of the first aspect, A fifth implementation manner of the first aspect, and a sixth implementation manner of the first aspect,
  • the material of the first sacrificial material includes any one of polysilicon, alpha silicon, and photoresist.
  • the first aspect of the embodiment of the present invention the first implementation manner of the first aspect, the second implementation manner of the first aspect, the third implementation manner of the first aspect, and the fourth implementation manner of the first aspect, In a fifth implementation manner of the first aspect, a sixth implementation manner of the first aspect, and any one of the seven implementation manners of the first aspect, in an eighth implementation manner of the first aspect of the embodiments of the present disclosure,
  • the material of the second sacrificial material includes any one of polysilicon, alpha silicon, and photoresist.
  • the first aspect of the embodiment of the present invention the first implementation manner of the first aspect, the second implementation manner of the first aspect, the third implementation manner of the first aspect, and the fourth implementation manner of the first aspect,
  • the fifth implementation manner of the first aspect, the sixth implementation manner of the first aspect, the seventh implementation manner of the first aspect, and the eighth implementation manner of the first aspect are the first embodiment of the present invention.
  • the first spacer is made of at least one of silicon nitride, silicon dioxide, titanium nitride, tantalum nitride, or other etching resistant material.
  • the second spacer is made of silicon nitride, silicon dioxide, titanium nitride, tantalum nitride or other anti-etching material. At least one of the materials.
  • the filler includes bulk silicon, SOI, silicon germanium, three-five materials, or more Any of a variety of semiconductor material film stack materials.
  • a second aspect of the embodiments of the present invention provides a method for fabricating a nanowire, including:
  • first sacrificial shape of a predetermined template shape on the surface of the hard mask layer, the first sacrificial body being solid and including M outer surfaces perpendicular to the substrate, the M being greater than 1;
  • N Selecting N outer surfaces according to a predetermined rule in the outer surfaces perpendicular to the hard mask layer for providing a template for growth of the first spacer, the N being greater than 1 and less than or equal to M;
  • Y outer surfaces are selected in accordance with a predetermined rule in the outer surfaces perpendicular to the filled hard mask layer for providing a template for growth of the second spacer, the Y being greater than 1 and less than or equal to X
  • the Y outer surfaces of the second sacrificial body respectively form a predetermined intersection angle with each of the semiconductor fins of the first group of semiconductor fins;
  • the hard mask nanowires are removed to obtain semiconductor nanowires.
  • the hard mask layer is made of silicon nitride, silicon dioxide, titanium nitride, tantalum nitride or the like. At least one of his etch resistant materials;
  • the material of the hard mask layer is different from that of the first spacer and the second spacer.
  • Embodiments of the present invention provide a method of fabricating a nanowire, comprising: disposing a substrate; depositing, on a surface of the substrate, a first sacrifice for growing a predetermined template shape, the first sacrificial being an entity and including M An outer surface perpendicular to the substrate, the M being greater than 1; selecting N outer surfaces in accordance with a predetermined rule in the outer surfaces perpendicular to the substrate for providing growth of the first spacer a template, the N is greater than 1 and less than or equal to M; depositing a first spacer of a predetermined thickness along the N outer surfaces of the first sacrificial, the first spacer of the predetermined thickness is still under Determining the first sacrificial material; anisotropically etching the substrate with the first spacer of the predetermined thickness as a mask; removing the first spacer of the predetermined thickness, Obtaining a first set of semiconductor fins; filling a portion of the substrate etched with a filler such that the filled substrate
  • the method of forming a spacer by using a sacrificial material as a template, and etching the substrate by using the spacer as a mask to generate a nanowire breaks through the prior art by directly performing etching limitation by photolithography technology, and can be fabricated. Nanowires with high uniformity, low critical dimension jitter, and high process stability.
  • FIG. 1 is a schematic view showing an embodiment of fabricating a nanowire according to an embodiment of the present invention
  • FIG. 2 is a partial schematic view showing another embodiment of fabricating a nanowire according to an embodiment of the present invention.
  • FIG. 3 is another partial schematic view showing another embodiment of fabricating a nanowire according to an embodiment of the present invention.
  • FIG. 4 is a schematic view showing another embodiment of fabricating a nanowire according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of an embodiment including a hard mask in fabricating a nanowire according to an embodiment of the present invention
  • FIG. 6 is a schematic diagram of an embodiment of fabricating a semiconductor nanowire with hard mask nanowires in a nanowire fabricated in an embodiment of the invention.
  • Embodiments of the present invention provide a method of fabricating nanowires for fabricating nanowires having high uniformity, low critical dimension jitter, and high process stability.
  • an embodiment of a method for fabricating nanowires in an embodiment of the present invention includes the following steps:
  • the first sacrificial body is a solid and includes M outer surfaces perpendicular to the substrate, the M is greater than 1;
  • the present invention etches the substrate by using the first spacer as a mask, but the thickness of the first spacer directly affects the first group generated by etching the substrate.
  • the width of the semiconductor fins also affects the size of the final nanowires. Therefore, before the first spacers are disposed, a first sacrificial growth of a predetermined template shape is deposited on the upper surface of the substrate for deposition.
  • the first spacer provides a template.
  • the substrate may be a regular-shaped entity, such as a rectangular parallelepiped, a cube, a triangle, etc.; alternatively, the first sacrifice may be a regular-shaped entity, such as a rectangular parallelepiped, a cube, a triangle, or the like;
  • the first sacrificial body includes M outer surfaces perpendicular to the substrate, the M being greater than 1, since an outer surface of the first sacrificial perpendicular to the substrate is A method for generating a first spacer, and anisotropically etching the substrate by using the first spacer as a mask to obtain a semiconductor fin, that is, in the embodiment of the invention, a plurality of semiconductor fins can be produced. article.
  • the first sacrifice in the embodiment of the present invention may be a solid cuboid.
  • the N outer surfaces are selected according to a predetermined rule for providing a template for the growth of the first spacer, the N is greater than 1 and less than or equal to M;
  • the first sacrificial material may have a plurality of outer surfaces perpendicular to the substrate, such as if the first sacrificial body is a rectangular parallelepiped, there may be four outer surfaces perpendicular to the substrate;
  • N outer surfaces need to be selected from the M outer surfaces according to a preset rule, and the preset rule includes that the first sacrificial bodies are parallel and lengthwise.
  • the longest outer surface perpendicular to the substrate such as the two parallel outer surfaces formed by the height and length of the cuboid from the cuboid.
  • the thickness of the first spacer is a thickness set according to actual application requirements, because when the substrate is etched, the first spacer of the predetermined thickness needs to be etched as a mask to generate a semiconductor fin, so The thickness of the first spacer then defines the width of the resulting semiconductor fin. Since the first spacer is for providing a mask for etching the substrate, the first spacer is located above the substrate.
  • the substrate needs to be etched by using the first spacer as a mask.
  • the first sacrificial material needs to be removed to facilitate etching the substrate.
  • the depth of the etching determines the height of the obtained semiconductor fin, and also determines the height of the final nanowire, so the depth of etching the substrate needs to be based on The actual needs are decided, and there is no limit here.
  • the first set of semiconductor fins When the first set of semiconductor fins are generated, a second set of semiconductor fins needs to be formed to finally form the nanowires, so the first spacer of the predetermined thickness needs to be removed before the second set of semiconductor fins are fabricated.
  • the strip formed is the first set of semiconductor fins.
  • the embodiment of the present invention also needs to grow the second sacrificial material and the second spacer on the first group of semiconductor fins, so it is required to use A filler fills the portion of the substrate that is etched to facilitate deposition of the second sacrificial and the second spacer.
  • the filled substrate has the same shape as the substrate to be etched.
  • the filler and the substrate can be etched by the same predetermined etching material, and the filler is the same or similar to the material of the substrate, for example, the same silicon material, thus avoiding When the filler is etched simultaneously with the substrate, the fluctuation is large and the etching effect is affected.
  • the second victim may be a regular shaped entity, such as a rectangular parallelepiped, a cube, a triangle, or the like.
  • the second victim includes X outer surfaces perpendicular to the substrate. a surface, the X is greater than 1, since an outer surface of the second sacrificial perpendicular to the substrate is used to generate a second spacer, and the second spacer is used as a mask for anisotropic etching
  • the substrate is obtained to obtain semiconductor fins, that is, in the embodiment of the invention, it is possible to produce a plurality of sets of semiconductor fins.
  • the second sacrificial body may be an entity having the same shape as the first sacrificial object, that is, the X may be equal to the M.
  • the second sacrificial material may have a plurality of outer surfaces perpendicular to the substrate, such as if the second sacrificial body is a rectangular parallelepiped, there may be four outer surfaces perpendicular to the substrate;
  • the Y outer surfaces need to be selected from the X outer surfaces according to a preset rule, and the preset rule includes that the second sacrificial bodies are preferably parallel to each other and length.
  • the longest outer surface perpendicular to the substrate such as from a cuboid
  • the two parallel outer surfaces formed by the height and length of the cuboid are selected.
  • the Y and the N may be equal, and the Y outer surfaces selected from the second sacrificial and the N outer surfaces selected from the first sacrificial may both be parallel and The longest outer surface.
  • the second sacrificial is for providing a template for generating the second spacer
  • the second spacer is for etching the filled substrate as a mask to obtain the second group
  • the semiconductor fins only the second set of semiconductor fins intersect with the first set of semiconductor fins to obtain nanowires, so the Y outer surfaces of the second sacrificial respectively
  • Each of the plurality of semiconductor fins is formed with a predetermined crossing angle equal to an angle formed by the second spacer and the first set of semiconductor fins, and the second spacer and the first The angle formed by the group of semiconductor fins determines the cross-sectional shape of the resulting nanowire.
  • the cross section of the finally obtained nanowire is It is a rectangle; otherwise, the resulting nanowire has a parallelogram in cross section.
  • the thickness of the second spacer is a thickness set according to actual application requirements, because etching needs to be performed by using the second spacer as a mask when etching the substrate, thereby generating a second group of semiconductor fins, so The thickness of the two spacers defines the width of the resulting first semiconductor fins and also the size of the resulting nanowires. If the thickness of the first spacer of the predetermined thickness is equal to the thickness of the second spacer of the predetermined thickness, the cross section of the finally formed nanowire is an equilateral quadrilateral. Since the second spacer of the predetermined thickness is for providing a mask for etching the filled substrate, the second spacer of the predetermined thickness is located on the filled substrate Above.
  • the padded substrate needs to be etched by using the second spacer as a mask. At this time, the second sacrifice needs to be removed to facilitate the filling. The subsequent substrate is etched.
  • the depth of the etching determines the height of the semiconductor fins.
  • the degree of the final generation of the nanowire is also determined, so the depth of etching the substrate needs to be determined according to actual needs, which is not limited herein.
  • the height of the second set of semiconductor fins is equal to the height of the first set of semiconductor fins.
  • the semiconductor fin After removing the second spacer, in the resulting second set of semiconductor fins, the semiconductor fin further includes a filler and a substrate.
  • the remaining substrate portions are rendered as nanowires.
  • the number of nanowires obtained last is related to the N outer surfaces of the first selected first sacrificial and the Y outer surfaces of the second sacrificial. Specifically, the number of nanowires obtained is The product of the N and the Y. For example, if N and Y are both 2, the first set of semiconductor fins is one, the second set of semiconductor fins is also one, and finally the obtained nanowires are four.
  • the first sacrificial material is used for providing a template for depositing a first spacer, and the substrate is anisotropically etched by using the first spacer as a mask to obtain a first group of semiconductor fins; a second sacrificial for providing a template for depositing a second spacer, anisotropically etching the filled substrate with the second spacer as a mask; removing the second spacer to obtain a second Grouping semiconductor fins; removing the filler to obtain nanowires.
  • the method of forming a spacer by using a sacrificial material as a template, and etching the substrate by using the spacer as a mask to generate a nanowire breaks through the prior art by directly performing etching limitation by photolithography technology, and can be fabricated. Nanowires with high uniformity, low critical dimension jitter, and high process stability.
  • a spacer is disposed on a substrate, a spacer is disposed on the substrate along the sacrificial, and the substrate is anisotropically etched using the spacer as a mask; in practical applications, the spacer may be grown by thin film deposition. And the anisotropic etching technology is implemented, and the etching of the substrate can be realized by an anisotropic etching technique; as described in detail below with reference to FIG. 2 and FIG. 3, the method for fabricating the nanowire in the embodiment of the present invention Another embodiment includes the following steps:
  • the animal 11 is solid and includes M outer surfaces perpendicular to the substrate 10, the M being greater than 1;
  • the first sacrificial film is defined as a first sacrificial shape of a predetermined template shape by covering the substrate and then using photolithography and etching techniques.
  • the substrate comprises a bulk silicon substrate, an SOI substrate, a silicon germanium substrate, a tri-five material, or a plurality of semiconductor material thin film stacks.
  • the material for forming the first sacrificial film comprises any one of polysilicon, alpha silicon, and photoresist.
  • the N outer surfaces are selected according to a predetermined rule for providing a template for the growth of the first spacer, the N is greater than 1 and less than or equal to M;
  • the first sacrificial material may have a plurality of outer surfaces perpendicular to the substrate, such as if the first sacrificial body is a rectangular parallelepiped, there may be four outer surfaces perpendicular to the substrate;
  • N outer surfaces need to be selected from the M outer surfaces according to a preset rule, and the preset rule includes that the first sacrificial bodies are parallel and lengthwise.
  • the longest outer surface perpendicular to the substrate such as the two parallel outer surfaces formed by the height and length of the cuboid from the cuboid.
  • the material of the first spacer is made of at least one of silicon nitride, silicon dioxide, titanium nitride, tantalum nitride or other etching resistant materials.
  • the first spacer film is etched to form a first spacer 12 of a predetermined thickness by using an anisotropic etching technique, and the substrate has a substrate under the first spacer 12 of the predetermined thickness;
  • the first spacer film etched by the anisotropic etching technique leaves only a spacer in close contact with the first sacrificial film.
  • the first spacer film is a thickness set according to actual application requirements, because the first spacer of the predetermined thickness needs to be etched as a mask when etching the substrate, thereby generating the first group of semiconductor fins. , so the thickness of the first spacer film defines the generated semiconductor fins
  • the width is also the width of the resulting semiconductor nanowires.
  • the substrate needs to be etched by using the first spacer as a mask.
  • the first sacrificial material needs to be removed to facilitate etching the substrate.
  • the depth of the etching determines the height of the obtained semiconductor fin, and also determines the height of the final nanowire, so the depth of etching the substrate needs to be based on The actual needs are decided, and there is no limit here.
  • the first spacer 12 of the predetermined thickness is removed, to obtain a first group of semiconductor fins 13;
  • the first set of semiconductor fins When the first set of semiconductor fins are generated, a second set of semiconductor fins needs to be formed to finally form the nanowires, so the first spacer of the predetermined thickness needs to be removed before the second set of semiconductor fins are fabricated.
  • the formed strip is the first set of semiconductor fins.
  • the embodiment of the present invention also needs to grow the second sacrificial material and the second spacer on the first group of semiconductor fins, so it is required to use A filler fills the portion of the substrate that is etched to facilitate deposition of the second sacrificial and the second spacer.
  • the filled substrate has the same shape as the substrate to be etched.
  • the filler and the substrate can be etched by the same predetermined etching material, and the filler is the same or similar to the material of the substrate, for example, the same silicon material, thus avoiding When the filler is etched simultaneously with the substrate, the fluctuation is large and the etching effect is affected.
  • the surface of the substrate to be etched is filled with a filler, the surface of the filled substrate may be bumped or concealed by the first set of semiconductor fins, thereby affecting subsequent implantation on the filled substrate.
  • a second sacrificial film is deposited and deposited, so the filled substrate can be polished first such that the tops of the first set of semiconductor fins are exposed.
  • the second sacrificial 16 is a solid and includes X outer surfaces perpendicular to the filled substrate, the X being greater than 1;
  • the surface of the filled substrate is not capable of directly depositing a second sacrificial growth of the predetermined template shape
  • first depositing a second sacrificial film on the surface of the filled substrate is deposited.
  • the second sacrificial film is completely covered by the substrate, and the second sacrificial film is defined as a second sacrificial shape of a predetermined template shape by photolithography and etching techniques.
  • the second sacrificial is for providing a template for generating the second spacer
  • the second spacer is for etching the filled substrate as a mask to obtain the second group
  • the semiconductor fins only the second set of semiconductor fins intersect with the first set of semiconductor fins to obtain nanowires, so the Y outer surfaces of the second sacrificial respectively
  • Each of the plurality of semiconductor fins is formed with a predetermined crossing angle equal to an angle formed by the second spacer and the first set of semiconductor fins, and the second spacer and the first The angle formed by the group of semiconductor fins determines the cross-sectional shape of the resulting nanowire.
  • the cross section of the finally obtained nanowire is It is a rectangle; otherwise, the resulting nanowire has a parallelogram in cross section.
  • the second spacer is made of at least one of silicon nitride, silicon dioxide, titanium nitride, tantalum nitride or other etching resistant materials.
  • the second spacer film is etched by using an anisotropic etching technique to form a second spacer 17 of a predetermined thickness, and the filled spacer is still under the second spacer of the predetermined thickness. bottom;
  • the thickness of the second spacer is a thickness set according to actual application requirements, because the second spacer of the predetermined thickness needs to be etched as a mask when etching the substrate, thereby generating a second group of semiconductor fins.
  • the strip so the thickness of the second spacer defines the width of the generated first semiconductor fin, which is also the size of the final nanowire. If the thickness of the first spacer is equal to the thickness of the second spacer, the cross section of the finally formed nanowire is an equilateral quadrilateral.
  • the second sacrificial film is made of any one of polysilicon, alpha silicon, and photoresist.
  • the filled substrate needs to be etched by using the second spacer as a mask. At this time, the second sacrificial film needs to be removed to facilitate the The filled substrate is etched.
  • the depth of the etching determines the height of the semiconductor fins, and also determines the height of the final semiconductor nanowires, so the depth of etching the substrate needs to be according to actual needs. To decide, there is no limit here.
  • the height of the second set of semiconductor fins is equal to the height of the first set of semiconductor fins.
  • the semiconductor fin After removing the second spacer of the predetermined thickness, in the obtained second group of semiconductor fins, the semiconductor fin further includes a filler and a substrate.
  • the remaining substrate portions are rendered as nanowires.
  • the number of nanowires obtained last is related to the N outer surfaces of the first selected first sacrificial and the Y outer surfaces of the second sacrificial. Specifically, the number of nanowires obtained is The product of the N and the Y. For example, if N and Y are both 2, the first set of semiconductor fins is one, the second set of semiconductor fins is also one, and finally the obtained nanowires are four.
  • the substrate is etched by photolithography, so that the semiconductor fins and the nanowires generated by the etching are finer.
  • another embodiment of a method of fabricating nanowires in an embodiment of the present invention includes the following step:
  • the method described in the above embodiments is to deposit a first set of semiconductor fins by depositing a first sacrificial material, a first spacer on a semiconductor substrate, and depositing a second sacrificial growth on the filled semiconductor substrate. And the second spacer obtains the second group of semiconductor fins; however, when the etching or the spacer is removed multiple times, the semiconductor substrate may be damaged during the operation, so that the obtained semiconductor nanowires are not Uniform or not meeting practical requirements.
  • a growth hard mask layer is first deposited on the semiconductor substrate, so that subsequent etching, removal, and the like are performed on the hard mask layer, thereby obtaining a hard mask nanowire.
  • the semiconductor is etched using a hard mask nanowire as a mask to obtain a semiconductor nanowire which is uniform and requires symbolic use.
  • a hard mask layer 21 is deposited on the semiconductor substrate 22 as shown in FIG.
  • the invention overcomes the limitation of lithography precision by etching the hard mask layer by using the first spacer as a mask, however, since the thickness of the first spacer directly affects the etching generated by the hard mask layer
  • the width of the first set of semiconductor fins also affects the size of the final generated nanowire, so before the first spacer is disposed, the first sacrificial growth of the predetermined template shape needs to be deposited on the surface of the hard mask layer. And for providing a template for depositing the first spacer.
  • the hard mask layer may be a regular shape entity, such as a rectangular parallelepiped, a cube, a triangle, etc.; optionally, the first sacrifice may be a regular shaped entity, such as a rectangular parallelepiped, a cube, a triangle.
  • the first sacrificial body includes M outer surfaces perpendicular to the hard mask layer, and the M is greater than 1, due to the first sacrificial and the hard mask The vertical outer surface of the layer is used to generate a first spacer, and the hard mask layer is anisotropically etched by using the first spacer as a mask to obtain a semiconductor fin, that is, in the embodiment of the present invention It can realize the production of multiple sets of semiconductor fins.
  • the first sacrifice in the embodiment of the present invention may be a solid cuboid.
  • N is greater than 1 and less than or equal to M;
  • the first sacrificial material may have a plurality of outer surfaces perpendicular to the hard mask layer, such as If the first sacrificial body is a rectangular parallelepiped, there may be four outer surfaces perpendicular to the hard mask layer; in order to simplify the process, it is necessary to select N outer surfaces from the M outer surfaces of the first sacrificial material, Used to provide a template for the growth of the first spacer. In order to facilitate the etching of the subsequent steps, the N outer surfaces need to be selected from the M outer surfaces according to a preset rule, and the preset rule includes that the first sacrificial bodies are parallel and lengthwise. The longest outer surface perpendicular to the hard mask layer, such as two parallel outer surfaces formed by selecting the height and length of the cuboid from the cuboid.
  • the thickness of the first spacer is a thickness set according to actual application requirements, because when the hard mask layer is etched, it is required to etch with the first spacer of the predetermined thickness as a mask to generate a semiconductor fin. Therefore, the thickness of the first spacer defines the width of the resulting semiconductor fin. Since the first spacer is for providing a mask for etching the hard mask layer, the first spacer is located above the hard mask layer.
  • the hard mask layer needs to be etched by using the first spacer as a mask. At this time, the first sacrificial material needs to be removed to facilitate the hard mask layer. Etching is performed.
  • the depth of the etching determines the height of the obtained semiconductor fin, and determines the height of the final nanowire, so the hard mask layer is etched.
  • the depth should be determined according to actual needs, and is not limited here.
  • the first set of semiconductor fins When the first set of semiconductor fins are generated, a second set of semiconductor fins needs to be formed to finally form the nanowires, so the first spacer of the predetermined thickness needs to be removed before the second set of semiconductor fins are fabricated.
  • the strip formed is the first set of semiconductor fins.
  • the mold layer can be etched by the same predetermined etching material
  • the present invention also needs to grow the second sacrificial layer and the second spacer on the first set of semiconductor fins, so that the portion of the hard mask layer to be etched needs to be filled with a filler to facilitate deposition and growth of the second sacrifice. And the second spacer.
  • the filled hard mask layer has the same shape as the hard mask layer to be etched.
  • the filler and the hard mask layer can be etched by the same predetermined etching material, and the filler is the same or similar to the material of the hard mask layer, for example, the same silicon material. In this way, it is avoided that the etching is caused when the filler and the hard mask layer are simultaneously etched, and the etching effect is affected.
  • the second victim may be a regular shaped entity, such as a rectangular parallelepiped, a cube, a triangle, or the like.
  • the second victim includes X perpendicular to the hard mask layer.
  • the outer surface, the X is greater than 1, since the outer surface of the second sacrificial perpendicular to the hard mask layer is for generating a second spacer, and the second spacer is used as a mask
  • the second sacrificial body may be an entity having the same shape as the first sacrificial object, that is, the X may be equal to the M.
  • the second sacrificial layer may have a plurality of outer surfaces perpendicular to the hard mask layer, such as if the second sacrificial body is a rectangular parallelepiped, there may be four outer surfaces perpendicular to the hard mask layer.
  • the Y outer surfaces need to be selected from the X outer surfaces according to a preset rule, and the preset rule includes that the second sacrificial bodies are preferably parallel to each other and length.
  • the longest outer surface perpendicular to the hard mask layer such as two parallel outer surfaces formed by selecting the height and length of the cuboid from the cuboid.
  • the Y and the N may be equal, and the Y outer surfaces selected from the second sacrifice are
  • the N outer surfaces selected from the first sacrificial body may all be parallel and the longest outer surface.
  • the second spacer is used to provide a template for forming a second spacer, and the second spacer is used for etching the filled hard mask layer as a mask.
  • the second set of semiconductor fins In the two sets of semiconductor fins, only the second set of semiconductor fins intersect with the first set of semiconductor fins to obtain nanowires, so the Y outer surfaces of the second sacrificial body are respectively.
  • Each of the semiconductor fins of the first set of semiconductor fins is formed with a predetermined crossing angle, which is equivalent to an angle formed by the second spacer and the first set of semiconductor fins, and the second spacer is The angle formed by the first set of semiconductor fins determines the cross-sectional shape of the resulting nanowire.
  • the cross section of the finally obtained nanowire is It is a rectangle; otherwise, the resulting nanowire has a parallelogram in cross section.
  • the thickness of the second spacer is a thickness set according to actual application requirements, because etching needs to be performed by using the second spacer as a mask when etching the hard mask layer, thereby generating a second group of semiconductor fins. Therefore, the thickness of the second spacer defines the width of the generated first semiconductor fin, which is also the size of the final nanowire. If the thickness of the first spacer of the predetermined thickness is equal to the thickness of the second spacer of the predetermined thickness, the cross section of the finally formed nanowire is an equilateral quadrilateral. Since the second spacer of the predetermined thickness is used to provide a mask for etching the filled hard mask layer, the second spacer of the predetermined thickness is located after the filling Above the hard mask layer.
  • the padded hard mask layer needs to be etched by using the second spacer as a mask. At this time, the second sacrifice needs to be removed to facilitate the The filled hard mask layer is etched.
  • the depth of the etching determines the height of the semiconductor fins, and also determines the height of the final nanowires, so the depth of the hard mask layer needs to be etched. According to actual needs, there is no limit here.
  • the height of the second set of semiconductor fins is The first set of semiconductor fins are of equal height.
  • the semiconductor fin After removing the second spacer, in the obtained second group of semiconductor fins, the semiconductor fin further includes a filler and a hard mask layer.
  • the remaining hard mask layer portions are rendered as hard mask nanowires.
  • the number of the last obtained hard mask nanowires is related to the N outer surfaces of the first selected first sacrificial and the Y outer surfaces of the second sacrificial. Specifically, the final hard mask is obtained.
  • the number of mold nanowires is the product of the N and the Y. For example, if N and Y are both 2, the first set of semiconductor fins is one, the second set of semiconductor fins is also one, and finally four hard mask nanowires are obtained.
  • the semiconductor nanowires can be formed by etching the semiconductor substrate with the hard mask as a nanowire.
  • the semiconductor nanowires 24 formed by etching the semiconductor substrate 22 with the hard mask nanowires 23 as a mask are shown in FIG.
  • the hard mask nanowires After etching the semiconductor substrate by using the hard mask nanowire as a mask, the hard mask nanowires need to be removed to obtain semiconductor nanowires.
  • the hard mask layer can be made of at least one of silicon nitride, silicon dioxide, titanium nitride, tantalum nitride or other etch-resistant materials; the hard mask layer The finished material is different from the first spacer and the second spacer.
  • a growth hard mask layer is deposited on the semiconductor substrate, and subsequent etching, filling, and removing operations are performed on the hard mask layer to obtain a hard mask nanometer.
  • the semiconductor substrate is etched using the hard mask nanowire as a mask to obtain a semiconductor nanowire.
  • the hard mask can prevent the semiconductor substrate from being damaged after the process of performing multiple etching, removal, etc., to generate semiconductor nanowires, thereby improving the integrity of the semiconductor nanowire.

Abstract

A method for manufacturing a nanowire comprises: a first victim (11) is deposited and grown on the upper surface of a substrate (10); a first spacer (12) is deposited and grown along a number N of outer surfaces of the first victim (11); the substrate (10) is subjected to anisotropically etching by employing the first spacer (12) as a mask; the first spacer (12) is removed to obtain a first group of semiconductor fin rays (13); the etched part of the substrate is filled with a filler (14); a second victim (16) is deposited and grown on the upper surface of the filled substrate (10); preset cross angles are formed between the a number Y of outer surfaces of the second victim (16) and various semiconductor fin rays (13) in the first group of semiconductor fin rays respectively; a second spacer (17) is deposited and grown along the number Y of outer surfaces of the second victim (16); and the filled substrate (10) is subjected to anisotropically etching by employing the second spacer (17) as the mask, so as to obtain the nanowire (19).

Description

一种制作纳米线的方法Method for making nanowires
本申请要求于2015年6月9日提交中国专利局、申请号为201510312421.2、发明名称为“一种制作纳米线的方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。The present application claims priority to Chinese Patent Application No. 201510312421. filed on Jun. 9, 2015, the entire disclosure of which is incorporated herein by reference. .
技术领域Technical field
本发明涉及半导体器件设计及制造领域，尤其涉及一种制作纳米线的方法。The present invention relates to the field of semiconductor device design and fabrication, and more particularly to a method of fabricating nanowires.
背景技术Background technique
随着半导体制作工艺的演进，晶体管的尺寸逐渐缩减，为芯片带来速度、集成度、功耗以及成本等方面的改善。但随着晶体管的尺寸接近物理极限，芯片的功率密度也随之提高，并且成为限制半导体工艺演进的瓶颈，其原因包括：(1)晶体管供电电压不能像关键尺寸缩减；(2)器件的短沟道效应等引起的泄露电流增加。为了能够继续获得新工艺节点对芯片特性的提升，器件的集成逐渐从平面的单栅MOSFET(Metal Oxide Semiconductor Field Effect Transistor，金氧半场效晶体管)向立体的双栅或者三栅FinFET(Fin Field Effect Transistor，鳍式场效晶体管)变化，并向全栅环绕GAA(Gate all around，环栅结构)的纳米线演进。但高均匀的竖直纳米线的制备在业界尚是个巨大挑战。纳米线是未来微纳电子学构建电路的基本单元。平面纳米线需要消耗较多的时间和成本来组装成功能电路，而竖直纳米线能够降低器件制备和组装成本，并且器件架构想三维方向的延伸利于更高密度的集成。As semiconductor fabrication processes evolve, transistor sizes have shrunk, resulting in improvements in speed, integration, power, and cost. However, as the size of the transistor approaches the physical limit, the power density of the chip increases, and it becomes a bottleneck limiting the evolution of the semiconductor process. The reasons include: (1) the transistor supply voltage cannot be reduced like a critical size; (2) the device is short. The leakage current caused by the channel effect or the like increases. In order to continue to gain new chip characteristics, the integration of the device gradually evolved from a planar single-gate MOSFET (Metal Oxide Semiconductor Field Effect Transistor) to a stereo double-gate or triple-gate FinFET (Fin Field). The Effect Transistor, the FinFET, changes and extends toward the nanowires of the GAA (Gate all around). However, the preparation of highly uniform vertical nanowires is still a huge challenge in the industry. Nanowires are the basic unit of future micro-nano electronics construction circuits. Planar nanowires require more time and cost to assemble into functional circuits, while vertical nanowires can reduce device fabrication and assembly costs, and device architectures want to extend in three dimensions for higher density integration.
硅纳米线的化学制备方法主要有VLS(Vapor-liquid-solid，气相-液相-固相)的CVD(Chemical Vapor Deposition,化学气相沉积)生长方法。该化学方法可以在硅衬底上大量生长竖直的单晶纳米线，但制备出的纳米线在均匀性(纳米线直径、纳米线侧壁粗糙度等)、可控性(纳米线间距、纳米线的高度等)等存在缺陷，只能筛选特定区域的纳米线进行晶体管制备，无法满足大规模集成电路对衬底的高均匀性要求，导致而无法进行芯片级的功能电路集成和组装。因此，不适用于未来微纳电子学大规模集成的应用。 The chemical preparation method of silicon nanowires mainly includes VLS (Vapor-liquid-solid) CVD (Chemical Vapor Deposition) growth method. The chemical method can grow a large number of vertical single crystal nanowires on a silicon substrate, but the prepared nanowires have uniformity (nanowire diameter, nanowire sidewall roughness, etc.), controllability (nanowire pitch, There are defects in the height of the nanowires, etc., and only the nanowires of a specific region can be screened for transistor fabrication, which cannot meet the high uniformity requirement of the large-scale integrated circuit for the substrate, and the chip-level functional circuit integration and assembly cannot be performed. Therefore, it is not suitable for the application of large-scale integration of micro-nanoelectronics in the future.
业界也采用光刻技术制备硅纳米线。即对单晶硅衬底表面利用光刻技术形成硅纳米线的硬掩模，然后利用刻蚀技术对衬底进行刻蚀形成硅纳米线结构，但由于光刻精度的限制，需要对纳米线进行裁剪或者应力限制的氧化工艺来减小纳米线的直径。这种制备方法受到光刻精度和波动性的限制，具体而言：(1)光刻技术的精度限制了纳米线的直径，直径分布为几十纳米甚至几百纳米，为“粗纳米线”，达不到GAA晶体管耗尽沟道的需求；(2)光刻波动性的限制，即由于光刻技术工作在极限附近，对图形的定义将不能精确控制，导致制作的纳米线硬掩模之间存在很大的波动性，进而使得以硬掩模为掩模刻蚀而成的纳米线之间也存在很大的波动性，达不到集成电路的均匀性要求。光刻技术和刻蚀技术直接制备的“粗纳米线”需要进行进一步裁剪，而这无疑会增加工艺的复杂度，并且会在工艺过程中进一步引入新的工艺波动。因此，这种纳米线制备技术存在工艺复杂、波动大、以及受到光刻技术限制的缺陷，不能满足未来微纳电子学大规模集成的需求。The industry also uses lithography to prepare silicon nanowires. That is, a hard mask of silicon nanowires is formed on the surface of the single crystal silicon substrate by photolithography, and then the substrate is etched by etching to form a silicon nanowire structure, but due to limitations of lithography precision, nanowires are required. A cutting or stress limiting oxidation process is performed to reduce the diameter of the nanowires. This preparation method is limited by lithography precision and volatility. Specifically, (1) the precision of the lithography technique limits the diameter of the nanowire, and the diameter distribution is tens of nanometers or even hundreds of nanometers, which is a "thick nanowire". The requirement for the depletion of the channel of the GAA transistor is not achieved; (2) the limitation of lithography volatility, that is, since the lithography technique works near the limit, the definition of the pattern cannot be precisely controlled, resulting in the fabrication of the nanowire hard mask. There is a great volatility between the two, and the nanowires etched by using the hard mask as a mask also have great fluctuations, which cannot meet the uniformity requirements of the integrated circuit. The “thick nanowires” directly prepared by lithography and etching techniques require further cutting, which undoubtedly increases the complexity of the process and introduces new process fluctuations in the process. Therefore, this nanowire preparation technology has the defects of complicated process, large fluctuation, and limited by lithography technology, and cannot meet the needs of large-scale integration of micro-nanoelectronics in the future.
发明内容Summary of the invention
本发明实施例提供了一种制作纳米线的方法，可实现制作出具有高均匀性、低关键尺寸抖动以及高工艺稳定性的纳米线。Embodiments of the present invention provide a method for fabricating nanowires, which can produce nanowires with high uniformity, low critical dimension jitter, and high process stability.
本发明实施例第一方面提供一种制作纳米线的方法，包括：A first aspect of the embodiments of the present invention provides a method for fabricating a nanowire, including:
设置衬底；Setting the substrate;
在所述衬底上表面沉积生长预设模板形状的第一牺牲物，所述第一牺牲物为实体且包括M个与所述衬底垂直的外表面，所述M大于1；Depositing a first sacrificial shape of a predetermined template shape on the surface of the substrate, the first sacrificial body being a solid and comprising M outer surfaces perpendicular to the substrate, the M being greater than 1;
在所述M个与所述衬底垂直的外表面中按照预定规则选择N个外表面用于为第一隔离物的生长提供模板，所述N大于1且小于等于M；Selecting N outer surfaces according to a predetermined rule in the outer surfaces perpendicular to the substrate for providing a template for growth of the first spacer, the N being greater than 1 and less than or equal to M;
沿第一牺牲物的所述N个外表面沉积生长预设厚度的第一隔离物，所述预设厚度的第一隔离物的下方仍有所述衬底；Depositing a first spacer of a predetermined thickness along the N outer surfaces of the first sacrificial, wherein the substrate is still under the first spacer of the predetermined thickness;
移除所述第一牺牲物；Removing the first victim;
以所述预设厚度的第一隔离物为掩模各向异性刻蚀所述衬底；Anisotropically etching the substrate by using the first spacer of the predetermined thickness as a mask;
移除所述预设厚度的第一隔离物，得到第一组半导体鳍条；Removing the first spacer of the predetermined thickness to obtain a first set of semiconductor fins;
使用填充物填充所述衬底被刻蚀的部分，使得被填充后的衬底与未被刻蚀 时的衬底形状一样，所述填充物与所述衬底能够被同种预定刻蚀材料刻蚀；Filling the etched portion of the substrate with a filler such that the filled substrate is not etched The shape of the substrate is the same, the filler and the substrate can be etched by the same predetermined etching material;
在所述被填充后的衬底的上表面沉积生长预设模板形状的第二牺牲物，所述第二牺牲物为实体且包括X个与所述被填充后的衬底垂直的外表面，所述X大于1；Depositing a second sacrificial growth template shape on the upper surface of the filled substrate, the second sacrificial being solid and including X outer surfaces perpendicular to the filled substrate, The X is greater than 1;
在所述X个与所述被填充后的衬底垂直的外表面中按照预定规则选择Y个外表面用于为第二隔离物的生长提供模板，所述Y大于1且小于等于X；第二牺牲物的所述Y个外表面分别与所述第一组半导体鳍条中各个半导体鳍条形成有预设交叉角度；Selecting Y outer surfaces according to a predetermined rule in the X outer surfaces perpendicular to the filled substrate for providing a template for growth of the second spacer, the Y being greater than 1 and less than or equal to X; The Y outer surfaces of the two sacrificial bodies respectively form a predetermined intersection angle with each of the semiconductor fins of the first group of semiconductor fins;
沿第二牺牲物的所述Y个外表面沉积生长预设厚度的第二隔离物，所述预设厚度的第二隔离物的下方仍有所述被填充后的衬底；Depositing a second spacer of a predetermined thickness along the Y outer surfaces of the second sacrificial, wherein the filled substrate is still under the second spacer of the predetermined thickness;
移除所述第二牺牲物；Removing the second victim;
以所述预设厚度的第二隔离物为掩模各向异性刻蚀所述被填充后的衬底；Anisotropically etching the filled substrate by using the second spacer of the predetermined thickness as a mask;
移除所述预设厚度的第二隔离物，得到第二组半导体鳍条；Removing the second spacer of the predetermined thickness to obtain a second set of semiconductor fins;
移除所述填充物，得到纳米线。The filler is removed to obtain nanowires.
结合本发明实施例第一方面，在本发明实施例第一方面的第一种实现方式中，所述衬底包括体硅衬底、SOI衬底、锗硅衬底、三五族材料衬底、或者多种半导体材料薄膜堆叠衬底其中任意一种半导体衬底。With reference to the first aspect of the embodiments of the present invention, in a first implementation manner of the first aspect of the embodiments of the present invention, the substrate comprises a bulk silicon substrate, an SOI substrate, a silicon germanium substrate, and a tri-five material substrate. Or a plurality of semiconductor material thin films stack any one of the semiconductor substrates.
结合本发明实施例第一方面或第一方面的第一种实现方式，在本发明实施例第一方面的第二种实现方式中，所述在所述衬底上表面沉积生长预设模板形状的第一牺牲物包括：In conjunction with the first aspect of the embodiment of the present invention or the first implementation of the first aspect, in a second implementation manner of the first aspect of the embodiment of the present invention, the depositing a preset template shape on the surface of the substrate The first sacrifices include:
在所述衬底上表面沉积生长第一牺牲物薄膜，利用光刻和刻蚀技术将所述第一牺牲物薄膜定义成预设模板形状的第一牺牲物。A first sacrificial film is deposited on the surface of the substrate, and the first sacrificial film is defined as a first sacrificial shape of a predetermined template shape by photolithography and etching techniques.
结合本发明实施例第一方面、第一方面的第一种实现方式以及第一方面的第二种实现方式中任意一种，在本发明实施例第一方面的第三种实现方式中，所述在被填充后的衬底上表面沉积生长预设模板形状的第二牺牲物包括：With reference to the first aspect of the embodiment of the present invention, the first implementation manner of the first aspect, and the second implementation manner of the first aspect, in a third implementation manner of the first aspect of the embodiment of the present invention, A second sacrifice for depositing a predetermined template shape on the surface of the filled substrate includes:
在所述被填充后的衬底上表面沉积生长第二牺牲物薄膜，利用光刻和刻蚀技术将所述第二牺牲物薄膜定义成预设模板形状的第二牺牲物。A second sacrificial film is deposited on the surface of the filled substrate, and the second sacrificial film is defined by a photolithography and etching technique as a second sacrificial of a predetermined template shape.
结合本发明实施例第一方面、第一方面的第一种实现方式、第一方面的第二种实现方式以及第一方面的第三种实现方式中任意一种，在本发明实施例第 一方面的第四种实现方式中，所述沿第一牺牲物的所述N个外表面沉积生长预设厚度的第一隔离物包括：With reference to the first aspect of the embodiments of the present invention, the first implementation manner of the first aspect, the second implementation manner of the first aspect, and the third implementation manner of the first aspect, in the embodiment of the present invention In a fourth implementation manner of the aspect, the depositing the first spacers of the predetermined thickness along the N outer surfaces of the first sacrificial includes:
沿第一牺牲物的所述N个外表面沉积生长预设厚度的第一隔离物薄膜，所述第一隔离物薄膜的厚度用于限定所述第一组半导体鳍条的宽度，以使得所述第一组半导体鳍条的宽度与所述第一隔离物薄膜的厚度相等；Depositing a first spacer film of a predetermined thickness along the N outer surfaces of the first sacrificial, the thickness of the first spacer film being used to define a width of the first set of semiconductor fins such that The width of the first set of semiconductor fins is equal to the thickness of the first spacer film;
利用各向异性刻蚀技术将所述第一隔离物薄膜刻蚀形成预设厚度的第一隔离物。The first spacer film is etched by an anisotropic etching technique to form a first spacer of a predetermined thickness.
结合本发明实施例第一方面、第一方面的第一种实现方式、第一方面的第二种实现方式、第一方面的第三种实现方式以及第一方面的第四种实现方式中任意一种，在本发明实施例第一方面的第五种实现方式中，所述沿第二牺牲物的所述Y个外表面沉积生长预设厚度的第二隔离物包括：In combination with the first aspect of the embodiment of the present invention, the first implementation manner of the first aspect, the second implementation manner of the first aspect, the third implementation manner of the first aspect, and the fourth implementation manner of the first aspect, In a fifth implementation manner of the first aspect of the embodiments of the present invention, the depositing the second spacers along the Y outer surfaces of the second sacrificial by the predetermined thickness comprises:
沿第二牺牲物的所述Y个外表面沉积生长预设厚度的第二隔离物薄膜，所述第二隔离物薄膜的厚度用于限定所述第二组半导体鳍条的宽度，以使得所述第二组半导体鳍条的宽度与所述第一隔离物薄膜的厚度相等；Depositing a second spacer film of a predetermined thickness along the Y outer surfaces of the second sacrificial, the thickness of the second spacer film being used to define a width of the second set of semiconductor fins such that The width of the second set of semiconductor fins is equal to the thickness of the first spacer film;
利用各向异性刻蚀技术将所述第二隔离物薄膜刻蚀形成预设厚度的第二隔离物。The second spacer film is etched by an anisotropic etching technique to form a second spacer of a predetermined thickness.
结合本发明实施例第一方面、第一方面的第一种实现方式、第一方面的第二种实现方式、第一方面的第三种实现方式、第一方面的第四种实现方式以及第一方面的第五种实现方式中任意一种，在本发明实施例第一方面的第六种实现方式中，在所述使用填充物填充所述衬底被刻蚀的部分之后，在所述在被填充后的衬底上表面沉积生长预设模板形状的第二牺牲物之前，所述方法还包括：With reference to the first aspect of the embodiments of the present invention, the first implementation manner of the first aspect, the second implementation manner of the first aspect, the third implementation manner of the first aspect, the fourth implementation manner of the first aspect, and the foregoing In a sixth implementation manner of the first aspect of the present invention, in the sixth implementation manner of the first aspect of the present invention, after the filler is used to fill the etched portion of the substrate, Before depositing a second sacrificial surface of the predetermined template shape on the surface of the filled substrate, the method further includes:
将所述被填充后的衬底抛光，以暴露出所述第一组半导体鳍条的顶部。The filled substrate is polished to expose the top of the first set of semiconductor fins.
结合本发明实施例第一方面、第一方面的第一种实现方式、第一方面的第二种实现方式、第一方面的第三种实现方式、第一方面的第四种实现方式、第一方面的第五种实现方式以及第一方面的第六种实现方式中任意一种，在本发明实施例第一方面的第七种实现方式中，The first aspect of the embodiment of the present invention, the first implementation manner of the first aspect, the second implementation manner of the first aspect, the third implementation manner of the first aspect, and the fourth implementation manner of the first aspect, A fifth implementation manner of the first aspect, and a sixth implementation manner of the first aspect,
所述第一可牺牲物的制成材料包括多晶硅、α硅以及光刻胶其中任意一种。 The material of the first sacrificial material includes any one of polysilicon, alpha silicon, and photoresist.
结合本发明实施例第一方面、第一方面的第一种实现方式、第一方面的第二种实现方式、第一方面的第三种实现方式、第一方面的第四种实现方式、第一方面的第五种实现方式、第一方面的第六种实现方式中以及第一方面的七种实现方式任意一种，在本发明实施例第一方面的第八种实现方式中，所述第二可牺牲物的制成材料包括多晶硅、α硅以及光刻胶其中任意一种。The first aspect of the embodiment of the present invention, the first implementation manner of the first aspect, the second implementation manner of the first aspect, the third implementation manner of the first aspect, and the fourth implementation manner of the first aspect, In a fifth implementation manner of the first aspect, a sixth implementation manner of the first aspect, and any one of the seven implementation manners of the first aspect, in an eighth implementation manner of the first aspect of the embodiments of the present disclosure, The material of the second sacrificial material includes any one of polysilicon, alpha silicon, and photoresist.
结合本发明实施例第一方面、第一方面的第一种实现方式、第一方面的第二种实现方式、第一方面的第三种实现方式、第一方面的第四种实现方式、第一方面的第五种实现方式、第一方面的第六种实现方式中、第一方面的七种实现方式以及第一方面的第八种实现方式中任意一种，在本发明实施例第一方面的第九种实现方式中，所述第一隔离物的制成材料包括氮化硅、二氧化硅、氮化钛、氮化钽或者其他耐刻蚀材料中的至少一种。The first aspect of the embodiment of the present invention, the first implementation manner of the first aspect, the second implementation manner of the first aspect, the third implementation manner of the first aspect, and the fourth implementation manner of the first aspect, The fifth implementation manner of the first aspect, the sixth implementation manner of the first aspect, the seventh implementation manner of the first aspect, and the eighth implementation manner of the first aspect are the first embodiment of the present invention. In a ninth implementation of the aspect, the first spacer is made of at least one of silicon nitride, silicon dioxide, titanium nitride, tantalum nitride, or other etching resistant material.
结合本发明实施例第一方面、第一方面的第一种实现方式、第一方面的第二种实现方式、第一方面的第三种实现方式、第一方面的第四种实现方式、第一方面的第五种实现方式、第一方面的第六种实现方式中、第一方面的七种实现方式、第一方面的第八种实现方式以及第一方面的第九种实现方式中任意一种，在本发明实施例第一方面的第十种实现方式中，所述第二隔离物的制成材料包括氮化硅、二氧化硅、氮化钛、氮化钽或者其他耐刻蚀材料中的至少一种。The first aspect of the embodiment of the present invention, the first implementation manner of the first aspect, the second implementation manner of the first aspect, the third implementation manner of the first aspect, and the fourth implementation manner of the first aspect, Any of the fifth implementation manners of the first aspect, the sixth implementation manner of the first aspect, the seven implementation manners of the first aspect, the eighth implementation manner of the first aspect, and the ninth implementation manner of the first aspect In a tenth implementation manner of the first aspect of the embodiments of the present invention, the second spacer is made of silicon nitride, silicon dioxide, titanium nitride, tantalum nitride or other anti-etching material. At least one of the materials.
结合本发明实施例第一方面、第一方面的第一种实现方式、第一方面的第二种实现方式、第一方面的第三种实现方式、第一方面的第四种实现方式、第一方面的第五种实现方式、第一方面的第六种实现方式中、第一方面的七种实现方式、第一方面的第八种实现方式、第一方面的第九种实现方式以及第一方面的第十种实现方式中任意一种，在本发明实施例第一方面的第十一种实现方式中，所述填充物包括体硅、SOI、锗硅、三五族材料、或者多种半导体材料薄膜堆叠材料其中任意一种。The first aspect of the embodiment of the present invention, the first implementation manner of the first aspect, the second implementation manner of the first aspect, the third implementation manner of the first aspect, and the fourth implementation manner of the first aspect, a fifth implementation manner of the first aspect, a sixth implementation manner of the first aspect, seven implementation manners of the first aspect, an eighth implementation manner of the first aspect, a ninth implementation manner of the first aspect, and a In an eleventh implementation manner of the first aspect of the present invention, the filler includes bulk silicon, SOI, silicon germanium, three-five materials, or more Any of a variety of semiconductor material film stack materials.
本发明实施例第二方面提供一种制作纳米线的方法，包括：A second aspect of the embodiments of the present invention provides a method for fabricating a nanowire, including:
设置半导体衬底；Setting a semiconductor substrate;
在所述半导体衬底上表面沉积生长硬掩模层；Depositing a growth hard mask layer on the surface of the semiconductor substrate;
在所述硬掩模层上表面沉积生长预设模板形状的第一牺牲物，所述第一牺牲物为实体且包括M个与所述衬底垂直的外表面，所述M大于1； Depositing a first sacrificial shape of a predetermined template shape on the surface of the hard mask layer, the first sacrificial body being solid and including M outer surfaces perpendicular to the substrate, the M being greater than 1;
在所述M个与所述硬掩模层垂直的外表面中按照预定规则选择N个外表面用于为第一隔离物的生长提供模板，所述N大于1且小于等于M；Selecting N outer surfaces according to a predetermined rule in the outer surfaces perpendicular to the hard mask layer for providing a template for growth of the first spacer, the N being greater than 1 and less than or equal to M;
沿第一牺牲物的所述N个外表面沉积生长预设厚度的第一隔离物，所述预设厚度的第一隔离物的下方仍有所述半导体衬底；Depositing a first spacer of a predetermined thickness along the N outer surfaces of the first sacrificial, the semiconductor substrate remaining under the first spacer of the predetermined thickness;
移除所述第一牺牲物；Removing the first victim;
以所述预设厚度的第一隔离物为掩模各向异性刻蚀所述硬掩模层；Anisotropically etching the hard mask layer by using the first spacer of the predetermined thickness as a mask;
移除所述预设厚度的第一隔离物，得到第一组半导体鳍条；Removing the first spacer of the predetermined thickness to obtain a first set of semiconductor fins;
使用填充物填充所述硬掩模层被刻蚀的部分，使得被填充后的硬掩模层与未被刻蚀时的硬掩模层形状一样，所述填充物与所述硬掩模层能够被预定刻蚀材料刻蚀；Filling the etched portion of the hard mask layer with a filler such that the filled hard mask layer has the same shape as the hard mask layer when not etched, the filler and the hard mask layer Can be etched by a predetermined etching material;
在所述被填充后的硬掩模层的上表面沉积生长预设模板形状的第二牺牲物，所述第二牺牲物为实体且包括X个与所述被填充后的硬掩模层垂直的外表面，所述X大于1；Depositing a second sacrificial of a predetermined template shape on the upper surface of the filled hard mask layer, the second sacrificial being solid and including X perpendicular to the filled hard mask layer The outer surface, the X is greater than 1;
在所述X个与所述被填充后的硬掩模层垂直的外表面中按照预定规则选择Y个外表面用于为第二隔离物的生长提供模板，所述Y大于1且小于等于X；第二牺牲物的所述Y个外表面分别与所述第一组半导体鳍条中各个半导体鳍条形成有预设交叉角度；Y outer surfaces are selected in accordance with a predetermined rule in the outer surfaces perpendicular to the filled hard mask layer for providing a template for growth of the second spacer, the Y being greater than 1 and less than or equal to X The Y outer surfaces of the second sacrificial body respectively form a predetermined intersection angle with each of the semiconductor fins of the first group of semiconductor fins;
沿第二牺牲物的所述Y个外表面沉积生长预设厚度第二隔离物，所述预设厚度的第二隔离物的下方仍有所述被填充后的衬底；Depositing a predetermined thickness second spacer along the Y outer surfaces of the second sacrificial, wherein the filled substrate is still under the second spacer of the predetermined thickness;
移除所述第二牺牲物；Removing the second victim;
以所述预设厚度的第二隔离物为掩模各向异性刻蚀所述被填充后的硬掩模层；Anisotropically etching the filled hard mask layer by using the second spacer of the predetermined thickness as a mask;
移除所述预设厚度的第二隔离物，得到第二组半导体鳍条；Removing the second spacer of the predetermined thickness to obtain a second set of semiconductor fins;
移除所述填充物，得到硬掩模纳米线；Removing the filler to obtain a hard mask nanowire;
以所述硬掩模纳米线为掩模刻蚀所述半导体衬底；Etching the semiconductor substrate with the hard mask nanowire as a mask;
移除所述硬掩模纳米线，得到半导体纳米线。The hard mask nanowires are removed to obtain semiconductor nanowires.
结合本发明实施例第二方面，在本发明实施例第二方面的第一种实现方式中，With reference to the second aspect of the embodiments of the present invention, in a first implementation manner of the second aspect of the embodiment of the present invention,
所述硬掩模层的制成材料包括氮化硅、二氧化硅、氮化钛、氮化钽或者其 他耐刻蚀材料中的至少一种；The hard mask layer is made of silicon nitride, silicon dioxide, titanium nitride, tantalum nitride or the like. At least one of his etch resistant materials;
所述硬掩模层的制成材料与所述第一隔离物以及所述第二隔离物的制成材料均不同。The material of the hard mask layer is different from that of the first spacer and the second spacer.
本发明实施例提供了一种制作纳米线的方法，包括：设置衬底；在所述衬底上表面沉积生长预设模板形状的第一牺牲物，所述第一牺牲物为实体且包括M个与所述衬底垂直的外表面，所述M大于1；在所述M个与所述衬底垂直的外表面中按照预定规则选择N个外表面用于为第一隔离物的生长提供模板，所述N大于1且小于等于M；沿第一牺牲物的所述N个外表面沉积生长预设厚度的第一隔离物，所述预设厚度的第一隔离物的下方仍有所述衬底；移除所述第一牺牲物；以所述预设厚度的第一隔离物为掩模各向异性刻蚀所述衬底；移除所述预设厚度的第一隔离物，得到第一组半导体鳍条；使用填充物填充所述衬底被刻蚀的部分，使得被填充后的衬底与未被刻蚀时的衬底形状一样，所述填充物与所述衬底能够被预定刻蚀材料刻蚀；在所述被填充后的衬底的上表面沉积生长预设模板形状的第二牺牲物，所述第二牺牲物为实体且包括X个与所述被填充后的衬底垂直的外表面，所述X大于1；在所述X个与所述被填充后的衬底垂直的外表面中按照预定规则选择Y个外表面用于为第二隔离物的生长提供模板，所述Y大于1且小于等于X；第二牺牲物的所述Y个外表面分别与所述第一组半导体鳍条中各个半导体鳍条形成有预设交叉角度；沿第二牺牲物的所述Y个外表面沉积生长预设厚度第二隔离物，所述预设厚度的第二隔离物的下方仍有所述被填充后的衬底；移除所述第二牺牲物；以所述预设厚度的第二隔离物为掩模各向异性刻蚀所述被填充后的衬底；移除所述预设厚度的第二隔离物，得到第二组半导体鳍条；移除所述填充物，得到纳米线。这样，通过牺牲物为模板形成隔离物，再以隔离物为掩模对衬底进行刻蚀从而生成纳米线的方法，突破了现有技术中纯粹通过光刻技术进行刻蚀限制，能够制作出具有高均匀性、低关键尺寸抖动以及高工艺稳定性的纳米线。Embodiments of the present invention provide a method of fabricating a nanowire, comprising: disposing a substrate; depositing, on a surface of the substrate, a first sacrifice for growing a predetermined template shape, the first sacrificial being an entity and including M An outer surface perpendicular to the substrate, the M being greater than 1; selecting N outer surfaces in accordance with a predetermined rule in the outer surfaces perpendicular to the substrate for providing growth of the first spacer a template, the N is greater than 1 and less than or equal to M; depositing a first spacer of a predetermined thickness along the N outer surfaces of the first sacrificial, the first spacer of the predetermined thickness is still under Determining the first sacrificial material; anisotropically etching the substrate with the first spacer of the predetermined thickness as a mask; removing the first spacer of the predetermined thickness, Obtaining a first set of semiconductor fins; filling a portion of the substrate etched with a filler such that the filled substrate is the same shape as the substrate when not etched, the filler and the substrate Can be etched by a predetermined etch material; deposited on the upper surface of the filled substrate a second sacrificial shape of a predetermined template shape, the second sacrificial being solid and comprising X outer surfaces perpendicular to the filled substrate, the X being greater than 1; Y outer surfaces are selected in a vertical outer surface of the filled substrate according to a predetermined rule for providing a template for growth of the second spacer, the Y being greater than 1 and less than or equal to X; the Y of the second sacrifice The outer surfaces are respectively formed with predetermined intersection angles with the respective semiconductor fins of the first group of semiconductor fins; and the second spacers of the predetermined thickness are deposited along the Y outer surfaces of the second sacrificial, the pre- Having the filled substrate under the second spacer having a thickness; removing the second sacrificial; anisotropically etching the second spacer with the predetermined thickness as a mask a padded substrate; removing the second spacer of the predetermined thickness to obtain a second set of semiconductor fins; removing the filler to obtain nanowires. In this way, the method of forming a spacer by using a sacrificial material as a template, and etching the substrate by using the spacer as a mask to generate a nanowire breaks through the prior art by directly performing etching limitation by photolithography technology, and can be fabricated. Nanowires with high uniformity, low critical dimension jitter, and high process stability.
附图说明DRAWINGS
图1为本发明实施例中制作纳米线的一个实施例示意图；1 is a schematic view showing an embodiment of fabricating a nanowire according to an embodiment of the present invention;
图2为本发明实施例中制作纳米线另一实施例的一个局部示意图； 2 is a partial schematic view showing another embodiment of fabricating a nanowire according to an embodiment of the present invention;
图3为本发明实施例中制作纳米线另一实施例的另一个局部示意图；3 is another partial schematic view showing another embodiment of fabricating a nanowire according to an embodiment of the present invention;
图4为本发明实施例中制作纳米线另一实施例的一个示意图；4 is a schematic view showing another embodiment of fabricating a nanowire according to an embodiment of the present invention;
图5为本发明实施例中制作纳米线中包括硬掩模的实施例的一个示意图；5 is a schematic diagram of an embodiment including a hard mask in fabricating a nanowire according to an embodiment of the present invention;
图6为本发明实施例中制作纳米线中以硬掩模纳米线制作半导体纳米线的实施例的一个示意图。6 is a schematic diagram of an embodiment of fabricating a semiconductor nanowire with hard mask nanowires in a nanowire fabricated in an embodiment of the invention.
具体实施方式detailed description
本发明实施例提供了一种制作纳米线的方法，用于制作出具有高均匀性、低关键尺寸抖动以及高工艺稳定性的纳米线。Embodiments of the present invention provide a method of fabricating nanowires for fabricating nanowires having high uniformity, low critical dimension jitter, and high process stability.
下面参照图1所示，本发明实施例中制作纳米线的方法的一个实施例包括如下步骤：Referring to FIG. 1 , an embodiment of a method for fabricating nanowires in an embodiment of the present invention includes the following steps:
101、设置衬底；101, setting a substrate;
102、在所述衬底上表面沉积生长预设模板形状的第一牺牲物，所述第一牺牲物为实体且包括M个与所述衬底垂直的外表面，所述M大于1；102, depositing a first sacrificial shape of the predetermined template shape on the surface of the substrate, the first sacrificial body is a solid and includes M outer surfaces perpendicular to the substrate, the M is greater than 1;
由于现有技术是利用光刻技术直接对衬底进行刻蚀，而由于光刻技术的光刻精度的限制，无法刻蚀比较精细的纳米线，而且抖动较大，刻蚀出的纳米线不均匀，使得纳米线无法满足未来微纳电子学大规模集成的需求。而本发明为突破光刻精度的限制，通过以第一隔离物为掩模来对衬底进行刻蚀，然而由于第一隔离物的厚度直接影响了对衬底刻蚀所生成的第一组半导体鳍条的宽度，也影响了最后生成纳米线的尺寸，所以在设置第一隔离物之前，需要先在所述衬底上表面沉积生长预设模板形状的第一牺牲物，用于为沉积第一隔离物提供模板。Since the prior art directly etches the substrate by using photolithography technology, due to the limitation of the lithography precision of the photolithography technology, the finer nanowires cannot be etched, and the jitter is large, and the etched nanowires are not Uniformity makes nanowires unable to meet the needs of large-scale integration of micro-nanoelectronics in the future. However, in order to overcome the limitation of lithography precision, the present invention etches the substrate by using the first spacer as a mask, but the thickness of the first spacer directly affects the first group generated by etching the substrate. The width of the semiconductor fins also affects the size of the final nanowires. Therefore, before the first spacers are disposed, a first sacrificial growth of a predetermined template shape is deposited on the upper surface of the substrate for deposition. The first spacer provides a template.
可选的，所述衬底可以为规则形状的实体，例如长方体、正方体、三角体等；可选的，所述第一牺牲物可以为规则形状的实体，例如长方体、正方体、三角体等；在本发明实施例中，所述第一牺牲物包括M个与所述衬底垂直的外表面，所述M大于1，由于所述第一牺牲物的与所述衬底垂直的外表面是用于生成第一隔离物，并以所述第一隔离物为掩模各向异性刻蚀所述衬底而得到半导体鳍条的，即在本发明实施例中，能够实现生产多组半导体鳍条。优选的，本发明实施例中第一牺牲物可以为实体长方体。 Optionally, the substrate may be a regular-shaped entity, such as a rectangular parallelepiped, a cube, a triangle, etc.; alternatively, the first sacrifice may be a regular-shaped entity, such as a rectangular parallelepiped, a cube, a triangle, or the like; In an embodiment of the invention, the first sacrificial body includes M outer surfaces perpendicular to the substrate, the M being greater than 1, since an outer surface of the first sacrificial perpendicular to the substrate is A method for generating a first spacer, and anisotropically etching the substrate by using the first spacer as a mask to obtain a semiconductor fin, that is, in the embodiment of the invention, a plurality of semiconductor fins can be produced. article. Preferably, the first sacrifice in the embodiment of the present invention may be a solid cuboid.
103、在所述M个与所述衬底垂直的外表面中按照预定规则选择N个外表面用于为第一隔离物的生长提供模板，所述N大于1且小于等于M；103, in the outer surface perpendicular to the substrate, the N outer surfaces are selected according to a predetermined rule for providing a template for the growth of the first spacer, the N is greater than 1 and less than or equal to M;
由于所述第一牺牲物会存在多个与所述衬底垂直的外表面，比如若所述第一牺牲物为长方体，则可能存在四个与所述衬底垂直的外表面；为了简化工艺制作，需要从所述第一牺牲物的M个外表面中选择N个外表面，用于为第一隔离物的生长提供模板。为了使得后续步骤的刻蚀更为方便，需要从所述M个外表面中根据预设规则选择所述N个外表面，所述预设规则包括优选所述第一牺牲物中互相平行且长度最长的与所述衬底垂直的外表面，比如从长方体中选择所述长方体的高与长所形成的两个平行的外表面。Since the first sacrificial material may have a plurality of outer surfaces perpendicular to the substrate, such as if the first sacrificial body is a rectangular parallelepiped, there may be four outer surfaces perpendicular to the substrate; To make, it is necessary to select N outer surfaces from the M outer surfaces of the first sacrificial for providing a template for the growth of the first spacer. In order to facilitate the etching of the subsequent steps, the N outer surfaces need to be selected from the M outer surfaces according to a preset rule, and the preset rule includes that the first sacrificial bodies are parallel and lengthwise. The longest outer surface perpendicular to the substrate, such as the two parallel outer surfaces formed by the height and length of the cuboid from the cuboid.
104、沿第一牺牲物的所述N个外表面沉积生长预设厚度的第一隔离物，所述预设厚度的第一隔离物的下方仍有所述衬底；104, depositing a first spacer of a predetermined thickness along the N outer surfaces of the first sacrificial, wherein the substrate is still under the first spacer of the predetermined thickness;
第一隔离物的厚度为根据实际应用需求所设定的厚度，因为在刻蚀衬底时需要以所述预设厚度的第一隔离物为掩模进行刻蚀，从而生成半导体鳍条，所以第一隔离物的厚度则限定着所生成的半导体鳍条的宽度。由于所述第一隔离物是用于为刻蚀所述衬底提供掩模的，所以所述第一隔离物位于所述衬底上方。The thickness of the first spacer is a thickness set according to actual application requirements, because when the substrate is etched, the first spacer of the predetermined thickness needs to be etched as a mask to generate a semiconductor fin, so The thickness of the first spacer then defines the width of the resulting semiconductor fin. Since the first spacer is for providing a mask for etching the substrate, the first spacer is located above the substrate.
105、移除所述第一牺牲物；105. Removing the first victim;
当第一隔离物生成时，则需要以所述第一隔离物为掩模对衬底进行刻蚀，此时，需要将第一牺牲物移除，以方便对所述衬底进行刻蚀。When the first spacer is formed, the substrate needs to be etched by using the first spacer as a mask. At this time, the first sacrificial material needs to be removed to facilitate etching the substrate.
106、以所述预设厚度的第一隔离物为掩模各向异性刻蚀所述衬底；106: Anisotropically etching the substrate by using the first spacer of the predetermined thickness as a mask;
需要说明的是，在对衬底进行刻蚀时，刻蚀的深度决定了所得到的半导体鳍条的高度，也决定了最后生成纳米线的高度，所以刻蚀所述衬底的深度需根据实际需求来决定，此处不做限定。It should be noted that, when etching the substrate, the depth of the etching determines the height of the obtained semiconductor fin, and also determines the height of the final nanowire, so the depth of etching the substrate needs to be based on The actual needs are decided, and there is no limit here.
107、移除所述预设厚度的第一隔离物，得到第一组半导体鳍条；107, removing the first spacer of the predetermined thickness to obtain a first group of semiconductor fins;
当第一组半导体鳍条生成时，则需要制作第二组半导体鳍条，以最后形成纳米线，所以在制作第二组半导体鳍条之前，需移除所述预设厚度的第一隔离物，以方便制作第二组半导体鳍条，在移除所述第一隔离物之后，所形成的条状物，则是第一组半导体鳍条。When the first set of semiconductor fins are generated, a second set of semiconductor fins needs to be formed to finally form the nanowires, so the first spacer of the predetermined thickness needs to be removed before the second set of semiconductor fins are fabricated. To facilitate the fabrication of the second set of semiconductor fins, after the first spacer is removed, the strip formed is the first set of semiconductor fins.
108、使用填充物填充所述衬底被刻蚀的部分，使得被填充后的衬底与未 被刻蚀时的衬底形状一样，所述填充物与所述衬底能够被同种预定刻蚀材料刻蚀；108. Filling the etched portion of the substrate with a filler so that the filled substrate and the unfilled The shape of the substrate when etched is the same, the filler and the substrate can be etched by the same predetermined etching material;
由于衬底被刻蚀掉一部分，而凸显出第一组半导体鳍条，而本发明实施例还需要在所述第一组半导体鳍条上生长第二牺牲物以及第二隔离物，故需要使用填充物填充所述衬底被刻蚀的部分，以方便沉积生长第二牺牲物以及第二隔离物。为了方便对被填充后的衬底进行刻蚀，所以被填充后的衬底与为被刻蚀的衬底形状一样。所述填充物与所述衬底能够被同种预定刻蚀材料刻蚀，则所述填充物与所述衬底的制成材料相同或相近，比如，同为体硅材料，这样，避免了在对所述填充物与所述衬底同时刻蚀时导致波动大而影响刻蚀效果。Since the substrate is etched away to partially protrude the first group of semiconductor fins, the embodiment of the present invention also needs to grow the second sacrificial material and the second spacer on the first group of semiconductor fins, so it is required to use A filler fills the portion of the substrate that is etched to facilitate deposition of the second sacrificial and the second spacer. In order to facilitate etching of the filled substrate, the filled substrate has the same shape as the substrate to be etched. The filler and the substrate can be etched by the same predetermined etching material, and the filler is the same or similar to the material of the substrate, for example, the same silicon material, thus avoiding When the filler is etched simultaneously with the substrate, the fluctuation is large and the etching effect is affected.
109、在所述被填充后的衬底的上表面沉积生长预设模板形状的第二牺牲物，所述第二牺牲物为实体且包括X个与所述被填充后的衬底垂直的外表面，所述X大于1；109. depositing a second sacrificial growth template shape on the upper surface of the filled substrate, the second sacrificial being solid and including X outer surfaces perpendicular to the filled substrate Surface, said X is greater than 1;
可选的，所述第二牺牲物可以为规则形状的实体，例如长方体、正方体、三角体等；在本发明实施例中，所述第二牺牲物包括X个与所述衬底垂直的外表面，所述X大于1，由于所述第二牺牲物的与所述衬底垂直的外表面是用于生成第二隔离物，并以所述第二隔离物为掩模各向异性刻蚀所述衬底而得到半导体鳍条的，即在本发明实施例中，能够实现生产多组半导体鳍条。优选的，本发明实施例中第二牺牲物可以为与所述第一牺牲物同样形状的实体，即所述X可以与所述M相等。Optionally, the second victim may be a regular shaped entity, such as a rectangular parallelepiped, a cube, a triangle, or the like. In the embodiment of the present invention, the second victim includes X outer surfaces perpendicular to the substrate. a surface, the X is greater than 1, since an outer surface of the second sacrificial perpendicular to the substrate is used to generate a second spacer, and the second spacer is used as a mask for anisotropic etching The substrate is obtained to obtain semiconductor fins, that is, in the embodiment of the invention, it is possible to produce a plurality of sets of semiconductor fins. Preferably, in the embodiment of the present invention, the second sacrificial body may be an entity having the same shape as the first sacrificial object, that is, the X may be equal to the M.
110、在所述X个与所述被填充后的衬底垂直的外表面中按照预定规则选择Y个外表面用于为第二隔离物的生长提供模板，所述Y大于1且小于等于X；第二牺牲物的所述Y个外表面分别与所述第一组半导体鳍条中各个半导体鳍条形成有预设交叉角度；110. Select Y outer surfaces according to a predetermined rule in the X outer surfaces perpendicular to the filled substrate for providing a template for growth of the second spacer, wherein Y is greater than 1 and less than or equal to X The Y outer surfaces of the second sacrificial body respectively form a predetermined intersection angle with each of the semiconductor fins of the first group of semiconductor fins;
由于所述第二牺牲物会存在多个与所述衬底垂直的外表面，比如若所述第二牺牲物为长方体，则可能存在四个与所述衬底垂直的外表面；为了简化工艺制作，需要从所述第二牺牲物的X个外表面中选择Y个外表面，用于为第二隔离物的生长提供模板。为了使得后续步骤的刻蚀更为方便，需要从所述X个外表面中根据预设规则选择所述Y个外表面，所述预设规则包括优选所述第二牺牲物中互相平行且长度最长的与所述衬底垂直的外表面，比如从长方体 中选择所述长方体的高与长所形成的两个平行的外表面。优选的，所述Y与所述N可以相等，且从所述第二牺牲物中所选择的Y个外表面与所述从第一牺牲物中所选择的N个外表面可以均为平行且长度最长的外表面。Since the second sacrificial material may have a plurality of outer surfaces perpendicular to the substrate, such as if the second sacrificial body is a rectangular parallelepiped, there may be four outer surfaces perpendicular to the substrate; To make, it is necessary to select Y outer surfaces from the X outer surfaces of the second sacrificial for providing a template for the growth of the second spacer. In order to facilitate the etching of the subsequent steps, the Y outer surfaces need to be selected from the X outer surfaces according to a preset rule, and the preset rule includes that the second sacrificial bodies are preferably parallel to each other and length. The longest outer surface perpendicular to the substrate, such as from a cuboid The two parallel outer surfaces formed by the height and length of the cuboid are selected. Preferably, the Y and the N may be equal, and the Y outer surfaces selected from the second sacrificial and the N outer surfaces selected from the first sacrificial may both be parallel and The longest outer surface.
由于所述第二牺牲物是用于给生成第二隔离物提供模板的，而所述第二隔离物是用于作为掩模对所述被填充后的衬底进行刻蚀而得到第二组半导体鳍条的，只有所述第二组半导体鳍条所述所述第一组半导体鳍条存在相交，才能够得到纳米线，所以第二牺牲物的所述Y个外表面分别与所述第一组半导体鳍条中各个半导体鳍条形成有预设交叉角度，等同于所述第二隔离物与所述第一组半导体鳍条形成的角度，而所述第二隔离物与所述第一组半导体鳍条所形成的角度则决定了最后生成纳米线的横截面形状。比如，若所述第二牺牲物的所述Y个外表面分别与所述第一组半导体鳍条中各个半导体鳍条所形成的角度为90度，则最后所得到的纳米线的横截面则为长方形；否则，则最后得到的纳米线的横截面则为平行四边形。Since the second sacrificial is for providing a template for generating the second spacer, and the second spacer is for etching the filled substrate as a mask to obtain the second group For the semiconductor fins, only the second set of semiconductor fins intersect with the first set of semiconductor fins to obtain nanowires, so the Y outer surfaces of the second sacrificial respectively Each of the plurality of semiconductor fins is formed with a predetermined crossing angle equal to an angle formed by the second spacer and the first set of semiconductor fins, and the second spacer and the first The angle formed by the group of semiconductor fins determines the cross-sectional shape of the resulting nanowire. For example, if the Y outer surfaces of the second sacrificial are respectively formed at an angle of 90 degrees with each of the semiconductor fins of the first group of semiconductor fins, the cross section of the finally obtained nanowire is It is a rectangle; otherwise, the resulting nanowire has a parallelogram in cross section.
111、沿第二牺牲物的所述Y个外表面沉积生长预设厚度的第二隔离物，所述预设厚度的第二隔离物下方仍有所述被填充后的衬底；111, depositing a second spacer of a predetermined thickness along the Y outer surfaces of the second sacrificial, wherein the filled substrate is still under the second spacer of the predetermined thickness;
第二隔离物的厚度为根据实际应用需求所设定的厚度，因为在刻蚀衬底时需要以所述第二隔离物为掩模进行刻蚀，从而生成第二组半导体鳍条，所以第二隔离物的厚度则限定着所生成的第体半导体鳍条的宽度，也是最终生成纳米线的尺寸。若所述预设厚度的第一隔离物的厚度与所述预设厚度的第二隔离物的厚度相等，则最后形成的纳米线的横截面为等边四边形。由于所述预设厚度的第二隔离物是用于为刻蚀所述被填充后的衬底提供掩模的，所以所述预设厚度的第二隔离物位于所述被填充后的衬底上方。The thickness of the second spacer is a thickness set according to actual application requirements, because etching needs to be performed by using the second spacer as a mask when etching the substrate, thereby generating a second group of semiconductor fins, so The thickness of the two spacers defines the width of the resulting first semiconductor fins and also the size of the resulting nanowires. If the thickness of the first spacer of the predetermined thickness is equal to the thickness of the second spacer of the predetermined thickness, the cross section of the finally formed nanowire is an equilateral quadrilateral. Since the second spacer of the predetermined thickness is for providing a mask for etching the filled substrate, the second spacer of the predetermined thickness is located on the filled substrate Above.
112、移除所述第二牺牲物；112. Removing the second victim;
当第二隔离物生成时，则需要以所述第二隔离物为掩模对被填充后的衬底进行刻蚀，此时，需要将第二牺牲物移除，以方便对所述被填充后的衬底进行刻蚀。When the second spacer is formed, the padded substrate needs to be etched by using the second spacer as a mask. At this time, the second sacrifice needs to be removed to facilitate the filling. The subsequent substrate is etched.
113、以所述预设厚度的第二隔离物为掩模各向异性刻蚀所述被填充后的衬底；113, anisotropically etching the filled substrate by using the second spacer of the predetermined thickness as a mask;
需要说明的是，在对衬底进行刻蚀时，刻蚀的深度决定了半导体鳍条的高 度，也决定了最后生成纳米线的高度，所以刻蚀所述衬底的深度需根据实际需求来决定，此处不做限定。优选的，所述第二组半导体鳍条的高度与所述第一组半导体鳍条的高度相等。It should be noted that when etching the substrate, the depth of the etching determines the height of the semiconductor fins. The degree of the final generation of the nanowire is also determined, so the depth of etching the substrate needs to be determined according to actual needs, which is not limited herein. Preferably, the height of the second set of semiconductor fins is equal to the height of the first set of semiconductor fins.
114、移除所述预设厚度的第二隔离物，得到第二组半导体鳍条；114. Removing the second spacer of the predetermined thickness to obtain a second set of semiconductor fins;
移除所述第二隔离物之后，所得到的第二组半导体鳍条中，所述半导体鳍条还包括填充物以及衬底。After removing the second spacer, in the resulting second set of semiconductor fins, the semiconductor fin further includes a filler and a substrate.
115、移除所述填充物，得到纳米线；115. Removing the filler to obtain a nanowire;
移除所述第二组半导体鳍条中的填充物之后，剩下的衬底部分所呈现的凸起则为纳米线。需要说明的是，最后所得到的纳米线的数量与之前所选择的第一牺牲物的N个外表面以及第二牺牲物的Y个外表面有关，具体的，最后得到的纳米线的数量为所述N与所述Y的乘积。比如N与Y均为2，则得到的第一组半导体鳍条为一条，第二组半导体鳍条也是一条，最后得到的纳米线为四条。After removing the filler in the second set of semiconductor fins, the remaining substrate portions are rendered as nanowires. It should be noted that the number of nanowires obtained last is related to the N outer surfaces of the first selected first sacrificial and the Y outer surfaces of the second sacrificial. Specifically, the number of nanowires obtained is The product of the N and the Y. For example, if N and Y are both 2, the first set of semiconductor fins is one, the second set of semiconductor fins is also one, and finally the obtained nanowires are four.
本发明实施例中，第一牺牲物用于为沉积第一隔离物提供模板，以所述第一隔离物为掩模各向异性刻蚀所述衬底，得到第一组半导体鳍条；第二牺牲物用于为沉积第二隔离物提供模板，以所述第二隔离物为掩模各向异性刻蚀所述被填充后的衬底；移除所述第二隔离物，得到第二组半导体鳍条；移除所述填充物，得到纳米线。这样，通过牺牲物为模板形成隔离物，再以隔离物为掩模对衬底进行刻蚀从而生成纳米线的方法，突破了现有技术中纯粹通过光刻技术进行刻蚀限制，能够制作出具有高均匀性、低关键尺寸抖动以及高工艺稳定性的纳米线。In the embodiment of the present invention, the first sacrificial material is used for providing a template for depositing a first spacer, and the substrate is anisotropically etched by using the first spacer as a mask to obtain a first group of semiconductor fins; a second sacrificial for providing a template for depositing a second spacer, anisotropically etching the filled substrate with the second spacer as a mask; removing the second spacer to obtain a second Grouping semiconductor fins; removing the filler to obtain nanowires. In this way, the method of forming a spacer by using a sacrificial material as a template, and etching the substrate by using the spacer as a mask to generate a nanowire breaks through the prior art by directly performing etching limitation by photolithography technology, and can be fabricated. Nanowires with high uniformity, low critical dimension jitter, and high process stability.
上述实施例描述了在衬底上设置牺牲物，沿牺牲物在衬底上设置隔离物，以隔离物为掩模各向异性刻蚀衬底；在实际应用中，隔离物可以通过薄膜沉积生长和各向异性刻蚀技术来实现，刻蚀衬底可以通过各向异性刻蚀技术来实现；下面进行具体说明，参照图2以及图3所示，本发明实施例中制作纳米线的方法的另一实施例包括如下步骤：The above embodiments describe that a spacer is disposed on a substrate, a spacer is disposed on the substrate along the sacrificial, and the substrate is anisotropically etched using the spacer as a mask; in practical applications, the spacer may be grown by thin film deposition. And the anisotropic etching technology is implemented, and the etching of the substrate can be realized by an anisotropic etching technique; as described in detail below with reference to FIG. 2 and FIG. 3, the method for fabricating the nanowire in the embodiment of the present invention Another embodiment includes the following steps:
201、设置衬底；201, setting a substrate;
202、在所述衬底10上表面沉积生长第一牺牲物薄膜，利用光刻和刻蚀技术将所述第一牺牲物薄膜定义成预设模板形状的第一牺牲物11，所述第一牺 牲物11为实体且包括M个与所述衬底10垂直的外表面，所述M大于1；202, depositing a first sacrificial film on the upper surface of the substrate 10, and defining the first sacrificial film into a first sacrificial pattern 11 of a predetermined template shape by using a photolithography and etching technique, the first Sacrifice The animal 11 is solid and includes M outer surfaces perpendicular to the substrate 10, the M being greater than 1;
由于在所述衬底上表面是无法直接沉积生长预设模板形状的第一牺牲物的，所以首先在所述衬底上表面沉积生长第一牺牲物薄膜，所述第一牺牲物薄膜是完全覆盖所述衬底的，再利用光刻和刻蚀技术将所述第一牺牲物薄膜定义成预设模板形状的第一牺牲物。Since the first sacrificial surface of the substrate is not directly deposited on the upper surface of the substrate, a first sacrificial film is first deposited on the surface of the substrate, and the first sacrificial film is completely The first sacrificial film is defined as a first sacrificial shape of a predetermined template shape by covering the substrate and then using photolithography and etching techniques.
可选的，所述衬底包括体硅衬底、SOI衬底、锗硅衬底、三五族材料、或者多种半导体材料薄膜堆叠等任意一种半导体衬底。Optionally, the substrate comprises a bulk silicon substrate, an SOI substrate, a silicon germanium substrate, a tri-five material, or a plurality of semiconductor material thin film stacks.
可选的，所述第一牺牲物薄膜的制成材料包括多晶硅、α硅以及光刻胶其中任意一种。Optionally, the material for forming the first sacrificial film comprises any one of polysilicon, alpha silicon, and photoresist.
203、在所述M个与所述衬底10垂直的外表面中按照预定规则选择N个外表面用于为第一隔离物的生长提供模板，所述N大于1且小于等于M；203, in the outer surface perpendicular to the substrate 10, the N outer surfaces are selected according to a predetermined rule for providing a template for the growth of the first spacer, the N is greater than 1 and less than or equal to M;
由于所述第一牺牲物会存在多个与所述衬底垂直的外表面，比如若所述第一牺牲物为长方体，则可能存在四个与所述衬底垂直的外表面；为了简化工艺制作，需要从所述第一牺牲物的M个外表面中选择N个外表面，用于为第一隔离物的生长提供模板。为了使得后续步骤的刻蚀更为方便，需要从所述M个外表面中根据预设规则选择所述N个外表面，所述预设规则包括优选所述第一牺牲物中互相平行且长度最长的与所述衬底垂直的外表面，比如从长方体中选择所述长方体的高与长所形成的两个平行的外表面。Since the first sacrificial material may have a plurality of outer surfaces perpendicular to the substrate, such as if the first sacrificial body is a rectangular parallelepiped, there may be four outer surfaces perpendicular to the substrate; To make, it is necessary to select N outer surfaces from the M outer surfaces of the first sacrificial for providing a template for the growth of the first spacer. In order to facilitate the etching of the subsequent steps, the N outer surfaces need to be selected from the M outer surfaces according to a preset rule, and the preset rule includes that the first sacrificial bodies are parallel and lengthwise. The longest outer surface perpendicular to the substrate, such as the two parallel outer surfaces formed by the height and length of the cuboid from the cuboid.
204、沿第一牺牲物11的所述N个外表面沉积生长预设厚度的第一隔离物薄膜，所述第一隔离物薄膜的厚度用于限定所述第一组半导体鳍条的宽度，以使得所述第一组半导体鳍条的宽度与所述第一隔离物薄膜的厚度相等；204. depositing, along the N outer surfaces of the first sacrificial 11, a first spacer film of a predetermined thickness, wherein a thickness of the first spacer film is used to define a width of the first group of semiconductor fins, So that the width of the first set of semiconductor fins is equal to the thickness of the first spacer film;
所述第一隔离物的制成材料包括氮化硅、二氧化硅、氮化钛、氮化钽或者其他耐刻蚀材料中的至少一种。The material of the first spacer is made of at least one of silicon nitride, silicon dioxide, titanium nitride, tantalum nitride or other etching resistant materials.
205、利用各向异性刻蚀技术将所述第一隔离物薄膜刻蚀形成预设厚度的第一隔离物12，所述预设厚度的第一隔离物12下方仍有衬底；205. The first spacer film is etched to form a first spacer 12 of a predetermined thickness by using an anisotropic etching technique, and the substrate has a substrate under the first spacer 12 of the predetermined thickness;
通过各向异性刻蚀技术刻蚀后的第一隔离物薄膜则仅剩与所述第一牺牲物薄膜紧贴的隔离物。第一隔离物薄膜为根据实际应用需求所设定的厚度，因为在刻蚀衬底时需要以所述预设厚度的第一隔离物为掩模进行刻蚀，从而生成第一组半导体鳍条，所以第一隔离物薄膜的厚度则限定着所生成的半导体鳍条 的宽度，也是最终生成半导体纳米线的宽度。The first spacer film etched by the anisotropic etching technique leaves only a spacer in close contact with the first sacrificial film. The first spacer film is a thickness set according to actual application requirements, because the first spacer of the predetermined thickness needs to be etched as a mask when etching the substrate, thereby generating the first group of semiconductor fins. , so the thickness of the first spacer film defines the generated semiconductor fins The width is also the width of the resulting semiconductor nanowires.
206、移除所述第一牺牲物11；206, removing the first sacrifice 11;
当第一隔离物生成时，则需要以所述第一隔离物为掩模对衬底进行刻蚀，此时，需要将第一牺牲物移除，以方便对所述衬底进行刻蚀。When the first spacer is formed, the substrate needs to be etched by using the first spacer as a mask. At this time, the first sacrificial material needs to be removed to facilitate etching the substrate.
207、以所述预设厚度的第一隔离物12为掩模各向异性刻蚀所述衬底10；207, anisotropically etching the substrate 10 with the first spacer 12 of the predetermined thickness as a mask;
需要说明的是，在对衬底进行刻蚀时，刻蚀的深度决定了所得到的半导体鳍条的高度，也决定了最后生成纳米线的高度，所以刻蚀所述衬底的深度需根据实际需求来决定，此处不做限定。It should be noted that, when etching the substrate, the depth of the etching determines the height of the obtained semiconductor fin, and also determines the height of the final nanowire, so the depth of etching the substrate needs to be based on The actual needs are decided, and there is no limit here.
208、移除所述预设厚度的第一隔离物12，得到第一组半导体鳍条13；208, the first spacer 12 of the predetermined thickness is removed, to obtain a first group of semiconductor fins 13;
当第一组半导体鳍条生成时，则需要制作第二组半导体鳍条，以最后形成纳米线，所以在制作第二组半导体鳍条之前，需移除所述预设厚度的第一隔离物，以方便制作第二组半导体鳍条，在移除所述预设厚度的第一隔离物之后，所形成的条状物，则是第一组半导体鳍条。When the first set of semiconductor fins are generated, a second set of semiconductor fins needs to be formed to finally form the nanowires, so the first spacer of the predetermined thickness needs to be removed before the second set of semiconductor fins are fabricated. To facilitate fabrication of the second set of semiconductor fins, after removing the first spacer of the predetermined thickness, the formed strip is the first set of semiconductor fins.
209、使用填充物14填充所述衬底被刻蚀的部分，使得被填充后的衬底15与未被刻蚀时的衬底10形状一样，所述填充物14与所述衬底10能够被同种预定刻蚀材料刻蚀；209. Filling the etched portion of the substrate with a filler 14 such that the filled substrate 15 has the same shape as the substrate 10 when not etched, and the filler 14 and the substrate 10 can Etched by the same predetermined etching material;
由于衬底被刻蚀掉一部分，而凸显出第一组半导体鳍条，而本发明实施例还需要在所述第一组半导体鳍条上生长第二牺牲物以及第二隔离物，故需要使用填充物填充所述衬底被刻蚀的部分，以方便沉积生长第二牺牲物以及第二隔离物。为了方便对被填充后的衬底进行刻蚀，所以被填充后的衬底与为被刻蚀的衬底形状一样。所述填充物与所述衬底能够被同种预定刻蚀材料刻蚀，则所述填充物与所述衬底的制成材料相同或相近，比如，同为体硅材料，这样，避免了在对所述填充物与所述衬底同时刻蚀时导致波动大而影响刻蚀效果。Since the substrate is etched away to partially protrude the first group of semiconductor fins, the embodiment of the present invention also needs to grow the second sacrificial material and the second spacer on the first group of semiconductor fins, so it is required to use A filler fills the portion of the substrate that is etched to facilitate deposition of the second sacrificial and the second spacer. In order to facilitate etching of the filled substrate, the filled substrate has the same shape as the substrate to be etched. The filler and the substrate can be etched by the same predetermined etching material, and the filler is the same or similar to the material of the substrate, for example, the same silicon material, thus avoiding When the filler is etched simultaneously with the substrate, the fluctuation is large and the etching effect is affected.
210、将所述被填充后的衬底15抛光，以暴露出所述第一组半导体鳍条13的顶部；210. Polishing the filled substrate 15 to expose a top portion of the first set of semiconductor fins 13;
由于在使用填充物填充所述衬底被刻蚀的部分时，可能会造成被填充后的衬底表面凹凸或掩盖了第一组半导体鳍条，从而影响了后续在被填充后的衬底上沉积生长第二牺牲物薄膜，所以可以先对所述被填充后的衬底进行抛光，使得所述第一组半导体鳍条的顶部暴露出来。 Since the surface of the substrate to be etched is filled with a filler, the surface of the filled substrate may be bumped or concealed by the first set of semiconductor fins, thereby affecting subsequent implantation on the filled substrate. A second sacrificial film is deposited and deposited, so the filled substrate can be polished first such that the tops of the first set of semiconductor fins are exposed.
211、在所述被填充后的衬底15上表面沉积生长第二牺牲物薄膜，利用光刻和刻蚀技术将所述第二牺牲物薄膜定义成预设模板形状的第二牺牲物16，所述第二牺牲物16为实体且包括X个与所述被填充后的衬底垂直的外表面，所述X大于1；211. depositing a second sacrificial film on the surface of the filled substrate 15 to define the second sacrificial film into a second template 16 of a predetermined template shape by using photolithography and etching techniques. The second sacrificial 16 is a solid and includes X outer surfaces perpendicular to the filled substrate, the X being greater than 1;
由于在所述被填充后的衬底上表面是无法直接沉积生长预设模板形状的第二牺牲物的，所以首先在所述被填充后的衬底上表面沉积生长第二牺牲物薄膜，所述第二牺牲物薄膜是完全覆盖所述衬底的，再利用光刻和刻蚀技术将所述第二牺牲物薄膜定义成预设模板形状的第二牺牲物。Since the surface of the filled substrate is not capable of directly depositing a second sacrificial growth of the predetermined template shape, first depositing a second sacrificial film on the surface of the filled substrate is deposited. The second sacrificial film is completely covered by the substrate, and the second sacrificial film is defined as a second sacrificial shape of a predetermined template shape by photolithography and etching techniques.
212、在所述X个与所述被填充后的衬底15垂直的外表面中按照预定规则选择Y个外表面用于为第二隔离物的生长提供模板，所述Y大于1且小于等于X；第二牺牲物16的所述Y个外表面分别与所述第一组半导体鳍条13中各个半导体鳍条形成有预设交叉角度；212. Selecting Y outer surfaces according to a predetermined rule in the X outer surfaces perpendicular to the filled substrate 15 for providing a template for the growth of the second spacer, wherein Y is greater than 1 and less than or equal to X; the Y outer surfaces of the second sacrificial body 16 are respectively formed with predetermined intersection angles with the respective semiconductor fins of the first group of semiconductor fins 13;
由于所述第二牺牲物是用于给生成第二隔离物提供模板的，而所述第二隔离物是用于作为掩模对所述被填充后的衬底进行刻蚀而得到第二组半导体鳍条的，只有所述第二组半导体鳍条所述所述第一组半导体鳍条存在相交，才能够得到纳米线，所以第二牺牲物的所述Y个外表面分别与所述第一组半导体鳍条中各个半导体鳍条形成有预设交叉角度，等同于所述第二隔离物与所述第一组半导体鳍条形成的角度，而所述第二隔离物与所述第一组半导体鳍条所形成的角度则决定了最后生成纳米线的横截面形状。比如，若所述第二牺牲物的所述Y个外表面分别与所述第一组半导体鳍条中各个半导体鳍条所形成的角度为90度，则最后所得到的纳米线的横截面则为长方形；否则，则最后得到的纳米线的横截面则为平行四边形。Since the second sacrificial is for providing a template for generating the second spacer, and the second spacer is for etching the filled substrate as a mask to obtain the second group For the semiconductor fins, only the second set of semiconductor fins intersect with the first set of semiconductor fins to obtain nanowires, so the Y outer surfaces of the second sacrificial respectively Each of the plurality of semiconductor fins is formed with a predetermined crossing angle equal to an angle formed by the second spacer and the first set of semiconductor fins, and the second spacer and the first The angle formed by the group of semiconductor fins determines the cross-sectional shape of the resulting nanowire. For example, if the Y outer surfaces of the second sacrificial are respectively formed at an angle of 90 degrees with each of the semiconductor fins of the first group of semiconductor fins, the cross section of the finally obtained nanowire is It is a rectangle; otherwise, the resulting nanowire has a parallelogram in cross section.
213、沿第二牺牲物16的所述Y个外表面沉积生长预设厚度的第二隔离物薄膜，所述第二隔离物薄膜的厚度用于限定所述第二组半导体鳍条的宽度，以使得所述第二组半导体鳍条的宽度与所述第一隔离物薄膜的厚度相等；213. depositing a second spacer film of a predetermined thickness along the Y outer surfaces of the second sacrificial 16, the thickness of the second spacer film being used to define a width of the second set of semiconductor fins, So that the width of the second set of semiconductor fins is equal to the thickness of the first spacer film;
所述第二隔离物的制成材料包括氮化硅、二氧化硅、氮化钛、氮化钽或者其他耐刻蚀材料中的至少一种。The second spacer is made of at least one of silicon nitride, silicon dioxide, titanium nitride, tantalum nitride or other etching resistant materials.
214、利用各向异性刻蚀技术将所述第二隔离物薄膜刻蚀形成预设厚度的第二隔离物17，所述预设厚度的第二隔离物下方仍有所述被填充后的衬底； 214. The second spacer film is etched by using an anisotropic etching technique to form a second spacer 17 of a predetermined thickness, and the filled spacer is still under the second spacer of the predetermined thickness. bottom;
第二隔离物的厚度为根据实际应用需求所设定的厚度，因为在刻蚀衬底时需要以所述预设厚度的第二隔离物为掩模进行刻蚀，从而生成第二组半导体鳍条，所以第二隔离物的厚度则限定着所生成的第体半导体鳍条的宽度，也是最终生成纳米线的尺寸。若所述第一隔离物的厚度与所述第二隔离物的厚度相等，则最后形成的纳米线的横截面为等边四边形。可选的，所述第二可牺牲物薄膜的制成材料包括多晶硅、α硅以及光刻胶其中任意一种。The thickness of the second spacer is a thickness set according to actual application requirements, because the second spacer of the predetermined thickness needs to be etched as a mask when etching the substrate, thereby generating a second group of semiconductor fins. The strip, so the thickness of the second spacer defines the width of the generated first semiconductor fin, which is also the size of the final nanowire. If the thickness of the first spacer is equal to the thickness of the second spacer, the cross section of the finally formed nanowire is an equilateral quadrilateral. Optionally, the second sacrificial film is made of any one of polysilicon, alpha silicon, and photoresist.
215、移除所述第二牺牲物16；215, remove the second sacrifice 16;
当第二隔离物生成时，则需要以所述第二隔离物为掩模对被填充后的衬底进行刻蚀，此时，需要将第二牺牲物薄膜移除，以方便对所述被填充后的衬底进行刻蚀。When the second spacer is formed, the filled substrate needs to be etched by using the second spacer as a mask. At this time, the second sacrificial film needs to be removed to facilitate the The filled substrate is etched.
216、以所述预设厚度的第二隔离物17为掩模利用各向异性刻蚀技术刻蚀所述被填充后的衬底15；216, the predetermined thickness of the second spacer 17 as a mask using an anisotropic etching technique to etch the filled substrate 15;
需要说明的是，在对衬底进行刻蚀时，刻蚀的深度决定了半导体鳍条的高度，也决定了最后生成半导体纳米线的高度，所以刻蚀所述衬底的深度需根据实际需求来决定，此处不做限定。优选的，所述第二组半导体鳍条的高度与所述第一组半导体鳍条的高度相等。It should be noted that, when etching the substrate, the depth of the etching determines the height of the semiconductor fins, and also determines the height of the final semiconductor nanowires, so the depth of etching the substrate needs to be according to actual needs. To decide, there is no limit here. Preferably, the height of the second set of semiconductor fins is equal to the height of the first set of semiconductor fins.
217移除所述预设厚度的第二隔离物17，得到第二组半导体鳍条18；217 removing the second spacer 17 of the predetermined thickness to obtain a second set of semiconductor fins 18;
移除所述预设厚度的第二隔离物之后，所得到的第二组半导体鳍条中，所述半导体鳍条还包括填充物以及衬底。After removing the second spacer of the predetermined thickness, in the obtained second group of semiconductor fins, the semiconductor fin further includes a filler and a substrate.
218、移除所述填充物14，得到纳米线19；218, remove the filler 14, to obtain a nanowire 19;
移除所述第二组半导体鳍条中的填充物之后，剩下的衬底部分所呈现的凸起则为纳米线。需要说明的是，最后所得到的纳米线的数量与之前所选择的第一牺牲物的N个外表面以及第二牺牲物的Y个外表面有关，具体的，最后得到的纳米线的数量为所述N与所述Y的乘积。比如N与Y均为2，则得到的第一组半导体鳍条为一条，第二组半导体鳍条也是一条，最后得到的纳米线为四条。After removing the filler in the second set of semiconductor fins, the remaining substrate portions are rendered as nanowires. It should be noted that the number of nanowires obtained last is related to the N outer surfaces of the first selected first sacrificial and the Y outer surfaces of the second sacrificial. Specifically, the number of nanowires obtained is The product of the N and the Y. For example, if N and Y are both 2, the first set of semiconductor fins is one, the second set of semiconductor fins is also one, and finally the obtained nanowires are four.
本发明实施例中，以光刻技术刻蚀衬底，使得刻蚀所生成的半导体鳍条以及纳米线更为精细。In the embodiment of the invention, the substrate is etched by photolithography, so that the semiconductor fins and the nanowires generated by the etching are finer.
参照图4所示，本发明实施例中制作纳米线的方法的另一实施例包括如下 步骤：Referring to FIG. 4, another embodiment of a method of fabricating nanowires in an embodiment of the present invention includes the following step:
301、设置半导体衬底；301, setting a semiconductor substrate;
302、在所述半导体衬底上表面沉积生长硬掩模层；302, depositing a growth hard mask layer on a surface of the semiconductor substrate;
上述实施例所描述的方法是通过直接在半导体衬底上沉积生长第一牺牲物、第一隔离物，得到第一组半导体鳍条，在被填充后的半导体衬底上沉积生长第二牺牲物、第二隔离物，得到第二组半导体鳍条；然而，在经过多次刻蚀、移除隔离物或填充物时，操作过程中有可能损坏半导体衬底，从而使得得到的半导体纳米线不均匀或不符合实用要求。本发明实施例中，则先在所述半导体衬底上沉积生长硬掩模层，使得后续刻蚀、移除等操作在所述硬掩模层上进行，从而先得到硬掩模纳米线，最后再以硬掩模纳米线为掩模对所述半导体刻蚀，从而得到均匀且符号使用要求的半导体纳米线。在所述半导体衬底22上沉积生长有硬掩模层21参照图5所示。The method described in the above embodiments is to deposit a first set of semiconductor fins by depositing a first sacrificial material, a first spacer on a semiconductor substrate, and depositing a second sacrificial growth on the filled semiconductor substrate. And the second spacer obtains the second group of semiconductor fins; however, when the etching or the spacer is removed multiple times, the semiconductor substrate may be damaged during the operation, so that the obtained semiconductor nanowires are not Uniform or not meeting practical requirements. In the embodiment of the present invention, a growth hard mask layer is first deposited on the semiconductor substrate, so that subsequent etching, removal, and the like are performed on the hard mask layer, thereby obtaining a hard mask nanowire. Finally, the semiconductor is etched using a hard mask nanowire as a mask to obtain a semiconductor nanowire which is uniform and requires symbolic use. A hard mask layer 21 is deposited on the semiconductor substrate 22 as shown in FIG.
303、在所述硬掩模层上表面沉积生长预设模板形状的第一牺牲物，所述第一牺牲物为实体且包括M个与所述硬掩模层垂直的外表面，所述M大于1；303. Depositing, on a surface of the hard mask layer, a first sacrificial growth template shape, the first sacrificial body being a solid body and including M outer surfaces perpendicular to the hard mask layer, the M Greater than 1;
本发明为突破光刻精度的限制，通过以第一隔离物为掩模来对硬掩模层进行刻蚀，然而由于第一隔离物的厚度直接影响了对硬掩模层刻蚀所生成的第一组半导体鳍条的宽度，也影响了最后生成纳米线的尺寸，所以在设置第一隔离物之前，需要先在所述硬掩模层上表面沉积生长预设模板形状的第一牺牲物，用于为沉积第一隔离物提供模板。The invention overcomes the limitation of lithography precision by etching the hard mask layer by using the first spacer as a mask, however, since the thickness of the first spacer directly affects the etching generated by the hard mask layer The width of the first set of semiconductor fins also affects the size of the final generated nanowire, so before the first spacer is disposed, the first sacrificial growth of the predetermined template shape needs to be deposited on the surface of the hard mask layer. And for providing a template for depositing the first spacer.
可选的，所述硬掩模层可以为规则形状的实体，例如长方体、正方体、三角体等；可选的，所述第一牺牲物可以为规则形状的实体，例如长方体、正方体、三角体等；在本发明实施例中，所述第一牺牲物包括M个与所述硬掩模层垂直的外表面，所述M大于1，由于所述第一牺牲物的与所述硬掩模层垂直的外表面是用于生成第一隔离物，并以所述第一隔离物为掩模各向异性刻蚀所述硬掩模层而得到半导体鳍条的，即在本发明实施例中，能够实现生产多组半导体鳍条。优选的，本发明实施例中第一牺牲物可以为实体长方体。Optionally, the hard mask layer may be a regular shape entity, such as a rectangular parallelepiped, a cube, a triangle, etc.; optionally, the first sacrifice may be a regular shaped entity, such as a rectangular parallelepiped, a cube, a triangle. In the embodiment of the present invention, the first sacrificial body includes M outer surfaces perpendicular to the hard mask layer, and the M is greater than 1, due to the first sacrificial and the hard mask The vertical outer surface of the layer is used to generate a first spacer, and the hard mask layer is anisotropically etched by using the first spacer as a mask to obtain a semiconductor fin, that is, in the embodiment of the present invention It can realize the production of multiple sets of semiconductor fins. Preferably, the first sacrifice in the embodiment of the present invention may be a solid cuboid.
304、在所述M个与所述硬掩模层垂直的外表面中按照预定规则选择N个外表面用于为第一隔离物的生长提供模板，所述N大于1且小于等于M；304, in the outer surface perpendicular to the hard mask layer, select N outer surfaces according to a predetermined rule for providing a template for the growth of the first spacer, the N is greater than 1 and less than or equal to M;
由于所述第一牺牲物会存在多个与所述硬掩模层垂直的外表面，比如若所 述第一牺牲物为长方体，则可能存在四个与所述硬掩模层垂直的外表面；为了简化工艺制作，需要从所述第一牺牲物的M个外表面中选择N个外表面，用于为第一隔离物的生长提供模板。为了使得后续步骤的刻蚀更为方便，需要从所述M个外表面中根据预设规则选择所述N个外表面，所述预设规则包括优选所述第一牺牲物中互相平行且长度最长的与所述硬掩模层垂直的外表面，比如从长方体中选择所述长方体的高与长所形成的两个平行的外表面。Since the first sacrificial material may have a plurality of outer surfaces perpendicular to the hard mask layer, such as If the first sacrificial body is a rectangular parallelepiped, there may be four outer surfaces perpendicular to the hard mask layer; in order to simplify the process, it is necessary to select N outer surfaces from the M outer surfaces of the first sacrificial material, Used to provide a template for the growth of the first spacer. In order to facilitate the etching of the subsequent steps, the N outer surfaces need to be selected from the M outer surfaces according to a preset rule, and the preset rule includes that the first sacrificial bodies are parallel and lengthwise. The longest outer surface perpendicular to the hard mask layer, such as two parallel outer surfaces formed by selecting the height and length of the cuboid from the cuboid.
305、沿第一牺牲物的所述N个外表面沉积生长预设厚度的第一隔离物，所述预设厚度的第一隔离物的下方仍有所述硬掩模层；305, depositing a first spacer of a predetermined thickness along the N outer surfaces of the first sacrificial layer, the hard mask layer remaining under the first spacer of the predetermined thickness;
第一隔离物的厚度为根据实际应用需求所设定的厚度，因为在刻蚀硬掩模层时需要以所述预设厚度的第一隔离物为掩模进行刻蚀，从而生成半导体鳍条，所以第一隔离物的厚度则限定着所生成的半导体鳍条的宽度。由于所述第一隔离物是用于为刻蚀所述硬掩模层提供掩模的，所以所述第一隔离物位于所述硬掩模层上方。The thickness of the first spacer is a thickness set according to actual application requirements, because when the hard mask layer is etched, it is required to etch with the first spacer of the predetermined thickness as a mask to generate a semiconductor fin. Therefore, the thickness of the first spacer defines the width of the resulting semiconductor fin. Since the first spacer is for providing a mask for etching the hard mask layer, the first spacer is located above the hard mask layer.
306、移除所述第一牺牲物；306. Remove the first sacrifice;
当第一隔离物生成时，则需要以所述第一隔离物为掩模对硬掩模层进行刻蚀，此时，需要将第一牺牲物移除，以方便对所述硬掩模层进行刻蚀。When the first spacer is formed, the hard mask layer needs to be etched by using the first spacer as a mask. At this time, the first sacrificial material needs to be removed to facilitate the hard mask layer. Etching is performed.
307、以所述预设厚度的第一隔离物为掩模各向异性刻蚀所述硬掩模层；307: Anisotropically etching the hard mask layer by using the first spacer of the predetermined thickness as a mask;
需要说明的是，在对硬掩模层进行刻蚀时，刻蚀的深度决定了所得到的半导体鳍条的高度，也决定了最后生成纳米线的高度，所以刻蚀所述硬掩模层的深度需根据实际需求来决定，此处不做限定。It should be noted that, when etching the hard mask layer, the depth of the etching determines the height of the obtained semiconductor fin, and determines the height of the final nanowire, so the hard mask layer is etched. The depth should be determined according to actual needs, and is not limited here.
308、移除所述预设厚度的第一隔离物，得到第一组半导体鳍条；308, removing the first spacer of the predetermined thickness to obtain a first group of semiconductor fins;
当第一组半导体鳍条生成时，则需要制作第二组半导体鳍条，以最后形成纳米线，所以在制作第二组半导体鳍条之前，需移除所述预设厚度的第一隔离物，以方便制作第二组半导体鳍条，在移除所述第一隔离物之后，所形成的条状物，则是第一组半导体鳍条。When the first set of semiconductor fins are generated, a second set of semiconductor fins needs to be formed to finally form the nanowires, so the first spacer of the predetermined thickness needs to be removed before the second set of semiconductor fins are fabricated. To facilitate the fabrication of the second set of semiconductor fins, after the first spacer is removed, the strip formed is the first set of semiconductor fins.
309、使用填充物填充所述硬掩模层被刻蚀的部分，使得被填充后的硬掩模层与未被刻蚀时的硬掩模层形状一样，所述填充物与所述硬掩模层能够被同种预定刻蚀材料刻蚀；309. Filling the etched portion of the hard mask layer with a filler such that the filled hard mask layer has the same shape as the hard mask layer when not etched, the filler and the hard mask The mold layer can be etched by the same predetermined etching material;
由于硬掩模层被刻蚀掉一部分，而凸显出第一组半导体鳍条，而本发明实 施例还需要在所述第一组半导体鳍条上生长第二牺牲物以及第二隔离物，故需要使用填充物填充所述硬掩模层被刻蚀的部分，以方便沉积生长第二牺牲物以及第二隔离物。为了方便对被填充后的硬掩模层进行刻蚀，所以被填充后的硬掩模层与为被刻蚀的硬掩模层形状一样。所述填充物与所述硬掩模层能够被同种预定刻蚀材料刻蚀，则所述填充物与所述硬掩模层的制成材料相同或相近，比如，同为体硅材料，这样，避免了在对所述填充物与所述硬掩模层同时刻蚀时导致波动大而影响刻蚀效果。Since the hard mask layer is etched away, a first set of semiconductor fins are highlighted, and the present invention The embodiment also needs to grow the second sacrificial layer and the second spacer on the first set of semiconductor fins, so that the portion of the hard mask layer to be etched needs to be filled with a filler to facilitate deposition and growth of the second sacrifice. And the second spacer. In order to facilitate etching of the filled hard mask layer, the filled hard mask layer has the same shape as the hard mask layer to be etched. The filler and the hard mask layer can be etched by the same predetermined etching material, and the filler is the same or similar to the material of the hard mask layer, for example, the same silicon material. In this way, it is avoided that the etching is caused when the filler and the hard mask layer are simultaneously etched, and the etching effect is affected.
310、在所述被填充后的硬掩模层的上表面沉积生长预设模板形状的第二牺牲物，所述第二牺牲物为实体且包括X个与所述被填充后的硬掩模层垂直的外表面，所述X大于1；310. Depositing, on an upper surface of the filled hard mask layer, a second sacrificial for growing a predetermined template shape, the second sacrificial being solid and including X and the filled hard mask a vertical outer surface of the layer, the X being greater than 1;
可选的，所述第二牺牲物可以为规则形状的实体，例如长方体、正方体、三角体等；在本发明实施例中，所述第二牺牲物包括X个与所述硬掩模层垂直的外表面，所述X大于1，由于所述第二牺牲物的与所述硬掩模层垂直的外表面是用于生成第二隔离物，并以所述第二隔离物为掩模各向异性刻蚀所述硬掩模层而得到半导体鳍条的，即在本发明实施例中，能够实现生产多组半导体鳍条。优选的，本发明实施例中第二牺牲物可以为与所述第一牺牲物同样形状的实体，即所述X可以与所述M相等。Optionally, the second victim may be a regular shaped entity, such as a rectangular parallelepiped, a cube, a triangle, or the like. In the embodiment of the present invention, the second victim includes X perpendicular to the hard mask layer. The outer surface, the X is greater than 1, since the outer surface of the second sacrificial perpendicular to the hard mask layer is for generating a second spacer, and the second spacer is used as a mask By etching the hard mask layer anisotropically to obtain a semiconductor fin, that is, in the embodiment of the present invention, it is possible to produce a plurality of sets of semiconductor fins. Preferably, in the embodiment of the present invention, the second sacrificial body may be an entity having the same shape as the first sacrificial object, that is, the X may be equal to the M.
311、在所述X个与所述被填充后的硬掩模层垂直的外表面中按照预定规则选择Y个外表面用于为第二隔离物的生长提供模板，所述Y大于1且小于等于X；第二牺牲物的所述Y个外表面分别与所述第一组半导体鳍条中各个半导体鳍条形成有预设交叉角度；311. Select Y outer surfaces according to a predetermined rule in the X outer surfaces perpendicular to the filled hard mask layer for providing a template for growth of the second spacer, wherein Y is greater than 1 and less than Equal to X; the Y outer surfaces of the second sacrificial are respectively formed with a predetermined intersection angle with each of the semiconductor fins of the first group of semiconductor fins;
由于所述第二牺牲物会存在多个与所述硬掩模层垂直的外表面，比如若所述第二牺牲物为长方体，则可能存在四个与所述硬掩模层垂直的外表面；为了简化工艺制作，需要从所述第二牺牲物的X个外表面中选择Y个外表面，用于为第二隔离物的生长提供模板。为了使得后续步骤的刻蚀更为方便，需要从所述X个外表面中根据预设规则选择所述Y个外表面，所述预设规则包括优选所述第二牺牲物中互相平行且长度最长的与所述硬掩模层垂直的外表面，比如从长方体中选择所述长方体的高与长所形成的两个平行的外表面。优选的，所述Y与所述N可以相等，且从所述第二牺牲物中所选择的Y个外表面与所 述从第一牺牲物中所选择的N个外表面可以均为平行且长度最长的外表面。Since the second sacrificial layer may have a plurality of outer surfaces perpendicular to the hard mask layer, such as if the second sacrificial body is a rectangular parallelepiped, there may be four outer surfaces perpendicular to the hard mask layer. In order to simplify the process, it is necessary to select Y outer surfaces from the X outer surfaces of the second sacrificial for providing a template for the growth of the second spacer. In order to facilitate the etching of the subsequent steps, the Y outer surfaces need to be selected from the X outer surfaces according to a preset rule, and the preset rule includes that the second sacrificial bodies are preferably parallel to each other and length. The longest outer surface perpendicular to the hard mask layer, such as two parallel outer surfaces formed by selecting the height and length of the cuboid from the cuboid. Preferably, the Y and the N may be equal, and the Y outer surfaces selected from the second sacrifice are The N outer surfaces selected from the first sacrificial body may all be parallel and the longest outer surface.
由于所述第二牺牲物是用于给生成第二隔离物提供模板的，而所述第二隔离物是用于作为掩模对所述被填充后的硬掩模层进行刻蚀而得到第二组半导体鳍条的，只有所述第二组半导体鳍条所述所述第一组半导体鳍条存在相交，才能够得到纳米线，所以第二牺牲物的所述Y个外表面分别与所述第一组半导体鳍条中各个半导体鳍条形成有预设交叉角度，等同于所述第二隔离物与所述第一组半导体鳍条形成的角度，而所述第二隔离物与所述第一组半导体鳍条所形成的角度则决定了最后生成纳米线的横截面形状。比如，若所述第二牺牲物的所述Y个外表面分别与所述第一组半导体鳍条中各个半导体鳍条所形成的角度为90度，则最后所得到的纳米线的横截面则为长方形；否则，则最后得到的纳米线的横截面则为平行四边形。The second spacer is used to provide a template for forming a second spacer, and the second spacer is used for etching the filled hard mask layer as a mask. In the two sets of semiconductor fins, only the second set of semiconductor fins intersect with the first set of semiconductor fins to obtain nanowires, so the Y outer surfaces of the second sacrificial body are respectively Each of the semiconductor fins of the first set of semiconductor fins is formed with a predetermined crossing angle, which is equivalent to an angle formed by the second spacer and the first set of semiconductor fins, and the second spacer is The angle formed by the first set of semiconductor fins determines the cross-sectional shape of the resulting nanowire. For example, if the Y outer surfaces of the second sacrificial are respectively formed at an angle of 90 degrees with each of the semiconductor fins of the first group of semiconductor fins, the cross section of the finally obtained nanowire is It is a rectangle; otherwise, the resulting nanowire has a parallelogram in cross section.
312、沿第二牺牲物的所述Y个外表面沉积生长预设厚度的第二隔离物，所述预设厚度的第二隔离物下方仍有所述被填充后的硬掩模层；312. depositing a second spacer of a predetermined thickness along the Y outer surfaces of the second sacrificial layer, and the filled hard mask layer is still under the second spacer of the predetermined thickness;
第二隔离物的厚度为根据实际应用需求所设定的厚度，因为在刻蚀硬掩模层时需要以所述第二隔离物为掩模进行刻蚀，从而生成第二组半导体鳍条，所以第二隔离物的厚度则限定着所生成的第体半导体鳍条的宽度，也是最终生成纳米线的尺寸。若所述预设厚度的第一隔离物的厚度与所述预设厚度的第二隔离物的厚度相等，则最后形成的纳米线的横截面为等边四边形。由于所述预设厚度的第二隔离物是用于为刻蚀所述被填充后的硬掩模层提供掩模的，所以所述预设厚度的第二隔离物位于所述被填充后的硬掩模层上方。The thickness of the second spacer is a thickness set according to actual application requirements, because etching needs to be performed by using the second spacer as a mask when etching the hard mask layer, thereby generating a second group of semiconductor fins. Therefore, the thickness of the second spacer defines the width of the generated first semiconductor fin, which is also the size of the final nanowire. If the thickness of the first spacer of the predetermined thickness is equal to the thickness of the second spacer of the predetermined thickness, the cross section of the finally formed nanowire is an equilateral quadrilateral. Since the second spacer of the predetermined thickness is used to provide a mask for etching the filled hard mask layer, the second spacer of the predetermined thickness is located after the filling Above the hard mask layer.
313、移除所述第二牺牲物；313. Remove the second sacrifice;
当第二隔离物生成时，则需要以所述第二隔离物为掩模对被填充后的硬掩模层进行刻蚀，此时，需要将第二牺牲物移除，以方便对所述被填充后的硬掩模层进行刻蚀。When the second spacer is formed, the padded hard mask layer needs to be etched by using the second spacer as a mask. At this time, the second sacrifice needs to be removed to facilitate the The filled hard mask layer is etched.
314、以所述预设厚度的第二隔离物为掩模各向异性刻蚀所述被填充后的硬掩模层；314: Anisotropically etching the filled hard mask layer by using the second spacer of the predetermined thickness as a mask;
需要说明的是，在对硬掩模层进行刻蚀时，刻蚀的深度决定了半导体鳍条的高度，也决定了最后生成纳米线的高度，所以刻蚀所述硬掩模层的深度需根据实际需求来决定，此处不做限定。优选的，所述第二组半导体鳍条的高度与 所述第一组半导体鳍条的高度相等。It should be noted that, when etching the hard mask layer, the depth of the etching determines the height of the semiconductor fins, and also determines the height of the final nanowires, so the depth of the hard mask layer needs to be etched. According to actual needs, there is no limit here. Preferably, the height of the second set of semiconductor fins is The first set of semiconductor fins are of equal height.
315、移除所述预设厚度的第二隔离物，得到第二组半导体鳍条；315, removing the second spacer of the predetermined thickness to obtain a second group of semiconductor fins;
移除所述第二隔离物之后，所得到的第二组半导体鳍条中，所述半导体鳍条还包括填充物以及硬掩模层。After removing the second spacer, in the obtained second group of semiconductor fins, the semiconductor fin further includes a filler and a hard mask layer.
316、移除所述填充物，得到硬掩模纳米线；316, removing the filler to obtain a hard mask nanowire;
移除所述第二组半导体鳍条中的填充物之后，剩下的硬掩模层部分所呈现的凸起则为硬掩模纳米线。需要说明的是，最后所得到的硬掩模纳米线的数量与之前所选择的第一牺牲物的N个外表面以及第二牺牲物的Y个外表面有关，具体的，最后得到的硬掩模纳米线的数量为所述N与所述Y的乘积。比如N与Y均为2，则得到的第一组半导体鳍条为一条，第二组半导体鳍条也是一条，最后得到的硬掩模纳米线为四条。After removing the filler in the second set of semiconductor fins, the remaining hard mask layer portions are rendered as hard mask nanowires. It should be noted that the number of the last obtained hard mask nanowires is related to the N outer surfaces of the first selected first sacrificial and the Y outer surfaces of the second sacrificial. Specifically, the final hard mask is obtained. The number of mold nanowires is the product of the N and the Y. For example, if N and Y are both 2, the first set of semiconductor fins is one, the second set of semiconductor fins is also one, and finally four hard mask nanowires are obtained.
317、以所述硬掩模纳米线为掩模刻蚀所述半导体衬底；317: etching the semiconductor substrate by using the hard mask nanowire as a mask;
得到了所述硬掩模纳米线后，则通过以所述硬掩模为纳米线刻蚀所述半导体衬底，则能够生成半导体纳米线。以硬掩模纳米线23为掩模刻蚀所述半导体衬底22生成的半导体纳米线24参照图6所示。After the hard mask nanowires are obtained, the semiconductor nanowires can be formed by etching the semiconductor substrate with the hard mask as a nanowire. The semiconductor nanowires 24 formed by etching the semiconductor substrate 22 with the hard mask nanowires 23 as a mask are shown in FIG.
318、移除所述硬掩模纳米线，得到半导体纳米线；318. Removing the hard mask nanowires to obtain semiconductor nanowires.
在通过以所述硬掩模纳米线为掩模刻蚀所述半导体衬底后，则需移除所述硬掩模纳米线，则得到半导体纳米线。After etching the semiconductor substrate by using the hard mask nanowire as a mask, the hard mask nanowires need to be removed to obtain semiconductor nanowires.
可选的，所述的硬掩模层的制成材料可以包括氮化硅、二氧化硅、氮化钛、氮化钽或者其他耐刻蚀材料中的至少一种；所述硬掩模层的制成材料与所述第一隔离物以及所述第二隔离物的制成材料均不同。Optionally, the hard mask layer can be made of at least one of silicon nitride, silicon dioxide, titanium nitride, tantalum nitride or other etch-resistant materials; the hard mask layer The finished material is different from the first spacer and the second spacer.
本发明实施例中，首先在所述半导体衬底上沉积生长硬掩模层，再使得后续的刻蚀、填充、移除等操作在所述硬掩模层上进行，在得到硬掩模纳米线后，再以所述硬掩模纳米线为掩模对所述半导体衬底刻蚀，以得到半导体纳米线。这样，所述硬掩模可以防止所述半导体衬底在经过多次刻蚀、移除等工艺操作后生成半导体纳米线的部分被破坏，从而提高了半导体纳米线的完整性。In the embodiment of the present invention, first, a growth hard mask layer is deposited on the semiconductor substrate, and subsequent etching, filling, and removing operations are performed on the hard mask layer to obtain a hard mask nanometer. After the line, the semiconductor substrate is etched using the hard mask nanowire as a mask to obtain a semiconductor nanowire. In this way, the hard mask can prevent the semiconductor substrate from being damaged after the process of performing multiple etching, removal, etc., to generate semiconductor nanowires, thereby improving the integrity of the semiconductor nanowire.
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域技术人员在没有作出创造性劳 动前提下所获得的所有其他实施例，都属于本发明保护的范围。The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, but not all embodiments. Based on the embodiments in the present invention, those skilled in the art are not creative All other embodiments obtained under the premise of the invention are within the scope of the invention.
以上所述，以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。 The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to be limiting; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art will understand that The technical solutions described in the embodiments are modified, or the equivalents of the technical features are replaced by the equivalents of the technical solutions of the embodiments of the present invention.

Claims (14)

  1. 一种制作纳米线的方法，其特征在于，包括：A method of fabricating nanowires, comprising:
    设置衬底；Setting the substrate;
    在所述衬底上表面沉积生长预设模板形状的第一牺牲物，所述第一牺牲物为实体且包括M个与所述衬底垂直的外表面，所述M大于1；Depositing a first sacrificial shape of a predetermined template shape on the surface of the substrate, the first sacrificial body being a solid and comprising M outer surfaces perpendicular to the substrate, the M being greater than 1;
    在所述M个与所述衬底垂直的外表面中按照预定规则选择N个外表面用于为第一隔离物的生长提供模板，所述N大于1且小于等于M；Selecting N outer surfaces according to a predetermined rule in the outer surfaces perpendicular to the substrate for providing a template for growth of the first spacer, the N being greater than 1 and less than or equal to M;
    沿第一牺牲物的所述N个外表面沉积生长预设厚度的第一隔离物，所述预设厚度的第一隔离物的下方仍有所述衬底；Depositing a first spacer of a predetermined thickness along the N outer surfaces of the first sacrificial, wherein the substrate is still under the first spacer of the predetermined thickness;
    移除所述第一牺牲物；Removing the first victim;
    以所述预设厚度的第一隔离物为掩模各向异性刻蚀所述衬底；Anisotropically etching the substrate by using the first spacer of the predetermined thickness as a mask;
    移除所述预设厚度的第一隔离物，得到第一组半导体鳍条；Removing the first spacer of the predetermined thickness to obtain a first set of semiconductor fins;
    使用填充物填充所述衬底被刻蚀的部分，使得被填充后的衬底与未被刻蚀时的衬底形状一样，所述填充物与所述衬底能够被同种预定刻蚀材料刻蚀；Filling the etched portion of the substrate with a filler such that the filled substrate is the same shape as the substrate when not etched, the filler and the substrate being capable of being of the same predetermined etch material Etching
    在所述被填充后的衬底的上表面沉积生长预设模板形状的第二牺牲物，所述第二牺牲物为实体且包括X个与所述被填充后的衬底垂直的外表面，所述X大于1；Depositing a second sacrificial growth template shape on the upper surface of the filled substrate, the second sacrificial being solid and including X outer surfaces perpendicular to the filled substrate, The X is greater than 1;
    在所述X个与所述被填充后的衬底垂直的外表面中按照预定规则选择Y个外表面用于为第二隔离物的生长提供模板，所述Y大于1且小于等于X；第二牺牲物的所述Y个外表面分别与所述第一组半导体鳍条中各个半导体鳍条形成有预设交叉角度；Selecting Y outer surfaces according to a predetermined rule in the X outer surfaces perpendicular to the filled substrate for providing a template for growth of the second spacer, the Y being greater than 1 and less than or equal to X; The Y outer surfaces of the two sacrificial bodies respectively form a predetermined intersection angle with each of the semiconductor fins of the first group of semiconductor fins;
    沿第二牺牲物的所述Y个外表面沉积生长预设厚度的第二隔离物，所述预设厚度的第二隔离物的下方仍有所述被填充后的衬底；Depositing a second spacer of a predetermined thickness along the Y outer surfaces of the second sacrificial, wherein the filled substrate is still under the second spacer of the predetermined thickness;
    移除所述第二牺牲物；Removing the second victim;
    以所述预设厚度的第二隔离物为掩模各向异性刻蚀所述被填充后的衬底；Anisotropically etching the filled substrate by using the second spacer of the predetermined thickness as a mask;
    移除所述预设厚度的第二隔离物，得到第二组半导体鳍条；Removing the second spacer of the predetermined thickness to obtain a second set of semiconductor fins;
    移除所述填充物，得到纳米线。The filler is removed to obtain nanowires.
  2. 根据权利要求1所述的方法，其特征在于，所述衬底包括体硅衬底、SOI衬底、锗硅衬底、三五族材料衬底、或者多种半导体材料薄膜堆叠衬底其 中任意一种半导体衬底。The method according to claim 1, wherein said substrate comprises a bulk silicon substrate, an SOI substrate, a silicon germanium substrate, a tri-five material substrate, or a plurality of semiconductor material thin film stacked substrates. Any of the semiconductor substrates.
  3. 根据权利要求1或2所述的方法，其特征在于，所述在所述衬底上表面沉积生长预设模板形状的第一牺牲物包括：The method according to claim 1 or 2, wherein the depositing the first sacrificial shape of the predetermined template shape on the upper surface of the substrate comprises:
    在所述衬底上表面沉积生长第一牺牲物薄膜，利用光刻和刻蚀技术将所述第一牺牲物薄膜定义成预设模板形状的第一牺牲物。A first sacrificial film is deposited on the surface of the substrate, and the first sacrificial film is defined as a first sacrificial shape of a predetermined template shape by photolithography and etching techniques.
  4. 根据权利要求1至3其中任意一项所述的方法，其特征在于，所述在被填充后的衬底上表面沉积生长预设模板形状的第二牺牲物包括：The method according to any one of claims 1 to 3, wherein the depositing the second sacrificial shape of the predetermined template shape on the surface of the filled substrate comprises:
    在所述被填充后的衬底上表面沉积生长第二牺牲物薄膜，利用光刻和刻蚀技术将所述第二牺牲物薄膜定义成预设模板形状的第二牺牲物。A second sacrificial film is deposited on the surface of the filled substrate, and the second sacrificial film is defined by a photolithography and etching technique as a second sacrificial of a predetermined template shape.
  5. 根据权利要求1至4其中任意一项所述的方法，其特征在于，所述沿第一牺牲物的所述N个外表面沉积生长预设厚度的第一隔离物包括：The method according to any one of claims 1 to 4, wherein depositing a first spacer of a predetermined thickness along the N outer surfaces of the first sacrificial comprises:
    沿第一牺牲物的所述N个外表面沉积生长预设厚度的第一隔离物薄膜，所述第一隔离物薄膜的厚度用于限定所述第一组半导体鳍条的宽度，以使得所述第一组半导体鳍条的宽度与所述第一隔离物薄膜的厚度相等；Depositing a first spacer film of a predetermined thickness along the N outer surfaces of the first sacrificial, the thickness of the first spacer film being used to define a width of the first set of semiconductor fins such that The width of the first set of semiconductor fins is equal to the thickness of the first spacer film;
    利用各向异性刻蚀技术将所述第一隔离物薄膜刻蚀形成预设厚度的第一隔离物。The first spacer film is etched by an anisotropic etching technique to form a first spacer of a predetermined thickness.
  6. 根据权利要求1至5其中任意一项所述的方法，其特征在于，所述沿第二牺牲物的所述Y个外表面沉积生长预设厚度的第二隔离物包括：The method according to any one of claims 1 to 5, wherein depositing a second spacer of a predetermined thickness along the Y outer surfaces of the second sacrificial comprises:
    沿第二牺牲物的所述Y个外表面沉积生长预设厚度的第二隔离物薄膜，所述第二隔离物薄膜的厚度用于限定所述第二组半导体鳍条的宽度，以使得所述第二组半导体鳍条的宽度与所述第一隔离物薄膜的厚度相等；Depositing a second spacer film of a predetermined thickness along the Y outer surfaces of the second sacrificial, the thickness of the second spacer film being used to define a width of the second set of semiconductor fins such that The width of the second set of semiconductor fins is equal to the thickness of the first spacer film;
    利用各向异性刻蚀技术将所述第二隔离物薄膜刻蚀形成预设厚度的第二隔离物。The second spacer film is etched by an anisotropic etching technique to form a second spacer of a predetermined thickness.
  7. 根据权利要求1至6其中任意一项所述的方法，其特征在于，在所述使用填充物填充所述衬底被刻蚀的部分之后，在所述在被填充后的衬底上表面沉积生长预设模板形状的第二牺牲物之前，所述方法还包括：The method according to any one of claims 1 to 6, wherein after depositing a portion of the substrate to be etched using a filler, depositing on the surface of the filled substrate Before growing the second sacrifice of the preset template shape, the method further includes:
    将所述被填充后的衬底抛光，以暴露出所述第一组半导体鳍条的顶部。The filled substrate is polished to expose the top of the first set of semiconductor fins.
  8. 根据权利要求1至7其中任意一项所述的方法，其特征在于，A method according to any one of claims 1 to 7, wherein
    所述第一可牺牲物的制成材料包括多晶硅、α硅以及光刻胶其中任意一 种。The first sacrificial material is made of polysilicon, alpha silicon, and photoresist. Kind.
  9. 根据权利要求1至8其中任意一项所述的方法，其特征在于，所述第二可牺牲物的制成材料包括多晶硅、α硅以及光刻胶其中任意一种。The method according to any one of claims 1 to 8, wherein the second sacrificial material is made of any one of polysilicon, alpha silicon, and photoresist.
  10. 根据权利要求1至9其中任意一项所述的方法，其特征在于，所述第一隔离物的制成材料包括氮化硅、二氧化硅、氮化钛、氮化钽或者其他耐刻蚀材料中的至少一种。The method according to any one of claims 1 to 9, wherein the first spacer is made of silicon nitride, silicon dioxide, titanium nitride, tantalum nitride or other etching resistant material. At least one of the materials.
  11. 根据权利要求1至10其中任意一项所述的方法，其特征在于，所述第二隔离物的制成材料包括氮化硅、二氧化硅、氮化钛、氮化钽或者其他耐刻蚀材料中的至少一种。The method according to any one of claims 1 to 10, wherein the second spacer is made of silicon nitride, silicon dioxide, titanium nitride, tantalum nitride or other etching resistant material. At least one of the materials.
  12. 根据权利要求1至11其中任意一项所述的方法，其特征在于，所述填充物包括体硅、SOI、锗硅、三五族材料、或者多种半导体材料薄膜堆叠材料其中任意一种。The method according to any one of claims 1 to 11, wherein the filler comprises any one of bulk silicon, SOI, silicon germanium, a tri-five material, or a plurality of semiconductor material thin film stack materials.
  13. 一种制作纳米线的方法，其特征在于，包括：A method of fabricating nanowires, comprising:
    设置半导体衬底；Setting a semiconductor substrate;
    在所述半导体衬底上表面沉积生长硬掩模层；Depositing a growth hard mask layer on the surface of the semiconductor substrate;
    在所述硬掩模层上表面沉积生长预设模板形状的第一牺牲物，所述第一牺牲物为实体且包括M个与所述衬底垂直的外表面，所述M大于1；Depositing a first sacrificial shape of a predetermined template shape on the surface of the hard mask layer, the first sacrificial body being solid and including M outer surfaces perpendicular to the substrate, the M being greater than 1;
    在所述M个与所述硬掩模层垂直的外表面中按照预定规则选择N个外表面用于为第一隔离物的生长提供模板，所述N大于1且小于等于M；Selecting N outer surfaces according to a predetermined rule in the outer surfaces perpendicular to the hard mask layer for providing a template for growth of the first spacer, the N being greater than 1 and less than or equal to M;
    沿第一牺牲物的所述N个外表面沉积生长预设厚度的第一隔离物，所述预设厚度的第一隔离物的下方仍有所述半导体衬底；Depositing a first spacer of a predetermined thickness along the N outer surfaces of the first sacrificial, the semiconductor substrate remaining under the first spacer of the predetermined thickness;
    移除所述第一牺牲物；Removing the first victim;
    以所述预设厚度的第一隔离物为掩模各向异性刻蚀所述硬掩模层；Anisotropically etching the hard mask layer by using the first spacer of the predetermined thickness as a mask;
    移除所述预设厚度的第一隔离物，得到第一组半导体鳍条；Removing the first spacer of the predetermined thickness to obtain a first set of semiconductor fins;
    使用填充物填充所述硬掩模层被刻蚀的部分，使得被填充后的硬掩模层与未被刻蚀时的硬掩模层形状一样，所述填充物与所述硬掩模层能够被预定刻蚀材料刻蚀；Filling the etched portion of the hard mask layer with a filler such that the filled hard mask layer has the same shape as the hard mask layer when not etched, the filler and the hard mask layer Can be etched by a predetermined etching material;
    在所述被填充后的硬掩模层的上表面沉积生长预设模板形状的第二牺牲物，所述第二牺牲物为实体且包括X个与所述被填充后的硬掩模层垂直的外 表面，所述X大于1；Depositing a second sacrificial of a predetermined template shape on the upper surface of the filled hard mask layer, the second sacrificial being solid and including X perpendicular to the filled hard mask layer Outside Surface, said X is greater than 1;
    在所述X个与所述被填充后的硬掩模层垂直的外表面中按照预定规则选择Y个外表面用于为第二隔离物的生长提供模板，所述Y大于1且小于等于X；第二牺牲物的所述Y个外表面分别与所述第一组半导体鳍条中各个半导体鳍条形成有预设交叉角度；Y outer surfaces are selected in accordance with a predetermined rule in the outer surfaces perpendicular to the filled hard mask layer for providing a template for growth of the second spacer, the Y being greater than 1 and less than or equal to X The Y outer surfaces of the second sacrificial body respectively form a predetermined intersection angle with each of the semiconductor fins of the first group of semiconductor fins;
    沿第二牺牲物的所述Y个外表面沉积生长预设厚度的第二隔离物，所述预设厚度的第二隔离物的下方仍有所述被填充后的衬底；Depositing a second spacer of a predetermined thickness along the Y outer surfaces of the second sacrificial, wherein the filled substrate is still under the second spacer of the predetermined thickness;
    移除所述第二牺牲物；Removing the second victim;
    以所述预设厚度的第二隔离物为掩模各向异性刻蚀所述被填充后的硬掩模层；Anisotropically etching the filled hard mask layer by using the second spacer of the predetermined thickness as a mask;
    移除所述预设厚度的第二隔离物，得到第二组半导体鳍条；Removing the second spacer of the predetermined thickness to obtain a second set of semiconductor fins;
    移除所述填充物，得到硬掩模纳米线；Removing the filler to obtain a hard mask nanowire;
    以所述硬掩模纳米线为掩模刻蚀所述半导体衬底；Etching the semiconductor substrate with the hard mask nanowire as a mask;
    移除所述硬掩模纳米线，得到半导体纳米线。The hard mask nanowires are removed to obtain semiconductor nanowires.
  14. 根据权利要求13所述的方法，其特征在于，The method of claim 13 wherein:
    所述硬掩模层的制成材料包括氮化硅、二氧化硅、氮化钛、氮化钽或者其他耐刻蚀材料中的至少一种；The material of the hard mask layer is at least one of silicon nitride, silicon dioxide, titanium nitride, tantalum nitride or other etching resistant materials;
    所述硬掩模层的制成材料与所述第一隔离物以及所述第二隔离物的制成材料均不同。 The material of the hard mask layer is different from that of the first spacer and the second spacer.
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